| Name | Base Address | 31 | 30 | 29 | 28 | 27 | 26 | 25 | 24 | 23 | 22 | 21 | 20 | 19 | 18 | 17 | 16 | 15 | 14 | 13 | 12 | 11 | 10 | 9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| secenc_rom | 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| bootreg | 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_intram0_boot | 0x00000000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| iol_config_interconnect | 0x00080000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| iol_ram_ctrl | 0x00080000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| iol_config | 0x00081000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| iol_timer | 0x00081100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| iol_spi | 0x00081100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . |
| iol_hsc | 0x00081c00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| iol_wdg_sys | 0x00082000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| iol_arm_tim0 | 0x00082080 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| iol_arm_tim1 | 0x00082100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| cada_config_interconnect | 0x00100000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ada_config_interconnect | 0x00100000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ada_ram_ctrl | 0x00100000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| cada_ram_ctrl | 0x00100000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| cada_config | 0x00101000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| ada_config | 0x00101000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| ada_timer | 0x00101100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| ada_hsc | 0x00101c00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| ada_wdg_sys | 0x00102000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| ada_arm_tim0 | 0x00102080 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| ada_arm_tim1 | 0x00102100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| cada_ise_ctrl | 0x00110000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| cada_internal_ise | 0x00110000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| cada_internal_ise_dma | 0x00110000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| cada_timer | 0x00110800 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| cada_hsc | 0x00110c00 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| cada_wdg_sys | 0x00111000 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| cada_arm_tim0 | 0x00111080 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| cada_arm_tim1 | 0x00111100 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| cvm | 0x02000000 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cvm_intram0 | 0x02000000 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cvm_cfg | 0x03f00000 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cvm_ram_ctrl | 0x03f00000 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com | 0x04000000 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_intram0 | 0x06000000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_intram1 | 0x06100000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_intram2 | 0x06200000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_a32_peri | 0x06400000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_i2c0 | 0x06400000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| com_i2c1 | 0x06400040 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . |
| com_spi0 | 0x06400080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . |
| com_spi1 | 0x064000c0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . |
| com_uart0 | 0x06400100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . |
| com_uart1 | 0x06400140 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . |
| com_gpio | 0x06400180 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . |
| com_pio | 0x06400200 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| com_blink | 0x06400300 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . |
| com_blink_mixled | 0x06400340 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| com_gxc_mixled0 | 0x06400360 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| com_gxc_mixled1 | 0x06400380 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . |
| com_wdg | 0x064003a0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | . | . | . | . | . |
| com_hsgmii0 | 0x06400400 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_hsgmii1 | 0x06400500 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| com_xspi | 0x06400600 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . |
| com_sync_timer | 0x06400800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . |
| com_sync_timer_global | 0x06400c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| com_hsc | 0x06401000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . |
| com_can_fd | 0x06420000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| crypt | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_crypt | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ise | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| com_ise | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| ise_dma | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| com_ise_dma | 0x06430000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| mtgy | 0x06432000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mtgy | 0x06432000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx | 0x06600000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_itcm_start | 0x06600000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_dtcm_start | 0x06680000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_config_interconnect | 0x06700000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_ram_ctrl | 0x06700000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_config | 0x06701000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_cda_rx_ise_ctrl | 0x06710000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_ise | 0x06710000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_ise_dma | 0x06710000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| com_cda_rx_timer | 0x06710800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_cda_rx_hsc | 0x06710c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| com_cda_rx_wdg_sys | 0x06711000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| com_cda_rx_arm_tim0 | 0x06711080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| com_cda_rx_arm_tim1 | 0x06711100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| com_cda_tx | 0x06800000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_itcm_start | 0x06800000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_dtcm_start | 0x06880000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_config_interconnect | 0x06900000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_ram_ctrl | 0x06900000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_config | 0x06901000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_cda_tx_ise_ctrl | 0x06910000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_ise | 0x06910000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_ise_dma | 0x06910000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| com_cda_tx_timer | 0x06910800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_cda_tx_hsc | 0x06910c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| com_cda_tx_wdg_sys | 0x06911000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| com_cda_tx_arm_tim0 | 0x06911080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| com_cda_tx_arm_tim1 | 0x06911100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| com_ada | 0x06a00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ada_itcm_start | 0x06a00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ada_dtcm_start | 0x06a80000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ada_config_interconnect | 0x06b00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ada_ram_ctrl | 0x06b00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ada_config | 0x06b01000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_ada_timer | 0x06b01100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| com_ada_hsc | 0x06b01c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| com_ada_wdg_sys | 0x06b02000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| com_ada_arm_tim0 | 0x06b02080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| com_ada_arm_tim1 | 0x06b02100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| com_iol | 0x06c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_iol_itcm_start | 0x06c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_iol_dtcm_start | 0x06c40000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_iol_config_interconnect | 0x06c80000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_iol_ram_ctrl | 0x06c80000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_iol_config | 0x06c81000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_iol_timer | 0x06c81100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| com_iol_spi | 0x06c81100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . |
| com_iol_hsc | 0x06c81c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| com_iol_wdg_sys | 0x06c82000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| com_iol_arm_tim0 | 0x06c82080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| com_iol_arm_tim1 | 0x06c82100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| com_gic | 0x07900000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_periphbase | 0x07980000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_gxcs | 0x07c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec_dram | 0x07c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_grpu_ram | 0x07c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_rate_limiter | 0x07c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_token_bucket_instance0 | 0x07c00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . |
| gxc_token_bucket_instance1 | 0x07c00080 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| gxc_gtpu_ram | 0x07c00800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gmac_regs | 0x07c01000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . |
| gxc_gpec_pram | 0x07c02000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec_regs | 0x07c03000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| intram0_gxc | 0x07c20000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| intram1_gxc | 0x07c40000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| intram2_gxc | 0x07c60000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| intram3_gxc | 0x07c70000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_config0 | 0x07d00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec00 | 0x07d00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec00_dram | 0x07d00000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec00_pram | 0x07d02000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec00_regs | 0x07d03000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec01 | 0x07d04000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec01_dram | 0x07d04000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec01_pram | 0x07d06000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec01_regs | 0x07d07000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec02 | 0x07d08000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec02_dram | 0x07d08000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec02_pram | 0x07d0a000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec02_regs | 0x07d0b000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec03 | 0x07d0c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec03_dram | 0x07d0c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec03_pram | 0x07d0e000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec03_regs | 0x07d0f000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec04 | 0x07d10000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec04_dram | 0x07d10000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec04_pram | 0x07d12000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec04_regs | 0x07d13000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec05 | 0x07d14000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec05_dram | 0x07d14000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec05_pram | 0x07d16000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec05_regs | 0x07d17000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec06 | 0x07d18000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec06_dram | 0x07d18000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec06_pram | 0x07d1a000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec06_regs | 0x07d1b000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec07 | 0x07d1c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec07_dram | 0x07d1c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec07_pram | 0x07d1e000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec07_regs | 0x07d1f000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gmac0 | 0x07d20000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_grpu0_ram | 0x07d20000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gtpu0_ram | 0x07d20800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gmac0_regs | 0x07d21000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . |
| gxc_pfifo0 | 0x07d22200 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| gxc_pfifo1 | 0x07d22300 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . |
| gxc_gpec0_irq | 0x07d22400 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| gxc_gpec10 | 0x07d40000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec10_dram | 0x07d40000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec10_pram | 0x07d42000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec10_regs | 0x07d43000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec11 | 0x07d44000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec11_dram | 0x07d44000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec11_pram | 0x07d46000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec11_regs | 0x07d47000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec12 | 0x07d48000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec12_dram | 0x07d48000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec12_pram | 0x07d4a000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec12_regs | 0x07d4b000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec13 | 0x07d4c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec13_dram | 0x07d4c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec13_pram | 0x07d4e000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec13_regs | 0x07d4f000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec14 | 0x07d50000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec14_dram | 0x07d50000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec14_pram | 0x07d52000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec14_regs | 0x07d53000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec15 | 0x07d54000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec15_dram | 0x07d54000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec15_pram | 0x07d56000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec15_regs | 0x07d57000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec16 | 0x07d58000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec16_dram | 0x07d58000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec16_pram | 0x07d5a000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec16_regs | 0x07d5b000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gpec17 | 0x07d5c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec17_dram | 0x07d5c000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec17_pram | 0x07d5e000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gpec17_regs | 0x07d5f000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_gmac1 | 0x07d60000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_grpu1_ram | 0x07d60000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gtpu1_ram | 0x07d60800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_gmac1_regs | 0x07d61000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . |
| gxc_pfifo2 | 0x07d62200 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| gxc_pfifo3 | 0x07d62300 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . |
| gxc_gpec1_irq | 0x07d62400 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| gxc_sr | 0x07d62500 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| gxc_timer | 0x07d62600 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . |
| gxc_start_stop | 0x07d62780 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | . | . | . | . |
| gxc_buf_man | 0x07d62790 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | . | . | . | . |
| gxc_sys_ram_ctrl | 0x07d63000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_config1 | 0x07d80000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_esc_unit_ram | 0x07d80000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_esc_unit | 0x07d82000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| gxc_pfifo0_config | 0x07d82800 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . |
| gxc_pfifo1_config | 0x07d82880 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| gxc_pfifo2_config | 0x07d82900 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . |
| gxc_pfifo3_config | 0x07d82980 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . |
| gxc_phy_ctrl0 | 0x07d82a00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . |
| gxc_phy_ctrl1 | 0x07d82a40 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . | . |
| gxc_sys_ctrl | 0x07d82b00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | 1 | . | . | . | . | . | . | . | . |
| gxc_trigger_lt | 0x07d82c00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_trigger_lt_global | 0x07d82d00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| gxc_systime | 0x07d82e00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . |
| gxc_systime_lt | 0x07d82f00 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| gxc_distribute_sync | 0x07d82f20 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| gxc_distribute_sync_global | 0x07d82f40 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| gxc_global_buf_man | 0x07d84000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| gxc_rate_limiter0 | 0x07d88000 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| gxc_rate_limiter1 | 0x07d88100 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| gxc_rate_limiter2 | 0x07d88200 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| gxc_rate_limiter3 | 0x07d88300 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . |
| envm | 0x08000000 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sqirom | 0x08000000 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_debug | 0x10000000 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_funnel | 0x100a0000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_replicator | 0x10110000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_etr | 0x10120000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_catu | 0x10130000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_cti | 0x10140000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| stm_apb | 0x10170000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| expansion | 0x11000000 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_cpu_debug | 0x12000000 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_cpu_debug_internal | 0x13000000 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| corperi | 0x1a000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| system_id | 0x1a000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_base_sys_ctrl | 0x1a010000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_firewall_ppu | 0x1a020000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_systop_ppu | 0x1a030000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_dbgtop_ppu | 0x1a040000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt_ctrl | 0x1a200000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt_read | 0x1a210000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt_ctl | 0x1a220000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt0 | 0x1a230000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt1 | 0x1a240000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt2 | 0x1a250000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| refclk_cnt3 | 0x1a260000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_ns_wdog_ctrl | 0x1a300000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_ns_wdog_refresh | 0x1a310000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_secure_wdog_ctrl | 0x1a320000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_secure_wdog_refresh | 0x1a330000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| s32k_cnt_ctrl | 0x1a400000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| s32k_cnt_read | 0x1a410000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| s32k_cnt_ctl | 0x1a420000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| s32k_cnt0 | 0x1a430000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| s32k_cnt1 | 0x1a440000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| interrupt_router | 0x1a500000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| cor_uart0 | 0x1a510000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| cor_uart1 | 0x1a520000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_base | 0x1a800000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_ctrl | 0x1a800000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_sysperi | 0x1a810000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_dbgperi | 0x1a820000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_aonperi | 0x1a830000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_envm | 0x1a840000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_cvm | 0x1a850000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_hostcpu | 0x1a860000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_com | 0x1a870000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_mot | 0x1a880000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_hperi_slv | 0x1a890000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_sms_slv | 0x1a8a0000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_hperi_mst | 0x1a8b0000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_sms_mst | 0x1a8c0000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_evm | 0x1a8d0000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_sys_fw_comp_debug | 0x1a8e0000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_base | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_extsys0_mhu0 | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2com0 | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_receiver_app2mot0 | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_receiver_app2com0 | 0x1b000000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_sender_mot2app0 | 0x1b010000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_sender_com2app0 | 0x1b010000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_com2app0 | 0x1b010000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| extsys0_to_host_mhu0 | 0x1b010000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2com1 | 0x1b020000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_receiver_app2mot1 | 0x1b020000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_receiver_app2com1 | 0x1b020000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_extsys0_mhu1 | 0x1b020000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_sender_mot2app1 | 0x1b030000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_sender_com2app1 | 0x1b030000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_com2app1 | 0x1b030000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| extsys0_to_host_mhu1 | 0x1b030000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2mot0 | 0x1b040000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_receiver_se2mot0 | 0x1b040000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_receiver_se2com0 | 0x1b040000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_extsys1_mhu0 | 0x1b040000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_sender_mot2se0 | 0x1b050000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_sender_com2se0 | 0x1b050000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_mot2app0 | 0x1b050000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| extsys1_to_host_mhu0 | 0x1b050000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2mot1 | 0x1b060000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_receiver_se2mot1 | 0x1b060000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_receiver_se2com1 | 0x1b060000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_extsys1_mhu1 | 0x1b060000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_mhu_sender_mot2se1 | 0x1b070000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| com_mhu_sender_com2se1 | 0x1b070000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_mot2app1 | 0x1b070000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| extsys1_to_host_mhu1 | 0x1b070000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2se0 | 0x1b800000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_secenc_mhu0 | 0x1b800000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_se2app0 | 0x1b810000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_to_host_mhu0 | 0x1b810000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_sender_app2se1 | 0x1b820000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| host_to_secenc_mhu1 | 0x1b820000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_mhu_receiver_se2app1 | 0x1b830000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_to_host_mhu1 | 0x1b830000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| int_apbcom | 0x1b900000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_clustop_ppu | 0x1bc00000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_core_ppu0 | 0x1bc10000 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic | 0x1c000000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic_distributor | 0x1c010000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic_cpu_interface | 0x1c02f000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic_virt_interface_ctrl | 0x1c04f000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic_virt_interface_ctrl_alias | 0x1c050000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_gic_virt_cpu_interface | 0x1c06f000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_stm500_stim | 0x1d000000 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_main_nic_gpv | 0x1e000000 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_ca | 0x2f000000 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_cryptocell | 0x2f000000 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_cryptocell_otp_ctrl | 0x2f004000 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| secenc_ram | 0x30000000 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_ram0 | 0x30000000 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| secenc_ram1 | 0x30060000 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| hperi | 0x40000000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| hperi_sys_cfg | 0x40000000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| global_status | 0x40000000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| envm_cfg | 0x40010000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sqi | 0x40010000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| evm_cfg | 0x40020000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| xspi_evm | 0x40020000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . |
| global_setup | 0x40030000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| global_asic_ctrl | 0x40030000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . |
| global_pad_ctrl | 0x40030400 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . |
| global_ioextender_mux_ctrl | 0x40030800 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . |
| global_ioextender | 0x40030c00 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . |
| crg | 0x40030d00 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| com_setup | 0x40040000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_asic_ctrl | 0x40040000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| com_mmio_ctrl | 0x40040100 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . |
| app_setup | 0x40050000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_asic_ctrl | 0x40050000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| app_mmio_ctrl | 0x40050200 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . |
| mot_setup | 0x40060000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_asic_ctrl | 0x40060000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| mot_mmio_ctrl | 0x40060200 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . |
| secenc_setup | 0x40070000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_asic_ctrl | 0x40070000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| app_peri | 0x40080000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_peri_hostcpu | 0x40080000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_biss0 | 0x40080000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| app_biss1 | 0x40080100 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| app_biss_ctrl0 | 0x40080200 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| app_biss_ctrl1 | 0x40080220 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . |
| app_endat0 | 0x40080240 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . | . |
| app_endat1 | 0x40080280 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . |
| app_endat_ctrl0 | 0x400802c0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . |
| app_endat_ctrl1 | 0x400802d0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | . | . | . | . |
| app_uart0 | 0x40080300 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . |
| app_uart1 | 0x40080340 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . |
| app_i2c0 | 0x40080380 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . |
| app_i2c1 | 0x400803c0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . |
| app_spi0 | 0x40080400 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| app_spi1 | 0x40080440 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . |
| app_sqi0 | 0x40080480 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . |
| app_sqi1 | 0x400804c0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . |
| app_gpio | 0x40080500 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| app_pio | 0x40080600 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . |
| app_blink | 0x40080700 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . | . |
| app_blink_mixled | 0x40080740 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| app_trigger_irq | 0x40080760 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| app_trigger_irq_global | 0x40080780 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . |
| app_sync_timer | 0x40080800 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . |
| app_sync_timer_global | 0x40080c00 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| app_dmac0 | 0x40081000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| dmac_ch0 | 0x40081100 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| app_dmac0_dmac_ch0 | 0x40081100 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| app_dmac0_dmac_ch1 | 0x40081120 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| dmac_ch1 | 0x40081120 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| app_dmac0_dmac_ch2 | 0x40081140 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| dmac_ch2 | 0x40081140 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| app_dmac0_dmac_ch3 | 0x40081160 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| dmac_ch3 | 0x40081160 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| dmac_reg | 0x40081800 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| app_dmac0_dmac_reg | 0x40081800 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| app_dmac1 | 0x40082000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_dmac1_dmac_ch0 | 0x40082100 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| app_dmac1_dmac_ch1 | 0x40082120 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| app_dmac1_dmac_ch2 | 0x40082140 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| app_dmac1_dmac_ch3 | 0x40082160 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| app_dmac1_dmac_reg | 0x40082800 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . |
| app_hsc | 0x40083000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . |
| app_peri_misc | 0x40090000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sdio | 0x40090000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_hsgmii | 0x40092000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| app_gem_gxl | 0x400c0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gem_gxl_conf | 0x400c0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| gem_gxl_ram_ctrl | 0x400c8000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| app_can_fd | 0x400d0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_crypt | 0x400e0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| app_ise | 0x400e0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . |
| app_ise_dma | 0x400e0000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| app_mtgy | 0x400e2000 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot | 0x48000000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_intram0 | 0x48000000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_intram1 | 0x48010000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_intram2 | 0x48020000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_intram3 | 0x48030000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_dbg | 0x48040000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_ctrl_local | 0x48044000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_ram_ctrl | 0x48044000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| peri0 | 0x49000000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_peri0 | 0x49000000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_ctrl | 0x49000000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| singen | 0x49000040 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . |
| sdmf0 | 0x49000100 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| sdmf1 | 0x49000200 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| sdmf2 | 0x49000300 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . |
| mpwm | 0x49000400 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . |
| menc | 0x49000600 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . |
| madc | 0x49000680 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . |
| madc_seq0 | 0x49000700 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . |
| madc_seq1 | 0x49000800 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| madc_seq2 | 0x49000900 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| madc_seq3 | 0x49000a00 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . |
| mot_hsc | 0x49000c00 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| mot_plic | 0x49010000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_peri1 | 0x49100000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_peri | 0x49200000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_hperi | 0x49200000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_peri_base | 0x49200000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_biss0 | 0x49200000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| mot_biss1 | 0x49200100 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . |
| mot_biss_ctrl0 | 0x49200200 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| mot_biss_ctrl1 | 0x49200220 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . |
| mot_endat0 | 0x49200240 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . | . |
| mot_endat1 | 0x49200280 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . | . | . |
| mot_endat_ctrl0 | 0x492002c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 0 | . | . | . | . |
| mot_endat_ctrl1 | 0x492002d0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | 1 | . | . | . | . |
| mot_uart0 | 0x49200300 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . |
| mot_uart1 | 0x49200340 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . |
| mot_i2c0 | 0x49200380 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . |
| mot_i2c1 | 0x492003c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . |
| mot_spi0 | 0x49200400 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| mot_spi1 | 0x49200440 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . |
| mot_sqi0 | 0x49200480 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . |
| mot_sqi1 | 0x492004c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . |
| mot_gpio | 0x49200500 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| mot_pio | 0x49200600 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . |
| mot_blink | 0x49200700 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . | . |
| mot_blink_mixled | 0x49200740 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . |
| mot_trigger_irq | 0x49200760 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 1 | . | . | . | . | . |
| mot_trigger_irq_global | 0x49200780 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | . | . | . | . | . |
| mot_wdg0 | 0x492007a0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 1 | . | . | . | . | . |
| mot_wdg1 | 0x492007c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | . | . | . | . | . |
| mot_timer0 | 0x49200800 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . |
| mot_timer1 | 0x49200880 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . |
| mot_sync_timer | 0x49200c00 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . |
| mot_sync_timer_global | 0x49201000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . |
| mot_irq_router_top_decoder | 0x49210000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cpu0_decoder | 0x49210000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_irq_router_cpu0_decoder | 0x49210000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_irq_router_cpu0_motion_exp_0 | 0x49210000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu0_sync_0 | 0x49210010 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu0_mpwm_0 | 0x49210020 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu0_adc_0 | 0x49210030 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . |
| mot_irq_router_cpu0_adc_1 | 0x49210040 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu0_enc_0 | 0x49210050 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu0_enc_1 | 0x49210060 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu0_com_0 | 0x49210070 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . |
| mot_irq_router_cpu0_com_1 | 0x49210080 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu0_com_2 | 0x49210090 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu0_com_3 | 0x492100a0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu0_peri_0 | 0x492100c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . |
| mot_irq_router_cpu0_peri_1 | 0x492100e0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . |
| mot_irq_router_cpu0_peri_2 | 0x49210100 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| mot_irq_router_cpu0_peri_3 | 0x49210120 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| mot_irq_router_cpu0_shdint_0 | 0x49210140 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . |
| cpu1_decoder | 0x49211000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_irq_router_cpu1_decoder | 0x49211000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| mot_irq_router_cpu1_motion_exp_0 | 0x49211000 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu1_sync_0 | 0x49211010 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu1_mpwm_0 | 0x49211020 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu1_adc_0 | 0x49211030 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . |
| mot_irq_router_cpu1_adc_1 | 0x49211040 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu1_enc_0 | 0x49211050 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu1_enc_1 | 0x49211060 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu1_com_0 | 0x49211070 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . |
| mot_irq_router_cpu1_com_1 | 0x49211080 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . |
| mot_irq_router_cpu1_com_2 | 0x49211090 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . |
| mot_irq_router_cpu1_com_3 | 0x492110a0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | . | . | . | . |
| mot_irq_router_cpu1_peri_0 | 0x492110c0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . |
| mot_irq_router_cpu1_peri_1 | 0x492110e0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . |
| mot_irq_router_cpu1_peri_2 | 0x49211100 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . |
| mot_irq_router_cpu1_peri_3 | 0x49211120 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | . | . | . | . | . |
| mot_irq_router_cpu1_shdint_0 | 0x49211140 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . |
| secenc_peri | 0x50000000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_timer0 | 0x50000000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_timer1 | 0x50001000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2app0 | 0x50003000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| seh_mhu0 | 0x50003000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_app2se0 | 0x50004000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| hse_mhu0 | 0x50004000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2app1 | 0x50005000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| seh_mhu1 | 0x50005000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_app2se1 | 0x50006000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| hse_mhu1 | 0x50006000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2com0 | 0x50010000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sees0_mhu0 | 0x50010000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_com2se0 | 0x50011000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| es0se_mhu0 | 0x50011000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2com1 | 0x50012000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sees0_mhu1 | 0x50012000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_com2se1 | 0x50013000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| es0se_mhu1 | 0x50013000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2mot0 | 0x50014000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sees1_mhu0 | 0x50014000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_mot2se0 | 0x50015000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| es1se_mhu0 | 0x50015000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_sender_se2mot1 | 0x50016000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sees1_mhu1 | 0x50016000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_mhu_receiver_mot2se1 | 0x50017000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| es1se_mhu1 | 0x50017000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_otp0 | 0x50018000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_otp1 | 0x5001a000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_otp_ctrl0 | 0x5001c000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| secenc_otp_ctrl1 | 0x5001d000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| secenc_asic_ctrl_sse | 0x5001e000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_hash | 0x5001f000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| secenc_sys2jtag | 0x50020000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . |
| secenc_sys_ctrl | 0x50080000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_watchdog | 0x50081000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_secenctop_ppu | 0x5008d000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_base_sys_ctrl | 0x5008e000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_soc_watchdog | 0x5008f000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_uart | 0x50090000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_secenc_ram_ctrl | 0x50091000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_ram_ctrl | 0x50091000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_fw_ctrl | 0x50200000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_fw_comp_fc1 | 0x50210000 | 0 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms | 0x60000000 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_tbuf_rx_access | 0x60000000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_rx_ram | 0x60000000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_host_access_rgn | 0x60000000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 |
| sms_tbuf_tx_access | 0x60040000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_tx_ram | 0x60040000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_ac_ram | 0x60080000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_ac_mem | 0x60080000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_cfg_sim_msg_combined | 0x60100000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| dpm_cfg | 0x60138000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| dpm_sys_cfg | 0x60138000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| dpm0 | 0x60138400 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . |
| dpm1 | 0x60138500 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . |
| hif_io_ctrl | 0x60138600 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | . | . | . | . | . | . |
| idpm_tb | 0x60140000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| idpm_sys_tb | 0x60140000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sim_msg_tb_regs | 0x60140000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| idpm_cfg | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| idpm_sms_combined | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_cfg | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_ctrl | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_cfg_decoder | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_hsc | 0x60180000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . |
| sms_host_irq | 0x60180400 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| sms_host_irq_logic | 0x60180400 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| sms_host_tba | 0x60181000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . |
| sms_host_cfg_regs | 0x60182000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| sms_host_irq_router_top_decoder | 0x6018f000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_irq_router_pcie_decoder | 0x6018f000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_irq_router_pcie_int_a_0 | 0x6018f000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| sms_device_cfg_decoder | 0x601a0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_top_decoder | 0x601a0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ada_decoder | 0x601a0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_ada_decoder | 0x601a0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_ada_plic_irq | 0x601a0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| cda_rx_decoder | 0x601a1000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_cda_rx_decoder | 0x601a1000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_cda_rx_plic_irq | 0x601a1000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| cda_tx_decoder | 0x601a2000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_cda_tx_decoder | 0x601a2000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_cda_tx_plic_irq | 0x601a2000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| iol_decoder | 0x601a3000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_iol_decoder | 0x601a3000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_device_irq_router_iol_plic_irq | 0x601a3000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| sms_device_irq_logic | 0x601b0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| sms_device_irq | 0x601b0000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| sms_tbuf_rx | 0x601b0200 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . |
| sms_tbuf_tx | 0x601b0400 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . |
| sms_device_tba | 0x601b0600 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | . | . | . | . | . | . | . | . |
| sms_device_cfg_regs | 0x601b0700 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | . | . | . | . |
| dpm_ram_ctrl | 0x601c1000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| intram0_ram_ctrl | 0x601c2000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| intram1_ram_ctrl | 0x601c3000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . |
| intram2_ram_ctrl | 0x601c4000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_window | 0x60200000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_window_ac | 0x60200000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_window_rx | 0x60210000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_window_tx | 0x60220000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_host_window_hs | 0x60230000 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_com_intram0 | 0x66000000 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_com_intram1 | 0x66100000 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| sms_com_intram2 | 0x66200000 | 0 | 1 | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| msi2irq_decoder | 0x68000000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . |
| msi2irq_0 | 0x68000000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| msi2irq_1 | 0x68000010 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . |
| msi2irq_2 | 0x68000020 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . |
| msi2irq_3 | 0x68000030 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . |
| pcie_dma_table_ram | 0x68010000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_regs_decoder | 0x68020000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_regs | 0x68020000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_sys_ctrl | 0x68020000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| irq2msi_cfg | 0x68030000 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . |
| msi2irq_0_cfg | 0x68030020 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . |
| msi2irq_1_cfg | 0x68030040 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . |
| msi2irq_2_cfg | 0x68030060 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | . | . | . | . | . |
| msi2irq_3_cfg | 0x68030080 | 0 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | . | . | . | . | . |
| pcie_phy_cfg | 0x6f000000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_management | 0x6f800000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_ep_cfg | 0x6f800000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_rp_cfg | 0x6f800000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_local_mgmt | 0x6f900000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_rp_cfg_rw | 0x6fa00000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_axi_cfg | 0x6fc00000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_dma | 0x6fe00000 | 0 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_rp | 0x70000000 | 0 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| pcie_rp_mem | 0x70100000 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| evm | 0x80000000 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ext_xspi | 0x80000000 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_fw_base | 0xa0400000 | 1 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| com_ext_xspi | 0xe0000000 | 1 | 1 | 1 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_cm0_private_peripherals | 0xe0000000 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| secenc_cm0_scs | 0xe000e000 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 1 | 1 | 0 | . | . | . | . | . | . | . | . | . | . | . | . |
| ada_internal_itcm_start | 0xee000000 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| iol_internal_itcm_start | 0xee000000 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cada_internal_itcm_start | 0xee000000 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| ada_internal_dtcm_start | 0xf0000000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| iol_internal_dtcm_start | 0xf0000000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| cada_internal_dtcm_start | 0xf0000000 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . | . |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | secenc_rom_base |
| 1-7ffe | 4-1fff8 | - | reserved |
| 7fff | 1fffc | R | secenc_rom_end |
| secenc_rom_base |
|
|||
| R |
Address : 0x00000000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_rom_base | |||
| secenc_rom_end |
|
|||
| R |
Address : 0x0001fffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_rom_end | |||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_netx22xx_6_mbist_power0 |
| 1 | 4 | R/W | gen_ram_ctrl_netx22xx_6_mbist_power1 |
| 2 | 8 | R/W | gen_ram_ctrl_netx22xx_6_mbist_power2 |
| 3 | c | R/W | gen_ram_ctrl_netx22xx_6_mbist_power3 |
| 4 | 10 | R/W | gen_ram_ctrl_netx22xx_6_mbist_power4 |
| 5 | 14 | R/W | gen_ram_ctrl_netx22xx_6_mbist_power5 |
| 6-1ff | 18-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_netx22xx_6_ecc0 |
| 201-27f | 804-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_netx22xx_6_ecc_status_corr0 |
| 281-2ff | a04-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_netx22xx_6_ecc_status_noncorr0 |
| 301-37f | c04-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_netx22xx_6_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_netx22xx_6_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_netx22xx_6_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_netx22xx_6_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_netx22xx_6_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_netx22xx_6_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x00080000 Address@com_iol_ram_ctrl : 0x06c80000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x00080004 Address@com_iol_ram_ctrl : 0x06c80004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x00080008 Address@com_iol_ram_ctrl : 0x06c80008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x0008000c Address@com_iol_ram_ctrl : 0x06c8000c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x00080010 Address@com_iol_ram_ctrl : 0x06c80010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@iol_ram_ctrl : 0x00080014 Address@com_iol_ram_ctrl : 0x06c80014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_6_ecc0 |
|
|||
| R/W |
0x00000000 |
Address@iol_ram_ctrl : 0x00080800 Address@com_iol_ram_ctrl : 0x06c80800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_6_ecc_status_corr0 |
|
|||
| R |
Address@iol_ram_ctrl : 0x00080a00 Address@com_iol_ram_ctrl : 0x06c80a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_6_ecc_status_noncorr0 |
|
|||
| R |
Address@iol_ram_ctrl : 0x00080c00 Address@com_iol_ram_ctrl : 0x06c80c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_6_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address@iol_ram_ctrl : 0x00080e00 Address@com_iol_ram_ctrl : 0x06c80e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_6_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address@iol_ram_ctrl : 0x00080e40 Address@com_iol_ram_ctrl : 0x06c80e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_6_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address@iol_ram_ctrl : 0x00080e80 Address@com_iol_ram_ctrl : 0x06c80e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_6_irq_mask_rst_reg0 |
|
|||||||||||||||||||||
| R/W |
0x00000000 |
Address@iol_ram_ctrl : 0x00080ec0 Address@com_iol_ram_ctrl : 0x06c80ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||||||||||||||||
| 7 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||
| 6 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||
| gen_ram_ctrl_netx22xx_6_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address@iol_ram_ctrl : 0x00080efc Address@com_iol_ram_ctrl : 0x06c80efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | el2_power_mgmt |
| 1 | 4 | R | el2_power_mgmt_info |
| 2 | 8 | R/W | el2_rst_ctrl |
| 3 | c | R/W | el2_rst_vec |
| 4 | 10 | R/W | el2_nmi_vec |
| 5 | 14 | W | el2_set_softint |
| 6 | 18 | W | el2_reset_softint |
| 7 | 1c | R | el2_softint |
| 8-3f | 20-fc | - | reserved |
| el2_power_mgmt |
|
|||
| R/W |
0x00000004 |
Address@iol_config : 0x00081000 Address@com_iol_config : 0x06c81000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "1" |
halt_req |
|
|
| 1 | 0 |
- |
reserved | |
| 0 | "0" |
run_req |
|
|
| el2_power_mgmt_info |
|
|||
| R |
Address@iol_config : 0x00081004 Address@com_iol_config : 0x06c81004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | wdg_active |
|
||
| 7 | - |
reserved | ||
| 6 | debug_mode_status |
|
||
| 5 | - |
reserved | ||
| 4 | halt_status |
|
||
| 3 | - |
reserved | ||
| 2 | halt_ack |
|
||
| 1 | - |
reserved | ||
| 0 | run_ack |
|
||
| el2_rst_ctrl |
|
|||
| R/W |
0x00000000 |
Address@iol_config : 0x00081008 Address@com_iol_config : 0x06c81008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
cpu_reset_n |
|
|
| el2_rst_vec |
|
|||
| R/W |
0x00000000 |
Address@iol_config : 0x0008100c Address@com_iol_config : 0x06c8100c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
reset_vector |
|
|
| el2_nmi_vec |
|
|||
| R/W |
0x00000000 |
Address@iol_config : 0x00081010 Address@com_iol_config : 0x06c81010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
nmi_vector |
|
|
| el2_set_softint |
|
|||
| W |
0x00000000 |
Address@iol_config : 0x00081014 Address@com_iol_config : 0x06c81014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
thread_0 |
|
|
| el2_reset_softint |
|
|||
| W |
0x00000000 |
Address@iol_config : 0x00081018 Address@com_iol_config : 0x06c81018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
thread_0 |
|
|
| el2_softint |
|
|||
| R |
Address@iol_config : 0x0008101c Address@com_iol_config : 0x06c8101c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | thread_0 |
|
||
| rv_timer_ctrl |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081100 Address@ada_timer : 0x00101100 Address@cada_timer : 0x00110800 Address@com_cda_rx_timer : 0x06710800 Address@com_cda_tx_timer : 0x06910800 Address@com_ada_timer : 0x06b01100 Address@com_iol_timer : 0x06c81100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
active |
|
|
| rv_timer_cfg |
|
|||
| R/W |
0x00010000 |
Address@iol_timer : 0x00081104 Address@ada_timer : 0x00101104 Address@cada_timer : 0x00110804 Address@com_cda_rx_timer : 0x06710804 Address@com_cda_tx_timer : 0x06910804 Address@com_ada_timer : 0x06b01104 Address@com_iol_timer : 0x06c81104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000001" |
step |
|
|
| 15 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
prescale |
|
|
| rv_timer_lower |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081108 Address@ada_timer : 0x00101108 Address@cada_timer : 0x00110808 Address@com_cda_rx_timer : 0x06710808 Address@com_cda_tx_timer : 0x06910808 Address@com_ada_timer : 0x06b01108 Address@com_iol_timer : 0x06c81108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
v |
|
|
| rv_timer_upper |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x0008110c Address@ada_timer : 0x0010110c Address@cada_timer : 0x0011080c Address@com_cda_rx_timer : 0x0671080c Address@com_cda_tx_timer : 0x0691080c Address@com_ada_timer : 0x06b0110c Address@com_iol_timer : 0x06c8110c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
v |
|
|
| rv_timer_intr_test |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081110 Address@ada_timer : 0x00101110 Address@cada_timer : 0x00110810 Address@com_cda_rx_timer : 0x06710810 Address@com_cda_tx_timer : 0x06910810 Address@com_ada_timer : 0x06b01110 Address@com_iol_timer : 0x06c81110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
t |
|
|
| rv_timer_compare_0_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081120 Address@ada_timer : 0x00101120 Address@cada_timer : 0x00110820 Address@com_cda_rx_timer : 0x06710820 Address@com_cda_tx_timer : 0x06910820 Address@com_ada_timer : 0x06b01120 Address@com_iol_timer : 0x06c81120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_0_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081124 Address@ada_timer : 0x00101124 Address@cada_timer : 0x00110824 Address@com_cda_rx_timer : 0x06710824 Address@com_cda_tx_timer : 0x06910824 Address@com_ada_timer : 0x06b01124 Address@com_iol_timer : 0x06c81124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_0_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081128 Address@ada_timer : 0x00101128 Address@cada_timer : 0x00110828 Address@com_cda_rx_timer : 0x06710828 Address@com_cda_tx_timer : 0x06910828 Address@com_ada_timer : 0x06b01128 Address@com_iol_timer : 0x06c81128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_0_state |
|
|||
| R |
Address@iol_timer : 0x0008112c Address@ada_timer : 0x0010112c Address@cada_timer : 0x0011082c Address@com_cda_rx_timer : 0x0671082c Address@com_cda_tx_timer : 0x0691082c Address@com_ada_timer : 0x06b0112c Address@com_iol_timer : 0x06c8112c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_1_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081130 Address@ada_timer : 0x00101130 Address@cada_timer : 0x00110830 Address@com_cda_rx_timer : 0x06710830 Address@com_cda_tx_timer : 0x06910830 Address@com_ada_timer : 0x06b01130 Address@com_iol_timer : 0x06c81130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_1_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081134 Address@ada_timer : 0x00101134 Address@cada_timer : 0x00110834 Address@com_cda_rx_timer : 0x06710834 Address@com_cda_tx_timer : 0x06910834 Address@com_ada_timer : 0x06b01134 Address@com_iol_timer : 0x06c81134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_1_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081138 Address@ada_timer : 0x00101138 Address@cada_timer : 0x00110838 Address@com_cda_rx_timer : 0x06710838 Address@com_cda_tx_timer : 0x06910838 Address@com_ada_timer : 0x06b01138 Address@com_iol_timer : 0x06c81138 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_1_state |
|
|||
| R |
Address@iol_timer : 0x0008113c Address@ada_timer : 0x0010113c Address@cada_timer : 0x0011083c Address@com_cda_rx_timer : 0x0671083c Address@com_cda_tx_timer : 0x0691083c Address@com_ada_timer : 0x06b0113c Address@com_iol_timer : 0x06c8113c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_2_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081140 Address@ada_timer : 0x00101140 Address@cada_timer : 0x00110840 Address@com_cda_rx_timer : 0x06710840 Address@com_cda_tx_timer : 0x06910840 Address@com_ada_timer : 0x06b01140 Address@com_iol_timer : 0x06c81140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_2_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081144 Address@ada_timer : 0x00101144 Address@cada_timer : 0x00110844 Address@com_cda_rx_timer : 0x06710844 Address@com_cda_tx_timer : 0x06910844 Address@com_ada_timer : 0x06b01144 Address@com_iol_timer : 0x06c81144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_2_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081148 Address@ada_timer : 0x00101148 Address@cada_timer : 0x00110848 Address@com_cda_rx_timer : 0x06710848 Address@com_cda_tx_timer : 0x06910848 Address@com_ada_timer : 0x06b01148 Address@com_iol_timer : 0x06c81148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_2_state |
|
|||
| R |
Address@iol_timer : 0x0008114c Address@ada_timer : 0x0010114c Address@cada_timer : 0x0011084c Address@com_cda_rx_timer : 0x0671084c Address@com_cda_tx_timer : 0x0691084c Address@com_ada_timer : 0x06b0114c Address@com_iol_timer : 0x06c8114c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_3_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081150 Address@ada_timer : 0x00101150 Address@cada_timer : 0x00110850 Address@com_cda_rx_timer : 0x06710850 Address@com_cda_tx_timer : 0x06910850 Address@com_ada_timer : 0x06b01150 Address@com_iol_timer : 0x06c81150 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_3_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081154 Address@ada_timer : 0x00101154 Address@cada_timer : 0x00110854 Address@com_cda_rx_timer : 0x06710854 Address@com_cda_tx_timer : 0x06910854 Address@com_ada_timer : 0x06b01154 Address@com_iol_timer : 0x06c81154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_3_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081158 Address@ada_timer : 0x00101158 Address@cada_timer : 0x00110858 Address@com_cda_rx_timer : 0x06710858 Address@com_cda_tx_timer : 0x06910858 Address@com_ada_timer : 0x06b01158 Address@com_iol_timer : 0x06c81158 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_3_state |
|
|||
| R |
Address@iol_timer : 0x0008115c Address@ada_timer : 0x0010115c Address@cada_timer : 0x0011085c Address@com_cda_rx_timer : 0x0671085c Address@com_cda_tx_timer : 0x0691085c Address@com_ada_timer : 0x06b0115c Address@com_iol_timer : 0x06c8115c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_4_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081160 Address@ada_timer : 0x00101160 Address@cada_timer : 0x00110860 Address@com_cda_rx_timer : 0x06710860 Address@com_cda_tx_timer : 0x06910860 Address@com_ada_timer : 0x06b01160 Address@com_iol_timer : 0x06c81160 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_4_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081164 Address@ada_timer : 0x00101164 Address@cada_timer : 0x00110864 Address@com_cda_rx_timer : 0x06710864 Address@com_cda_tx_timer : 0x06910864 Address@com_ada_timer : 0x06b01164 Address@com_iol_timer : 0x06c81164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_4_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081168 Address@ada_timer : 0x00101168 Address@cada_timer : 0x00110868 Address@com_cda_rx_timer : 0x06710868 Address@com_cda_tx_timer : 0x06910868 Address@com_ada_timer : 0x06b01168 Address@com_iol_timer : 0x06c81168 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_4_state |
|
|||
| R |
Address@iol_timer : 0x0008116c Address@ada_timer : 0x0010116c Address@cada_timer : 0x0011086c Address@com_cda_rx_timer : 0x0671086c Address@com_cda_tx_timer : 0x0691086c Address@com_ada_timer : 0x06b0116c Address@com_iol_timer : 0x06c8116c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_5_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081170 Address@ada_timer : 0x00101170 Address@cada_timer : 0x00110870 Address@com_cda_rx_timer : 0x06710870 Address@com_cda_tx_timer : 0x06910870 Address@com_ada_timer : 0x06b01170 Address@com_iol_timer : 0x06c81170 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_5_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081174 Address@ada_timer : 0x00101174 Address@cada_timer : 0x00110874 Address@com_cda_rx_timer : 0x06710874 Address@com_cda_tx_timer : 0x06910874 Address@com_ada_timer : 0x06b01174 Address@com_iol_timer : 0x06c81174 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_5_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081178 Address@ada_timer : 0x00101178 Address@cada_timer : 0x00110878 Address@com_cda_rx_timer : 0x06710878 Address@com_cda_tx_timer : 0x06910878 Address@com_ada_timer : 0x06b01178 Address@com_iol_timer : 0x06c81178 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_5_state |
|
|||
| R |
Address@iol_timer : 0x0008117c Address@ada_timer : 0x0010117c Address@cada_timer : 0x0011087c Address@com_cda_rx_timer : 0x0671087c Address@com_cda_tx_timer : 0x0691087c Address@com_ada_timer : 0x06b0117c Address@com_iol_timer : 0x06c8117c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_6_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081180 Address@ada_timer : 0x00101180 Address@cada_timer : 0x00110880 Address@com_cda_rx_timer : 0x06710880 Address@com_cda_tx_timer : 0x06910880 Address@com_ada_timer : 0x06b01180 Address@com_iol_timer : 0x06c81180 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_6_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081184 Address@ada_timer : 0x00101184 Address@cada_timer : 0x00110884 Address@com_cda_rx_timer : 0x06710884 Address@com_cda_tx_timer : 0x06910884 Address@com_ada_timer : 0x06b01184 Address@com_iol_timer : 0x06c81184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_6_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081188 Address@ada_timer : 0x00101188 Address@cada_timer : 0x00110888 Address@com_cda_rx_timer : 0x06710888 Address@com_cda_tx_timer : 0x06910888 Address@com_ada_timer : 0x06b01188 Address@com_iol_timer : 0x06c81188 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_6_state |
|
|||
| R |
Address@iol_timer : 0x0008118c Address@ada_timer : 0x0010118c Address@cada_timer : 0x0011088c Address@com_cda_rx_timer : 0x0671088c Address@com_cda_tx_timer : 0x0691088c Address@com_ada_timer : 0x06b0118c Address@com_iol_timer : 0x06c8118c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| rv_timer_compare_7_lower |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081190 Address@ada_timer : 0x00101190 Address@cada_timer : 0x00110890 Address@com_cda_rx_timer : 0x06710890 Address@com_cda_tx_timer : 0x06910890 Address@com_ada_timer : 0x06b01190 Address@com_iol_timer : 0x06c81190 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_compare_7_upper |
|
|||
| R/W |
0xffffffff |
Address@iol_timer : 0x00081194 Address@ada_timer : 0x00101194 Address@cada_timer : 0x00110894 Address@com_cda_rx_timer : 0x06710894 Address@com_cda_tx_timer : 0x06910894 Address@com_ada_timer : 0x06b01194 Address@com_iol_timer : 0x06c81194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
v |
|
|
| rv_timer_intr_7_enable |
|
|||
| R/W |
0x00000000 |
Address@iol_timer : 0x00081198 Address@ada_timer : 0x00101198 Address@cada_timer : 0x00110898 Address@com_cda_rx_timer : 0x06710898 Address@com_cda_tx_timer : 0x06910898 Address@com_ada_timer : 0x06b01198 Address@com_iol_timer : 0x06c81198 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ie |
|
|
| rv_timer_intr_7_state |
|
|||
| R |
Address@iol_timer : 0x0008119c Address@ada_timer : 0x0010119c Address@cada_timer : 0x0011089c Address@com_cda_rx_timer : 0x0671089c Address@com_cda_tx_timer : 0x0691089c Address@com_ada_timer : 0x06b0119c Address@com_iol_timer : 0x06c8119c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | is |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | spi_cr0 |
| 1 | 4 | R/W | spi_cr1 |
| 2 | 8 | R/W | spi_dr |
| 3 | c | R | spi_sr |
| 4 | 10 | - | reserved |
| 5 | 14 | R/W | spi_imsc |
| 6 | 18 | R | spi_ris |
| 7 | 1c | R | spi_mis |
| 8 | 20 | R/W | spi_icr |
| 9 | 24 | - | reserved |
| a | 28 | R/W | spi_dmacr |
| b | 2c | R/W | spi_pio_mode |
| c | 30 | R/W | spi_data_register |
| d | 34 | R | spi_status_register |
| e | 38 | R/W | spi_control_register |
| f | 3c | R/W | spi_interrupt_control_register |
| spi_cr0 |
|
||||||||||||||||||
| R/W |
0x80080007 |
Address@iol_spi : 0x00081100 Address@com_spi0 : 0x06400080 Address@com_spi1 : 0x064000c0 Address@com_iol_spi : 0x06c81100 Address@app_spi0 : 0x40080400 Address@app_spi1 : 0x40080440 Address@mot_spi0 : 0x49200400 Address@mot_spi1 : 0x49200440 |
Bits | Reset value | Name | Description | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "1" |
netx100_comp |
|
||||||||||||||||
| 30 - 29 | 0 |
- |
reserved | ||||||||||||||||
| 28 | "0" |
slave_sig_early |
|
||||||||||||||||
| 27 | "0" |
filter_in |
|
||||||||||||||||
| 26 | 0 |
- |
reserved | ||||||||||||||||
| 25 - 24 | "00" |
format |
|
||||||||||||||||
| 23 - 20 | 0 |
- |
reserved | ||||||||||||||||
| 19 - 8 | 0x800 |
sck_muladd |
|
||||||||||||||||
| 7 | "0" |
SPH |
|
||||||||||||||||
| 6 | "0" |
SPO |
|
||||||||||||||||
| 5 - 4 | 0 |
- |
reserved | ||||||||||||||||
| 3 - 0 | "0111" |
datasize |
|
||||||||||||||||
| spi_cr1 |
|
|||||||
| R/W |
0x08080000 |
Address@iol_spi : 0x00081104 Address@com_spi0 : 0x06400084 Address@com_spi1 : 0x064000c4 Address@com_iol_spi : 0x06c81104 Address@app_spi0 : 0x40080404 Address@app_spi1 : 0x40080444 Address@mot_spi0 : 0x49200404 Address@mot_spi1 : 0x49200444 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | |||||
| 28 | "0" |
rx_fifo_clr |
|
|||||
| 27 - 24 | "1000" |
rx_fifo_wm |
|
|||||
| 23 - 21 | 0 |
- |
reserved | |||||
| 20 | "0" |
tx_fifo_clr |
|
|||||
| 19 - 16 | "1000" |
tx_fifo_wm |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 | "0" |
fss_static |
|
|||||
| 10 - 8 | "000" |
fss |
|
|||||
| 7 - 5 | 0 |
- |
reserved | |||||
| 4 | "0" |
pio_mode |
|
|||||
| 3 | "0" |
SOD |
|
|||||
| 2 | "0" |
MS |
|
|||||
| 1 | "0" |
SSE |
|
|||||
| 0 | "0" |
LBM |
|
|||||
| spi_dr |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x00081108 Address@com_spi0 : 0x06400088 Address@com_spi1 : 0x064000c8 Address@com_iol_spi : 0x06c81108 Address@app_spi0 : 0x40080408 Address@app_spi1 : 0x40080448 Address@mot_spi0 : 0x49200408 Address@mot_spi1 : 0x49200448 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
data |
|
|
| spi_sr |
|
|||
| R |
Address@iol_spi : 0x0008110c Address@com_spi0 : 0x0640008c Address@com_spi1 : 0x064000cc Address@com_iol_spi : 0x06c8110c Address@app_spi0 : 0x4008040c Address@app_spi1 : 0x4008044c Address@mot_spi0 : 0x4920040c Address@mot_spi1 : 0x4920044c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | rx_fifo_err_undr |
|
||
| 30 | rx_fifo_err_ovfl |
|
||
| 29 | - |
reserved | ||
| 28 - 24 | rx_fifo_level |
|
||
| 23 | tx_fifo_err_undr |
|
||
| 22 | tx_fifo_err_ovfl |
|
||
| 21 | - |
reserved | ||
| 20 - 16 | tx_fifo_level |
|
||
| 15 - 5 | - |
reserved | ||
| 4 | BSY |
|
||
| 3 | RFF |
|
||
| 2 | RNE |
|
||
| 1 | TNF |
|
||
| 0 | TFE |
|
||
| spi_imsc |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x00081114 Address@com_spi0 : 0x06400094 Address@com_spi1 : 0x064000d4 Address@com_iol_spi : 0x06c81114 Address@app_spi0 : 0x40080414 Address@app_spi1 : 0x40080454 Address@mot_spi0 : 0x49200414 Address@mot_spi1 : 0x49200454 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
txeim |
|
|
| 5 | "0" |
rxfim |
|
|
| 4 | "0" |
rxneim |
|
|
| 3 | "0" |
TXIM |
|
|
| 2 | "0" |
RXIM |
|
|
| 1 | "0" |
RTIM |
|
|
| 0 | "0" |
RORIM |
|
|
| spi_ris |
|
|||||||
| R |
Address@iol_spi : 0x00081118 Address@com_spi0 : 0x06400098 Address@com_spi1 : 0x064000d8 Address@com_iol_spi : 0x06c81118 Address@app_spi0 : 0x40080418 Address@app_spi1 : 0x40080458 Address@mot_spi0 : 0x49200418 Address@mot_spi1 : 0x49200458 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||||||
| 6 | txeris |
|
||||||
| 5 | rxfris |
|
||||||
| 4 | rxneris |
|
||||||
| 3 | TXRIS |
|
||||||
| 2 | RXRIS |
|
||||||
| 1 | RTRIS |
|
||||||
| 0 | RORRIS |
|
||||||
| spi_mis |
|
|||
| R |
Address@iol_spi : 0x0008111c Address@com_spi0 : 0x0640009c Address@com_spi1 : 0x064000dc Address@com_iol_spi : 0x06c8111c Address@app_spi0 : 0x4008041c Address@app_spi1 : 0x4008045c Address@mot_spi0 : 0x4920041c Address@mot_spi1 : 0x4920045c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||
| 6 | txemis |
|
||
| 5 | rxfmis |
|
||
| 4 | rxnemis |
|
||
| 3 | TXMIS |
|
||
| 2 | RXMIS |
|
||
| 1 | RTMIS |
|
||
| 0 | RORMIS |
|
||
| spi_icr |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x00081120 Address@com_spi0 : 0x064000a0 Address@com_spi1 : 0x064000e0 Address@com_iol_spi : 0x06c81120 Address@app_spi0 : 0x40080420 Address@app_spi1 : 0x40080460 Address@mot_spi0 : 0x49200420 Address@mot_spi1 : 0x49200460 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
txeic |
|
|
| 5 | "0" |
rxfic |
|
|
| 4 | "0" |
rxneic |
|
|
| 3 | "0" |
TXIC |
|
|
| 2 | "0" |
RXIC |
|
|
| 1 | "0" |
RTIC |
|
|
| 0 | "0" |
RORIC |
|
|
| spi_dmacr |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x00081128 Address@com_spi0 : 0x064000a8 Address@com_spi1 : 0x064000e8 Address@com_iol_spi : 0x06c81128 Address@app_spi0 : 0x40080428 Address@app_spi1 : 0x40080468 Address@mot_spi0 : 0x49200428 Address@mot_spi1 : 0x49200468 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
TXDMAE |
|
|
| 0 | "0" |
RXDMAE |
|
|
| spi_pio_mode |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x0008112c Address@com_spi0 : 0x064000ac Address@com_spi1 : 0x064000ec Address@com_iol_spi : 0x06c8112c Address@app_spi0 : 0x4008042c Address@app_spi1 : 0x4008046c Address@mot_spi0 : 0x4920042c Address@mot_spi1 : 0x4920046c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
miso_oe |
|
|
| 20 | "0" |
mosi_oe |
|
|
| 19 | "0" |
sck_oe |
|
|
| 18 | "0" |
fss2_oe |
|
|
| 17 | "0" |
fss1_oe |
|
|
| 16 | "0" |
fss0_oe |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
miso_out |
|
|
| 12 | "0" |
mosi_out |
|
|
| 11 | "0" |
sck_out |
|
|
| 10 | "0" |
fss2_out |
|
|
| 9 | "0" |
fss1_out |
|
|
| 8 | "0" |
fss0_out |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 | - |
miso_in_ro |
|
|
| 4 | - |
mosi_in_ro |
|
|
| 3 | - |
sck_in_ro |
|
|
| 2 | - |
fss2_in_ro |
|
|
| 1 | - |
fss1_in_ro |
|
|
| 0 | - |
fss0_in_ro |
|
|
| spi_data_register (NETX_SPI%_DATA) |
|
|||
| R/W |
0x00000000 |
Address@iol_spi : 0x00081130 Address@com_spi0 : 0x064000b0 Address@com_spi1 : 0x064000f0 Address@com_iol_spi : 0x06c81130 Address@app_spi0 : 0x40080430 Address@app_spi1 : 0x40080470 Address@mot_spi0 : 0x49200430 Address@mot_spi1 : 0x49200470 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
dr_valid1 |
|
|
| 16 | "0" |
dr_valid0 |
|
|
| 15 - 8 | "00000000" |
data_byte_1 |
|
|
| 7 - 0 | "00000000" |
data_byte_0 |
|
|
| spi_status_register (NETX_SPI%_STAT) |
|
|||
| R |
Address@iol_spi : 0x00081134 Address@com_spi0 : 0x064000b4 Address@com_spi1 : 0x064000f4 Address@com_iol_spi : 0x06c81134 Address@app_spi0 : 0x40080434 Address@app_spi1 : 0x40080474 Address@mot_spi0 : 0x49200434 Address@mot_spi1 : 0x49200474 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 26 | - |
reserved | ||
| 25 | SR_selected |
|
||
| 24 | SR_out_full |
|
||
| 23 | SR_out_empty |
|
||
| 22 | SR_out_fw |
|
||
| 21 | SR_out_fuel |
|
||
| 20 | SR_in_full |
|
||
| 19 | SR_in_recdata |
|
||
| 18 | SR_in_fuel |
|
||
| 17 - 9 | SR_out_fuel_val |
|
||
| 8 - 0 | SR_in_fuel_val |
|
||
| spi_control_register (NETX_SPI%_CTRL) |
|
|||||||||||||||||||||||||||||||||||
| R/W |
0x500000c0 |
Address@iol_spi : 0x00081138 Address@com_spi0 : 0x064000b8 Address@com_spi1 : 0x064000f8 Address@com_iol_spi : 0x06c81138 Address@app_spi0 : 0x40080438 Address@app_spi1 : 0x40080478 Address@mot_spi0 : 0x49200438 Address@mot_spi1 : 0x49200478 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
CR_en |
|
|||||||||||||||||||||||||||||||||
| 30 | "1" |
CR_ms |
|
|||||||||||||||||||||||||||||||||
| 29 | "0" |
CR_cpol |
|
|||||||||||||||||||||||||||||||||
| 28 | "1" |
CR_ncpha |
|
|||||||||||||||||||||||||||||||||
| 27 - 25 | "000" |
CR_burst |
|
|||||||||||||||||||||||||||||||||
| 24 - 22 | "000" |
CR_burstdelay |
|
|||||||||||||||||||||||||||||||||
| 21 | "0" |
CR_clr_outfifo |
|
|||||||||||||||||||||||||||||||||
| 20 | "0" |
CR_clr_infifo |
|
|||||||||||||||||||||||||||||||||
| 19 - 12 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||
| 11 | "0" |
CS_mode |
|
|||||||||||||||||||||||||||||||||
| 10 - 8 | "000" |
CR_ss |
|
|||||||||||||||||||||||||||||||||
| 7 | "1" |
CR_write |
|
|||||||||||||||||||||||||||||||||
| 6 | "1" |
CR_read |
|
|||||||||||||||||||||||||||||||||
| 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||
| 4 - 1 | "0000" |
CR_speed |
|
|||||||||||||||||||||||||||||||||
| 0 | "0" |
CR_softreset |
|
|||||||||||||||||||||||||||||||||
| spi_interrupt_control_register (NETX_SPI%_INT_CTRL) |
|
|||
| R/W |
0x00001008 |
Address@iol_spi : 0x0008113c Address@com_spi0 : 0x064000bc Address@com_spi1 : 0x064000fc Address@com_iol_spi : 0x06c8113c Address@app_spi0 : 0x4008043c Address@app_spi1 : 0x4008047c Address@mot_spi0 : 0x4920043c Address@mot_spi1 : 0x4920047c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
IR_out_full_en |
|
|
| 23 | "0" |
IR_out_empty_en |
|
|
| 22 | "0" |
IR_out_fw_en |
|
|
| 21 | "0" |
IR_out_fuel_en |
|
|
| 20 | "0" |
IR_in_full_en |
|
|
| 19 | "0" |
IR_in_recdata_en |
|
|
| 18 | "0" |
IR_in_fuel_en |
|
|
| 17 - 9 | 0x8 |
IR_out_fuel |
|
|
| 8 - 0 | 0x8 |
IR_in_fuel |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_hsc_start |
| 1-1f | 4-7c | - | reserved |
| 20 | 80 | R/W | sms_hsc_set_start |
| 21-3f | 84-fc | - | reserved |
| 40 | 100 | R/W | sms_hsc_clr_start |
| 41-7f | 104-1fc | - | reserved |
| 80 | 200 | R/W | sms_hsc_irq_set |
| 81 | 204 | R/W | sms_hsc_irq_clr |
| 82 | 208 | R | sms_hsc_irq_state |
| 83-ff | 20c-3fc | - | reserved |
| sms_hsc_start |
|
|||
| R/W |
0x00000000 |
Address@iol_hsc : 0x00081c00 Address@ada_hsc : 0x00101c00 Address@cada_hsc : 0x00110c00 Address@com_hsc : 0x06401000 Address@com_cda_rx_hsc : 0x06710c00 Address@com_cda_tx_hsc : 0x06910c00 Address@com_ada_hsc : 0x06b01c00 Address@com_iol_hsc : 0x06c81c00 Address@app_hsc : 0x40083000 Address@mot_hsc : 0x49000c00 Address@sms_host_hsc : 0x60180000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| sms_hsc_set_start |
|
|||
| R/W |
0x00000000 |
Address@iol_hsc : 0x00081c80 Address@ada_hsc : 0x00101c80 Address@cada_hsc : 0x00110c80 Address@com_hsc : 0x06401080 Address@com_cda_rx_hsc : 0x06710c80 Address@com_cda_tx_hsc : 0x06910c80 Address@com_ada_hsc : 0x06b01c80 Address@com_iol_hsc : 0x06c81c80 Address@app_hsc : 0x40083080 Address@mot_hsc : 0x49000c80 Address@sms_host_hsc : 0x60180080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| sms_hsc_clr_start |
|
|||
| R/W |
0x00000000 |
Address@iol_hsc : 0x00081d00 Address@ada_hsc : 0x00101d00 Address@cada_hsc : 0x00110d00 Address@com_hsc : 0x06401100 Address@com_cda_rx_hsc : 0x06710d00 Address@com_cda_tx_hsc : 0x06910d00 Address@com_ada_hsc : 0x06b01d00 Address@com_iol_hsc : 0x06c81d00 Address@app_hsc : 0x40083100 Address@mot_hsc : 0x49000d00 Address@sms_host_hsc : 0x60180100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| sms_hsc_irq_set |
|
|||
| R/W |
0x00000000 |
Address@iol_hsc : 0x00081e00 Address@ada_hsc : 0x00101e00 Address@cada_hsc : 0x00110e00 Address@com_hsc : 0x06401200 Address@com_cda_rx_hsc : 0x06710e00 Address@com_cda_tx_hsc : 0x06910e00 Address@com_ada_hsc : 0x06b01e00 Address@com_iol_hsc : 0x06c81e00 Address@app_hsc : 0x40083200 Address@mot_hsc : 0x49000e00 Address@sms_host_hsc : 0x60180200 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
set_mask |
|
|
| sms_hsc_irq_clr |
|
|||
| R/W |
0x00000000 |
Address@iol_hsc : 0x00081e04 Address@ada_hsc : 0x00101e04 Address@cada_hsc : 0x00110e04 Address@com_hsc : 0x06401204 Address@com_cda_rx_hsc : 0x06710e04 Address@com_cda_tx_hsc : 0x06910e04 Address@com_ada_hsc : 0x06b01e04 Address@com_iol_hsc : 0x06c81e04 Address@app_hsc : 0x40083204 Address@mot_hsc : 0x49000e04 Address@sms_host_hsc : 0x60180204 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
clr_mask |
|
|
| sms_hsc_irq_state |
|
|||
| R |
Address@iol_hsc : 0x00081e08 Address@ada_hsc : 0x00101e08 Address@cada_hsc : 0x00110e08 Address@com_hsc : 0x06401208 Address@com_cda_rx_hsc : 0x06710e08 Address@com_cda_tx_hsc : 0x06910e08 Address@com_ada_hsc : 0x06b01e08 Address@com_iol_hsc : 0x06c81e08 Address@app_hsc : 0x40083208 Address@mot_hsc : 0x49000e08 Address@sms_host_hsc : 0x60180208 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | irq |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | netx_sys_wdg_ctrl |
| 1 | 4 | R | netx_sys_wdg |
| 2 | 8 | R/W | netx_sys_wdg_irq_timeout |
| 3 | c | R/W | netx_sys_wdg_res_timeout |
| 4 | 10 | R/W | netx_sys_wdg_irq_raw |
| 5 | 14 | R | netx_sys_wdg_irq_masked |
| 6 | 18 | R/W | netx_sys_wdg_irq_msk_set |
| 7 | 1c | R/W | netx_sys_wdg_irq_msk_reset |
| netx_sys_wdg_ctrl |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x00082000 Address@ada_wdg_sys : 0x00102000 Address@cada_wdg_sys : 0x00111000 Address@com_wdg : 0x064003a0 Address@com_cda_rx_wdg_sys : 0x06711000 Address@com_cda_tx_wdg_sys : 0x06911000 Address@com_ada_wdg_sys : 0x06b02000 Address@com_iol_wdg_sys : 0x06c82000 Address@mot_wdg0 : 0x492007a0 Address@mot_wdg1 : 0x492007c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
write_enable |
|
|
| 30 - 29 | 0 |
- |
reserved | |
| 28 | "0" |
wdg_counter_trigger_w |
|
|
| 27 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
irq_req_watchdog |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 - 0 | 0x0 |
wdg_access_code |
|
|
| netx_sys_wdg |
|
|||
| R |
Address@iol_wdg_sys : 0x00082004 Address@ada_wdg_sys : 0x00102004 Address@cada_wdg_sys : 0x00111004 Address@com_wdg : 0x064003a4 Address@com_cda_rx_wdg_sys : 0x06711004 Address@com_cda_tx_wdg_sys : 0x06911004 Address@com_ada_wdg_sys : 0x06b02004 Address@com_iol_wdg_sys : 0x06c82004 Address@mot_wdg0 : 0x492007a4 Address@mot_wdg1 : 0x492007c4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 17 | - |
reserved | ||
| 16 - 0 | wdg_counter |
|
||
| netx_sys_wdg_irq_timeout |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x00082008 Address@ada_wdg_sys : 0x00102008 Address@cada_wdg_sys : 0x00111008 Address@com_wdg : 0x064003a8 Address@com_cda_rx_wdg_sys : 0x06711008 Address@com_cda_tx_wdg_sys : 0x06911008 Address@com_ada_wdg_sys : 0x06b02008 Address@com_iol_wdg_sys : 0x06c82008 Address@mot_wdg0 : 0x492007a8 Address@mot_wdg1 : 0x492007c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
wdg_irq_timeout |
|
|
| netx_sys_wdg_res_timeout |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x0008200c Address@ada_wdg_sys : 0x0010200c Address@cada_wdg_sys : 0x0011100c Address@com_wdg : 0x064003ac Address@com_cda_rx_wdg_sys : 0x0671100c Address@com_cda_tx_wdg_sys : 0x0691100c Address@com_ada_wdg_sys : 0x06b0200c Address@com_iol_wdg_sys : 0x06c8200c Address@mot_wdg0 : 0x492007ac Address@mot_wdg1 : 0x492007cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
wdg_res_timeout |
|
|
| netx_sys_wdg_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x00082010 Address@ada_wdg_sys : 0x00102010 Address@cada_wdg_sys : 0x00111010 Address@com_wdg : 0x064003b0 Address@com_cda_rx_wdg_sys : 0x06711010 Address@com_cda_tx_wdg_sys : 0x06911010 Address@com_ada_wdg_sys : 0x06b02010 Address@com_iol_wdg_sys : 0x06c82010 Address@mot_wdg0 : 0x492007b0 Address@mot_wdg1 : 0x492007d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
wdg_res_irq |
|
|
| netx_sys_wdg_irq_masked |
|
|||
| R |
Address@iol_wdg_sys : 0x00082014 Address@ada_wdg_sys : 0x00102014 Address@cada_wdg_sys : 0x00111014 Address@com_wdg : 0x064003b4 Address@com_cda_rx_wdg_sys : 0x06711014 Address@com_cda_tx_wdg_sys : 0x06911014 Address@com_ada_wdg_sys : 0x06b02014 Address@com_iol_wdg_sys : 0x06c82014 Address@mot_wdg0 : 0x492007b4 Address@mot_wdg1 : 0x492007d4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | wdg_res_irq |
|
||
| netx_sys_wdg_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x00082018 Address@ada_wdg_sys : 0x00102018 Address@cada_wdg_sys : 0x00111018 Address@com_wdg : 0x064003b8 Address@com_cda_rx_wdg_sys : 0x06711018 Address@com_cda_tx_wdg_sys : 0x06911018 Address@com_ada_wdg_sys : 0x06b02018 Address@com_iol_wdg_sys : 0x06c82018 Address@mot_wdg0 : 0x492007b8 Address@mot_wdg1 : 0x492007d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
wdg_res_irq |
|
|
| netx_sys_wdg_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address@iol_wdg_sys : 0x0008201c Address@ada_wdg_sys : 0x0010201c Address@cada_wdg_sys : 0x0011101c Address@com_wdg : 0x064003bc Address@com_cda_rx_wdg_sys : 0x0671101c Address@com_cda_tx_wdg_sys : 0x0691101c Address@com_ada_wdg_sys : 0x06b0201c Address@com_iol_wdg_sys : 0x06c8201c Address@mot_wdg0 : 0x492007bc Address@mot_wdg1 : 0x492007dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
wdg_res_irq |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | timer_config_timer0 |
| 1 | 4 | R/W | timer_config_timer1 |
| 2 | 8 | R/W | timer_config_timer2 |
| 3 | c | R/W | timer_preload_timer0 |
| 4 | 10 | R/W | timer_preload_timer1 |
| 5 | 14 | R/W | timer_preload_timer2 |
| 6 | 18 | R/W | timer_timer0 |
| 7 | 1c | R/W | timer_timer1 |
| 8 | 20 | R/W | timer_timer2 |
| 9 | 24 | R | timer_systime_s |
| a | 28 | R | timer_systime_ns |
| b | 2c | R/W | timer_compare_systime_s_value |
| c | 30 | R/W | timer_irq_raw |
| d | 34 | R | timer_irq_masked |
| e | 38 | R/W | timer_irq_msk_set |
| f | 3c | R/W | timer_irq_msk_reset |
| 10 | 40 | R/W | timer_systime_config |
| 11-1f | 44-7c | - | reserved |
| timer_config_timer0 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082080 Address@iol_arm_tim1 : 0x00082100 Address@ada_arm_tim0 : 0x00102080 Address@ada_arm_tim1 : 0x00102100 Address@cada_arm_tim0 : 0x00111080 Address@cada_arm_tim1 : 0x00111100 Address@com_cda_rx_arm_tim0 : 0x06711080 Address@com_cda_rx_arm_tim1 : 0x06711100 Address@com_cda_tx_arm_tim0 : 0x06911080 Address@com_cda_tx_arm_tim1 : 0x06911100 Address@com_ada_arm_tim0 : 0x06b02080 Address@com_ada_arm_tim1 : 0x06b02100 Address@com_iol_arm_tim0 : 0x06c82080 Address@com_iol_arm_tim1 : 0x06c82100 Address@gxc_timer : 0x07d62600 Address@mot_timer0 : 0x49200800 Address@mot_timer1 : 0x49200880 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 2 | "00" |
systime_config |
|
|
| 1 - 0 | "00" |
mode |
|
|
| timer_config_timer1 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082084 Address@iol_arm_tim1 : 0x00082104 Address@ada_arm_tim0 : 0x00102084 Address@ada_arm_tim1 : 0x00102104 Address@cada_arm_tim0 : 0x00111084 Address@cada_arm_tim1 : 0x00111104 Address@com_cda_rx_arm_tim0 : 0x06711084 Address@com_cda_rx_arm_tim1 : 0x06711104 Address@com_cda_tx_arm_tim0 : 0x06911084 Address@com_cda_tx_arm_tim1 : 0x06911104 Address@com_ada_arm_tim0 : 0x06b02084 Address@com_ada_arm_tim1 : 0x06b02104 Address@com_iol_arm_tim0 : 0x06c82084 Address@com_iol_arm_tim1 : 0x06c82104 Address@gxc_timer : 0x07d62604 Address@mot_timer0 : 0x49200804 Address@mot_timer1 : 0x49200884 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 2 | "00" |
systime_config |
|
|
| 1 - 0 | "00" |
mode |
|
|
| timer_config_timer2 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082088 Address@iol_arm_tim1 : 0x00082108 Address@ada_arm_tim0 : 0x00102088 Address@ada_arm_tim1 : 0x00102108 Address@cada_arm_tim0 : 0x00111088 Address@cada_arm_tim1 : 0x00111108 Address@com_cda_rx_arm_tim0 : 0x06711088 Address@com_cda_rx_arm_tim1 : 0x06711108 Address@com_cda_tx_arm_tim0 : 0x06911088 Address@com_cda_tx_arm_tim1 : 0x06911108 Address@com_ada_arm_tim0 : 0x06b02088 Address@com_ada_arm_tim1 : 0x06b02108 Address@com_iol_arm_tim0 : 0x06c82088 Address@com_iol_arm_tim1 : 0x06c82108 Address@gxc_timer : 0x07d62608 Address@mot_timer0 : 0x49200808 Address@mot_timer1 : 0x49200888 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 2 | "00" |
systime_config |
|
|
| 1 - 0 | "00" |
mode |
|
|
| timer_preload_timer0 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x0008208c Address@iol_arm_tim1 : 0x0008210c Address@ada_arm_tim0 : 0x0010208c Address@ada_arm_tim1 : 0x0010210c Address@cada_arm_tim0 : 0x0011108c Address@cada_arm_tim1 : 0x0011110c Address@com_cda_rx_arm_tim0 : 0x0671108c Address@com_cda_rx_arm_tim1 : 0x0671110c Address@com_cda_tx_arm_tim0 : 0x0691108c Address@com_cda_tx_arm_tim1 : 0x0691110c Address@com_ada_arm_tim0 : 0x06b0208c Address@com_ada_arm_tim1 : 0x06b0210c Address@com_iol_arm_tim0 : 0x06c8208c Address@com_iol_arm_tim1 : 0x06c8210c Address@gxc_timer : 0x07d6260c Address@mot_timer0 : 0x4920080c Address@mot_timer1 : 0x4920088c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_preload_timer1 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082090 Address@iol_arm_tim1 : 0x00082110 Address@ada_arm_tim0 : 0x00102090 Address@ada_arm_tim1 : 0x00102110 Address@cada_arm_tim0 : 0x00111090 Address@cada_arm_tim1 : 0x00111110 Address@com_cda_rx_arm_tim0 : 0x06711090 Address@com_cda_rx_arm_tim1 : 0x06711110 Address@com_cda_tx_arm_tim0 : 0x06911090 Address@com_cda_tx_arm_tim1 : 0x06911110 Address@com_ada_arm_tim0 : 0x06b02090 Address@com_ada_arm_tim1 : 0x06b02110 Address@com_iol_arm_tim0 : 0x06c82090 Address@com_iol_arm_tim1 : 0x06c82110 Address@gxc_timer : 0x07d62610 Address@mot_timer0 : 0x49200810 Address@mot_timer1 : 0x49200890 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_preload_timer2 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082094 Address@iol_arm_tim1 : 0x00082114 Address@ada_arm_tim0 : 0x00102094 Address@ada_arm_tim1 : 0x00102114 Address@cada_arm_tim0 : 0x00111094 Address@cada_arm_tim1 : 0x00111114 Address@com_cda_rx_arm_tim0 : 0x06711094 Address@com_cda_rx_arm_tim1 : 0x06711114 Address@com_cda_tx_arm_tim0 : 0x06911094 Address@com_cda_tx_arm_tim1 : 0x06911114 Address@com_ada_arm_tim0 : 0x06b02094 Address@com_ada_arm_tim1 : 0x06b02114 Address@com_iol_arm_tim0 : 0x06c82094 Address@com_iol_arm_tim1 : 0x06c82114 Address@gxc_timer : 0x07d62614 Address@mot_timer0 : 0x49200814 Address@mot_timer1 : 0x49200894 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_timer0 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x00082098 Address@iol_arm_tim1 : 0x00082118 Address@ada_arm_tim0 : 0x00102098 Address@ada_arm_tim1 : 0x00102118 Address@cada_arm_tim0 : 0x00111098 Address@cada_arm_tim1 : 0x00111118 Address@com_cda_rx_arm_tim0 : 0x06711098 Address@com_cda_rx_arm_tim1 : 0x06711118 Address@com_cda_tx_arm_tim0 : 0x06911098 Address@com_cda_tx_arm_tim1 : 0x06911118 Address@com_ada_arm_tim0 : 0x06b02098 Address@com_ada_arm_tim1 : 0x06b02118 Address@com_iol_arm_tim0 : 0x06c82098 Address@com_iol_arm_tim1 : 0x06c82118 Address@gxc_timer : 0x07d62618 Address@mot_timer0 : 0x49200818 Address@mot_timer1 : 0x49200898 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_timer1 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x0008209c Address@iol_arm_tim1 : 0x0008211c Address@ada_arm_tim0 : 0x0010209c Address@ada_arm_tim1 : 0x0010211c Address@cada_arm_tim0 : 0x0011109c Address@cada_arm_tim1 : 0x0011111c Address@com_cda_rx_arm_tim0 : 0x0671109c Address@com_cda_rx_arm_tim1 : 0x0671111c Address@com_cda_tx_arm_tim0 : 0x0691109c Address@com_cda_tx_arm_tim1 : 0x0691111c Address@com_ada_arm_tim0 : 0x06b0209c Address@com_ada_arm_tim1 : 0x06b0211c Address@com_iol_arm_tim0 : 0x06c8209c Address@com_iol_arm_tim1 : 0x06c8211c Address@gxc_timer : 0x07d6261c Address@mot_timer0 : 0x4920081c Address@mot_timer1 : 0x4920089c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_timer2 |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820a0 Address@iol_arm_tim1 : 0x00082120 Address@ada_arm_tim0 : 0x001020a0 Address@ada_arm_tim1 : 0x00102120 Address@cada_arm_tim0 : 0x001110a0 Address@cada_arm_tim1 : 0x00111120 Address@com_cda_rx_arm_tim0 : 0x067110a0 Address@com_cda_rx_arm_tim1 : 0x06711120 Address@com_cda_tx_arm_tim0 : 0x069110a0 Address@com_cda_tx_arm_tim1 : 0x06911120 Address@com_ada_arm_tim0 : 0x06b020a0 Address@com_ada_arm_tim1 : 0x06b02120 Address@com_iol_arm_tim0 : 0x06c820a0 Address@com_iol_arm_tim1 : 0x06c82120 Address@gxc_timer : 0x07d62620 Address@mot_timer0 : 0x49200820 Address@mot_timer1 : 0x492008a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_systime_s (NETX_SYS_TIME_S) |
|
|||
| R |
Address@iol_arm_tim0 : 0x000820a4 Address@iol_arm_tim1 : 0x00082124 Address@ada_arm_tim0 : 0x001020a4 Address@ada_arm_tim1 : 0x00102124 Address@cada_arm_tim0 : 0x001110a4 Address@cada_arm_tim1 : 0x00111124 Address@com_cda_rx_arm_tim0 : 0x067110a4 Address@com_cda_rx_arm_tim1 : 0x06711124 Address@com_cda_tx_arm_tim0 : 0x069110a4 Address@com_cda_tx_arm_tim1 : 0x06911124 Address@com_ada_arm_tim0 : 0x06b020a4 Address@com_ada_arm_tim1 : 0x06b02124 Address@com_iol_arm_tim0 : 0x06c820a4 Address@com_iol_arm_tim1 : 0x06c82124 Address@gxc_timer : 0x07d62624 Address@mot_timer0 : 0x49200824 Address@mot_timer1 : 0x492008a4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| timer_systime_ns (NETX_SYS_TIME_NS) |
|
|||
| R |
Address@iol_arm_tim0 : 0x000820a8 Address@iol_arm_tim1 : 0x00082128 Address@ada_arm_tim0 : 0x001020a8 Address@ada_arm_tim1 : 0x00102128 Address@cada_arm_tim0 : 0x001110a8 Address@cada_arm_tim1 : 0x00111128 Address@com_cda_rx_arm_tim0 : 0x067110a8 Address@com_cda_rx_arm_tim1 : 0x06711128 Address@com_cda_tx_arm_tim0 : 0x069110a8 Address@com_cda_tx_arm_tim1 : 0x06911128 Address@com_ada_arm_tim0 : 0x06b020a8 Address@com_ada_arm_tim1 : 0x06b02128 Address@com_iol_arm_tim0 : 0x06c820a8 Address@com_iol_arm_tim1 : 0x06c82128 Address@gxc_timer : 0x07d62628 Address@mot_timer0 : 0x49200828 Address@mot_timer1 : 0x492008a8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| timer_compare_systime_s_value |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820ac Address@iol_arm_tim1 : 0x0008212c Address@ada_arm_tim0 : 0x001020ac Address@ada_arm_tim1 : 0x0010212c Address@cada_arm_tim0 : 0x001110ac Address@cada_arm_tim1 : 0x0011112c Address@com_cda_rx_arm_tim0 : 0x067110ac Address@com_cda_rx_arm_tim1 : 0x0671112c Address@com_cda_tx_arm_tim0 : 0x069110ac Address@com_cda_tx_arm_tim1 : 0x0691112c Address@com_ada_arm_tim0 : 0x06b020ac Address@com_ada_arm_tim1 : 0x06b0212c Address@com_iol_arm_tim0 : 0x06c820ac Address@com_iol_arm_tim1 : 0x06c8212c Address@gxc_timer : 0x07d6262c Address@mot_timer0 : 0x4920082c Address@mot_timer1 : 0x492008ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| timer_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820b0 Address@iol_arm_tim1 : 0x00082130 Address@ada_arm_tim0 : 0x001020b0 Address@ada_arm_tim1 : 0x00102130 Address@cada_arm_tim0 : 0x001110b0 Address@cada_arm_tim1 : 0x00111130 Address@com_cda_rx_arm_tim0 : 0x067110b0 Address@com_cda_rx_arm_tim1 : 0x06711130 Address@com_cda_tx_arm_tim0 : 0x069110b0 Address@com_cda_tx_arm_tim1 : 0x06911130 Address@com_ada_arm_tim0 : 0x06b020b0 Address@com_ada_arm_tim1 : 0x06b02130 Address@com_iol_arm_tim0 : 0x06c820b0 Address@com_iol_arm_tim1 : 0x06c82130 Address@gxc_timer : 0x07d62630 Address@mot_timer0 : 0x49200830 Address@mot_timer1 : 0x492008b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
systime_s_irq |
|
|
| 2 | "0" |
timer2_irq |
|
|
| 1 | "0" |
timer1_irq |
|
|
| 0 | "0" |
timer0_irq |
|
|
| timer_irq_masked |
|
|||
| R |
Address@iol_arm_tim0 : 0x000820b4 Address@iol_arm_tim1 : 0x00082134 Address@ada_arm_tim0 : 0x001020b4 Address@ada_arm_tim1 : 0x00102134 Address@cada_arm_tim0 : 0x001110b4 Address@cada_arm_tim1 : 0x00111134 Address@com_cda_rx_arm_tim0 : 0x067110b4 Address@com_cda_rx_arm_tim1 : 0x06711134 Address@com_cda_tx_arm_tim0 : 0x069110b4 Address@com_cda_tx_arm_tim1 : 0x06911134 Address@com_ada_arm_tim0 : 0x06b020b4 Address@com_ada_arm_tim1 : 0x06b02134 Address@com_iol_arm_tim0 : 0x06c820b4 Address@com_iol_arm_tim1 : 0x06c82134 Address@gxc_timer : 0x07d62634 Address@mot_timer0 : 0x49200834 Address@mot_timer1 : 0x492008b4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | systime_s_irq |
|
||
| 2 | timer2_irq |
|
||
| 1 | timer1_irq |
|
||
| 0 | timer0_irq |
|
||
| timer_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820b8 Address@iol_arm_tim1 : 0x00082138 Address@ada_arm_tim0 : 0x001020b8 Address@ada_arm_tim1 : 0x00102138 Address@cada_arm_tim0 : 0x001110b8 Address@cada_arm_tim1 : 0x00111138 Address@com_cda_rx_arm_tim0 : 0x067110b8 Address@com_cda_rx_arm_tim1 : 0x06711138 Address@com_cda_tx_arm_tim0 : 0x069110b8 Address@com_cda_tx_arm_tim1 : 0x06911138 Address@com_ada_arm_tim0 : 0x06b020b8 Address@com_ada_arm_tim1 : 0x06b02138 Address@com_iol_arm_tim0 : 0x06c820b8 Address@com_iol_arm_tim1 : 0x06c82138 Address@gxc_timer : 0x07d62638 Address@mot_timer0 : 0x49200838 Address@mot_timer1 : 0x492008b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
systime_s_irq |
|
|
| 2 | "0" |
timer2_irq |
|
|
| 1 | "0" |
timer1_irq |
|
|
| 0 | "0" |
timer0_irq |
|
|
| timer_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820bc Address@iol_arm_tim1 : 0x0008213c Address@ada_arm_tim0 : 0x001020bc Address@ada_arm_tim1 : 0x0010213c Address@cada_arm_tim0 : 0x001110bc Address@cada_arm_tim1 : 0x0011113c Address@com_cda_rx_arm_tim0 : 0x067110bc Address@com_cda_rx_arm_tim1 : 0x0671113c Address@com_cda_tx_arm_tim0 : 0x069110bc Address@com_cda_tx_arm_tim1 : 0x0691113c Address@com_ada_arm_tim0 : 0x06b020bc Address@com_ada_arm_tim1 : 0x06b0213c Address@com_iol_arm_tim0 : 0x06c820bc Address@com_iol_arm_tim1 : 0x06c8213c Address@gxc_timer : 0x07d6263c Address@mot_timer0 : 0x4920083c Address@mot_timer1 : 0x492008bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
systime_s_irq |
|
|
| 2 | "0" |
timer2_irq |
|
|
| 1 | "0" |
timer1_irq |
|
|
| 0 | "0" |
timer0_irq |
|
|
| timer_systime_config |
|
|||
| R/W |
0x00000000 |
Address@iol_arm_tim0 : 0x000820c0 Address@iol_arm_tim1 : 0x00082140 Address@ada_arm_tim0 : 0x001020c0 Address@ada_arm_tim1 : 0x00102140 Address@cada_arm_tim0 : 0x001110c0 Address@cada_arm_tim1 : 0x00111140 Address@com_cda_rx_arm_tim0 : 0x067110c0 Address@com_cda_rx_arm_tim1 : 0x06711140 Address@com_cda_tx_arm_tim0 : 0x069110c0 Address@com_cda_tx_arm_tim1 : 0x06911140 Address@com_ada_arm_tim0 : 0x06b020c0 Address@com_ada_arm_tim1 : 0x06b02140 Address@com_iol_arm_tim0 : 0x06c820c0 Address@com_iol_arm_tim1 : 0x06c82140 Address@gxc_timer : 0x07d62640 Address@mot_timer0 : 0x49200840 Address@mot_timer1 : 0x492008c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
systime_config |
|
|
| gen_ram_ctrl_ada_0_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100000 Address@com_ada_ram_ctrl : 0x06b00000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100004 Address@com_ada_ram_ctrl : 0x06b00004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100008 Address@com_ada_ram_ctrl : 0x06b00008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010000c Address@com_ada_ram_ctrl : 0x06b0000c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100010 Address@com_ada_ram_ctrl : 0x06b00010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100014 Address@com_ada_ram_ctrl : 0x06b00014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100018 Address@com_ada_ram_ctrl : 0x06b00018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010001c Address@com_ada_ram_ctrl : 0x06b0001c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power8 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100020 Address@com_ada_ram_ctrl : 0x06b00020 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power9 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100024 Address@com_ada_ram_ctrl : 0x06b00024 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power10 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100028 Address@com_ada_ram_ctrl : 0x06b00028 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power11 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010002c Address@com_ada_ram_ctrl : 0x06b0002c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power12 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100030 Address@com_ada_ram_ctrl : 0x06b00030 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power13 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100034 Address@com_ada_ram_ctrl : 0x06b00034 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power14 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100038 Address@com_ada_ram_ctrl : 0x06b00038 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power15 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010003c Address@com_ada_ram_ctrl : 0x06b0003c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power16 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100040 Address@com_ada_ram_ctrl : 0x06b00040 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power17 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100044 Address@com_ada_ram_ctrl : 0x06b00044 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power18 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100048 Address@com_ada_ram_ctrl : 0x06b00048 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power19 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010004c Address@com_ada_ram_ctrl : 0x06b0004c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power20 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100050 Address@com_ada_ram_ctrl : 0x06b00050 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power21 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100054 Address@com_ada_ram_ctrl : 0x06b00054 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power22 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100058 Address@com_ada_ram_ctrl : 0x06b00058 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power23 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010005c Address@com_ada_ram_ctrl : 0x06b0005c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power24 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100060 Address@com_ada_ram_ctrl : 0x06b00060 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power25 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100064 Address@com_ada_ram_ctrl : 0x06b00064 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power26 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100068 Address@com_ada_ram_ctrl : 0x06b00068 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power27 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010006c Address@com_ada_ram_ctrl : 0x06b0006c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power28 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100070 Address@com_ada_ram_ctrl : 0x06b00070 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power29 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100074 Address@com_ada_ram_ctrl : 0x06b00074 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power30 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100078 Address@com_ada_ram_ctrl : 0x06b00078 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power31 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010007c Address@com_ada_ram_ctrl : 0x06b0007c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power32 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100080 Address@com_ada_ram_ctrl : 0x06b00080 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power33 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100084 Address@com_ada_ram_ctrl : 0x06b00084 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power34 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100088 Address@com_ada_ram_ctrl : 0x06b00088 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power35 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010008c Address@com_ada_ram_ctrl : 0x06b0008c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power36 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100090 Address@com_ada_ram_ctrl : 0x06b00090 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power37 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100094 Address@com_ada_ram_ctrl : 0x06b00094 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power38 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x00100098 Address@com_ada_ram_ctrl : 0x06b00098 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power39 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x0010009c Address@com_ada_ram_ctrl : 0x06b0009c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power40 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x001000a0 Address@com_ada_ram_ctrl : 0x06b000a0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_mbist_power41 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@ada_ram_ctrl : 0x001000a4 Address@com_ada_ram_ctrl : 0x06b000a4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ada_0_ecc0 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100800 Address@com_ada_ram_ctrl : 0x06b00800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_ada_0_ecc1 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100804 Address@com_ada_ram_ctrl : 0x06b00804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_ada_0_ecc2 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100808 Address@com_ada_ram_ctrl : 0x06b00808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_ada_0_ecc3 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x0010080c Address@com_ada_ram_ctrl : 0x06b0080c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_ada_0_ecc_status_corr0 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100a00 Address@com_ada_ram_ctrl : 0x06b00a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_corr1 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100a04 Address@com_ada_ram_ctrl : 0x06b00a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_corr2 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100a08 Address@com_ada_ram_ctrl : 0x06b00a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_corr3 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100a0c Address@com_ada_ram_ctrl : 0x06b00a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_noncorr0 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100c00 Address@com_ada_ram_ctrl : 0x06b00c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_noncorr1 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100c04 Address@com_ada_ram_ctrl : 0x06b00c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_noncorr2 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100c08 Address@com_ada_ram_ctrl : 0x06b00c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_ecc_status_noncorr3 |
|
|||
| R |
Address@ada_ram_ctrl : 0x00100c0c Address@com_ada_ram_ctrl : 0x06b00c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ada_0_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e00 Address@com_ada_ram_ctrl : 0x06b00e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_ada_0_irq_raw_reg1 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e04 Address@com_ada_ram_ctrl : 0x06b00e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_ada_0_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e40 Address@com_ada_ram_ctrl : 0x06b00e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_ada_0_irq_masked_reg1 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e44 Address@com_ada_ram_ctrl : 0x06b00e44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_ada_0_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e80 Address@com_ada_ram_ctrl : 0x06b00e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_ada_0_irq_mask_set_reg1 |
|
|||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100e84 Address@com_ada_ram_ctrl : 0x06b00e84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_ada_0_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100ec0 Address@com_ada_ram_ctrl : 0x06b00ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_ada_0_irq_mask_rst_reg1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@ada_ram_ctrl : 0x00100ec4 Address@com_ada_ram_ctrl : 0x06b00ec4 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_ada_0_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address@ada_ram_ctrl : 0x00100efc Address@com_ada_ram_ctrl : 0x06b00efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| gen_ram_ctrl_cada_0_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100000 Address@com_cda_rx_ram_ctrl : 0x06700000 Address@com_cda_tx_ram_ctrl : 0x06900000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100004 Address@com_cda_rx_ram_ctrl : 0x06700004 Address@com_cda_tx_ram_ctrl : 0x06900004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100008 Address@com_cda_rx_ram_ctrl : 0x06700008 Address@com_cda_tx_ram_ctrl : 0x06900008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010000c Address@com_cda_rx_ram_ctrl : 0x0670000c Address@com_cda_tx_ram_ctrl : 0x0690000c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100010 Address@com_cda_rx_ram_ctrl : 0x06700010 Address@com_cda_tx_ram_ctrl : 0x06900010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100014 Address@com_cda_rx_ram_ctrl : 0x06700014 Address@com_cda_tx_ram_ctrl : 0x06900014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100018 Address@com_cda_rx_ram_ctrl : 0x06700018 Address@com_cda_tx_ram_ctrl : 0x06900018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010001c Address@com_cda_rx_ram_ctrl : 0x0670001c Address@com_cda_tx_ram_ctrl : 0x0690001c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power8 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100020 Address@com_cda_rx_ram_ctrl : 0x06700020 Address@com_cda_tx_ram_ctrl : 0x06900020 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power9 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100024 Address@com_cda_rx_ram_ctrl : 0x06700024 Address@com_cda_tx_ram_ctrl : 0x06900024 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power10 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100028 Address@com_cda_rx_ram_ctrl : 0x06700028 Address@com_cda_tx_ram_ctrl : 0x06900028 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power11 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010002c Address@com_cda_rx_ram_ctrl : 0x0670002c Address@com_cda_tx_ram_ctrl : 0x0690002c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power12 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100030 Address@com_cda_rx_ram_ctrl : 0x06700030 Address@com_cda_tx_ram_ctrl : 0x06900030 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power13 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100034 Address@com_cda_rx_ram_ctrl : 0x06700034 Address@com_cda_tx_ram_ctrl : 0x06900034 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power14 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100038 Address@com_cda_rx_ram_ctrl : 0x06700038 Address@com_cda_tx_ram_ctrl : 0x06900038 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power15 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010003c Address@com_cda_rx_ram_ctrl : 0x0670003c Address@com_cda_tx_ram_ctrl : 0x0690003c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power16 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100040 Address@com_cda_rx_ram_ctrl : 0x06700040 Address@com_cda_tx_ram_ctrl : 0x06900040 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power17 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100044 Address@com_cda_rx_ram_ctrl : 0x06700044 Address@com_cda_tx_ram_ctrl : 0x06900044 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power18 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100048 Address@com_cda_rx_ram_ctrl : 0x06700048 Address@com_cda_tx_ram_ctrl : 0x06900048 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power19 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010004c Address@com_cda_rx_ram_ctrl : 0x0670004c Address@com_cda_tx_ram_ctrl : 0x0690004c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power20 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100050 Address@com_cda_rx_ram_ctrl : 0x06700050 Address@com_cda_tx_ram_ctrl : 0x06900050 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power21 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100054 Address@com_cda_rx_ram_ctrl : 0x06700054 Address@com_cda_tx_ram_ctrl : 0x06900054 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power22 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100058 Address@com_cda_rx_ram_ctrl : 0x06700058 Address@com_cda_tx_ram_ctrl : 0x06900058 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power23 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010005c Address@com_cda_rx_ram_ctrl : 0x0670005c Address@com_cda_tx_ram_ctrl : 0x0690005c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power24 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100060 Address@com_cda_rx_ram_ctrl : 0x06700060 Address@com_cda_tx_ram_ctrl : 0x06900060 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power25 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100064 Address@com_cda_rx_ram_ctrl : 0x06700064 Address@com_cda_tx_ram_ctrl : 0x06900064 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power26 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100068 Address@com_cda_rx_ram_ctrl : 0x06700068 Address@com_cda_tx_ram_ctrl : 0x06900068 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power27 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010006c Address@com_cda_rx_ram_ctrl : 0x0670006c Address@com_cda_tx_ram_ctrl : 0x0690006c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power28 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100070 Address@com_cda_rx_ram_ctrl : 0x06700070 Address@com_cda_tx_ram_ctrl : 0x06900070 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power29 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100074 Address@com_cda_rx_ram_ctrl : 0x06700074 Address@com_cda_tx_ram_ctrl : 0x06900074 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power30 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100078 Address@com_cda_rx_ram_ctrl : 0x06700078 Address@com_cda_tx_ram_ctrl : 0x06900078 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power31 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010007c Address@com_cda_rx_ram_ctrl : 0x0670007c Address@com_cda_tx_ram_ctrl : 0x0690007c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power32 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100080 Address@com_cda_rx_ram_ctrl : 0x06700080 Address@com_cda_tx_ram_ctrl : 0x06900080 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power33 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100084 Address@com_cda_rx_ram_ctrl : 0x06700084 Address@com_cda_tx_ram_ctrl : 0x06900084 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power34 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100088 Address@com_cda_rx_ram_ctrl : 0x06700088 Address@com_cda_tx_ram_ctrl : 0x06900088 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power35 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010008c Address@com_cda_rx_ram_ctrl : 0x0670008c Address@com_cda_tx_ram_ctrl : 0x0690008c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power36 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100090 Address@com_cda_rx_ram_ctrl : 0x06700090 Address@com_cda_tx_ram_ctrl : 0x06900090 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power37 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100094 Address@com_cda_rx_ram_ctrl : 0x06700094 Address@com_cda_tx_ram_ctrl : 0x06900094 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power38 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x00100098 Address@com_cda_rx_ram_ctrl : 0x06700098 Address@com_cda_tx_ram_ctrl : 0x06900098 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power39 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x0010009c Address@com_cda_rx_ram_ctrl : 0x0670009c Address@com_cda_tx_ram_ctrl : 0x0690009c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power40 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000a0 Address@com_cda_rx_ram_ctrl : 0x067000a0 Address@com_cda_tx_ram_ctrl : 0x069000a0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power41 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000a4 Address@com_cda_rx_ram_ctrl : 0x067000a4 Address@com_cda_tx_ram_ctrl : 0x069000a4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power42 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000a8 Address@com_cda_rx_ram_ctrl : 0x067000a8 Address@com_cda_tx_ram_ctrl : 0x069000a8 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power43 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000ac Address@com_cda_rx_ram_ctrl : 0x067000ac Address@com_cda_tx_ram_ctrl : 0x069000ac |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power44 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000b0 Address@com_cda_rx_ram_ctrl : 0x067000b0 Address@com_cda_tx_ram_ctrl : 0x069000b0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_mbist_power45 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@cada_ram_ctrl : 0x001000b4 Address@com_cda_rx_ram_ctrl : 0x067000b4 Address@com_cda_tx_ram_ctrl : 0x069000b4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_cada_0_ecc0 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100800 Address@com_cda_rx_ram_ctrl : 0x06700800 Address@com_cda_tx_ram_ctrl : 0x06900800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_cada_0_ecc1 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100804 Address@com_cda_rx_ram_ctrl : 0x06700804 Address@com_cda_tx_ram_ctrl : 0x06900804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_cada_0_ecc2 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100808 Address@com_cda_rx_ram_ctrl : 0x06700808 Address@com_cda_tx_ram_ctrl : 0x06900808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_cada_0_ecc3 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x0010080c Address@com_cda_rx_ram_ctrl : 0x0670080c Address@com_cda_tx_ram_ctrl : 0x0690080c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_cada_0_ecc_status_corr0 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100a00 Address@com_cda_rx_ram_ctrl : 0x06700a00 Address@com_cda_tx_ram_ctrl : 0x06900a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_corr1 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100a04 Address@com_cda_rx_ram_ctrl : 0x06700a04 Address@com_cda_tx_ram_ctrl : 0x06900a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_corr2 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100a08 Address@com_cda_rx_ram_ctrl : 0x06700a08 Address@com_cda_tx_ram_ctrl : 0x06900a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_corr3 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100a0c Address@com_cda_rx_ram_ctrl : 0x06700a0c Address@com_cda_tx_ram_ctrl : 0x06900a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_noncorr0 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100c00 Address@com_cda_rx_ram_ctrl : 0x06700c00 Address@com_cda_tx_ram_ctrl : 0x06900c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_noncorr1 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100c04 Address@com_cda_rx_ram_ctrl : 0x06700c04 Address@com_cda_tx_ram_ctrl : 0x06900c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_noncorr2 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100c08 Address@com_cda_rx_ram_ctrl : 0x06700c08 Address@com_cda_tx_ram_ctrl : 0x06900c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_ecc_status_noncorr3 |
|
|||
| R |
Address@cada_ram_ctrl : 0x00100c0c Address@com_cda_rx_ram_ctrl : 0x06700c0c Address@com_cda_tx_ram_ctrl : 0x06900c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_cada_0_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e00 Address@com_cda_rx_ram_ctrl : 0x06700e00 Address@com_cda_tx_ram_ctrl : 0x06900e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_cada_0_irq_raw_reg1 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e04 Address@com_cda_rx_ram_ctrl : 0x06700e04 Address@com_cda_tx_ram_ctrl : 0x06900e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
mem_45_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_44_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_43_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_42_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_cada_0_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e40 Address@com_cda_rx_ram_ctrl : 0x06700e40 Address@com_cda_tx_ram_ctrl : 0x06900e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_cada_0_irq_masked_reg1 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e44 Address@com_cda_rx_ram_ctrl : 0x06700e44 Address@com_cda_tx_ram_ctrl : 0x06900e44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
mem_45_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_44_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_43_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_42_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_cada_0_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e80 Address@com_cda_rx_ram_ctrl : 0x06700e80 Address@com_cda_tx_ram_ctrl : 0x06900e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_cada_0_irq_mask_set_reg1 |
|
|||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100e84 Address@com_cda_rx_ram_ctrl : 0x06700e84 Address@com_cda_tx_ram_ctrl : 0x06900e84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
mem_45_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_44_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_43_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_42_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|
| gen_ram_ctrl_cada_0_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100ec0 Address@com_cda_rx_ram_ctrl : 0x06700ec0 Address@com_cda_tx_ram_ctrl : 0x06900ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_23_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
mem_22_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
mem_21_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
mem_20_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
mem_19_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
mem_18_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_17_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_16_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_15_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_14_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_13_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_12_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_11_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_10_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_9_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_8_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_cada_0_irq_mask_rst_reg1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@cada_ram_ctrl : 0x00100ec4 Address@com_cda_rx_ram_ctrl : 0x06700ec4 Address@com_cda_tx_ram_ctrl : 0x06900ec4 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_45_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_44_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_43_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_42_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_41_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_40_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_39_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_38_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_37_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_36_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_35_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_34_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_33_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_32_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_31_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_30_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_29_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_28_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_27_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_26_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_25_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_24_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_cada_0_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address@cada_ram_ctrl : 0x00100efc Address@com_cda_rx_ram_ctrl : 0x06700efc Address@com_cda_tx_ram_ctrl : 0x06900efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | eh2_power_mgmt |
| 1 | 4 | R | eh2_power_mgmt_info |
| 2 | 8 | R/W | eh2_rst_ctrl |
| 3 | c | R/W | eh2_rst_vec |
| 4 | 10 | R/W | eh2_nmi_vec |
| 5 | 14 | W | eh2_set_softint |
| 6 | 18 | W | eh2_reset_softint |
| 7 | 1c | R | eh2_softint |
| 8-3f | 20-fc | - | reserved |
| eh2_power_mgmt |
|
|||
| R/W |
0x0000000c |
Address@cada_config : 0x00101000 Address@ada_config : 0x00101000 Address@com_cda_rx_config : 0x06701000 Address@com_cda_tx_config : 0x06901000 Address@com_ada_config : 0x06b01000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 2 | "11" |
halt_req |
|
|
| 1 - 0 | "00" |
run_req |
|
|
| eh2_power_mgmt_info |
|
|||
| R |
Address@cada_config : 0x00101004 Address@ada_config : 0x00101004 Address@com_cda_rx_config : 0x06701004 Address@com_cda_tx_config : 0x06901004 Address@com_ada_config : 0x06b01004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | wdg_active |
|
||
| 7 - 6 | debug_mode_status |
|
||
| 5 - 4 | halt_status |
|
||
| 3 - 2 | halt_ack |
|
||
| 1 - 0 | run_ack |
|
||
| eh2_rst_ctrl |
|
|||
| R/W |
0x00000000 |
Address@cada_config : 0x00101008 Address@ada_config : 0x00101008 Address@com_cda_rx_config : 0x06701008 Address@com_cda_tx_config : 0x06901008 Address@com_ada_config : 0x06b01008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
cpu_reset_n |
|
|
| eh2_rst_vec |
|
|||
| R/W |
0xee000000 |
Address@cada_config : 0x0010100c Address@ada_config : 0x0010100c Address@com_cda_rx_config : 0x0670100c Address@com_cda_tx_config : 0x0690100c Address@com_ada_config : 0x06b0100c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xee000000 |
reset_vector |
|
|
| eh2_nmi_vec |
|
|||
| R/W |
0xee000000 |
Address@cada_config : 0x00101010 Address@ada_config : 0x00101010 Address@com_cda_rx_config : 0x06701010 Address@com_cda_tx_config : 0x06901010 Address@com_ada_config : 0x06b01010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xee000000 |
nmi_vector |
|
|
| eh2_set_softint |
|
|||
| W |
0x00000000 |
Address@cada_config : 0x00101014 Address@ada_config : 0x00101014 Address@com_cda_rx_config : 0x06701014 Address@com_cda_tx_config : 0x06901014 Address@com_ada_config : 0x06b01014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
thread_1 |
|
|
| 0 | "0" |
thread_0 |
|
|
| eh2_reset_softint |
|
|||
| W |
0x00000000 |
Address@cada_config : 0x00101018 Address@ada_config : 0x00101018 Address@com_cda_rx_config : 0x06701018 Address@com_cda_tx_config : 0x06901018 Address@com_ada_config : 0x06b01018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
thread_1 |
|
|
| 0 | "0" |
thread_0 |
|
|
| eh2_softint |
|
|||
| R |
Address@cada_config : 0x0010101c Address@ada_config : 0x0010101c Address@com_cda_rx_config : 0x0670101c Address@com_cda_tx_config : 0x0690101c Address@com_ada_config : 0x06b0101c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | thread_1 |
|
||
| 0 | thread_0 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | ise_dma_cfg |
| 1 | 4 | R/W | ise_dma_axi_cfg |
| 2 | 8 | R | ise_dma_status |
| 3 | c | R | ise_dma_debug_axi_read_addr |
| 4 | 10 | R | ise_dma_debug_axi_write_addr |
| 5 | 14 | R/W | ise_dma_debug_cfg |
| 6 | 18 | R | ise_dma_current_job |
| 7 | 1c | R | ise_dma_last_job |
| 8 | 20 | W | ise_dma_ctrl |
| 9 | 24 | W | ise_dma_job_queue_push |
| a | 28 | R | ise_dma_job_done_queue_read |
| b | 2c | - | reserved |
| c | 30 | R/W | ise_dma_irq_raw |
| d | 34 | R/W | ise_dma_irq_masked |
| e | 38 | R/W | ise_dma_irq_mask_set |
| f | 3c | R/W | ise_dma_irq_mask_rst |
| ise_dma_cfg |
|
|||
| R/W |
0x00001008 |
Address@cada_internal_ise_dma : 0x00110000 Address@ise_dma : 0x06430000 Address@com_ise_dma : 0x06430000 Address@com_cda_rx_ise_dma : 0x06710000 Address@com_cda_tx_ise_dma : 0x06910000 Address@app_ise_dma : 0x400e0000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
job_done_queue_lists |
|
|
| 13 | "0" |
job_done_queue_enable |
|
|
| 12 - 8 | "10000" |
job_done_queue_wm |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "01000" |
job_queue_wm |
|
|
| ise_dma_axi_cfg |
|
|||
| R/W |
0x07070912 |
Address@cada_internal_ise_dma : 0x00110004 Address@ise_dma : 0x06430004 Address@com_ise_dma : 0x06430004 Address@com_cda_rx_ise_dma : 0x06710004 Address@com_cda_tx_ise_dma : 0x06910004 Address@app_ise_dma : 0x400e0004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000111" |
max_burst_len_write |
|
|
| 23 - 16 | "00000111" |
max_burst_len_read |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 11 | "001" |
awprot |
|
|
| 10 - 7 | "0010" |
awcache |
|
|
| 6 - 4 | "001" |
arprot |
|
|
| 3 - 0 | "0010" |
arcache |
|
|
| ise_dma_status |
|
|||
| R |
Address@cada_internal_ise_dma : 0x00110008 Address@ise_dma : 0x06430008 Address@com_ise_dma : 0x06430008 Address@com_cda_rx_ise_dma : 0x06710008 Address@com_cda_tx_ise_dma : 0x06910008 Address@app_ise_dma : 0x400e0008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | waiting_for_job_abort |
|
||
| 30 | read_err_job_desc |
|
||
| 29 | job_done_queue_empty |
|
||
| 28 | job_done_queue_full |
|
||
| 27 - 23 | job_done_queue_fill |
|
||
| 22 | idle |
|
||
| 21 | job_queue_empty |
|
||
| 20 | job_queue_full |
|
||
| 19 - 15 | job_queue_fill |
|
||
| 14 | job_output_done |
|
||
| 13 | job_output_busy |
|
||
| 12 | job_process_done |
|
||
| 11 | job_process_busy |
|
||
| 10 | job_input_done |
|
||
| 9 | job_input_busy |
|
||
| 8 | job_in_progress |
|
||
| 7 - 4 | job_cfg_err |
|
||
| 3 - 2 | axi_write_err |
|
||
| 1 - 0 | axi_read_err |
|
||
| ise_dma_debug_axi_read_addr |
|
|||
| R |
Address@cada_internal_ise_dma : 0x0011000c Address@ise_dma : 0x0643000c Address@com_ise_dma : 0x0643000c Address@com_cda_rx_ise_dma : 0x0671000c Address@com_cda_tx_ise_dma : 0x0691000c Address@app_ise_dma : 0x400e000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| ise_dma_debug_axi_write_addr |
|
|||
| R |
Address@cada_internal_ise_dma : 0x00110010 Address@ise_dma : 0x06430010 Address@com_ise_dma : 0x06430010 Address@com_cda_rx_ise_dma : 0x06710010 Address@com_cda_tx_ise_dma : 0x06910010 Address@app_ise_dma : 0x400e0010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| ise_dma_debug_cfg |
|
|||
| R/W |
0x02000700 |
Address@cada_internal_ise_dma : 0x00110014 Address@ise_dma : 0x06430014 Address@com_ise_dma : 0x06430014 Address@com_cda_rx_ise_dma : 0x06710014 Address@com_cda_tx_ise_dma : 0x06910014 Address@app_ise_dma : 0x400e0014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 16 | 0x200 |
inactivity_threshold |
|
|
| 15 - 11 | 0 |
- |
reserved | |
| 10 - 8 | "111" |
desc_req_words |
|
|
| 7 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
override_clock_en_ctrl |
|
|
| ise_dma_current_job |
|
|||
| R |
Address@cada_internal_ise_dma : 0x00110018 Address@ise_dma : 0x06430018 Address@com_ise_dma : 0x06430018 Address@com_cda_rx_ise_dma : 0x06710018 Address@com_cda_tx_ise_dma : 0x06910018 Address@app_ise_dma : 0x400e0018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ptr |
|
||
| ise_dma_last_job |
|
|||
| R |
Address@cada_internal_ise_dma : 0x0011001c Address@ise_dma : 0x0643001c Address@com_ise_dma : 0x0643001c Address@com_cda_rx_ise_dma : 0x0671001c Address@com_cda_tx_ise_dma : 0x0691001c Address@app_ise_dma : 0x400e001c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ptr |
|
||
| ise_dma_ctrl |
|
|||
| W |
0x00000000 |
Address@cada_internal_ise_dma : 0x00110020 Address@ise_dma : 0x06430020 Address@com_ise_dma : 0x06430020 Address@com_cda_rx_ise_dma : 0x06710020 Address@com_cda_tx_ise_dma : 0x06910020 Address@app_ise_dma : 0x400e0020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
axi_write_cancel |
|
|
| 6 | "0" |
axi_read_cancel |
|
|
| 5 | "0" |
axi_write_flush |
|
|
| 4 | "0" |
axi_read_flush |
|
|
| 3 | "0" |
job_list_abort |
|
|
| 2 | "0" |
job_abort |
|
|
| 1 | "0" |
job_done_queue_clear |
|
|
| 0 | "0" |
job_queue_clear |
|
|
| ise_dma_job_queue_push |
|
|||
| W |
0x00000000 |
Address@cada_internal_ise_dma : 0x00110024 Address@ise_dma : 0x06430024 Address@com_ise_dma : 0x06430024 Address@com_cda_rx_ise_dma : 0x06710024 Address@com_cda_tx_ise_dma : 0x06910024 Address@app_ise_dma : 0x400e0024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| ise_dma_job_done_queue_read |
|
|||
| R |
Address@cada_internal_ise_dma : 0x00110028 Address@ise_dma : 0x06430028 Address@com_ise_dma : 0x06430028 Address@com_cda_rx_ise_dma : 0x06710028 Address@com_cda_tx_ise_dma : 0x06910028 Address@app_ise_dma : 0x400e0028 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ptr |
|
||
| ise_dma_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@cada_internal_ise_dma : 0x00110030 Address@ise_dma : 0x06430030 Address@com_ise_dma : 0x06430030 Address@com_cda_rx_ise_dma : 0x06710030 Address@com_cda_tx_ise_dma : 0x06910030 Address@app_ise_dma : 0x400e0030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
waiting_for_job_abort |
|
|
| 11 | "0" |
inactivity |
|
|
| 10 | "0" |
job_done_queue_wm |
|
|
| 9 | "0" |
job_done_queue_full |
|
|
| 8 | "0" |
job_list_finished |
|
|
| 7 | "0" |
job_finished_error |
|
|
| 6 | "0" |
job_finished_ok |
|
|
| 5 | "0" |
job_finished |
|
|
| 4 | "0" |
job_error |
|
|
| 3 | "0" |
job_queue_wm |
|
|
| 2 | "0" |
job_queue_full |
|
|
| 1 | "0" |
job_queue_empty |
|
|
| 0 | "0" |
job_queue_overflow |
|
|
| ise_dma_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@cada_internal_ise_dma : 0x00110034 Address@ise_dma : 0x06430034 Address@com_ise_dma : 0x06430034 Address@com_cda_rx_ise_dma : 0x06710034 Address@com_cda_tx_ise_dma : 0x06910034 Address@app_ise_dma : 0x400e0034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
waiting_for_job_abort |
|
|
| 11 | "0" |
inactivity |
|
|
| 10 | "0" |
job_done_queue_wm |
|
|
| 9 | "0" |
job_done_queue_full |
|
|
| 8 | "0" |
job_list_finished |
|
|
| 7 | "0" |
job_finished_error |
|
|
| 6 | "0" |
job_finished_ok |
|
|
| 5 | "0" |
job_finished |
|
|
| 4 | "0" |
job_error |
|
|
| 3 | "0" |
job_queue_wm |
|
|
| 2 | "0" |
job_queue_full |
|
|
| 1 | "0" |
job_queue_empty |
|
|
| 0 | "0" |
job_queue_overflow |
|
|
| ise_dma_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@cada_internal_ise_dma : 0x00110038 Address@ise_dma : 0x06430038 Address@com_ise_dma : 0x06430038 Address@com_cda_rx_ise_dma : 0x06710038 Address@com_cda_tx_ise_dma : 0x06910038 Address@app_ise_dma : 0x400e0038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
waiting_for_job_abort |
|
|
| 11 | "0" |
inactivity |
|
|
| 10 | "0" |
job_done_queue_wm |
|
|
| 9 | "0" |
job_done_queue_full |
|
|
| 8 | "0" |
job_list_finished |
|
|
| 7 | "0" |
job_finished_error |
|
|
| 6 | "0" |
job_finished_ok |
|
|
| 5 | "0" |
job_finished |
|
|
| 4 | "0" |
job_error |
|
|
| 3 | "0" |
job_queue_wm |
|
|
| 2 | "0" |
job_queue_full |
|
|
| 1 | "0" |
job_queue_empty |
|
|
| 0 | "0" |
job_queue_overflow |
|
|
| ise_dma_irq_mask_rst |
|
|||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@cada_internal_ise_dma : 0x0011003c Address@ise_dma : 0x0643003c Address@com_ise_dma : 0x0643003c Address@com_cda_rx_ise_dma : 0x0671003c Address@com_cda_tx_ise_dma : 0x0691003c Address@app_ise_dma : 0x400e003c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||||||||||||||||||||||
| 12 | "0" |
waiting_for_job_abort |
|
|||||||||||||||||||||||||||||
| 11 | "0" |
inactivity |
|
|||||||||||||||||||||||||||||
| 10 | "0" |
job_done_queue_wm |
|
|||||||||||||||||||||||||||||
| 9 | "0" |
job_done_queue_full |
|
|||||||||||||||||||||||||||||
| 8 | "0" |
job_list_finished |
|
|||||||||||||||||||||||||||||
| 7 | "0" |
job_finished_error |
|
|||||||||||||||||||||||||||||
| 6 | "0" |
job_finished_ok |
|
|||||||||||||||||||||||||||||
| 5 | "0" |
job_finished |
|
|||||||||||||||||||||||||||||
| 4 | "0" |
job_error |
|
|||||||||||||||||||||||||||||
| 3 | "0" |
job_queue_wm |
|
|||||||||||||||||||||||||||||
| 2 | "0" |
job_queue_full |
|
|||||||||||||||||||||||||||||
| 1 | "0" |
job_queue_empty |
|
|||||||||||||||||||||||||||||
| 0 | "0" |
job_queue_overflow |
|
|||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | intram512_base |
| 1-1fffe | 4-7fff8 | - | reserved |
| 1ffff | 7fffc | R/W | intram512_end |
| intram512_base |
|
|||
| R/W |
0x00000000 |
Address : 0x02000000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
intram512_base | ||
| intram512_end | |||
| R/W |
0x00000000 |
Address : 0x0207fffc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
intram512_end | |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_netx22xx_4_mbist_power0 |
| 1-1ff | 4-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_netx22xx_4_ecc0 |
| 201-27f | 804-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_netx22xx_4_ecc_status_corr0 |
| 281-2ff | a04-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_netx22xx_4_ecc_status_noncorr0 |
| 301-37f | c04-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_netx22xx_4_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_netx22xx_4_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_netx22xx_4_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_netx22xx_4_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_netx22xx_4_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_netx22xx_4_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x03f00000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_4_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x03f00800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_4_ecc_status_corr0 |
|
|||
| R |
Address : 0x03f00a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_4_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x03f00c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_4_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x03f00e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_4_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x03f00e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_4_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x03f00e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_4_irq_mask_rst_reg0 |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x03f00ec0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||
| gen_ram_ctrl_netx22xx_4_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x03f00efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | intram1024_base |
| 1-3fffe | 4-ffff8 | - | reserved |
| 3ffff | ffffc | R/W | intram1024_end |
| intram1024_base |
|
|||
| R/W |
0x00000000 |
Address@com_intram0 : 0x06000000 Address@com_intram1 : 0x06100000 Address@com_intram2 : 0x06200000 Address@sms_com_intram0 : 0x66000000 Address@sms_com_intram1 : 0x66100000 Address@sms_com_intram2 : 0x66200000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
intram1024_base | ||
| intram1024_end | |||
| R/W |
0x00000000 |
Address@com_intram0 : 0x060ffffc Address@com_intram1 : 0x061ffffc Address@com_intram2 : 0x062ffffc Address@sms_com_intram0 : 0x660ffffc Address@sms_com_intram1 : 0x661ffffc Address@sms_com_intram2 : 0x662ffffc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
intram1024_end | |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | i2c_mcr |
| 1 | 4 | R/W | i2c_scr |
| 2 | 8 | R/W | i2c_cmd |
| 3 | c | R/W | i2c_mdr |
| 4 | 10 | R/W | i2c_sdr |
| 5 | 14 | R/W | i2c_mfifo_cr |
| 6 | 18 | R/W | i2c_sfifo_cr |
| 7 | 1c | R/W | i2c_sr |
| 8 | 20 | R/W | i2c_irqmsk |
| 9 | 24 | R/W | i2c_irqsr |
| a | 28 | R | i2c_irqmsked |
| b | 2c | R/W | i2c_dmacr |
| c | 30 | R/W | i2c_pio |
| d-f | 34-3c | - | reserved |
| i2c_mcr |
|
||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400000 Address@com_i2c1 : 0x06400040 Address@app_i2c0 : 0x40080380 Address@app_i2c1 : 0x400803c0 Address@mot_i2c0 : 0x49200380 Address@mot_i2c1 : 0x492003c0 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||||||||||||||||||||||
| 18 | "0" |
en_timeout |
|
||||||||||||||||||||||||||||
| 17 | "0" |
rst_i2c |
|
||||||||||||||||||||||||||||
| 16 | "0" |
pio_mode |
|
||||||||||||||||||||||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||||||||||||||||||||||
| 10 - 4 | "0000000" |
sadr |
|
||||||||||||||||||||||||||||
| 3 - 1 | "000" |
mode |
|
||||||||||||||||||||||||||||
| 0 | "0" |
en_i2c |
|
||||||||||||||||||||||||||||
| i2c_scr |
|
||||||||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400004 Address@com_i2c1 : 0x06400044 Address@app_i2c0 : 0x40080384 Address@app_i2c1 : 0x400803c4 Address@mot_i2c0 : 0x49200384 Address@mot_i2c1 : 0x492003c4 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 | "0" |
autoreset_ac_start |
|
||||||
| 19 | 0 |
- |
reserved | ||||||
| 18 | "0" |
ac_gcall |
|
||||||
| 17 | "0" |
ac_start |
|
||||||
| 16 | "0" |
ac_srx |
|
||||||
| 15 - 11 | 0 |
- |
reserved | ||||||
| 10 | "0" |
sid10 |
|
||||||
| 9 - 0 | 0x0 |
sid |
|
||||||
| i2c_cmd |
|
||||||||||||||||||||||||||||
| R/W |
0x0000000e |
Address@com_i2c0 : 0x06400008 Address@com_i2c1 : 0x06400048 Address@app_i2c0 : 0x40080388 Address@app_i2c1 : 0x400803c8 Address@mot_i2c0 : 0x49200388 Address@mot_i2c1 : 0x492003c8 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | ||||||||||||||||||||||||||
| 27 - 20 | "00000000" |
acpollmax |
|
||||||||||||||||||||||||||
| 19 - 18 | 0 |
- |
reserved | ||||||||||||||||||||||||||
| 17 - 8 | 0x0 |
tsize |
|
||||||||||||||||||||||||||
| 7 - 4 | 0 |
- |
reserved | ||||||||||||||||||||||||||
| 3 - 1 | "111" |
cmd |
|
||||||||||||||||||||||||||
| 0 | "0" |
nwr |
|
||||||||||||||||||||||||||
| i2c_mdr |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x0640000c Address@com_i2c1 : 0x0640004c Address@app_i2c0 : 0x4008038c Address@app_i2c1 : 0x400803cc Address@mot_i2c0 : 0x4920038c Address@mot_i2c1 : 0x492003cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
mdata |
|
|
| i2c_sdr |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400010 Address@com_i2c1 : 0x06400050 Address@app_i2c0 : 0x40080390 Address@app_i2c1 : 0x400803d0 Address@mot_i2c0 : 0x49200390 Address@mot_i2c1 : 0x492003d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
sdata |
|
|
| i2c_mfifo_cr |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400014 Address@com_i2c1 : 0x06400054 Address@app_i2c0 : 0x40080394 Address@app_i2c1 : 0x400803d4 Address@mot_i2c0 : 0x49200394 Address@mot_i2c1 : 0x492003d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
mfifo_clr |
|
|
| 7 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
mfifo_wm |
|
|
| i2c_sfifo_cr |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400018 Address@com_i2c1 : 0x06400058 Address@app_i2c0 : 0x40080398 Address@app_i2c1 : 0x400803d8 Address@mot_i2c0 : 0x49200398 Address@mot_i2c1 : 0x492003d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sfifo_clr |
|
|
| 7 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
sfifo_wm |
|
|
| i2c_sr |
|
||||||||
| R/W |
0xc0110040 |
Address@com_i2c0 : 0x0640001c Address@com_i2c1 : 0x0640005c Address@app_i2c0 : 0x4008039c Address@app_i2c1 : 0x400803dc Address@mot_i2c0 : 0x4920039c Address@mot_i2c1 : 0x492003dc |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | - |
sda_state |
|
||||||
| 30 | - |
scl_state |
|
||||||
| 29 | 0 |
- |
reserved | ||||||
| 28 | "0" |
timeout |
|
||||||
| 27 | - |
sid10_aced |
|
||||||
| 26 | - |
gcall_aced |
|
||||||
| 25 | - |
nwr_aced |
|
||||||
| 24 | - |
last_ac |
|
||||||
| 23 | - |
slave_access |
|
||||||
| 22 | - |
started |
|
||||||
| 21 | - |
nwr |
|
||||||
| 20 | - |
bus_master |
|
||||||
| 19 | - |
sfifo_err_undr |
|
||||||
| 18 | - |
sfifo_err_ovfl |
|
||||||
| 17 | - |
sfifo_full |
|
||||||
| 16 | - |
sfifo_empty |
|
||||||
| 15 | 0 |
- |
reserved | ||||||
| 14 - 10 | - |
sfifo_level |
|
||||||
| 9 | - |
mfifo_err_undr |
|
||||||
| 8 | - |
mfifo_err_ovfl |
|
||||||
| 7 | - |
mfifo_full |
|
||||||
| 6 | - |
mfifo_empty |
|
||||||
| 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | - |
mfifo_level |
|
||||||
| i2c_irqmsk |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400020 Address@com_i2c1 : 0x06400060 Address@app_i2c0 : 0x400803a0 Address@app_i2c1 : 0x400803e0 Address@mot_i2c0 : 0x492003a0 Address@mot_i2c1 : 0x492003e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
sreq |
|
|
| 5 | "0" |
sfifo_req |
|
|
| 4 | "0" |
mfifo_req |
|
|
| 3 | "0" |
bus_busy |
|
|
| 2 | "0" |
fifo_err |
|
|
| 1 | "0" |
cmd_err |
|
|
| 0 | "0" |
cmd_ok |
|
|
| i2c_irqsr |
|
|||||||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x06400024 Address@com_i2c1 : 0x06400064 Address@app_i2c0 : 0x400803a4 Address@app_i2c1 : 0x400803e4 Address@mot_i2c0 : 0x492003a4 Address@mot_i2c1 : 0x492003e4 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |||||
| 6 | "0" |
sreq |
|
|||||
| 5 | "0" |
sfifo_req |
|
|||||
| 4 | "0" |
mfifo_req |
|
|||||
| 3 | "0" |
bus_busy |
|
|||||
| 2 | "0" |
fifo_err |
|
|||||
| 1 | "0" |
cmd_err |
|
|||||
| 0 | "0" |
cmd_ok |
|
|||||
| i2c_irqmsked |
|
|||
| R |
Address@com_i2c0 : 0x06400028 Address@com_i2c1 : 0x06400068 Address@app_i2c0 : 0x400803a8 Address@app_i2c1 : 0x400803e8 Address@mot_i2c0 : 0x492003a8 Address@mot_i2c1 : 0x492003e8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||
| 6 | sreq |
|
||
| 5 | sfifo_req |
|
||
| 4 | mfifo_req |
|
||
| 3 | bus_busy |
|
||
| 2 | fifo_err |
|
||
| 1 | cmd_err |
|
||
| 0 | cmd_ok |
|
||
| i2c_dmacr |
|
|||
| R/W |
0x00000000 |
Address@com_i2c0 : 0x0640002c Address@com_i2c1 : 0x0640006c Address@app_i2c0 : 0x400803ac Address@app_i2c1 : 0x400803ec Address@mot_i2c0 : 0x492003ac Address@mot_i2c1 : 0x492003ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdmab_en |
|
|
| 2 | "0" |
sdmas_en |
|
|
| 1 | "0" |
mdmab_en |
|
|
| 0 | "0" |
mdmas_en |
|
|
| i2c_pio |
|
|||||||
| R/W |
0x00000044 |
Address@com_i2c0 : 0x06400030 Address@com_i2c1 : 0x06400070 Address@app_i2c0 : 0x400803b0 Address@app_i2c1 : 0x400803f0 Address@mot_i2c0 : 0x492003b0 Address@mot_i2c1 : 0x492003f0 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |||||
| 6 | - |
sda_in_ro |
|
|||||
| 5 | "0" |
sda_oe |
|
|||||
| 4 | "0" |
sda_out |
|
|||||
| 3 | 0 |
- |
reserved | |||||
| 2 | - |
scl_in_ro |
|
|||||
| 1 | "0" |
scl_oe |
|
|||||
| 0 | "0" |
scl_out |
|
|||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | uartdr |
| 1 | 4 | R/W | uartrsr |
| 2 | 8 | R/W | uartlcr_h |
| 3 | c | R/W | uartlcr_m |
| 4 | 10 | R/W | uartlcr_l |
| 5 | 14 | R/W | uartcr |
| 6 | 18 | R | uartfr |
| 7 | 1c | R/W | uartiir |
| 8 | 20 | R/W | uartilpr |
| 9 | 24 | R/W | uartrts |
| a | 28 | R/W | uartforerun |
| b | 2c | R/W | uarttrail |
| c | 30 | R/W | uartdrvout |
| d | 34 | R/W | uartcr_2 |
| e | 38 | R/W | uartrxiflsel |
| f | 3c | R/W | uarttxiflsel |
| uartdr (NETX_UART%_DATA) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400100 Address@com_uart1 : 0x06400140 Address@app_uart0 : 0x40080300 Address@app_uart1 : 0x40080340 Address@mot_uart0 : 0x49200300 Address@mot_uart1 : 0x49200340 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
BE |
|
|
| 9 | "0" |
PE |
|
|
| 8 | "0" |
FE |
|
|
| 7 - 0 | "00000000" |
DATA |
|
|
| uartrsr (NETX_UART%_STAT) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400104 Address@com_uart1 : 0x06400144 Address@app_uart0 : 0x40080304 Address@app_uart1 : 0x40080344 Address@mot_uart0 : 0x49200304 Address@mot_uart1 : 0x49200344 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
OE |
|
|
| 2 | "0" |
BE |
|
|
| 1 | "0" |
PE |
|
|
| 0 | "0" |
FE |
|
|
| uartlcr_h (NETX_UART%_LINE_CTRL) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400108 Address@com_uart1 : 0x06400148 Address@app_uart0 : 0x40080308 Address@app_uart1 : 0x40080348 Address@mot_uart0 : 0x49200308 Address@mot_uart1 : 0x49200348 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 - 5 | "00" |
WLEN |
|
|
| 4 | "0" |
FEN |
|
|
| 3 | "0" |
STP2 |
|
|
| 2 | "0" |
EPS |
|
|
| 1 | "0" |
PEN |
|
|
| 0 | "0" |
BRK |
|
|
| uartlcr_m (NETX_UART%_BAUD_DIV_MSB) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x0640010c Address@com_uart1 : 0x0640014c Address@app_uart0 : 0x4008030c Address@app_uart1 : 0x4008034c Address@mot_uart0 : 0x4920030c Address@mot_uart1 : 0x4920034c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
BAUDDIVMS |
|
|
| uartlcr_l (NETX_UART%_BAUD_DIV_LSB) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400110 Address@com_uart1 : 0x06400150 Address@app_uart0 : 0x40080310 Address@app_uart1 : 0x40080350 Address@mot_uart0 : 0x49200310 Address@mot_uart1 : 0x49200350 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
BAUDDIVLS |
|
|
| uartcr (NETX_UART%_CTRL) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400114 Address@com_uart1 : 0x06400154 Address@app_uart0 : 0x40080314 Address@app_uart1 : 0x40080354 Address@mot_uart0 : 0x49200314 Address@mot_uart1 : 0x49200354 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
TX_RX_LOOP |
|
|
| 7 | "0" |
LBE |
|
|
| 6 | "0" |
RTIE |
|
|
| 5 | "0" |
TIE |
|
|
| 4 | "0" |
RIE |
|
|
| 3 | "0" |
MSIE |
|
|
| 2 | "0" |
SIRLP |
|
|
| 1 | "0" |
SIREN |
|
|
| 0 | "0" |
uartEN |
|
|
| uartfr (NETX_UART%_FLAG) |
|
|||
| R |
Address@com_uart0 : 0x06400118 Address@com_uart1 : 0x06400158 Address@app_uart0 : 0x40080318 Address@app_uart1 : 0x40080358 Address@mot_uart0 : 0x49200318 Address@mot_uart1 : 0x49200358 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | TXFE |
|
||
| 6 | RXFF |
|
||
| 5 | TXFF |
|
||
| 4 | RXFE |
|
||
| 3 | BUSY |
|
||
| 2 | DCD |
|
||
| 1 | DSR |
|
||
| 0 | CTS |
|
||
| uartiir (NETX_UART%_INT_ID) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x0640011c Address@com_uart1 : 0x0640015c Address@app_uart0 : 0x4008031c Address@app_uart1 : 0x4008035c Address@mot_uart0 : 0x4920031c Address@mot_uart1 : 0x4920035c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
RTIS |
|
|
| 2 | "0" |
TIS |
|
|
| 1 | "0" |
RIS |
|
|
| 0 | "0" |
MIS |
|
|
| uartilpr (NETX_UART%_IRDA_LO_PWR_CNTR) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400120 Address@com_uart1 : 0x06400160 Address@app_uart0 : 0x40080320 Address@app_uart1 : 0x40080360 Address@mot_uart0 : 0x49200320 Address@mot_uart1 : 0x49200360 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
ILPDVSR |
|
|
| uartrts (NETX_UART%_RTS_CTRL) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400124 Address@com_uart1 : 0x06400164 Address@app_uart0 : 0x40080324 Address@app_uart1 : 0x40080364 Address@mot_uart0 : 0x49200324 Address@mot_uart1 : 0x49200364 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
STICK |
|
|
| 6 | "0" |
CTS_pol |
|
|
| 5 | "0" |
CTS_ctr |
|
|
| 4 | "0" |
RTS_pol |
|
|
| 3 | "0" |
MOD2 |
|
|
| 2 | "0" |
COUNT |
|
|
| 1 | "0" |
RTS |
|
|
| 0 | "0" |
AUTO |
|
|
| uartforerun (NETX_UART%_RTS_LEAD_CYC) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400128 Address@com_uart1 : 0x06400168 Address@app_uart0 : 0x40080328 Address@app_uart1 : 0x40080368 Address@mot_uart0 : 0x49200328 Address@mot_uart1 : 0x49200368 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
FORERUN |
|
|
| uarttrail (NETX_UART%_RTS_TRAIL_CYC) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x0640012c Address@com_uart1 : 0x0640016c Address@app_uart0 : 0x4008032c Address@app_uart1 : 0x4008036c Address@mot_uart0 : 0x4920032c Address@mot_uart1 : 0x4920036c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
TRAIL |
|
|
| uartdrvout (NETX_UART%_OUT_DRV_EN) |
|
|||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400130 Address@com_uart1 : 0x06400170 Address@app_uart0 : 0x40080330 Address@app_uart1 : 0x40080370 Address@mot_uart0 : 0x49200330 Address@mot_uart1 : 0x49200370 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | - |
cts_in_ro |
|
|
| 4 | - |
rx_in_ro |
|
|
| 3 | "0" |
rts_out |
|
|
| 2 | "0" |
tx_out |
|
|
| 1 | "0" |
DRVRTS |
|
|
| 0 | "0" |
DRVTX |
|
|
| uartcr_2 (NETX_UART%_BAUD_MODE_CTRL) |
|
|||||||
| R/W |
0x00000000 |
Address@com_uart0 : 0x06400134 Address@com_uart1 : 0x06400174 Address@app_uart0 : 0x40080334 Address@app_uart1 : 0x40080374 Address@mot_uart0 : 0x49200334 Address@mot_uart1 : 0x49200374 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |||||
| 4 | "0" |
pio_mode |
|
|||||
| 3 - 2 | 0 |
- |
reserved | |||||
| 1 | "0" |
oversampling_8x |
|
|||||
| 0 | "0" |
Baud_Rate_Mode |
|
|||||
| uartrxiflsel (NETX_UART%_RX_FIFO_IRQ_LVL) |
|
|||
| R/W |
0x00000008 |
Address@com_uart0 : 0x06400138 Address@com_uart1 : 0x06400178 Address@app_uart0 : 0x40080338 Address@app_uart1 : 0x40080378 Address@mot_uart0 : 0x49200338 Address@mot_uart1 : 0x49200378 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
RXDMA |
|
|
| 4 - 0 | "01000" |
RXIFLSEL |
|
|
| uarttxiflsel (NETX_UART%_TX_FIFO_IRQ_LVL) |
|
|||
| R/W |
0x00000008 |
Address@com_uart0 : 0x0640013c Address@com_uart1 : 0x0640017c Address@app_uart0 : 0x4008033c Address@app_uart1 : 0x4008037c Address@mot_uart0 : 0x4920033c Address@mot_uart1 : 0x4920037c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
TXDMA |
|
|
| 4 - 0 | "01000" |
TXIFLSEL |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gpio_cfg0 |
| 1 | 4 | R/W | gpio_cfg1 |
| 2 | 8 | R/W | gpio_cfg2 |
| 3 | c | R/W | gpio_cfg3 |
| 4 | 10 | R/W | gpio_tc0 |
| 5 | 14 | R/W | gpio_tc1 |
| 6 | 18 | R/W | gpio_tc2 |
| 7 | 1c | R/W | gpio_tc3 |
| 8 | 20 | R/W | gpio_counter0_ctrl |
| 9 | 24 | R/W | gpio_counter1_ctrl |
| a | 28 | R/W | gpio_counter2_ctrl |
| b | 2c | R/W | gpio_counter3_ctrl |
| c | 30 | R/W | gpio_counter0_max |
| d | 34 | R/W | gpio_counter1_max |
| e | 38 | R/W | gpio_counter2_max |
| f | 3c | R/W | gpio_counter3_max |
| 10 | 40 | R/W | gpio_counter0_cnt |
| 11 | 44 | R/W | gpio_counter1_cnt |
| 12 | 48 | R/W | gpio_counter2_cnt |
| 13 | 4c | R/W | gpio_counter3_cnt |
| 14 | 50 | R/W | gpio_line |
| 15 | 54 | R | gpio_in |
| 16 | 58 | R/W | gpio_irq_raw |
| 17 | 5c | R | gpio_irq_masked |
| 18 | 60 | R/W | gpio_irq_mask_set |
| 19 | 64 | R/W | gpio_irq_mask_rst |
| 1a | 68 | R/W | gpio_cnt_irq_raw |
| 1b | 6c | R | gpio_cnt_irq_masked |
| 1c | 70 | R/W | gpio_cnt_irq_mask_set |
| 1d | 74 | R/W | gpio_cnt_irq_mask_rst |
| 1e-1f | 78-7c | - | reserved |
| gpio_cfg0 |
|
|||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x06400180 |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |||||||||||||||||||||
| 13 | "0" |
blink_once |
|
|||||||||||||||||||||
| 12 - 8 | "00000" |
blink_len |
|
|||||||||||||||||||||
| 7 - 5 | "000" |
count_ref |
|
|||||||||||||||||||||
| 4 | "0" |
inv |
|
|||||||||||||||||||||
| 3 - 0 | "0000" |
mode |
|
|||||||||||||||||||||
| gpio_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x06400184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
blink_once |
|
|
| 12 - 8 | "00000" |
blink_len |
|
|
| 7 - 5 | "000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x06400188 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
blink_once |
|
|
| 12 - 8 | "00000" |
blink_len |
|
|
| 7 - 5 | "000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_cfg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x0640018c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
blink_once |
|
|
| 12 - 8 | "00000" |
blink_len |
|
|
| 7 - 5 | "000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_tc0 |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x06400190 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||||
| gpio_tc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x06400194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_tc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x06400198 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_tc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x0640019c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter0_ctrl |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x064001a0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |||||||||
| 8 - 7 | "00" |
gpio_ref |
|
|||||||||
| 6 - 5 | "00" |
event_act |
|
|||||||||
| 4 | "0" |
once |
|
|||||||||
| 3 | "0" |
sel_event |
|
|||||||||
| 2 | "0" |
irq_en |
|
|||||||||
| 1 | "0" |
sym_nasym |
|
|||||||||
| 0 | "0" |
run |
|
|||||||||
| gpio_counter1_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x064001a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 - 7 | "00" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_counter2_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x064001a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 - 7 | "00" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_counter3_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x064001ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 - 7 | "00" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_counter0_max |
|
|||
| R/W |
0x00000000 |
Address : 0x064001b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter1_max |
|
|||
| R/W |
0x00000000 |
Address : 0x064001b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter2_max |
|
|||
| R/W |
0x00000000 |
Address : 0x064001b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter3_max |
|
|||
| R/W |
0x00000000 |
Address : 0x064001bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter0_cnt |
|
|||
| R/W |
0x00000000 |
Address : 0x064001c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter1_cnt |
|
|||
| R/W |
0x00000000 |
Address : 0x064001c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter2_cnt |
|
|||
| R/W |
0x00000000 |
Address : 0x064001c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_counter3_cnt |
|
|||
| R/W |
0x00000000 |
Address : 0x064001cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_line |
|
|||
| R/W |
0x00000000 |
Address : 0x064001d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
val |
|
|
| gpio_in |
|
|||
| R |
Address : 0x064001d4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 - 0 | val |
|
||
| gpio_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x064001d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
gpio3 |
|
|
| 2 | "0" |
gpio2 |
|
|
| 1 | "0" |
gpio1 |
|
|
| 0 | "0" |
gpio0 |
|
|
| gpio_irq_masked |
|
|||
| R |
Address : 0x064001dc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | gpio3 |
|
||
| 2 | gpio2 |
|
||
| 1 | gpio1 |
|
||
| 0 | gpio0 |
|
||
| gpio_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x064001e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
gpio3 |
|
|
| 2 | "0" |
gpio2 |
|
|
| 1 | "0" |
gpio1 |
|
|
| 0 | "0" |
gpio0 |
|
|
| gpio_irq_mask_rst |
|
|||
| R/W |
0x00000000 |
Address : 0x064001e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
gpio3 |
|
|
| 2 | "0" |
gpio2 |
|
|
| 1 | "0" |
gpio1 |
|
|
| 0 | "0" |
gpio0 |
|
|
| gpio_cnt_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x064001e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| gpio_cnt_irq_masked |
|
|||
| R |
Address : 0x064001ec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | cnt3 |
|
||
| 2 | cnt2 |
|
||
| 1 | cnt1 |
|
||
| 0 | cnt0 |
|
||
| gpio_cnt_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x064001f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| gpio_cnt_irq_mask_rst |
|
|||
| R/W |
0x00000000 |
Address : 0x064001f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | pio_in |
| 1 | 4 | R/W | pio_out |
| 2 | 8 | R/W | pio_oe |
| 3 | c | R/W | pio_in_inv |
| 4 | 10 | R/W | pio_edge_event |
| 5 | 14 | R/W | pio_irq_raw |
| 6 | 18 | R/W | pio_irq_masked |
| 7 | 1c | R/W | pio_irq_mask_set |
| 8 | 20 | R/W | pio_irq_mask_rst |
| 9-3f | 24-fc | - | reserved |
| pio_in |
|
|||
| R |
Address@com_pio : 0x06400200 Address@app_pio : 0x40080600 Address@mot_pio : 0x49200600 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| pio_out |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x06400204 Address@app_pio : 0x40080604 Address@mot_pio : 0x49200604 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
val_wm |
|
|
| 15 - 0 | 0x0 |
val |
|
|
| pio_oe |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x06400208 Address@app_pio : 0x40080608 Address@mot_pio : 0x49200608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
val_wm |
|
|
| 15 - 0 | 0x0 |
val |
|
|
| pio_in_inv |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x0640020c Address@app_pio : 0x4008060c Address@mot_pio : 0x4920060c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| pio_edge_event |
|
|||||||
| R/W |
0x00000000 |
Address@com_pio : 0x06400210 Address@app_pio : 0x40080610 Address@mot_pio : 0x49200610 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
val_wm |
|
|||||
| 15 - 0 | 0x0 |
val |
|
|||||
| pio_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x06400214 Address@app_pio : 0x40080614 Address@mot_pio : 0x49200614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
pio15 |
|
|
| 14 | "0" |
pio14 |
|
|
| 13 | "0" |
pio13 |
|
|
| 12 | "0" |
pio12 |
|
|
| 11 | "0" |
pio11 |
|
|
| 10 | "0" |
pio10 |
|
|
| 9 | "0" |
pio9 |
|
|
| 8 | "0" |
pio8 |
|
|
| 7 | "0" |
pio7 |
|
|
| 6 | "0" |
pio6 |
|
|
| 5 | "0" |
pio5 |
|
|
| 4 | "0" |
pio4 |
|
|
| 3 | "0" |
pio3 |
|
|
| 2 | "0" |
pio2 |
|
|
| 1 | "0" |
pio1 |
|
|
| 0 | "0" |
pio0 |
|
|
| pio_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x06400218 Address@app_pio : 0x40080618 Address@mot_pio : 0x49200618 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
pio15 |
|
|
| 14 | "0" |
pio14 |
|
|
| 13 | "0" |
pio13 |
|
|
| 12 | "0" |
pio12 |
|
|
| 11 | "0" |
pio11 |
|
|
| 10 | "0" |
pio10 |
|
|
| 9 | "0" |
pio9 |
|
|
| 8 | "0" |
pio8 |
|
|
| 7 | "0" |
pio7 |
|
|
| 6 | "0" |
pio6 |
|
|
| 5 | "0" |
pio5 |
|
|
| 4 | "0" |
pio4 |
|
|
| 3 | "0" |
pio3 |
|
|
| 2 | "0" |
pio2 |
|
|
| 1 | "0" |
pio1 |
|
|
| 0 | "0" |
pio0 |
|
|
| pio_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@com_pio : 0x0640021c Address@app_pio : 0x4008061c Address@mot_pio : 0x4920061c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
pio15 |
|
|
| 14 | "0" |
pio14 |
|
|
| 13 | "0" |
pio13 |
|
|
| 12 | "0" |
pio12 |
|
|
| 11 | "0" |
pio11 |
|
|
| 10 | "0" |
pio10 |
|
|
| 9 | "0" |
pio9 |
|
|
| 8 | "0" |
pio8 |
|
|
| 7 | "0" |
pio7 |
|
|
| 6 | "0" |
pio6 |
|
|
| 5 | "0" |
pio5 |
|
|
| 4 | "0" |
pio4 |
|
|
| 3 | "0" |
pio3 |
|
|
| 2 | "0" |
pio2 |
|
|
| 1 | "0" |
pio1 |
|
|
| 0 | "0" |
pio0 |
|
|
| pio_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@com_pio : 0x06400220 Address@app_pio : 0x40080620 Address@mot_pio : 0x49200620 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
pio15 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
pio14 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
pio13 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
pio12 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
pio11 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
pio10 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
pio9 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
pio8 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
pio7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
pio6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
pio5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
pio3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
pio2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
pio1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
pio0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | blink_enable |
| 1 | 4 | R/W | blink_config0 |
| 2 | 8 | R/W | blink_seq0 |
| 3 | c | R/W | blink_config1 |
| 4 | 10 | R/W | blink_seq1 |
| 5 | 14 | R/W | blink_config2 |
| 6 | 18 | R/W | blink_seq2 |
| 7 | 1c | R/W | blink_config3 |
| 8 | 20 | R/W | blink_seq3 |
| 9 | 24 | R/W | blink_wdg_cfg |
| a | 28 | R/W | blink_wdg_trigger |
| b-f | 2c-3c | - | reserved |
| blink_enable |
|
|||
| R/W |
0x00000000 |
Address@com_blink : 0x06400300 Address@app_blink : 0x40080700 Address@mot_blink : 0x49200700 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
en3_wm |
|
|
| 18 | "0" |
en2_wm |
|
|
| 17 | "0" |
en1_wm |
|
|
| 16 | "0" |
en0_wm |
|
|
| 15 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
en3 |
|
|
| 2 | "0" |
en2 |
|
|
| 1 | "0" |
en1 |
|
|
| 0 | "0" |
en0 |
|
|
| blink_config0 |
|
|||||||||||
| R/W |
0x00000163 |
Address@com_blink : 0x06400304 Address@app_blink : 0x40080704 Address@mot_blink : 0x49200704 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||
| 12 - 8 | "00001" |
blink_len |
|
|||||||||
| 7 - 0 | "01100011" |
period |
|
|||||||||
| blink_seq0 |
|
|||
| R/W |
0x00000001 |
Address@com_blink : 0x06400308 Address@app_blink : 0x40080708 Address@mot_blink : 0x49200708 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x1 |
val |
|
|
| blink_config1 |
|
|||||||||||
| R/W |
0x00000163 |
Address@com_blink : 0x0640030c Address@app_blink : 0x4008070c Address@mot_blink : 0x4920070c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||
| 12 - 8 | "00001" |
blink_len |
|
|||||||||
| 7 - 0 | "01100011" |
period |
|
|||||||||
| blink_seq1 |
|
|||
| R/W |
0x00000001 |
Address@com_blink : 0x06400310 Address@app_blink : 0x40080710 Address@mot_blink : 0x49200710 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x1 |
val |
|
|
| blink_config2 |
|
|||||||||||
| R/W |
0x00000163 |
Address@com_blink : 0x06400314 Address@app_blink : 0x40080714 Address@mot_blink : 0x49200714 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||
| 12 - 8 | "00001" |
blink_len |
|
|||||||||
| 7 - 0 | "01100011" |
period |
|
|||||||||
| blink_seq2 |
|
|||
| R/W |
0x00000001 |
Address@com_blink : 0x06400318 Address@app_blink : 0x40080718 Address@mot_blink : 0x49200718 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x1 |
val |
|
|
| blink_config3 |
|
|||||||||||
| R/W |
0x00000163 |
Address@com_blink : 0x0640031c Address@app_blink : 0x4008071c Address@mot_blink : 0x4920071c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||
| 12 - 8 | "00001" |
blink_len |
|
|||||||||
| 7 - 0 | "01100011" |
period |
|
|||||||||
| blink_seq3 |
|
|||
| R/W |
0x00000001 |
Address@com_blink : 0x06400320 Address@app_blink : 0x40080720 Address@mot_blink : 0x49200720 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x1 |
val |
|
|
| blink_wdg_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_blink : 0x06400324 Address@app_blink : 0x40080724 Address@mot_blink : 0x49200724 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | ||||||||
| 28 | - |
wdg_timeout_status_ro |
|
||||||||
| 27 - 25 | 0 |
- |
reserved | ||||||||
| 24 - 16 | - |
wdg_cnt_ro |
|
||||||||
| 15 - 12 | 0 |
- |
reserved | ||||||||
| 11 | "0" |
fallback_led3 |
|
||||||||
| 10 | "0" |
fallback_led2 |
|
||||||||
| 9 | "0" |
fallback_led1 |
|
||||||||
| 8 | "0" |
fallback_led0 |
|
||||||||
| 7 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
wdg_timeout |
|
||||||||
| blink_wdg_trigger |
|
|||
| R/W |
0x00008c8c |
Address@com_blink : 0x06400328 Address@app_blink : 0x40080728 Address@mot_blink : 0x49200728 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "10001100" |
next_trigger |
|
|
| 7 - 0 | "10001100" |
trigger |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mixled_cfg |
| 1 | 4 | R/W | mixled_brightness_ch0_a |
| 2 | 8 | R/W | mixled_brightness_ch0_b |
| 3 | c | R/W | mixled_brightness_ch0_a_b |
| 4 | 10 | R/W | mixled_brightness_ch1_a |
| 5 | 14 | R/W | mixled_brightness_ch1_b |
| 6 | 18 | R/W | mixled_brightness_ch1_a_b |
| 7 | 1c | - | reserved |
| mixled_cfg |
|
||||||||||||
| R/W |
0x00000000 |
Address@com_blink_mixled : 0x06400340 Address@com_gxc_mixled0 : 0x06400360 Address@com_gxc_mixled1 : 0x06400380 Address@app_blink_mixled : 0x40080740 Address@mot_blink_mixled : 0x49200740 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||||||||
| 2 | "0" |
simple_pwm_pattern |
|
||||||||||
| 1 | "0" |
enable_1 |
|
||||||||||
| 0 | "0" |
enable_0 |
|
||||||||||
| mixled_brightness_ch0_a |
|
|||
| R/W |
0x00000010 |
Address@com_blink_mixled : 0x06400344 Address@com_gxc_mixled0 : 0x06400364 Address@com_gxc_mixled1 : 0x06400384 Address@app_blink_mixled : 0x40080744 Address@mot_blink_mixled : 0x49200744 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "10000" |
val |
|
|
| mixled_brightness_ch0_b |
|
|||
| R/W |
0x00000010 |
Address@com_blink_mixled : 0x06400348 Address@com_gxc_mixled0 : 0x06400368 Address@com_gxc_mixled1 : 0x06400388 Address@app_blink_mixled : 0x40080748 Address@mot_blink_mixled : 0x49200748 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "10000" |
val |
|
|
| mixled_brightness_ch0_a_b |
|
|||
| R/W |
0x00000808 |
Address@com_blink_mixled : 0x0640034c Address@com_gxc_mixled0 : 0x0640036c Address@com_gxc_mixled1 : 0x0640038c Address@app_blink_mixled : 0x4008074c Address@mot_blink_mixled : 0x4920074c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 - 8 | "01000" |
led_b |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "01000" |
led_a |
|
|
| mixled_brightness_ch1_a |
|
|||
| R/W |
0x00000010 |
Address@com_blink_mixled : 0x06400350 Address@com_gxc_mixled0 : 0x06400370 Address@com_gxc_mixled1 : 0x06400390 Address@app_blink_mixled : 0x40080750 Address@mot_blink_mixled : 0x49200750 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "10000" |
val |
|
|
| mixled_brightness_ch1_b |
|
|||
| R/W |
0x00000010 |
Address@com_blink_mixled : 0x06400354 Address@com_gxc_mixled0 : 0x06400374 Address@com_gxc_mixled1 : 0x06400394 Address@app_blink_mixled : 0x40080754 Address@mot_blink_mixled : 0x49200754 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "10000" |
val |
|
|
| mixled_brightness_ch1_a_b |
|
|||
| R/W |
0x00000808 |
Address@com_blink_mixled : 0x06400358 Address@com_gxc_mixled0 : 0x06400378 Address@com_gxc_mixled1 : 0x06400398 Address@app_blink_mixled : 0x40080758 Address@mot_blink_mixled : 0x49200758 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 - 8 | "01000" |
led_b |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "01000" |
led_a |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mr_control |
| 1 | 4 | R | mr_status |
| 2-3 | 8-c | - | reserved |
| 4 | 10 | R/W | mr_an_adv |
| 5 | 14 | R | mr_an_lpa |
| 6 | 18 | R | mr_an_exp |
| 7-e | 1c-38 | - | reserved |
| f | 3c | R | mr_ext_status |
| 10 | 40 | R/W | h_cmd |
| 11 | 44 | R | h_evt |
| 12 | 48 | R | h_status |
| 13 | 4c | R/W | h_an_config |
| 14 | 50 | R/W | h_ibs_config |
| 15 | 54 | R/W | h_adapt_config |
| 16 | 58 | R/W | h_pcs_config |
| 17 | 5c | R/W | h_pma_special |
| 18 | 60 | R/W | h_bypass |
| 19 | 64 | R/W | h_cdr_config |
| 1a | 68 | R/W | h_cdr_config2 |
| 1b | 6c | R | h_cdr_status |
| 1c | 70 | R/W | h_clkgen_config |
| 1d | 74 | R/W | h_afe_cfg |
| 1e | 78 | R/W | h_cal |
| 1f | 7c | R/W | h_power |
| 20 | 80 | R/W | h_sd100_cfg |
| 21-3f | 84-fc | - | reserved |
| mr_control |
|
|||
| R/W |
0x00001800 |
Address@com_hsgmii0 : 0x06400400 Address@com_hsgmii1 : 0x06400500 Address@app_hsgmii : 0x40092000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
reset |
|
|
| 14 | "0" |
loopback |
|
|
| 13 | 0 |
- |
reserved | |
| 12 | "1" |
autoneg_enable |
|
|
| 11 | "1" |
power_down |
|
|
| 10 | 0 |
- |
reserved | |
| 9 | "0" |
restart_autoneg |
|
|
| 8 - 0 | 0 |
- |
reserved | |
| mr_status |
|
||||||
| R |
Address@com_hsgmii0 : 0x06400404 Address@com_hsgmii1 : 0x06400504 Address@app_hsgmii : 0x40092004 |
Bits | Name | Description | |||
|---|---|---|---|---|---|---|---|
| 31 - 16 | - |
reserved | |||||
| 15 | base100_t4 |
|
|||||
| 14 | base100_x_fd |
|
|||||
| 13 | base100_x_hd |
|
|||||
| 12 | base10_fd |
|
|||||
| 11 | base10_hd |
|
|||||
| 10 | base100_t2_fd |
|
|||||
| 9 | base100_t2_hd |
|
|||||
| 8 | extended_status |
|
|||||
| 7 | unidirectional_ability |
|
|||||
| 6 | mf_preamble_suppression |
|
|||||
| 5 | auto_neg_complete |
|
|||||
| 4 | remote_fault |
|
|||||
| 3 | link_status |
|
|||||
| 2 | - |
reserved | |||||
| 1 | jabber_detect |
|
|||||
| 0 | extended_capability |
|
|||||
| mr_an_adv |
|
|||
| R/W |
0x00004001 |
Address@com_hsgmii0 : 0x06400410 Address@com_hsgmii1 : 0x06400510 Address@app_hsgmii : 0x40092010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x4001 |
mr_adv_ability |
|
|
| mr_an_lpa |
|
|||
| R |
Address@com_hsgmii0 : 0x06400414 Address@com_hsgmii1 : 0x06400514 Address@app_hsgmii : 0x40092014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | mr_lp_adv_ability |
|
||
| mr_an_exp |
|
|||
| R |
Address@com_hsgmii0 : 0x06400418 Address@com_hsgmii1 : 0x06400518 Address@app_hsgmii : 0x40092018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | np |
|
||
| 1 | page |
|
||
| 0 | - |
reserved | ||
| mr_ext_status |
|
|||
| R |
Address@com_hsgmii0 : 0x0640043c Address@com_hsgmii1 : 0x0640053c Address@app_hsgmii : 0x4009203c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 | base1000_x_fd |
|
||
| 14 | base1000_x_hd |
|
||
| 13 | base1000_t_fd |
|
||
| 12 | base1000_t_hd |
|
||
| 11 - 0 | - |
reserved | ||
| h_cmd |
|
|||
| R/W |
0x00000000 |
Address@com_hsgmii0 : 0x06400440 Address@com_hsgmii1 : 0x06400540 Address@app_hsgmii : 0x40092040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
tx_idle_insert_k |
|
|
| 0 | "0" |
tx_realign |
|
|
| h_evt |
|
|||||||
| R |
Address@com_hsgmii0 : 0x06400444 Address@com_hsgmii1 : 0x06400544 Address@app_hsgmii : 0x40092044 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||||||
| 7 | tx_epd3 |
|
||||||
| 6 | tx_shrink |
|
||||||
| 5 | rx_adapt_sp_shift |
|
||||||
| 4 | tx_realign |
|
||||||
| 3 | com_det |
|
||||||
| 2 | lp_adv_ability_received |
|
||||||
| 1 | sync_status_fail |
|
||||||
| 0 | link_status_down |
|
||||||
| h_status |
|
|||
| R |
Address@com_hsgmii0 : 0x06400448 Address@com_hsgmii1 : 0x06400548 Address@app_hsgmii : 0x40092048 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 - 0 | tx_alignment |
|
||
| h_an_config |
|
|||
| R/W |
0x00000640 |
Address@com_hsgmii0 : 0x0640044c Address@com_hsgmii1 : 0x0640054c Address@app_hsgmii : 0x4009204c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x640 |
an_link_timer_duration |
|
|
| h_ibs_config |
|
||||||||
| R/W |
0x00000010 |
Address@com_hsgmii0 : 0x06400450 Address@com_hsgmii1 : 0x06400550 Address@app_hsgmii : 0x40092050 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | ||||||
| 10 | "0" |
tx_crs_mode |
|
||||||
| 9 | "0" |
tx_col_mode |
|
||||||
| 8 | "0" |
an_restart_ctrl |
|
||||||
| 7 | "0" |
an_adv_use_ibs |
|
||||||
| 6 - 5 | "00" |
mdef_ibs_speed |
|
||||||
| 4 | "1" |
mdef_ibs_duplex |
|
||||||
| 3 | "0" |
mdef_ibs_link_status |
|
||||||
| 2 | 0 |
- |
reserved | ||||||
| 1 - 0 | "00" |
ibs_src |
|
||||||
| h_adapt_config |
|
||||||||||
| R/W |
0x00003101 |
Address@com_hsgmii0 : 0x06400454 Address@com_hsgmii1 : 0x06400554 Address@app_hsgmii : 0x40092054 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | ||||||||
| 13 | "1" |
tx_adapt_enable |
|
||||||||
| 12 | "1" |
rx_adapt_enable |
|
||||||||
| 11 | "0" |
tx_adapt_nibble_flip |
|
||||||||
| 10 | "0" |
rx_adapt_nibble_flip |
|
||||||||
| 9 | "0" |
tx_adapt_nibble_preamble_repair |
|
||||||||
| 8 | "1" |
rx_cesup_odd_nibble |
|
||||||||
| 7 - 6 | "00" |
rx_cesup_mii |
|
||||||||
| 5 - 4 | "00" |
rx_cesup_gmii |
|
||||||||
| 3 | "0" |
rx_adapt_nibble_status |
|
||||||||
| 2 | 0 |
- |
reserved | ||||||||
| 1 - 0 | "01" |
tx_adapt_nibble_status |
|
||||||||
| h_pcs_config |
|
|||||||||||
| R/W |
0x00000041 |
Address@com_hsgmii0 : 0x06400458 Address@com_hsgmii1 : 0x06400558 Address@app_hsgmii : 0x40092058 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |||||||||
| 6 | "1" |
sd1000_val |
|
|||||||||
| 5 | "0" |
sd1000_src |
|
|||||||||
| 4 | "0" |
pcs100_sample_mid |
|
|||||||||
| 3 | "0" |
tx_shadow_cfg_msb |
|
|||||||||
| 2 | "0" |
rx_special_idle_sfd |
|
|||||||||
| 1 | "0" |
tx_special_idle_sfd |
|
|||||||||
| 0 | "1" |
en_cdet |
|
|||||||||
| h_pma_special |
|
||||||
| R/W |
0x001fe0f8 |
Address@com_hsgmii0 : 0x0640045c Address@com_hsgmii1 : 0x0640055c Address@app_hsgmii : 0x4009205c |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 | "0" |
tx_inv |
|
||||
| 30 | "0" |
tx_lsb_first |
|
||||
| 29 | "0" |
rx_inv |
|
||||
| 28 | "0" |
rx_lsb_first |
|
||||
| 27 - 21 | 0 |
- |
reserved | ||||
| 20 | "1" |
rx_comma_rev |
|
||||
| 19 - 10 | 0x3f8 |
rx_comma_mask |
|
||||
| 9 - 0 | 0xf8 |
rx_comma |
|
||||
| h_bypass |
|
||||||||
| R/W |
0x00000000 |
Address@com_hsgmii0 : 0x06400460 Address@com_hsgmii1 : 0x06400560 Address@app_hsgmii : 0x40092060 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 23 | 0x0 |
tx_enc_direct_kddn |
|
||||||
| 22 - 16 | 0 |
- |
reserved | ||||||
| 15 - 7 | 0x0 |
tx_enc_direct_kddp |
|
||||||
| 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
pcs100_tx_b5_direct |
|
||||||
| 4 | "0" |
pcs100_rx_b5_direct |
|
||||||
| 3 - 2 | "00" |
rx_bypass |
|
||||||
| 1 | "0" |
tx_tbi_direct |
|
||||||
| 0 | "0" |
tx_enc_direct |
|
||||||
| h_cdr_config |
|
|||
| R/W |
0x00400800 |
Address@com_hsgmii0 : 0x06400464 Address@com_hsgmii1 : 0x06400564 Address@app_hsgmii : 0x40092064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x40 |
cdr_coeff_i |
|
|
| 15 - 0 | 0x800 |
cdr_coeff_p |
|
|
| h_cdr_config2 |
|
|||
| R/W |
0x0000000b |
Address@com_hsgmii0 : 0x06400468 Address@com_hsgmii1 : 0x06400568 Address@app_hsgmii : 0x40092068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
phdet_lr_en |
|
|
| 3 | "1" |
phdet_hr_en |
|
|
| 2 - 0 | "011" |
cdr_integ_limit |
|
|
| h_cdr_status | ||||
| R |
Address@com_hsgmii0 : 0x0640046c Address@com_hsgmii1 : 0x0640056c Address@app_hsgmii : 0x4009206c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | phsel_inc_sum |
|
||
| 15 - 0 | phsel_dec_sum |
|
||
| h_clkgen_config |
|
|||
| R/W |
0x00000004 |
Address@com_hsgmii0 : 0x06400470 Address@com_hsgmii1 : 0x06400570 Address@app_hsgmii : 0x40092070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0100" |
pll_fd |
|
|
| h_afe_cfg |
|
||||||||
| R/W |
0x00000000 |
Address@com_hsgmii0 : 0x06400474 Address@com_hsgmii1 : 0x06400574 Address@app_hsgmii : 0x40092074 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | ||||||
| 7 | "0" |
tx_term_enable |
|
||||||
| 6 - 3 | "0000" |
d_vcm |
|
||||||
| 2 | "0" |
rx_term_enable |
|
||||||
| 1 | "0" |
d_hyst_off |
|
||||||
| 0 | "0" |
d_cmr_on |
|
||||||
| h_cal |
|
||||||||||||||||||||
| R/W |
0x00004000 |
Address@com_hsgmii0 : 0x06400478 Address@com_hsgmii1 : 0x06400578 Address@app_hsgmii : 0x40092078 |
Bits | Reset value | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 23 | 0 |
- |
reserved | ||||||||||||||||||
| 22 - 19 | "0000" |
d_iout |
|
||||||||||||||||||
| 18 - 17 | "00" |
d_slew |
|
||||||||||||||||||
| 16 - 14 | "001" |
clkgen_tx_dll_fd |
|
||||||||||||||||||
| 13 - 11 | "000" |
d_dll_div |
|
||||||||||||||||||
| 10 - 6 | "00000" |
termination_rx |
|
||||||||||||||||||
| 5 - 1 | "00000" |
termination_tx |
|
||||||||||||||||||
| 0 | "0" |
clkgen_pll_vregh |
|
||||||||||||||||||
| h_power |
|
||||||||
| R/W |
0x00000000 |
Address@com_hsgmii0 : 0x0640047c Address@com_hsgmii1 : 0x0640057c Address@app_hsgmii : 0x4009207c |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | ||||||
| 6 | "0" |
pcs_sel100 |
|
||||||
| 5 | "0" |
pcs_enable |
|
||||||
| 4 | "0" |
rx_pma_nres |
|
||||||
| 3 | "0" |
tx_pma_nres |
|
||||||
| 2 | "0" |
pll_on |
|
||||||
| 1 | "0" |
d_comp_on |
|
||||||
| 0 | "0" |
d_tx_on |
|
||||||
| h_sd100_cfg |
|
|||||||||||
| R/W |
0x80000400 |
Address@com_hsgmii0 : 0x06400480 Address@com_hsgmii1 : 0x06400580 Address@app_hsgmii : 0x40092080 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0x4000 |
link_status_time |
|
|||||||||
| 16 - 2 | 0x100 |
sd_off_time |
|
|||||||||
| 1 - 0 | "00" |
sd_src |
|
|||||||||
| xspi_cr |
|
|||||||||||||||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400600 Address@xspi_evm : 0x40020000 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
reset |
|
|||||||||||||
| 30 - 6 | 0 |
- |
reserved | |||||||||||||
| 5 | "0" |
intn_polarity |
|
|||||||||||||
| 4 | "0" |
clk_monitor_enable |
|
|||||||||||||
| 3 - 2 | "00" |
xspi_mode |
|
|||||||||||||
| 1 | 0 |
- |
reserved | |||||||||||||
| 0 | "0" |
xspi_en |
|
|||||||||||||
| xspi_clk_cr0 |
|
||||||||||||||||||
| R/W |
0x000000ff |
Address@com_xspi : 0x06400604 Address@xspi_evm : 0x40020004 |
Bits | Reset value | Name | Description | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | ||||||||||||||||
| 8 | "0" |
clk_tx_en |
|
||||||||||||||||
| 7 - 0 | "11111111" |
clk_tx_div_val |
|
||||||||||||||||
| xspi_clk_cr1 |
|
||||||||||||||||
| R/W |
0x000000ff |
Address@com_xspi : 0x06400608 Address@xspi_evm : 0x40020008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | ||||||||||||||
| 8 | "0" |
clk_tx_en |
|
||||||||||||||
| 7 - 0 | "11111111" |
clk_tx_div_val |
|
||||||||||||||
| xspi_dll_cr0 |
|
||||||||
| R/W |
0x00364040 |
Address@com_xspi : 0x0640060c Address@xspi_evm : 0x4002000c |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | ||||||
| 25 | "0" |
clk_rx_delay_by |
|
||||||
| 24 | "0" |
clk_tx_delay_by |
|
||||||
| 23 | 0 |
- |
reserved | ||||||
| 22 - 20 | "011" |
phase_dly_value |
|
||||||
| 19 | 0 |
- |
reserved | ||||||
| 18 - 16 | "110" |
starting_value |
|
||||||
| 15 - 8 | "01000000" |
clk_rx_delay |
|
||||||
| 7 - 0 | "01000000" |
clk_tx_delay |
|
||||||
| xspi_dll_cr1 |
|
||||||||
| R/W |
0x00364040 |
Address@com_xspi : 0x06400610 Address@xspi_evm : 0x40020010 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | ||||||
| 25 | "0" |
clk_rx_delay_by |
|
||||||
| 24 | "0" |
clk_tx_delay_by |
|
||||||
| 23 | 0 |
- |
reserved | ||||||
| 22 - 20 | "011" |
phase_dly_value |
|
||||||
| 19 | 0 |
- |
reserved | ||||||
| 18 - 16 | "110" |
starting_value |
|
||||||
| 15 - 8 | "01000000" |
clk_rx_delay |
|
||||||
| 7 - 0 | "01000000" |
clk_tx_delay |
|
||||||
| xspi_dll_cr2 |
|
||||||||
| R/W |
0x31052710 |
Address@com_xspi : 0x06400614 Address@xspi_evm : 0x40020014 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
resync_dll |
|
||||||
| 30 | "0" |
disable_resync |
|
||||||
| 29 - 28 | "11" |
toggle_en |
|
||||||
| 27 - 24 | "0001" |
resync_delay |
|
||||||
| 23 - 16 | "00000101" |
delay_tolerance |
|
||||||
| 15 - 14 | 0 |
- |
reserved | ||||||
| 13 - 0 | 0x2710 |
resync_period |
|
||||||
| xspi_csn_addr_map |
|
||||||||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400618 Address@xspi_evm : 0x40020018 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
en |
|
||||||
| 30 - 28 | 0 |
- |
reserved | ||||||
| 27 - 0 | 0x0 |
boundary |
|
||||||
| xspi_sr |
|
|||||||||||||||
| R |
Address@com_xspi : 0x0640061c Address@xspi_evm : 0x4002001c |
Bits | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | csn1_dll_resync |
|
||||||||||||||
| 30 - 23 | csn1_dll_lock_value |
|
||||||||||||||
| 22 - 21 | csn1_dll_lock_mode |
|
||||||||||||||
| 20 | csn1_dll_lc_skipped |
|
||||||||||||||
| 19 | csn1_dll_locked |
|
||||||||||||||
| 18 | csn0_dll_resync |
|
||||||||||||||
| 17 - 10 | csn0_dll_lock_value |
|
||||||||||||||
| 9 - 8 | csn0_dll_lock_mode |
|
||||||||||||||
| 7 | csn0_dll_lc_skipped |
|
||||||||||||||
| 6 | csn0_dll_locked |
|
||||||||||||||
| 5 | clk_rx_tx_drifted |
|
||||||||||||||
| 4 | clk_rx_too_fast |
|
||||||||||||||
| 3 | clk_rx_too_slow |
|
||||||||||||||
| 2 | axi_core_busy |
|
||||||||||||||
| 1 | io_fifo_controller_busy |
|
||||||||||||||
| 0 | io_controller_busy |
|
||||||||||||||
| xspi_fsr |
|
|||
| R |
Address@com_xspi : 0x06400620 Address@xspi_evm : 0x40020020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||
| 21 | io_rx_fifo_empty |
|
||
| 20 | io_rx_fifo_full |
|
||
| 19 | io_rx_info_fifo_empty |
|
||
| 18 | io_rx_info_fifo_full |
|
||
| 17 | io_tx_fifo_empty |
|
||
| 16 | io_tx_fifo_full |
|
||
| 15 | mm_rx_info_fifo_full |
|
||
| 14 | mm_rx_info_fifo_empty |
|
||
| 13 | mm_ar_info_fifo_full |
|
||
| 12 | mm_ar_info_fifo_empty |
|
||
| 11 | mm_ax_fifo_full |
|
||
| 10 | mm_ax_fifo_empty |
|
||
| 9 | pm_rx_fifo_full |
|
||
| 8 | pm_rx_fifo_empty |
|
||
| 7 | sys_rx_fifo_overflow |
|
||
| 6 | sys_rx_fifo_underrun |
|
||
| 5 | sys_rx_fifo_full |
|
||
| 4 | sys_rx_fifo_empty |
|
||
| 3 | sys_tx_fifo_overflow |
|
||
| 2 | sys_tx_fifo_underrun |
|
||
| 1 | sys_tx_fifo_full |
|
||
| 0 | sys_tx_fifo_empty |
|
||
| xspi_fcr |
|
||||||||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400624 Address@xspi_evm : 0x40020024 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
clear_axi_fifos |
|
||||||
| 1 | "0" |
clear_sys_fifos |
|
||||||
| 0 | "0" |
clear_io_fifos |
|
||||||
| xspi_dvr0 |
|
||||||||
| R/W |
0x06000000 |
Address@com_xspi : 0x06400628 Address@xspi_evm : 0x40020028 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||
| 30 | "0" |
ca_en |
|
||||||
| 29 | "0" |
ial_delay_en |
|
||||||
| 28 | "0" |
ial_en |
|
||||||
| 27 | "0" |
payload_en |
|
||||||
| 26 - 25 | "11" |
csn_out |
|
||||||
| 24 | "0" |
ds_out |
|
||||||
| 23 - 16 | "00000000" |
d_out |
|
||||||
| 15 - 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
ds_oe |
|
||||||
| 7 - 0 | "00000000" |
d_oe |
|
||||||
| xspi_dvr1 |
|
||||||||
| R/W |
0x06000000 |
Address@com_xspi : 0x0640062c Address@xspi_evm : 0x4002002c |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||
| 30 | "0" |
ca_en |
|
||||||
| 29 | "0" |
ial_delay_en |
|
||||||
| 28 | "0" |
ial_en |
|
||||||
| 27 | "0" |
payload_en |
|
||||||
| 26 - 25 | "11" |
csn_out |
|
||||||
| 24 | "0" |
ds_out |
|
||||||
| 23 - 16 | "00000000" |
d_out |
|
||||||
| 15 - 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
ds_oe |
|
||||||
| 7 - 0 | "00000000" |
d_oe |
|
||||||
| xspi_tcr0 |
|
||||||||||||||
| R/W |
0x00002220 |
Address@com_xspi : 0x06400630 Address@xspi_evm : 0x40020030 |
Bits | Reset value | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||||||||
| 30 | "0" |
rx_additional_edge |
|
||||||||||||
| 29 | "0" |
rx_sdr_edge |
|
||||||||||||
| 28 | "0" |
ca_ds_en |
|
||||||||||||
| 27 - 26 | "00" |
switch_off_delay |
|
||||||||||||
| 25 - 24 | "00" |
switch_on_delay |
|
||||||||||||
| 23 | 0 |
- |
reserved | ||||||||||||
| 22 - 20 | "000" |
address_bytes_used |
|
||||||||||||
| 19 - 18 | 0 |
- |
reserved | ||||||||||||
| 17 | "0" |
pm_continue |
|
||||||||||||
| 16 | "0" |
pm_stall_possible |
|
||||||||||||
| 15 - 14 | 0 |
- |
reserved | ||||||||||||
| 13 | "1" |
tx_ds_pol |
|
||||||||||||
| 12 | "0" |
tx_ds_en |
|
||||||||||||
| 11 - 8 | "0010" |
rx_ds_off_delay |
|
||||||||||||
| 7 - 4 | "0010" |
rx_ds_on_delay |
|
||||||||||||
| 3 | "0" |
rx_ds_en |
|
||||||||||||
| 2 | "0" |
rx_ddr |
|
||||||||||||
| 1 - 0 | "00" |
rx_bit_width |
|
||||||||||||
| xspi_tcr1 |
|
||||||||||||||
| R/W |
0x05002220 |
Address@com_xspi : 0x06400634 Address@xspi_evm : 0x40020034 |
Bits | Reset value | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||||||||
| 30 | "0" |
rx_additional_edge |
|
||||||||||||
| 29 | "0" |
rx_sdr_edge |
|
||||||||||||
| 28 | "0" |
ca_ds_en |
|
||||||||||||
| 27 - 26 | "01" |
switch_off_delay |
|
||||||||||||
| 25 - 24 | "01" |
switch_on_delay |
|
||||||||||||
| 23 | 0 |
- |
reserved | ||||||||||||
| 22 - 20 | "000" |
address_bytes_used |
|
||||||||||||
| 19 - 18 | 0 |
- |
reserved | ||||||||||||
| 17 | "0" |
pm_continue |
|
||||||||||||
| 16 | "0" |
pm_stall_possible |
|
||||||||||||
| 15 - 14 | 0 |
- |
reserved | ||||||||||||
| 13 | "1" |
tx_ds_pol |
|
||||||||||||
| 12 | "0" |
tx_ds_en |
|
||||||||||||
| 11 - 8 | "0010" |
rx_ds_off_delay |
|
||||||||||||
| 7 - 4 | "0010" |
rx_ds_on_delay |
|
||||||||||||
| 3 | "0" |
rx_ds_en |
|
||||||||||||
| 2 | "0" |
rx_ddr |
|
||||||||||||
| 1 - 0 | "00" |
rx_bit_width |
|
||||||||||||
| xspi_tcr2 |
|
||||||||||||
| R/W |
0x00000030 |
Address@com_xspi : 0x06400638 Address@xspi_evm : 0x40020038 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | ||||||||||
| 21 | "0" |
pm_rx_capture_all |
|
||||||||||
| 20 | "0" |
pm_csn_idx |
|
||||||||||
| 19 - 17 | 0 |
- |
reserved | ||||||||||
| 16 | "0" |
pm_skip_ial |
|
||||||||||
| 15 - 13 | 0 |
- |
reserved | ||||||||||
| 12 - 8 | "00000" |
pm_ca_length |
|
||||||||||
| 7 - 6 | 0 |
- |
reserved | ||||||||||
| 5 - 4 | "11" |
pm_transfer_type |
|
||||||||||
| 3 | "0" |
end_transfer |
|
||||||||||
| 2 | 0 |
- |
reserved | ||||||||||
| 1 | "0" |
pm_auto_finish |
|
||||||||||
| 0 | "0" |
pm_start_transfer |
|
||||||||||
| xspi_tlr |
|
||||||||||||
| R/W |
0x00000000 |
Address@com_xspi : 0x0640063c Address@xspi_evm : 0x4002003c |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
transfer_length |
|
||||||||||
| xspi_ial0 |
|
|||||||
| W |
0x06000000 |
Address@com_xspi : 0x06400640 Address@xspi_evm : 0x40020040 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |||||
| 27 - 26 | "01" |
ds_sample_delay |
|
|||||
| 25 | "1" |
ds_pol |
|
|||||
| 24 | "0" |
dynamic |
|
|||||
| 23 - 16 | "00000000" |
delay |
|
|||||
| 15 - 0 | 0x0 |
ial |
|
|||||
| xspi_ial1 |
|
|||||||
| W |
0x06000000 |
Address@com_xspi : 0x06400644 Address@xspi_evm : 0x40020044 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |||||
| 27 - 26 | "01" |
ds_sample_delay |
|
|||||
| 25 | "1" |
ds_pol |
|
|||||
| 24 | "0" |
dynamic |
|
|||||
| 23 - 16 | "00000000" |
delay |
|
|||||
| 15 - 0 | 0x0 |
ial |
|
|||||
| xspi_ial2 |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x06400648 Address@xspi_evm : 0x40020048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
delay |
|
|
| 15 - 0 | 0x0 |
ial |
|
|
| xspi_ial3 |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x0640064c Address@xspi_evm : 0x4002004c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
delay |
|
|
| 15 - 0 | 0x0 |
ial |
|
|
| xspi_mm_wcr0 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400650 Address@xspi_evm : 0x40020050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
write_command |
|
|
| xspi_mm_wcr1 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400654 Address@xspi_evm : 0x40020054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
write_command |
|
|
| xspi_mm_rcr0 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400658 Address@xspi_evm : 0x40020058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
read_command |
|
|
| xspi_mm_rcr1 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x0640065c Address@xspi_evm : 0x4002005c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
read_command |
|
|
| xspi_mm_cr0 |
|
||||||||||||
| R/W |
0x00000404 |
Address@com_xspi : 0x06400660 Address@xspi_evm : 0x40020060 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||||||
| 30 | "0" |
tx_skip_ial |
|
||||||||||
| 29 | "0" |
rx_skip_ial |
|
||||||||||
| 28 | "0" |
tx_enable |
|
||||||||||
| 27 - 26 | 0 |
- |
reserved | ||||||||||
| 25 - 24 | "00" |
memory_word_size |
|
||||||||||
| 23 - 19 | 0 |
- |
reserved | ||||||||||
| 18 - 17 | "00" |
page_size |
|
||||||||||
| 16 | "0" |
page_size_en |
|
||||||||||
| 15 - 12 | 0 |
- |
reserved | ||||||||||
| 11 | "0" |
rx_address_phase_off |
|
||||||||||
| 10 | "1" |
rx_address_phase_position |
|
||||||||||
| 9 | "0" |
rx_command_phase_off |
|
||||||||||
| 8 | "0" |
rx_command_phase_position |
|
||||||||||
| 7 - 4 | 0 |
- |
reserved | ||||||||||
| 3 | "0" |
tx_address_phase_off |
|
||||||||||
| 2 | "1" |
tx_address_phase_position |
|
||||||||||
| 1 | "0" |
tx_command_phase_off |
|
||||||||||
| 0 | "0" |
tx_command_phase_position |
|
||||||||||
| xspi_mm_cr1 |
|
|||||||||||
| R/W |
0x00000033 |
Address@com_xspi : 0x06400664 Address@xspi_evm : 0x40020064 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||||
| 30 | "0" |
data_tx_ddr |
|
|||||||||
| 29 - 28 | "00" |
data_tx_bit_width |
|
|||||||||
| 27 - 26 | 0 |
- |
reserved | |||||||||
| 25 - 24 | "00" |
rx_address_tx_bit_width |
|
|||||||||
| 23 | "0" |
rx_address_tx_ddr |
|
|||||||||
| 22 - 20 | "000" |
rx_address_bytes_used |
|
|||||||||
| 19 - 18 | 0 |
- |
reserved | |||||||||
| 17 - 16 | "00" |
tx_address_tx_bit_width |
|
|||||||||
| 15 | "0" |
tx_address_tx_ddr |
|
|||||||||
| 14 - 12 | "000" |
tx_address_bytes_used |
|
|||||||||
| 11 | "0" |
read_command_fd |
|
|||||||||
| 10 | "0" |
write_command_fd |
|
|||||||||
| 9 | "0" |
read_command_tx_ddr |
|
|||||||||
| 8 | "0" |
write_command_tx_ddr |
|
|||||||||
| 7 - 6 | "00" |
read_command_tx_bit_width |
|
|||||||||
| 5 - 4 | "11" |
read_command_length |
|
|||||||||
| 3 - 2 | "00" |
write_command_tx_bit_width |
|
|||||||||
| 1 - 0 | "11" |
write_command_length |
|
|||||||||
| xspi_mm_cr2 |
|
||||||||||||
| R/W |
0x00000404 |
Address@com_xspi : 0x06400668 Address@xspi_evm : 0x40020068 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | ||||||||||
| 30 | "0" |
tx_skip_ial |
|
||||||||||
| 29 | "0" |
rx_skip_ial |
|
||||||||||
| 28 | "0" |
tx_enable |
|
||||||||||
| 27 - 26 | 0 |
- |
reserved | ||||||||||
| 25 - 24 | "00" |
memory_word_size |
|
||||||||||
| 23 - 19 | 0 |
- |
reserved | ||||||||||
| 18 - 17 | "00" |
page_size |
|
||||||||||
| 16 | "0" |
page_size_en |
|
||||||||||
| 15 - 12 | 0 |
- |
reserved | ||||||||||
| 11 | "0" |
rx_address_phase_off |
|
||||||||||
| 10 | "1" |
rx_address_phase_position |
|
||||||||||
| 9 | "0" |
rx_command_phase_off |
|
||||||||||
| 8 | "0" |
rx_command_phase_position |
|
||||||||||
| 7 - 4 | 0 |
- |
reserved | ||||||||||
| 3 | "0" |
tx_address_phase_off |
|
||||||||||
| 2 | "1" |
tx_address_phase_position |
|
||||||||||
| 1 | "0" |
tx_command_phase_off |
|
||||||||||
| 0 | "0" |
tx_command_phase_position |
|
||||||||||
| xspi_mm_cr3 |
|
|||||||||||
| R/W |
0x00000033 |
Address@com_xspi : 0x0640066c Address@xspi_evm : 0x4002006c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||||
| 30 | "0" |
data_tx_ddr |
|
|||||||||
| 29 - 28 | "00" |
data_tx_bit_width |
|
|||||||||
| 27 - 26 | 0 |
- |
reserved | |||||||||
| 25 - 24 | "00" |
rx_address_tx_bit_width |
|
|||||||||
| 23 | "0" |
rx_address_tx_ddr |
|
|||||||||
| 22 - 20 | "000" |
rx_address_bytes_used |
|
|||||||||
| 19 - 18 | 0 |
- |
reserved | |||||||||
| 17 - 16 | "00" |
tx_address_tx_bit_width |
|
|||||||||
| 15 | "0" |
tx_address_tx_ddr |
|
|||||||||
| 14 - 12 | "000" |
tx_address_bytes_used |
|
|||||||||
| 11 | "0" |
read_command_fd |
|
|||||||||
| 10 | "0" |
write_command_fd |
|
|||||||||
| 9 | "0" |
read_command_tx_ddr |
|
|||||||||
| 8 | "0" |
write_command_tx_ddr |
|
|||||||||
| 7 - 6 | "00" |
read_command_tx_bit_width |
|
|||||||||
| 5 - 4 | "11" |
read_command_length |
|
|||||||||
| 3 - 2 | "00" |
write_command_tx_bit_width |
|
|||||||||
| 1 - 0 | "11" |
write_command_length |
|
|||||||||
| xspi_mhc0 |
|
|||
| R/W |
0x00001031 |
Address@com_xspi : 0x06400670 Address@xspi_evm : 0x40020070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 12 | "0001" |
tx_inter_csn_min_high_cycles |
|
|
| 11 - 8 | "0000" |
tx_intra_csn_min_high_cycles |
|
|
| 7 - 4 | "0011" |
rx_inter_csn_min_high_cycles |
|
|
| 3 - 0 | "0001" |
rx_intra_csn_min_high_cycles |
|
|
| xspi_mhc1 |
|
|||
| R/W |
0x00001031 |
Address@com_xspi : 0x06400674 Address@xspi_evm : 0x40020074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 12 | "0001" |
tx_inter_csn_min_high_cycles |
|
|
| 11 - 8 | "0000" |
tx_intra_csn_min_high_cycles |
|
|
| 7 - 4 | "0011" |
rx_inter_csn_min_high_cycles |
|
|
| 3 - 0 | "0001" |
rx_intra_csn_min_high_cycles |
|
|
| xspi_mlc0 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400678 Address@xspi_evm : 0x40020078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
csn_max_low_cycles |
|
|
| xspi_mlc1 |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x0640067c Address@xspi_evm : 0x4002007c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
csn_max_low_cycles |
|
|
| xspi_irq_mask |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400680 Address@xspi_evm : 0x40020080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
clk_rx_tx_drifted_im |
|
|
| 9 | "0" |
clk_rx_too_fast_im |
|
|
| 8 | "0" |
clk_rx_too_slow_im |
|
|
| 7 | "0" |
external_im |
|
|
| 6 | "0" |
rx_fifo_overflow_im |
|
|
| 5 | "0" |
rx_fifo_underrun_im |
|
|
| 4 | "0" |
rx_fifo_nempty_im |
|
|
| 3 | "0" |
tx_fifo_overflow_im |
|
|
| 2 | "0" |
tx_fifo_underrun_im |
|
|
| 1 | "0" |
tx_fifo_empty_im |
|
|
| 0 | "0" |
transfer_end_im |
|
|
| xspi_irq_raw |
|
|||||||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400684 Address@xspi_evm : 0x40020084 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||
| 10 | "0" |
clk_rx_tx_drifted_is |
|
|||||
| 9 | "0" |
clk_rx_too_fast_is |
|
|||||
| 8 | "0" |
clk_rx_too_slow_is |
|
|||||
| 7 | "0" |
external_is |
|
|||||
| 6 | "0" |
rx_fifo_overflow_is |
|
|||||
| 5 | "0" |
rx_fifo_underrun_is |
|
|||||
| 4 | "0" |
rx_fifo_nempty_is |
|
|||||
| 3 | "0" |
tx_fifo_overflow_is |
|
|||||
| 2 | "0" |
tx_fifo_underrun_is |
|
|||||
| 1 | "0" |
tx_fifo_empty_is |
|
|||||
| 0 | "0" |
transfer_end_is |
|
|||||
| xspi_irq_masked |
|
|||||||
| R |
Address@com_xspi : 0x06400688 Address@xspi_evm : 0x40020088 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 11 | - |
reserved | ||||||
| 10 | clk_rx_tx_drifted_mis |
|
||||||
| 9 | clk_rx_too_fast_mis |
|
||||||
| 8 | clk_rx_too_slow_mis |
|
||||||
| 7 | external_mis |
|
||||||
| 6 | rx_fifo_overflow_mis |
|
||||||
| 5 | rx_fifo_underrun_mis |
|
||||||
| 4 | rx_fifo_nempty_mis |
|
||||||
| 3 | tx_fifo_overflow_mis |
|
||||||
| 2 | tx_fifo_underrun_mis |
|
||||||
| 1 | tx_fifo_empty_mis |
|
||||||
| 0 | transfer_end_mis |
|
||||||
| xspi_pio_out |
|
|||
| R/W |
0x00001e00 |
Address@com_xspi : 0x0640068c Address@xspi_evm : 0x4002008c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
clk_out |
|
|
| 12 | "1" |
rstn_out |
|
|
| 11 | "1" |
intn_out |
|
|
| 10 - 9 | "11" |
csn_out |
|
|
| 8 | "0" |
ds_out |
|
|
| 7 - 0 | "00000000" |
d_out |
|
|
| xspi_pio_oe |
|
|||
| R/W |
0x00000000 |
Address@com_xspi : 0x06400690 Address@xspi_evm : 0x40020090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
clk_oe |
|
|
| 12 | "0" |
rstn_oe |
|
|
| 11 | "0" |
intn_oe |
|
|
| 10 - 9 | "00" |
csn_oe |
|
|
| 8 | "0" |
ds_oe |
|
|
| 7 - 0 | "00000000" |
d_oe |
|
|
| xspi_pio_is |
|
|||
| R |
Address@com_xspi : 0x06400694 Address@xspi_evm : 0x40020094 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 14 | - |
reserved | ||
| 13 | clk_is |
|
||
| 12 | rstn_is |
|
||
| 11 | intn_is |
|
||
| 10 - 9 | csn_is |
|
||
| 8 | ds_is |
|
||
| 7 - 0 | d_is |
|
||
| xspi_rx_dr |
|
|||
| R |
Address@com_xspi : 0x06400698 Address@xspi_evm : 0x40020098 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | data |
|
||
| xspi_csn0_ar_1s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006a0 Address@xspi_evm : 0x400200a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_2s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006a4 Address@xspi_evm : 0x400200a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_4s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006a8 Address@xspi_evm : 0x400200a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_8s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006ac Address@xspi_evm : 0x400200ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_1d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006b0 Address@xspi_evm : 0x400200b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_2d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006b4 Address@xspi_evm : 0x400200b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_4d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006b8 Address@xspi_evm : 0x400200b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn0_ar_8d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006bc Address@xspi_evm : 0x400200bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_1s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006c0 Address@xspi_evm : 0x400200c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_2s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006c4 Address@xspi_evm : 0x400200c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_4s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006c8 Address@xspi_evm : 0x400200c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_8s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006cc Address@xspi_evm : 0x400200cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_1d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006d0 Address@xspi_evm : 0x400200d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_2d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006d4 Address@xspi_evm : 0x400200d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_4d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006d8 Address@xspi_evm : 0x400200d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_csn1_ar_8d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006dc Address@xspi_evm : 0x400200dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
address |
|
|
| xspi_tx_dr_1s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006e0 Address@xspi_evm : 0x400200e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_2s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006e4 Address@xspi_evm : 0x400200e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_4s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006e8 Address@xspi_evm : 0x400200e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_8s |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006ec Address@xspi_evm : 0x400200ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_1d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006f0 Address@xspi_evm : 0x400200f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_2d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006f4 Address@xspi_evm : 0x400200f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_4d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006f8 Address@xspi_evm : 0x400200f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_8d |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x064006fc Address@xspi_evm : 0x400200fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_4s_ds_off |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x06400700 Address@xspi_evm : 0x40020100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_8s_ds_off |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x06400704 Address@xspi_evm : 0x40020104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_4d_ds_off |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x06400708 Address@xspi_evm : 0x40020108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_tx_dr_8d_ds_off |
|
|||
| W |
0x00000000 |
Address@com_xspi : 0x0640070c Address@xspi_evm : 0x4002010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| xspi_csn0_addr_byte0_cr0 |
|
|||||||||||||||
| R/W |
0x03020100 |
Address@com_xspi : 0x06400710 Address@xspi_evm : 0x40020110 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000011" |
addr_bit3_cfg |
|
|||||||||||||
| 23 - 16 | "00000010" |
addr_bit2_cfg |
|
|||||||||||||
| 15 - 8 | "00000001" |
addr_bit1_cfg |
|
|||||||||||||
| 7 - 0 | "00000000" |
addr_bit0_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte0_cr1 |
|
|||||||||||||||
| R/W |
0x07060504 |
Address@com_xspi : 0x06400714 Address@xspi_evm : 0x40020114 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000111" |
addr_bit7_cfg |
|
|||||||||||||
| 23 - 16 | "00000110" |
addr_bit6_cfg |
|
|||||||||||||
| 15 - 8 | "00000101" |
addr_bit5_cfg |
|
|||||||||||||
| 7 - 0 | "00000100" |
addr_bit4_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte1_cr0 |
|
|||||||||||||||
| R/W |
0x0b0a0908 |
Address@com_xspi : 0x06400718 Address@xspi_evm : 0x40020118 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00001011" |
addr_bit11_cfg |
|
|||||||||||||
| 23 - 16 | "00001010" |
addr_bit10_cfg |
|
|||||||||||||
| 15 - 8 | "00001001" |
addr_bit9_cfg |
|
|||||||||||||
| 7 - 0 | "00001000" |
addr_bit8_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte1_cr1 |
|
|||||||||||||||
| R/W |
0x0f0e0d0c |
Address@com_xspi : 0x0640071c Address@xspi_evm : 0x4002011c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00001111" |
addr_bit15_cfg |
|
|||||||||||||
| 23 - 16 | "00001110" |
addr_bit14_cfg |
|
|||||||||||||
| 15 - 8 | "00001101" |
addr_bit13_cfg |
|
|||||||||||||
| 7 - 0 | "00001100" |
addr_bit12_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte2_cr0 |
|
|||||||||||||||
| R/W |
0x13121110 |
Address@com_xspi : 0x06400720 Address@xspi_evm : 0x40020120 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00010011" |
addr_bit19_cfg |
|
|||||||||||||
| 23 - 16 | "00010010" |
addr_bit18_cfg |
|
|||||||||||||
| 15 - 8 | "00010001" |
addr_bit17_cfg |
|
|||||||||||||
| 7 - 0 | "00010000" |
addr_bit16_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte2_cr1 |
|
|||||||||||||||
| R/W |
0x17161514 |
Address@com_xspi : 0x06400724 Address@xspi_evm : 0x40020124 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00010111" |
addr_bit23_cfg |
|
|||||||||||||
| 23 - 16 | "00010110" |
addr_bit22_cfg |
|
|||||||||||||
| 15 - 8 | "00010101" |
addr_bit21_cfg |
|
|||||||||||||
| 7 - 0 | "00010100" |
addr_bit20_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte3_cr0 |
|
|||||||||||||||
| R/W |
0x1b1a1918 |
Address@com_xspi : 0x06400728 Address@xspi_evm : 0x40020128 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00011011" |
addr_bit27_cfg |
|
|||||||||||||
| 23 - 16 | "00011010" |
addr_bit26_cfg |
|
|||||||||||||
| 15 - 8 | "00011001" |
addr_bit25_cfg |
|
|||||||||||||
| 7 - 0 | "00011000" |
addr_bit24_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte3_cr1 |
|
|||||||||||||||
| R/W |
0x1f1e1d1c |
Address@com_xspi : 0x0640072c Address@xspi_evm : 0x4002012c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00011111" |
addr_bit31_cfg |
|
|||||||||||||
| 23 - 16 | "00011110" |
addr_bit30_cfg |
|
|||||||||||||
| 15 - 8 | "00011101" |
addr_bit29_cfg |
|
|||||||||||||
| 7 - 0 | "00011100" |
addr_bit28_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte4_cr0 |
|
|||||||||||||||
| R/W |
0x23222120 |
Address@com_xspi : 0x06400730 Address@xspi_evm : 0x40020130 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00100011" |
addr_bit35_cfg |
|
|||||||||||||
| 23 - 16 | "00100010" |
addr_bit34_cfg |
|
|||||||||||||
| 15 - 8 | "00100001" |
addr_bit33_cfg |
|
|||||||||||||
| 7 - 0 | "00100000" |
addr_bit32_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte4_cr1 |
|
|||||||||||||||
| R/W |
0x27262524 |
Address@com_xspi : 0x06400734 Address@xspi_evm : 0x40020134 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00100111" |
addr_bit39_cfg |
|
|||||||||||||
| 23 - 16 | "00100110" |
addr_bit38_cfg |
|
|||||||||||||
| 15 - 8 | "00100101" |
addr_bit37_cfg |
|
|||||||||||||
| 7 - 0 | "00100100" |
addr_bit36_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte5_cr0 |
|
|||||||||||||||
| R/W |
0x2b2a2928 |
Address@com_xspi : 0x06400738 Address@xspi_evm : 0x40020138 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00101011" |
addr_bit43_cfg |
|
|||||||||||||
| 23 - 16 | "00101010" |
addr_bit42_cfg |
|
|||||||||||||
| 15 - 8 | "00101001" |
addr_bit41_cfg |
|
|||||||||||||
| 7 - 0 | "00101000" |
addr_bit40_cfg |
|
|||||||||||||
| xspi_csn0_addr_byte5_cr1 |
|
|||||||||||||||
| R/W |
0x2f2e2d2c |
Address@com_xspi : 0x0640073c Address@xspi_evm : 0x4002013c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00101111" |
addr_bit47_cfg |
|
|||||||||||||
| 23 - 16 | "00101110" |
addr_bit46_cfg |
|
|||||||||||||
| 15 - 8 | "00101101" |
addr_bit45_cfg |
|
|||||||||||||
| 7 - 0 | "00101100" |
addr_bit44_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte0_cr0 |
|
|||||||||||||||
| R/W |
0x03020100 |
Address@com_xspi : 0x06400740 Address@xspi_evm : 0x40020140 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000011" |
addr_bit3_cfg |
|
|||||||||||||
| 23 - 16 | "00000010" |
addr_bit2_cfg |
|
|||||||||||||
| 15 - 8 | "00000001" |
addr_bit1_cfg |
|
|||||||||||||
| 7 - 0 | "00000000" |
addr_bit0_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte0_cr1 |
|
|||||||||||||||
| R/W |
0x07060504 |
Address@com_xspi : 0x06400744 Address@xspi_evm : 0x40020144 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000111" |
addr_bit7_cfg |
|
|||||||||||||
| 23 - 16 | "00000110" |
addr_bit6_cfg |
|
|||||||||||||
| 15 - 8 | "00000101" |
addr_bit5_cfg |
|
|||||||||||||
| 7 - 0 | "00000100" |
addr_bit4_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte1_cr0 |
|
|||||||||||||||
| R/W |
0x0b0a0908 |
Address@com_xspi : 0x06400748 Address@xspi_evm : 0x40020148 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00001011" |
addr_bit11_cfg |
|
|||||||||||||
| 23 - 16 | "00001010" |
addr_bit10_cfg |
|
|||||||||||||
| 15 - 8 | "00001001" |
addr_bit9_cfg |
|
|||||||||||||
| 7 - 0 | "00001000" |
addr_bit8_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte1_cr1 |
|
|||||||||||||||
| R/W |
0x0f0e0d0c |
Address@com_xspi : 0x0640074c Address@xspi_evm : 0x4002014c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00001111" |
addr_bit15_cfg |
|
|||||||||||||
| 23 - 16 | "00001110" |
addr_bit14_cfg |
|
|||||||||||||
| 15 - 8 | "00001101" |
addr_bit13_cfg |
|
|||||||||||||
| 7 - 0 | "00001100" |
addr_bit12_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte2_cr0 |
|
|||||||||||||||
| R/W |
0x13121110 |
Address@com_xspi : 0x06400750 Address@xspi_evm : 0x40020150 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00010011" |
addr_bit19_cfg |
|
|||||||||||||
| 23 - 16 | "00010010" |
addr_bit18_cfg |
|
|||||||||||||
| 15 - 8 | "00010001" |
addr_bit17_cfg |
|
|||||||||||||
| 7 - 0 | "00010000" |
addr_bit16_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte2_cr1 |
|
|||||||||||||||
| R/W |
0x17161514 |
Address@com_xspi : 0x06400754 Address@xspi_evm : 0x40020154 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00010111" |
addr_bit23_cfg |
|
|||||||||||||
| 23 - 16 | "00010110" |
addr_bit22_cfg |
|
|||||||||||||
| 15 - 8 | "00010101" |
addr_bit21_cfg |
|
|||||||||||||
| 7 - 0 | "00010100" |
addr_bit20_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte3_cr0 |
|
|||||||||||||||
| R/W |
0x1b1a1918 |
Address@com_xspi : 0x06400758 Address@xspi_evm : 0x40020158 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00011011" |
addr_bit27_cfg |
|
|||||||||||||
| 23 - 16 | "00011010" |
addr_bit26_cfg |
|
|||||||||||||
| 15 - 8 | "00011001" |
addr_bit25_cfg |
|
|||||||||||||
| 7 - 0 | "00011000" |
addr_bit24_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte3_cr1 |
|
|||||||||||||||
| R/W |
0x1f1e1d1c |
Address@com_xspi : 0x0640075c Address@xspi_evm : 0x4002015c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00011111" |
addr_bit31_cfg |
|
|||||||||||||
| 23 - 16 | "00011110" |
addr_bit30_cfg |
|
|||||||||||||
| 15 - 8 | "00011101" |
addr_bit29_cfg |
|
|||||||||||||
| 7 - 0 | "00011100" |
addr_bit28_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte4_cr0 |
|
|||||||||||||||
| R/W |
0x23222120 |
Address@com_xspi : 0x06400760 Address@xspi_evm : 0x40020160 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00100011" |
addr_bit35_cfg |
|
|||||||||||||
| 23 - 16 | "00100010" |
addr_bit34_cfg |
|
|||||||||||||
| 15 - 8 | "00100001" |
addr_bit33_cfg |
|
|||||||||||||
| 7 - 0 | "00100000" |
addr_bit32_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte4_cr1 |
|
|||||||||||||||
| R/W |
0x27262524 |
Address@com_xspi : 0x06400764 Address@xspi_evm : 0x40020164 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00100111" |
addr_bit39_cfg |
|
|||||||||||||
| 23 - 16 | "00100110" |
addr_bit38_cfg |
|
|||||||||||||
| 15 - 8 | "00100101" |
addr_bit37_cfg |
|
|||||||||||||
| 7 - 0 | "00100100" |
addr_bit36_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte5_cr0 |
|
|||||||||||||||
| R/W |
0x2b2a2928 |
Address@com_xspi : 0x06400768 Address@xspi_evm : 0x40020168 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00101011" |
addr_bit43_cfg |
|
|||||||||||||
| 23 - 16 | "00101010" |
addr_bit42_cfg |
|
|||||||||||||
| 15 - 8 | "00101001" |
addr_bit41_cfg |
|
|||||||||||||
| 7 - 0 | "00101000" |
addr_bit40_cfg |
|
|||||||||||||
| xspi_csn1_addr_byte5_cr1 |
|
|||||||||||||||
| R/W |
0x2f2e2d2c |
Address@com_xspi : 0x0640076c Address@xspi_evm : 0x4002016c |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00101111" |
addr_bit47_cfg |
|
|||||||||||||
| 23 - 16 | "00101110" |
addr_bit46_cfg |
|
|||||||||||||
| 15 - 8 | "00101101" |
addr_bit45_cfg |
|
|||||||||||||
| 7 - 0 | "00101100" |
addr_bit44_cfg |
|
|||||||||||||
| sync_cfg |
|
||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400800 Address@com_sync_timer_global : 0x06400c00 Address@app_sync_timer : 0x40080800 Address@app_sync_timer_global : 0x40080c00 Address@mot_sync_timer : 0x49200c00 Address@mot_sync_timer_global : 0x49201000 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||
| 2 | "0" |
write_sync_src_sel |
|
||||
| 1 | "0" |
incr_src_sel |
|
||||
| 0 | "0" |
en |
|
||||
| sync_timebase_modulus | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400804 Address@com_sync_timer_global : 0x06400c04 Address@app_sync_timer : 0x40080804 Address@app_sync_timer_global : 0x40080c04 Address@mot_sync_timer : 0x49200c04 Address@mot_sync_timer_global : 0x49201004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_cmd_do_sync |
|
|||
| W |
0x00000000 |
Address@com_sync_timer : 0x06400808 Address@com_sync_timer_global : 0x06400c08 Address@app_sync_timer : 0x40080808 Address@app_sync_timer_global : 0x40080c08 Address@mot_sync_timer : 0x49200c08 Address@mot_sync_timer_global : 0x49201008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 | "0" |
sync29 |
|
|
| 29 | "0" |
sync28 |
|
|
| 28 | "0" |
sync27 |
|
|
| 27 | "0" |
sync26 |
|
|
| 26 | "0" |
sync25 |
|
|
| 25 | "0" |
sync24 |
|
|
| 24 | "0" |
sync23 |
|
|
| 23 | "0" |
sync22 |
|
|
| 22 | "0" |
sync21 |
|
|
| 21 | "0" |
sync20 |
|
|
| 20 | "0" |
sync19 |
|
|
| 19 | "0" |
sync18 |
|
|
| 18 | "0" |
sync17 |
|
|
| 17 | "0" |
sync16 |
|
|
| 16 | "0" |
sync15 |
|
|
| 15 | "0" |
sync14 |
|
|
| 14 | "0" |
sync13 |
|
|
| 13 | "0" |
sync12 |
|
|
| 12 | "0" |
sync11 |
|
|
| 11 | "0" |
sync10 |
|
|
| 10 | "0" |
sync9 |
|
|
| 9 | "0" |
sync8 |
|
|
| 8 | "0" |
sync7 |
|
|
| 7 | "0" |
sync6 |
|
|
| 6 | "0" |
sync5 |
|
|
| 5 | "0" |
sync4 |
|
|
| 4 | "0" |
sync3 |
|
|
| 3 | "0" |
sync2 |
|
|
| 2 | "0" |
sync1 |
|
|
| 1 | "0" |
sync0 |
|
|
| 0 | "0" |
read_sync |
|
|
| sync_write_sync_ctrl |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640080c Address@com_sync_timer_global : 0x06400c0c Address@app_sync_timer : 0x4008080c Address@app_sync_timer_global : 0x40080c0c Address@mot_sync_timer : 0x49200c0c Address@mot_sync_timer_global : 0x4920100c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
sub_phase_ws_written |
||
| 3 | "0" |
base_phase_ws_written |
||
| 2 | "0" |
base_phase_rld_ws_written |
||
| 1 | "0" |
timebase_inc_ws_written |
||
| 0 | "0" |
timebase_ws_written |
|
|
| sync_timebase_ws | |||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400810 Address@com_sync_timer_global : 0x06400c10 Address@app_sync_timer : 0x40080810 Address@app_sync_timer_global : 0x40080c10 Address@mot_sync_timer : 0x49200c10 Address@mot_sync_timer_global : 0x49201010 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved |
| 15 - 0 | 0x0 |
val |
|
| sync_timebase_inc_ws | |||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400814 Address@com_sync_timer_global : 0x06400c14 Address@app_sync_timer : 0x40080814 Address@app_sync_timer_global : 0x40080c14 Address@mot_sync_timer : 0x49200c14 Address@mot_sync_timer_global : 0x49201014 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved |
| 15 - 0 | 0x0 |
val |
|
| sync_base_phase_rld_ws | |||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400818 Address@com_sync_timer_global : 0x06400c18 Address@app_sync_timer : 0x40080818 Address@app_sync_timer_global : 0x40080c18 Address@mot_sync_timer : 0x49200c18 Address@mot_sync_timer_global : 0x49201018 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved |
| 15 - 0 | 0x0 |
val |
|
| sync_base_phase_ws | |||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640081c Address@com_sync_timer_global : 0x06400c1c Address@app_sync_timer : 0x4008081c Address@app_sync_timer_global : 0x40080c1c Address@mot_sync_timer : 0x49200c1c Address@mot_sync_timer_global : 0x4920101c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved |
| 15 - 0 | 0x0 |
val |
|
| sync_sub_phase_ws | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400820 Address@com_sync_timer_global : 0x06400c20 Address@app_sync_timer : 0x40080820 Address@app_sync_timer_global : 0x40080c20 Address@mot_sync_timer : 0x49200c20 Address@mot_sync_timer_global : 0x49201020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 - 11 | "0000" |
sub_phase_sel |
|
|
| 10 - 0 | 0x0 |
val |
||
| sync_timebase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400824 Address@com_sync_timer_global : 0x06400c24 Address@app_sync_timer : 0x40080824 Address@app_sync_timer_global : 0x40080c24 Address@mot_sync_timer : 0x49200c24 Address@mot_sync_timer_global : 0x49201024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_timebase_inc | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400828 Address@com_sync_timer_global : 0x06400c28 Address@app_sync_timer : 0x40080828 Address@app_sync_timer_global : 0x40080c28 Address@mot_sync_timer : 0x49200c28 Address@mot_sync_timer_global : 0x49201028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_base_phase_rld | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640082c Address@com_sync_timer_global : 0x06400c2c Address@app_sync_timer : 0x4008082c Address@app_sync_timer_global : 0x40080c2c Address@mot_sync_timer : 0x49200c2c Address@mot_sync_timer_global : 0x4920102c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_base_phase | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400830 Address@com_sync_timer_global : 0x06400c30 Address@app_sync_timer : 0x40080830 Address@app_sync_timer_global : 0x40080c30 Address@mot_sync_timer : 0x49200c30 Address@mot_sync_timer_global : 0x49201030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_read_sync_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400834 Address@com_sync_timer_global : 0x06400c34 Address@app_sync_timer : 0x40080834 Address@app_sync_timer_global : 0x40080c34 Address@mot_sync_timer : 0x49200c34 Address@mot_sync_timer_global : 0x49201034 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | ||||||||
| 24 - 20 | "00000" |
sync_in_ifil_thres |
|
||||||||
| 19 - 15 | "00000" |
sub_phase_sel1 |
|
||||||||
| 14 - 10 | "00000" |
sub_phase_sel0 |
|
||||||||
| 9 - 8 | "00" |
sync_in_edge |
|
||||||||
| 7 - 5 | "000" |
sel_ext_rs |
|
||||||||
| 4 - 2 | "000" |
sel_int_rs |
|
||||||||
| 1 - 0 | "00" |
src |
|
||||||||
| sync_timebase_rs | ||||
| R |
Address@com_sync_timer : 0x06400838 Address@com_sync_timer_global : 0x06400c38 Address@app_sync_timer : 0x40080838 Address@app_sync_timer_global : 0x40080c38 Address@mot_sync_timer : 0x49200c38 Address@mot_sync_timer_global : 0x49201038 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| sync_base_phase_rs | |||
| R |
Address@com_sync_timer : 0x0640083c Address@com_sync_timer_global : 0x06400c3c Address@app_sync_timer : 0x4008083c Address@app_sync_timer_global : 0x40080c3c Address@mot_sync_timer : 0x49200c3c Address@mot_sync_timer_global : 0x4920103c |
Bits | Name | Description |
|---|---|---|---|
| 31 - 16 | - |
reserved | |
| 15 - 0 | val |
||
| sync_sub_phase_sel0_rs | |||
| R |
Address@com_sync_timer : 0x06400840 Address@com_sync_timer_global : 0x06400c40 Address@app_sync_timer : 0x40080840 Address@app_sync_timer_global : 0x40080c40 Address@mot_sync_timer : 0x49200c40 Address@mot_sync_timer_global : 0x49201040 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 11 | - |
reserved | |
| 10 - 0 | val |
||
| sync_sub_phase_sel1_rs | |||
| R |
Address@com_sync_timer : 0x06400844 Address@com_sync_timer_global : 0x06400c44 Address@app_sync_timer : 0x40080844 Address@app_sync_timer_global : 0x40080c44 Address@mot_sync_timer : 0x49200c44 Address@mot_sync_timer_global : 0x49201044 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 11 | - |
reserved | |
| 10 - 0 | val |
||
| sync_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400848 Address@com_sync_timer_global : 0x06400c48 Address@app_sync_timer : 0x40080848 Address@app_sync_timer_global : 0x40080c48 Address@mot_sync_timer : 0x49200c48 Address@mot_sync_timer_global : 0x49201048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sync29_evt |
|
|
| 30 | "0" |
sync28_evt |
|
|
| 29 | "0" |
sync27_evt |
|
|
| 28 | "0" |
sync26_evt |
|
|
| 27 | "0" |
sync25_evt |
|
|
| 26 | "0" |
sync24_evt |
|
|
| 25 | "0" |
sync23_evt |
|
|
| 24 | "0" |
sync22_evt |
|
|
| 23 | "0" |
sync21_evt |
|
|
| 22 | "0" |
sync20_evt |
|
|
| 21 | "0" |
sync19_evt |
|
|
| 20 | "0" |
sync18_evt |
|
|
| 19 | "0" |
sync17_evt |
|
|
| 18 | "0" |
sync16_evt |
|
|
| 17 | "0" |
sync15_evt |
|
|
| 16 | "0" |
sync14_evt |
|
|
| 15 | "0" |
sync13_evt |
|
|
| 14 | "0" |
sync12_evt |
|
|
| 13 | "0" |
sync11_evt |
|
|
| 12 | "0" |
sync10_evt |
|
|
| 11 | "0" |
sync9_evt |
|
|
| 10 | "0" |
sync8_evt |
|
|
| 9 | "0" |
sync7_evt |
|
|
| 8 | "0" |
sync6_evt |
|
|
| 7 | "0" |
sync5_evt |
|
|
| 6 | "0" |
sync4_evt |
|
|
| 5 | "0" |
sync3_evt |
|
|
| 4 | "0" |
sync2_evt |
|
|
| 3 | "0" |
sync1_evt |
|
|
| 2 | "0" |
sync0_evt |
|
|
| 1 | "0" |
read_sync_evt |
|
|
| 0 | "0" |
base_phase_rld_evt |
|
|
| sync_irq_masked |
|
|||
| R |
Address@com_sync_timer : 0x0640084c Address@com_sync_timer_global : 0x06400c4c Address@app_sync_timer : 0x4008084c Address@app_sync_timer_global : 0x40080c4c Address@mot_sync_timer : 0x49200c4c Address@mot_sync_timer_global : 0x4920104c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | sync29_evt |
|
||
| 30 | sync28_evt |
|
||
| 29 | sync27_evt |
|
||
| 28 | sync26_evt |
|
||
| 27 | sync25_evt |
|
||
| 26 | sync24_evt |
|
||
| 25 | sync23_evt |
|
||
| 24 | sync22_evt |
|
||
| 23 | sync21_evt |
|
||
| 22 | sync20_evt |
|
||
| 21 | sync19_evt |
|
||
| 20 | sync18_evt |
|
||
| 19 | sync17_evt |
|
||
| 18 | sync16_evt |
|
||
| 17 | sync15_evt |
|
||
| 16 | sync14_evt |
|
||
| 15 | sync13_evt |
|
||
| 14 | sync12_evt |
|
||
| 13 | sync11_evt |
|
||
| 12 | sync10_evt |
|
||
| 11 | sync9_evt |
|
||
| 10 | sync8_evt |
|
||
| 9 | sync7_evt |
|
||
| 8 | sync6_evt |
|
||
| 7 | sync5_evt |
|
||
| 6 | sync4_evt |
|
||
| 5 | sync3_evt |
|
||
| 4 | sync2_evt |
|
||
| 3 | sync1_evt |
|
||
| 2 | sync0_evt |
|
||
| 1 | read_sync_evt |
|
||
| 0 | base_phase_rld_evt |
|
||
| sync_irq_msk_set | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400850 Address@com_sync_timer_global : 0x06400c50 Address@app_sync_timer : 0x40080850 Address@app_sync_timer_global : 0x40080c50 Address@mot_sync_timer : 0x49200c50 Address@mot_sync_timer_global : 0x49201050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sync29_evt |
||
| 30 | "0" |
sync28_evt |
||
| 29 | "0" |
sync27_evt |
||
| 28 | "0" |
sync26_evt |
||
| 27 | "0" |
sync25_evt |
||
| 26 | "0" |
sync24_evt |
||
| 25 | "0" |
sync23_evt |
||
| 24 | "0" |
sync22_evt |
||
| 23 | "0" |
sync21_evt |
||
| 22 | "0" |
sync20_evt |
||
| 21 | "0" |
sync19_evt |
||
| 20 | "0" |
sync18_evt |
||
| 19 | "0" |
sync17_evt |
||
| 18 | "0" |
sync16_evt |
||
| 17 | "0" |
sync15_evt |
||
| 16 | "0" |
sync14_evt |
||
| 15 | "0" |
sync13_evt |
||
| 14 | "0" |
sync12_evt |
||
| 13 | "0" |
sync11_evt |
||
| 12 | "0" |
sync10_evt |
||
| 11 | "0" |
sync9_evt |
||
| 10 | "0" |
sync8_evt |
||
| 9 | "0" |
sync7_evt |
||
| 8 | "0" |
sync6_evt |
||
| 7 | "0" |
sync5_evt |
||
| 6 | "0" |
sync4_evt |
||
| 5 | "0" |
sync3_evt |
||
| 4 | "0" |
sync2_evt |
||
| 3 | "0" |
sync1_evt |
||
| 2 | "0" |
sync0_evt |
||
| 1 | "0" |
read_sync_evt |
||
| 0 | "0" |
base_phase_rld_evt |
|
|
| sync_irq_msk_reset | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400854 Address@com_sync_timer_global : 0x06400c54 Address@app_sync_timer : 0x40080854 Address@app_sync_timer_global : 0x40080c54 Address@mot_sync_timer : 0x49200c54 Address@mot_sync_timer_global : 0x49201054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sync29_evt |
||
| 30 | "0" |
sync28_evt |
||
| 29 | "0" |
sync27_evt |
||
| 28 | "0" |
sync26_evt |
||
| 27 | "0" |
sync25_evt |
||
| 26 | "0" |
sync24_evt |
||
| 25 | "0" |
sync23_evt |
||
| 24 | "0" |
sync22_evt |
||
| 23 | "0" |
sync21_evt |
||
| 22 | "0" |
sync20_evt |
||
| 21 | "0" |
sync19_evt |
||
| 20 | "0" |
sync18_evt |
||
| 19 | "0" |
sync17_evt |
||
| 18 | "0" |
sync16_evt |
||
| 17 | "0" |
sync15_evt |
||
| 16 | "0" |
sync14_evt |
||
| 15 | "0" |
sync13_evt |
||
| 14 | "0" |
sync12_evt |
||
| 13 | "0" |
sync11_evt |
||
| 12 | "0" |
sync10_evt |
||
| 11 | "0" |
sync9_evt |
||
| 10 | "0" |
sync8_evt |
||
| 9 | "0" |
sync7_evt |
||
| 8 | "0" |
sync6_evt |
||
| 7 | "0" |
sync5_evt |
||
| 6 | "0" |
sync4_evt |
||
| 5 | "0" |
sync3_evt |
||
| 4 | "0" |
sync2_evt |
||
| 3 | "0" |
sync1_evt |
||
| 2 | "0" |
sync0_evt |
||
| 1 | "0" |
read_sync_evt |
||
| 0 | "0" |
base_phase_rld_evt |
|
|
| sync_irq_no | ||||
| R |
Address@com_sync_timer : 0x06400858 Address@com_sync_timer_global : 0x06400c58 Address@app_sync_timer : 0x40080858 Address@app_sync_timer_global : 0x40080c58 Address@mot_sync_timer : 0x49200c58 Address@mot_sync_timer_global : 0x49201058 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 6 | - |
reserved | ||
| 5 - 0 | val |
|
||
| sync_reload_configuration | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640085c Address@com_sync_timer_global : 0x06400c5c Address@app_sync_timer : 0x4008085c Address@app_sync_timer_global : 0x40080c5c Address@mot_sync_timer : 0x49200c5c Address@mot_sync_timer_global : 0x4920105c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
autorld_sub_phases |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
autorld_base_phase |
|
|
| 0 | "0" |
autorld_timebase |
|
|
| sync_sub_phase_0_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400860 Address@com_sync_timer_global : 0x06400c60 Address@app_sync_timer : 0x40080860 Address@app_sync_timer_global : 0x40080c60 Address@mot_sync_timer : 0x49200c60 Address@mot_sync_timer_global : 0x49201060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_0 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400864 Address@com_sync_timer_global : 0x06400c64 Address@app_sync_timer : 0x40080864 Address@app_sync_timer_global : 0x40080c64 Address@mot_sync_timer : 0x49200c64 Address@mot_sync_timer_global : 0x49201064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_0 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400868 Address@com_sync_timer_global : 0x06400c68 Address@app_sync_timer : 0x40080868 Address@app_sync_timer_global : 0x40080c68 Address@mot_sync_timer : 0x49200c68 Address@mot_sync_timer_global : 0x49201068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_1_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640086c Address@com_sync_timer_global : 0x06400c6c Address@app_sync_timer : 0x4008086c Address@app_sync_timer_global : 0x40080c6c Address@mot_sync_timer : 0x49200c6c Address@mot_sync_timer_global : 0x4920106c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_1 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400870 Address@com_sync_timer_global : 0x06400c70 Address@app_sync_timer : 0x40080870 Address@app_sync_timer_global : 0x40080c70 Address@mot_sync_timer : 0x49200c70 Address@mot_sync_timer_global : 0x49201070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400874 Address@com_sync_timer_global : 0x06400c74 Address@app_sync_timer : 0x40080874 Address@app_sync_timer_global : 0x40080c74 Address@mot_sync_timer : 0x49200c74 Address@mot_sync_timer_global : 0x49201074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_2_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400878 Address@com_sync_timer_global : 0x06400c78 Address@app_sync_timer : 0x40080878 Address@app_sync_timer_global : 0x40080c78 Address@mot_sync_timer : 0x49200c78 Address@mot_sync_timer_global : 0x49201078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_2 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640087c Address@com_sync_timer_global : 0x06400c7c Address@app_sync_timer : 0x4008087c Address@app_sync_timer_global : 0x40080c7c Address@mot_sync_timer : 0x49200c7c Address@mot_sync_timer_global : 0x4920107c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400880 Address@com_sync_timer_global : 0x06400c80 Address@app_sync_timer : 0x40080880 Address@app_sync_timer_global : 0x40080c80 Address@mot_sync_timer : 0x49200c80 Address@mot_sync_timer_global : 0x49201080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_3_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400884 Address@com_sync_timer_global : 0x06400c84 Address@app_sync_timer : 0x40080884 Address@app_sync_timer_global : 0x40080c84 Address@mot_sync_timer : 0x49200c84 Address@mot_sync_timer_global : 0x49201084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_3 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400888 Address@com_sync_timer_global : 0x06400c88 Address@app_sync_timer : 0x40080888 Address@app_sync_timer_global : 0x40080c88 Address@mot_sync_timer : 0x49200c88 Address@mot_sync_timer_global : 0x49201088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_3 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640088c Address@com_sync_timer_global : 0x06400c8c Address@app_sync_timer : 0x4008088c Address@app_sync_timer_global : 0x40080c8c Address@mot_sync_timer : 0x49200c8c Address@mot_sync_timer_global : 0x4920108c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_4_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400890 Address@com_sync_timer_global : 0x06400c90 Address@app_sync_timer : 0x40080890 Address@app_sync_timer_global : 0x40080c90 Address@mot_sync_timer : 0x49200c90 Address@mot_sync_timer_global : 0x49201090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_4 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400894 Address@com_sync_timer_global : 0x06400c94 Address@app_sync_timer : 0x40080894 Address@app_sync_timer_global : 0x40080c94 Address@mot_sync_timer : 0x49200c94 Address@mot_sync_timer_global : 0x49201094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_4 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400898 Address@com_sync_timer_global : 0x06400c98 Address@app_sync_timer : 0x40080898 Address@app_sync_timer_global : 0x40080c98 Address@mot_sync_timer : 0x49200c98 Address@mot_sync_timer_global : 0x49201098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_5_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640089c Address@com_sync_timer_global : 0x06400c9c Address@app_sync_timer : 0x4008089c Address@app_sync_timer_global : 0x40080c9c Address@mot_sync_timer : 0x49200c9c Address@mot_sync_timer_global : 0x4920109c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_5 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008a0 Address@com_sync_timer_global : 0x06400ca0 Address@app_sync_timer : 0x400808a0 Address@app_sync_timer_global : 0x40080ca0 Address@mot_sync_timer : 0x49200ca0 Address@mot_sync_timer_global : 0x492010a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_5 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008a4 Address@com_sync_timer_global : 0x06400ca4 Address@app_sync_timer : 0x400808a4 Address@app_sync_timer_global : 0x40080ca4 Address@mot_sync_timer : 0x49200ca4 Address@mot_sync_timer_global : 0x492010a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_6_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008a8 Address@com_sync_timer_global : 0x06400ca8 Address@app_sync_timer : 0x400808a8 Address@app_sync_timer_global : 0x40080ca8 Address@mot_sync_timer : 0x49200ca8 Address@mot_sync_timer_global : 0x492010a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_6 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008ac Address@com_sync_timer_global : 0x06400cac Address@app_sync_timer : 0x400808ac Address@app_sync_timer_global : 0x40080cac Address@mot_sync_timer : 0x49200cac Address@mot_sync_timer_global : 0x492010ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_6 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008b0 Address@com_sync_timer_global : 0x06400cb0 Address@app_sync_timer : 0x400808b0 Address@app_sync_timer_global : 0x40080cb0 Address@mot_sync_timer : 0x49200cb0 Address@mot_sync_timer_global : 0x492010b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_7_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008b4 Address@com_sync_timer_global : 0x06400cb4 Address@app_sync_timer : 0x400808b4 Address@app_sync_timer_global : 0x40080cb4 Address@mot_sync_timer : 0x49200cb4 Address@mot_sync_timer_global : 0x492010b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_7 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008b8 Address@com_sync_timer_global : 0x06400cb8 Address@app_sync_timer : 0x400808b8 Address@app_sync_timer_global : 0x40080cb8 Address@mot_sync_timer : 0x49200cb8 Address@mot_sync_timer_global : 0x492010b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_7 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008bc Address@com_sync_timer_global : 0x06400cbc Address@app_sync_timer : 0x400808bc Address@app_sync_timer_global : 0x40080cbc Address@mot_sync_timer : 0x49200cbc Address@mot_sync_timer_global : 0x492010bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_8_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008c0 Address@com_sync_timer_global : 0x06400cc0 Address@app_sync_timer : 0x400808c0 Address@app_sync_timer_global : 0x40080cc0 Address@mot_sync_timer : 0x49200cc0 Address@mot_sync_timer_global : 0x492010c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_8 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008c4 Address@com_sync_timer_global : 0x06400cc4 Address@app_sync_timer : 0x400808c4 Address@app_sync_timer_global : 0x40080cc4 Address@mot_sync_timer : 0x49200cc4 Address@mot_sync_timer_global : 0x492010c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_8 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008c8 Address@com_sync_timer_global : 0x06400cc8 Address@app_sync_timer : 0x400808c8 Address@app_sync_timer_global : 0x40080cc8 Address@mot_sync_timer : 0x49200cc8 Address@mot_sync_timer_global : 0x492010c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_9_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008cc Address@com_sync_timer_global : 0x06400ccc Address@app_sync_timer : 0x400808cc Address@app_sync_timer_global : 0x40080ccc Address@mot_sync_timer : 0x49200ccc Address@mot_sync_timer_global : 0x492010cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_9 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008d0 Address@com_sync_timer_global : 0x06400cd0 Address@app_sync_timer : 0x400808d0 Address@app_sync_timer_global : 0x40080cd0 Address@mot_sync_timer : 0x49200cd0 Address@mot_sync_timer_global : 0x492010d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_9 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008d4 Address@com_sync_timer_global : 0x06400cd4 Address@app_sync_timer : 0x400808d4 Address@app_sync_timer_global : 0x40080cd4 Address@mot_sync_timer : 0x49200cd4 Address@mot_sync_timer_global : 0x492010d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_10_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008d8 Address@com_sync_timer_global : 0x06400cd8 Address@app_sync_timer : 0x400808d8 Address@app_sync_timer_global : 0x40080cd8 Address@mot_sync_timer : 0x49200cd8 Address@mot_sync_timer_global : 0x492010d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_10 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008dc Address@com_sync_timer_global : 0x06400cdc Address@app_sync_timer : 0x400808dc Address@app_sync_timer_global : 0x40080cdc Address@mot_sync_timer : 0x49200cdc Address@mot_sync_timer_global : 0x492010dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_10 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008e0 Address@com_sync_timer_global : 0x06400ce0 Address@app_sync_timer : 0x400808e0 Address@app_sync_timer_global : 0x40080ce0 Address@mot_sync_timer : 0x49200ce0 Address@mot_sync_timer_global : 0x492010e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_11_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008e4 Address@com_sync_timer_global : 0x06400ce4 Address@app_sync_timer : 0x400808e4 Address@app_sync_timer_global : 0x40080ce4 Address@mot_sync_timer : 0x49200ce4 Address@mot_sync_timer_global : 0x492010e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_11 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008e8 Address@com_sync_timer_global : 0x06400ce8 Address@app_sync_timer : 0x400808e8 Address@app_sync_timer_global : 0x40080ce8 Address@mot_sync_timer : 0x49200ce8 Address@mot_sync_timer_global : 0x492010e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_11 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008ec Address@com_sync_timer_global : 0x06400cec Address@app_sync_timer : 0x400808ec Address@app_sync_timer_global : 0x40080cec Address@mot_sync_timer : 0x49200cec Address@mot_sync_timer_global : 0x492010ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_12_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008f0 Address@com_sync_timer_global : 0x06400cf0 Address@app_sync_timer : 0x400808f0 Address@app_sync_timer_global : 0x40080cf0 Address@mot_sync_timer : 0x49200cf0 Address@mot_sync_timer_global : 0x492010f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_12 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008f4 Address@com_sync_timer_global : 0x06400cf4 Address@app_sync_timer : 0x400808f4 Address@app_sync_timer_global : 0x40080cf4 Address@mot_sync_timer : 0x49200cf4 Address@mot_sync_timer_global : 0x492010f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_12 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008f8 Address@com_sync_timer_global : 0x06400cf8 Address@app_sync_timer : 0x400808f8 Address@app_sync_timer_global : 0x40080cf8 Address@mot_sync_timer : 0x49200cf8 Address@mot_sync_timer_global : 0x492010f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_13_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064008fc Address@com_sync_timer_global : 0x06400cfc Address@app_sync_timer : 0x400808fc Address@app_sync_timer_global : 0x40080cfc Address@mot_sync_timer : 0x49200cfc Address@mot_sync_timer_global : 0x492010fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_13 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400900 Address@com_sync_timer_global : 0x06400d00 Address@app_sync_timer : 0x40080900 Address@app_sync_timer_global : 0x40080d00 Address@mot_sync_timer : 0x49200d00 Address@mot_sync_timer_global : 0x49201100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_13 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400904 Address@com_sync_timer_global : 0x06400d04 Address@app_sync_timer : 0x40080904 Address@app_sync_timer_global : 0x40080d04 Address@mot_sync_timer : 0x49200d04 Address@mot_sync_timer_global : 0x49201104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_14_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400908 Address@com_sync_timer_global : 0x06400d08 Address@app_sync_timer : 0x40080908 Address@app_sync_timer_global : 0x40080d08 Address@mot_sync_timer : 0x49200d08 Address@mot_sync_timer_global : 0x49201108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_14 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640090c Address@com_sync_timer_global : 0x06400d0c Address@app_sync_timer : 0x4008090c Address@app_sync_timer_global : 0x40080d0c Address@mot_sync_timer : 0x49200d0c Address@mot_sync_timer_global : 0x4920110c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_14 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400910 Address@com_sync_timer_global : 0x06400d10 Address@app_sync_timer : 0x40080910 Address@app_sync_timer_global : 0x40080d10 Address@mot_sync_timer : 0x49200d10 Address@mot_sync_timer_global : 0x49201110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sub_phase_15_rld |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400914 Address@com_sync_timer_global : 0x06400d14 Address@app_sync_timer : 0x40080914 Address@app_sync_timer_global : 0x40080d14 Address@mot_sync_timer : 0x49200d14 Address@mot_sync_timer_global : 0x49201114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_sub_phase_15 | ||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400918 Address@com_sync_timer_global : 0x06400d18 Address@app_sync_timer : 0x40080918 Address@app_sync_timer_global : 0x40080d18 Address@mot_sync_timer : 0x49200d18 Address@mot_sync_timer_global : 0x49201118 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
val |
|
|
| sync_reload_sub_phase_offset_15 |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640091c Address@com_sync_timer_global : 0x06400d1c Address@app_sync_timer : 0x4008091c Address@app_sync_timer_global : 0x40080d1c Address@mot_sync_timer : 0x49200d1c Address@mot_sync_timer_global : 0x4920111c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
reload_value |
|
|
| sync_sync_gen_0_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400920 Address@com_sync_timer_global : 0x06400d20 Address@app_sync_timer : 0x40080920 Address@app_sync_timer_global : 0x40080d20 Address@mot_sync_timer : 0x49200d20 Address@mot_sync_timer_global : 0x49201120 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_0_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400924 Address@com_sync_timer_global : 0x06400d24 Address@app_sync_timer : 0x40080924 Address@app_sync_timer_global : 0x40080d24 Address@mot_sync_timer : 0x49200d24 Address@mot_sync_timer_global : 0x49201124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_1_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400928 Address@com_sync_timer_global : 0x06400d28 Address@app_sync_timer : 0x40080928 Address@app_sync_timer_global : 0x40080d28 Address@mot_sync_timer : 0x49200d28 Address@mot_sync_timer_global : 0x49201128 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_1_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640092c Address@com_sync_timer_global : 0x06400d2c Address@app_sync_timer : 0x4008092c Address@app_sync_timer_global : 0x40080d2c Address@mot_sync_timer : 0x49200d2c Address@mot_sync_timer_global : 0x4920112c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_2_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400930 Address@com_sync_timer_global : 0x06400d30 Address@app_sync_timer : 0x40080930 Address@app_sync_timer_global : 0x40080d30 Address@mot_sync_timer : 0x49200d30 Address@mot_sync_timer_global : 0x49201130 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_2_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400934 Address@com_sync_timer_global : 0x06400d34 Address@app_sync_timer : 0x40080934 Address@app_sync_timer_global : 0x40080d34 Address@mot_sync_timer : 0x49200d34 Address@mot_sync_timer_global : 0x49201134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_3_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400938 Address@com_sync_timer_global : 0x06400d38 Address@app_sync_timer : 0x40080938 Address@app_sync_timer_global : 0x40080d38 Address@mot_sync_timer : 0x49200d38 Address@mot_sync_timer_global : 0x49201138 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_3_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640093c Address@com_sync_timer_global : 0x06400d3c Address@app_sync_timer : 0x4008093c Address@app_sync_timer_global : 0x40080d3c Address@mot_sync_timer : 0x49200d3c Address@mot_sync_timer_global : 0x4920113c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_4_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400940 Address@com_sync_timer_global : 0x06400d40 Address@app_sync_timer : 0x40080940 Address@app_sync_timer_global : 0x40080d40 Address@mot_sync_timer : 0x49200d40 Address@mot_sync_timer_global : 0x49201140 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_4_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400944 Address@com_sync_timer_global : 0x06400d44 Address@app_sync_timer : 0x40080944 Address@app_sync_timer_global : 0x40080d44 Address@mot_sync_timer : 0x49200d44 Address@mot_sync_timer_global : 0x49201144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_5_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400948 Address@com_sync_timer_global : 0x06400d48 Address@app_sync_timer : 0x40080948 Address@app_sync_timer_global : 0x40080d48 Address@mot_sync_timer : 0x49200d48 Address@mot_sync_timer_global : 0x49201148 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_5_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640094c Address@com_sync_timer_global : 0x06400d4c Address@app_sync_timer : 0x4008094c Address@app_sync_timer_global : 0x40080d4c Address@mot_sync_timer : 0x49200d4c Address@mot_sync_timer_global : 0x4920114c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_6_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400950 Address@com_sync_timer_global : 0x06400d50 Address@app_sync_timer : 0x40080950 Address@app_sync_timer_global : 0x40080d50 Address@mot_sync_timer : 0x49200d50 Address@mot_sync_timer_global : 0x49201150 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_6_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400954 Address@com_sync_timer_global : 0x06400d54 Address@app_sync_timer : 0x40080954 Address@app_sync_timer_global : 0x40080d54 Address@mot_sync_timer : 0x49200d54 Address@mot_sync_timer_global : 0x49201154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_7_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400958 Address@com_sync_timer_global : 0x06400d58 Address@app_sync_timer : 0x40080958 Address@app_sync_timer_global : 0x40080d58 Address@mot_sync_timer : 0x49200d58 Address@mot_sync_timer_global : 0x49201158 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_7_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640095c Address@com_sync_timer_global : 0x06400d5c Address@app_sync_timer : 0x4008095c Address@app_sync_timer_global : 0x40080d5c Address@mot_sync_timer : 0x49200d5c Address@mot_sync_timer_global : 0x4920115c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_8_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400960 Address@com_sync_timer_global : 0x06400d60 Address@app_sync_timer : 0x40080960 Address@app_sync_timer_global : 0x40080d60 Address@mot_sync_timer : 0x49200d60 Address@mot_sync_timer_global : 0x49201160 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_8_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400964 Address@com_sync_timer_global : 0x06400d64 Address@app_sync_timer : 0x40080964 Address@app_sync_timer_global : 0x40080d64 Address@mot_sync_timer : 0x49200d64 Address@mot_sync_timer_global : 0x49201164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_9_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400968 Address@com_sync_timer_global : 0x06400d68 Address@app_sync_timer : 0x40080968 Address@app_sync_timer_global : 0x40080d68 Address@mot_sync_timer : 0x49200d68 Address@mot_sync_timer_global : 0x49201168 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_9_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640096c Address@com_sync_timer_global : 0x06400d6c Address@app_sync_timer : 0x4008096c Address@app_sync_timer_global : 0x40080d6c Address@mot_sync_timer : 0x49200d6c Address@mot_sync_timer_global : 0x4920116c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_10_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400970 Address@com_sync_timer_global : 0x06400d70 Address@app_sync_timer : 0x40080970 Address@app_sync_timer_global : 0x40080d70 Address@mot_sync_timer : 0x49200d70 Address@mot_sync_timer_global : 0x49201170 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_10_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400974 Address@com_sync_timer_global : 0x06400d74 Address@app_sync_timer : 0x40080974 Address@app_sync_timer_global : 0x40080d74 Address@mot_sync_timer : 0x49200d74 Address@mot_sync_timer_global : 0x49201174 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_11_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400978 Address@com_sync_timer_global : 0x06400d78 Address@app_sync_timer : 0x40080978 Address@app_sync_timer_global : 0x40080d78 Address@mot_sync_timer : 0x49200d78 Address@mot_sync_timer_global : 0x49201178 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_11_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640097c Address@com_sync_timer_global : 0x06400d7c Address@app_sync_timer : 0x4008097c Address@app_sync_timer_global : 0x40080d7c Address@mot_sync_timer : 0x49200d7c Address@mot_sync_timer_global : 0x4920117c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_12_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400980 Address@com_sync_timer_global : 0x06400d80 Address@app_sync_timer : 0x40080980 Address@app_sync_timer_global : 0x40080d80 Address@mot_sync_timer : 0x49200d80 Address@mot_sync_timer_global : 0x49201180 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_12_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400984 Address@com_sync_timer_global : 0x06400d84 Address@app_sync_timer : 0x40080984 Address@app_sync_timer_global : 0x40080d84 Address@mot_sync_timer : 0x49200d84 Address@mot_sync_timer_global : 0x49201184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_13_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400988 Address@com_sync_timer_global : 0x06400d88 Address@app_sync_timer : 0x40080988 Address@app_sync_timer_global : 0x40080d88 Address@mot_sync_timer : 0x49200d88 Address@mot_sync_timer_global : 0x49201188 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_13_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640098c Address@com_sync_timer_global : 0x06400d8c Address@app_sync_timer : 0x4008098c Address@app_sync_timer_global : 0x40080d8c Address@mot_sync_timer : 0x49200d8c Address@mot_sync_timer_global : 0x4920118c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_14_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400990 Address@com_sync_timer_global : 0x06400d90 Address@app_sync_timer : 0x40080990 Address@app_sync_timer_global : 0x40080d90 Address@mot_sync_timer : 0x49200d90 Address@mot_sync_timer_global : 0x49201190 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_14_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400994 Address@com_sync_timer_global : 0x06400d94 Address@app_sync_timer : 0x40080994 Address@app_sync_timer_global : 0x40080d94 Address@mot_sync_timer : 0x49200d94 Address@mot_sync_timer_global : 0x49201194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_15_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400998 Address@com_sync_timer_global : 0x06400d98 Address@app_sync_timer : 0x40080998 Address@app_sync_timer_global : 0x40080d98 Address@mot_sync_timer : 0x49200d98 Address@mot_sync_timer_global : 0x49201198 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_15_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x0640099c Address@com_sync_timer_global : 0x06400d9c Address@app_sync_timer : 0x4008099c Address@app_sync_timer_global : 0x40080d9c Address@mot_sync_timer : 0x49200d9c Address@mot_sync_timer_global : 0x4920119c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_16_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009a0 Address@com_sync_timer_global : 0x06400da0 Address@app_sync_timer : 0x400809a0 Address@app_sync_timer_global : 0x40080da0 Address@mot_sync_timer : 0x49200da0 Address@mot_sync_timer_global : 0x492011a0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_16_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009a4 Address@com_sync_timer_global : 0x06400da4 Address@app_sync_timer : 0x400809a4 Address@app_sync_timer_global : 0x40080da4 Address@mot_sync_timer : 0x49200da4 Address@mot_sync_timer_global : 0x492011a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_17_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009a8 Address@com_sync_timer_global : 0x06400da8 Address@app_sync_timer : 0x400809a8 Address@app_sync_timer_global : 0x40080da8 Address@mot_sync_timer : 0x49200da8 Address@mot_sync_timer_global : 0x492011a8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_17_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009ac Address@com_sync_timer_global : 0x06400dac Address@app_sync_timer : 0x400809ac Address@app_sync_timer_global : 0x40080dac Address@mot_sync_timer : 0x49200dac Address@mot_sync_timer_global : 0x492011ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_18_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009b0 Address@com_sync_timer_global : 0x06400db0 Address@app_sync_timer : 0x400809b0 Address@app_sync_timer_global : 0x40080db0 Address@mot_sync_timer : 0x49200db0 Address@mot_sync_timer_global : 0x492011b0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_18_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009b4 Address@com_sync_timer_global : 0x06400db4 Address@app_sync_timer : 0x400809b4 Address@app_sync_timer_global : 0x40080db4 Address@mot_sync_timer : 0x49200db4 Address@mot_sync_timer_global : 0x492011b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_19_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009b8 Address@com_sync_timer_global : 0x06400db8 Address@app_sync_timer : 0x400809b8 Address@app_sync_timer_global : 0x40080db8 Address@mot_sync_timer : 0x49200db8 Address@mot_sync_timer_global : 0x492011b8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_19_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009bc Address@com_sync_timer_global : 0x06400dbc Address@app_sync_timer : 0x400809bc Address@app_sync_timer_global : 0x40080dbc Address@mot_sync_timer : 0x49200dbc Address@mot_sync_timer_global : 0x492011bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_20_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009c0 Address@com_sync_timer_global : 0x06400dc0 Address@app_sync_timer : 0x400809c0 Address@app_sync_timer_global : 0x40080dc0 Address@mot_sync_timer : 0x49200dc0 Address@mot_sync_timer_global : 0x492011c0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_20_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009c4 Address@com_sync_timer_global : 0x06400dc4 Address@app_sync_timer : 0x400809c4 Address@app_sync_timer_global : 0x40080dc4 Address@mot_sync_timer : 0x49200dc4 Address@mot_sync_timer_global : 0x492011c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_21_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009c8 Address@com_sync_timer_global : 0x06400dc8 Address@app_sync_timer : 0x400809c8 Address@app_sync_timer_global : 0x40080dc8 Address@mot_sync_timer : 0x49200dc8 Address@mot_sync_timer_global : 0x492011c8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_21_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009cc Address@com_sync_timer_global : 0x06400dcc Address@app_sync_timer : 0x400809cc Address@app_sync_timer_global : 0x40080dcc Address@mot_sync_timer : 0x49200dcc Address@mot_sync_timer_global : 0x492011cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_22_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009d0 Address@com_sync_timer_global : 0x06400dd0 Address@app_sync_timer : 0x400809d0 Address@app_sync_timer_global : 0x40080dd0 Address@mot_sync_timer : 0x49200dd0 Address@mot_sync_timer_global : 0x492011d0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_22_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009d4 Address@com_sync_timer_global : 0x06400dd4 Address@app_sync_timer : 0x400809d4 Address@app_sync_timer_global : 0x40080dd4 Address@mot_sync_timer : 0x49200dd4 Address@mot_sync_timer_global : 0x492011d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_23_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009d8 Address@com_sync_timer_global : 0x06400dd8 Address@app_sync_timer : 0x400809d8 Address@app_sync_timer_global : 0x40080dd8 Address@mot_sync_timer : 0x49200dd8 Address@mot_sync_timer_global : 0x492011d8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_23_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009dc Address@com_sync_timer_global : 0x06400ddc Address@app_sync_timer : 0x400809dc Address@app_sync_timer_global : 0x40080ddc Address@mot_sync_timer : 0x49200ddc Address@mot_sync_timer_global : 0x492011dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_24_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009e0 Address@com_sync_timer_global : 0x06400de0 Address@app_sync_timer : 0x400809e0 Address@app_sync_timer_global : 0x40080de0 Address@mot_sync_timer : 0x49200de0 Address@mot_sync_timer_global : 0x492011e0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_24_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009e4 Address@com_sync_timer_global : 0x06400de4 Address@app_sync_timer : 0x400809e4 Address@app_sync_timer_global : 0x40080de4 Address@mot_sync_timer : 0x49200de4 Address@mot_sync_timer_global : 0x492011e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_25_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009e8 Address@com_sync_timer_global : 0x06400de8 Address@app_sync_timer : 0x400809e8 Address@app_sync_timer_global : 0x40080de8 Address@mot_sync_timer : 0x49200de8 Address@mot_sync_timer_global : 0x492011e8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_25_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009ec Address@com_sync_timer_global : 0x06400dec Address@app_sync_timer : 0x400809ec Address@app_sync_timer_global : 0x40080dec Address@mot_sync_timer : 0x49200dec Address@mot_sync_timer_global : 0x492011ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_26_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009f0 Address@com_sync_timer_global : 0x06400df0 Address@app_sync_timer : 0x400809f0 Address@app_sync_timer_global : 0x40080df0 Address@mot_sync_timer : 0x49200df0 Address@mot_sync_timer_global : 0x492011f0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_26_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009f4 Address@com_sync_timer_global : 0x06400df4 Address@app_sync_timer : 0x400809f4 Address@app_sync_timer_global : 0x40080df4 Address@mot_sync_timer : 0x49200df4 Address@mot_sync_timer_global : 0x492011f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_27_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009f8 Address@com_sync_timer_global : 0x06400df8 Address@app_sync_timer : 0x400809f8 Address@app_sync_timer_global : 0x40080df8 Address@mot_sync_timer : 0x49200df8 Address@mot_sync_timer_global : 0x492011f8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_27_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x064009fc Address@com_sync_timer_global : 0x06400dfc Address@app_sync_timer : 0x400809fc Address@app_sync_timer_global : 0x40080dfc Address@mot_sync_timer : 0x49200dfc Address@mot_sync_timer_global : 0x492011fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_28_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a00 Address@com_sync_timer_global : 0x06400e00 Address@app_sync_timer : 0x40080a00 Address@app_sync_timer_global : 0x40080e00 Address@mot_sync_timer : 0x49200e00 Address@mot_sync_timer_global : 0x49201200 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_28_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a04 Address@com_sync_timer_global : 0x06400e04 Address@app_sync_timer : 0x40080a04 Address@app_sync_timer_global : 0x40080e04 Address@mot_sync_timer : 0x49200e04 Address@mot_sync_timer_global : 0x49201204 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_gen_29_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a08 Address@com_sync_timer_global : 0x06400e08 Address@app_sync_timer : 0x40080a08 Address@app_sync_timer_global : 0x40080e08 Address@mot_sync_timer : 0x49200e08 Address@mot_sync_timer_global : 0x49201208 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 5 | 0x0 |
sub_phase |
|||||||||
| 4 - 0 | "00000" |
sub_phase_sel |
|
||||||||
| sync_sync_gen_29_base_phase |
|
|||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a0c Address@com_sync_timer_global : 0x06400e0c Address@app_sync_timer : 0x40080a0c Address@app_sync_timer_global : 0x40080e0c Address@mot_sync_timer : 0x49200e0c Address@mot_sync_timer_global : 0x4920120c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| sync_sync_out_0_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a10 Address@com_sync_timer_global : 0x06400e10 Address@app_sync_timer : 0x40080a10 Address@app_sync_timer_global : 0x40080e10 Address@mot_sync_timer : 0x49200e10 Address@mot_sync_timer_global : 0x49201210 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_1_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a14 Address@com_sync_timer_global : 0x06400e14 Address@app_sync_timer : 0x40080a14 Address@app_sync_timer_global : 0x40080e14 Address@mot_sync_timer : 0x49200e14 Address@mot_sync_timer_global : 0x49201214 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_2_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a18 Address@com_sync_timer_global : 0x06400e18 Address@app_sync_timer : 0x40080a18 Address@app_sync_timer_global : 0x40080e18 Address@mot_sync_timer : 0x49200e18 Address@mot_sync_timer_global : 0x49201218 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_3_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a1c Address@com_sync_timer_global : 0x06400e1c Address@app_sync_timer : 0x40080a1c Address@app_sync_timer_global : 0x40080e1c Address@mot_sync_timer : 0x49200e1c Address@mot_sync_timer_global : 0x4920121c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_4_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a20 Address@com_sync_timer_global : 0x06400e20 Address@app_sync_timer : 0x40080a20 Address@app_sync_timer_global : 0x40080e20 Address@mot_sync_timer : 0x49200e20 Address@mot_sync_timer_global : 0x49201220 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_5_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a24 Address@com_sync_timer_global : 0x06400e24 Address@app_sync_timer : 0x40080a24 Address@app_sync_timer_global : 0x40080e24 Address@mot_sync_timer : 0x49200e24 Address@mot_sync_timer_global : 0x49201224 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_6_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a28 Address@com_sync_timer_global : 0x06400e28 Address@app_sync_timer : 0x40080a28 Address@app_sync_timer_global : 0x40080e28 Address@mot_sync_timer : 0x49200e28 Address@mot_sync_timer_global : 0x49201228 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| sync_sync_out_7_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@com_sync_timer : 0x06400a2c Address@com_sync_timer_global : 0x06400e2c Address@app_sync_timer : 0x40080a2c Address@app_sync_timer_global : 0x40080e2c Address@mot_sync_timer : 0x49200e2c Address@mot_sync_timer_global : 0x4920122c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |||||||
| 10 - 2 | 0x0 |
duration |
|
|||||||
| 1 - 0 | "00" |
polarity |
|
|||||||
| can_fd_receive_buffer_random_access_region_start |
|
|||
| R |
Address@com_can_fd : 0x06420000 Address@app_can_fd : 0x400d0000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| can_fd_receive_buffer_random_access_region_end |
|
|||
| R |
Address@com_can_fd : 0x064200fc Address@app_can_fd : 0x400d00fc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| can_fd_receive_buffer_fifo_region_start |
|
|||
| R |
Address@com_can_fd : 0x06420100 Address@app_can_fd : 0x400d0100 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| can_fd_receive_buffer_fifo_region_end |
|
|||
| R |
Address@com_can_fd : 0x064201fc Address@app_can_fd : 0x400d01fc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| can_fd_receive_buffer_srb_cmd |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06420400 Address@app_can_fd : 0x400d0400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 4 | "00" |
RDB |
|
|
| 3 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
FOR |
|
|
| can_fd_receive_buffer_srb_ien |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06420404 Address@app_can_fd : 0x400d0404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 - 12 | "00" |
DUF |
|
|
| 11 - 10 | "00" |
DOF |
|
|
| 9 - 8 | "00" |
DPD |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
RPA |
|
|
| 3 | "0" |
RUF |
|
|
| 2 | "0" |
RMT |
|
|
| 1 | "0" |
RAL |
|
|
| 0 | "0" |
IA |
|
|
| can_fd_receive_buffer_srb_istat |
|
|||
| R |
Address@com_can_fd : 0x06420408 Address@app_can_fd : 0x400d0408 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 14 | - |
reserved | ||
| 13 - 12 | DUF |
|
||
| 11 - 10 | DOF |
|
||
| 9 - 8 | DPD |
|
||
| 7 - 5 | - |
reserved | ||
| 4 | RPA |
|
||
| 3 | RUF |
|
||
| 2 | RMT |
|
||
| 1 | RAL |
|
||
| 0 | IA |
|
||
| can_fd_receive_buffer_srb_irq |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x0642040c Address@app_can_fd : 0x400d040c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 - 12 | "00" |
DUF |
|
|
| 11 - 10 | "00" |
DOF |
|
|
| 9 - 8 | "00" |
DPD |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
RPA |
|
|
| 3 | "0" |
RUF |
|
|
| 2 | "0" |
RMT |
|
|
| 1 | "0" |
RAL |
|
|
| 0 | "0" |
IA |
|
|
| can_fd_receive_buffer_srb_stat |
|
|||
| R |
Address@com_can_fd : 0x06420410 Address@app_can_fd : 0x400d0410 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 25 | - |
reserved | ||
| 24 | DMA |
|
||
| 23 - 21 | - |
reserved | ||
| 20 - 16 | FOFS |
|
||
| 15 | DI |
|
||
| 14 | EOP |
|
||
| 13 | DA |
|
||
| 12 - 8 | LPOS |
|
||
| 7 - 3 | - |
reserved | ||
| 2 - 0 | CHID |
|
||
| can_fd_receive_buffer_srb_rx_npackets |
|
|||
| R |
Address@com_can_fd : 0x06420414 Address@app_can_fd : 0x400d0414 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 16 | MAX_COUNT |
|
||
| 15 - 8 | - |
reserved | ||
| 7 - 0 | COUNT |
|
||
| can_fd_receive_buffer_srb_ctrl |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06420418 Address@app_can_fd : 0x400d0418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0x0 |
DMA_BASE_ADDR |
|
|
| 7 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
DEN |
|
|
| can_fd_can_time_stamp_time_ts_l |
|
|||
| R |
Address@com_can_fd : 0x06420800 Address@app_can_fd : 0x400d0800 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | TS_L |
|
||
| can_fd_can_time_stamp_time_ts_h |
|
|||
| R |
Address@com_can_fd : 0x06420804 Address@app_can_fd : 0x400d0804 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | TS_H |
|
||
| can_fd_can_time_stamp_time_mode |
|
|||||||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06420808 Address@app_can_fd : 0x400d0808 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 23 | 0 |
- |
reserved | |||||
| 22 - 16 | "0000000" |
PRESCALER |
|
|||||
| 15 - 3 | 0 |
- |
reserved | |||||
| 2 | "0" |
CAPTSRC |
|
|||||
| 1 | "0" |
CAPTEN |
|
|||||
| 0 | "0" |
INTEN |
|
|||||
| can_fd_can_time_stamp_time_interval |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x0642080c Address@app_can_fd : 0x400d080c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
INTERVAL |
|
|
| can_fd_can_time_stamp_time_cmd |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06420810 Address@app_can_fd : 0x400d0810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
RESTART |
|
|
| 0 | "0" |
CAPT |
|
|
| can_fd_can_time_stamp_time_capt_l |
|
|||
| R |
Address@com_can_fd : 0x06420814 Address@app_can_fd : 0x400d0814 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | CAPT_L |
|
||
| can_fd_can_time_stamp_time_capt_h |
|
|||
| R |
Address@com_can_fd : 0x06420818 Address@app_can_fd : 0x400d0818 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | CAPT_H |
|
||
| can_fd_build_data_rev_info |
|
|||
| R |
Address@com_can_fd : 0x06420c00 Address@app_can_fd : 0x400d0c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | MOD |
|
||
| 30 - 0 | REV |
|
||
| can_fd_global_signals_global_interrupt |
|
|||
| R |
Address@com_can_fd : 0x06420e00 Address@app_can_fd : 0x400d0e00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | OTH_N3 |
|
||
| 30 - 29 | - |
reserved | ||
| 28 | TE_N3 |
|
||
| 27 | TFD_N3 |
|
||
| 26 | ABD_N3 |
|
||
| 25 | TNE_N3 |
|
||
| 24 | OTH_N2 |
|
||
| 23 - 22 | - |
reserved | ||
| 21 | TE_N2 |
|
||
| 20 | TFD_N2 |
|
||
| 19 | ABD_N2 |
|
||
| 18 | TNE_N2 |
|
||
| 17 | OTH_N1 |
|
||
| 16 - 15 | - |
reserved | ||
| 14 | TE_N1 |
|
||
| 13 | TFD_N1 |
|
||
| 12 | ABD_N1 |
|
||
| 11 | TNE_N1 |
|
||
| 10 | OTH_N0 |
|
||
| 9 - 8 | - |
reserved | ||
| 7 | TE_N0 |
|
||
| 6 | TFD_N0 |
|
||
| 5 | ABD_N0 |
|
||
| 4 | TNE_N0 |
|
||
| 3 | SRB_O |
|
||
| 2 - 1 | - |
reserved | ||
| 0 | RPA |
|
||
| can_fd_can_channel_0_random_access_region_start |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06421800 Address@app_can_fd : 0x400d1800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_random_access_region_end |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x064218fc Address@app_can_fd : 0x400d18fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_fifo_region_start |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06421900 Address@app_can_fd : 0x400d1900 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_fifo_region_end |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x064219fc Address@app_can_fd : 0x400d19fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_control_region_start |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06421a00 Address@app_can_fd : 0x400d1a00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_control_region_end |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06421bfc Address@app_can_fd : 0x400d1bfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| can_fd_can_channel_0_kcan_cmd |
|
|||
| W |
0x00000000 |
Address@com_can_fd : 0x06421c00 Address@app_can_fd : 0x400d1c00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 - 16 | 0x0 |
EC |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
RRQ |
|
|
| 4 | "0" |
WTEC |
|
|
| 3 | "0" |
WREC |
|
|
| 2 | "0" |
FTX |
|
|
| 1 | "0" |
AT |
|
|
| 0 | "0" |
SRQ |
|
|
| can_fd_can_channel_0_kcan_ien |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c08 Address@app_can_fd : 0x400d1c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
TNE |
|
|
| 17 | "0" |
TAL |
|
|
| 16 | "0" |
TE |
|
|
| 15 | "0" |
TOF |
|
|
| 14 | "0" |
TFD |
|
|
| 13 | "0" |
ABD |
|
|
| 12 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ROF |
|
|
| 4 | "0" |
IDLE |
|
|
| 3 | "0" |
FDIC |
|
|
| 2 | "0" |
BPP |
|
|
| 1 | "0" |
TAE |
|
|
| 0 | "0" |
TAR |
|
|
| can_fd_can_channel_0_kcan_istat |
|
|||
| R |
Address@com_can_fd : 0x06421c0c Address@app_can_fd : 0x400d1c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 19 | - |
reserved | ||
| 18 | TNE |
|
||
| 17 | TAL |
|
||
| 16 | TE |
|
||
| 15 | TOF |
|
||
| 14 | TFD |
|
||
| 13 | ABD |
|
||
| 12 - 6 | - |
reserved | ||
| 5 | ROF |
|
||
| 4 | IDLE |
|
||
| 3 | FDIC |
|
||
| 2 | BPP |
|
||
| 1 | TAE |
|
||
| 0 | TAR |
|
||
| can_fd_can_channel_0_kcan_irq |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c10 Address@app_can_fd : 0x400d1c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
TNE |
|
|
| 17 | "0" |
TAL |
|
|
| 16 | "0" |
TE |
|
|
| 15 | "0" |
TOF |
|
|
| 14 | "0" |
TFD |
|
|
| 13 | "0" |
ABD |
|
|
| 12 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ROF |
|
|
| 4 | "0" |
IDLE |
|
|
| 3 | "0" |
FDIC |
|
|
| 2 | "0" |
BPP |
|
|
| 1 | "0" |
TAE |
|
|
| 0 | "0" |
TAR |
|
|
| can_fd_can_channel_0_kcan_tx_npackets |
|
|||
| R |
Address@com_can_fd : 0x06421c14 Address@app_can_fd : 0x400d1c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 16 | MAX_COUNT |
|
||
| 15 - 8 | - |
reserved | ||
| 7 - 0 | COUNT |
|
||
| can_fd_can_channel_0_kcan_stat |
|
|||
| R |
Address@com_can_fd : 0x06421c18 Address@app_can_fd : 0x400d1c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | CMD_SEQ_NO |
|
||
| 23 - 20 | - |
reserved | ||
| 19 | FD |
|
||
| 18 - 16 | - |
reserved | ||
| 15 | IRM |
|
||
| 14 | RMR |
|
||
| 13 | TXI |
|
||
| 12 | TXE |
|
||
| 11 | BOFF |
|
||
| 10 | IDLE |
|
||
| 9 | IRQ |
|
||
| 8 | TXFR |
|
||
| 7 | AR |
|
||
| 6 | SRP |
|
||
| 5 - 0 | - |
reserved | ||
| can_fd_can_channel_0_kcan_mode |
|
|||
| R/W |
0x00008560 |
Address@com_can_fd : 0x06421c1c Address@app_can_fd : 0x400d1c1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
CCM |
|
|
| 30 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
AAM |
|
|
| 20 | "0" |
APT |
|
|
| 19 | 0 |
- |
reserved | |
| 18 - 16 | "000" |
CHID |
|
|
| 15 | "1" |
NIFDEN |
|
|
| 14 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
EPEN |
|
|
| 11 | "0" |
MRRQ |
|
|
| 10 | "1" |
DWH |
|
|
| 9 | "0" |
LOM |
|
|
| 8 | "1" |
RM |
|
|
| 7 - 0 | "01100000" |
EWL |
|
|
| can_fd_can_channel_0_kcan_btrn |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c20 Address@app_can_fd : 0x400d1c20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 26 | "00000" |
TSEG2 |
|
|
| 25 - 17 | 0x0 |
TSEG1 |
|
|
| 16 - 13 | "0000" |
SJQ |
|
|
| 12 - 0 | 0x0 |
BRP |
|
|
| can_fd_can_channel_0_kcan_blp |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c24 Address@app_can_fd : 0x400d1c24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
PRESCALER |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 - 0 | 0x0 |
INTERVAL |
|
|
| can_fd_can_channel_0_kcan_btrd |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c28 Address@app_can_fd : 0x400d1c28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 26 | "00000" |
TSEG2 |
|
|
| 25 - 17 | 0x0 |
TSEG1 |
|
|
| 16 - 13 | "0000" |
SJW |
|
|
| 12 - 0 | 0x0 |
BRP |
|
|
| can_fd_can_channel_0_kcan_tx_rate_limit |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06421c2c Address@app_can_fd : 0x400d1c2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 0 | 0x0 |
DELAY |
|
|
| can_fd_can_channel_0_kcan_ssp_ctrl |
|
|||
| R/W |
0x00030000 |
Address@com_can_fd : 0x06421c34 Address@app_can_fd : 0x400d1c34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
MTRD |
|
|
| 17 | "1" |
RXRSP |
|
|
| 16 | "1" |
TRDCE |
|
|
| 15 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
OFFSET |
|
|
| can_fd_can_channel_1_base_addr |
|
|||
| R/W |
0x00000000 |
Address@com_can_fd : 0x06422000 Address@app_can_fd : 0x400d2000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mtgy_cmd |
| 1 | 4 | R | mtgy_stat |
| 2 | 8 | R/W | mtgy_irq_raw |
| 3 | c | R | mtgy_irq_masked |
| 4 | 10 | R/W | mtgy_irq_msk_set |
| 5 | 14 | R/W | mtgy_irq_msk_reset |
| 6-3ff | 18-ffc | - | reserved |
| 400 | 1000 | R/W | mtgy_op_tc0 |
| 401 | 1004 | R/W | mtgy_op_tc1 |
| 402 | 1008 | R/W | mtgy_op_tc2 |
| 403 | 100c | R/W | mtgy_op_tc3 |
| 404 | 1010 | R/W | mtgy_op_tc4 |
| 405 | 1014 | R/W | mtgy_op_tc5 |
| 406 | 1018 | R/W | mtgy_op_tc6 |
| 407 | 101c | R/W | mtgy_op_tc7 |
| 408 | 1020 | R/W | mtgy_op_tc8 |
| 409 | 1024 | R/W | mtgy_op_tc9 |
| 40a | 1028 | R/W | mtgy_op_tc10 |
| 40b | 102c | R/W | mtgy_op_tc11 |
| 40c | 1030 | R/W | mtgy_op_tc12 |
| 40d | 1034 | R/W | mtgy_op_tc13 |
| 40e | 1038 | R/W | mtgy_op_tc14 |
| 40f | 103c | R/W | mtgy_op_tc15 |
| 410 | 1040 | R/W | mtgy_op_tc16 |
| 411 | 1044 | R/W | mtgy_op_tc17 |
| 412 | 1048 | R/W | mtgy_op_tc18 |
| 413 | 104c | R/W | mtgy_op_tc19 |
| 414 | 1050 | R/W | mtgy_op_tc20 |
| 415 | 1054 | R/W | mtgy_op_tc21 |
| 416 | 1058 | R/W | mtgy_op_tc22 |
| 417 | 105c | R/W | mtgy_op_tc23 |
| 418 | 1060 | R/W | mtgy_op_tc24 |
| 419 | 1064 | R/W | mtgy_op_tc25 |
| 41a | 1068 | R/W | mtgy_op_tc26 |
| 41b | 106c | R/W | mtgy_op_tc27 |
| 41c | 1070 | R/W | mtgy_op_tc28 |
| 41d | 1074 | R/W | mtgy_op_tc29 |
| 41e | 1078 | R/W | mtgy_op_tc30 |
| 41f | 107c | R/W | mtgy_op_tc31 |
| 420 | 1080 | R/W | mtgy_op_tc32 |
| 421 | 1084 | R/W | mtgy_op_tc33 |
| 422 | 1088 | R/W | mtgy_op_tc34 |
| 423 | 108c | R/W | mtgy_op_tc35 |
| 424 | 1090 | R/W | mtgy_op_tc36 |
| 425 | 1094 | R/W | mtgy_op_tc37 |
| 426 | 1098 | R/W | mtgy_op_tc38 |
| 427 | 109c | R/W | mtgy_op_tc39 |
| 428 | 10a0 | R/W | mtgy_op_tc40 |
| 429 | 10a4 | R/W | mtgy_op_tc41 |
| 42a | 10a8 | R/W | mtgy_op_tc42 |
| 42b | 10ac | R/W | mtgy_op_tc43 |
| 42c | 10b0 | R/W | mtgy_op_tc44 |
| 42d | 10b4 | R/W | mtgy_op_tc45 |
| 42e | 10b8 | R/W | mtgy_op_tc46 |
| 42f | 10bc | R/W | mtgy_op_tc47 |
| 430 | 10c0 | R/W | mtgy_op_tc48 |
| 431 | 10c4 | R/W | mtgy_op_tc49 |
| 432 | 10c8 | R/W | mtgy_op_tc50 |
| 433 | 10cc | R/W | mtgy_op_tc51 |
| 434 | 10d0 | R/W | mtgy_op_tc52 |
| 435 | 10d4 | R/W | mtgy_op_tc53 |
| 436 | 10d8 | R/W | mtgy_op_tc54 |
| 437 | 10dc | R/W | mtgy_op_tc55 |
| 438 | 10e0 | R/W | mtgy_op_tc56 |
| 439 | 10e4 | R/W | mtgy_op_tc57 |
| 43a | 10e8 | R/W | mtgy_op_tc58 |
| 43b | 10ec | R/W | mtgy_op_tc59 |
| 43c | 10f0 | R/W | mtgy_op_tc60 |
| 43d | 10f4 | R/W | mtgy_op_tc61 |
| 43e | 10f8 | R/W | mtgy_op_tc62 |
| 43f | 10fc | R/W | mtgy_op_tc63 |
| 440 | 1100 | R/W | mtgy_op_tc64 |
| 441 | 1104 | R/W | mtgy_op_tc65 |
| 442 | 1108 | R/W | mtgy_op_tc66 |
| 443 | 110c | R/W | mtgy_op_tc67 |
| 444 | 1110 | R/W | mtgy_op_tc68 |
| 445 | 1114 | R/W | mtgy_op_tc69 |
| 446 | 1118 | R/W | mtgy_op_tc70 |
| 447 | 111c | R/W | mtgy_op_tc71 |
| 448 | 1120 | R/W | mtgy_op_tc72 |
| 449 | 1124 | R/W | mtgy_op_tc73 |
| 44a | 1128 | R/W | mtgy_op_tc74 |
| 44b | 112c | R/W | mtgy_op_tc75 |
| 44c | 1130 | R/W | mtgy_op_tc76 |
| 44d | 1134 | R/W | mtgy_op_tc77 |
| 44e | 1138 | R/W | mtgy_op_tc78 |
| 44f | 113c | R/W | mtgy_op_tc79 |
| 450 | 1140 | R/W | mtgy_op_tc80 |
| 451 | 1144 | R/W | mtgy_op_tc81 |
| 452 | 1148 | R/W | mtgy_op_tc82 |
| 453 | 114c | R/W | mtgy_op_tc83 |
| 454 | 1150 | R/W | mtgy_op_tc84 |
| 455 | 1154 | R/W | mtgy_op_tc85 |
| 456 | 1158 | R/W | mtgy_op_tc86 |
| 457 | 115c | R/W | mtgy_op_tc87 |
| 458 | 1160 | R/W | mtgy_op_tc88 |
| 459 | 1164 | R/W | mtgy_op_tc89 |
| 45a | 1168 | R/W | mtgy_op_tc90 |
| 45b | 116c | R/W | mtgy_op_tc91 |
| 45c | 1170 | R/W | mtgy_op_tc92 |
| 45d | 1174 | R/W | mtgy_op_tc93 |
| 45e | 1178 | R/W | mtgy_op_tc94 |
| 45f | 117c | R/W | mtgy_op_tc95 |
| 460 | 1180 | R/W | mtgy_op_tc96 |
| 461 | 1184 | R/W | mtgy_op_tc97 |
| 462 | 1188 | R/W | mtgy_op_tc98 |
| 463 | 118c | R/W | mtgy_op_tc99 |
| 464 | 1190 | R/W | mtgy_op_tc100 |
| 465 | 1194 | R/W | mtgy_op_tc101 |
| 466 | 1198 | R/W | mtgy_op_tc102 |
| 467 | 119c | R/W | mtgy_op_tc103 |
| 468 | 11a0 | R/W | mtgy_op_tc104 |
| 469 | 11a4 | R/W | mtgy_op_tc105 |
| 46a | 11a8 | R/W | mtgy_op_tc106 |
| 46b | 11ac | R/W | mtgy_op_tc107 |
| 46c | 11b0 | R/W | mtgy_op_tc108 |
| 46d | 11b4 | R/W | mtgy_op_tc109 |
| 46e | 11b8 | R/W | mtgy_op_tc110 |
| 46f | 11bc | R/W | mtgy_op_tc111 |
| 470 | 11c0 | R/W | mtgy_op_tc112 |
| 471 | 11c4 | R/W | mtgy_op_tc113 |
| 472 | 11c8 | R/W | mtgy_op_tc114 |
| 473 | 11cc | R/W | mtgy_op_tc115 |
| 474 | 11d0 | R/W | mtgy_op_tc116 |
| 475 | 11d4 | R/W | mtgy_op_tc117 |
| 476 | 11d8 | R/W | mtgy_op_tc118 |
| 477 | 11dc | R/W | mtgy_op_tc119 |
| 478 | 11e0 | R/W | mtgy_op_tc120 |
| 479 | 11e4 | R/W | mtgy_op_tc121 |
| 47a | 11e8 | R/W | mtgy_op_tc122 |
| 47b | 11ec | R/W | mtgy_op_tc123 |
| 47c | 11f0 | R/W | mtgy_op_tc124 |
| 47d | 11f4 | R/W | mtgy_op_tc125 |
| 47e | 11f8 | R/W | mtgy_op_tc126 |
| 47f | 11fc | R/W | mtgy_op_tc127 |
| 480 | 1200 | R/W | mtgy_op_ts0 |
| 481 | 1204 | R/W | mtgy_op_ts1 |
| 482 | 1208 | R/W | mtgy_op_ts2 |
| 483 | 120c | R/W | mtgy_op_ts3 |
| 484 | 1210 | R/W | mtgy_op_ts4 |
| 485 | 1214 | R/W | mtgy_op_ts5 |
| 486 | 1218 | R/W | mtgy_op_ts6 |
| 487 | 121c | R/W | mtgy_op_ts7 |
| 488 | 1220 | R/W | mtgy_op_ts8 |
| 489 | 1224 | R/W | mtgy_op_ts9 |
| 48a | 1228 | R/W | mtgy_op_ts10 |
| 48b | 122c | R/W | mtgy_op_ts11 |
| 48c | 1230 | R/W | mtgy_op_ts12 |
| 48d | 1234 | R/W | mtgy_op_ts13 |
| 48e | 1238 | R/W | mtgy_op_ts14 |
| 48f | 123c | R/W | mtgy_op_ts15 |
| 490 | 1240 | R/W | mtgy_op_ts16 |
| 491 | 1244 | R/W | mtgy_op_ts17 |
| 492 | 1248 | R/W | mtgy_op_ts18 |
| 493 | 124c | R/W | mtgy_op_ts19 |
| 494 | 1250 | R/W | mtgy_op_ts20 |
| 495 | 1254 | R/W | mtgy_op_ts21 |
| 496 | 1258 | R/W | mtgy_op_ts22 |
| 497 | 125c | R/W | mtgy_op_ts23 |
| 498 | 1260 | R/W | mtgy_op_ts24 |
| 499 | 1264 | R/W | mtgy_op_ts25 |
| 49a | 1268 | R/W | mtgy_op_ts26 |
| 49b | 126c | R/W | mtgy_op_ts27 |
| 49c | 1270 | R/W | mtgy_op_ts28 |
| 49d | 1274 | R/W | mtgy_op_ts29 |
| 49e | 1278 | R/W | mtgy_op_ts30 |
| 49f | 127c | R/W | mtgy_op_ts31 |
| 4a0 | 1280 | R/W | mtgy_op_ts32 |
| 4a1 | 1284 | R/W | mtgy_op_ts33 |
| 4a2 | 1288 | R/W | mtgy_op_ts34 |
| 4a3 | 128c | R/W | mtgy_op_ts35 |
| 4a4 | 1290 | R/W | mtgy_op_ts36 |
| 4a5 | 1294 | R/W | mtgy_op_ts37 |
| 4a6 | 1298 | R/W | mtgy_op_ts38 |
| 4a7 | 129c | R/W | mtgy_op_ts39 |
| 4a8 | 12a0 | R/W | mtgy_op_ts40 |
| 4a9 | 12a4 | R/W | mtgy_op_ts41 |
| 4aa | 12a8 | R/W | mtgy_op_ts42 |
| 4ab | 12ac | R/W | mtgy_op_ts43 |
| 4ac | 12b0 | R/W | mtgy_op_ts44 |
| 4ad | 12b4 | R/W | mtgy_op_ts45 |
| 4ae | 12b8 | R/W | mtgy_op_ts46 |
| 4af | 12bc | R/W | mtgy_op_ts47 |
| 4b0 | 12c0 | R/W | mtgy_op_ts48 |
| 4b1 | 12c4 | R/W | mtgy_op_ts49 |
| 4b2 | 12c8 | R/W | mtgy_op_ts50 |
| 4b3 | 12cc | R/W | mtgy_op_ts51 |
| 4b4 | 12d0 | R/W | mtgy_op_ts52 |
| 4b5 | 12d4 | R/W | mtgy_op_ts53 |
| 4b6 | 12d8 | R/W | mtgy_op_ts54 |
| 4b7 | 12dc | R/W | mtgy_op_ts55 |
| 4b8 | 12e0 | R/W | mtgy_op_ts56 |
| 4b9 | 12e4 | R/W | mtgy_op_ts57 |
| 4ba | 12e8 | R/W | mtgy_op_ts58 |
| 4bb | 12ec | R/W | mtgy_op_ts59 |
| 4bc | 12f0 | R/W | mtgy_op_ts60 |
| 4bd | 12f4 | R/W | mtgy_op_ts61 |
| 4be | 12f8 | R/W | mtgy_op_ts62 |
| 4bf | 12fc | R/W | mtgy_op_ts63 |
| 4c0 | 1300 | R/W | mtgy_op_ts64 |
| 4c1 | 1304 | R/W | mtgy_op_ts65 |
| 4c2 | 1308 | R/W | mtgy_op_ts66 |
| 4c3 | 130c | R/W | mtgy_op_ts67 |
| 4c4 | 1310 | R/W | mtgy_op_ts68 |
| 4c5 | 1314 | R/W | mtgy_op_ts69 |
| 4c6 | 1318 | R/W | mtgy_op_ts70 |
| 4c7 | 131c | R/W | mtgy_op_ts71 |
| 4c8 | 1320 | R/W | mtgy_op_ts72 |
| 4c9 | 1324 | R/W | mtgy_op_ts73 |
| 4ca | 1328 | R/W | mtgy_op_ts74 |
| 4cb | 132c | R/W | mtgy_op_ts75 |
| 4cc | 1330 | R/W | mtgy_op_ts76 |
| 4cd | 1334 | R/W | mtgy_op_ts77 |
| 4ce | 1338 | R/W | mtgy_op_ts78 |
| 4cf | 133c | R/W | mtgy_op_ts79 |
| 4d0 | 1340 | R/W | mtgy_op_ts80 |
| 4d1 | 1344 | R/W | mtgy_op_ts81 |
| 4d2 | 1348 | R/W | mtgy_op_ts82 |
| 4d3 | 134c | R/W | mtgy_op_ts83 |
| 4d4 | 1350 | R/W | mtgy_op_ts84 |
| 4d5 | 1354 | R/W | mtgy_op_ts85 |
| 4d6 | 1358 | R/W | mtgy_op_ts86 |
| 4d7 | 135c | R/W | mtgy_op_ts87 |
| 4d8 | 1360 | R/W | mtgy_op_ts88 |
| 4d9 | 1364 | R/W | mtgy_op_ts89 |
| 4da | 1368 | R/W | mtgy_op_ts90 |
| 4db | 136c | R/W | mtgy_op_ts91 |
| 4dc | 1370 | R/W | mtgy_op_ts92 |
| 4dd | 1374 | R/W | mtgy_op_ts93 |
| 4de | 1378 | R/W | mtgy_op_ts94 |
| 4df | 137c | R/W | mtgy_op_ts95 |
| 4e0 | 1380 | R/W | mtgy_op_ts96 |
| 4e1 | 1384 | R/W | mtgy_op_ts97 |
| 4e2 | 1388 | R/W | mtgy_op_ts98 |
| 4e3 | 138c | R/W | mtgy_op_ts99 |
| 4e4 | 1390 | R/W | mtgy_op_ts100 |
| 4e5 | 1394 | R/W | mtgy_op_ts101 |
| 4e6 | 1398 | R/W | mtgy_op_ts102 |
| 4e7 | 139c | R/W | mtgy_op_ts103 |
| 4e8 | 13a0 | R/W | mtgy_op_ts104 |
| 4e9 | 13a4 | R/W | mtgy_op_ts105 |
| 4ea | 13a8 | R/W | mtgy_op_ts106 |
| 4eb | 13ac | R/W | mtgy_op_ts107 |
| 4ec | 13b0 | R/W | mtgy_op_ts108 |
| 4ed | 13b4 | R/W | mtgy_op_ts109 |
| 4ee | 13b8 | R/W | mtgy_op_ts110 |
| 4ef | 13bc | R/W | mtgy_op_ts111 |
| 4f0 | 13c0 | R/W | mtgy_op_ts112 |
| 4f1 | 13c4 | R/W | mtgy_op_ts113 |
| 4f2 | 13c8 | R/W | mtgy_op_ts114 |
| 4f3 | 13cc | R/W | mtgy_op_ts115 |
| 4f4 | 13d0 | R/W | mtgy_op_ts116 |
| 4f5 | 13d4 | R/W | mtgy_op_ts117 |
| 4f6 | 13d8 | R/W | mtgy_op_ts118 |
| 4f7 | 13dc | R/W | mtgy_op_ts119 |
| 4f8 | 13e0 | R/W | mtgy_op_ts120 |
| 4f9 | 13e4 | R/W | mtgy_op_ts121 |
| 4fa | 13e8 | R/W | mtgy_op_ts122 |
| 4fb | 13ec | R/W | mtgy_op_ts123 |
| 4fc | 13f0 | R/W | mtgy_op_ts124 |
| 4fd | 13f4 | R/W | mtgy_op_ts125 |
| 4fe | 13f8 | R/W | mtgy_op_ts126 |
| 4ff | 13fc | R/W | mtgy_op_ts127 |
| 500 | 1400 | R/W | mtgy_op_p0 |
| 501 | 1404 | R/W | mtgy_op_p1 |
| 502 | 1408 | R/W | mtgy_op_p2 |
| 503 | 140c | R/W | mtgy_op_p3 |
| 504 | 1410 | R/W | mtgy_op_p4 |
| 505 | 1414 | R/W | mtgy_op_p5 |
| 506 | 1418 | R/W | mtgy_op_p6 |
| 507 | 141c | R/W | mtgy_op_p7 |
| 508 | 1420 | R/W | mtgy_op_p8 |
| 509 | 1424 | R/W | mtgy_op_p9 |
| 50a | 1428 | R/W | mtgy_op_p10 |
| 50b | 142c | R/W | mtgy_op_p11 |
| 50c | 1430 | R/W | mtgy_op_p12 |
| 50d | 1434 | R/W | mtgy_op_p13 |
| 50e | 1438 | R/W | mtgy_op_p14 |
| 50f | 143c | R/W | mtgy_op_p15 |
| 510 | 1440 | R/W | mtgy_op_p16 |
| 511 | 1444 | R/W | mtgy_op_p17 |
| 512 | 1448 | R/W | mtgy_op_p18 |
| 513 | 144c | R/W | mtgy_op_p19 |
| 514 | 1450 | R/W | mtgy_op_p20 |
| 515 | 1454 | R/W | mtgy_op_p21 |
| 516 | 1458 | R/W | mtgy_op_p22 |
| 517 | 145c | R/W | mtgy_op_p23 |
| 518 | 1460 | R/W | mtgy_op_p24 |
| 519 | 1464 | R/W | mtgy_op_p25 |
| 51a | 1468 | R/W | mtgy_op_p26 |
| 51b | 146c | R/W | mtgy_op_p27 |
| 51c | 1470 | R/W | mtgy_op_p28 |
| 51d | 1474 | R/W | mtgy_op_p29 |
| 51e | 1478 | R/W | mtgy_op_p30 |
| 51f | 147c | R/W | mtgy_op_p31 |
| 520 | 1480 | R/W | mtgy_op_p32 |
| 521 | 1484 | R/W | mtgy_op_p33 |
| 522 | 1488 | R/W | mtgy_op_p34 |
| 523 | 148c | R/W | mtgy_op_p35 |
| 524 | 1490 | R/W | mtgy_op_p36 |
| 525 | 1494 | R/W | mtgy_op_p37 |
| 526 | 1498 | R/W | mtgy_op_p38 |
| 527 | 149c | R/W | mtgy_op_p39 |
| 528 | 14a0 | R/W | mtgy_op_p40 |
| 529 | 14a4 | R/W | mtgy_op_p41 |
| 52a | 14a8 | R/W | mtgy_op_p42 |
| 52b | 14ac | R/W | mtgy_op_p43 |
| 52c | 14b0 | R/W | mtgy_op_p44 |
| 52d | 14b4 | R/W | mtgy_op_p45 |
| 52e | 14b8 | R/W | mtgy_op_p46 |
| 52f | 14bc | R/W | mtgy_op_p47 |
| 530 | 14c0 | R/W | mtgy_op_p48 |
| 531 | 14c4 | R/W | mtgy_op_p49 |
| 532 | 14c8 | R/W | mtgy_op_p50 |
| 533 | 14cc | R/W | mtgy_op_p51 |
| 534 | 14d0 | R/W | mtgy_op_p52 |
| 535 | 14d4 | R/W | mtgy_op_p53 |
| 536 | 14d8 | R/W | mtgy_op_p54 |
| 537 | 14dc | R/W | mtgy_op_p55 |
| 538 | 14e0 | R/W | mtgy_op_p56 |
| 539 | 14e4 | R/W | mtgy_op_p57 |
| 53a | 14e8 | R/W | mtgy_op_p58 |
| 53b | 14ec | R/W | mtgy_op_p59 |
| 53c | 14f0 | R/W | mtgy_op_p60 |
| 53d | 14f4 | R/W | mtgy_op_p61 |
| 53e | 14f8 | R/W | mtgy_op_p62 |
| 53f | 14fc | R/W | mtgy_op_p63 |
| 540 | 1500 | R/W | mtgy_op_p64 |
| 541 | 1504 | R/W | mtgy_op_p65 |
| 542 | 1508 | R/W | mtgy_op_p66 |
| 543 | 150c | R/W | mtgy_op_p67 |
| 544 | 1510 | R/W | mtgy_op_p68 |
| 545 | 1514 | R/W | mtgy_op_p69 |
| 546 | 1518 | R/W | mtgy_op_p70 |
| 547 | 151c | R/W | mtgy_op_p71 |
| 548 | 1520 | R/W | mtgy_op_p72 |
| 549 | 1524 | R/W | mtgy_op_p73 |
| 54a | 1528 | R/W | mtgy_op_p74 |
| 54b | 152c | R/W | mtgy_op_p75 |
| 54c | 1530 | R/W | mtgy_op_p76 |
| 54d | 1534 | R/W | mtgy_op_p77 |
| 54e | 1538 | R/W | mtgy_op_p78 |
| 54f | 153c | R/W | mtgy_op_p79 |
| 550 | 1540 | R/W | mtgy_op_p80 |
| 551 | 1544 | R/W | mtgy_op_p81 |
| 552 | 1548 | R/W | mtgy_op_p82 |
| 553 | 154c | R/W | mtgy_op_p83 |
| 554 | 1550 | R/W | mtgy_op_p84 |
| 555 | 1554 | R/W | mtgy_op_p85 |
| 556 | 1558 | R/W | mtgy_op_p86 |
| 557 | 155c | R/W | mtgy_op_p87 |
| 558 | 1560 | R/W | mtgy_op_p88 |
| 559 | 1564 | R/W | mtgy_op_p89 |
| 55a | 1568 | R/W | mtgy_op_p90 |
| 55b | 156c | R/W | mtgy_op_p91 |
| 55c | 1570 | R/W | mtgy_op_p92 |
| 55d | 1574 | R/W | mtgy_op_p93 |
| 55e | 1578 | R/W | mtgy_op_p94 |
| 55f | 157c | R/W | mtgy_op_p95 |
| 560 | 1580 | R/W | mtgy_op_p96 |
| 561 | 1584 | R/W | mtgy_op_p97 |
| 562 | 1588 | R/W | mtgy_op_p98 |
| 563 | 158c | R/W | mtgy_op_p99 |
| 564 | 1590 | R/W | mtgy_op_p100 |
| 565 | 1594 | R/W | mtgy_op_p101 |
| 566 | 1598 | R/W | mtgy_op_p102 |
| 567 | 159c | R/W | mtgy_op_p103 |
| 568 | 15a0 | R/W | mtgy_op_p104 |
| 569 | 15a4 | R/W | mtgy_op_p105 |
| 56a | 15a8 | R/W | mtgy_op_p106 |
| 56b | 15ac | R/W | mtgy_op_p107 |
| 56c | 15b0 | R/W | mtgy_op_p108 |
| 56d | 15b4 | R/W | mtgy_op_p109 |
| 56e | 15b8 | R/W | mtgy_op_p110 |
| 56f | 15bc | R/W | mtgy_op_p111 |
| 570 | 15c0 | R/W | mtgy_op_p112 |
| 571 | 15c4 | R/W | mtgy_op_p113 |
| 572 | 15c8 | R/W | mtgy_op_p114 |
| 573 | 15cc | R/W | mtgy_op_p115 |
| 574 | 15d0 | R/W | mtgy_op_p116 |
| 575 | 15d4 | R/W | mtgy_op_p117 |
| 576 | 15d8 | R/W | mtgy_op_p118 |
| 577 | 15dc | R/W | mtgy_op_p119 |
| 578 | 15e0 | R/W | mtgy_op_p120 |
| 579 | 15e4 | R/W | mtgy_op_p121 |
| 57a | 15e8 | R/W | mtgy_op_p122 |
| 57b | 15ec | R/W | mtgy_op_p123 |
| 57c | 15f0 | R/W | mtgy_op_p124 |
| 57d | 15f4 | R/W | mtgy_op_p125 |
| 57e | 15f8 | R/W | mtgy_op_p126 |
| 57f | 15fc | R/W | mtgy_op_p127 |
| 580 | 1600 | R/W | mtgy_op_b0 |
| 581 | 1604 | R/W | mtgy_op_b1 |
| 582 | 1608 | R/W | mtgy_op_b2 |
| 583 | 160c | R/W | mtgy_op_b3 |
| 584 | 1610 | R/W | mtgy_op_b4 |
| 585 | 1614 | R/W | mtgy_op_b5 |
| 586 | 1618 | R/W | mtgy_op_b6 |
| 587 | 161c | R/W | mtgy_op_b7 |
| 588 | 1620 | R/W | mtgy_op_b8 |
| 589 | 1624 | R/W | mtgy_op_b9 |
| 58a | 1628 | R/W | mtgy_op_b10 |
| 58b | 162c | R/W | mtgy_op_b11 |
| 58c | 1630 | R/W | mtgy_op_b12 |
| 58d | 1634 | R/W | mtgy_op_b13 |
| 58e | 1638 | R/W | mtgy_op_b14 |
| 58f | 163c | R/W | mtgy_op_b15 |
| 590 | 1640 | R/W | mtgy_op_b16 |
| 591 | 1644 | R/W | mtgy_op_b17 |
| 592 | 1648 | R/W | mtgy_op_b18 |
| 593 | 164c | R/W | mtgy_op_b19 |
| 594 | 1650 | R/W | mtgy_op_b20 |
| 595 | 1654 | R/W | mtgy_op_b21 |
| 596 | 1658 | R/W | mtgy_op_b22 |
| 597 | 165c | R/W | mtgy_op_b23 |
| 598 | 1660 | R/W | mtgy_op_b24 |
| 599 | 1664 | R/W | mtgy_op_b25 |
| 59a | 1668 | R/W | mtgy_op_b26 |
| 59b | 166c | R/W | mtgy_op_b27 |
| 59c | 1670 | R/W | mtgy_op_b28 |
| 59d | 1674 | R/W | mtgy_op_b29 |
| 59e | 1678 | R/W | mtgy_op_b30 |
| 59f | 167c | R/W | mtgy_op_b31 |
| 5a0 | 1680 | R/W | mtgy_op_b32 |
| 5a1 | 1684 | R/W | mtgy_op_b33 |
| 5a2 | 1688 | R/W | mtgy_op_b34 |
| 5a3 | 168c | R/W | mtgy_op_b35 |
| 5a4 | 1690 | R/W | mtgy_op_b36 |
| 5a5 | 1694 | R/W | mtgy_op_b37 |
| 5a6 | 1698 | R/W | mtgy_op_b38 |
| 5a7 | 169c | R/W | mtgy_op_b39 |
| 5a8 | 16a0 | R/W | mtgy_op_b40 |
| 5a9 | 16a4 | R/W | mtgy_op_b41 |
| 5aa | 16a8 | R/W | mtgy_op_b42 |
| 5ab | 16ac | R/W | mtgy_op_b43 |
| 5ac | 16b0 | R/W | mtgy_op_b44 |
| 5ad | 16b4 | R/W | mtgy_op_b45 |
| 5ae | 16b8 | R/W | mtgy_op_b46 |
| 5af | 16bc | R/W | mtgy_op_b47 |
| 5b0 | 16c0 | R/W | mtgy_op_b48 |
| 5b1 | 16c4 | R/W | mtgy_op_b49 |
| 5b2 | 16c8 | R/W | mtgy_op_b50 |
| 5b3 | 16cc | R/W | mtgy_op_b51 |
| 5b4 | 16d0 | R/W | mtgy_op_b52 |
| 5b5 | 16d4 | R/W | mtgy_op_b53 |
| 5b6 | 16d8 | R/W | mtgy_op_b54 |
| 5b7 | 16dc | R/W | mtgy_op_b55 |
| 5b8 | 16e0 | R/W | mtgy_op_b56 |
| 5b9 | 16e4 | R/W | mtgy_op_b57 |
| 5ba | 16e8 | R/W | mtgy_op_b58 |
| 5bb | 16ec | R/W | mtgy_op_b59 |
| 5bc | 16f0 | R/W | mtgy_op_b60 |
| 5bd | 16f4 | R/W | mtgy_op_b61 |
| 5be | 16f8 | R/W | mtgy_op_b62 |
| 5bf | 16fc | R/W | mtgy_op_b63 |
| 5c0 | 1700 | R/W | mtgy_op_b64 |
| 5c1 | 1704 | R/W | mtgy_op_b65 |
| 5c2 | 1708 | R/W | mtgy_op_b66 |
| 5c3 | 170c | R/W | mtgy_op_b67 |
| 5c4 | 1710 | R/W | mtgy_op_b68 |
| 5c5 | 1714 | R/W | mtgy_op_b69 |
| 5c6 | 1718 | R/W | mtgy_op_b70 |
| 5c7 | 171c | R/W | mtgy_op_b71 |
| 5c8 | 1720 | R/W | mtgy_op_b72 |
| 5c9 | 1724 | R/W | mtgy_op_b73 |
| 5ca | 1728 | R/W | mtgy_op_b74 |
| 5cb | 172c | R/W | mtgy_op_b75 |
| 5cc | 1730 | R/W | mtgy_op_b76 |
| 5cd | 1734 | R/W | mtgy_op_b77 |
| 5ce | 1738 | R/W | mtgy_op_b78 |
| 5cf | 173c | R/W | mtgy_op_b79 |
| 5d0 | 1740 | R/W | mtgy_op_b80 |
| 5d1 | 1744 | R/W | mtgy_op_b81 |
| 5d2 | 1748 | R/W | mtgy_op_b82 |
| 5d3 | 174c | R/W | mtgy_op_b83 |
| 5d4 | 1750 | R/W | mtgy_op_b84 |
| 5d5 | 1754 | R/W | mtgy_op_b85 |
| 5d6 | 1758 | R/W | mtgy_op_b86 |
| 5d7 | 175c | R/W | mtgy_op_b87 |
| 5d8 | 1760 | R/W | mtgy_op_b88 |
| 5d9 | 1764 | R/W | mtgy_op_b89 |
| 5da | 1768 | R/W | mtgy_op_b90 |
| 5db | 176c | R/W | mtgy_op_b91 |
| 5dc | 1770 | R/W | mtgy_op_b92 |
| 5dd | 1774 | R/W | mtgy_op_b93 |
| 5de | 1778 | R/W | mtgy_op_b94 |
| 5df | 177c | R/W | mtgy_op_b95 |
| 5e0 | 1780 | R/W | mtgy_op_b96 |
| 5e1 | 1784 | R/W | mtgy_op_b97 |
| 5e2 | 1788 | R/W | mtgy_op_b98 |
| 5e3 | 178c | R/W | mtgy_op_b99 |
| 5e4 | 1790 | R/W | mtgy_op_b100 |
| 5e5 | 1794 | R/W | mtgy_op_b101 |
| 5e6 | 1798 | R/W | mtgy_op_b102 |
| 5e7 | 179c | R/W | mtgy_op_b103 |
| 5e8 | 17a0 | R/W | mtgy_op_b104 |
| 5e9 | 17a4 | R/W | mtgy_op_b105 |
| 5ea | 17a8 | R/W | mtgy_op_b106 |
| 5eb | 17ac | R/W | mtgy_op_b107 |
| 5ec | 17b0 | R/W | mtgy_op_b108 |
| 5ed | 17b4 | R/W | mtgy_op_b109 |
| 5ee | 17b8 | R/W | mtgy_op_b110 |
| 5ef | 17bc | R/W | mtgy_op_b111 |
| 5f0 | 17c0 | R/W | mtgy_op_b112 |
| 5f1 | 17c4 | R/W | mtgy_op_b113 |
| 5f2 | 17c8 | R/W | mtgy_op_b114 |
| 5f3 | 17cc | R/W | mtgy_op_b115 |
| 5f4 | 17d0 | R/W | mtgy_op_b116 |
| 5f5 | 17d4 | R/W | mtgy_op_b117 |
| 5f6 | 17d8 | R/W | mtgy_op_b118 |
| 5f7 | 17dc | R/W | mtgy_op_b119 |
| 5f8 | 17e0 | R/W | mtgy_op_b120 |
| 5f9 | 17e4 | R/W | mtgy_op_b121 |
| 5fa | 17e8 | R/W | mtgy_op_b122 |
| 5fb | 17ec | R/W | mtgy_op_b123 |
| 5fc | 17f0 | R/W | mtgy_op_b124 |
| 5fd | 17f4 | R/W | mtgy_op_b125 |
| 5fe | 17f8 | R/W | mtgy_op_b126 |
| 5ff | 17fc | R/W | mtgy_op_b127 |
| 600 | 1800 | R/W | mtgy_op_a0 |
| 601 | 1804 | R/W | mtgy_op_a1 |
| 602 | 1808 | R/W | mtgy_op_a2 |
| 603 | 180c | R/W | mtgy_op_a3 |
| 604 | 1810 | R/W | mtgy_op_a4 |
| 605 | 1814 | R/W | mtgy_op_a5 |
| 606 | 1818 | R/W | mtgy_op_a6 |
| 607 | 181c | R/W | mtgy_op_a7 |
| 608 | 1820 | R/W | mtgy_op_a8 |
| 609 | 1824 | R/W | mtgy_op_a9 |
| 60a | 1828 | R/W | mtgy_op_a10 |
| 60b | 182c | R/W | mtgy_op_a11 |
| 60c | 1830 | R/W | mtgy_op_a12 |
| 60d | 1834 | R/W | mtgy_op_a13 |
| 60e | 1838 | R/W | mtgy_op_a14 |
| 60f | 183c | R/W | mtgy_op_a15 |
| 610 | 1840 | R/W | mtgy_op_a16 |
| 611 | 1844 | R/W | mtgy_op_a17 |
| 612 | 1848 | R/W | mtgy_op_a18 |
| 613 | 184c | R/W | mtgy_op_a19 |
| 614 | 1850 | R/W | mtgy_op_a20 |
| 615 | 1854 | R/W | mtgy_op_a21 |
| 616 | 1858 | R/W | mtgy_op_a22 |
| 617 | 185c | R/W | mtgy_op_a23 |
| 618 | 1860 | R/W | mtgy_op_a24 |
| 619 | 1864 | R/W | mtgy_op_a25 |
| 61a | 1868 | R/W | mtgy_op_a26 |
| 61b | 186c | R/W | mtgy_op_a27 |
| 61c | 1870 | R/W | mtgy_op_a28 |
| 61d | 1874 | R/W | mtgy_op_a29 |
| 61e | 1878 | R/W | mtgy_op_a30 |
| 61f | 187c | R/W | mtgy_op_a31 |
| 620 | 1880 | R/W | mtgy_op_a32 |
| 621 | 1884 | R/W | mtgy_op_a33 |
| 622 | 1888 | R/W | mtgy_op_a34 |
| 623 | 188c | R/W | mtgy_op_a35 |
| 624 | 1890 | R/W | mtgy_op_a36 |
| 625 | 1894 | R/W | mtgy_op_a37 |
| 626 | 1898 | R/W | mtgy_op_a38 |
| 627 | 189c | R/W | mtgy_op_a39 |
| 628 | 18a0 | R/W | mtgy_op_a40 |
| 629 | 18a4 | R/W | mtgy_op_a41 |
| 62a | 18a8 | R/W | mtgy_op_a42 |
| 62b | 18ac | R/W | mtgy_op_a43 |
| 62c | 18b0 | R/W | mtgy_op_a44 |
| 62d | 18b4 | R/W | mtgy_op_a45 |
| 62e | 18b8 | R/W | mtgy_op_a46 |
| 62f | 18bc | R/W | mtgy_op_a47 |
| 630 | 18c0 | R/W | mtgy_op_a48 |
| 631 | 18c4 | R/W | mtgy_op_a49 |
| 632 | 18c8 | R/W | mtgy_op_a50 |
| 633 | 18cc | R/W | mtgy_op_a51 |
| 634 | 18d0 | R/W | mtgy_op_a52 |
| 635 | 18d4 | R/W | mtgy_op_a53 |
| 636 | 18d8 | R/W | mtgy_op_a54 |
| 637 | 18dc | R/W | mtgy_op_a55 |
| 638 | 18e0 | R/W | mtgy_op_a56 |
| 639 | 18e4 | R/W | mtgy_op_a57 |
| 63a | 18e8 | R/W | mtgy_op_a58 |
| 63b | 18ec | R/W | mtgy_op_a59 |
| 63c | 18f0 | R/W | mtgy_op_a60 |
| 63d | 18f4 | R/W | mtgy_op_a61 |
| 63e | 18f8 | R/W | mtgy_op_a62 |
| 63f | 18fc | R/W | mtgy_op_a63 |
| 640 | 1900 | R/W | mtgy_op_a64 |
| 641 | 1904 | R/W | mtgy_op_a65 |
| 642 | 1908 | R/W | mtgy_op_a66 |
| 643 | 190c | R/W | mtgy_op_a67 |
| 644 | 1910 | R/W | mtgy_op_a68 |
| 645 | 1914 | R/W | mtgy_op_a69 |
| 646 | 1918 | R/W | mtgy_op_a70 |
| 647 | 191c | R/W | mtgy_op_a71 |
| 648 | 1920 | R/W | mtgy_op_a72 |
| 649 | 1924 | R/W | mtgy_op_a73 |
| 64a | 1928 | R/W | mtgy_op_a74 |
| 64b | 192c | R/W | mtgy_op_a75 |
| 64c | 1930 | R/W | mtgy_op_a76 |
| 64d | 1934 | R/W | mtgy_op_a77 |
| 64e | 1938 | R/W | mtgy_op_a78 |
| 64f | 193c | R/W | mtgy_op_a79 |
| 650 | 1940 | R/W | mtgy_op_a80 |
| 651 | 1944 | R/W | mtgy_op_a81 |
| 652 | 1948 | R/W | mtgy_op_a82 |
| 653 | 194c | R/W | mtgy_op_a83 |
| 654 | 1950 | R/W | mtgy_op_a84 |
| 655 | 1954 | R/W | mtgy_op_a85 |
| 656 | 1958 | R/W | mtgy_op_a86 |
| 657 | 195c | R/W | mtgy_op_a87 |
| 658 | 1960 | R/W | mtgy_op_a88 |
| 659 | 1964 | R/W | mtgy_op_a89 |
| 65a | 1968 | R/W | mtgy_op_a90 |
| 65b | 196c | R/W | mtgy_op_a91 |
| 65c | 1970 | R/W | mtgy_op_a92 |
| 65d | 1974 | R/W | mtgy_op_a93 |
| 65e | 1978 | R/W | mtgy_op_a94 |
| 65f | 197c | R/W | mtgy_op_a95 |
| 660 | 1980 | R/W | mtgy_op_a96 |
| 661 | 1984 | R/W | mtgy_op_a97 |
| 662 | 1988 | R/W | mtgy_op_a98 |
| 663 | 198c | R/W | mtgy_op_a99 |
| 664 | 1990 | R/W | mtgy_op_a100 |
| 665 | 1994 | R/W | mtgy_op_a101 |
| 666 | 1998 | R/W | mtgy_op_a102 |
| 667 | 199c | R/W | mtgy_op_a103 |
| 668 | 19a0 | R/W | mtgy_op_a104 |
| 669 | 19a4 | R/W | mtgy_op_a105 |
| 66a | 19a8 | R/W | mtgy_op_a106 |
| 66b | 19ac | R/W | mtgy_op_a107 |
| 66c | 19b0 | R/W | mtgy_op_a108 |
| 66d | 19b4 | R/W | mtgy_op_a109 |
| 66e | 19b8 | R/W | mtgy_op_a110 |
| 66f | 19bc | R/W | mtgy_op_a111 |
| 670 | 19c0 | R/W | mtgy_op_a112 |
| 671 | 19c4 | R/W | mtgy_op_a113 |
| 672 | 19c8 | R/W | mtgy_op_a114 |
| 673 | 19cc | R/W | mtgy_op_a115 |
| 674 | 19d0 | R/W | mtgy_op_a116 |
| 675 | 19d4 | R/W | mtgy_op_a117 |
| 676 | 19d8 | R/W | mtgy_op_a118 |
| 677 | 19dc | R/W | mtgy_op_a119 |
| 678 | 19e0 | R/W | mtgy_op_a120 |
| 679 | 19e4 | R/W | mtgy_op_a121 |
| 67a | 19e8 | R/W | mtgy_op_a122 |
| 67b | 19ec | R/W | mtgy_op_a123 |
| 67c | 19f0 | R/W | mtgy_op_a124 |
| 67d | 19f4 | R/W | mtgy_op_a125 |
| 67e | 19f8 | R/W | mtgy_op_a126 |
| 67f | 19fc | R/W | mtgy_op_a127 |
| 680 | 1a00 | R/W | mtgy_op_e0 |
| 681 | 1a04 | R/W | mtgy_op_e1 |
| 682 | 1a08 | R/W | mtgy_op_e2 |
| 683 | 1a0c | R/W | mtgy_op_e3 |
| 684 | 1a10 | R/W | mtgy_op_e4 |
| 685 | 1a14 | R/W | mtgy_op_e5 |
| 686 | 1a18 | R/W | mtgy_op_e6 |
| 687 | 1a1c | R/W | mtgy_op_e7 |
| 688 | 1a20 | R/W | mtgy_op_e8 |
| 689 | 1a24 | R/W | mtgy_op_e9 |
| 68a | 1a28 | R/W | mtgy_op_e10 |
| 68b | 1a2c | R/W | mtgy_op_e11 |
| 68c | 1a30 | R/W | mtgy_op_e12 |
| 68d | 1a34 | R/W | mtgy_op_e13 |
| 68e | 1a38 | R/W | mtgy_op_e14 |
| 68f | 1a3c | R/W | mtgy_op_e15 |
| 690 | 1a40 | R/W | mtgy_op_e16 |
| 691 | 1a44 | R/W | mtgy_op_e17 |
| 692 | 1a48 | R/W | mtgy_op_e18 |
| 693 | 1a4c | R/W | mtgy_op_e19 |
| 694 | 1a50 | R/W | mtgy_op_e20 |
| 695 | 1a54 | R/W | mtgy_op_e21 |
| 696 | 1a58 | R/W | mtgy_op_e22 |
| 697 | 1a5c | R/W | mtgy_op_e23 |
| 698 | 1a60 | R/W | mtgy_op_e24 |
| 699 | 1a64 | R/W | mtgy_op_e25 |
| 69a | 1a68 | R/W | mtgy_op_e26 |
| 69b | 1a6c | R/W | mtgy_op_e27 |
| 69c | 1a70 | R/W | mtgy_op_e28 |
| 69d | 1a74 | R/W | mtgy_op_e29 |
| 69e | 1a78 | R/W | mtgy_op_e30 |
| 69f | 1a7c | R/W | mtgy_op_e31 |
| 6a0 | 1a80 | R/W | mtgy_op_e32 |
| 6a1 | 1a84 | R/W | mtgy_op_e33 |
| 6a2 | 1a88 | R/W | mtgy_op_e34 |
| 6a3 | 1a8c | R/W | mtgy_op_e35 |
| 6a4 | 1a90 | R/W | mtgy_op_e36 |
| 6a5 | 1a94 | R/W | mtgy_op_e37 |
| 6a6 | 1a98 | R/W | mtgy_op_e38 |
| 6a7 | 1a9c | R/W | mtgy_op_e39 |
| 6a8 | 1aa0 | R/W | mtgy_op_e40 |
| 6a9 | 1aa4 | R/W | mtgy_op_e41 |
| 6aa | 1aa8 | R/W | mtgy_op_e42 |
| 6ab | 1aac | R/W | mtgy_op_e43 |
| 6ac | 1ab0 | R/W | mtgy_op_e44 |
| 6ad | 1ab4 | R/W | mtgy_op_e45 |
| 6ae | 1ab8 | R/W | mtgy_op_e46 |
| 6af | 1abc | R/W | mtgy_op_e47 |
| 6b0 | 1ac0 | R/W | mtgy_op_e48 |
| 6b1 | 1ac4 | R/W | mtgy_op_e49 |
| 6b2 | 1ac8 | R/W | mtgy_op_e50 |
| 6b3 | 1acc | R/W | mtgy_op_e51 |
| 6b4 | 1ad0 | R/W | mtgy_op_e52 |
| 6b5 | 1ad4 | R/W | mtgy_op_e53 |
| 6b6 | 1ad8 | R/W | mtgy_op_e54 |
| 6b7 | 1adc | R/W | mtgy_op_e55 |
| 6b8 | 1ae0 | R/W | mtgy_op_e56 |
| 6b9 | 1ae4 | R/W | mtgy_op_e57 |
| 6ba | 1ae8 | R/W | mtgy_op_e58 |
| 6bb | 1aec | R/W | mtgy_op_e59 |
| 6bc | 1af0 | R/W | mtgy_op_e60 |
| 6bd | 1af4 | R/W | mtgy_op_e61 |
| 6be | 1af8 | R/W | mtgy_op_e62 |
| 6bf | 1afc | R/W | mtgy_op_e63 |
| 6c0 | 1b00 | R/W | mtgy_op_e64 |
| 6c1 | 1b04 | R/W | mtgy_op_e65 |
| 6c2 | 1b08 | R/W | mtgy_op_e66 |
| 6c3 | 1b0c | R/W | mtgy_op_e67 |
| 6c4 | 1b10 | R/W | mtgy_op_e68 |
| 6c5 | 1b14 | R/W | mtgy_op_e69 |
| 6c6 | 1b18 | R/W | mtgy_op_e70 |
| 6c7 | 1b1c | R/W | mtgy_op_e71 |
| 6c8 | 1b20 | R/W | mtgy_op_e72 |
| 6c9 | 1b24 | R/W | mtgy_op_e73 |
| 6ca | 1b28 | R/W | mtgy_op_e74 |
| 6cb | 1b2c | R/W | mtgy_op_e75 |
| 6cc | 1b30 | R/W | mtgy_op_e76 |
| 6cd | 1b34 | R/W | mtgy_op_e77 |
| 6ce | 1b38 | R/W | mtgy_op_e78 |
| 6cf | 1b3c | R/W | mtgy_op_e79 |
| 6d0 | 1b40 | R/W | mtgy_op_e80 |
| 6d1 | 1b44 | R/W | mtgy_op_e81 |
| 6d2 | 1b48 | R/W | mtgy_op_e82 |
| 6d3 | 1b4c | R/W | mtgy_op_e83 |
| 6d4 | 1b50 | R/W | mtgy_op_e84 |
| 6d5 | 1b54 | R/W | mtgy_op_e85 |
| 6d6 | 1b58 | R/W | mtgy_op_e86 |
| 6d7 | 1b5c | R/W | mtgy_op_e87 |
| 6d8 | 1b60 | R/W | mtgy_op_e88 |
| 6d9 | 1b64 | R/W | mtgy_op_e89 |
| 6da | 1b68 | R/W | mtgy_op_e90 |
| 6db | 1b6c | R/W | mtgy_op_e91 |
| 6dc | 1b70 | R/W | mtgy_op_e92 |
| 6dd | 1b74 | R/W | mtgy_op_e93 |
| 6de | 1b78 | R/W | mtgy_op_e94 |
| 6df | 1b7c | R/W | mtgy_op_e95 |
| 6e0 | 1b80 | R/W | mtgy_op_e96 |
| 6e1 | 1b84 | R/W | mtgy_op_e97 |
| 6e2 | 1b88 | R/W | mtgy_op_e98 |
| 6e3 | 1b8c | R/W | mtgy_op_e99 |
| 6e4 | 1b90 | R/W | mtgy_op_e100 |
| 6e5 | 1b94 | R/W | mtgy_op_e101 |
| 6e6 | 1b98 | R/W | mtgy_op_e102 |
| 6e7 | 1b9c | R/W | mtgy_op_e103 |
| 6e8 | 1ba0 | R/W | mtgy_op_e104 |
| 6e9 | 1ba4 | R/W | mtgy_op_e105 |
| 6ea | 1ba8 | R/W | mtgy_op_e106 |
| 6eb | 1bac | R/W | mtgy_op_e107 |
| 6ec | 1bb0 | R/W | mtgy_op_e108 |
| 6ed | 1bb4 | R/W | mtgy_op_e109 |
| 6ee | 1bb8 | R/W | mtgy_op_e110 |
| 6ef | 1bbc | R/W | mtgy_op_e111 |
| 6f0 | 1bc0 | R/W | mtgy_op_e112 |
| 6f1 | 1bc4 | R/W | mtgy_op_e113 |
| 6f2 | 1bc8 | R/W | mtgy_op_e114 |
| 6f3 | 1bcc | R/W | mtgy_op_e115 |
| 6f4 | 1bd0 | R/W | mtgy_op_e116 |
| 6f5 | 1bd4 | R/W | mtgy_op_e117 |
| 6f6 | 1bd8 | R/W | mtgy_op_e118 |
| 6f7 | 1bdc | R/W | mtgy_op_e119 |
| 6f8 | 1be0 | R/W | mtgy_op_e120 |
| 6f9 | 1be4 | R/W | mtgy_op_e121 |
| 6fa | 1be8 | R/W | mtgy_op_e122 |
| 6fb | 1bec | R/W | mtgy_op_e123 |
| 6fc | 1bf0 | R/W | mtgy_op_e124 |
| 6fd | 1bf4 | R/W | mtgy_op_e125 |
| 6fe | 1bf8 | R/W | mtgy_op_e126 |
| 6ff | 1bfc | R/W | mtgy_op_e127 |
| 700 | 1c00 | R/W | mtgy_op_x0 |
| 701 | 1c04 | R/W | mtgy_op_x1 |
| 702 | 1c08 | R/W | mtgy_op_x2 |
| 703 | 1c0c | R/W | mtgy_op_x3 |
| 704 | 1c10 | R/W | mtgy_op_x4 |
| 705 | 1c14 | R/W | mtgy_op_x5 |
| 706 | 1c18 | R/W | mtgy_op_x6 |
| 707 | 1c1c | R/W | mtgy_op_x7 |
| 708 | 1c20 | R/W | mtgy_op_x8 |
| 709 | 1c24 | R/W | mtgy_op_x9 |
| 70a | 1c28 | R/W | mtgy_op_x10 |
| 70b | 1c2c | R/W | mtgy_op_x11 |
| 70c | 1c30 | R/W | mtgy_op_x12 |
| 70d | 1c34 | R/W | mtgy_op_x13 |
| 70e | 1c38 | R/W | mtgy_op_x14 |
| 70f | 1c3c | R/W | mtgy_op_x15 |
| 710 | 1c40 | R/W | mtgy_op_x16 |
| 711 | 1c44 | R/W | mtgy_op_x17 |
| 712 | 1c48 | R/W | mtgy_op_x18 |
| 713 | 1c4c | R/W | mtgy_op_x19 |
| 714 | 1c50 | R/W | mtgy_op_x20 |
| 715 | 1c54 | R/W | mtgy_op_x21 |
| 716 | 1c58 | R/W | mtgy_op_x22 |
| 717 | 1c5c | R/W | mtgy_op_x23 |
| 718 | 1c60 | R/W | mtgy_op_x24 |
| 719 | 1c64 | R/W | mtgy_op_x25 |
| 71a | 1c68 | R/W | mtgy_op_x26 |
| 71b | 1c6c | R/W | mtgy_op_x27 |
| 71c | 1c70 | R/W | mtgy_op_x28 |
| 71d | 1c74 | R/W | mtgy_op_x29 |
| 71e | 1c78 | R/W | mtgy_op_x30 |
| 71f | 1c7c | R/W | mtgy_op_x31 |
| 720 | 1c80 | R/W | mtgy_op_x32 |
| 721 | 1c84 | R/W | mtgy_op_x33 |
| 722 | 1c88 | R/W | mtgy_op_x34 |
| 723 | 1c8c | R/W | mtgy_op_x35 |
| 724 | 1c90 | R/W | mtgy_op_x36 |
| 725 | 1c94 | R/W | mtgy_op_x37 |
| 726 | 1c98 | R/W | mtgy_op_x38 |
| 727 | 1c9c | R/W | mtgy_op_x39 |
| 728 | 1ca0 | R/W | mtgy_op_x40 |
| 729 | 1ca4 | R/W | mtgy_op_x41 |
| 72a | 1ca8 | R/W | mtgy_op_x42 |
| 72b | 1cac | R/W | mtgy_op_x43 |
| 72c | 1cb0 | R/W | mtgy_op_x44 |
| 72d | 1cb4 | R/W | mtgy_op_x45 |
| 72e | 1cb8 | R/W | mtgy_op_x46 |
| 72f | 1cbc | R/W | mtgy_op_x47 |
| 730 | 1cc0 | R/W | mtgy_op_x48 |
| 731 | 1cc4 | R/W | mtgy_op_x49 |
| 732 | 1cc8 | R/W | mtgy_op_x50 |
| 733 | 1ccc | R/W | mtgy_op_x51 |
| 734 | 1cd0 | R/W | mtgy_op_x52 |
| 735 | 1cd4 | R/W | mtgy_op_x53 |
| 736 | 1cd8 | R/W | mtgy_op_x54 |
| 737 | 1cdc | R/W | mtgy_op_x55 |
| 738 | 1ce0 | R/W | mtgy_op_x56 |
| 739 | 1ce4 | R/W | mtgy_op_x57 |
| 73a | 1ce8 | R/W | mtgy_op_x58 |
| 73b | 1cec | R/W | mtgy_op_x59 |
| 73c | 1cf0 | R/W | mtgy_op_x60 |
| 73d | 1cf4 | R/W | mtgy_op_x61 |
| 73e | 1cf8 | R/W | mtgy_op_x62 |
| 73f | 1cfc | R/W | mtgy_op_x63 |
| 740 | 1d00 | R/W | mtgy_op_x64 |
| 741 | 1d04 | R/W | mtgy_op_x65 |
| 742 | 1d08 | R/W | mtgy_op_x66 |
| 743 | 1d0c | R/W | mtgy_op_x67 |
| 744 | 1d10 | R/W | mtgy_op_x68 |
| 745 | 1d14 | R/W | mtgy_op_x69 |
| 746 | 1d18 | R/W | mtgy_op_x70 |
| 747 | 1d1c | R/W | mtgy_op_x71 |
| 748 | 1d20 | R/W | mtgy_op_x72 |
| 749 | 1d24 | R/W | mtgy_op_x73 |
| 74a | 1d28 | R/W | mtgy_op_x74 |
| 74b | 1d2c | R/W | mtgy_op_x75 |
| 74c | 1d30 | R/W | mtgy_op_x76 |
| 74d | 1d34 | R/W | mtgy_op_x77 |
| 74e | 1d38 | R/W | mtgy_op_x78 |
| 74f | 1d3c | R/W | mtgy_op_x79 |
| 750 | 1d40 | R/W | mtgy_op_x80 |
| 751 | 1d44 | R/W | mtgy_op_x81 |
| 752 | 1d48 | R/W | mtgy_op_x82 |
| 753 | 1d4c | R/W | mtgy_op_x83 |
| 754 | 1d50 | R/W | mtgy_op_x84 |
| 755 | 1d54 | R/W | mtgy_op_x85 |
| 756 | 1d58 | R/W | mtgy_op_x86 |
| 757 | 1d5c | R/W | mtgy_op_x87 |
| 758 | 1d60 | R/W | mtgy_op_x88 |
| 759 | 1d64 | R/W | mtgy_op_x89 |
| 75a | 1d68 | R/W | mtgy_op_x90 |
| 75b | 1d6c | R/W | mtgy_op_x91 |
| 75c | 1d70 | R/W | mtgy_op_x92 |
| 75d | 1d74 | R/W | mtgy_op_x93 |
| 75e | 1d78 | R/W | mtgy_op_x94 |
| 75f | 1d7c | R/W | mtgy_op_x95 |
| 760 | 1d80 | R/W | mtgy_op_x96 |
| 761 | 1d84 | R/W | mtgy_op_x97 |
| 762 | 1d88 | R/W | mtgy_op_x98 |
| 763 | 1d8c | R/W | mtgy_op_x99 |
| 764 | 1d90 | R/W | mtgy_op_x100 |
| 765 | 1d94 | R/W | mtgy_op_x101 |
| 766 | 1d98 | R/W | mtgy_op_x102 |
| 767 | 1d9c | R/W | mtgy_op_x103 |
| 768 | 1da0 | R/W | mtgy_op_x104 |
| 769 | 1da4 | R/W | mtgy_op_x105 |
| 76a | 1da8 | R/W | mtgy_op_x106 |
| 76b | 1dac | R/W | mtgy_op_x107 |
| 76c | 1db0 | R/W | mtgy_op_x108 |
| 76d | 1db4 | R/W | mtgy_op_x109 |
| 76e | 1db8 | R/W | mtgy_op_x110 |
| 76f | 1dbc | R/W | mtgy_op_x111 |
| 770 | 1dc0 | R/W | mtgy_op_x112 |
| 771 | 1dc4 | R/W | mtgy_op_x113 |
| 772 | 1dc8 | R/W | mtgy_op_x114 |
| 773 | 1dcc | R/W | mtgy_op_x115 |
| 774 | 1dd0 | R/W | mtgy_op_x116 |
| 775 | 1dd4 | R/W | mtgy_op_x117 |
| 776 | 1dd8 | R/W | mtgy_op_x118 |
| 777 | 1ddc | R/W | mtgy_op_x119 |
| 778 | 1de0 | R/W | mtgy_op_x120 |
| 779 | 1de4 | R/W | mtgy_op_x121 |
| 77a | 1de8 | R/W | mtgy_op_x122 |
| 77b | 1dec | R/W | mtgy_op_x123 |
| 77c | 1df0 | R/W | mtgy_op_x124 |
| 77d | 1df4 | R/W | mtgy_op_x125 |
| 77e | 1df8 | R/W | mtgy_op_x126 |
| 77f | 1dfc | R/W | mtgy_op_x127 |
| 780-7ff | 1e00-1ffc | - | reserved |
| mtgy_cmd |
|
||||||||||||||||||||||||||||
| R/W |
0x00000094 |
Address@mtgy : 0x06432000 Address@com_mtgy : 0x06432000 Address@app_mtgy : 0x400e2000 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 27 | "00000" |
src_addr_x |
|
||||||||||||||||||||||||||
| 26 - 22 | "00000" |
src_addr_e |
|
||||||||||||||||||||||||||
| 21 - 17 | "00000" |
dest_addr |
|
||||||||||||||||||||||||||
| 16 - 12 | "00000" |
src_addr |
|
||||||||||||||||||||||||||
| 11 - 8 | "0000" |
op |
|
||||||||||||||||||||||||||
| 7 - 4 | "1001" |
precision |
|
||||||||||||||||||||||||||
| 3 | 0 |
- |
reserved | ||||||||||||||||||||||||||
| 2 | "1" |
f_sel |
|
||||||||||||||||||||||||||
| 1 | "0" |
abort |
|
||||||||||||||||||||||||||
| 0 | "0" |
start |
|
||||||||||||||||||||||||||
| mtgy_stat |
|
|||
| R |
Address@mtgy : 0x06432004 Address@com_mtgy : 0x06432004 Address@app_mtgy : 0x400e2004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | done |
|
||
| mtgy_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06432008 Address@com_mtgy : 0x06432008 Address@app_mtgy : 0x400e2008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
done |
|
|
| mtgy_irq_masked |
|
|||
| R |
Address@mtgy : 0x0643200c Address@com_mtgy : 0x0643200c Address@app_mtgy : 0x400e200c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | done |
|
||
| mtgy_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06432010 Address@com_mtgy : 0x06432010 Address@app_mtgy : 0x400e2010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
done |
|
|
| mtgy_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06432014 Address@com_mtgy : 0x06432014 Address@app_mtgy : 0x400e2014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
done |
|
|
| mtgy_op_tc0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433000 Address@com_mtgy : 0x06433000 Address@app_mtgy : 0x400e3000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433004 Address@com_mtgy : 0x06433004 Address@app_mtgy : 0x400e3004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433008 Address@com_mtgy : 0x06433008 Address@app_mtgy : 0x400e3008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643300c Address@com_mtgy : 0x0643300c Address@app_mtgy : 0x400e300c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433010 Address@com_mtgy : 0x06433010 Address@app_mtgy : 0x400e3010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433014 Address@com_mtgy : 0x06433014 Address@app_mtgy : 0x400e3014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433018 Address@com_mtgy : 0x06433018 Address@app_mtgy : 0x400e3018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643301c Address@com_mtgy : 0x0643301c Address@app_mtgy : 0x400e301c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433020 Address@com_mtgy : 0x06433020 Address@app_mtgy : 0x400e3020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433024 Address@com_mtgy : 0x06433024 Address@app_mtgy : 0x400e3024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433028 Address@com_mtgy : 0x06433028 Address@app_mtgy : 0x400e3028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643302c Address@com_mtgy : 0x0643302c Address@app_mtgy : 0x400e302c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433030 Address@com_mtgy : 0x06433030 Address@app_mtgy : 0x400e3030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433034 Address@com_mtgy : 0x06433034 Address@app_mtgy : 0x400e3034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433038 Address@com_mtgy : 0x06433038 Address@app_mtgy : 0x400e3038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643303c Address@com_mtgy : 0x0643303c Address@app_mtgy : 0x400e303c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433040 Address@com_mtgy : 0x06433040 Address@app_mtgy : 0x400e3040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433044 Address@com_mtgy : 0x06433044 Address@app_mtgy : 0x400e3044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433048 Address@com_mtgy : 0x06433048 Address@app_mtgy : 0x400e3048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643304c Address@com_mtgy : 0x0643304c Address@app_mtgy : 0x400e304c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433050 Address@com_mtgy : 0x06433050 Address@app_mtgy : 0x400e3050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433054 Address@com_mtgy : 0x06433054 Address@app_mtgy : 0x400e3054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433058 Address@com_mtgy : 0x06433058 Address@app_mtgy : 0x400e3058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643305c Address@com_mtgy : 0x0643305c Address@app_mtgy : 0x400e305c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433060 Address@com_mtgy : 0x06433060 Address@app_mtgy : 0x400e3060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433064 Address@com_mtgy : 0x06433064 Address@app_mtgy : 0x400e3064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433068 Address@com_mtgy : 0x06433068 Address@app_mtgy : 0x400e3068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643306c Address@com_mtgy : 0x0643306c Address@app_mtgy : 0x400e306c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433070 Address@com_mtgy : 0x06433070 Address@app_mtgy : 0x400e3070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433074 Address@com_mtgy : 0x06433074 Address@app_mtgy : 0x400e3074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433078 Address@com_mtgy : 0x06433078 Address@app_mtgy : 0x400e3078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643307c Address@com_mtgy : 0x0643307c Address@app_mtgy : 0x400e307c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433080 Address@com_mtgy : 0x06433080 Address@app_mtgy : 0x400e3080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433084 Address@com_mtgy : 0x06433084 Address@app_mtgy : 0x400e3084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433088 Address@com_mtgy : 0x06433088 Address@app_mtgy : 0x400e3088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643308c Address@com_mtgy : 0x0643308c Address@app_mtgy : 0x400e308c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433090 Address@com_mtgy : 0x06433090 Address@app_mtgy : 0x400e3090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433094 Address@com_mtgy : 0x06433094 Address@app_mtgy : 0x400e3094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433098 Address@com_mtgy : 0x06433098 Address@app_mtgy : 0x400e3098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643309c Address@com_mtgy : 0x0643309c Address@app_mtgy : 0x400e309c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330a0 Address@com_mtgy : 0x064330a0 Address@app_mtgy : 0x400e30a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330a4 Address@com_mtgy : 0x064330a4 Address@app_mtgy : 0x400e30a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330a8 Address@com_mtgy : 0x064330a8 Address@app_mtgy : 0x400e30a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330ac Address@com_mtgy : 0x064330ac Address@app_mtgy : 0x400e30ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330b0 Address@com_mtgy : 0x064330b0 Address@app_mtgy : 0x400e30b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330b4 Address@com_mtgy : 0x064330b4 Address@app_mtgy : 0x400e30b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330b8 Address@com_mtgy : 0x064330b8 Address@app_mtgy : 0x400e30b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330bc Address@com_mtgy : 0x064330bc Address@app_mtgy : 0x400e30bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330c0 Address@com_mtgy : 0x064330c0 Address@app_mtgy : 0x400e30c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330c4 Address@com_mtgy : 0x064330c4 Address@app_mtgy : 0x400e30c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330c8 Address@com_mtgy : 0x064330c8 Address@app_mtgy : 0x400e30c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330cc Address@com_mtgy : 0x064330cc Address@app_mtgy : 0x400e30cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330d0 Address@com_mtgy : 0x064330d0 Address@app_mtgy : 0x400e30d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330d4 Address@com_mtgy : 0x064330d4 Address@app_mtgy : 0x400e30d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330d8 Address@com_mtgy : 0x064330d8 Address@app_mtgy : 0x400e30d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330dc Address@com_mtgy : 0x064330dc Address@app_mtgy : 0x400e30dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330e0 Address@com_mtgy : 0x064330e0 Address@app_mtgy : 0x400e30e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330e4 Address@com_mtgy : 0x064330e4 Address@app_mtgy : 0x400e30e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330e8 Address@com_mtgy : 0x064330e8 Address@app_mtgy : 0x400e30e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330ec Address@com_mtgy : 0x064330ec Address@app_mtgy : 0x400e30ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330f0 Address@com_mtgy : 0x064330f0 Address@app_mtgy : 0x400e30f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330f4 Address@com_mtgy : 0x064330f4 Address@app_mtgy : 0x400e30f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330f8 Address@com_mtgy : 0x064330f8 Address@app_mtgy : 0x400e30f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064330fc Address@com_mtgy : 0x064330fc Address@app_mtgy : 0x400e30fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433100 Address@com_mtgy : 0x06433100 Address@app_mtgy : 0x400e3100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433104 Address@com_mtgy : 0x06433104 Address@app_mtgy : 0x400e3104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433108 Address@com_mtgy : 0x06433108 Address@app_mtgy : 0x400e3108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643310c Address@com_mtgy : 0x0643310c Address@app_mtgy : 0x400e310c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433110 Address@com_mtgy : 0x06433110 Address@app_mtgy : 0x400e3110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433114 Address@com_mtgy : 0x06433114 Address@app_mtgy : 0x400e3114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433118 Address@com_mtgy : 0x06433118 Address@app_mtgy : 0x400e3118 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643311c Address@com_mtgy : 0x0643311c Address@app_mtgy : 0x400e311c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433120 Address@com_mtgy : 0x06433120 Address@app_mtgy : 0x400e3120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433124 Address@com_mtgy : 0x06433124 Address@app_mtgy : 0x400e3124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433128 Address@com_mtgy : 0x06433128 Address@app_mtgy : 0x400e3128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643312c Address@com_mtgy : 0x0643312c Address@app_mtgy : 0x400e312c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433130 Address@com_mtgy : 0x06433130 Address@app_mtgy : 0x400e3130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433134 Address@com_mtgy : 0x06433134 Address@app_mtgy : 0x400e3134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433138 Address@com_mtgy : 0x06433138 Address@app_mtgy : 0x400e3138 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643313c Address@com_mtgy : 0x0643313c Address@app_mtgy : 0x400e313c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433140 Address@com_mtgy : 0x06433140 Address@app_mtgy : 0x400e3140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433144 Address@com_mtgy : 0x06433144 Address@app_mtgy : 0x400e3144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433148 Address@com_mtgy : 0x06433148 Address@app_mtgy : 0x400e3148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643314c Address@com_mtgy : 0x0643314c Address@app_mtgy : 0x400e314c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433150 Address@com_mtgy : 0x06433150 Address@app_mtgy : 0x400e3150 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433154 Address@com_mtgy : 0x06433154 Address@app_mtgy : 0x400e3154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433158 Address@com_mtgy : 0x06433158 Address@app_mtgy : 0x400e3158 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643315c Address@com_mtgy : 0x0643315c Address@app_mtgy : 0x400e315c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433160 Address@com_mtgy : 0x06433160 Address@app_mtgy : 0x400e3160 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433164 Address@com_mtgy : 0x06433164 Address@app_mtgy : 0x400e3164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433168 Address@com_mtgy : 0x06433168 Address@app_mtgy : 0x400e3168 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643316c Address@com_mtgy : 0x0643316c Address@app_mtgy : 0x400e316c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433170 Address@com_mtgy : 0x06433170 Address@app_mtgy : 0x400e3170 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433174 Address@com_mtgy : 0x06433174 Address@app_mtgy : 0x400e3174 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433178 Address@com_mtgy : 0x06433178 Address@app_mtgy : 0x400e3178 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643317c Address@com_mtgy : 0x0643317c Address@app_mtgy : 0x400e317c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433180 Address@com_mtgy : 0x06433180 Address@app_mtgy : 0x400e3180 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433184 Address@com_mtgy : 0x06433184 Address@app_mtgy : 0x400e3184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433188 Address@com_mtgy : 0x06433188 Address@app_mtgy : 0x400e3188 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643318c Address@com_mtgy : 0x0643318c Address@app_mtgy : 0x400e318c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433190 Address@com_mtgy : 0x06433190 Address@app_mtgy : 0x400e3190 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433194 Address@com_mtgy : 0x06433194 Address@app_mtgy : 0x400e3194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433198 Address@com_mtgy : 0x06433198 Address@app_mtgy : 0x400e3198 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643319c Address@com_mtgy : 0x0643319c Address@app_mtgy : 0x400e319c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331a0 Address@com_mtgy : 0x064331a0 Address@app_mtgy : 0x400e31a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331a4 Address@com_mtgy : 0x064331a4 Address@app_mtgy : 0x400e31a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331a8 Address@com_mtgy : 0x064331a8 Address@app_mtgy : 0x400e31a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331ac Address@com_mtgy : 0x064331ac Address@app_mtgy : 0x400e31ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331b0 Address@com_mtgy : 0x064331b0 Address@app_mtgy : 0x400e31b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331b4 Address@com_mtgy : 0x064331b4 Address@app_mtgy : 0x400e31b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331b8 Address@com_mtgy : 0x064331b8 Address@app_mtgy : 0x400e31b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331bc Address@com_mtgy : 0x064331bc Address@app_mtgy : 0x400e31bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331c0 Address@com_mtgy : 0x064331c0 Address@app_mtgy : 0x400e31c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331c4 Address@com_mtgy : 0x064331c4 Address@app_mtgy : 0x400e31c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331c8 Address@com_mtgy : 0x064331c8 Address@app_mtgy : 0x400e31c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331cc Address@com_mtgy : 0x064331cc Address@app_mtgy : 0x400e31cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331d0 Address@com_mtgy : 0x064331d0 Address@app_mtgy : 0x400e31d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331d4 Address@com_mtgy : 0x064331d4 Address@app_mtgy : 0x400e31d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331d8 Address@com_mtgy : 0x064331d8 Address@app_mtgy : 0x400e31d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331dc Address@com_mtgy : 0x064331dc Address@app_mtgy : 0x400e31dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331e0 Address@com_mtgy : 0x064331e0 Address@app_mtgy : 0x400e31e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331e4 Address@com_mtgy : 0x064331e4 Address@app_mtgy : 0x400e31e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331e8 Address@com_mtgy : 0x064331e8 Address@app_mtgy : 0x400e31e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331ec Address@com_mtgy : 0x064331ec Address@app_mtgy : 0x400e31ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331f0 Address@com_mtgy : 0x064331f0 Address@app_mtgy : 0x400e31f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331f4 Address@com_mtgy : 0x064331f4 Address@app_mtgy : 0x400e31f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331f8 Address@com_mtgy : 0x064331f8 Address@app_mtgy : 0x400e31f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_tc127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064331fc Address@com_mtgy : 0x064331fc Address@app_mtgy : 0x400e31fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433200 Address@com_mtgy : 0x06433200 Address@app_mtgy : 0x400e3200 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433204 Address@com_mtgy : 0x06433204 Address@app_mtgy : 0x400e3204 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433208 Address@com_mtgy : 0x06433208 Address@app_mtgy : 0x400e3208 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643320c Address@com_mtgy : 0x0643320c Address@app_mtgy : 0x400e320c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433210 Address@com_mtgy : 0x06433210 Address@app_mtgy : 0x400e3210 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433214 Address@com_mtgy : 0x06433214 Address@app_mtgy : 0x400e3214 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433218 Address@com_mtgy : 0x06433218 Address@app_mtgy : 0x400e3218 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643321c Address@com_mtgy : 0x0643321c Address@app_mtgy : 0x400e321c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433220 Address@com_mtgy : 0x06433220 Address@app_mtgy : 0x400e3220 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433224 Address@com_mtgy : 0x06433224 Address@app_mtgy : 0x400e3224 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433228 Address@com_mtgy : 0x06433228 Address@app_mtgy : 0x400e3228 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643322c Address@com_mtgy : 0x0643322c Address@app_mtgy : 0x400e322c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433230 Address@com_mtgy : 0x06433230 Address@app_mtgy : 0x400e3230 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433234 Address@com_mtgy : 0x06433234 Address@app_mtgy : 0x400e3234 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433238 Address@com_mtgy : 0x06433238 Address@app_mtgy : 0x400e3238 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643323c Address@com_mtgy : 0x0643323c Address@app_mtgy : 0x400e323c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433240 Address@com_mtgy : 0x06433240 Address@app_mtgy : 0x400e3240 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433244 Address@com_mtgy : 0x06433244 Address@app_mtgy : 0x400e3244 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433248 Address@com_mtgy : 0x06433248 Address@app_mtgy : 0x400e3248 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643324c Address@com_mtgy : 0x0643324c Address@app_mtgy : 0x400e324c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433250 Address@com_mtgy : 0x06433250 Address@app_mtgy : 0x400e3250 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433254 Address@com_mtgy : 0x06433254 Address@app_mtgy : 0x400e3254 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433258 Address@com_mtgy : 0x06433258 Address@app_mtgy : 0x400e3258 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643325c Address@com_mtgy : 0x0643325c Address@app_mtgy : 0x400e325c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433260 Address@com_mtgy : 0x06433260 Address@app_mtgy : 0x400e3260 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433264 Address@com_mtgy : 0x06433264 Address@app_mtgy : 0x400e3264 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433268 Address@com_mtgy : 0x06433268 Address@app_mtgy : 0x400e3268 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643326c Address@com_mtgy : 0x0643326c Address@app_mtgy : 0x400e326c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433270 Address@com_mtgy : 0x06433270 Address@app_mtgy : 0x400e3270 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433274 Address@com_mtgy : 0x06433274 Address@app_mtgy : 0x400e3274 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433278 Address@com_mtgy : 0x06433278 Address@app_mtgy : 0x400e3278 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643327c Address@com_mtgy : 0x0643327c Address@app_mtgy : 0x400e327c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433280 Address@com_mtgy : 0x06433280 Address@app_mtgy : 0x400e3280 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433284 Address@com_mtgy : 0x06433284 Address@app_mtgy : 0x400e3284 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433288 Address@com_mtgy : 0x06433288 Address@app_mtgy : 0x400e3288 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643328c Address@com_mtgy : 0x0643328c Address@app_mtgy : 0x400e328c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433290 Address@com_mtgy : 0x06433290 Address@app_mtgy : 0x400e3290 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433294 Address@com_mtgy : 0x06433294 Address@app_mtgy : 0x400e3294 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433298 Address@com_mtgy : 0x06433298 Address@app_mtgy : 0x400e3298 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643329c Address@com_mtgy : 0x0643329c Address@app_mtgy : 0x400e329c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332a0 Address@com_mtgy : 0x064332a0 Address@app_mtgy : 0x400e32a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332a4 Address@com_mtgy : 0x064332a4 Address@app_mtgy : 0x400e32a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332a8 Address@com_mtgy : 0x064332a8 Address@app_mtgy : 0x400e32a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332ac Address@com_mtgy : 0x064332ac Address@app_mtgy : 0x400e32ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332b0 Address@com_mtgy : 0x064332b0 Address@app_mtgy : 0x400e32b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332b4 Address@com_mtgy : 0x064332b4 Address@app_mtgy : 0x400e32b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332b8 Address@com_mtgy : 0x064332b8 Address@app_mtgy : 0x400e32b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332bc Address@com_mtgy : 0x064332bc Address@app_mtgy : 0x400e32bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332c0 Address@com_mtgy : 0x064332c0 Address@app_mtgy : 0x400e32c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332c4 Address@com_mtgy : 0x064332c4 Address@app_mtgy : 0x400e32c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332c8 Address@com_mtgy : 0x064332c8 Address@app_mtgy : 0x400e32c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332cc Address@com_mtgy : 0x064332cc Address@app_mtgy : 0x400e32cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332d0 Address@com_mtgy : 0x064332d0 Address@app_mtgy : 0x400e32d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332d4 Address@com_mtgy : 0x064332d4 Address@app_mtgy : 0x400e32d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332d8 Address@com_mtgy : 0x064332d8 Address@app_mtgy : 0x400e32d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332dc Address@com_mtgy : 0x064332dc Address@app_mtgy : 0x400e32dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332e0 Address@com_mtgy : 0x064332e0 Address@app_mtgy : 0x400e32e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332e4 Address@com_mtgy : 0x064332e4 Address@app_mtgy : 0x400e32e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332e8 Address@com_mtgy : 0x064332e8 Address@app_mtgy : 0x400e32e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332ec Address@com_mtgy : 0x064332ec Address@app_mtgy : 0x400e32ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332f0 Address@com_mtgy : 0x064332f0 Address@app_mtgy : 0x400e32f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332f4 Address@com_mtgy : 0x064332f4 Address@app_mtgy : 0x400e32f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332f8 Address@com_mtgy : 0x064332f8 Address@app_mtgy : 0x400e32f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064332fc Address@com_mtgy : 0x064332fc Address@app_mtgy : 0x400e32fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433300 Address@com_mtgy : 0x06433300 Address@app_mtgy : 0x400e3300 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433304 Address@com_mtgy : 0x06433304 Address@app_mtgy : 0x400e3304 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433308 Address@com_mtgy : 0x06433308 Address@app_mtgy : 0x400e3308 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643330c Address@com_mtgy : 0x0643330c Address@app_mtgy : 0x400e330c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433310 Address@com_mtgy : 0x06433310 Address@app_mtgy : 0x400e3310 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433314 Address@com_mtgy : 0x06433314 Address@app_mtgy : 0x400e3314 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433318 Address@com_mtgy : 0x06433318 Address@app_mtgy : 0x400e3318 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643331c Address@com_mtgy : 0x0643331c Address@app_mtgy : 0x400e331c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433320 Address@com_mtgy : 0x06433320 Address@app_mtgy : 0x400e3320 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433324 Address@com_mtgy : 0x06433324 Address@app_mtgy : 0x400e3324 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433328 Address@com_mtgy : 0x06433328 Address@app_mtgy : 0x400e3328 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643332c Address@com_mtgy : 0x0643332c Address@app_mtgy : 0x400e332c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433330 Address@com_mtgy : 0x06433330 Address@app_mtgy : 0x400e3330 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433334 Address@com_mtgy : 0x06433334 Address@app_mtgy : 0x400e3334 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433338 Address@com_mtgy : 0x06433338 Address@app_mtgy : 0x400e3338 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643333c Address@com_mtgy : 0x0643333c Address@app_mtgy : 0x400e333c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433340 Address@com_mtgy : 0x06433340 Address@app_mtgy : 0x400e3340 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433344 Address@com_mtgy : 0x06433344 Address@app_mtgy : 0x400e3344 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433348 Address@com_mtgy : 0x06433348 Address@app_mtgy : 0x400e3348 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643334c Address@com_mtgy : 0x0643334c Address@app_mtgy : 0x400e334c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433350 Address@com_mtgy : 0x06433350 Address@app_mtgy : 0x400e3350 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433354 Address@com_mtgy : 0x06433354 Address@app_mtgy : 0x400e3354 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433358 Address@com_mtgy : 0x06433358 Address@app_mtgy : 0x400e3358 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643335c Address@com_mtgy : 0x0643335c Address@app_mtgy : 0x400e335c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433360 Address@com_mtgy : 0x06433360 Address@app_mtgy : 0x400e3360 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433364 Address@com_mtgy : 0x06433364 Address@app_mtgy : 0x400e3364 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433368 Address@com_mtgy : 0x06433368 Address@app_mtgy : 0x400e3368 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643336c Address@com_mtgy : 0x0643336c Address@app_mtgy : 0x400e336c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433370 Address@com_mtgy : 0x06433370 Address@app_mtgy : 0x400e3370 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433374 Address@com_mtgy : 0x06433374 Address@app_mtgy : 0x400e3374 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433378 Address@com_mtgy : 0x06433378 Address@app_mtgy : 0x400e3378 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643337c Address@com_mtgy : 0x0643337c Address@app_mtgy : 0x400e337c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433380 Address@com_mtgy : 0x06433380 Address@app_mtgy : 0x400e3380 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433384 Address@com_mtgy : 0x06433384 Address@app_mtgy : 0x400e3384 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433388 Address@com_mtgy : 0x06433388 Address@app_mtgy : 0x400e3388 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643338c Address@com_mtgy : 0x0643338c Address@app_mtgy : 0x400e338c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433390 Address@com_mtgy : 0x06433390 Address@app_mtgy : 0x400e3390 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433394 Address@com_mtgy : 0x06433394 Address@app_mtgy : 0x400e3394 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433398 Address@com_mtgy : 0x06433398 Address@app_mtgy : 0x400e3398 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643339c Address@com_mtgy : 0x0643339c Address@app_mtgy : 0x400e339c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333a0 Address@com_mtgy : 0x064333a0 Address@app_mtgy : 0x400e33a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333a4 Address@com_mtgy : 0x064333a4 Address@app_mtgy : 0x400e33a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333a8 Address@com_mtgy : 0x064333a8 Address@app_mtgy : 0x400e33a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333ac Address@com_mtgy : 0x064333ac Address@app_mtgy : 0x400e33ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333b0 Address@com_mtgy : 0x064333b0 Address@app_mtgy : 0x400e33b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333b4 Address@com_mtgy : 0x064333b4 Address@app_mtgy : 0x400e33b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333b8 Address@com_mtgy : 0x064333b8 Address@app_mtgy : 0x400e33b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333bc Address@com_mtgy : 0x064333bc Address@app_mtgy : 0x400e33bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333c0 Address@com_mtgy : 0x064333c0 Address@app_mtgy : 0x400e33c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333c4 Address@com_mtgy : 0x064333c4 Address@app_mtgy : 0x400e33c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333c8 Address@com_mtgy : 0x064333c8 Address@app_mtgy : 0x400e33c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333cc Address@com_mtgy : 0x064333cc Address@app_mtgy : 0x400e33cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333d0 Address@com_mtgy : 0x064333d0 Address@app_mtgy : 0x400e33d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333d4 Address@com_mtgy : 0x064333d4 Address@app_mtgy : 0x400e33d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333d8 Address@com_mtgy : 0x064333d8 Address@app_mtgy : 0x400e33d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333dc Address@com_mtgy : 0x064333dc Address@app_mtgy : 0x400e33dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333e0 Address@com_mtgy : 0x064333e0 Address@app_mtgy : 0x400e33e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333e4 Address@com_mtgy : 0x064333e4 Address@app_mtgy : 0x400e33e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333e8 Address@com_mtgy : 0x064333e8 Address@app_mtgy : 0x400e33e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333ec Address@com_mtgy : 0x064333ec Address@app_mtgy : 0x400e33ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333f0 Address@com_mtgy : 0x064333f0 Address@app_mtgy : 0x400e33f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333f4 Address@com_mtgy : 0x064333f4 Address@app_mtgy : 0x400e33f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333f8 Address@com_mtgy : 0x064333f8 Address@app_mtgy : 0x400e33f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_ts127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064333fc Address@com_mtgy : 0x064333fc Address@app_mtgy : 0x400e33fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433400 Address@com_mtgy : 0x06433400 Address@app_mtgy : 0x400e3400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433404 Address@com_mtgy : 0x06433404 Address@app_mtgy : 0x400e3404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433408 Address@com_mtgy : 0x06433408 Address@app_mtgy : 0x400e3408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643340c Address@com_mtgy : 0x0643340c Address@app_mtgy : 0x400e340c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433410 Address@com_mtgy : 0x06433410 Address@app_mtgy : 0x400e3410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433414 Address@com_mtgy : 0x06433414 Address@app_mtgy : 0x400e3414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433418 Address@com_mtgy : 0x06433418 Address@app_mtgy : 0x400e3418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643341c Address@com_mtgy : 0x0643341c Address@app_mtgy : 0x400e341c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433420 Address@com_mtgy : 0x06433420 Address@app_mtgy : 0x400e3420 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433424 Address@com_mtgy : 0x06433424 Address@app_mtgy : 0x400e3424 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433428 Address@com_mtgy : 0x06433428 Address@app_mtgy : 0x400e3428 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643342c Address@com_mtgy : 0x0643342c Address@app_mtgy : 0x400e342c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433430 Address@com_mtgy : 0x06433430 Address@app_mtgy : 0x400e3430 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433434 Address@com_mtgy : 0x06433434 Address@app_mtgy : 0x400e3434 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433438 Address@com_mtgy : 0x06433438 Address@app_mtgy : 0x400e3438 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643343c Address@com_mtgy : 0x0643343c Address@app_mtgy : 0x400e343c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433440 Address@com_mtgy : 0x06433440 Address@app_mtgy : 0x400e3440 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433444 Address@com_mtgy : 0x06433444 Address@app_mtgy : 0x400e3444 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433448 Address@com_mtgy : 0x06433448 Address@app_mtgy : 0x400e3448 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643344c Address@com_mtgy : 0x0643344c Address@app_mtgy : 0x400e344c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433450 Address@com_mtgy : 0x06433450 Address@app_mtgy : 0x400e3450 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433454 Address@com_mtgy : 0x06433454 Address@app_mtgy : 0x400e3454 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433458 Address@com_mtgy : 0x06433458 Address@app_mtgy : 0x400e3458 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643345c Address@com_mtgy : 0x0643345c Address@app_mtgy : 0x400e345c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433460 Address@com_mtgy : 0x06433460 Address@app_mtgy : 0x400e3460 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433464 Address@com_mtgy : 0x06433464 Address@app_mtgy : 0x400e3464 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433468 Address@com_mtgy : 0x06433468 Address@app_mtgy : 0x400e3468 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643346c Address@com_mtgy : 0x0643346c Address@app_mtgy : 0x400e346c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433470 Address@com_mtgy : 0x06433470 Address@app_mtgy : 0x400e3470 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433474 Address@com_mtgy : 0x06433474 Address@app_mtgy : 0x400e3474 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433478 Address@com_mtgy : 0x06433478 Address@app_mtgy : 0x400e3478 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643347c Address@com_mtgy : 0x0643347c Address@app_mtgy : 0x400e347c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433480 Address@com_mtgy : 0x06433480 Address@app_mtgy : 0x400e3480 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433484 Address@com_mtgy : 0x06433484 Address@app_mtgy : 0x400e3484 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433488 Address@com_mtgy : 0x06433488 Address@app_mtgy : 0x400e3488 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643348c Address@com_mtgy : 0x0643348c Address@app_mtgy : 0x400e348c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433490 Address@com_mtgy : 0x06433490 Address@app_mtgy : 0x400e3490 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433494 Address@com_mtgy : 0x06433494 Address@app_mtgy : 0x400e3494 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433498 Address@com_mtgy : 0x06433498 Address@app_mtgy : 0x400e3498 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643349c Address@com_mtgy : 0x0643349c Address@app_mtgy : 0x400e349c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334a0 Address@com_mtgy : 0x064334a0 Address@app_mtgy : 0x400e34a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334a4 Address@com_mtgy : 0x064334a4 Address@app_mtgy : 0x400e34a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334a8 Address@com_mtgy : 0x064334a8 Address@app_mtgy : 0x400e34a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334ac Address@com_mtgy : 0x064334ac Address@app_mtgy : 0x400e34ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334b0 Address@com_mtgy : 0x064334b0 Address@app_mtgy : 0x400e34b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334b4 Address@com_mtgy : 0x064334b4 Address@app_mtgy : 0x400e34b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334b8 Address@com_mtgy : 0x064334b8 Address@app_mtgy : 0x400e34b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334bc Address@com_mtgy : 0x064334bc Address@app_mtgy : 0x400e34bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334c0 Address@com_mtgy : 0x064334c0 Address@app_mtgy : 0x400e34c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334c4 Address@com_mtgy : 0x064334c4 Address@app_mtgy : 0x400e34c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334c8 Address@com_mtgy : 0x064334c8 Address@app_mtgy : 0x400e34c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334cc Address@com_mtgy : 0x064334cc Address@app_mtgy : 0x400e34cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334d0 Address@com_mtgy : 0x064334d0 Address@app_mtgy : 0x400e34d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334d4 Address@com_mtgy : 0x064334d4 Address@app_mtgy : 0x400e34d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334d8 Address@com_mtgy : 0x064334d8 Address@app_mtgy : 0x400e34d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334dc Address@com_mtgy : 0x064334dc Address@app_mtgy : 0x400e34dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334e0 Address@com_mtgy : 0x064334e0 Address@app_mtgy : 0x400e34e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334e4 Address@com_mtgy : 0x064334e4 Address@app_mtgy : 0x400e34e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334e8 Address@com_mtgy : 0x064334e8 Address@app_mtgy : 0x400e34e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334ec Address@com_mtgy : 0x064334ec Address@app_mtgy : 0x400e34ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334f0 Address@com_mtgy : 0x064334f0 Address@app_mtgy : 0x400e34f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334f4 Address@com_mtgy : 0x064334f4 Address@app_mtgy : 0x400e34f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334f8 Address@com_mtgy : 0x064334f8 Address@app_mtgy : 0x400e34f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064334fc Address@com_mtgy : 0x064334fc Address@app_mtgy : 0x400e34fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433500 Address@com_mtgy : 0x06433500 Address@app_mtgy : 0x400e3500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433504 Address@com_mtgy : 0x06433504 Address@app_mtgy : 0x400e3504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433508 Address@com_mtgy : 0x06433508 Address@app_mtgy : 0x400e3508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643350c Address@com_mtgy : 0x0643350c Address@app_mtgy : 0x400e350c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433510 Address@com_mtgy : 0x06433510 Address@app_mtgy : 0x400e3510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433514 Address@com_mtgy : 0x06433514 Address@app_mtgy : 0x400e3514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433518 Address@com_mtgy : 0x06433518 Address@app_mtgy : 0x400e3518 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643351c Address@com_mtgy : 0x0643351c Address@app_mtgy : 0x400e351c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433520 Address@com_mtgy : 0x06433520 Address@app_mtgy : 0x400e3520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433524 Address@com_mtgy : 0x06433524 Address@app_mtgy : 0x400e3524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433528 Address@com_mtgy : 0x06433528 Address@app_mtgy : 0x400e3528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643352c Address@com_mtgy : 0x0643352c Address@app_mtgy : 0x400e352c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433530 Address@com_mtgy : 0x06433530 Address@app_mtgy : 0x400e3530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433534 Address@com_mtgy : 0x06433534 Address@app_mtgy : 0x400e3534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433538 Address@com_mtgy : 0x06433538 Address@app_mtgy : 0x400e3538 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643353c Address@com_mtgy : 0x0643353c Address@app_mtgy : 0x400e353c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433540 Address@com_mtgy : 0x06433540 Address@app_mtgy : 0x400e3540 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433544 Address@com_mtgy : 0x06433544 Address@app_mtgy : 0x400e3544 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433548 Address@com_mtgy : 0x06433548 Address@app_mtgy : 0x400e3548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643354c Address@com_mtgy : 0x0643354c Address@app_mtgy : 0x400e354c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433550 Address@com_mtgy : 0x06433550 Address@app_mtgy : 0x400e3550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433554 Address@com_mtgy : 0x06433554 Address@app_mtgy : 0x400e3554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433558 Address@com_mtgy : 0x06433558 Address@app_mtgy : 0x400e3558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643355c Address@com_mtgy : 0x0643355c Address@app_mtgy : 0x400e355c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433560 Address@com_mtgy : 0x06433560 Address@app_mtgy : 0x400e3560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433564 Address@com_mtgy : 0x06433564 Address@app_mtgy : 0x400e3564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433568 Address@com_mtgy : 0x06433568 Address@app_mtgy : 0x400e3568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643356c Address@com_mtgy : 0x0643356c Address@app_mtgy : 0x400e356c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433570 Address@com_mtgy : 0x06433570 Address@app_mtgy : 0x400e3570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433574 Address@com_mtgy : 0x06433574 Address@app_mtgy : 0x400e3574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433578 Address@com_mtgy : 0x06433578 Address@app_mtgy : 0x400e3578 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643357c Address@com_mtgy : 0x0643357c Address@app_mtgy : 0x400e357c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433580 Address@com_mtgy : 0x06433580 Address@app_mtgy : 0x400e3580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433584 Address@com_mtgy : 0x06433584 Address@app_mtgy : 0x400e3584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433588 Address@com_mtgy : 0x06433588 Address@app_mtgy : 0x400e3588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643358c Address@com_mtgy : 0x0643358c Address@app_mtgy : 0x400e358c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433590 Address@com_mtgy : 0x06433590 Address@app_mtgy : 0x400e3590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433594 Address@com_mtgy : 0x06433594 Address@app_mtgy : 0x400e3594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433598 Address@com_mtgy : 0x06433598 Address@app_mtgy : 0x400e3598 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643359c Address@com_mtgy : 0x0643359c Address@app_mtgy : 0x400e359c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335a0 Address@com_mtgy : 0x064335a0 Address@app_mtgy : 0x400e35a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335a4 Address@com_mtgy : 0x064335a4 Address@app_mtgy : 0x400e35a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335a8 Address@com_mtgy : 0x064335a8 Address@app_mtgy : 0x400e35a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335ac Address@com_mtgy : 0x064335ac Address@app_mtgy : 0x400e35ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335b0 Address@com_mtgy : 0x064335b0 Address@app_mtgy : 0x400e35b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335b4 Address@com_mtgy : 0x064335b4 Address@app_mtgy : 0x400e35b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335b8 Address@com_mtgy : 0x064335b8 Address@app_mtgy : 0x400e35b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335bc Address@com_mtgy : 0x064335bc Address@app_mtgy : 0x400e35bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335c0 Address@com_mtgy : 0x064335c0 Address@app_mtgy : 0x400e35c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335c4 Address@com_mtgy : 0x064335c4 Address@app_mtgy : 0x400e35c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335c8 Address@com_mtgy : 0x064335c8 Address@app_mtgy : 0x400e35c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335cc Address@com_mtgy : 0x064335cc Address@app_mtgy : 0x400e35cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335d0 Address@com_mtgy : 0x064335d0 Address@app_mtgy : 0x400e35d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335d4 Address@com_mtgy : 0x064335d4 Address@app_mtgy : 0x400e35d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335d8 Address@com_mtgy : 0x064335d8 Address@app_mtgy : 0x400e35d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335dc Address@com_mtgy : 0x064335dc Address@app_mtgy : 0x400e35dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335e0 Address@com_mtgy : 0x064335e0 Address@app_mtgy : 0x400e35e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335e4 Address@com_mtgy : 0x064335e4 Address@app_mtgy : 0x400e35e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335e8 Address@com_mtgy : 0x064335e8 Address@app_mtgy : 0x400e35e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335ec Address@com_mtgy : 0x064335ec Address@app_mtgy : 0x400e35ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335f0 Address@com_mtgy : 0x064335f0 Address@app_mtgy : 0x400e35f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335f4 Address@com_mtgy : 0x064335f4 Address@app_mtgy : 0x400e35f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335f8 Address@com_mtgy : 0x064335f8 Address@app_mtgy : 0x400e35f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_p127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064335fc Address@com_mtgy : 0x064335fc Address@app_mtgy : 0x400e35fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433600 Address@com_mtgy : 0x06433600 Address@app_mtgy : 0x400e3600 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433604 Address@com_mtgy : 0x06433604 Address@app_mtgy : 0x400e3604 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433608 Address@com_mtgy : 0x06433608 Address@app_mtgy : 0x400e3608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643360c Address@com_mtgy : 0x0643360c Address@app_mtgy : 0x400e360c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433610 Address@com_mtgy : 0x06433610 Address@app_mtgy : 0x400e3610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433614 Address@com_mtgy : 0x06433614 Address@app_mtgy : 0x400e3614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433618 Address@com_mtgy : 0x06433618 Address@app_mtgy : 0x400e3618 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643361c Address@com_mtgy : 0x0643361c Address@app_mtgy : 0x400e361c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433620 Address@com_mtgy : 0x06433620 Address@app_mtgy : 0x400e3620 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433624 Address@com_mtgy : 0x06433624 Address@app_mtgy : 0x400e3624 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433628 Address@com_mtgy : 0x06433628 Address@app_mtgy : 0x400e3628 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643362c Address@com_mtgy : 0x0643362c Address@app_mtgy : 0x400e362c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433630 Address@com_mtgy : 0x06433630 Address@app_mtgy : 0x400e3630 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433634 Address@com_mtgy : 0x06433634 Address@app_mtgy : 0x400e3634 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433638 Address@com_mtgy : 0x06433638 Address@app_mtgy : 0x400e3638 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643363c Address@com_mtgy : 0x0643363c Address@app_mtgy : 0x400e363c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433640 Address@com_mtgy : 0x06433640 Address@app_mtgy : 0x400e3640 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433644 Address@com_mtgy : 0x06433644 Address@app_mtgy : 0x400e3644 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433648 Address@com_mtgy : 0x06433648 Address@app_mtgy : 0x400e3648 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643364c Address@com_mtgy : 0x0643364c Address@app_mtgy : 0x400e364c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433650 Address@com_mtgy : 0x06433650 Address@app_mtgy : 0x400e3650 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433654 Address@com_mtgy : 0x06433654 Address@app_mtgy : 0x400e3654 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433658 Address@com_mtgy : 0x06433658 Address@app_mtgy : 0x400e3658 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643365c Address@com_mtgy : 0x0643365c Address@app_mtgy : 0x400e365c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433660 Address@com_mtgy : 0x06433660 Address@app_mtgy : 0x400e3660 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433664 Address@com_mtgy : 0x06433664 Address@app_mtgy : 0x400e3664 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433668 Address@com_mtgy : 0x06433668 Address@app_mtgy : 0x400e3668 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643366c Address@com_mtgy : 0x0643366c Address@app_mtgy : 0x400e366c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433670 Address@com_mtgy : 0x06433670 Address@app_mtgy : 0x400e3670 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433674 Address@com_mtgy : 0x06433674 Address@app_mtgy : 0x400e3674 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433678 Address@com_mtgy : 0x06433678 Address@app_mtgy : 0x400e3678 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643367c Address@com_mtgy : 0x0643367c Address@app_mtgy : 0x400e367c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433680 Address@com_mtgy : 0x06433680 Address@app_mtgy : 0x400e3680 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433684 Address@com_mtgy : 0x06433684 Address@app_mtgy : 0x400e3684 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433688 Address@com_mtgy : 0x06433688 Address@app_mtgy : 0x400e3688 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643368c Address@com_mtgy : 0x0643368c Address@app_mtgy : 0x400e368c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433690 Address@com_mtgy : 0x06433690 Address@app_mtgy : 0x400e3690 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433694 Address@com_mtgy : 0x06433694 Address@app_mtgy : 0x400e3694 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433698 Address@com_mtgy : 0x06433698 Address@app_mtgy : 0x400e3698 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643369c Address@com_mtgy : 0x0643369c Address@app_mtgy : 0x400e369c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336a0 Address@com_mtgy : 0x064336a0 Address@app_mtgy : 0x400e36a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336a4 Address@com_mtgy : 0x064336a4 Address@app_mtgy : 0x400e36a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336a8 Address@com_mtgy : 0x064336a8 Address@app_mtgy : 0x400e36a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336ac Address@com_mtgy : 0x064336ac Address@app_mtgy : 0x400e36ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336b0 Address@com_mtgy : 0x064336b0 Address@app_mtgy : 0x400e36b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336b4 Address@com_mtgy : 0x064336b4 Address@app_mtgy : 0x400e36b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336b8 Address@com_mtgy : 0x064336b8 Address@app_mtgy : 0x400e36b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336bc Address@com_mtgy : 0x064336bc Address@app_mtgy : 0x400e36bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336c0 Address@com_mtgy : 0x064336c0 Address@app_mtgy : 0x400e36c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336c4 Address@com_mtgy : 0x064336c4 Address@app_mtgy : 0x400e36c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336c8 Address@com_mtgy : 0x064336c8 Address@app_mtgy : 0x400e36c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336cc Address@com_mtgy : 0x064336cc Address@app_mtgy : 0x400e36cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336d0 Address@com_mtgy : 0x064336d0 Address@app_mtgy : 0x400e36d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336d4 Address@com_mtgy : 0x064336d4 Address@app_mtgy : 0x400e36d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336d8 Address@com_mtgy : 0x064336d8 Address@app_mtgy : 0x400e36d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336dc Address@com_mtgy : 0x064336dc Address@app_mtgy : 0x400e36dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336e0 Address@com_mtgy : 0x064336e0 Address@app_mtgy : 0x400e36e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336e4 Address@com_mtgy : 0x064336e4 Address@app_mtgy : 0x400e36e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336e8 Address@com_mtgy : 0x064336e8 Address@app_mtgy : 0x400e36e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336ec Address@com_mtgy : 0x064336ec Address@app_mtgy : 0x400e36ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336f0 Address@com_mtgy : 0x064336f0 Address@app_mtgy : 0x400e36f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336f4 Address@com_mtgy : 0x064336f4 Address@app_mtgy : 0x400e36f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336f8 Address@com_mtgy : 0x064336f8 Address@app_mtgy : 0x400e36f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064336fc Address@com_mtgy : 0x064336fc Address@app_mtgy : 0x400e36fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433700 Address@com_mtgy : 0x06433700 Address@app_mtgy : 0x400e3700 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433704 Address@com_mtgy : 0x06433704 Address@app_mtgy : 0x400e3704 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433708 Address@com_mtgy : 0x06433708 Address@app_mtgy : 0x400e3708 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643370c Address@com_mtgy : 0x0643370c Address@app_mtgy : 0x400e370c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433710 Address@com_mtgy : 0x06433710 Address@app_mtgy : 0x400e3710 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433714 Address@com_mtgy : 0x06433714 Address@app_mtgy : 0x400e3714 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433718 Address@com_mtgy : 0x06433718 Address@app_mtgy : 0x400e3718 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643371c Address@com_mtgy : 0x0643371c Address@app_mtgy : 0x400e371c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433720 Address@com_mtgy : 0x06433720 Address@app_mtgy : 0x400e3720 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433724 Address@com_mtgy : 0x06433724 Address@app_mtgy : 0x400e3724 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433728 Address@com_mtgy : 0x06433728 Address@app_mtgy : 0x400e3728 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643372c Address@com_mtgy : 0x0643372c Address@app_mtgy : 0x400e372c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433730 Address@com_mtgy : 0x06433730 Address@app_mtgy : 0x400e3730 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433734 Address@com_mtgy : 0x06433734 Address@app_mtgy : 0x400e3734 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433738 Address@com_mtgy : 0x06433738 Address@app_mtgy : 0x400e3738 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643373c Address@com_mtgy : 0x0643373c Address@app_mtgy : 0x400e373c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433740 Address@com_mtgy : 0x06433740 Address@app_mtgy : 0x400e3740 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433744 Address@com_mtgy : 0x06433744 Address@app_mtgy : 0x400e3744 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433748 Address@com_mtgy : 0x06433748 Address@app_mtgy : 0x400e3748 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643374c Address@com_mtgy : 0x0643374c Address@app_mtgy : 0x400e374c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433750 Address@com_mtgy : 0x06433750 Address@app_mtgy : 0x400e3750 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433754 Address@com_mtgy : 0x06433754 Address@app_mtgy : 0x400e3754 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433758 Address@com_mtgy : 0x06433758 Address@app_mtgy : 0x400e3758 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643375c Address@com_mtgy : 0x0643375c Address@app_mtgy : 0x400e375c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433760 Address@com_mtgy : 0x06433760 Address@app_mtgy : 0x400e3760 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433764 Address@com_mtgy : 0x06433764 Address@app_mtgy : 0x400e3764 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433768 Address@com_mtgy : 0x06433768 Address@app_mtgy : 0x400e3768 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643376c Address@com_mtgy : 0x0643376c Address@app_mtgy : 0x400e376c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433770 Address@com_mtgy : 0x06433770 Address@app_mtgy : 0x400e3770 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433774 Address@com_mtgy : 0x06433774 Address@app_mtgy : 0x400e3774 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433778 Address@com_mtgy : 0x06433778 Address@app_mtgy : 0x400e3778 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643377c Address@com_mtgy : 0x0643377c Address@app_mtgy : 0x400e377c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433780 Address@com_mtgy : 0x06433780 Address@app_mtgy : 0x400e3780 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433784 Address@com_mtgy : 0x06433784 Address@app_mtgy : 0x400e3784 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433788 Address@com_mtgy : 0x06433788 Address@app_mtgy : 0x400e3788 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643378c Address@com_mtgy : 0x0643378c Address@app_mtgy : 0x400e378c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433790 Address@com_mtgy : 0x06433790 Address@app_mtgy : 0x400e3790 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433794 Address@com_mtgy : 0x06433794 Address@app_mtgy : 0x400e3794 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433798 Address@com_mtgy : 0x06433798 Address@app_mtgy : 0x400e3798 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643379c Address@com_mtgy : 0x0643379c Address@app_mtgy : 0x400e379c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337a0 Address@com_mtgy : 0x064337a0 Address@app_mtgy : 0x400e37a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337a4 Address@com_mtgy : 0x064337a4 Address@app_mtgy : 0x400e37a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337a8 Address@com_mtgy : 0x064337a8 Address@app_mtgy : 0x400e37a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337ac Address@com_mtgy : 0x064337ac Address@app_mtgy : 0x400e37ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337b0 Address@com_mtgy : 0x064337b0 Address@app_mtgy : 0x400e37b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337b4 Address@com_mtgy : 0x064337b4 Address@app_mtgy : 0x400e37b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337b8 Address@com_mtgy : 0x064337b8 Address@app_mtgy : 0x400e37b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337bc Address@com_mtgy : 0x064337bc Address@app_mtgy : 0x400e37bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337c0 Address@com_mtgy : 0x064337c0 Address@app_mtgy : 0x400e37c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337c4 Address@com_mtgy : 0x064337c4 Address@app_mtgy : 0x400e37c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337c8 Address@com_mtgy : 0x064337c8 Address@app_mtgy : 0x400e37c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337cc Address@com_mtgy : 0x064337cc Address@app_mtgy : 0x400e37cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337d0 Address@com_mtgy : 0x064337d0 Address@app_mtgy : 0x400e37d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337d4 Address@com_mtgy : 0x064337d4 Address@app_mtgy : 0x400e37d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337d8 Address@com_mtgy : 0x064337d8 Address@app_mtgy : 0x400e37d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337dc Address@com_mtgy : 0x064337dc Address@app_mtgy : 0x400e37dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337e0 Address@com_mtgy : 0x064337e0 Address@app_mtgy : 0x400e37e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337e4 Address@com_mtgy : 0x064337e4 Address@app_mtgy : 0x400e37e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337e8 Address@com_mtgy : 0x064337e8 Address@app_mtgy : 0x400e37e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337ec Address@com_mtgy : 0x064337ec Address@app_mtgy : 0x400e37ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337f0 Address@com_mtgy : 0x064337f0 Address@app_mtgy : 0x400e37f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337f4 Address@com_mtgy : 0x064337f4 Address@app_mtgy : 0x400e37f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337f8 Address@com_mtgy : 0x064337f8 Address@app_mtgy : 0x400e37f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_b127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064337fc Address@com_mtgy : 0x064337fc Address@app_mtgy : 0x400e37fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433800 Address@com_mtgy : 0x06433800 Address@app_mtgy : 0x400e3800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433804 Address@com_mtgy : 0x06433804 Address@app_mtgy : 0x400e3804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433808 Address@com_mtgy : 0x06433808 Address@app_mtgy : 0x400e3808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643380c Address@com_mtgy : 0x0643380c Address@app_mtgy : 0x400e380c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433810 Address@com_mtgy : 0x06433810 Address@app_mtgy : 0x400e3810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433814 Address@com_mtgy : 0x06433814 Address@app_mtgy : 0x400e3814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433818 Address@com_mtgy : 0x06433818 Address@app_mtgy : 0x400e3818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643381c Address@com_mtgy : 0x0643381c Address@app_mtgy : 0x400e381c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433820 Address@com_mtgy : 0x06433820 Address@app_mtgy : 0x400e3820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433824 Address@com_mtgy : 0x06433824 Address@app_mtgy : 0x400e3824 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433828 Address@com_mtgy : 0x06433828 Address@app_mtgy : 0x400e3828 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643382c Address@com_mtgy : 0x0643382c Address@app_mtgy : 0x400e382c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433830 Address@com_mtgy : 0x06433830 Address@app_mtgy : 0x400e3830 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433834 Address@com_mtgy : 0x06433834 Address@app_mtgy : 0x400e3834 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433838 Address@com_mtgy : 0x06433838 Address@app_mtgy : 0x400e3838 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643383c Address@com_mtgy : 0x0643383c Address@app_mtgy : 0x400e383c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433840 Address@com_mtgy : 0x06433840 Address@app_mtgy : 0x400e3840 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433844 Address@com_mtgy : 0x06433844 Address@app_mtgy : 0x400e3844 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433848 Address@com_mtgy : 0x06433848 Address@app_mtgy : 0x400e3848 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643384c Address@com_mtgy : 0x0643384c Address@app_mtgy : 0x400e384c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433850 Address@com_mtgy : 0x06433850 Address@app_mtgy : 0x400e3850 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433854 Address@com_mtgy : 0x06433854 Address@app_mtgy : 0x400e3854 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433858 Address@com_mtgy : 0x06433858 Address@app_mtgy : 0x400e3858 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643385c Address@com_mtgy : 0x0643385c Address@app_mtgy : 0x400e385c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433860 Address@com_mtgy : 0x06433860 Address@app_mtgy : 0x400e3860 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433864 Address@com_mtgy : 0x06433864 Address@app_mtgy : 0x400e3864 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433868 Address@com_mtgy : 0x06433868 Address@app_mtgy : 0x400e3868 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643386c Address@com_mtgy : 0x0643386c Address@app_mtgy : 0x400e386c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433870 Address@com_mtgy : 0x06433870 Address@app_mtgy : 0x400e3870 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433874 Address@com_mtgy : 0x06433874 Address@app_mtgy : 0x400e3874 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433878 Address@com_mtgy : 0x06433878 Address@app_mtgy : 0x400e3878 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643387c Address@com_mtgy : 0x0643387c Address@app_mtgy : 0x400e387c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433880 Address@com_mtgy : 0x06433880 Address@app_mtgy : 0x400e3880 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433884 Address@com_mtgy : 0x06433884 Address@app_mtgy : 0x400e3884 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433888 Address@com_mtgy : 0x06433888 Address@app_mtgy : 0x400e3888 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643388c Address@com_mtgy : 0x0643388c Address@app_mtgy : 0x400e388c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433890 Address@com_mtgy : 0x06433890 Address@app_mtgy : 0x400e3890 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433894 Address@com_mtgy : 0x06433894 Address@app_mtgy : 0x400e3894 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433898 Address@com_mtgy : 0x06433898 Address@app_mtgy : 0x400e3898 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643389c Address@com_mtgy : 0x0643389c Address@app_mtgy : 0x400e389c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338a0 Address@com_mtgy : 0x064338a0 Address@app_mtgy : 0x400e38a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338a4 Address@com_mtgy : 0x064338a4 Address@app_mtgy : 0x400e38a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338a8 Address@com_mtgy : 0x064338a8 Address@app_mtgy : 0x400e38a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338ac Address@com_mtgy : 0x064338ac Address@app_mtgy : 0x400e38ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338b0 Address@com_mtgy : 0x064338b0 Address@app_mtgy : 0x400e38b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338b4 Address@com_mtgy : 0x064338b4 Address@app_mtgy : 0x400e38b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338b8 Address@com_mtgy : 0x064338b8 Address@app_mtgy : 0x400e38b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338bc Address@com_mtgy : 0x064338bc Address@app_mtgy : 0x400e38bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338c0 Address@com_mtgy : 0x064338c0 Address@app_mtgy : 0x400e38c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338c4 Address@com_mtgy : 0x064338c4 Address@app_mtgy : 0x400e38c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338c8 Address@com_mtgy : 0x064338c8 Address@app_mtgy : 0x400e38c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338cc Address@com_mtgy : 0x064338cc Address@app_mtgy : 0x400e38cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338d0 Address@com_mtgy : 0x064338d0 Address@app_mtgy : 0x400e38d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338d4 Address@com_mtgy : 0x064338d4 Address@app_mtgy : 0x400e38d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338d8 Address@com_mtgy : 0x064338d8 Address@app_mtgy : 0x400e38d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338dc Address@com_mtgy : 0x064338dc Address@app_mtgy : 0x400e38dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338e0 Address@com_mtgy : 0x064338e0 Address@app_mtgy : 0x400e38e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338e4 Address@com_mtgy : 0x064338e4 Address@app_mtgy : 0x400e38e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338e8 Address@com_mtgy : 0x064338e8 Address@app_mtgy : 0x400e38e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338ec Address@com_mtgy : 0x064338ec Address@app_mtgy : 0x400e38ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338f0 Address@com_mtgy : 0x064338f0 Address@app_mtgy : 0x400e38f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338f4 Address@com_mtgy : 0x064338f4 Address@app_mtgy : 0x400e38f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338f8 Address@com_mtgy : 0x064338f8 Address@app_mtgy : 0x400e38f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064338fc Address@com_mtgy : 0x064338fc Address@app_mtgy : 0x400e38fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433900 Address@com_mtgy : 0x06433900 Address@app_mtgy : 0x400e3900 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433904 Address@com_mtgy : 0x06433904 Address@app_mtgy : 0x400e3904 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433908 Address@com_mtgy : 0x06433908 Address@app_mtgy : 0x400e3908 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643390c Address@com_mtgy : 0x0643390c Address@app_mtgy : 0x400e390c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433910 Address@com_mtgy : 0x06433910 Address@app_mtgy : 0x400e3910 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433914 Address@com_mtgy : 0x06433914 Address@app_mtgy : 0x400e3914 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433918 Address@com_mtgy : 0x06433918 Address@app_mtgy : 0x400e3918 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643391c Address@com_mtgy : 0x0643391c Address@app_mtgy : 0x400e391c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433920 Address@com_mtgy : 0x06433920 Address@app_mtgy : 0x400e3920 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433924 Address@com_mtgy : 0x06433924 Address@app_mtgy : 0x400e3924 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433928 Address@com_mtgy : 0x06433928 Address@app_mtgy : 0x400e3928 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643392c Address@com_mtgy : 0x0643392c Address@app_mtgy : 0x400e392c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433930 Address@com_mtgy : 0x06433930 Address@app_mtgy : 0x400e3930 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433934 Address@com_mtgy : 0x06433934 Address@app_mtgy : 0x400e3934 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433938 Address@com_mtgy : 0x06433938 Address@app_mtgy : 0x400e3938 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643393c Address@com_mtgy : 0x0643393c Address@app_mtgy : 0x400e393c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433940 Address@com_mtgy : 0x06433940 Address@app_mtgy : 0x400e3940 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433944 Address@com_mtgy : 0x06433944 Address@app_mtgy : 0x400e3944 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433948 Address@com_mtgy : 0x06433948 Address@app_mtgy : 0x400e3948 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643394c Address@com_mtgy : 0x0643394c Address@app_mtgy : 0x400e394c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433950 Address@com_mtgy : 0x06433950 Address@app_mtgy : 0x400e3950 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433954 Address@com_mtgy : 0x06433954 Address@app_mtgy : 0x400e3954 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433958 Address@com_mtgy : 0x06433958 Address@app_mtgy : 0x400e3958 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643395c Address@com_mtgy : 0x0643395c Address@app_mtgy : 0x400e395c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433960 Address@com_mtgy : 0x06433960 Address@app_mtgy : 0x400e3960 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433964 Address@com_mtgy : 0x06433964 Address@app_mtgy : 0x400e3964 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433968 Address@com_mtgy : 0x06433968 Address@app_mtgy : 0x400e3968 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643396c Address@com_mtgy : 0x0643396c Address@app_mtgy : 0x400e396c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433970 Address@com_mtgy : 0x06433970 Address@app_mtgy : 0x400e3970 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433974 Address@com_mtgy : 0x06433974 Address@app_mtgy : 0x400e3974 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433978 Address@com_mtgy : 0x06433978 Address@app_mtgy : 0x400e3978 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643397c Address@com_mtgy : 0x0643397c Address@app_mtgy : 0x400e397c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433980 Address@com_mtgy : 0x06433980 Address@app_mtgy : 0x400e3980 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433984 Address@com_mtgy : 0x06433984 Address@app_mtgy : 0x400e3984 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433988 Address@com_mtgy : 0x06433988 Address@app_mtgy : 0x400e3988 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643398c Address@com_mtgy : 0x0643398c Address@app_mtgy : 0x400e398c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433990 Address@com_mtgy : 0x06433990 Address@app_mtgy : 0x400e3990 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433994 Address@com_mtgy : 0x06433994 Address@app_mtgy : 0x400e3994 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433998 Address@com_mtgy : 0x06433998 Address@app_mtgy : 0x400e3998 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x0643399c Address@com_mtgy : 0x0643399c Address@app_mtgy : 0x400e399c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339a0 Address@com_mtgy : 0x064339a0 Address@app_mtgy : 0x400e39a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339a4 Address@com_mtgy : 0x064339a4 Address@app_mtgy : 0x400e39a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339a8 Address@com_mtgy : 0x064339a8 Address@app_mtgy : 0x400e39a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339ac Address@com_mtgy : 0x064339ac Address@app_mtgy : 0x400e39ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339b0 Address@com_mtgy : 0x064339b0 Address@app_mtgy : 0x400e39b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339b4 Address@com_mtgy : 0x064339b4 Address@app_mtgy : 0x400e39b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339b8 Address@com_mtgy : 0x064339b8 Address@app_mtgy : 0x400e39b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339bc Address@com_mtgy : 0x064339bc Address@app_mtgy : 0x400e39bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339c0 Address@com_mtgy : 0x064339c0 Address@app_mtgy : 0x400e39c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339c4 Address@com_mtgy : 0x064339c4 Address@app_mtgy : 0x400e39c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339c8 Address@com_mtgy : 0x064339c8 Address@app_mtgy : 0x400e39c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339cc Address@com_mtgy : 0x064339cc Address@app_mtgy : 0x400e39cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339d0 Address@com_mtgy : 0x064339d0 Address@app_mtgy : 0x400e39d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339d4 Address@com_mtgy : 0x064339d4 Address@app_mtgy : 0x400e39d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339d8 Address@com_mtgy : 0x064339d8 Address@app_mtgy : 0x400e39d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339dc Address@com_mtgy : 0x064339dc Address@app_mtgy : 0x400e39dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339e0 Address@com_mtgy : 0x064339e0 Address@app_mtgy : 0x400e39e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339e4 Address@com_mtgy : 0x064339e4 Address@app_mtgy : 0x400e39e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339e8 Address@com_mtgy : 0x064339e8 Address@app_mtgy : 0x400e39e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339ec Address@com_mtgy : 0x064339ec Address@app_mtgy : 0x400e39ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339f0 Address@com_mtgy : 0x064339f0 Address@app_mtgy : 0x400e39f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339f4 Address@com_mtgy : 0x064339f4 Address@app_mtgy : 0x400e39f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339f8 Address@com_mtgy : 0x064339f8 Address@app_mtgy : 0x400e39f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_a127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x064339fc Address@com_mtgy : 0x064339fc Address@app_mtgy : 0x400e39fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a00 Address@com_mtgy : 0x06433a00 Address@app_mtgy : 0x400e3a00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a04 Address@com_mtgy : 0x06433a04 Address@app_mtgy : 0x400e3a04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a08 Address@com_mtgy : 0x06433a08 Address@app_mtgy : 0x400e3a08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a0c Address@com_mtgy : 0x06433a0c Address@app_mtgy : 0x400e3a0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a10 Address@com_mtgy : 0x06433a10 Address@app_mtgy : 0x400e3a10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a14 Address@com_mtgy : 0x06433a14 Address@app_mtgy : 0x400e3a14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a18 Address@com_mtgy : 0x06433a18 Address@app_mtgy : 0x400e3a18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a1c Address@com_mtgy : 0x06433a1c Address@app_mtgy : 0x400e3a1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a20 Address@com_mtgy : 0x06433a20 Address@app_mtgy : 0x400e3a20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a24 Address@com_mtgy : 0x06433a24 Address@app_mtgy : 0x400e3a24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a28 Address@com_mtgy : 0x06433a28 Address@app_mtgy : 0x400e3a28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a2c Address@com_mtgy : 0x06433a2c Address@app_mtgy : 0x400e3a2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a30 Address@com_mtgy : 0x06433a30 Address@app_mtgy : 0x400e3a30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a34 Address@com_mtgy : 0x06433a34 Address@app_mtgy : 0x400e3a34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a38 Address@com_mtgy : 0x06433a38 Address@app_mtgy : 0x400e3a38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a3c Address@com_mtgy : 0x06433a3c Address@app_mtgy : 0x400e3a3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a40 Address@com_mtgy : 0x06433a40 Address@app_mtgy : 0x400e3a40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a44 Address@com_mtgy : 0x06433a44 Address@app_mtgy : 0x400e3a44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a48 Address@com_mtgy : 0x06433a48 Address@app_mtgy : 0x400e3a48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a4c Address@com_mtgy : 0x06433a4c Address@app_mtgy : 0x400e3a4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a50 Address@com_mtgy : 0x06433a50 Address@app_mtgy : 0x400e3a50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a54 Address@com_mtgy : 0x06433a54 Address@app_mtgy : 0x400e3a54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a58 Address@com_mtgy : 0x06433a58 Address@app_mtgy : 0x400e3a58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a5c Address@com_mtgy : 0x06433a5c Address@app_mtgy : 0x400e3a5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a60 Address@com_mtgy : 0x06433a60 Address@app_mtgy : 0x400e3a60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a64 Address@com_mtgy : 0x06433a64 Address@app_mtgy : 0x400e3a64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a68 Address@com_mtgy : 0x06433a68 Address@app_mtgy : 0x400e3a68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a6c Address@com_mtgy : 0x06433a6c Address@app_mtgy : 0x400e3a6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a70 Address@com_mtgy : 0x06433a70 Address@app_mtgy : 0x400e3a70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a74 Address@com_mtgy : 0x06433a74 Address@app_mtgy : 0x400e3a74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a78 Address@com_mtgy : 0x06433a78 Address@app_mtgy : 0x400e3a78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a7c Address@com_mtgy : 0x06433a7c Address@app_mtgy : 0x400e3a7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a80 Address@com_mtgy : 0x06433a80 Address@app_mtgy : 0x400e3a80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a84 Address@com_mtgy : 0x06433a84 Address@app_mtgy : 0x400e3a84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a88 Address@com_mtgy : 0x06433a88 Address@app_mtgy : 0x400e3a88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a8c Address@com_mtgy : 0x06433a8c Address@app_mtgy : 0x400e3a8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a90 Address@com_mtgy : 0x06433a90 Address@app_mtgy : 0x400e3a90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a94 Address@com_mtgy : 0x06433a94 Address@app_mtgy : 0x400e3a94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a98 Address@com_mtgy : 0x06433a98 Address@app_mtgy : 0x400e3a98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433a9c Address@com_mtgy : 0x06433a9c Address@app_mtgy : 0x400e3a9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433aa0 Address@com_mtgy : 0x06433aa0 Address@app_mtgy : 0x400e3aa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433aa4 Address@com_mtgy : 0x06433aa4 Address@app_mtgy : 0x400e3aa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433aa8 Address@com_mtgy : 0x06433aa8 Address@app_mtgy : 0x400e3aa8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433aac Address@com_mtgy : 0x06433aac Address@app_mtgy : 0x400e3aac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ab0 Address@com_mtgy : 0x06433ab0 Address@app_mtgy : 0x400e3ab0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ab4 Address@com_mtgy : 0x06433ab4 Address@app_mtgy : 0x400e3ab4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ab8 Address@com_mtgy : 0x06433ab8 Address@app_mtgy : 0x400e3ab8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433abc Address@com_mtgy : 0x06433abc Address@app_mtgy : 0x400e3abc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ac0 Address@com_mtgy : 0x06433ac0 Address@app_mtgy : 0x400e3ac0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ac4 Address@com_mtgy : 0x06433ac4 Address@app_mtgy : 0x400e3ac4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ac8 Address@com_mtgy : 0x06433ac8 Address@app_mtgy : 0x400e3ac8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433acc Address@com_mtgy : 0x06433acc Address@app_mtgy : 0x400e3acc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ad0 Address@com_mtgy : 0x06433ad0 Address@app_mtgy : 0x400e3ad0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ad4 Address@com_mtgy : 0x06433ad4 Address@app_mtgy : 0x400e3ad4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ad8 Address@com_mtgy : 0x06433ad8 Address@app_mtgy : 0x400e3ad8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433adc Address@com_mtgy : 0x06433adc Address@app_mtgy : 0x400e3adc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ae0 Address@com_mtgy : 0x06433ae0 Address@app_mtgy : 0x400e3ae0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ae4 Address@com_mtgy : 0x06433ae4 Address@app_mtgy : 0x400e3ae4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ae8 Address@com_mtgy : 0x06433ae8 Address@app_mtgy : 0x400e3ae8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433aec Address@com_mtgy : 0x06433aec Address@app_mtgy : 0x400e3aec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433af0 Address@com_mtgy : 0x06433af0 Address@app_mtgy : 0x400e3af0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433af4 Address@com_mtgy : 0x06433af4 Address@app_mtgy : 0x400e3af4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433af8 Address@com_mtgy : 0x06433af8 Address@app_mtgy : 0x400e3af8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433afc Address@com_mtgy : 0x06433afc Address@app_mtgy : 0x400e3afc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b00 Address@com_mtgy : 0x06433b00 Address@app_mtgy : 0x400e3b00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b04 Address@com_mtgy : 0x06433b04 Address@app_mtgy : 0x400e3b04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b08 Address@com_mtgy : 0x06433b08 Address@app_mtgy : 0x400e3b08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b0c Address@com_mtgy : 0x06433b0c Address@app_mtgy : 0x400e3b0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b10 Address@com_mtgy : 0x06433b10 Address@app_mtgy : 0x400e3b10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b14 Address@com_mtgy : 0x06433b14 Address@app_mtgy : 0x400e3b14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b18 Address@com_mtgy : 0x06433b18 Address@app_mtgy : 0x400e3b18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b1c Address@com_mtgy : 0x06433b1c Address@app_mtgy : 0x400e3b1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b20 Address@com_mtgy : 0x06433b20 Address@app_mtgy : 0x400e3b20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b24 Address@com_mtgy : 0x06433b24 Address@app_mtgy : 0x400e3b24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b28 Address@com_mtgy : 0x06433b28 Address@app_mtgy : 0x400e3b28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b2c Address@com_mtgy : 0x06433b2c Address@app_mtgy : 0x400e3b2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b30 Address@com_mtgy : 0x06433b30 Address@app_mtgy : 0x400e3b30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b34 Address@com_mtgy : 0x06433b34 Address@app_mtgy : 0x400e3b34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b38 Address@com_mtgy : 0x06433b38 Address@app_mtgy : 0x400e3b38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b3c Address@com_mtgy : 0x06433b3c Address@app_mtgy : 0x400e3b3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b40 Address@com_mtgy : 0x06433b40 Address@app_mtgy : 0x400e3b40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b44 Address@com_mtgy : 0x06433b44 Address@app_mtgy : 0x400e3b44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b48 Address@com_mtgy : 0x06433b48 Address@app_mtgy : 0x400e3b48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b4c Address@com_mtgy : 0x06433b4c Address@app_mtgy : 0x400e3b4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b50 Address@com_mtgy : 0x06433b50 Address@app_mtgy : 0x400e3b50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b54 Address@com_mtgy : 0x06433b54 Address@app_mtgy : 0x400e3b54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b58 Address@com_mtgy : 0x06433b58 Address@app_mtgy : 0x400e3b58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b5c Address@com_mtgy : 0x06433b5c Address@app_mtgy : 0x400e3b5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b60 Address@com_mtgy : 0x06433b60 Address@app_mtgy : 0x400e3b60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b64 Address@com_mtgy : 0x06433b64 Address@app_mtgy : 0x400e3b64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b68 Address@com_mtgy : 0x06433b68 Address@app_mtgy : 0x400e3b68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b6c Address@com_mtgy : 0x06433b6c Address@app_mtgy : 0x400e3b6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b70 Address@com_mtgy : 0x06433b70 Address@app_mtgy : 0x400e3b70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b74 Address@com_mtgy : 0x06433b74 Address@app_mtgy : 0x400e3b74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b78 Address@com_mtgy : 0x06433b78 Address@app_mtgy : 0x400e3b78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b7c Address@com_mtgy : 0x06433b7c Address@app_mtgy : 0x400e3b7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b80 Address@com_mtgy : 0x06433b80 Address@app_mtgy : 0x400e3b80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b84 Address@com_mtgy : 0x06433b84 Address@app_mtgy : 0x400e3b84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b88 Address@com_mtgy : 0x06433b88 Address@app_mtgy : 0x400e3b88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b8c Address@com_mtgy : 0x06433b8c Address@app_mtgy : 0x400e3b8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b90 Address@com_mtgy : 0x06433b90 Address@app_mtgy : 0x400e3b90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b94 Address@com_mtgy : 0x06433b94 Address@app_mtgy : 0x400e3b94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b98 Address@com_mtgy : 0x06433b98 Address@app_mtgy : 0x400e3b98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433b9c Address@com_mtgy : 0x06433b9c Address@app_mtgy : 0x400e3b9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ba0 Address@com_mtgy : 0x06433ba0 Address@app_mtgy : 0x400e3ba0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ba4 Address@com_mtgy : 0x06433ba4 Address@app_mtgy : 0x400e3ba4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ba8 Address@com_mtgy : 0x06433ba8 Address@app_mtgy : 0x400e3ba8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bac Address@com_mtgy : 0x06433bac Address@app_mtgy : 0x400e3bac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bb0 Address@com_mtgy : 0x06433bb0 Address@app_mtgy : 0x400e3bb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bb4 Address@com_mtgy : 0x06433bb4 Address@app_mtgy : 0x400e3bb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bb8 Address@com_mtgy : 0x06433bb8 Address@app_mtgy : 0x400e3bb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bbc Address@com_mtgy : 0x06433bbc Address@app_mtgy : 0x400e3bbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bc0 Address@com_mtgy : 0x06433bc0 Address@app_mtgy : 0x400e3bc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bc4 Address@com_mtgy : 0x06433bc4 Address@app_mtgy : 0x400e3bc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bc8 Address@com_mtgy : 0x06433bc8 Address@app_mtgy : 0x400e3bc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bcc Address@com_mtgy : 0x06433bcc Address@app_mtgy : 0x400e3bcc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bd0 Address@com_mtgy : 0x06433bd0 Address@app_mtgy : 0x400e3bd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bd4 Address@com_mtgy : 0x06433bd4 Address@app_mtgy : 0x400e3bd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bd8 Address@com_mtgy : 0x06433bd8 Address@app_mtgy : 0x400e3bd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bdc Address@com_mtgy : 0x06433bdc Address@app_mtgy : 0x400e3bdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433be0 Address@com_mtgy : 0x06433be0 Address@app_mtgy : 0x400e3be0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433be4 Address@com_mtgy : 0x06433be4 Address@app_mtgy : 0x400e3be4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433be8 Address@com_mtgy : 0x06433be8 Address@app_mtgy : 0x400e3be8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bec Address@com_mtgy : 0x06433bec Address@app_mtgy : 0x400e3bec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bf0 Address@com_mtgy : 0x06433bf0 Address@app_mtgy : 0x400e3bf0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bf4 Address@com_mtgy : 0x06433bf4 Address@app_mtgy : 0x400e3bf4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bf8 Address@com_mtgy : 0x06433bf8 Address@app_mtgy : 0x400e3bf8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_e127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433bfc Address@com_mtgy : 0x06433bfc Address@app_mtgy : 0x400e3bfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x0 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c00 Address@com_mtgy : 0x06433c00 Address@app_mtgy : 0x400e3c00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x1 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c04 Address@com_mtgy : 0x06433c04 Address@app_mtgy : 0x400e3c04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x2 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c08 Address@com_mtgy : 0x06433c08 Address@app_mtgy : 0x400e3c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x3 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c0c Address@com_mtgy : 0x06433c0c Address@app_mtgy : 0x400e3c0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x4 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c10 Address@com_mtgy : 0x06433c10 Address@app_mtgy : 0x400e3c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x5 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c14 Address@com_mtgy : 0x06433c14 Address@app_mtgy : 0x400e3c14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x6 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c18 Address@com_mtgy : 0x06433c18 Address@app_mtgy : 0x400e3c18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x7 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c1c Address@com_mtgy : 0x06433c1c Address@app_mtgy : 0x400e3c1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x8 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c20 Address@com_mtgy : 0x06433c20 Address@app_mtgy : 0x400e3c20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x9 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c24 Address@com_mtgy : 0x06433c24 Address@app_mtgy : 0x400e3c24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x10 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c28 Address@com_mtgy : 0x06433c28 Address@app_mtgy : 0x400e3c28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x11 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c2c Address@com_mtgy : 0x06433c2c Address@app_mtgy : 0x400e3c2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x12 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c30 Address@com_mtgy : 0x06433c30 Address@app_mtgy : 0x400e3c30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x13 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c34 Address@com_mtgy : 0x06433c34 Address@app_mtgy : 0x400e3c34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x14 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c38 Address@com_mtgy : 0x06433c38 Address@app_mtgy : 0x400e3c38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x15 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c3c Address@com_mtgy : 0x06433c3c Address@app_mtgy : 0x400e3c3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x16 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c40 Address@com_mtgy : 0x06433c40 Address@app_mtgy : 0x400e3c40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x17 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c44 Address@com_mtgy : 0x06433c44 Address@app_mtgy : 0x400e3c44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x18 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c48 Address@com_mtgy : 0x06433c48 Address@app_mtgy : 0x400e3c48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x19 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c4c Address@com_mtgy : 0x06433c4c Address@app_mtgy : 0x400e3c4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x20 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c50 Address@com_mtgy : 0x06433c50 Address@app_mtgy : 0x400e3c50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x21 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c54 Address@com_mtgy : 0x06433c54 Address@app_mtgy : 0x400e3c54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x22 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c58 Address@com_mtgy : 0x06433c58 Address@app_mtgy : 0x400e3c58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x23 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c5c Address@com_mtgy : 0x06433c5c Address@app_mtgy : 0x400e3c5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x24 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c60 Address@com_mtgy : 0x06433c60 Address@app_mtgy : 0x400e3c60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x25 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c64 Address@com_mtgy : 0x06433c64 Address@app_mtgy : 0x400e3c64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x26 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c68 Address@com_mtgy : 0x06433c68 Address@app_mtgy : 0x400e3c68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x27 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c6c Address@com_mtgy : 0x06433c6c Address@app_mtgy : 0x400e3c6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x28 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c70 Address@com_mtgy : 0x06433c70 Address@app_mtgy : 0x400e3c70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x29 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c74 Address@com_mtgy : 0x06433c74 Address@app_mtgy : 0x400e3c74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x30 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c78 Address@com_mtgy : 0x06433c78 Address@app_mtgy : 0x400e3c78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x31 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c7c Address@com_mtgy : 0x06433c7c Address@app_mtgy : 0x400e3c7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x32 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c80 Address@com_mtgy : 0x06433c80 Address@app_mtgy : 0x400e3c80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x33 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c84 Address@com_mtgy : 0x06433c84 Address@app_mtgy : 0x400e3c84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x34 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c88 Address@com_mtgy : 0x06433c88 Address@app_mtgy : 0x400e3c88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x35 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c8c Address@com_mtgy : 0x06433c8c Address@app_mtgy : 0x400e3c8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x36 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c90 Address@com_mtgy : 0x06433c90 Address@app_mtgy : 0x400e3c90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x37 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c94 Address@com_mtgy : 0x06433c94 Address@app_mtgy : 0x400e3c94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x38 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c98 Address@com_mtgy : 0x06433c98 Address@app_mtgy : 0x400e3c98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x39 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433c9c Address@com_mtgy : 0x06433c9c Address@app_mtgy : 0x400e3c9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x40 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ca0 Address@com_mtgy : 0x06433ca0 Address@app_mtgy : 0x400e3ca0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x41 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ca4 Address@com_mtgy : 0x06433ca4 Address@app_mtgy : 0x400e3ca4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x42 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ca8 Address@com_mtgy : 0x06433ca8 Address@app_mtgy : 0x400e3ca8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x43 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cac Address@com_mtgy : 0x06433cac Address@app_mtgy : 0x400e3cac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x44 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cb0 Address@com_mtgy : 0x06433cb0 Address@app_mtgy : 0x400e3cb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x45 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cb4 Address@com_mtgy : 0x06433cb4 Address@app_mtgy : 0x400e3cb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x46 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cb8 Address@com_mtgy : 0x06433cb8 Address@app_mtgy : 0x400e3cb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x47 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cbc Address@com_mtgy : 0x06433cbc Address@app_mtgy : 0x400e3cbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x48 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cc0 Address@com_mtgy : 0x06433cc0 Address@app_mtgy : 0x400e3cc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x49 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cc4 Address@com_mtgy : 0x06433cc4 Address@app_mtgy : 0x400e3cc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x50 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cc8 Address@com_mtgy : 0x06433cc8 Address@app_mtgy : 0x400e3cc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x51 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ccc Address@com_mtgy : 0x06433ccc Address@app_mtgy : 0x400e3ccc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x52 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cd0 Address@com_mtgy : 0x06433cd0 Address@app_mtgy : 0x400e3cd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x53 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cd4 Address@com_mtgy : 0x06433cd4 Address@app_mtgy : 0x400e3cd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x54 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cd8 Address@com_mtgy : 0x06433cd8 Address@app_mtgy : 0x400e3cd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x55 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cdc Address@com_mtgy : 0x06433cdc Address@app_mtgy : 0x400e3cdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x56 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ce0 Address@com_mtgy : 0x06433ce0 Address@app_mtgy : 0x400e3ce0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x57 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ce4 Address@com_mtgy : 0x06433ce4 Address@app_mtgy : 0x400e3ce4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x58 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ce8 Address@com_mtgy : 0x06433ce8 Address@app_mtgy : 0x400e3ce8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x59 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cec Address@com_mtgy : 0x06433cec Address@app_mtgy : 0x400e3cec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x60 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cf0 Address@com_mtgy : 0x06433cf0 Address@app_mtgy : 0x400e3cf0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x61 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cf4 Address@com_mtgy : 0x06433cf4 Address@app_mtgy : 0x400e3cf4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x62 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cf8 Address@com_mtgy : 0x06433cf8 Address@app_mtgy : 0x400e3cf8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x63 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433cfc Address@com_mtgy : 0x06433cfc Address@app_mtgy : 0x400e3cfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x64 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d00 Address@com_mtgy : 0x06433d00 Address@app_mtgy : 0x400e3d00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x65 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d04 Address@com_mtgy : 0x06433d04 Address@app_mtgy : 0x400e3d04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x66 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d08 Address@com_mtgy : 0x06433d08 Address@app_mtgy : 0x400e3d08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x67 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d0c Address@com_mtgy : 0x06433d0c Address@app_mtgy : 0x400e3d0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x68 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d10 Address@com_mtgy : 0x06433d10 Address@app_mtgy : 0x400e3d10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x69 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d14 Address@com_mtgy : 0x06433d14 Address@app_mtgy : 0x400e3d14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x70 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d18 Address@com_mtgy : 0x06433d18 Address@app_mtgy : 0x400e3d18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x71 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d1c Address@com_mtgy : 0x06433d1c Address@app_mtgy : 0x400e3d1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x72 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d20 Address@com_mtgy : 0x06433d20 Address@app_mtgy : 0x400e3d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x73 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d24 Address@com_mtgy : 0x06433d24 Address@app_mtgy : 0x400e3d24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x74 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d28 Address@com_mtgy : 0x06433d28 Address@app_mtgy : 0x400e3d28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x75 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d2c Address@com_mtgy : 0x06433d2c Address@app_mtgy : 0x400e3d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x76 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d30 Address@com_mtgy : 0x06433d30 Address@app_mtgy : 0x400e3d30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x77 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d34 Address@com_mtgy : 0x06433d34 Address@app_mtgy : 0x400e3d34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x78 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d38 Address@com_mtgy : 0x06433d38 Address@app_mtgy : 0x400e3d38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x79 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d3c Address@com_mtgy : 0x06433d3c Address@app_mtgy : 0x400e3d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x80 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d40 Address@com_mtgy : 0x06433d40 Address@app_mtgy : 0x400e3d40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x81 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d44 Address@com_mtgy : 0x06433d44 Address@app_mtgy : 0x400e3d44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x82 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d48 Address@com_mtgy : 0x06433d48 Address@app_mtgy : 0x400e3d48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x83 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d4c Address@com_mtgy : 0x06433d4c Address@app_mtgy : 0x400e3d4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x84 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d50 Address@com_mtgy : 0x06433d50 Address@app_mtgy : 0x400e3d50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x85 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d54 Address@com_mtgy : 0x06433d54 Address@app_mtgy : 0x400e3d54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x86 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d58 Address@com_mtgy : 0x06433d58 Address@app_mtgy : 0x400e3d58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x87 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d5c Address@com_mtgy : 0x06433d5c Address@app_mtgy : 0x400e3d5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x88 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d60 Address@com_mtgy : 0x06433d60 Address@app_mtgy : 0x400e3d60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x89 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d64 Address@com_mtgy : 0x06433d64 Address@app_mtgy : 0x400e3d64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x90 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d68 Address@com_mtgy : 0x06433d68 Address@app_mtgy : 0x400e3d68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x91 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d6c Address@com_mtgy : 0x06433d6c Address@app_mtgy : 0x400e3d6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x92 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d70 Address@com_mtgy : 0x06433d70 Address@app_mtgy : 0x400e3d70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x93 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d74 Address@com_mtgy : 0x06433d74 Address@app_mtgy : 0x400e3d74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x94 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d78 Address@com_mtgy : 0x06433d78 Address@app_mtgy : 0x400e3d78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x95 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d7c Address@com_mtgy : 0x06433d7c Address@app_mtgy : 0x400e3d7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x96 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d80 Address@com_mtgy : 0x06433d80 Address@app_mtgy : 0x400e3d80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x97 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d84 Address@com_mtgy : 0x06433d84 Address@app_mtgy : 0x400e3d84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x98 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d88 Address@com_mtgy : 0x06433d88 Address@app_mtgy : 0x400e3d88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x99 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d8c Address@com_mtgy : 0x06433d8c Address@app_mtgy : 0x400e3d8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x100 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d90 Address@com_mtgy : 0x06433d90 Address@app_mtgy : 0x400e3d90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x101 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d94 Address@com_mtgy : 0x06433d94 Address@app_mtgy : 0x400e3d94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x102 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d98 Address@com_mtgy : 0x06433d98 Address@app_mtgy : 0x400e3d98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x103 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433d9c Address@com_mtgy : 0x06433d9c Address@app_mtgy : 0x400e3d9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x104 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433da0 Address@com_mtgy : 0x06433da0 Address@app_mtgy : 0x400e3da0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x105 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433da4 Address@com_mtgy : 0x06433da4 Address@app_mtgy : 0x400e3da4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x106 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433da8 Address@com_mtgy : 0x06433da8 Address@app_mtgy : 0x400e3da8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x107 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dac Address@com_mtgy : 0x06433dac Address@app_mtgy : 0x400e3dac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x108 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433db0 Address@com_mtgy : 0x06433db0 Address@app_mtgy : 0x400e3db0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x109 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433db4 Address@com_mtgy : 0x06433db4 Address@app_mtgy : 0x400e3db4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x110 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433db8 Address@com_mtgy : 0x06433db8 Address@app_mtgy : 0x400e3db8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x111 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dbc Address@com_mtgy : 0x06433dbc Address@app_mtgy : 0x400e3dbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x112 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dc0 Address@com_mtgy : 0x06433dc0 Address@app_mtgy : 0x400e3dc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x113 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dc4 Address@com_mtgy : 0x06433dc4 Address@app_mtgy : 0x400e3dc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x114 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dc8 Address@com_mtgy : 0x06433dc8 Address@app_mtgy : 0x400e3dc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x115 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dcc Address@com_mtgy : 0x06433dcc Address@app_mtgy : 0x400e3dcc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x116 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dd0 Address@com_mtgy : 0x06433dd0 Address@app_mtgy : 0x400e3dd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x117 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dd4 Address@com_mtgy : 0x06433dd4 Address@app_mtgy : 0x400e3dd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x118 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dd8 Address@com_mtgy : 0x06433dd8 Address@app_mtgy : 0x400e3dd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x119 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433ddc Address@com_mtgy : 0x06433ddc Address@app_mtgy : 0x400e3ddc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x120 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433de0 Address@com_mtgy : 0x06433de0 Address@app_mtgy : 0x400e3de0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x121 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433de4 Address@com_mtgy : 0x06433de4 Address@app_mtgy : 0x400e3de4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x122 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433de8 Address@com_mtgy : 0x06433de8 Address@app_mtgy : 0x400e3de8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x123 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dec Address@com_mtgy : 0x06433dec Address@app_mtgy : 0x400e3dec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x124 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433df0 Address@com_mtgy : 0x06433df0 Address@app_mtgy : 0x400e3df0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x125 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433df4 Address@com_mtgy : 0x06433df4 Address@app_mtgy : 0x400e3df4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x126 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433df8 Address@com_mtgy : 0x06433df8 Address@app_mtgy : 0x400e3df8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| mtgy_op_x127 |
|
|||
| R/W |
0x00000000 |
Address@mtgy : 0x06433dfc Address@com_mtgy : 0x06433dfc Address@app_mtgy : 0x400e3dfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | - | gpec_dram_start |
| 1-7fe | 4-1ff8 | - | reserved |
| 7ff | 1ffc | - | gpec_dram_end |
| gpec_dram_start | |||
|
Address@gxc_gpec_dram : 0x07c00000 Address@gxc_gpec00_dram : 0x07d00000 Address@gxc_gpec01_dram : 0x07d04000 Address@gxc_gpec02_dram : 0x07d08000 Address@gxc_gpec03_dram : 0x07d0c000 Address@gxc_gpec04_dram : 0x07d10000 Address@gxc_gpec05_dram : 0x07d14000 Address@gxc_gpec06_dram : 0x07d18000 Address@gxc_gpec07_dram : 0x07d1c000 Address@gxc_gpec10_dram : 0x07d40000 Address@gxc_gpec11_dram : 0x07d44000 Address@gxc_gpec12_dram : 0x07d48000 Address@gxc_gpec13_dram : 0x07d4c000 Address@gxc_gpec14_dram : 0x07d50000 Address@gxc_gpec15_dram : 0x07d54000 Address@gxc_gpec16_dram : 0x07d58000 Address@gxc_gpec17_dram : 0x07d5c000 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gpec_dram_start | ||
| gpec_dram_end | |||
|
Address@gxc_gpec_dram : 0x07c01ffc Address@gxc_gpec00_dram : 0x07d01ffc Address@gxc_gpec01_dram : 0x07d05ffc Address@gxc_gpec02_dram : 0x07d09ffc Address@gxc_gpec03_dram : 0x07d0dffc Address@gxc_gpec04_dram : 0x07d11ffc Address@gxc_gpec05_dram : 0x07d15ffc Address@gxc_gpec06_dram : 0x07d19ffc Address@gxc_gpec07_dram : 0x07d1dffc Address@gxc_gpec10_dram : 0x07d41ffc Address@gxc_gpec11_dram : 0x07d45ffc Address@gxc_gpec12_dram : 0x07d49ffc Address@gxc_gpec13_dram : 0x07d4dffc Address@gxc_gpec14_dram : 0x07d51ffc Address@gxc_gpec15_dram : 0x07d55ffc Address@gxc_gpec16_dram : 0x07d59ffc Address@gxc_gpec17_dram : 0x07d5dffc |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gpec_dram_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | - | gmac_ram_start |
| 1-17e | 4-5f8 | - | reserved |
| 17f | 5fc | - | gmac_ram_end |
| 180-1ff | 600-7fc | - | reserved |
| gmac_ram_start |
|
|||
|
Address@gxc_grpu_ram : 0x07c00000 Address@gxc_gtpu_ram : 0x07c00800 Address@gxc_grpu0_ram : 0x07d20000 Address@gxc_gtpu0_ram : 0x07d20800 Address@gxc_grpu1_ram : 0x07d60000 Address@gxc_gtpu1_ram : 0x07d60800 |
Bits | Name | Description | |
|---|---|---|---|---|
| 31 - 0 | gmac_ram_start | |||
| gmac_ram_end |
|
|||
|
Address@gxc_grpu_ram : 0x07c005fc Address@gxc_gtpu_ram : 0x07c00dfc Address@gxc_grpu0_ram : 0x07d205fc Address@gxc_gtpu0_ram : 0x07d20dfc Address@gxc_grpu1_ram : 0x07d605fc Address@gxc_gtpu1_ram : 0x07d60dfc |
Bits | Name | Description | |
|---|---|---|---|---|
| 31 - 0 | gmac_ram_end | |||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | tbi_cr0 |
| 1 | 4 | R/W | tbi_bucket0_cfg |
| 2 | 8 | R/W | tbi_bucket0_lvl |
| 3 | c | R/W | tbi_bucket1_cfg |
| 4 | 10 | R/W | tbi_bucket1_lvl |
| 5 | 14 | R/W | tbi_bucket2_cfg |
| 6 | 18 | R/W | tbi_bucket2_lvl |
| 7 | 1c | R/W | tbi_bucket3_cfg |
| 8 | 20 | R/W | tbi_bucket3_lvl |
| 9 | 24 | R/W | tbi_bucket4_cfg |
| a | 28 | R/W | tbi_bucket4_lvl |
| b | 2c | R/W | tbi_bucket5_cfg |
| c | 30 | R/W | tbi_bucket5_lvl |
| d | 34 | R/W | tbi_bucket6_cfg |
| e | 38 | R/W | tbi_bucket6_lvl |
| f | 3c | R/W | tbi_bucket7_cfg |
| 10 | 40 | R/W | tbi_bucket7_lvl |
| 11-1f | 44-7c | - | reserved |
| tbi_cr0 |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00000 Address@gxc_token_bucket_instance1 : 0x07c00080 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||
| 5 - 4 | "00" |
tbi_update_rate |
|
|||||||||
| 3 - 1 | 0 |
- |
reserved | |||||||||
| 0 | "0" |
tbi_en |
|
|||||||||
| tbi_bucket0_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00004 Address@gxc_token_bucket_instance1 : 0x07c00084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket0_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00008 Address@gxc_token_bucket_instance1 : 0x07c00088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket1_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c0000c Address@gxc_token_bucket_instance1 : 0x07c0008c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket1_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00010 Address@gxc_token_bucket_instance1 : 0x07c00090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket2_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00014 Address@gxc_token_bucket_instance1 : 0x07c00094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket2_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00018 Address@gxc_token_bucket_instance1 : 0x07c00098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket3_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c0001c Address@gxc_token_bucket_instance1 : 0x07c0009c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket3_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00020 Address@gxc_token_bucket_instance1 : 0x07c000a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket4_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00024 Address@gxc_token_bucket_instance1 : 0x07c000a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket4_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00028 Address@gxc_token_bucket_instance1 : 0x07c000a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket5_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c0002c Address@gxc_token_bucket_instance1 : 0x07c000ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket5_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00030 Address@gxc_token_bucket_instance1 : 0x07c000b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket6_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00034 Address@gxc_token_bucket_instance1 : 0x07c000b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket6_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00038 Address@gxc_token_bucket_instance1 : 0x07c000b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| tbi_bucket7_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c0003c Address@gxc_token_bucket_instance1 : 0x07c000bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 16 | 0x0 |
size |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 4 | 0x0 |
inc |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
share |
|
|
| 1 | "0" |
cbs_en |
|
|
| 0 | "0" |
en |
|
|
| tbi_bucket7_lvl |
|
|||
| R/W |
0x00000000 |
Address@gxc_token_bucket_instance0 : 0x07c00040 Address@gxc_token_bucket_instance1 : 0x07c000c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 0 | 0x0 |
level |
|
|
| gmac_sr0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01000 Address@gxc_gmac0_regs : 0x07d21000 Address@gxc_gmac1_regs : 0x07d61000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr0 |
|
|
| gmac_sr1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01004 Address@gxc_gmac0_regs : 0x07d21004 Address@gxc_gmac1_regs : 0x07d61004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr1 |
|
|
| gmac_sr2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01008 Address@gxc_gmac0_regs : 0x07d21008 Address@gxc_gmac1_regs : 0x07d61008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr2 |
|
|
| gmac_sr3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0100c Address@gxc_gmac0_regs : 0x07d2100c Address@gxc_gmac1_regs : 0x07d6100c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr3 |
|
|
| gmac_sr4 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01010 Address@gxc_gmac0_regs : 0x07d21010 Address@gxc_gmac1_regs : 0x07d61010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr4 |
|
|
| gmac_sr5 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01014 Address@gxc_gmac0_regs : 0x07d21014 Address@gxc_gmac1_regs : 0x07d61014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr5 |
|
|
| gmac_sr6 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01018 Address@gxc_gmac0_regs : 0x07d21018 Address@gxc_gmac1_regs : 0x07d61018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr6 |
|
|
| gmac_sr7 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0101c Address@gxc_gmac0_regs : 0x07d2101c Address@gxc_gmac1_regs : 0x07d6101c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr7 |
|
|
| gmac_sr8 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01020 Address@gxc_gmac0_regs : 0x07d21020 Address@gxc_gmac1_regs : 0x07d61020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr8 |
|
|
| gmac_sr9 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01024 Address@gxc_gmac0_regs : 0x07d21024 Address@gxc_gmac1_regs : 0x07d61024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr9 |
|
|
| gmac_sr10 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01028 Address@gxc_gmac0_regs : 0x07d21028 Address@gxc_gmac1_regs : 0x07d61028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr10 |
|
|
| gmac_sr11 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0102c Address@gxc_gmac0_regs : 0x07d2102c Address@gxc_gmac1_regs : 0x07d6102c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr11 |
|
|
| gmac_sr12 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01030 Address@gxc_gmac0_regs : 0x07d21030 Address@gxc_gmac1_regs : 0x07d61030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr12 |
|
|
| gmac_sr13 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01034 Address@gxc_gmac0_regs : 0x07d21034 Address@gxc_gmac1_regs : 0x07d61034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr13 |
|
|
| gmac_sr14 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01038 Address@gxc_gmac0_regs : 0x07d21038 Address@gxc_gmac1_regs : 0x07d61038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr14 |
|
|
| gmac_sr15 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0103c Address@gxc_gmac0_regs : 0x07d2103c Address@gxc_gmac1_regs : 0x07d6103c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sr15 |
|
|
| gmac_wr0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01040 Address@gxc_gmac0_regs : 0x07d21040 Address@gxc_gmac1_regs : 0x07d61040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr0 |
|
|
| gmac_wr1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01044 Address@gxc_gmac0_regs : 0x07d21044 Address@gxc_gmac1_regs : 0x07d61044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr1 |
|
|
| gmac_wr2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01048 Address@gxc_gmac0_regs : 0x07d21048 Address@gxc_gmac1_regs : 0x07d61048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr2 |
|
|
| gmac_wr3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0104c Address@gxc_gmac0_regs : 0x07d2104c Address@gxc_gmac1_regs : 0x07d6104c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr3 |
|
|
| gmac_wr4 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01050 Address@gxc_gmac0_regs : 0x07d21050 Address@gxc_gmac1_regs : 0x07d61050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr4 |
|
|
| gmac_wr5 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01054 Address@gxc_gmac0_regs : 0x07d21054 Address@gxc_gmac1_regs : 0x07d61054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr5 |
|
|
| gmac_wr6 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01058 Address@gxc_gmac0_regs : 0x07d21058 Address@gxc_gmac1_regs : 0x07d61058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr6 |
|
|
| gmac_wr7 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0105c Address@gxc_gmac0_regs : 0x07d2105c Address@gxc_gmac1_regs : 0x07d6105c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr7 |
|
|
| gmac_wr8 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01060 Address@gxc_gmac0_regs : 0x07d21060 Address@gxc_gmac1_regs : 0x07d61060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr8 |
|
|
| gmac_wr9 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01064 Address@gxc_gmac0_regs : 0x07d21064 Address@gxc_gmac1_regs : 0x07d61064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
wr9 |
|
|
| gmac_statcfg0 |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01068 Address@gxc_gmac0_regs : 0x07d21068 Address@gxc_gmac1_regs : 0x07d61068 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||||
| 30 | "0" |
lmo_link_and_n_eld_bad_link |
|
|||||||||
| 29 | "0" |
dr_err_or_crx_err_or_fcr_err |
|
|||||||||
| 28 | "0" |
hdx1000 |
|
|||||||||
| 27 | "0" |
link_mode_out_duplex |
|
|||||||||
| 26 | "0" |
link_mode_out_link |
|
|||||||||
| 25 - 24 | "00" |
link_mode_out_speed |
|
|||||||||
| 23 | "0" |
utxe_empty |
|
|||||||||
| 22 | "0" |
utxe_nxt |
|
|||||||||
| 21 | "0" |
urxe_bit32 |
|
|||||||||
| 20 | "0" |
urxe_rdy |
|
|||||||||
| 19 | "0" |
utx_empty |
|
|||||||||
| 18 | "0" |
utx_nxt |
|
|||||||||
| 17 | "0" |
urx_bit32 |
|
|||||||||
| 16 | "0" |
urx_rdy |
|
|||||||||
| 15 | 0 |
- |
reserved | |||||||||
| 14 | "0" |
eld_bad_link |
|
|||||||||
| 13 | "0" |
utxe_ufl |
|
|||||||||
| 12 | "0" |
urxe_ovf |
|
|||||||||
| 11 | "0" |
utx_ufl |
|
|||||||||
| 10 | "0" |
urx_ovf |
|
|||||||||
| 9 - 8 | 0 |
- |
reserved | |||||||||
| 7 | "0" |
gpio3_oe |
|
|||||||||
| 6 | "0" |
gpio2_oe |
|
|||||||||
| 5 | "0" |
gpio1_oe |
|
|||||||||
| 4 | "0" |
gpio0_oe |
|
|||||||||
| 3 | "0" |
gpio3 |
|
|||||||||
| 2 | "0" |
gpio2 |
|
|||||||||
| 1 | "0" |
gpio1 |
|
|||||||||
| 0 | "0" |
gpio0 |
|
|||||||||
| gmac_statcfg1 |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0106c Address@gxc_gmac0_regs : 0x07d2106c Address@gxc_gmac1_regs : 0x07d6106c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||||
| 30 | "0" |
lmo_link_and_n_eld_bad_link |
|
|||||||||
| 29 | "0" |
dr_err_or_crx_err_or_fcr_err |
|
|||||||||
| 28 | "0" |
hdx1000 |
|
|||||||||
| 27 | "0" |
link_mode_out_duplex |
|
|||||||||
| 26 | "0" |
link_mode_out_link |
|
|||||||||
| 25 - 24 | "00" |
link_mode_out_speed |
|
|||||||||
| 23 | "0" |
utxe_empty |
|
|||||||||
| 22 | "0" |
utxe_nxt |
|
|||||||||
| 21 | "0" |
urxe_bit32 |
|
|||||||||
| 20 | "0" |
urxe_rdy |
|
|||||||||
| 19 | "0" |
utx_empty |
|
|||||||||
| 18 | "0" |
utx_nxt |
|
|||||||||
| 17 | "0" |
urx_bit32 |
|
|||||||||
| 16 | "0" |
urx_rdy |
|
|||||||||
| 15 | 0 |
- |
reserved | |||||||||
| 14 | "0" |
eld_bad_link |
|
|||||||||
| 13 | "0" |
utxe_ufl |
|
|||||||||
| 12 | "0" |
urxe_ovf |
|
|||||||||
| 11 | "0" |
utx_ufl |
|
|||||||||
| 10 | "0" |
urx_ovf |
|
|||||||||
| 9 - 8 | 0 |
- |
reserved | |||||||||
| 7 | "0" |
gpio3_oe |
|
|||||||||
| 6 | "0" |
gpio2_oe |
|
|||||||||
| 5 | "0" |
gpio1_oe |
|
|||||||||
| 4 | "0" |
gpio0_oe |
|
|||||||||
| 3 | "0" |
gpio3 |
|
|||||||||
| 2 | "0" |
gpio2 |
|
|||||||||
| 1 | "0" |
gpio1 |
|
|||||||||
| 0 | "0" |
gpio0 |
|
|||||||||
| gmac_stat_bits |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01070 Address@gxc_gmac0_regs : 0x07d21070 Address@gxc_gmac1_regs : 0x07d61070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
write_mask |
|
|
| 15 - 0 | 0x0 |
val |
|
|
| gmac_cmp0_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01074 Address@gxc_gmac0_regs : 0x07d21074 Address@gxc_gmac1_regs : 0x07d61074 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | cnt2_tpu_z |
|
||
| 30 | cnt1_tpu_z |
|
||
| 29 | cnt2_rpu_z |
|
||
| 28 | cnt1_rpu_z |
|
||
| 27 | cnt_tx_z |
|
||
| 26 | cnt_rx_z |
|
||
| 25 | wr9_z |
|
||
| 24 | wr8_z |
|
||
| 23 | wr7_z |
|
||
| 22 | wr6_z |
|
||
| 21 | wr5_z |
|
||
| 20 | wr4_z |
|
||
| 19 | wr3_z |
|
||
| 18 | wr2_z |
|
||
| 17 | wr1_z |
|
||
| 16 | wr0_z |
|
||
| 15 | sr15_z |
|
||
| 14 | sr14_z |
|
||
| 13 | sr13_z |
|
||
| 12 | sr12_z |
|
||
| 11 | sr11_z |
|
||
| 10 | sr10_z |
|
||
| 9 | sr9_z |
|
||
| 8 | sr8_z |
|
||
| 7 | sr7_z |
|
||
| 6 | sr6_z |
|
||
| 5 | sr5_z |
|
||
| 4 | sr4_z |
|
||
| 3 | sr3_z |
|
||
| 2 | sr2_z |
|
||
| 1 | sr1_z |
|
||
| 0 | sr0_z |
|
||
| gmac_cmp1_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01078 Address@gxc_gmac0_regs : 0x07d21078 Address@gxc_gmac1_regs : 0x07d61078 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 28 | - |
reserved | ||
| 27 | counter32 |
|
||
| 26 | systime32 |
|
||
| 25 | counter64 |
|
||
| 24 | systime64 |
|
||
| 23 | txcnt_wr5_b3 |
|
||
| 22 | txcnt_wr5_b2 |
|
||
| 21 | txcnt_wr5_b1 |
|
||
| 20 | txcnt_wr5_b0 |
|
||
| 19 | txcnt_wr4_b3 |
|
||
| 18 | txcnt_wr4_b2 |
|
||
| 17 | txcnt_wr4_b1 |
|
||
| 16 | txcnt_wr4_b0 |
|
||
| 15 | rxcnt_wr1_b3 |
|
||
| 14 | rxcnt_wr1_b2 |
|
||
| 13 | rxcnt_wr1_b1 |
|
||
| 12 | rxcnt_wr1_b0 |
|
||
| 11 | rxcnt_wr0_b3 |
|
||
| 10 | rxcnt_wr0_b2 |
|
||
| 9 | rxcnt_wr0_b1 |
|
||
| 8 | rxcnt_wr0_b0 |
|
||
| 7 | txcnt_wr7 |
|
||
| 6 | txcnt_wr6 |
|
||
| 5 | txcnt_wr5 |
|
||
| 4 | txcnt_wr4 |
|
||
| 3 | rxcnt_wr3 |
|
||
| 2 | rxcnt_wr2 |
|
||
| 1 | rxcnt_wr1 |
|
||
| 0 | rxcnt_wr0 |
|
||
| gmac_cmp2_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c0107c Address@gxc_gmac0_regs : 0x07d2107c Address@gxc_gmac1_regs : 0x07d6107c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||
| 21 | wr6_se_wr7 |
|
||
| 20 | wr4_se_wr5 |
|
||
| 19 | wr2_se_wr3 |
|
||
| 18 | wr0_se_wr1 |
|
||
| 17 | rpm2_hit2or3 |
|
||
| 16 | rpm2_hit0or1 |
|
||
| 15 | rpm2_hit3 |
|
||
| 14 | rpm2_hit2 |
|
||
| 13 | rpm2_hit1 |
|
||
| 12 | rpm2_hit0 |
|
||
| 11 | tpm_hit2or3 |
|
||
| 10 | tpm_hit0or1 |
|
||
| 9 | rpm_hit2or3 |
|
||
| 8 | rpm_hit0or1 |
|
||
| 7 | tpm_hit3 |
|
||
| 6 | tpm_hit2 |
|
||
| 5 | tpm_hit1 |
|
||
| 4 | tpm_hit0 |
|
||
| 3 | rpm_hit3 |
|
||
| 2 | rpm_hit2 |
|
||
| 1 | rpm_hit1 |
|
||
| 0 | rpm_hit0 |
|
||
| gmac_cmp_rx_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01080 Address@gxc_gmac0_regs : 0x07d21080 Address@gxc_gmac1_regs : 0x07d61080 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | - |
reserved | ||
| 30 | rx2_b3_eq_01_02_03_07_08_09_0d |
|
||
| 29 | rx2_eq_450008 |
|
||
| 28 | rx2_w1_eq_feb6 |
|
||
| 27 | rx2_w1_eq_a488 |
|
||
| 26 | rx2_w1_eq_0081 |
|
||
| 25 | rx_b3_eq_01_02_03_07_08_09_0d |
|
||
| 24 | rx_eq_450008 |
|
||
| 23 | rx_w1_eq_feb6 |
|
||
| 22 | rx_w1_eq_a488 |
|
||
| 21 | rx_w1_eq_0081 |
|
||
| 20 | rx_b3_is_smd |
|
||
| 19 | rx_b3_eq_0e |
|
||
| 18 | rx_b3_eq_1f |
|
||
| 17 | rx_b3_eq_0f |
|
||
| 16 | rx_b3_eq_ff |
|
||
| 15 | rx_b3_eq_61_52_9e_2a |
|
||
| 14 | rx_b3_eq_e6_4c_7f_b3 |
|
||
| 13 | rx_b3_eq_d5_07_19 |
|
||
| 12 | rx_b3_eq_07_19 |
|
||
| 11 | rx_b3_eq_2a |
|
||
| 10 | rx_b3_eq_9e |
|
||
| 9 | rx_b3_eq_52 |
|
||
| 8 | rx_b3_eq_61 |
|
||
| 7 | rx_b3_eq_b3 |
|
||
| 6 | rx_b3_eq_7f |
|
||
| 5 | rx_b3_eq_4c |
|
||
| 4 | rx_b3_eq_e6 |
|
||
| 3 | rx_b3_eq_19 |
|
||
| 2 | rx_b3_eq_07 |
|
||
| 1 | rx_b3_eq_d5 |
|
||
| 0 | rx_b3_eq_55 |
|
||
| gmac_status_int |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01084 Address@gxc_gmac0_regs : 0x07d21084 Address@gxc_gmac1_regs : 0x07d61084 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | utxe32_nxt |
|
||
| 30 | utx32_nxt |
|
||
| 29 | utxe32_last |
|
||
| 28 | utx32_last |
|
||
| 27 | utxe32or31_nxt |
|
||
| 26 | utx32or31_nxt |
|
||
| 25 | - |
reserved | ||
| 24 | tx_crc_ok_wr9 |
|
||
| 23 - 12 | - |
reserved | ||
| 11 | zero |
|
||
| 10 | - |
reserved | ||
| 9 | btran |
|
||
| 8 | brec |
|
||
| 7 | tpu_ovf |
|
||
| 6 | tpu_neg |
|
||
| 5 | tpu_zero |
|
||
| 4 | tpu_carry |
|
||
| 3 | rpu_ovf |
|
||
| 2 | rpu_neg |
|
||
| 1 | rpu_zero |
|
||
| 0 | rpu_carry |
|
||
| gmac_status_mii |
|
|||||||||||||||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01088 Address@gxc_gmac0_regs : 0x07d21088 Address@gxc_gmac1_regs : 0x07d61088 |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |||||||||||||||||||||
| 29 | - |
tx_swap |
|
|||||||||||||||||||||
| 28 | - |
rx_swap |
|
|||||||||||||||||||||
| 27 | 0 |
- |
reserved | |||||||||||||||||||||
| 26 | "0" |
dr_err_or_crx_err_or_fcr_err_was_here |
|
|||||||||||||||||||||
| 25 | "0" |
crx_err_or_fcr_err_was_here |
|
|||||||||||||||||||||
| 24 | "0" |
dr_err_or_crx_err_was_here |
|
|||||||||||||||||||||
| 23 | 0 |
- |
reserved | |||||||||||||||||||||
| 22 | "0" |
dr_err_or_crx_err_or_fcr_err |
|
|||||||||||||||||||||
| 21 | "0" |
crx_err_or_fcr_err |
|
|||||||||||||||||||||
| 20 | "0" |
dr_err_or_crx_err |
|
|||||||||||||||||||||
| 19 | "0" |
invalid_cg |
|
|||||||||||||||||||||
| 18 | "0" |
crs_and_txen |
|
|||||||||||||||||||||
| 17 | "0" |
col |
|
|||||||||||||||||||||
| 16 | "0" |
crs |
|
|||||||||||||||||||||
| 15 | "0" |
invalid_cg_was_here |
|
|||||||||||||||||||||
| 14 | "0" |
crs_and_txen_was_here |
|
|||||||||||||||||||||
| 13 | "0" |
col_was_here |
|
|||||||||||||||||||||
| 12 | "0" |
crs_was_here |
|
|||||||||||||||||||||
| 11 | "0" |
fcr_err_was_here |
|
|||||||||||||||||||||
| 10 | "0" |
crx_err_was_here |
|
|||||||||||||||||||||
| 9 | "0" |
dr_err_was_here |
|
|||||||||||||||||||||
| 8 | "0" |
rx_err_was_here |
|
|||||||||||||||||||||
| 7 | "0" |
crx_err |
|
|||||||||||||||||||||
| 6 | "0" |
crx |
|
|||||||||||||||||||||
| 5 | "0" |
fcr_err |
|
|||||||||||||||||||||
| 4 | "0" |
dr_err |
|
|||||||||||||||||||||
| 3 | "0" |
v_ne |
|
|||||||||||||||||||||
| 2 | "0" |
nv_ne |
|
|||||||||||||||||||||
| 1 | "0" |
rx_err |
|
|||||||||||||||||||||
| 0 | "0" |
rx_dv |
|
|||||||||||||||||||||
| gmac_status_miif |
|
|||||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0108c Address@gxc_gmac0_regs : 0x07d2108c Address@gxc_gmac1_regs : 0x07d6108c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
miif_error |
|
|||||||||||
| 30 | "0" |
miif_unfl |
|
|||||||||||
| 29 | "0" |
miif_ovfl |
|
|||||||||||
| 28 | "0" |
miif_short_dv |
|
|||||||||||
| 27 - 25 | 0 |
- |
reserved | |||||||||||
| 24 | "0" |
miif_short_ifg |
|
|||||||||||
| 23 - 21 | 0 |
- |
reserved | |||||||||||
| 20 | "0" |
miif_dr_err_or_crx_err |
|
|||||||||||
| 19 | "0" |
miif_wr_state_in_frame |
|
|||||||||||
| 18 | "0" |
miif_rd_state_wait_for_fifo_empty |
|
|||||||||||
| 17 | "0" |
miif_rd_state_frame_data |
|
|||||||||||
| 16 | "0" |
miif_rd_state_fifo_ramp_up |
|
|||||||||||
| 15 | "0" |
miif_rd_state_wait_for_frame |
|
|||||||||||
| 14 - 9 | 0 |
- |
reserved | |||||||||||
| 8 | "0" |
miif_not_empty |
|
|||||||||||
| 7 | "0" |
miif_crx_err |
|
|||||||||||
| 6 | "0" |
miif_crx |
|
|||||||||||
| 5 | 0 |
- |
reserved | |||||||||||
| 4 | "0" |
miif_dr_err |
|
|||||||||||
| 3 | "0" |
miif_v_ne |
|
|||||||||||
| 2 | "0" |
miif_nv_ne |
|
|||||||||||
| 1 | "0" |
miif_rx_err |
|
|||||||||||
| 0 | "0" |
miif_rx_dv |
|
|||||||||||
| gmac_config_mii |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01090 Address@gxc_gmac0_regs : 0x07d21090 Address@gxc_gmac1_regs : 0x07d61090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
hgmii_tx_idle_insert_k_cmd |
|
|
| 5 | "0" |
hgmii_tx_realign_cmd |
|
|
| 4 | "0" |
hgmii_mr_main_reset_cmd |
|
|
| 3 | "0" |
hgmii_mr_restart_an_cmd |
|
|
| 2 | "0" |
tx_dribble_nibble |
|
|
| 1 | "0" |
tx_err |
|
|
| 0 | "0" |
tx_en |
|
|
| gmac_debug_mii |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01094 Address@gxc_gmac0_regs : 0x07d21094 Address@gxc_gmac1_regs : 0x07d61094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
rgmii_warning_rx_data_not_repeated |
|
|
| 16 | "0" |
rmii_warning_direct_rxdv |
|
|
| 15 | "0" |
rmii_warning_10M_resync |
|
|
| 14 | "0" |
rmii_warning_misaligned_sof |
|
|
| 13 | "0" |
rmii_warning_misaligned_fc |
|
|
| 12 | "0" |
rmii_error_10M_not_repeated |
|
|
| 11 | "0" |
rmii_error_protocol |
|
|
| 10 | "0" |
rmii_error_short_crsdv |
|
|
| 9 | "0" |
rmii_error_unaligned_eof |
|
|
| 8 | "0" |
rmii_error_unaligned_eo_fc |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
misaligned_sof |
|
|
| 4 | "0" |
misaligned_smd |
|
|
| 3 | "0" |
invalid_smd |
|
|
| 2 | "0" |
short_preamble |
|
|
| 1 | "0" |
dribble_nibble |
|
|
| 0 | "0" |
smd_found |
|
|
| gmac_debug_sgmii |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01098 Address@gxc_gmac0_regs : 0x07d21098 Address@gxc_gmac1_regs : 0x07d61098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
sgmii_lp_adv_ability_received |
|
|
| 12 | "0" |
sgmii_mr_link |
|
|
| 11 | 0 |
- |
reserved | |
| 10 | "0" |
sgmii_rx_sync_status_fail |
|
|
| 9 | "0" |
sgmii_rx_com_det_evt |
|
|
| 8 | "0" |
sgmii_rx_adapt_sp_shift_evt |
|
|
| 7 - 4 | "0000" |
sgmii_tx_alignment |
|
|
| 3 | "0" |
sgmii_tx_realign_evt |
|
|
| 2 | "0" |
sgmii_tx_shrink_evt |
|
|
| 1 | "0" |
sgmii_tx_epd3_evt |
|
|
| 0 | "0" |
sgmii_tx_even |
|
|
| gmac_lut_bits |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0109c Address@gxc_gmac0_regs : 0x07d2109c Address@gxc_gmac1_regs : 0x07d6109c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
lut_out |
|
|
| 15 - 0 | 0x0 |
lut_in |
||
| gmac_rpu_wr0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010a0 Address@gxc_gmac0_regs : 0x07d210a0 Address@gxc_gmac1_regs : 0x07d610a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_rpu_wr1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010a4 Address@gxc_gmac0_regs : 0x07d210a4 Address@gxc_gmac1_regs : 0x07d610a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_rx_config |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x30200100 |
Address@gxc_gmac_regs : 0x07c010a8 Address@gxc_gmac0_regs : 0x07d210a8 Address@gxc_gmac1_regs : 0x07d610a8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
shift_rx_only_when_rxdv |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 29 - 23 | "1100000" |
rx_ifg_cnt_val |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
urx_fifo_fill_level_wrap |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 21 | "1" |
autoclear_error |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
autoclear_status |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
smd_detection_mode |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
rx_nibble2byte_man |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 17 - 16 | "00" |
rx_crc32_src |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 15 - 14 | "00" |
rx_crc_src |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
urxe_write_odd |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
urx_write_odd |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
rx_count_stops_at_ovfl |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
rx_shift_lr |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 9 - 8 | "01" |
rpu_sync_delay |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 7 - 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||
| 4 - 3 | "00" |
rx_fifo_depth_add |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 2 - 0 | "000" |
rx_fifo_depth |
|
|||||||||||||||||||||||||||||||||||||||||||||
| gmac_rx_config_clock_handling |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010ac Address@gxc_gmac0_regs : 0x07d210ac Address@gxc_gmac1_regs : 0x07d610ac |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
hgmii_mr_lp_adv_ability |
|
|||||
| 15 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
rx_nibble2byte_man_mode |
|
|||||
| gmac_rx |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010b0 Address@gxc_gmac0_regs : 0x07d210b0 Address@gxc_gmac1_regs : 0x07d610b0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | rx |
|
||
| gmac_rx2 |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010b4 Address@gxc_gmac0_regs : 0x07d210b4 Address@gxc_gmac1_regs : 0x07d610b4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_rx_last4 |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010b8 Address@gxc_gmac0_regs : 0x07d210b8 Address@gxc_gmac1_regs : 0x07d610b8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_rx_count |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010bc Address@gxc_gmac0_regs : 0x07d210bc Address@gxc_gmac1_regs : 0x07d610bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
rx_count |
|
|
| gmac_rpu_count1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010c0 Address@gxc_gmac0_regs : 0x07d210c0 Address@gxc_gmac1_regs : 0x07d610c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
rpu_count1 |
|
|
| gmac_rpu_count2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010c4 Address@gxc_gmac0_regs : 0x07d210c4 Address@gxc_gmac1_regs : 0x07d610c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
rpu_count2 |
|
|
| gmac_cmp_rpucnt_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010c8 Address@gxc_gmac0_regs : 0x07d210c8 Address@gxc_gmac1_regs : 0x07d610c8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 29 | - |
reserved | ||
| 28 | rx_ifg_cnt_zero |
|
||
| 27 | rpucnt2_wr3 |
|
||
| 26 | rpucnt2_wr2 |
|
||
| 25 | rpucnt2_wr1 |
|
||
| 24 | rpucnt2_wr0 |
|
||
| 23 | rpucnt2_mod8_zero |
|
||
| 22 | rpucnt2_mod4_zero |
|
||
| 21 | rpucnt1_mod8_zero |
|
||
| 20 | rpucnt1_mod4_zero |
|
||
| 19 | rpucnt2_gr_wr2_w1 |
|
||
| 18 | rpucnt2_sm_wr2_w0 |
|
||
| 17 | rpucnt1_gr_wr2_w1 |
|
||
| 16 | rpucnt1_sm_wr2_w0 |
|
||
| 15 | rpucnt1_sr7 |
|
||
| 14 | rpucnt1_sr6 |
|
||
| 13 | rpucnt1_sr5 |
|
||
| 12 | rpucnt1_sr4 |
|
||
| 11 | rpucnt1_sr3 |
|
||
| 10 | rpucnt1_sr2 |
|
||
| 9 | rpucnt1_sr1 |
|
||
| 8 | rpucnt1_sr0 |
|
||
| 7 | rpucnt1_wr7 |
|
||
| 6 | rpucnt1_wr6 |
|
||
| 5 | rpucnt1_wr5 |
|
||
| 4 | rpucnt1_wr4 |
|
||
| 3 | rpucnt1_wr3 |
|
||
| 2 | rpucnt1_wr2 |
|
||
| 1 | rpucnt1_wr1 |
|
||
| 0 | rpucnt1_wr0 |
|
||
| gmac_cmp_rxcrc_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010cc Address@gxc_gmac0_regs : 0x07d210cc Address@gxc_gmac1_regs : 0x07d610cc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||
| 21 | rx_crc32_ok_rx_last4_inv_hi_not_drewh |
|
||
| 20 | rx_crc32_ok_rx_last4_inv_not_drewh |
|
||
| 19 | rx_crc32_ok_wr9_not_drewh |
|
||
| 18 | rx_crc32_ok_not_drewh |
|
||
| 17 | rx_last4_b3_eq_crc32_b3_not_drewh |
|
||
| 16 | rx_crc_ok_rx_last4_inv_hi_not_drewh |
|
||
| 15 | rx_crc_ok_rx_last4_inv_not_drewh |
|
||
| 14 | rx_crc_ok_wr8_not_drewh |
|
||
| 13 | rx_crc_ok_not_drewh |
|
||
| 12 | rx_last4_b3_eq_crc_b3_not_drewh |
|
||
| 11 | rx_last4_b3_eq_crc32_b3 |
|
||
| 10 | rx_crc32_ok_rx_last4_inv_hi |
|
||
| 9 | rx_crc32_ok_rx_last4_inv_wr9 |
|
||
| 8 | rx_crc32_ok_rx_last4_inv |
|
||
| 7 | rx_crc32_ok_wr9 |
|
||
| 6 | rx_crc32_ok |
|
||
| 5 | rx_last4_b3_eq_crc_b3 |
|
||
| 4 | rx_crc_ok_rx_last4_inv_hi |
|
||
| 3 | rx_crc_ok_rx_last4_inv_wr8 |
|
||
| 2 | rx_crc_ok_rx_last4_inv |
|
||
| 1 | rx_crc_ok_wr8 |
|
||
| 0 | rx_crc_ok |
|
||
| gmac_tpu_wr0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010d0 Address@gxc_gmac0_regs : 0x07d210d0 Address@gxc_gmac1_regs : 0x07d610d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_tpu_wr1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010d4 Address@gxc_gmac0_regs : 0x07d210d4 Address@gxc_gmac1_regs : 0x07d610d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_tx_config |
|
|||||||||||||||
| R/W |
0x301ffc00 |
Address@gxc_gmac_regs : 0x07c010d8 Address@gxc_gmac0_regs : 0x07d210d8 Address@gxc_gmac1_regs : 0x07d610d8 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |||||||||||||
| 29 - 23 | "1100000" |
tx_ifg_cnt_val |
|
|||||||||||||
| 22 | "0" |
utx_fifo_fill_level_wrap |
|
|||||||||||||
| 21 - 20 | "01" |
mii_output_phase |
|
|||||||||||||
| 19 - 15 | "11111" |
utxe_watermark |
|
|||||||||||||
| 14 - 10 | "11111" |
utx_watermark |
|
|||||||||||||
| 9 - 8 | "00" |
tx_crc32_src |
|
|||||||||||||
| 7 - 6 | "00" |
tx_crc_src |
|
|||||||||||||
| 5 | "0" |
tx_count_stops_at_ovfl |
|
|||||||||||||
| 4 | "0" |
tx_shift_lr |
|
|||||||||||||
| 3 - 2 | "00" |
tpu_sync_delay |
|
|||||||||||||
| 1 - 0 | "00" |
tx_read_phase |
|
|||||||||||||
| gmac_tx_config_clock_handling |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010dc Address@gxc_gmac0_regs : 0x07d210dc Address@gxc_gmac1_regs : 0x07d610dc |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||||
| 1 | "0" |
tx_stay_on_byteborder |
|
|||||||||
| 0 | "0" |
tx_nibble2byte_mode |
|
|||||||||
| gmac_tx |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010e0 Address@gxc_gmac0_regs : 0x07d210e0 Address@gxc_gmac1_regs : 0x07d610e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
tx |
|
|
| gmac_tx2 |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010e4 Address@gxc_gmac0_regs : 0x07d210e4 Address@gxc_gmac1_regs : 0x07d610e4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | tx |
|
||
| gmac_tx_toggle_en |
|
|||||||
| W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010e8 Address@gxc_gmac0_regs : 0x07d210e8 Address@gxc_gmac1_regs : 0x07d610e8 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |||||
| 16 - 12 | "00000" |
txcnt_val |
|
|||||
| 11 | "0" |
load_txcnt |
|
|||||
| 10 | "0" |
mirror |
|
|||||
| 9 | "0" |
txer |
|
|||||
| 8 | "0" |
txen |
|
|||||
| 7 - 0 | "00000000" |
tx0 |
|
|||||
| gmac_tx_count |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010ec Address@gxc_gmac0_regs : 0x07d210ec Address@gxc_gmac1_regs : 0x07d610ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
tx_count |
|
|
| gmac_tpu_count1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010f0 Address@gxc_gmac0_regs : 0x07d210f0 Address@gxc_gmac1_regs : 0x07d610f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
tpu_count1 |
|
|
| gmac_tpu_count2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c010f4 Address@gxc_gmac0_regs : 0x07d210f4 Address@gxc_gmac1_regs : 0x07d610f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
tpu_count2 |
|
|
| gmac_cmp_tpucnt_status |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c010f8 Address@gxc_gmac0_regs : 0x07d210f8 Address@gxc_gmac1_regs : 0x07d610f8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 29 | - |
reserved | ||
| 28 | tx_ifg_cnt_zero |
|
||
| 27 | tpucnt2_wr7 |
|
||
| 26 | tpucnt2_wr6 |
|
||
| 25 | tpucnt2_wr5 |
|
||
| 24 | tpucnt2_wr4 |
|
||
| 23 | tpucnt2_mod8_zero |
|
||
| 22 | tpucnt2_mod4_zero |
|
||
| 21 | tpucnt1_mod8_zero |
|
||
| 20 | tpucnt1_mod4_zero |
|
||
| 19 | tpucnt2_gr_wr6_w1 |
|
||
| 18 | tpucnt2_sm_wr6_w0 |
|
||
| 17 | tpucnt1_gr_wr6_w1 |
|
||
| 16 | tpucnt1_sm_wr6_w0 |
|
||
| 15 | tpucnt1_sr7 |
|
||
| 14 | tpucnt1_sr6 |
|
||
| 13 | tpucnt1_sr5 |
|
||
| 12 | tpucnt1_sr4 |
|
||
| 11 | tpucnt1_sr3 |
|
||
| 10 | tpucnt1_sr2 |
|
||
| 9 | tpucnt1_sr1 |
|
||
| 8 | tpucnt1_sr0 |
|
||
| 7 | tpucnt1_wr7 |
|
||
| 6 | tpucnt1_wr6 |
|
||
| 5 | tpucnt1_wr5 |
|
||
| 4 | tpucnt1_wr4 |
|
||
| 3 | tpucnt1_wr3 |
|
||
| 2 | tpucnt1_wr2 |
|
||
| 1 | tpucnt1_wr1 |
|
||
| 0 | tpucnt1_wr0 |
|
||
| gmac_systime_msk |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01100 Address@gxc_gmac0_regs : 0x07d21100 Address@gxc_gmac1_regs : 0x07d61100 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_systime_cmp |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01104 Address@gxc_gmac0_regs : 0x07d21104 Address@gxc_gmac1_regs : 0x07d61104 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_systime |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01108 Address@gxc_gmac0_regs : 0x07d21108 Address@gxc_gmac1_regs : 0x07d61108 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_counter |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c0110c Address@gxc_gmac0_regs : 0x07d2110c Address@gxc_gmac1_regs : 0x07d6110c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_systime_phy |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01110 Address@gxc_gmac0_regs : 0x07d21110 Address@gxc_gmac1_regs : 0x07d61110 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_counter_phy |
|
|||
| R |
Address@gxc_gmac_regs : 0x07c01114 Address@gxc_gmac0_regs : 0x07d21114 Address@gxc_gmac1_regs : 0x07d61114 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gmac_rpu_pc |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01118 Address@gxc_gmac0_regs : 0x07d21118 Address@gxc_gmac1_regs : 0x07d61118 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |||||||||
| 6 - 0 | "0000000" |
rpu_pc |
|
|||||||||
| gmac_tpu_pc |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0111c Address@gxc_gmac0_regs : 0x07d2111c Address@gxc_gmac1_regs : 0x07d6111c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |||||
| 6 - 0 | "0000000" |
tpu_pc |
|
|||||
| gmac_urtx |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01120 Address@gxc_gmac0_regs : 0x07d21120 Address@gxc_gmac1_regs : 0x07d61120 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||||
| gmac_urx32 |
|
|||
| W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01124 Address@gxc_gmac0_regs : 0x07d21124 Address@gxc_gmac1_regs : 0x07d61124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_urtxe |
|
|||||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01128 Address@gxc_gmac0_regs : 0x07d21128 Address@gxc_gmac1_regs : 0x07d61128 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||||
| gmac_urxe32 |
|
|||
| W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0112c Address@gxc_gmac0_regs : 0x07d2112c Address@gxc_gmac1_regs : 0x07d6112c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_pm_mask0 |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01130 Address@gxc_gmac0_regs : 0x07d21130 Address@gxc_gmac1_regs : 0x07d61130 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_pm_val0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01134 Address@gxc_gmac0_regs : 0x07d21134 Address@gxc_gmac1_regs : 0x07d61134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_pm_mask1 |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01138 Address@gxc_gmac0_regs : 0x07d21138 Address@gxc_gmac1_regs : 0x07d61138 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_pm_val1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0113c Address@gxc_gmac0_regs : 0x07d2113c Address@gxc_gmac1_regs : 0x07d6113c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_pm_mask2 |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01140 Address@gxc_gmac0_regs : 0x07d21140 Address@gxc_gmac1_regs : 0x07d61140 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_pm_val2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01144 Address@gxc_gmac0_regs : 0x07d21144 Address@gxc_gmac1_regs : 0x07d61144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_pm_mask3 |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01148 Address@gxc_gmac0_regs : 0x07d21148 Address@gxc_gmac1_regs : 0x07d61148 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||
| gmac_pm_val3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0114c Address@gxc_gmac0_regs : 0x07d2114c Address@gxc_gmac1_regs : 0x07d6114c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gmac_rpu_jmp_latch |
|
|||||||
| R |
Address@gxc_gmac_regs : 0x07c01180 Address@gxc_gmac0_regs : 0x07d21180 Address@gxc_gmac1_regs : 0x07d61180 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||||||
| 6 - 0 | old_pc |
|
||||||
| gmac_rx_crc_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01184 Address@gxc_gmac0_regs : 0x07d21184 Address@gxc_gmac1_regs : 0x07d61184 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||
| 12 | "0" |
swap_output |
|
|||||||
| 11 | "0" |
endian |
|
|||||||
| 10 | "0" |
direct_div |
|
|||||||
| 9 - 8 | "00" |
nof_bits |
|
|||||||
| 7 - 3 | "00000" |
len |
|
|||||||
| 2 | "0" |
invert |
|
|||||||
| 1 | "0" |
zero |
|
|||||||
| 0 | "0" |
shift_right |
|
|||||||
| gmac_rx_crc_polynomial |
|
|||||||||
| R/W |
0x04c11db7 |
Address@gxc_gmac_regs : 0x07c01188 Address@gxc_gmac0_regs : 0x07d21188 Address@gxc_gmac1_regs : 0x07d61188 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x4c11db7 |
val |
|
|||||||
| gmac_rx_crc |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c0118c Address@gxc_gmac0_regs : 0x07d2118c Address@gxc_gmac1_regs : 0x07d6118c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||
| gmac_rx_crc32_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01190 Address@gxc_gmac0_regs : 0x07d21190 Address@gxc_gmac1_regs : 0x07d61190 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||
| 12 | "0" |
swap_output |
|
|||||||
| 11 | "0" |
endian |
|
|||||||
| 10 | "0" |
direct_div |
|
|||||||
| 9 - 8 | "00" |
nof_bits |
|
|||||||
| 7 - 3 | 0 |
- |
reserved | |||||||
| 2 | "0" |
invert |
|
|||||||
| 1 | "0" |
zero |
|
|||||||
| 0 | "0" |
shift_right |
|
|||||||
| gmac_rx_crc32 |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c01194 Address@gxc_gmac0_regs : 0x07d21194 Address@gxc_gmac1_regs : 0x07d61194 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||
| gmac_rpu_count1_2lsb_shift_val |
|
|||||||
| R |
Address@gxc_gmac_regs : 0x07c01198 Address@gxc_gmac0_regs : 0x07d21198 Address@gxc_gmac1_regs : 0x07d61198 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 5 | msk |
|
||||||
| 4 - 0 | srt |
|
||||||
| gmac_rpu_count2_2lsb_shift_val |
|
|||||||
| R |
Address@gxc_gmac_regs : 0x07c0119c Address@gxc_gmac0_regs : 0x07d2119c Address@gxc_gmac1_regs : 0x07d6119c |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 5 | msk |
|
||||||
| 4 - 0 | srt |
|
||||||
| gmac_rx_frame_err_cnt |
|
|||
| W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c011a0 Address@gxc_gmac0_regs : 0x07d211a0 Address@gxc_gmac1_regs : 0x07d611a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
cnt1 |
|
|
| 3 | "0" |
cnt0 |
|
|
| 2 | "0" |
proc_err |
|
|
| 1 | "0" |
frwd_err |
|
|
| 0 | "0" |
frame_err |
|
|
| gmac_rx_rpm_hit_num |
|
|||||||||||||
| R |
Address@gxc_gmac_regs : 0x07c011a4 Address@gxc_gmac0_regs : 0x07d211a4 Address@gxc_gmac1_regs : 0x07d611a4 |
Bits | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||||
| 2 - 0 | rpm_hit_num |
|
||||||||||||
| gmac_rx_smd_hit_num |
|
|||||||||||||||||||||
| R |
Address@gxc_gmac_regs : 0x07c011a8 Address@gxc_gmac0_regs : 0x07d211a8 Address@gxc_gmac1_regs : 0x07d611a8 |
Bits | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||||||||||||||||||||
| 3 - 0 | smd_hit_num |
|
||||||||||||||||||||
| gmac_tpu_jmp_latch |
|
|||||||
| R |
Address@gxc_gmac_regs : 0x07c011c0 Address@gxc_gmac0_regs : 0x07d211c0 Address@gxc_gmac1_regs : 0x07d611c0 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||||||
| 6 - 0 | old_pc |
|
||||||
| gmac_tx_crc_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c011c4 Address@gxc_gmac0_regs : 0x07d211c4 Address@gxc_gmac1_regs : 0x07d611c4 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||
| 12 | "0" |
swap_output |
|
|||||||
| 11 | "0" |
endian |
|
|||||||
| 10 | "0" |
direct_div |
|
|||||||
| 9 - 8 | "00" |
nof_bits |
|
|||||||
| 7 - 3 | "00000" |
len |
|
|||||||
| 2 | "0" |
invert |
|
|||||||
| 1 | "0" |
zero |
|
|||||||
| 0 | "0" |
shift_right |
|
|||||||
| gmac_tx_crc_polynomial |
|
|||||||||
| R/W |
0x04c11db7 |
Address@gxc_gmac_regs : 0x07c011c8 Address@gxc_gmac0_regs : 0x07d211c8 Address@gxc_gmac1_regs : 0x07d611c8 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x4c11db7 |
val |
|
|||||||
| gmac_tx_crc |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c011cc Address@gxc_gmac0_regs : 0x07d211cc Address@gxc_gmac1_regs : 0x07d611cc |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||
| gmac_tx_crc32_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c011d0 Address@gxc_gmac0_regs : 0x07d211d0 Address@gxc_gmac1_regs : 0x07d611d0 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||
| 12 | "0" |
swap_output |
|
|||||||
| 11 | "0" |
endian |
|
|||||||
| 10 | "0" |
direct_div |
|
|||||||
| 9 - 8 | "00" |
nof_bits |
|
|||||||
| 7 - 3 | 0 |
- |
reserved | |||||||
| 2 | "0" |
invert |
|
|||||||
| 1 | "0" |
zero |
|
|||||||
| 0 | "0" |
shift_right |
|
|||||||
| gmac_tx_crc32 |
|
|||||||||
| R/W |
0x00000000 |
Address@gxc_gmac_regs : 0x07c011d4 Address@gxc_gmac0_regs : 0x07d211d4 Address@gxc_gmac1_regs : 0x07d611d4 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | - | gpec_pram_start |
| 1-3fe | 4-ff8 | - | reserved |
| 3ff | ffc | - | gpec_pram_end |
| gpec_pram_start | |||
|
Address@gxc_gpec_pram : 0x07c02000 Address@gxc_gpec00_pram : 0x07d02000 Address@gxc_gpec01_pram : 0x07d06000 Address@gxc_gpec02_pram : 0x07d0a000 Address@gxc_gpec03_pram : 0x07d0e000 Address@gxc_gpec04_pram : 0x07d12000 Address@gxc_gpec05_pram : 0x07d16000 Address@gxc_gpec06_pram : 0x07d1a000 Address@gxc_gpec07_pram : 0x07d1e000 Address@gxc_gpec10_pram : 0x07d42000 Address@gxc_gpec11_pram : 0x07d46000 Address@gxc_gpec12_pram : 0x07d4a000 Address@gxc_gpec13_pram : 0x07d4e000 Address@gxc_gpec14_pram : 0x07d52000 Address@gxc_gpec15_pram : 0x07d56000 Address@gxc_gpec16_pram : 0x07d5a000 Address@gxc_gpec17_pram : 0x07d5e000 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gpec_pram_start | ||
| gpec_pram_end | |||
|
Address@gxc_gpec_pram : 0x07c02ffc Address@gxc_gpec00_pram : 0x07d02ffc Address@gxc_gpec01_pram : 0x07d06ffc Address@gxc_gpec02_pram : 0x07d0affc Address@gxc_gpec03_pram : 0x07d0effc Address@gxc_gpec04_pram : 0x07d12ffc Address@gxc_gpec05_pram : 0x07d16ffc Address@gxc_gpec06_pram : 0x07d1affc Address@gxc_gpec07_pram : 0x07d1effc Address@gxc_gpec10_pram : 0x07d42ffc Address@gxc_gpec11_pram : 0x07d46ffc Address@gxc_gpec12_pram : 0x07d4affc Address@gxc_gpec13_pram : 0x07d4effc Address@gxc_gpec14_pram : 0x07d52ffc Address@gxc_gpec15_pram : 0x07d56ffc Address@gxc_gpec16_pram : 0x07d5affc Address@gxc_gpec17_pram : 0x07d5effc |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gpec_pram_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gpec_r0 |
| 1 | 4 | R/W | gpec_r1 |
| 2 | 8 | R/W | gpec_r2 |
| 3 | c | R/W | gpec_r3 |
| 4 | 10 | R/W | gpec_r4 |
| 5 | 14 | R/W | gpec_r5 |
| 6 | 18 | R/W | gpec_r6 |
| 7 | 1c | R/W | gpec_r7 |
| 8 | 20 | R/W | gpec_stat_bits |
| 9 | 24 | R/W | gpec_range_urx_count |
| a | 28 | R/W | gpec_usr0 |
| b | 2c | R/W | gpec_range67 |
| c | 30 | R/W | gpec_timer0 |
| d | 34 | R/W | gpec_timer1 |
| e | 38 | R/W | gpec_timer2 |
| f | 3c | R/W | gpec_timer3 |
| 10 | 40 | R/W | gpec_timer4 |
| 11 | 44 | R/W | gpec_timer5 |
| 12 | 48 | R/W | gpec_urx_count |
| 13 | 4c | R/W | gpec_axi_data |
| 14 | 50 | R/W | gpec_pc |
| 15 | 54 | R/W | gpec_zero |
| 16 | 58 | R/W | gpec_config |
| 17 | 5c | R/W | gpec_ec_mask0 |
| 18 | 60 | R/W | gpec_ec_mask1 |
| 19 | 64 | R/W | gpec_ec_mask2 |
| 1a | 68 | R/W | gpec_ec_mask3 |
| 1b | 6c | R/W | gpec_ec_mask4 |
| 1c | 70 | R/W | gpec_ec_mask5 |
| 1d | 74 | R/W | gpec_ec_mask6 |
| 1e | 78 | R/W | gpec_ec_mask7 |
| 1f | 7c | R/W | gpec_pfifo_mask |
| 20 | 80 | R/W | gpec_pfifo_cfg |
| 21 | 84 | R/W | gpec_lut_bits |
| 22 | 88 | R/W | gpec_crc_data |
| 23 | 8c | W | gpec_irq |
| 24 | 90 | R | gpec_systime |
| 25 | 94 | R | gpec_counter |
| 26 | 98 | R/W | gpec_fifo_data |
| 27 | 9c | R/W | gpec_host_req |
| 28 | a0 | R/W | gpec_sr0 |
| 29 | a4 | R/W | gpec_sr1 |
| 2a | a8 | R/W | gpec_sr2 |
| 2b | ac | R/W | gpec_sr3 |
| 2c | b0 | R/W | gpec_sr4 |
| 2d | b4 | R/W | gpec_sr5 |
| 2e | b8 | R/W | gpec_sr6 |
| 2f | bc | R/W | gpec_sr7 |
| 30 | c0 | R/W | gpec_sr8 |
| 31 | c4 | R/W | gpec_sr9 |
| 32 | c8 | R/W | gpec_sr10 |
| 33 | cc | R/W | gpec_sr11 |
| 34 | d0 | R/W | gpec_sr12 |
| 35 | d4 | R/W | gpec_sr13 |
| 36 | d8 | R/W | gpec_sr14 |
| 37 | dc | R/W | gpec_sr15 |
| 38 | e0 | R/W | gpec_statcfg0 |
| 39 | e4 | R/W | gpec_statcfg1 |
| 3a | e8 | R/W | gpec_axi_wr_cfg |
| 3b | ec | R/W | gpec_axi_rd_cfg |
| 3c | f0 | R/W | gpec_urtx0 |
| 3d | f4 | R/W | gpec_urtx1 |
| 3e | f8 | R/W | gpec_urtxe0 |
| 3f | fc | R/W | gpec_urtxe1 |
| gpec_r0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03000 Address@gxc_gpec00_regs : 0x07d03000 Address@gxc_gpec01_regs : 0x07d07000 Address@gxc_gpec02_regs : 0x07d0b000 Address@gxc_gpec03_regs : 0x07d0f000 Address@gxc_gpec04_regs : 0x07d13000 Address@gxc_gpec05_regs : 0x07d17000 Address@gxc_gpec06_regs : 0x07d1b000 Address@gxc_gpec07_regs : 0x07d1f000 Address@gxc_gpec10_regs : 0x07d43000 Address@gxc_gpec11_regs : 0x07d47000 Address@gxc_gpec12_regs : 0x07d4b000 Address@gxc_gpec13_regs : 0x07d4f000 Address@gxc_gpec14_regs : 0x07d53000 Address@gxc_gpec15_regs : 0x07d57000 Address@gxc_gpec16_regs : 0x07d5b000 Address@gxc_gpec17_regs : 0x07d5f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r0 |
|
|
| gpec_r1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03004 Address@gxc_gpec00_regs : 0x07d03004 Address@gxc_gpec01_regs : 0x07d07004 Address@gxc_gpec02_regs : 0x07d0b004 Address@gxc_gpec03_regs : 0x07d0f004 Address@gxc_gpec04_regs : 0x07d13004 Address@gxc_gpec05_regs : 0x07d17004 Address@gxc_gpec06_regs : 0x07d1b004 Address@gxc_gpec07_regs : 0x07d1f004 Address@gxc_gpec10_regs : 0x07d43004 Address@gxc_gpec11_regs : 0x07d47004 Address@gxc_gpec12_regs : 0x07d4b004 Address@gxc_gpec13_regs : 0x07d4f004 Address@gxc_gpec14_regs : 0x07d53004 Address@gxc_gpec15_regs : 0x07d57004 Address@gxc_gpec16_regs : 0x07d5b004 Address@gxc_gpec17_regs : 0x07d5f004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r1 |
|
|
| gpec_r2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03008 Address@gxc_gpec00_regs : 0x07d03008 Address@gxc_gpec01_regs : 0x07d07008 Address@gxc_gpec02_regs : 0x07d0b008 Address@gxc_gpec03_regs : 0x07d0f008 Address@gxc_gpec04_regs : 0x07d13008 Address@gxc_gpec05_regs : 0x07d17008 Address@gxc_gpec06_regs : 0x07d1b008 Address@gxc_gpec07_regs : 0x07d1f008 Address@gxc_gpec10_regs : 0x07d43008 Address@gxc_gpec11_regs : 0x07d47008 Address@gxc_gpec12_regs : 0x07d4b008 Address@gxc_gpec13_regs : 0x07d4f008 Address@gxc_gpec14_regs : 0x07d53008 Address@gxc_gpec15_regs : 0x07d57008 Address@gxc_gpec16_regs : 0x07d5b008 Address@gxc_gpec17_regs : 0x07d5f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r2 |
|
|
| gpec_r3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0300c Address@gxc_gpec00_regs : 0x07d0300c Address@gxc_gpec01_regs : 0x07d0700c Address@gxc_gpec02_regs : 0x07d0b00c Address@gxc_gpec03_regs : 0x07d0f00c Address@gxc_gpec04_regs : 0x07d1300c Address@gxc_gpec05_regs : 0x07d1700c Address@gxc_gpec06_regs : 0x07d1b00c Address@gxc_gpec07_regs : 0x07d1f00c Address@gxc_gpec10_regs : 0x07d4300c Address@gxc_gpec11_regs : 0x07d4700c Address@gxc_gpec12_regs : 0x07d4b00c Address@gxc_gpec13_regs : 0x07d4f00c Address@gxc_gpec14_regs : 0x07d5300c Address@gxc_gpec15_regs : 0x07d5700c Address@gxc_gpec16_regs : 0x07d5b00c Address@gxc_gpec17_regs : 0x07d5f00c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r3 |
|
|
| gpec_r4 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03010 Address@gxc_gpec00_regs : 0x07d03010 Address@gxc_gpec01_regs : 0x07d07010 Address@gxc_gpec02_regs : 0x07d0b010 Address@gxc_gpec03_regs : 0x07d0f010 Address@gxc_gpec04_regs : 0x07d13010 Address@gxc_gpec05_regs : 0x07d17010 Address@gxc_gpec06_regs : 0x07d1b010 Address@gxc_gpec07_regs : 0x07d1f010 Address@gxc_gpec10_regs : 0x07d43010 Address@gxc_gpec11_regs : 0x07d47010 Address@gxc_gpec12_regs : 0x07d4b010 Address@gxc_gpec13_regs : 0x07d4f010 Address@gxc_gpec14_regs : 0x07d53010 Address@gxc_gpec15_regs : 0x07d57010 Address@gxc_gpec16_regs : 0x07d5b010 Address@gxc_gpec17_regs : 0x07d5f010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r4 |
|
|
| gpec_r5 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03014 Address@gxc_gpec00_regs : 0x07d03014 Address@gxc_gpec01_regs : 0x07d07014 Address@gxc_gpec02_regs : 0x07d0b014 Address@gxc_gpec03_regs : 0x07d0f014 Address@gxc_gpec04_regs : 0x07d13014 Address@gxc_gpec05_regs : 0x07d17014 Address@gxc_gpec06_regs : 0x07d1b014 Address@gxc_gpec07_regs : 0x07d1f014 Address@gxc_gpec10_regs : 0x07d43014 Address@gxc_gpec11_regs : 0x07d47014 Address@gxc_gpec12_regs : 0x07d4b014 Address@gxc_gpec13_regs : 0x07d4f014 Address@gxc_gpec14_regs : 0x07d53014 Address@gxc_gpec15_regs : 0x07d57014 Address@gxc_gpec16_regs : 0x07d5b014 Address@gxc_gpec17_regs : 0x07d5f014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r5 |
|
|
| gpec_r6 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03018 Address@gxc_gpec00_regs : 0x07d03018 Address@gxc_gpec01_regs : 0x07d07018 Address@gxc_gpec02_regs : 0x07d0b018 Address@gxc_gpec03_regs : 0x07d0f018 Address@gxc_gpec04_regs : 0x07d13018 Address@gxc_gpec05_regs : 0x07d17018 Address@gxc_gpec06_regs : 0x07d1b018 Address@gxc_gpec07_regs : 0x07d1f018 Address@gxc_gpec10_regs : 0x07d43018 Address@gxc_gpec11_regs : 0x07d47018 Address@gxc_gpec12_regs : 0x07d4b018 Address@gxc_gpec13_regs : 0x07d4f018 Address@gxc_gpec14_regs : 0x07d53018 Address@gxc_gpec15_regs : 0x07d57018 Address@gxc_gpec16_regs : 0x07d5b018 Address@gxc_gpec17_regs : 0x07d5f018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r6 |
|
|
| gpec_r7 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0301c Address@gxc_gpec00_regs : 0x07d0301c Address@gxc_gpec01_regs : 0x07d0701c Address@gxc_gpec02_regs : 0x07d0b01c Address@gxc_gpec03_regs : 0x07d0f01c Address@gxc_gpec04_regs : 0x07d1301c Address@gxc_gpec05_regs : 0x07d1701c Address@gxc_gpec06_regs : 0x07d1b01c Address@gxc_gpec07_regs : 0x07d1f01c Address@gxc_gpec10_regs : 0x07d4301c Address@gxc_gpec11_regs : 0x07d4701c Address@gxc_gpec12_regs : 0x07d4b01c Address@gxc_gpec13_regs : 0x07d4f01c Address@gxc_gpec14_regs : 0x07d5301c Address@gxc_gpec15_regs : 0x07d5701c Address@gxc_gpec16_regs : 0x07d5b01c Address@gxc_gpec17_regs : 0x07d5f01c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
r7 |
|
|
| gpec_stat_bits |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03020 Address@gxc_gpec00_regs : 0x07d03020 Address@gxc_gpec01_regs : 0x07d07020 Address@gxc_gpec02_regs : 0x07d0b020 Address@gxc_gpec03_regs : 0x07d0f020 Address@gxc_gpec04_regs : 0x07d13020 Address@gxc_gpec05_regs : 0x07d17020 Address@gxc_gpec06_regs : 0x07d1b020 Address@gxc_gpec07_regs : 0x07d1f020 Address@gxc_gpec10_regs : 0x07d43020 Address@gxc_gpec11_regs : 0x07d47020 Address@gxc_gpec12_regs : 0x07d4b020 Address@gxc_gpec13_regs : 0x07d4f020 Address@gxc_gpec14_regs : 0x07d53020 Address@gxc_gpec15_regs : 0x07d57020 Address@gxc_gpec16_regs : 0x07d5b020 Address@gxc_gpec17_regs : 0x07d5f020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
set_mask |
|
|
| 15 - 0 | 0x0 |
flags |
|
|
| gpec_range_urx_count |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03024 Address@gxc_gpec00_regs : 0x07d03024 Address@gxc_gpec01_regs : 0x07d07024 Address@gxc_gpec02_regs : 0x07d0b024 Address@gxc_gpec03_regs : 0x07d0f024 Address@gxc_gpec04_regs : 0x07d13024 Address@gxc_gpec05_regs : 0x07d17024 Address@gxc_gpec06_regs : 0x07d1b024 Address@gxc_gpec07_regs : 0x07d1f024 Address@gxc_gpec10_regs : 0x07d43024 Address@gxc_gpec11_regs : 0x07d47024 Address@gxc_gpec12_regs : 0x07d4b024 Address@gxc_gpec13_regs : 0x07d4f024 Address@gxc_gpec14_regs : 0x07d53024 Address@gxc_gpec15_regs : 0x07d57024 Address@gxc_gpec16_regs : 0x07d5b024 Address@gxc_gpec17_regs : 0x07d5f024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
range_urxe_count |
|
|
| 15 - 0 | 0x0 |
range_urx_count |
|
|
| gpec_usr0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03028 Address@gxc_gpec00_regs : 0x07d03028 Address@gxc_gpec01_regs : 0x07d07028 Address@gxc_gpec02_regs : 0x07d0b028 Address@gxc_gpec03_regs : 0x07d0f028 Address@gxc_gpec04_regs : 0x07d13028 Address@gxc_gpec05_regs : 0x07d17028 Address@gxc_gpec06_regs : 0x07d1b028 Address@gxc_gpec07_regs : 0x07d1f028 Address@gxc_gpec10_regs : 0x07d43028 Address@gxc_gpec11_regs : 0x07d47028 Address@gxc_gpec12_regs : 0x07d4b028 Address@gxc_gpec13_regs : 0x07d4f028 Address@gxc_gpec14_regs : 0x07d53028 Address@gxc_gpec15_regs : 0x07d57028 Address@gxc_gpec16_regs : 0x07d5b028 Address@gxc_gpec17_regs : 0x07d5f028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_range67 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0302c Address@gxc_gpec00_regs : 0x07d0302c Address@gxc_gpec01_regs : 0x07d0702c Address@gxc_gpec02_regs : 0x07d0b02c Address@gxc_gpec03_regs : 0x07d0f02c Address@gxc_gpec04_regs : 0x07d1302c Address@gxc_gpec05_regs : 0x07d1702c Address@gxc_gpec06_regs : 0x07d1b02c Address@gxc_gpec07_regs : 0x07d1f02c Address@gxc_gpec10_regs : 0x07d4302c Address@gxc_gpec11_regs : 0x07d4702c Address@gxc_gpec12_regs : 0x07d4b02c Address@gxc_gpec13_regs : 0x07d4f02c Address@gxc_gpec14_regs : 0x07d5302c Address@gxc_gpec15_regs : 0x07d5702c Address@gxc_gpec16_regs : 0x07d5b02c Address@gxc_gpec17_regs : 0x07d5f02c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | |
| 28 - 16 | 0x0 |
range7 |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 - 0 | 0x0 |
range6 |
|
|
| gpec_timer0 |
|
||||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03030 Address@gxc_gpec00_regs : 0x07d03030 Address@gxc_gpec01_regs : 0x07d07030 Address@gxc_gpec02_regs : 0x07d0b030 Address@gxc_gpec03_regs : 0x07d0f030 Address@gxc_gpec04_regs : 0x07d13030 Address@gxc_gpec05_regs : 0x07d17030 Address@gxc_gpec06_regs : 0x07d1b030 Address@gxc_gpec07_regs : 0x07d1f030 Address@gxc_gpec10_regs : 0x07d43030 Address@gxc_gpec11_regs : 0x07d47030 Address@gxc_gpec12_regs : 0x07d4b030 Address@gxc_gpec13_regs : 0x07d4f030 Address@gxc_gpec14_regs : 0x07d53030 Address@gxc_gpec15_regs : 0x07d57030 Address@gxc_gpec16_regs : 0x07d5b030 Address@gxc_gpec17_regs : 0x07d5f030 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload0 |
|
||||||
| gpec_timer1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03034 Address@gxc_gpec00_regs : 0x07d03034 Address@gxc_gpec01_regs : 0x07d07034 Address@gxc_gpec02_regs : 0x07d0b034 Address@gxc_gpec03_regs : 0x07d0f034 Address@gxc_gpec04_regs : 0x07d13034 Address@gxc_gpec05_regs : 0x07d17034 Address@gxc_gpec06_regs : 0x07d1b034 Address@gxc_gpec07_regs : 0x07d1f034 Address@gxc_gpec10_regs : 0x07d43034 Address@gxc_gpec11_regs : 0x07d47034 Address@gxc_gpec12_regs : 0x07d4b034 Address@gxc_gpec13_regs : 0x07d4f034 Address@gxc_gpec14_regs : 0x07d53034 Address@gxc_gpec15_regs : 0x07d57034 Address@gxc_gpec16_regs : 0x07d5b034 Address@gxc_gpec17_regs : 0x07d5f034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload1 |
|
|
| gpec_timer2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03038 Address@gxc_gpec00_regs : 0x07d03038 Address@gxc_gpec01_regs : 0x07d07038 Address@gxc_gpec02_regs : 0x07d0b038 Address@gxc_gpec03_regs : 0x07d0f038 Address@gxc_gpec04_regs : 0x07d13038 Address@gxc_gpec05_regs : 0x07d17038 Address@gxc_gpec06_regs : 0x07d1b038 Address@gxc_gpec07_regs : 0x07d1f038 Address@gxc_gpec10_regs : 0x07d43038 Address@gxc_gpec11_regs : 0x07d47038 Address@gxc_gpec12_regs : 0x07d4b038 Address@gxc_gpec13_regs : 0x07d4f038 Address@gxc_gpec14_regs : 0x07d53038 Address@gxc_gpec15_regs : 0x07d57038 Address@gxc_gpec16_regs : 0x07d5b038 Address@gxc_gpec17_regs : 0x07d5f038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload2 |
|
|
| gpec_timer3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0303c Address@gxc_gpec00_regs : 0x07d0303c Address@gxc_gpec01_regs : 0x07d0703c Address@gxc_gpec02_regs : 0x07d0b03c Address@gxc_gpec03_regs : 0x07d0f03c Address@gxc_gpec04_regs : 0x07d1303c Address@gxc_gpec05_regs : 0x07d1703c Address@gxc_gpec06_regs : 0x07d1b03c Address@gxc_gpec07_regs : 0x07d1f03c Address@gxc_gpec10_regs : 0x07d4303c Address@gxc_gpec11_regs : 0x07d4703c Address@gxc_gpec12_regs : 0x07d4b03c Address@gxc_gpec13_regs : 0x07d4f03c Address@gxc_gpec14_regs : 0x07d5303c Address@gxc_gpec15_regs : 0x07d5703c Address@gxc_gpec16_regs : 0x07d5b03c Address@gxc_gpec17_regs : 0x07d5f03c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload3 |
|
|
| gpec_timer4 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03040 Address@gxc_gpec00_regs : 0x07d03040 Address@gxc_gpec01_regs : 0x07d07040 Address@gxc_gpec02_regs : 0x07d0b040 Address@gxc_gpec03_regs : 0x07d0f040 Address@gxc_gpec04_regs : 0x07d13040 Address@gxc_gpec05_regs : 0x07d17040 Address@gxc_gpec06_regs : 0x07d1b040 Address@gxc_gpec07_regs : 0x07d1f040 Address@gxc_gpec10_regs : 0x07d43040 Address@gxc_gpec11_regs : 0x07d47040 Address@gxc_gpec12_regs : 0x07d4b040 Address@gxc_gpec13_regs : 0x07d4f040 Address@gxc_gpec14_regs : 0x07d53040 Address@gxc_gpec15_regs : 0x07d57040 Address@gxc_gpec16_regs : 0x07d5b040 Address@gxc_gpec17_regs : 0x07d5f040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload4 |
|
|
| gpec_timer5 |
|
|||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03044 Address@gxc_gpec00_regs : 0x07d03044 Address@gxc_gpec01_regs : 0x07d07044 Address@gxc_gpec02_regs : 0x07d0b044 Address@gxc_gpec03_regs : 0x07d0f044 Address@gxc_gpec04_regs : 0x07d13044 Address@gxc_gpec05_regs : 0x07d17044 Address@gxc_gpec06_regs : 0x07d1b044 Address@gxc_gpec07_regs : 0x07d1f044 Address@gxc_gpec10_regs : 0x07d43044 Address@gxc_gpec11_regs : 0x07d47044 Address@gxc_gpec12_regs : 0x07d4b044 Address@gxc_gpec13_regs : 0x07d4f044 Address@gxc_gpec14_regs : 0x07d53044 Address@gxc_gpec15_regs : 0x07d57044 Address@gxc_gpec16_regs : 0x07d5b044 Address@gxc_gpec17_regs : 0x07d5f044 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_preload5 |
|
|||||||||||||||||||||||||
| gpec_urx_count |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03048 Address@gxc_gpec00_regs : 0x07d03048 Address@gxc_gpec01_regs : 0x07d07048 Address@gxc_gpec02_regs : 0x07d0b048 Address@gxc_gpec03_regs : 0x07d0f048 Address@gxc_gpec04_regs : 0x07d13048 Address@gxc_gpec05_regs : 0x07d17048 Address@gxc_gpec06_regs : 0x07d1b048 Address@gxc_gpec07_regs : 0x07d1f048 Address@gxc_gpec10_regs : 0x07d43048 Address@gxc_gpec11_regs : 0x07d47048 Address@gxc_gpec12_regs : 0x07d4b048 Address@gxc_gpec13_regs : 0x07d4f048 Address@gxc_gpec14_regs : 0x07d53048 Address@gxc_gpec15_regs : 0x07d57048 Address@gxc_gpec16_regs : 0x07d5b048 Address@gxc_gpec17_regs : 0x07d5f048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
urxe_count |
|
|
| 15 - 0 | 0x0 |
urx_count |
|
|
| gpec_axi_data |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0304c Address@gxc_gpec00_regs : 0x07d0304c Address@gxc_gpec01_regs : 0x07d0704c Address@gxc_gpec02_regs : 0x07d0b04c Address@gxc_gpec03_regs : 0x07d0f04c Address@gxc_gpec04_regs : 0x07d1304c Address@gxc_gpec05_regs : 0x07d1704c Address@gxc_gpec06_regs : 0x07d1b04c Address@gxc_gpec07_regs : 0x07d1f04c Address@gxc_gpec10_regs : 0x07d4304c Address@gxc_gpec11_regs : 0x07d4704c Address@gxc_gpec12_regs : 0x07d4b04c Address@gxc_gpec13_regs : 0x07d4f04c Address@gxc_gpec14_regs : 0x07d5304c Address@gxc_gpec15_regs : 0x07d5704c Address@gxc_gpec16_regs : 0x07d5b04c Address@gxc_gpec17_regs : 0x07d5f04c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_pc |
|
|||
| R/W |
0x000007ff |
Address@gxc_gpec_regs : 0x07c03050 Address@gxc_gpec00_regs : 0x07d03050 Address@gxc_gpec01_regs : 0x07d07050 Address@gxc_gpec02_regs : 0x07d0b050 Address@gxc_gpec03_regs : 0x07d0f050 Address@gxc_gpec04_regs : 0x07d13050 Address@gxc_gpec05_regs : 0x07d17050 Address@gxc_gpec06_regs : 0x07d1b050 Address@gxc_gpec07_regs : 0x07d1f050 Address@gxc_gpec10_regs : 0x07d43050 Address@gxc_gpec11_regs : 0x07d47050 Address@gxc_gpec12_regs : 0x07d4b050 Address@gxc_gpec13_regs : 0x07d4f050 Address@gxc_gpec14_regs : 0x07d53050 Address@gxc_gpec15_regs : 0x07d57050 Address@gxc_gpec16_regs : 0x07d5b050 Address@gxc_gpec17_regs : 0x07d5f050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x7ff |
pc |
|
|
| gpec_zero |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03054 Address@gxc_gpec00_regs : 0x07d03054 Address@gxc_gpec01_regs : 0x07d07054 Address@gxc_gpec02_regs : 0x07d0b054 Address@gxc_gpec03_regs : 0x07d0f054 Address@gxc_gpec04_regs : 0x07d13054 Address@gxc_gpec05_regs : 0x07d17054 Address@gxc_gpec06_regs : 0x07d1b054 Address@gxc_gpec07_regs : 0x07d1f054 Address@gxc_gpec10_regs : 0x07d43054 Address@gxc_gpec11_regs : 0x07d47054 Address@gxc_gpec12_regs : 0x07d4b054 Address@gxc_gpec13_regs : 0x07d4f054 Address@gxc_gpec14_regs : 0x07d53054 Address@gxc_gpec15_regs : 0x07d57054 Address@gxc_gpec16_regs : 0x07d5b054 Address@gxc_gpec17_regs : 0x07d5f054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
zero |
|
|
| gpec_config |
|
|||||||||||||||||||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03058 Address@gxc_gpec00_regs : 0x07d03058 Address@gxc_gpec01_regs : 0x07d07058 Address@gxc_gpec02_regs : 0x07d0b058 Address@gxc_gpec03_regs : 0x07d0f058 Address@gxc_gpec04_regs : 0x07d13058 Address@gxc_gpec05_regs : 0x07d17058 Address@gxc_gpec06_regs : 0x07d1b058 Address@gxc_gpec07_regs : 0x07d1f058 Address@gxc_gpec10_regs : 0x07d43058 Address@gxc_gpec11_regs : 0x07d47058 Address@gxc_gpec12_regs : 0x07d4b058 Address@gxc_gpec13_regs : 0x07d4f058 Address@gxc_gpec14_regs : 0x07d53058 Address@gxc_gpec15_regs : 0x07d57058 Address@gxc_gpec16_regs : 0x07d5b058 Address@gxc_gpec17_regs : 0x07d5f058 |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | "00" |
register_mode |
|
|||||||||||||||||||||
| 29 - 27 | "000" |
frame_cmp_status |
|
|||||||||||||||||||||
| 26 - 23 | "0000" |
usr |
|
|||||||||||||||||||||
| 22 | "0" |
frame_cmp_config64 |
|
|||||||||||||||||||||
| 21 - 18 | "0000" |
event |
|
|||||||||||||||||||||
| 17 - 15 | "000" |
timer5 |
|
|||||||||||||||||||||
| 14 - 12 | "000" |
timer4 |
|
|||||||||||||||||||||
| 11 - 9 | "000" |
timer3 |
|
|||||||||||||||||||||
| 8 - 6 | "000" |
timer2 |
|
|||||||||||||||||||||
| 5 - 3 | "000" |
timer1 |
|
|||||||||||||||||||||
| 2 - 0 | "000" |
timer0 |
|
|||||||||||||||||||||
| gpec_ec_mask0 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c0305c Address@gxc_gpec00_regs : 0x07d0305c Address@gxc_gpec01_regs : 0x07d0705c Address@gxc_gpec02_regs : 0x07d0b05c Address@gxc_gpec03_regs : 0x07d0f05c Address@gxc_gpec04_regs : 0x07d1305c Address@gxc_gpec05_regs : 0x07d1705c Address@gxc_gpec06_regs : 0x07d1b05c Address@gxc_gpec07_regs : 0x07d1f05c Address@gxc_gpec10_regs : 0x07d4305c Address@gxc_gpec11_regs : 0x07d4705c Address@gxc_gpec12_regs : 0x07d4b05c Address@gxc_gpec13_regs : 0x07d4f05c Address@gxc_gpec14_regs : 0x07d5305c Address@gxc_gpec15_regs : 0x07d5705c Address@gxc_gpec16_regs : 0x07d5b05c Address@gxc_gpec17_regs : 0x07d5f05c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask1 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03060 Address@gxc_gpec00_regs : 0x07d03060 Address@gxc_gpec01_regs : 0x07d07060 Address@gxc_gpec02_regs : 0x07d0b060 Address@gxc_gpec03_regs : 0x07d0f060 Address@gxc_gpec04_regs : 0x07d13060 Address@gxc_gpec05_regs : 0x07d17060 Address@gxc_gpec06_regs : 0x07d1b060 Address@gxc_gpec07_regs : 0x07d1f060 Address@gxc_gpec10_regs : 0x07d43060 Address@gxc_gpec11_regs : 0x07d47060 Address@gxc_gpec12_regs : 0x07d4b060 Address@gxc_gpec13_regs : 0x07d4f060 Address@gxc_gpec14_regs : 0x07d53060 Address@gxc_gpec15_regs : 0x07d57060 Address@gxc_gpec16_regs : 0x07d5b060 Address@gxc_gpec17_regs : 0x07d5f060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask2 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03064 Address@gxc_gpec00_regs : 0x07d03064 Address@gxc_gpec01_regs : 0x07d07064 Address@gxc_gpec02_regs : 0x07d0b064 Address@gxc_gpec03_regs : 0x07d0f064 Address@gxc_gpec04_regs : 0x07d13064 Address@gxc_gpec05_regs : 0x07d17064 Address@gxc_gpec06_regs : 0x07d1b064 Address@gxc_gpec07_regs : 0x07d1f064 Address@gxc_gpec10_regs : 0x07d43064 Address@gxc_gpec11_regs : 0x07d47064 Address@gxc_gpec12_regs : 0x07d4b064 Address@gxc_gpec13_regs : 0x07d4f064 Address@gxc_gpec14_regs : 0x07d53064 Address@gxc_gpec15_regs : 0x07d57064 Address@gxc_gpec16_regs : 0x07d5b064 Address@gxc_gpec17_regs : 0x07d5f064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask3 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03068 Address@gxc_gpec00_regs : 0x07d03068 Address@gxc_gpec01_regs : 0x07d07068 Address@gxc_gpec02_regs : 0x07d0b068 Address@gxc_gpec03_regs : 0x07d0f068 Address@gxc_gpec04_regs : 0x07d13068 Address@gxc_gpec05_regs : 0x07d17068 Address@gxc_gpec06_regs : 0x07d1b068 Address@gxc_gpec07_regs : 0x07d1f068 Address@gxc_gpec10_regs : 0x07d43068 Address@gxc_gpec11_regs : 0x07d47068 Address@gxc_gpec12_regs : 0x07d4b068 Address@gxc_gpec13_regs : 0x07d4f068 Address@gxc_gpec14_regs : 0x07d53068 Address@gxc_gpec15_regs : 0x07d57068 Address@gxc_gpec16_regs : 0x07d5b068 Address@gxc_gpec17_regs : 0x07d5f068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask4 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c0306c Address@gxc_gpec00_regs : 0x07d0306c Address@gxc_gpec01_regs : 0x07d0706c Address@gxc_gpec02_regs : 0x07d0b06c Address@gxc_gpec03_regs : 0x07d0f06c Address@gxc_gpec04_regs : 0x07d1306c Address@gxc_gpec05_regs : 0x07d1706c Address@gxc_gpec06_regs : 0x07d1b06c Address@gxc_gpec07_regs : 0x07d1f06c Address@gxc_gpec10_regs : 0x07d4306c Address@gxc_gpec11_regs : 0x07d4706c Address@gxc_gpec12_regs : 0x07d4b06c Address@gxc_gpec13_regs : 0x07d4f06c Address@gxc_gpec14_regs : 0x07d5306c Address@gxc_gpec15_regs : 0x07d5706c Address@gxc_gpec16_regs : 0x07d5b06c Address@gxc_gpec17_regs : 0x07d5f06c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask5 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03070 Address@gxc_gpec00_regs : 0x07d03070 Address@gxc_gpec01_regs : 0x07d07070 Address@gxc_gpec02_regs : 0x07d0b070 Address@gxc_gpec03_regs : 0x07d0f070 Address@gxc_gpec04_regs : 0x07d13070 Address@gxc_gpec05_regs : 0x07d17070 Address@gxc_gpec06_regs : 0x07d1b070 Address@gxc_gpec07_regs : 0x07d1f070 Address@gxc_gpec10_regs : 0x07d43070 Address@gxc_gpec11_regs : 0x07d47070 Address@gxc_gpec12_regs : 0x07d4b070 Address@gxc_gpec13_regs : 0x07d4f070 Address@gxc_gpec14_regs : 0x07d53070 Address@gxc_gpec15_regs : 0x07d57070 Address@gxc_gpec16_regs : 0x07d5b070 Address@gxc_gpec17_regs : 0x07d5f070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask6 |
|
|||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03074 Address@gxc_gpec00_regs : 0x07d03074 Address@gxc_gpec01_regs : 0x07d07074 Address@gxc_gpec02_regs : 0x07d0b074 Address@gxc_gpec03_regs : 0x07d0f074 Address@gxc_gpec04_regs : 0x07d13074 Address@gxc_gpec05_regs : 0x07d17074 Address@gxc_gpec06_regs : 0x07d1b074 Address@gxc_gpec07_regs : 0x07d1f074 Address@gxc_gpec10_regs : 0x07d43074 Address@gxc_gpec11_regs : 0x07d47074 Address@gxc_gpec12_regs : 0x07d4b074 Address@gxc_gpec13_regs : 0x07d4f074 Address@gxc_gpec14_regs : 0x07d53074 Address@gxc_gpec15_regs : 0x07d57074 Address@gxc_gpec16_regs : 0x07d5b074 Address@gxc_gpec17_regs : 0x07d5f074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|
| 30 - 29 | "00" |
level_edge_event1 |
|
|
| 28 - 27 | "00" |
level_edge_event0 |
|
|
| 26 | 0 |
- |
reserved | |
| 25 - 16 | 0x0 |
jmp_adr |
|
|
| 15 - 8 | "11111111" |
sel1 |
|
|
| 7 - 0 | "11111111" |
sel0 |
|
|
| gpec_ec_mask7 |
|
|||||||||||||||
| R/W |
0x0000ffff |
Address@gxc_gpec_regs : 0x07c03078 Address@gxc_gpec00_regs : 0x07d03078 Address@gxc_gpec01_regs : 0x07d07078 Address@gxc_gpec02_regs : 0x07d0b078 Address@gxc_gpec03_regs : 0x07d0f078 Address@gxc_gpec04_regs : 0x07d13078 Address@gxc_gpec05_regs : 0x07d17078 Address@gxc_gpec06_regs : 0x07d1b078 Address@gxc_gpec07_regs : 0x07d1f078 Address@gxc_gpec10_regs : 0x07d43078 Address@gxc_gpec11_regs : 0x07d47078 Address@gxc_gpec12_regs : 0x07d4b078 Address@gxc_gpec13_regs : 0x07d4f078 Address@gxc_gpec14_regs : 0x07d53078 Address@gxc_gpec15_regs : 0x07d57078 Address@gxc_gpec16_regs : 0x07d5b078 Address@gxc_gpec17_regs : 0x07d5f078 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
and_or |
|
|||||||||||||
| 30 - 29 | "00" |
level_edge_event1 |
|
|||||||||||||
| 28 - 27 | "00" |
level_edge_event0 |
|
|||||||||||||
| 26 | 0 |
- |
reserved | |||||||||||||
| 25 - 16 | 0x0 |
jmp_adr |
|
|||||||||||||
| 15 - 8 | "11111111" |
sel1 |
|
|||||||||||||
| 7 - 0 | "11111111" |
sel0 |
|
|||||||||||||
| gpec_pfifo_mask |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0307c Address@gxc_gpec00_regs : 0x07d0307c Address@gxc_gpec01_regs : 0x07d0707c Address@gxc_gpec02_regs : 0x07d0b07c Address@gxc_gpec03_regs : 0x07d0f07c Address@gxc_gpec04_regs : 0x07d1307c Address@gxc_gpec05_regs : 0x07d1707c Address@gxc_gpec06_regs : 0x07d1b07c Address@gxc_gpec07_regs : 0x07d1f07c Address@gxc_gpec10_regs : 0x07d4307c Address@gxc_gpec11_regs : 0x07d4707c Address@gxc_gpec12_regs : 0x07d4b07c Address@gxc_gpec13_regs : 0x07d4f07c Address@gxc_gpec14_regs : 0x07d5307c Address@gxc_gpec15_regs : 0x07d5707c Address@gxc_gpec16_regs : 0x07d5b07c Address@gxc_gpec17_regs : 0x07d5f07c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gpec_pfifo_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03080 Address@gxc_gpec00_regs : 0x07d03080 Address@gxc_gpec01_regs : 0x07d07080 Address@gxc_gpec02_regs : 0x07d0b080 Address@gxc_gpec03_regs : 0x07d0f080 Address@gxc_gpec04_regs : 0x07d13080 Address@gxc_gpec05_regs : 0x07d17080 Address@gxc_gpec06_regs : 0x07d1b080 Address@gxc_gpec07_regs : 0x07d1f080 Address@gxc_gpec10_regs : 0x07d43080 Address@gxc_gpec11_regs : 0x07d47080 Address@gxc_gpec12_regs : 0x07d4b080 Address@gxc_gpec13_regs : 0x07d4f080 Address@gxc_gpec14_regs : 0x07d53080 Address@gxc_gpec15_regs : 0x07d57080 Address@gxc_gpec16_regs : 0x07d5b080 Address@gxc_gpec17_regs : 0x07d5f080 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | ||||||||
| 23 | "0" |
inst |
|
||||||||
| 22 - 20 | "000" |
bucket_sel |
|
||||||||
| 19 | "0" |
set_busy |
|
||||||||
| 18 | "0" |
clr_busy |
|
||||||||
| 17 - 0 | 0x0 |
decrement |
|
||||||||
| gpec_lut_bits |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03084 Address@gxc_gpec00_regs : 0x07d03084 Address@gxc_gpec01_regs : 0x07d07084 Address@gxc_gpec02_regs : 0x07d0b084 Address@gxc_gpec03_regs : 0x07d0f084 Address@gxc_gpec04_regs : 0x07d13084 Address@gxc_gpec05_regs : 0x07d17084 Address@gxc_gpec06_regs : 0x07d1b084 Address@gxc_gpec07_regs : 0x07d1f084 Address@gxc_gpec10_regs : 0x07d43084 Address@gxc_gpec11_regs : 0x07d47084 Address@gxc_gpec12_regs : 0x07d4b084 Address@gxc_gpec13_regs : 0x07d4f084 Address@gxc_gpec14_regs : 0x07d53084 Address@gxc_gpec15_regs : 0x07d57084 Address@gxc_gpec16_regs : 0x07d5b084 Address@gxc_gpec17_regs : 0x07d5f084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
lut_out |
|
|
| 15 - 0 | 0x0 |
lut_in |
|
|
| gpec_crc_data |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03088 Address@gxc_gpec00_regs : 0x07d03088 Address@gxc_gpec01_regs : 0x07d07088 Address@gxc_gpec02_regs : 0x07d0b088 Address@gxc_gpec03_regs : 0x07d0f088 Address@gxc_gpec04_regs : 0x07d13088 Address@gxc_gpec05_regs : 0x07d17088 Address@gxc_gpec06_regs : 0x07d1b088 Address@gxc_gpec07_regs : 0x07d1f088 Address@gxc_gpec10_regs : 0x07d43088 Address@gxc_gpec11_regs : 0x07d47088 Address@gxc_gpec12_regs : 0x07d4b088 Address@gxc_gpec13_regs : 0x07d4f088 Address@gxc_gpec14_regs : 0x07d53088 Address@gxc_gpec15_regs : 0x07d57088 Address@gxc_gpec16_regs : 0x07d5b088 Address@gxc_gpec17_regs : 0x07d5f088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_irq |
|
|||
| W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0308c Address@gxc_gpec00_regs : 0x07d0308c Address@gxc_gpec01_regs : 0x07d0708c Address@gxc_gpec02_regs : 0x07d0b08c Address@gxc_gpec03_regs : 0x07d0f08c Address@gxc_gpec04_regs : 0x07d1308c Address@gxc_gpec05_regs : 0x07d1708c Address@gxc_gpec06_regs : 0x07d1b08c Address@gxc_gpec07_regs : 0x07d1f08c Address@gxc_gpec10_regs : 0x07d4308c Address@gxc_gpec11_regs : 0x07d4708c Address@gxc_gpec12_regs : 0x07d4b08c Address@gxc_gpec13_regs : 0x07d4f08c Address@gxc_gpec14_regs : 0x07d5308c Address@gxc_gpec15_regs : 0x07d5708c Address@gxc_gpec16_regs : 0x07d5b08c Address@gxc_gpec17_regs : 0x07d5f08c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_systime |
|
|||
| R |
Address@gxc_gpec_regs : 0x07c03090 Address@gxc_gpec00_regs : 0x07d03090 Address@gxc_gpec01_regs : 0x07d07090 Address@gxc_gpec02_regs : 0x07d0b090 Address@gxc_gpec03_regs : 0x07d0f090 Address@gxc_gpec04_regs : 0x07d13090 Address@gxc_gpec05_regs : 0x07d17090 Address@gxc_gpec06_regs : 0x07d1b090 Address@gxc_gpec07_regs : 0x07d1f090 Address@gxc_gpec10_regs : 0x07d43090 Address@gxc_gpec11_regs : 0x07d47090 Address@gxc_gpec12_regs : 0x07d4b090 Address@gxc_gpec13_regs : 0x07d4f090 Address@gxc_gpec14_regs : 0x07d53090 Address@gxc_gpec15_regs : 0x07d57090 Address@gxc_gpec16_regs : 0x07d5b090 Address@gxc_gpec17_regs : 0x07d5f090 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gpec_counter |
|
|||
| R |
Address@gxc_gpec_regs : 0x07c03094 Address@gxc_gpec00_regs : 0x07d03094 Address@gxc_gpec01_regs : 0x07d07094 Address@gxc_gpec02_regs : 0x07d0b094 Address@gxc_gpec03_regs : 0x07d0f094 Address@gxc_gpec04_regs : 0x07d13094 Address@gxc_gpec05_regs : 0x07d17094 Address@gxc_gpec06_regs : 0x07d1b094 Address@gxc_gpec07_regs : 0x07d1f094 Address@gxc_gpec10_regs : 0x07d43094 Address@gxc_gpec11_regs : 0x07d47094 Address@gxc_gpec12_regs : 0x07d4b094 Address@gxc_gpec13_regs : 0x07d4f094 Address@gxc_gpec14_regs : 0x07d53094 Address@gxc_gpec15_regs : 0x07d57094 Address@gxc_gpec16_regs : 0x07d5b094 Address@gxc_gpec17_regs : 0x07d5f094 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gpec_fifo_data |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c03098 Address@gxc_gpec00_regs : 0x07d03098 Address@gxc_gpec01_regs : 0x07d07098 Address@gxc_gpec02_regs : 0x07d0b098 Address@gxc_gpec03_regs : 0x07d0f098 Address@gxc_gpec04_regs : 0x07d13098 Address@gxc_gpec05_regs : 0x07d17098 Address@gxc_gpec06_regs : 0x07d1b098 Address@gxc_gpec07_regs : 0x07d1f098 Address@gxc_gpec10_regs : 0x07d43098 Address@gxc_gpec11_regs : 0x07d47098 Address@gxc_gpec12_regs : 0x07d4b098 Address@gxc_gpec13_regs : 0x07d4f098 Address@gxc_gpec14_regs : 0x07d53098 Address@gxc_gpec15_regs : 0x07d57098 Address@gxc_gpec16_regs : 0x07d5b098 Address@gxc_gpec17_regs : 0x07d5f098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fifo_data |
|
|
| gpec_host_req |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c0309c Address@gxc_gpec00_regs : 0x07d0309c Address@gxc_gpec01_regs : 0x07d0709c Address@gxc_gpec02_regs : 0x07d0b09c Address@gxc_gpec03_regs : 0x07d0f09c Address@gxc_gpec04_regs : 0x07d1309c Address@gxc_gpec05_regs : 0x07d1709c Address@gxc_gpec06_regs : 0x07d1b09c Address@gxc_gpec07_regs : 0x07d1f09c Address@gxc_gpec10_regs : 0x07d4309c Address@gxc_gpec11_regs : 0x07d4709c Address@gxc_gpec12_regs : 0x07d4b09c Address@gxc_gpec13_regs : 0x07d4f09c Address@gxc_gpec14_regs : 0x07d5309c Address@gxc_gpec15_regs : 0x07d5709c Address@gxc_gpec16_regs : 0x07d5b09c Address@gxc_gpec17_regs : 0x07d5f09c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_sr0 |
|
|||||||||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030a0 Address@gxc_gpec00_regs : 0x07d030a0 Address@gxc_gpec01_regs : 0x07d070a0 Address@gxc_gpec02_regs : 0x07d0b0a0 Address@gxc_gpec03_regs : 0x07d0f0a0 Address@gxc_gpec04_regs : 0x07d130a0 Address@gxc_gpec05_regs : 0x07d170a0 Address@gxc_gpec06_regs : 0x07d1b0a0 Address@gxc_gpec07_regs : 0x07d1f0a0 Address@gxc_gpec10_regs : 0x07d430a0 Address@gxc_gpec11_regs : 0x07d470a0 Address@gxc_gpec12_regs : 0x07d4b0a0 Address@gxc_gpec13_regs : 0x07d4f0a0 Address@gxc_gpec14_regs : 0x07d530a0 Address@gxc_gpec15_regs : 0x07d570a0 Address@gxc_gpec16_regs : 0x07d5b0a0 Address@gxc_gpec17_regs : 0x07d5f0a0 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR0 |
|
|||||||||||
| gpec_sr1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030a4 Address@gxc_gpec00_regs : 0x07d030a4 Address@gxc_gpec01_regs : 0x07d070a4 Address@gxc_gpec02_regs : 0x07d0b0a4 Address@gxc_gpec03_regs : 0x07d0f0a4 Address@gxc_gpec04_regs : 0x07d130a4 Address@gxc_gpec05_regs : 0x07d170a4 Address@gxc_gpec06_regs : 0x07d1b0a4 Address@gxc_gpec07_regs : 0x07d1f0a4 Address@gxc_gpec10_regs : 0x07d430a4 Address@gxc_gpec11_regs : 0x07d470a4 Address@gxc_gpec12_regs : 0x07d4b0a4 Address@gxc_gpec13_regs : 0x07d4f0a4 Address@gxc_gpec14_regs : 0x07d530a4 Address@gxc_gpec15_regs : 0x07d570a4 Address@gxc_gpec16_regs : 0x07d5b0a4 Address@gxc_gpec17_regs : 0x07d5f0a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR1 |
|
|
| gpec_sr2 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030a8 Address@gxc_gpec00_regs : 0x07d030a8 Address@gxc_gpec01_regs : 0x07d070a8 Address@gxc_gpec02_regs : 0x07d0b0a8 Address@gxc_gpec03_regs : 0x07d0f0a8 Address@gxc_gpec04_regs : 0x07d130a8 Address@gxc_gpec05_regs : 0x07d170a8 Address@gxc_gpec06_regs : 0x07d1b0a8 Address@gxc_gpec07_regs : 0x07d1f0a8 Address@gxc_gpec10_regs : 0x07d430a8 Address@gxc_gpec11_regs : 0x07d470a8 Address@gxc_gpec12_regs : 0x07d4b0a8 Address@gxc_gpec13_regs : 0x07d4f0a8 Address@gxc_gpec14_regs : 0x07d530a8 Address@gxc_gpec15_regs : 0x07d570a8 Address@gxc_gpec16_regs : 0x07d5b0a8 Address@gxc_gpec17_regs : 0x07d5f0a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR2 |
|
|
| gpec_sr3 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030ac Address@gxc_gpec00_regs : 0x07d030ac Address@gxc_gpec01_regs : 0x07d070ac Address@gxc_gpec02_regs : 0x07d0b0ac Address@gxc_gpec03_regs : 0x07d0f0ac Address@gxc_gpec04_regs : 0x07d130ac Address@gxc_gpec05_regs : 0x07d170ac Address@gxc_gpec06_regs : 0x07d1b0ac Address@gxc_gpec07_regs : 0x07d1f0ac Address@gxc_gpec10_regs : 0x07d430ac Address@gxc_gpec11_regs : 0x07d470ac Address@gxc_gpec12_regs : 0x07d4b0ac Address@gxc_gpec13_regs : 0x07d4f0ac Address@gxc_gpec14_regs : 0x07d530ac Address@gxc_gpec15_regs : 0x07d570ac Address@gxc_gpec16_regs : 0x07d5b0ac Address@gxc_gpec17_regs : 0x07d5f0ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR3 |
|
|
| gpec_sr4 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030b0 Address@gxc_gpec00_regs : 0x07d030b0 Address@gxc_gpec01_regs : 0x07d070b0 Address@gxc_gpec02_regs : 0x07d0b0b0 Address@gxc_gpec03_regs : 0x07d0f0b0 Address@gxc_gpec04_regs : 0x07d130b0 Address@gxc_gpec05_regs : 0x07d170b0 Address@gxc_gpec06_regs : 0x07d1b0b0 Address@gxc_gpec07_regs : 0x07d1f0b0 Address@gxc_gpec10_regs : 0x07d430b0 Address@gxc_gpec11_regs : 0x07d470b0 Address@gxc_gpec12_regs : 0x07d4b0b0 Address@gxc_gpec13_regs : 0x07d4f0b0 Address@gxc_gpec14_regs : 0x07d530b0 Address@gxc_gpec15_regs : 0x07d570b0 Address@gxc_gpec16_regs : 0x07d5b0b0 Address@gxc_gpec17_regs : 0x07d5f0b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR4 |
|
|
| gpec_sr5 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030b4 Address@gxc_gpec00_regs : 0x07d030b4 Address@gxc_gpec01_regs : 0x07d070b4 Address@gxc_gpec02_regs : 0x07d0b0b4 Address@gxc_gpec03_regs : 0x07d0f0b4 Address@gxc_gpec04_regs : 0x07d130b4 Address@gxc_gpec05_regs : 0x07d170b4 Address@gxc_gpec06_regs : 0x07d1b0b4 Address@gxc_gpec07_regs : 0x07d1f0b4 Address@gxc_gpec10_regs : 0x07d430b4 Address@gxc_gpec11_regs : 0x07d470b4 Address@gxc_gpec12_regs : 0x07d4b0b4 Address@gxc_gpec13_regs : 0x07d4f0b4 Address@gxc_gpec14_regs : 0x07d530b4 Address@gxc_gpec15_regs : 0x07d570b4 Address@gxc_gpec16_regs : 0x07d5b0b4 Address@gxc_gpec17_regs : 0x07d5f0b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR5 |
|
|
| gpec_sr6 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030b8 Address@gxc_gpec00_regs : 0x07d030b8 Address@gxc_gpec01_regs : 0x07d070b8 Address@gxc_gpec02_regs : 0x07d0b0b8 Address@gxc_gpec03_regs : 0x07d0f0b8 Address@gxc_gpec04_regs : 0x07d130b8 Address@gxc_gpec05_regs : 0x07d170b8 Address@gxc_gpec06_regs : 0x07d1b0b8 Address@gxc_gpec07_regs : 0x07d1f0b8 Address@gxc_gpec10_regs : 0x07d430b8 Address@gxc_gpec11_regs : 0x07d470b8 Address@gxc_gpec12_regs : 0x07d4b0b8 Address@gxc_gpec13_regs : 0x07d4f0b8 Address@gxc_gpec14_regs : 0x07d530b8 Address@gxc_gpec15_regs : 0x07d570b8 Address@gxc_gpec16_regs : 0x07d5b0b8 Address@gxc_gpec17_regs : 0x07d5f0b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR6 |
|
|
| gpec_sr7 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030bc Address@gxc_gpec00_regs : 0x07d030bc Address@gxc_gpec01_regs : 0x07d070bc Address@gxc_gpec02_regs : 0x07d0b0bc Address@gxc_gpec03_regs : 0x07d0f0bc Address@gxc_gpec04_regs : 0x07d130bc Address@gxc_gpec05_regs : 0x07d170bc Address@gxc_gpec06_regs : 0x07d1b0bc Address@gxc_gpec07_regs : 0x07d1f0bc Address@gxc_gpec10_regs : 0x07d430bc Address@gxc_gpec11_regs : 0x07d470bc Address@gxc_gpec12_regs : 0x07d4b0bc Address@gxc_gpec13_regs : 0x07d4f0bc Address@gxc_gpec14_regs : 0x07d530bc Address@gxc_gpec15_regs : 0x07d570bc Address@gxc_gpec16_regs : 0x07d5b0bc Address@gxc_gpec17_regs : 0x07d5f0bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR7 |
|
|
| gpec_sr8 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030c0 Address@gxc_gpec00_regs : 0x07d030c0 Address@gxc_gpec01_regs : 0x07d070c0 Address@gxc_gpec02_regs : 0x07d0b0c0 Address@gxc_gpec03_regs : 0x07d0f0c0 Address@gxc_gpec04_regs : 0x07d130c0 Address@gxc_gpec05_regs : 0x07d170c0 Address@gxc_gpec06_regs : 0x07d1b0c0 Address@gxc_gpec07_regs : 0x07d1f0c0 Address@gxc_gpec10_regs : 0x07d430c0 Address@gxc_gpec11_regs : 0x07d470c0 Address@gxc_gpec12_regs : 0x07d4b0c0 Address@gxc_gpec13_regs : 0x07d4f0c0 Address@gxc_gpec14_regs : 0x07d530c0 Address@gxc_gpec15_regs : 0x07d570c0 Address@gxc_gpec16_regs : 0x07d5b0c0 Address@gxc_gpec17_regs : 0x07d5f0c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR8 |
|
|
| gpec_sr9 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030c4 Address@gxc_gpec00_regs : 0x07d030c4 Address@gxc_gpec01_regs : 0x07d070c4 Address@gxc_gpec02_regs : 0x07d0b0c4 Address@gxc_gpec03_regs : 0x07d0f0c4 Address@gxc_gpec04_regs : 0x07d130c4 Address@gxc_gpec05_regs : 0x07d170c4 Address@gxc_gpec06_regs : 0x07d1b0c4 Address@gxc_gpec07_regs : 0x07d1f0c4 Address@gxc_gpec10_regs : 0x07d430c4 Address@gxc_gpec11_regs : 0x07d470c4 Address@gxc_gpec12_regs : 0x07d4b0c4 Address@gxc_gpec13_regs : 0x07d4f0c4 Address@gxc_gpec14_regs : 0x07d530c4 Address@gxc_gpec15_regs : 0x07d570c4 Address@gxc_gpec16_regs : 0x07d5b0c4 Address@gxc_gpec17_regs : 0x07d5f0c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR9 |
|
|
| gpec_sr10 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030c8 Address@gxc_gpec00_regs : 0x07d030c8 Address@gxc_gpec01_regs : 0x07d070c8 Address@gxc_gpec02_regs : 0x07d0b0c8 Address@gxc_gpec03_regs : 0x07d0f0c8 Address@gxc_gpec04_regs : 0x07d130c8 Address@gxc_gpec05_regs : 0x07d170c8 Address@gxc_gpec06_regs : 0x07d1b0c8 Address@gxc_gpec07_regs : 0x07d1f0c8 Address@gxc_gpec10_regs : 0x07d430c8 Address@gxc_gpec11_regs : 0x07d470c8 Address@gxc_gpec12_regs : 0x07d4b0c8 Address@gxc_gpec13_regs : 0x07d4f0c8 Address@gxc_gpec14_regs : 0x07d530c8 Address@gxc_gpec15_regs : 0x07d570c8 Address@gxc_gpec16_regs : 0x07d5b0c8 Address@gxc_gpec17_regs : 0x07d5f0c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR10 |
|
|
| gpec_sr11 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030cc Address@gxc_gpec00_regs : 0x07d030cc Address@gxc_gpec01_regs : 0x07d070cc Address@gxc_gpec02_regs : 0x07d0b0cc Address@gxc_gpec03_regs : 0x07d0f0cc Address@gxc_gpec04_regs : 0x07d130cc Address@gxc_gpec05_regs : 0x07d170cc Address@gxc_gpec06_regs : 0x07d1b0cc Address@gxc_gpec07_regs : 0x07d1f0cc Address@gxc_gpec10_regs : 0x07d430cc Address@gxc_gpec11_regs : 0x07d470cc Address@gxc_gpec12_regs : 0x07d4b0cc Address@gxc_gpec13_regs : 0x07d4f0cc Address@gxc_gpec14_regs : 0x07d530cc Address@gxc_gpec15_regs : 0x07d570cc Address@gxc_gpec16_regs : 0x07d5b0cc Address@gxc_gpec17_regs : 0x07d5f0cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR11 |
|
|
| gpec_sr12 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030d0 Address@gxc_gpec00_regs : 0x07d030d0 Address@gxc_gpec01_regs : 0x07d070d0 Address@gxc_gpec02_regs : 0x07d0b0d0 Address@gxc_gpec03_regs : 0x07d0f0d0 Address@gxc_gpec04_regs : 0x07d130d0 Address@gxc_gpec05_regs : 0x07d170d0 Address@gxc_gpec06_regs : 0x07d1b0d0 Address@gxc_gpec07_regs : 0x07d1f0d0 Address@gxc_gpec10_regs : 0x07d430d0 Address@gxc_gpec11_regs : 0x07d470d0 Address@gxc_gpec12_regs : 0x07d4b0d0 Address@gxc_gpec13_regs : 0x07d4f0d0 Address@gxc_gpec14_regs : 0x07d530d0 Address@gxc_gpec15_regs : 0x07d570d0 Address@gxc_gpec16_regs : 0x07d5b0d0 Address@gxc_gpec17_regs : 0x07d5f0d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR12 |
|
|
| gpec_sr13 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030d4 Address@gxc_gpec00_regs : 0x07d030d4 Address@gxc_gpec01_regs : 0x07d070d4 Address@gxc_gpec02_regs : 0x07d0b0d4 Address@gxc_gpec03_regs : 0x07d0f0d4 Address@gxc_gpec04_regs : 0x07d130d4 Address@gxc_gpec05_regs : 0x07d170d4 Address@gxc_gpec06_regs : 0x07d1b0d4 Address@gxc_gpec07_regs : 0x07d1f0d4 Address@gxc_gpec10_regs : 0x07d430d4 Address@gxc_gpec11_regs : 0x07d470d4 Address@gxc_gpec12_regs : 0x07d4b0d4 Address@gxc_gpec13_regs : 0x07d4f0d4 Address@gxc_gpec14_regs : 0x07d530d4 Address@gxc_gpec15_regs : 0x07d570d4 Address@gxc_gpec16_regs : 0x07d5b0d4 Address@gxc_gpec17_regs : 0x07d5f0d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR13 |
|
|
| gpec_sr14 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030d8 Address@gxc_gpec00_regs : 0x07d030d8 Address@gxc_gpec01_regs : 0x07d070d8 Address@gxc_gpec02_regs : 0x07d0b0d8 Address@gxc_gpec03_regs : 0x07d0f0d8 Address@gxc_gpec04_regs : 0x07d130d8 Address@gxc_gpec05_regs : 0x07d170d8 Address@gxc_gpec06_regs : 0x07d1b0d8 Address@gxc_gpec07_regs : 0x07d1f0d8 Address@gxc_gpec10_regs : 0x07d430d8 Address@gxc_gpec11_regs : 0x07d470d8 Address@gxc_gpec12_regs : 0x07d4b0d8 Address@gxc_gpec13_regs : 0x07d4f0d8 Address@gxc_gpec14_regs : 0x07d530d8 Address@gxc_gpec15_regs : 0x07d570d8 Address@gxc_gpec16_regs : 0x07d5b0d8 Address@gxc_gpec17_regs : 0x07d5f0d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR14 |
|
|
| gpec_sr15 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030dc Address@gxc_gpec00_regs : 0x07d030dc Address@gxc_gpec01_regs : 0x07d070dc Address@gxc_gpec02_regs : 0x07d0b0dc Address@gxc_gpec03_regs : 0x07d0f0dc Address@gxc_gpec04_regs : 0x07d130dc Address@gxc_gpec05_regs : 0x07d170dc Address@gxc_gpec06_regs : 0x07d1b0dc Address@gxc_gpec07_regs : 0x07d1f0dc Address@gxc_gpec10_regs : 0x07d430dc Address@gxc_gpec11_regs : 0x07d470dc Address@gxc_gpec12_regs : 0x07d4b0dc Address@gxc_gpec13_regs : 0x07d4f0dc Address@gxc_gpec14_regs : 0x07d530dc Address@gxc_gpec15_regs : 0x07d570dc Address@gxc_gpec16_regs : 0x07d5b0dc Address@gxc_gpec17_regs : 0x07d5f0dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SR15 |
|
|
| gpec_statcfg0 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030e0 Address@gxc_gpec00_regs : 0x07d030e0 Address@gxc_gpec01_regs : 0x07d070e0 Address@gxc_gpec02_regs : 0x07d0b0e0 Address@gxc_gpec03_regs : 0x07d0f0e0 Address@gxc_gpec04_regs : 0x07d130e0 Address@gxc_gpec05_regs : 0x07d170e0 Address@gxc_gpec06_regs : 0x07d1b0e0 Address@gxc_gpec07_regs : 0x07d1f0e0 Address@gxc_gpec10_regs : 0x07d430e0 Address@gxc_gpec11_regs : 0x07d470e0 Address@gxc_gpec12_regs : 0x07d4b0e0 Address@gxc_gpec13_regs : 0x07d4f0e0 Address@gxc_gpec14_regs : 0x07d530e0 Address@gxc_gpec15_regs : 0x07d570e0 Address@gxc_gpec16_regs : 0x07d5b0e0 Address@gxc_gpec17_regs : 0x07d5f0e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_statcfg1 |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030e4 Address@gxc_gpec00_regs : 0x07d030e4 Address@gxc_gpec01_regs : 0x07d070e4 Address@gxc_gpec02_regs : 0x07d0b0e4 Address@gxc_gpec03_regs : 0x07d0f0e4 Address@gxc_gpec04_regs : 0x07d130e4 Address@gxc_gpec05_regs : 0x07d170e4 Address@gxc_gpec06_regs : 0x07d1b0e4 Address@gxc_gpec07_regs : 0x07d1f0e4 Address@gxc_gpec10_regs : 0x07d430e4 Address@gxc_gpec11_regs : 0x07d470e4 Address@gxc_gpec12_regs : 0x07d4b0e4 Address@gxc_gpec13_regs : 0x07d4f0e4 Address@gxc_gpec14_regs : 0x07d530e4 Address@gxc_gpec15_regs : 0x07d570e4 Address@gxc_gpec16_regs : 0x07d5b0e4 Address@gxc_gpec17_regs : 0x07d5f0e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpec_axi_wr_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030e8 Address@gxc_gpec00_regs : 0x07d030e8 Address@gxc_gpec01_regs : 0x07d070e8 Address@gxc_gpec02_regs : 0x07d0b0e8 Address@gxc_gpec03_regs : 0x07d0f0e8 Address@gxc_gpec04_regs : 0x07d130e8 Address@gxc_gpec05_regs : 0x07d170e8 Address@gxc_gpec06_regs : 0x07d1b0e8 Address@gxc_gpec07_regs : 0x07d1f0e8 Address@gxc_gpec10_regs : 0x07d430e8 Address@gxc_gpec11_regs : 0x07d470e8 Address@gxc_gpec12_regs : 0x07d4b0e8 Address@gxc_gpec13_regs : 0x07d4f0e8 Address@gxc_gpec14_regs : 0x07d530e8 Address@gxc_gpec15_regs : 0x07d570e8 Address@gxc_gpec16_regs : 0x07d5b0e8 Address@gxc_gpec17_regs : 0x07d5f0e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
axi_wr_snrdy |
|
|
| 30 - 28 | "000" |
axi_wr_cfg |
|
|
| 27 - 0 | 0x0 |
axi_wr_addr |
|
|
| gpec_axi_rd_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030ec Address@gxc_gpec00_regs : 0x07d030ec Address@gxc_gpec01_regs : 0x07d070ec Address@gxc_gpec02_regs : 0x07d0b0ec Address@gxc_gpec03_regs : 0x07d0f0ec Address@gxc_gpec04_regs : 0x07d130ec Address@gxc_gpec05_regs : 0x07d170ec Address@gxc_gpec06_regs : 0x07d1b0ec Address@gxc_gpec07_regs : 0x07d1f0ec Address@gxc_gpec10_regs : 0x07d430ec Address@gxc_gpec11_regs : 0x07d470ec Address@gxc_gpec12_regs : 0x07d4b0ec Address@gxc_gpec13_regs : 0x07d4f0ec Address@gxc_gpec14_regs : 0x07d530ec Address@gxc_gpec15_regs : 0x07d570ec Address@gxc_gpec16_regs : 0x07d5b0ec Address@gxc_gpec17_regs : 0x07d5f0ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
axi_rd_snrdy |
|
|
| 30 - 28 | "000" |
axi_rd_cfg |
|
|
| 27 - 0 | 0x0 |
axi_rd_addr |
|
|
| gpec_urtx0 |
|
||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030f0 Address@gxc_gpec00_regs : 0x07d030f0 Address@gxc_gpec01_regs : 0x07d070f0 Address@gxc_gpec02_regs : 0x07d0b0f0 Address@gxc_gpec03_regs : 0x07d0f0f0 Address@gxc_gpec04_regs : 0x07d130f0 Address@gxc_gpec05_regs : 0x07d170f0 Address@gxc_gpec06_regs : 0x07d1b0f0 Address@gxc_gpec07_regs : 0x07d1f0f0 Address@gxc_gpec10_regs : 0x07d430f0 Address@gxc_gpec11_regs : 0x07d470f0 Address@gxc_gpec12_regs : 0x07d4b0f0 Address@gxc_gpec13_regs : 0x07d4f0f0 Address@gxc_gpec14_regs : 0x07d530f0 Address@gxc_gpec15_regs : 0x07d570f0 Address@gxc_gpec16_regs : 0x07d5b0f0 Address@gxc_gpec17_regs : 0x07d5f0f0 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
urtx0 |
|
||||
| gpec_urtx1 |
|
||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030f4 Address@gxc_gpec00_regs : 0x07d030f4 Address@gxc_gpec01_regs : 0x07d070f4 Address@gxc_gpec02_regs : 0x07d0b0f4 Address@gxc_gpec03_regs : 0x07d0f0f4 Address@gxc_gpec04_regs : 0x07d130f4 Address@gxc_gpec05_regs : 0x07d170f4 Address@gxc_gpec06_regs : 0x07d1b0f4 Address@gxc_gpec07_regs : 0x07d1f0f4 Address@gxc_gpec10_regs : 0x07d430f4 Address@gxc_gpec11_regs : 0x07d470f4 Address@gxc_gpec12_regs : 0x07d4b0f4 Address@gxc_gpec13_regs : 0x07d4f0f4 Address@gxc_gpec14_regs : 0x07d530f4 Address@gxc_gpec15_regs : 0x07d570f4 Address@gxc_gpec16_regs : 0x07d5b0f4 Address@gxc_gpec17_regs : 0x07d5f0f4 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
urtx1 |
|
||||
| gpec_urtxe0 |
|
||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030f8 Address@gxc_gpec00_regs : 0x07d030f8 Address@gxc_gpec01_regs : 0x07d070f8 Address@gxc_gpec02_regs : 0x07d0b0f8 Address@gxc_gpec03_regs : 0x07d0f0f8 Address@gxc_gpec04_regs : 0x07d130f8 Address@gxc_gpec05_regs : 0x07d170f8 Address@gxc_gpec06_regs : 0x07d1b0f8 Address@gxc_gpec07_regs : 0x07d1f0f8 Address@gxc_gpec10_regs : 0x07d430f8 Address@gxc_gpec11_regs : 0x07d470f8 Address@gxc_gpec12_regs : 0x07d4b0f8 Address@gxc_gpec13_regs : 0x07d4f0f8 Address@gxc_gpec14_regs : 0x07d530f8 Address@gxc_gpec15_regs : 0x07d570f8 Address@gxc_gpec16_regs : 0x07d5b0f8 Address@gxc_gpec17_regs : 0x07d5f0f8 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
urtxe0 |
|
||||
| gpec_urtxe1 |
|
||||||
| R/W |
0x00000000 |
Address@gxc_gpec_regs : 0x07c030fc Address@gxc_gpec00_regs : 0x07d030fc Address@gxc_gpec01_regs : 0x07d070fc Address@gxc_gpec02_regs : 0x07d0b0fc Address@gxc_gpec03_regs : 0x07d0f0fc Address@gxc_gpec04_regs : 0x07d130fc Address@gxc_gpec05_regs : 0x07d170fc Address@gxc_gpec06_regs : 0x07d1b0fc Address@gxc_gpec07_regs : 0x07d1f0fc Address@gxc_gpec10_regs : 0x07d430fc Address@gxc_gpec11_regs : 0x07d470fc Address@gxc_gpec12_regs : 0x07d4b0fc Address@gxc_gpec13_regs : 0x07d4f0fc Address@gxc_gpec14_regs : 0x07d530fc Address@gxc_gpec15_regs : 0x07d570fc Address@gxc_gpec16_regs : 0x07d5b0fc Address@gxc_gpec17_regs : 0x07d5f0fc |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
urtxe1 |
|
||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | intram128_base |
| 1-7ffe | 4-1fff8 | - | reserved |
| 7fff | 1fffc | R/W | intram128_end |
| intram128_base |
|
|||
| R/W |
0x00000000 |
Address@intram0_gxc : 0x07c20000 Address@intram1_gxc : 0x07c40000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
intram128_base | ||
| intram128_end | |||
| R/W |
0x00000000 |
Address@intram0_gxc : 0x07c3fffc Address@intram1_gxc : 0x07c5fffc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
intram128_end | |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | intram64_base |
| 1-3ffe | 4-fff8 | - | reserved |
| 3fff | fffc | R/W | intram64_end |
| intram64_base |
|
|||
| R/W |
0x00000000 |
Address@intram2_gxc : 0x07c60000 Address@intram3_gxc : 0x07c70000 Address@mot_intram0 : 0x48000000 Address@mot_intram1 : 0x48010000 Address@mot_intram2 : 0x48020000 Address@mot_intram3 : 0x48030000 Address@sms_rx_ram : 0x60000000 Address@sms_tx_ram : 0x60040000 Address@sms_ac_ram : 0x60080000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
intram64_base | ||
| intram64_end | |||
| R/W |
0x00000000 |
Address@intram2_gxc : 0x07c6fffc Address@intram3_gxc : 0x07c7fffc Address@mot_intram0 : 0x4800fffc Address@mot_intram1 : 0x4801fffc Address@mot_intram2 : 0x4802fffc Address@mot_intram3 : 0x4803fffc Address@sms_rx_ram : 0x6000fffc Address@sms_tx_ram : 0x6004fffc Address@sms_ac_ram : 0x6008fffc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
intram64_end | |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_pfifo_start |
| 1-e | 4-38 | - | reserved |
| f | 3c | - | gxc_pfifo_end |
| 10 | 40 | R/W | gxc_pfifo_reset |
| 11 | 44 | R | gxc_pfifo_full |
| 12 | 48 | R | gxc_pfifo_empty |
| 13 | 4c | R | gxc_pfifo_overflow |
| 14 | 50 | R | gxc_pfifo_underrun |
| 15 | 54 | R/W | gxc_pfifo_avoid_ufl |
| 16 | 58 | R/W | gxc_pfifo_avoid_ofl |
| 17 | 5c | R/W | gxc_pfifo_nok |
| 18-1f | 60-7c | - | reserved |
| 20 | 80 | R | gxc_pfifo_fill_level_start |
| 21-2e | 84-b8 | - | reserved |
| 2f | bc | - | gxc_pfifo_fill_level_end |
| 30-3f | c0-fc | - | reserved |
| gxc_pfifo_start |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_pfifo0 : 0x07d22200 Address@gxc_pfifo1 : 0x07d22300 Address@gxc_pfifo2 : 0x07d62200 Address@gxc_pfifo3 : 0x07d62300 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
fifo_data |
|
|||||
| gxc_pfifo_end | |||
|
Address@gxc_pfifo0 : 0x07d2223c Address@gxc_pfifo1 : 0x07d2233c Address@gxc_pfifo2 : 0x07d6223c Address@gxc_pfifo3 : 0x07d6233c |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gxc_pfifo_end | ||
| gxc_pfifo_reset |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_pfifo0 : 0x07d22240 Address@gxc_pfifo1 : 0x07d22340 Address@gxc_pfifo2 : 0x07d62240 Address@gxc_pfifo3 : 0x07d62340 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||
| 15 - 0 | 0x0 |
reset_fifo |
|
|||||
| gxc_pfifo_full |
|
|||
| R |
Address@gxc_pfifo0 : 0x07d22244 Address@gxc_pfifo1 : 0x07d22344 Address@gxc_pfifo2 : 0x07d62244 Address@gxc_pfifo3 : 0x07d62344 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | fifo_full |
|
||
| gxc_pfifo_empty |
|
|||
| R |
Address@gxc_pfifo0 : 0x07d22248 Address@gxc_pfifo1 : 0x07d22348 Address@gxc_pfifo2 : 0x07d62248 Address@gxc_pfifo3 : 0x07d62348 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | fifo_empty |
|
||
| gxc_pfifo_overflow |
|
|||
| R |
Address@gxc_pfifo0 : 0x07d2224c Address@gxc_pfifo1 : 0x07d2234c Address@gxc_pfifo2 : 0x07d6224c Address@gxc_pfifo3 : 0x07d6234c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | fifo_overflow |
|
||
| gxc_pfifo_underrun |
|
|||
| R |
Address@gxc_pfifo0 : 0x07d22250 Address@gxc_pfifo1 : 0x07d22350 Address@gxc_pfifo2 : 0x07d62250 Address@gxc_pfifo3 : 0x07d62350 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | fifo_underrun |
|
||
| gxc_pfifo_avoid_ufl |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0 : 0x07d22254 Address@gxc_pfifo1 : 0x07d22354 Address@gxc_pfifo2 : 0x07d62254 Address@gxc_pfifo3 : 0x07d62354 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gxc_pfifo_avoid_ofl |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0 : 0x07d22258 Address@gxc_pfifo1 : 0x07d22358 Address@gxc_pfifo2 : 0x07d62258 Address@gxc_pfifo3 : 0x07d62358 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gxc_pfifo_nok |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0 : 0x07d2225c Address@gxc_pfifo1 : 0x07d2235c Address@gxc_pfifo2 : 0x07d6225c Address@gxc_pfifo3 : 0x07d6235c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |
| 16 | "0" |
cpu |
|
|
| 15 | "0" |
gpec17 |
|
|
| 14 | "0" |
gpec16 |
|
|
| 13 | "0" |
gpec15 |
|
|
| 12 | "0" |
gpec14 |
|
|
| 11 | "0" |
gpec13 |
|
|
| 10 | "0" |
gpec12 |
|
|
| 9 | "0" |
gpec11 |
|
|
| 8 | "0" |
gpec10 |
|
|
| 7 | "0" |
gpec07 |
|
|
| 6 | "0" |
gpec06 |
|
|
| 5 | "0" |
gpec05 |
|
|
| 4 | "0" |
gpec04 |
|
|
| 3 | "0" |
gpec03 |
|
|
| 2 | "0" |
gpec02 |
|
|
| 1 | "0" |
gpec01 |
|
|
| 0 | "0" |
gpec00 |
|
|
| gxc_pfifo_fill_level_start |
|
|||
| R |
Address@gxc_pfifo0 : 0x07d22280 Address@gxc_pfifo1 : 0x07d22380 Address@gxc_pfifo2 : 0x07d62280 Address@gxc_pfifo3 : 0x07d62380 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 10 | - |
reserved | ||
| 9 - 0 | fill_level |
|
||
| gxc_pfifo_fill_level_end | |||
|
Address@gxc_pfifo0 : 0x07d222bc Address@gxc_pfifo1 : 0x07d223bc Address@gxc_pfifo2 : 0x07d622bc Address@gxc_pfifo3 : 0x07d623bc |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | gxc_pfifo_fill_level_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_gpec_irq_gpec_irq_raw |
| 1 | 4 | R/W | gxc_gpec_irq_gpec_irq_masked |
| 2 | 8 | R/W | gxc_gpec_irq_gpec_irq_mask_set |
| 3 | c | R/W | gxc_gpec_irq_gpec_irq_mask_rst |
| 4 | 10 | R/W | gxc_gpec_irq_host_req_raw |
| 5 | 14 | R/W | gxc_gpec_irq_host_req_mask |
| 6-7 | 18-1c | - | reserved |
| gxc_gpec_irq_gpec_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec0_irq : 0x07d22400 Address@gxc_gpec1_irq : 0x07d62400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
gpec_irq31 |
|
|
| 30 | "0" |
gpec_irq30 |
|
|
| 29 | "0" |
gpec_irq29 |
|
|
| 28 | "0" |
gpec_irq28 |
|
|
| 27 | "0" |
gpec_irq27 |
|
|
| 26 | "0" |
gpec_irq26 |
|
|
| 25 | "0" |
gpec_irq25 |
|
|
| 24 | "0" |
gpec_irq24 |
|
|
| 23 | "0" |
gpec_irq23 |
|
|
| 22 | "0" |
gpec_irq22 |
|
|
| 21 | "0" |
gpec_irq21 |
|
|
| 20 | "0" |
gpec_irq20 |
|
|
| 19 | "0" |
gpec_irq19 |
|
|
| 18 | "0" |
gpec_irq18 |
|
|
| 17 | "0" |
gpec_irq17 |
|
|
| 16 | "0" |
gpec_irq16 |
|
|
| 15 | "0" |
gpec_irq15 |
|
|
| 14 | "0" |
gpec_irq14 |
|
|
| 13 | "0" |
gpec_irq13 |
|
|
| 12 | "0" |
gpec_irq12 |
|
|
| 11 | "0" |
gpec_irq11 |
|
|
| 10 | "0" |
gpec_irq10 |
|
|
| 9 | "0" |
gpec_irq9 |
|
|
| 8 | "0" |
gpec_irq8 |
|
|
| 7 | "0" |
gpec_irq7 |
|
|
| 6 | "0" |
gpec_irq6 |
|
|
| 5 | "0" |
gpec_irq5 |
|
|
| 4 | "0" |
gpec_irq4 |
|
|
| 3 | "0" |
gpec_irq3 |
|
|
| 2 | "0" |
gpec_irq2 |
|
|
| 1 | "0" |
gpec_irq1 |
|
|
| 0 | "0" |
gpec_irq0 |
|
|
| gxc_gpec_irq_gpec_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec0_irq : 0x07d22404 Address@gxc_gpec1_irq : 0x07d62404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
gpec_irq31 |
|
|
| 30 | "0" |
gpec_irq30 |
|
|
| 29 | "0" |
gpec_irq29 |
|
|
| 28 | "0" |
gpec_irq28 |
|
|
| 27 | "0" |
gpec_irq27 |
|
|
| 26 | "0" |
gpec_irq26 |
|
|
| 25 | "0" |
gpec_irq25 |
|
|
| 24 | "0" |
gpec_irq24 |
|
|
| 23 | "0" |
gpec_irq23 |
|
|
| 22 | "0" |
gpec_irq22 |
|
|
| 21 | "0" |
gpec_irq21 |
|
|
| 20 | "0" |
gpec_irq20 |
|
|
| 19 | "0" |
gpec_irq19 |
|
|
| 18 | "0" |
gpec_irq18 |
|
|
| 17 | "0" |
gpec_irq17 |
|
|
| 16 | "0" |
gpec_irq16 |
|
|
| 15 | "0" |
gpec_irq15 |
|
|
| 14 | "0" |
gpec_irq14 |
|
|
| 13 | "0" |
gpec_irq13 |
|
|
| 12 | "0" |
gpec_irq12 |
|
|
| 11 | "0" |
gpec_irq11 |
|
|
| 10 | "0" |
gpec_irq10 |
|
|
| 9 | "0" |
gpec_irq9 |
|
|
| 8 | "0" |
gpec_irq8 |
|
|
| 7 | "0" |
gpec_irq7 |
|
|
| 6 | "0" |
gpec_irq6 |
|
|
| 5 | "0" |
gpec_irq5 |
|
|
| 4 | "0" |
gpec_irq4 |
|
|
| 3 | "0" |
gpec_irq3 |
|
|
| 2 | "0" |
gpec_irq2 |
|
|
| 1 | "0" |
gpec_irq1 |
|
|
| 0 | "0" |
gpec_irq0 |
|
|
| gxc_gpec_irq_gpec_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec0_irq : 0x07d22408 Address@gxc_gpec1_irq : 0x07d62408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
gpec_irq31 |
|
|
| 30 | "0" |
gpec_irq30 |
|
|
| 29 | "0" |
gpec_irq29 |
|
|
| 28 | "0" |
gpec_irq28 |
|
|
| 27 | "0" |
gpec_irq27 |
|
|
| 26 | "0" |
gpec_irq26 |
|
|
| 25 | "0" |
gpec_irq25 |
|
|
| 24 | "0" |
gpec_irq24 |
|
|
| 23 | "0" |
gpec_irq23 |
|
|
| 22 | "0" |
gpec_irq22 |
|
|
| 21 | "0" |
gpec_irq21 |
|
|
| 20 | "0" |
gpec_irq20 |
|
|
| 19 | "0" |
gpec_irq19 |
|
|
| 18 | "0" |
gpec_irq18 |
|
|
| 17 | "0" |
gpec_irq17 |
|
|
| 16 | "0" |
gpec_irq16 |
|
|
| 15 | "0" |
gpec_irq15 |
|
|
| 14 | "0" |
gpec_irq14 |
|
|
| 13 | "0" |
gpec_irq13 |
|
|
| 12 | "0" |
gpec_irq12 |
|
|
| 11 | "0" |
gpec_irq11 |
|
|
| 10 | "0" |
gpec_irq10 |
|
|
| 9 | "0" |
gpec_irq9 |
|
|
| 8 | "0" |
gpec_irq8 |
|
|
| 7 | "0" |
gpec_irq7 |
|
|
| 6 | "0" |
gpec_irq6 |
|
|
| 5 | "0" |
gpec_irq5 |
|
|
| 4 | "0" |
gpec_irq4 |
|
|
| 3 | "0" |
gpec_irq3 |
|
|
| 2 | "0" |
gpec_irq2 |
|
|
| 1 | "0" |
gpec_irq1 |
|
|
| 0 | "0" |
gpec_irq0 |
|
|
| gxc_gpec_irq_gpec_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@gxc_gpec0_irq : 0x07d2240c Address@gxc_gpec1_irq : 0x07d6240c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
gpec_irq31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
gpec_irq30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
gpec_irq29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
gpec_irq28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
gpec_irq27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
gpec_irq26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
gpec_irq25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
gpec_irq24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
gpec_irq23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
gpec_irq22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
gpec_irq21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
gpec_irq20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
gpec_irq19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
gpec_irq18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
gpec_irq17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
gpec_irq16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpec_irq15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpec_irq14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpec_irq13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpec_irq12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpec_irq11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpec_irq10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpec_irq9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpec_irq8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpec_irq7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpec_irq6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpec_irq5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpec_irq4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpec_irq3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpec_irq2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpec_irq1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpec_irq0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gxc_gpec_irq_host_req_raw |
|
|||
| R/W |
0x00000000 |
Address@gxc_gpec0_irq : 0x07d22410 Address@gxc_gpec1_irq : 0x07d62410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
||
| gxc_gpec_irq_host_req_mask |
|
|||
| R/W |
0xffffffff |
Address@gxc_gpec0_irq : 0x07d22414 Address@gxc_gpec1_irq : 0x07d62414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0xffffffff |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_sr_sr0 |
| 1 | 4 | R/W | gxc_sr_sr1 |
| 2 | 8 | R/W | gxc_sr_sr2 |
| 3 | c | R/W | gxc_sr_sr3 |
| 4 | 10 | R/W | gxc_sr_sr4 |
| 5 | 14 | R/W | gxc_sr_sr5 |
| 6 | 18 | R/W | gxc_sr_sr6 |
| 7 | 1c | R/W | gxc_sr_sr7 |
| 8 | 20 | R/W | gxc_sr_sr8 |
| 9 | 24 | R/W | gxc_sr_sr9 |
| a | 28 | R/W | gxc_sr_sr10 |
| b | 2c | R/W | gxc_sr_sr11 |
| c | 30 | R/W | gxc_sr_sr12 |
| d | 34 | R/W | gxc_sr_sr13 |
| e | 38 | R/W | gxc_sr_sr14 |
| f | 3c | R/W | gxc_sr_sr15 |
| 10 | 40 | R/W | gxc_sr_statcfg0 |
| 11 | 44 | R/W | gxc_sr_statcfg1 |
| 12 | 48 | R/W | gxc_sr_stat_bits |
| 13 | 4c | R/W | gxc_sr_lut_bits |
| 14 | 50 | R/W | gxc_sr_lut_cfg0 |
| 15 | 54 | R/W | gxc_sr_lut_cfg1 |
| 16 | 58 | R/W | gxc_sr_lut_cfg2 |
| 17 | 5c | R/W | gxc_sr_lut_cfg3 |
| 18 | 60 | R/W | gxc_sr_lut_cfg4 |
| 19 | 64 | R/W | gxc_sr_lut_cfg5 |
| 1a | 68 | R/W | gxc_sr_lut_cfg6 |
| 1b | 6c | R/W | gxc_sr_lut_cfg7 |
| 1c | 70 | R/W | gxc_sr_lut_cfg8 |
| 1d | 74 | R/W | gxc_sr_lut_cfg9 |
| 1e | 78 | R/W | gxc_sr_lut_cfg10 |
| 1f | 7c | R/W | gxc_sr_lut_cfg11 |
| 20 | 80 | R/W | gxc_sr_lut_cfg12 |
| 21 | 84 | R/W | gxc_sr_lut_cfg13 |
| 22 | 88 | R/W | gxc_sr_lut_cfg14 |
| 23 | 8c | R/W | gxc_sr_lut_cfg15 |
| 24-3f | 90-fc | - | reserved |
| gxc_sr_sr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6250c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr5 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr6 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62518 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr7 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6251c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr8 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr9 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr10 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr11 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6252c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr12 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr13 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr14 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62538 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_sr15 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6253c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sr_statcfg0 |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x07d62540 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||
| 30 | "0" |
lmo_link_and_n_eld_bad_link |
|
|||||||
| 29 | "0" |
dr_err_or_crx_err_or_fcr_err |
|
|||||||
| 28 | "0" |
hdx1000 |
|
|||||||
| 27 | "0" |
link_mode_out_duplex |
|
|||||||
| 26 | "0" |
link_mode_out_link |
|
|||||||
| 25 - 24 | "00" |
link_mode_out_speed |
|
|||||||
| 23 | "0" |
utxe_empty |
|
|||||||
| 22 | "0" |
utxe_nxt |
|
|||||||
| 21 | "0" |
urxe_bit32 |
|
|||||||
| 20 | "0" |
urxe_rdy |
|
|||||||
| 19 | "0" |
utx_empty |
|
|||||||
| 18 | "0" |
utx_nxt |
|
|||||||
| 17 | "0" |
urx_bit32 |
|
|||||||
| 16 | "0" |
urx_rdy |
|
|||||||
| 15 | 0 |
- |
reserved | |||||||
| 14 | "0" |
eld_bad_link |
|
|||||||
| 13 | "0" |
utxe_ufl |
|
|||||||
| 12 | "0" |
urxe_ovf |
|
|||||||
| 11 | "0" |
utx_ufl |
|
|||||||
| 10 | "0" |
urx_ovf |
|
|||||||
| 9 - 8 | 0 |
- |
reserved | |||||||
| 7 | "0" |
gpio3_oe |
|
|||||||
| 6 | "0" |
gpio2_oe |
|
|||||||
| 5 | "0" |
gpio1_oe |
|
|||||||
| 4 | "0" |
gpio0_oe |
|
|||||||
| 3 | "0" |
gpio3 |
|
|||||||
| 2 | "0" |
gpio2 |
|
|||||||
| 1 | "0" |
gpio1 |
|
|||||||
| 0 | "0" |
gpio0 |
|
|||||||
| gxc_sr_statcfg1 |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x07d62544 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||||
| 30 | "0" |
lmo_link_and_n_eld_bad_link |
|
|||||||
| 29 | "0" |
dr_err_or_crx_err_or_fcr_err |
|
|||||||
| 28 | "0" |
hdx1000 |
|
|||||||
| 27 | "0" |
link_mode_out_duplex |
|
|||||||
| 26 | "0" |
link_mode_out_link |
|
|||||||
| 25 - 24 | "00" |
link_mode_out_speed |
|
|||||||
| 23 | "0" |
utxe_empty |
|
|||||||
| 22 | "0" |
utxe_nxt |
|
|||||||
| 21 | "0" |
urxe_bit32 |
|
|||||||
| 20 | "0" |
urxe_rdy |
|
|||||||
| 19 | "0" |
utx_empty |
|
|||||||
| 18 | "0" |
utx_nxt |
|
|||||||
| 17 | "0" |
urx_bit32 |
|
|||||||
| 16 | "0" |
urx_rdy |
|
|||||||
| 15 | 0 |
- |
reserved | |||||||
| 14 | "0" |
eld_bad_link |
|
|||||||
| 13 | "0" |
utxe_ufl |
|
|||||||
| 12 | "0" |
urxe_ovf |
|
|||||||
| 11 | "0" |
utx_ufl |
|
|||||||
| 10 | "0" |
urx_ovf |
|
|||||||
| 9 - 8 | 0 |
- |
reserved | |||||||
| 7 | "0" |
gpio3_oe |
|
|||||||
| 6 | "0" |
gpio2_oe |
|
|||||||
| 5 | "0" |
gpio1_oe |
|
|||||||
| 4 | "0" |
gpio0_oe |
|
|||||||
| 3 | "0" |
gpio3 |
|
|||||||
| 2 | "0" |
gpio2 |
|
|||||||
| 1 | "0" |
gpio1 |
|
|||||||
| 0 | "0" |
gpio0 |
|
|||||||
| gxc_sr_stat_bits |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
set_mask |
|
|
| 15 - 0 | 0x0 |
flags |
|
|
| gxc_sr_lut_bits |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6254c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
lut_out |
|
|
| 15 - 0 | 0x0 |
lut_in |
|
|
| gxc_sr_lut_cfg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d62550 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 - 16 | "0000" |
lut |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 - 14 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 - 8 | "000000" |
lut_in1_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 - 0 | "000000" |
lut_in0_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gxc_sr_lut_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6255c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg5 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg6 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg7 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6256c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg8 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg9 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg10 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62578 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg11 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6257c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg12 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg13 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg14 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| gxc_sr_lut_cfg15 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6258c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
lut |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 - 8 | "000000" |
lut_in1_sel |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
lut_in0_sel |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_start_ctrl |
| 1 | 4 | R/W | gxc_stop_ctrl |
| 2 | 8 | R/W | gxc_clk_enable |
| 3 | c | R/W | gxc_clk_disable |
| gxc_start_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62780 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
tpu1 |
|
|
| 24 | "0" |
rpu1 |
|
|
| 23 | "0" |
gpec17 |
|
|
| 22 | "0" |
gpec16 |
|
|
| 21 | "0" |
gpec15 |
|
|
| 20 | "0" |
gpec14 |
|
|
| 19 | "0" |
gpec13 |
|
|
| 18 | "0" |
gpec12 |
|
|
| 17 | "0" |
gpec11 |
|
|
| 16 | "0" |
gpec10 |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
tpu0 |
|
|
| 8 | "0" |
rpu0 |
|
|
| 7 | "0" |
gpec07 |
|
|
| 6 | "0" |
gpec06 |
|
|
| 5 | "0" |
gpec05 |
|
|
| 4 | "0" |
gpec04 |
|
|
| 3 | "0" |
gpec03 |
|
|
| 2 | "0" |
gpec02 |
|
|
| 1 | "0" |
gpec01 |
|
|
| 0 | "0" |
gpec00 |
|
|
| gxc_stop_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62784 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
tpu1 |
|
|
| 24 | "0" |
rpu1 |
|
|
| 23 | "0" |
gpec17 |
|
|
| 22 | "0" |
gpec16 |
|
|
| 21 | "0" |
gpec15 |
|
|
| 20 | "0" |
gpec14 |
|
|
| 19 | "0" |
gpec13 |
|
|
| 18 | "0" |
gpec12 |
|
|
| 17 | "0" |
gpec11 |
|
|
| 16 | "0" |
gpec10 |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
tpu0 |
|
|
| 8 | "0" |
rpu0 |
|
|
| 7 | "0" |
gpec07 |
|
|
| 6 | "0" |
gpec06 |
|
|
| 5 | "0" |
gpec05 |
|
|
| 4 | "0" |
gpec04 |
|
|
| 3 | "0" |
gpec03 |
|
|
| 2 | "0" |
gpec02 |
|
|
| 1 | "0" |
gpec01 |
|
|
| 0 | "0" |
gpec00 |
|
|
| gxc_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x07d62788 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 | "0" |
global_buf_man |
|
|
| 26 | "0" |
pfifo11 |
|
|
| 25 | "0" |
pfifo10 |
|
|
| 24 | "0" |
gmac1 |
|
|
| 23 | "0" |
gpec17 |
|
|
| 22 | "0" |
gpec16 |
|
|
| 21 | "0" |
gpec15 |
|
|
| 20 | "0" |
gpec14 |
|
|
| 19 | "0" |
gpec13 |
|
|
| 18 | "0" |
gpec12 |
|
|
| 17 | "0" |
gpec11 |
|
|
| 16 | "0" |
gpec10 |
|
|
| 15 - 12 | 0 |
- |
reserved | |
| 11 | "0" |
esc_unit |
|
|
| 10 | "0" |
pfifo01 |
|
|
| 9 | "0" |
pfifo00 |
|
|
| 8 | "0" |
gmac0 |
|
|
| 7 | "0" |
gpec07 |
|
|
| 6 | "0" |
gpec06 |
|
|
| 5 | "0" |
gpec05 |
|
|
| 4 | "0" |
gpec04 |
|
|
| 3 | "0" |
gpec03 |
|
|
| 2 | "0" |
gpec02 |
|
|
| 1 | "0" |
gpec01 |
|
|
| 0 | "0" |
gpec00 |
|
|
| gxc_clk_disable |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6278c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 | "0" |
global_buf_man |
|
|
| 26 | "0" |
pfifo11 |
|
|
| 25 | "0" |
pfifo10 |
|
|
| 24 | "0" |
gmac1 |
|
|
| 23 | "0" |
gpec17 |
|
|
| 22 | "0" |
gpec16 |
|
|
| 21 | "0" |
gpec15 |
|
|
| 20 | "0" |
gpec14 |
|
|
| 19 | "0" |
gpec13 |
|
|
| 18 | "0" |
gpec12 |
|
|
| 17 | "0" |
gpec11 |
|
|
| 16 | "0" |
gpec10 |
|
|
| 15 - 12 | 0 |
- |
reserved | |
| 11 | "0" |
esc_unit |
|
|
| 10 | "0" |
pfifo01 |
|
|
| 9 | "0" |
pfifo00 |
|
|
| 8 | "0" |
gmac0 |
|
|
| 7 | "0" |
gpec07 |
|
|
| 6 | "0" |
gpec06 |
|
|
| 5 | "0" |
gpec05 |
|
|
| 4 | "0" |
gpec04 |
|
|
| 3 | "0" |
gpec03 |
|
|
| 2 | "0" |
gpec02 |
|
|
| 1 | "0" |
gpec01 |
|
|
| 0 | "0" |
gpec00 |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_buf_man_gpec00 |
| 1 | 4 | R/W | gxc_buf_man_gpec10 |
| 2 | 8 | R/W | gxc_buf_man |
| 3 | c | - | reserved |
| gxc_buf_man_gpec00 |
|
|||||||||||||||
| R/W |
0x00000007 |
Address : 0x07d62790 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |||||||||||||
| 11 | "0" |
sm_update_dis |
|
|||||||||||||
| 10 | "0" |
sm_update_en |
|
|||||||||||||
| 9 | "0" |
reset |
|
|||||||||||||
| 8 | "0" |
parallel_mode |
|
|||||||||||||
| 7 | "0" |
semaphore_mode |
|
|||||||||||||
| 6 - 5 | "00" |
req_type |
|
|||||||||||||
| 4 | 0 |
- |
reserved | |||||||||||||
| 3 - 0 | "0111" |
buf_nr |
|
|||||||||||||
| gxc_buf_man_gpec10 |
|
|||||||||||||||
| R/W |
0x00000007 |
Address : 0x07d62794 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |||||||||||||
| 11 | "0" |
sm_update_dis |
|
|||||||||||||
| 10 | "0" |
sm_update_en |
|
|||||||||||||
| 9 | "0" |
reset |
|
|||||||||||||
| 8 | "0" |
parallel_mode |
|
|||||||||||||
| 7 | "0" |
semaphore_mode |
|
|||||||||||||
| 6 - 5 | "00" |
req_type |
|
|||||||||||||
| 4 | 0 |
- |
reserved | |||||||||||||
| 3 - 0 | "0111" |
buf_nr |
|
|||||||||||||
| gxc_buf_man |
|
|||||||||||||||
| R/W |
0x00000007 |
Address : 0x07d62798 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |||||||||||||
| 9 | "0" |
reset |
|
|||||||||||||
| 8 | "0" |
parallel_mode |
|
|||||||||||||
| 7 | "0" |
semaphore_mode |
|
|||||||||||||
| 6 - 5 | "00" |
req_type |
|
|||||||||||||
| 4 | 0 |
- |
reserved | |||||||||||||
| 3 - 0 | "0111" |
buf_nr |
|
|||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6300c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6301c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power8 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63020 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power9 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63024 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power10 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63028 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power11 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6302c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power12 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63030 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power13 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63034 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power14 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63038 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power15 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6303c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power16 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63040 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power17 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63044 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power18 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63048 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power19 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6304c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power20 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63050 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power21 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63054 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power22 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63058 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power23 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6305c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power24 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63060 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power25 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63064 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power26 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63068 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power27 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6306c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power28 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63070 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power29 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63074 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power30 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63078 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power31 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6307c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power32 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63080 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power33 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63084 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power34 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63088 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power35 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6308c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power36 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63090 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power37 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63094 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power38 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d63098 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power39 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d6309c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power40 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630a0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power41 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630a4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power42 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630a8 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power43 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630ac |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power44 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630b0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power45 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630b4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power46 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630b8 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power47 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630bc |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power48 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630c0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power49 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630c4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power50 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630c8 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power51 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630cc |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_mbist_power52 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x07d630d0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gxc_sys_0_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6380c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc5 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc6 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc7 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6381c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc8 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc9 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63824 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc10 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63828 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc11 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6382c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc12 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63830 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc13 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63834 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc14 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63838 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc15 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6383c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc16 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63840 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc17 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63844 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc18 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63848 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc19 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6384c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc20 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63850 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc21 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63854 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc22 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63858 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc23 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6385c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc24 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63860 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc25 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63864 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc26 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63868 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc27 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6386c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc28 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63870 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc29 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63874 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc30 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63878 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc31 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6387c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc32 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63880 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc33 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63884 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc34 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63888 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc35 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6388c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc36 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63890 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc37 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63894 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc38 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63898 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc39 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d6389c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc40 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d638a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc41 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d638a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc42 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d638a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc43 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d638ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc44 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d638b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr0 |
|
|||
| R |
Address : 0x07d63a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr1 |
|
|||
| R |
Address : 0x07d63a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr2 |
|
|||
| R |
Address : 0x07d63a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr3 |
|
|||
| R |
Address : 0x07d63a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr4 |
|
|||
| R |
Address : 0x07d63a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr5 |
|
|||
| R |
Address : 0x07d63a14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr6 |
|
|||
| R |
Address : 0x07d63a18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr7 |
|
|||
| R |
Address : 0x07d63a1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr8 |
|
|||
| R |
Address : 0x07d63a20 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr9 |
|
|||
| R |
Address : 0x07d63a24 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr10 |
|
|||
| R |
Address : 0x07d63a28 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr11 |
|
|||
| R |
Address : 0x07d63a2c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr12 |
|
|||
| R |
Address : 0x07d63a30 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr13 |
|
|||
| R |
Address : 0x07d63a34 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr14 |
|
|||
| R |
Address : 0x07d63a38 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr15 |
|
|||
| R |
Address : 0x07d63a3c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr16 |
|
|||
| R |
Address : 0x07d63a40 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr17 |
|
|||
| R |
Address : 0x07d63a44 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr18 |
|
|||
| R |
Address : 0x07d63a48 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr19 |
|
|||
| R |
Address : 0x07d63a4c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr20 |
|
|||
| R |
Address : 0x07d63a50 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr21 |
|
|||
| R |
Address : 0x07d63a54 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr22 |
|
|||
| R |
Address : 0x07d63a58 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr23 |
|
|||
| R |
Address : 0x07d63a5c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr24 |
|
|||
| R |
Address : 0x07d63a60 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr25 |
|
|||
| R |
Address : 0x07d63a64 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr26 |
|
|||
| R |
Address : 0x07d63a68 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr27 |
|
|||
| R |
Address : 0x07d63a6c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr28 |
|
|||
| R |
Address : 0x07d63a70 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr29 |
|
|||
| R |
Address : 0x07d63a74 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr30 |
|
|||
| R |
Address : 0x07d63a78 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr31 |
|
|||
| R |
Address : 0x07d63a7c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr32 |
|
|||
| R |
Address : 0x07d63a80 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr33 |
|
|||
| R |
Address : 0x07d63a84 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr34 |
|
|||
| R |
Address : 0x07d63a88 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr35 |
|
|||
| R |
Address : 0x07d63a8c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr36 |
|
|||
| R |
Address : 0x07d63a90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr37 |
|
|||
| R |
Address : 0x07d63a94 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr38 |
|
|||
| R |
Address : 0x07d63a98 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr39 |
|
|||
| R |
Address : 0x07d63a9c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr40 |
|
|||
| R |
Address : 0x07d63aa0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr41 |
|
|||
| R |
Address : 0x07d63aa4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr42 |
|
|||
| R |
Address : 0x07d63aa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr43 |
|
|||
| R |
Address : 0x07d63aac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_corr44 |
|
|||
| R |
Address : 0x07d63ab0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x07d63c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr1 |
|
|||
| R |
Address : 0x07d63c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr2 |
|
|||
| R |
Address : 0x07d63c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr3 |
|
|||
| R |
Address : 0x07d63c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr4 |
|
|||
| R |
Address : 0x07d63c10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr5 |
|
|||
| R |
Address : 0x07d63c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr6 |
|
|||
| R |
Address : 0x07d63c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr7 |
|
|||
| R |
Address : 0x07d63c1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr8 |
|
|||
| R |
Address : 0x07d63c20 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr9 |
|
|||
| R |
Address : 0x07d63c24 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr10 |
|
|||
| R |
Address : 0x07d63c28 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr11 |
|
|||
| R |
Address : 0x07d63c2c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr12 |
|
|||
| R |
Address : 0x07d63c30 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr13 |
|
|||
| R |
Address : 0x07d63c34 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr14 |
|
|||
| R |
Address : 0x07d63c38 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr15 |
|
|||
| R |
Address : 0x07d63c3c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr16 |
|
|||
| R |
Address : 0x07d63c40 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr17 |
|
|||
| R |
Address : 0x07d63c44 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr18 |
|
|||
| R |
Address : 0x07d63c48 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr19 |
|
|||
| R |
Address : 0x07d63c4c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr20 |
|
|||
| R |
Address : 0x07d63c50 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr21 |
|
|||
| R |
Address : 0x07d63c54 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr22 |
|
|||
| R |
Address : 0x07d63c58 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr23 |
|
|||
| R |
Address : 0x07d63c5c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr24 |
|
|||
| R |
Address : 0x07d63c60 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr25 |
|
|||
| R |
Address : 0x07d63c64 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr26 |
|
|||
| R |
Address : 0x07d63c68 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr27 |
|
|||
| R |
Address : 0x07d63c6c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr28 |
|
|||
| R |
Address : 0x07d63c70 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr29 |
|
|||
| R |
Address : 0x07d63c74 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr30 |
|
|||
| R |
Address : 0x07d63c78 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr31 |
|
|||
| R |
Address : 0x07d63c7c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr32 |
|
|||
| R |
Address : 0x07d63c80 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr33 |
|
|||
| R |
Address : 0x07d63c84 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr34 |
|
|||
| R |
Address : 0x07d63c88 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr35 |
|
|||
| R |
Address : 0x07d63c8c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr36 |
|
|||
| R |
Address : 0x07d63c90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr37 |
|
|||
| R |
Address : 0x07d63c94 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr38 |
|
|||
| R |
Address : 0x07d63c98 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr39 |
|
|||
| R |
Address : 0x07d63c9c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr40 |
|
|||
| R |
Address : 0x07d63ca0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr41 |
|
|||
| R |
Address : 0x07d63ca4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr42 |
|
|||
| R |
Address : 0x07d63ca8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr43 |
|
|||
| R |
Address : 0x07d63cac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr44 |
|
|||
| R |
Address : 0x07d63cb0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gxc_sys_0_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_31_err_ecc_non_correctable |
|
|
| 30 | "0" |
mem_30_err_ecc_non_correctable |
|
|
| 29 | "0" |
mem_29_err_ecc_non_correctable |
|
|
| 28 | "0" |
mem_28_err_ecc_non_correctable |
|
|
| 27 | "0" |
mem_27_err_ecc_non_correctable |
|
|
| 26 | "0" |
mem_26_err_ecc_non_correctable |
|
|
| 25 | "0" |
mem_25_err_ecc_non_correctable |
|
|
| 24 | "0" |
mem_24_err_ecc_non_correctable |
|
|
| 23 | "0" |
mem_23_err_ecc_non_correctable |
|
|
| 22 | "0" |
mem_22_err_ecc_non_correctable |
|
|
| 21 | "0" |
mem_21_err_ecc_non_correctable |
|
|
| 20 | "0" |
mem_20_err_ecc_non_correctable |
|
|
| 19 | "0" |
mem_19_err_ecc_non_correctable |
|
|
| 18 | "0" |
mem_18_err_ecc_non_correctable |
|
|
| 17 | "0" |
mem_17_err_ecc_non_correctable |
|
|
| 16 | "0" |
mem_16_err_ecc_non_correctable |
|
|
| 15 | "0" |
mem_15_err_ecc_non_correctable |
|
|
| 14 | "0" |
mem_14_err_ecc_non_correctable |
|
|
| 13 | "0" |
mem_13_err_ecc_non_correctable |
|
|
| 12 | "0" |
mem_12_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_11_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_10_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_9_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_raw_reg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_18_err_ecc_correctable |
|
|
| 30 | "0" |
mem_17_err_ecc_correctable |
|
|
| 29 | "0" |
mem_16_err_ecc_correctable |
|
|
| 28 | "0" |
mem_15_err_ecc_correctable |
|
|
| 27 | "0" |
mem_14_err_ecc_correctable |
|
|
| 26 | "0" |
mem_13_err_ecc_correctable |
|
|
| 25 | "0" |
mem_12_err_ecc_correctable |
|
|
| 24 | "0" |
mem_11_err_ecc_correctable |
|
|
| 23 | "0" |
mem_10_err_ecc_correctable |
|
|
| 22 | "0" |
mem_9_err_ecc_correctable |
|
|
| 21 | "0" |
mem_8_err_ecc_correctable |
|
|
| 20 | "0" |
mem_7_err_ecc_correctable |
|
|
| 19 | "0" |
mem_6_err_ecc_correctable |
|
|
| 18 | "0" |
mem_5_err_ecc_correctable |
|
|
| 17 | "0" |
mem_4_err_ecc_correctable |
|
|
| 16 | "0" |
mem_3_err_ecc_correctable |
|
|
| 15 | "0" |
mem_2_err_ecc_correctable |
|
|
| 14 | "0" |
mem_1_err_ecc_correctable |
|
|
| 13 | "0" |
mem_0_err_ecc_correctable |
|
|
| 12 | "0" |
mem_44_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_43_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_42_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_41_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_40_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_39_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_38_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_37_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_36_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_35_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_34_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_33_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_32_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_raw_reg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_44_err_ecc_correctable |
|
|
| 24 | "0" |
mem_43_err_ecc_correctable |
|
|
| 23 | "0" |
mem_42_err_ecc_correctable |
|
|
| 22 | "0" |
mem_41_err_ecc_correctable |
|
|
| 21 | "0" |
mem_40_err_ecc_correctable |
|
|
| 20 | "0" |
mem_39_err_ecc_correctable |
|
|
| 19 | "0" |
mem_38_err_ecc_correctable |
|
|
| 18 | "0" |
mem_37_err_ecc_correctable |
|
|
| 17 | "0" |
mem_36_err_ecc_correctable |
|
|
| 16 | "0" |
mem_35_err_ecc_correctable |
|
|
| 15 | "0" |
mem_34_err_ecc_correctable |
|
|
| 14 | "0" |
mem_33_err_ecc_correctable |
|
|
| 13 | "0" |
mem_32_err_ecc_correctable |
|
|
| 12 | "0" |
mem_31_err_ecc_correctable |
|
|
| 11 | "0" |
mem_30_err_ecc_correctable |
|
|
| 10 | "0" |
mem_29_err_ecc_correctable |
|
|
| 9 | "0" |
mem_28_err_ecc_correctable |
|
|
| 8 | "0" |
mem_27_err_ecc_correctable |
|
|
| 7 | "0" |
mem_26_err_ecc_correctable |
|
|
| 6 | "0" |
mem_25_err_ecc_correctable |
|
|
| 5 | "0" |
mem_24_err_ecc_correctable |
|
|
| 4 | "0" |
mem_23_err_ecc_correctable |
|
|
| 3 | "0" |
mem_22_err_ecc_correctable |
|
|
| 2 | "0" |
mem_21_err_ecc_correctable |
|
|
| 1 | "0" |
mem_20_err_ecc_correctable |
|
|
| 0 | "0" |
mem_19_err_ecc_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_raw_reg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_24_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_6_mbist_or_init_finished |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_raw_reg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
mem_52_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_51_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_50_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_49_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_48_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_47_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_46_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_45_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_44_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_43_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_42_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_38_mbist_or_init_finished |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_31_err_ecc_non_correctable |
|
|
| 30 | "0" |
mem_30_err_ecc_non_correctable |
|
|
| 29 | "0" |
mem_29_err_ecc_non_correctable |
|
|
| 28 | "0" |
mem_28_err_ecc_non_correctable |
|
|
| 27 | "0" |
mem_27_err_ecc_non_correctable |
|
|
| 26 | "0" |
mem_26_err_ecc_non_correctable |
|
|
| 25 | "0" |
mem_25_err_ecc_non_correctable |
|
|
| 24 | "0" |
mem_24_err_ecc_non_correctable |
|
|
| 23 | "0" |
mem_23_err_ecc_non_correctable |
|
|
| 22 | "0" |
mem_22_err_ecc_non_correctable |
|
|
| 21 | "0" |
mem_21_err_ecc_non_correctable |
|
|
| 20 | "0" |
mem_20_err_ecc_non_correctable |
|
|
| 19 | "0" |
mem_19_err_ecc_non_correctable |
|
|
| 18 | "0" |
mem_18_err_ecc_non_correctable |
|
|
| 17 | "0" |
mem_17_err_ecc_non_correctable |
|
|
| 16 | "0" |
mem_16_err_ecc_non_correctable |
|
|
| 15 | "0" |
mem_15_err_ecc_non_correctable |
|
|
| 14 | "0" |
mem_14_err_ecc_non_correctable |
|
|
| 13 | "0" |
mem_13_err_ecc_non_correctable |
|
|
| 12 | "0" |
mem_12_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_11_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_10_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_9_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_masked_reg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_18_err_ecc_correctable |
|
|
| 30 | "0" |
mem_17_err_ecc_correctable |
|
|
| 29 | "0" |
mem_16_err_ecc_correctable |
|
|
| 28 | "0" |
mem_15_err_ecc_correctable |
|
|
| 27 | "0" |
mem_14_err_ecc_correctable |
|
|
| 26 | "0" |
mem_13_err_ecc_correctable |
|
|
| 25 | "0" |
mem_12_err_ecc_correctable |
|
|
| 24 | "0" |
mem_11_err_ecc_correctable |
|
|
| 23 | "0" |
mem_10_err_ecc_correctable |
|
|
| 22 | "0" |
mem_9_err_ecc_correctable |
|
|
| 21 | "0" |
mem_8_err_ecc_correctable |
|
|
| 20 | "0" |
mem_7_err_ecc_correctable |
|
|
| 19 | "0" |
mem_6_err_ecc_correctable |
|
|
| 18 | "0" |
mem_5_err_ecc_correctable |
|
|
| 17 | "0" |
mem_4_err_ecc_correctable |
|
|
| 16 | "0" |
mem_3_err_ecc_correctable |
|
|
| 15 | "0" |
mem_2_err_ecc_correctable |
|
|
| 14 | "0" |
mem_1_err_ecc_correctable |
|
|
| 13 | "0" |
mem_0_err_ecc_correctable |
|
|
| 12 | "0" |
mem_44_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_43_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_42_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_41_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_40_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_39_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_38_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_37_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_36_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_35_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_34_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_33_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_32_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_masked_reg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_44_err_ecc_correctable |
|
|
| 24 | "0" |
mem_43_err_ecc_correctable |
|
|
| 23 | "0" |
mem_42_err_ecc_correctable |
|
|
| 22 | "0" |
mem_41_err_ecc_correctable |
|
|
| 21 | "0" |
mem_40_err_ecc_correctable |
|
|
| 20 | "0" |
mem_39_err_ecc_correctable |
|
|
| 19 | "0" |
mem_38_err_ecc_correctable |
|
|
| 18 | "0" |
mem_37_err_ecc_correctable |
|
|
| 17 | "0" |
mem_36_err_ecc_correctable |
|
|
| 16 | "0" |
mem_35_err_ecc_correctable |
|
|
| 15 | "0" |
mem_34_err_ecc_correctable |
|
|
| 14 | "0" |
mem_33_err_ecc_correctable |
|
|
| 13 | "0" |
mem_32_err_ecc_correctable |
|
|
| 12 | "0" |
mem_31_err_ecc_correctable |
|
|
| 11 | "0" |
mem_30_err_ecc_correctable |
|
|
| 10 | "0" |
mem_29_err_ecc_correctable |
|
|
| 9 | "0" |
mem_28_err_ecc_correctable |
|
|
| 8 | "0" |
mem_27_err_ecc_correctable |
|
|
| 7 | "0" |
mem_26_err_ecc_correctable |
|
|
| 6 | "0" |
mem_25_err_ecc_correctable |
|
|
| 5 | "0" |
mem_24_err_ecc_correctable |
|
|
| 4 | "0" |
mem_23_err_ecc_correctable |
|
|
| 3 | "0" |
mem_22_err_ecc_correctable |
|
|
| 2 | "0" |
mem_21_err_ecc_correctable |
|
|
| 1 | "0" |
mem_20_err_ecc_correctable |
|
|
| 0 | "0" |
mem_19_err_ecc_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_masked_reg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_24_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_6_mbist_or_init_finished |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_masked_reg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
mem_52_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_51_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_50_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_49_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_48_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_47_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_46_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_45_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_44_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_43_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_42_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_41_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_40_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_39_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_38_mbist_or_init_finished |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_31_err_ecc_non_correctable |
|
|
| 30 | "0" |
mem_30_err_ecc_non_correctable |
|
|
| 29 | "0" |
mem_29_err_ecc_non_correctable |
|
|
| 28 | "0" |
mem_28_err_ecc_non_correctable |
|
|
| 27 | "0" |
mem_27_err_ecc_non_correctable |
|
|
| 26 | "0" |
mem_26_err_ecc_non_correctable |
|
|
| 25 | "0" |
mem_25_err_ecc_non_correctable |
|
|
| 24 | "0" |
mem_24_err_ecc_non_correctable |
|
|
| 23 | "0" |
mem_23_err_ecc_non_correctable |
|
|
| 22 | "0" |
mem_22_err_ecc_non_correctable |
|
|
| 21 | "0" |
mem_21_err_ecc_non_correctable |
|
|
| 20 | "0" |
mem_20_err_ecc_non_correctable |
|
|
| 19 | "0" |
mem_19_err_ecc_non_correctable |
|
|
| 18 | "0" |
mem_18_err_ecc_non_correctable |
|
|
| 17 | "0" |
mem_17_err_ecc_non_correctable |
|
|
| 16 | "0" |
mem_16_err_ecc_non_correctable |
|
|
| 15 | "0" |
mem_15_err_ecc_non_correctable |
|
|
| 14 | "0" |
mem_14_err_ecc_non_correctable |
|
|
| 13 | "0" |
mem_13_err_ecc_non_correctable |
|
|
| 12 | "0" |
mem_12_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_11_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_10_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_9_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_18_err_ecc_correctable |
|
|
| 30 | "0" |
mem_17_err_ecc_correctable |
|
|
| 29 | "0" |
mem_16_err_ecc_correctable |
|
|
| 28 | "0" |
mem_15_err_ecc_correctable |
|
|
| 27 | "0" |
mem_14_err_ecc_correctable |
|
|
| 26 | "0" |
mem_13_err_ecc_correctable |
|
|
| 25 | "0" |
mem_12_err_ecc_correctable |
|
|
| 24 | "0" |
mem_11_err_ecc_correctable |
|
|
| 23 | "0" |
mem_10_err_ecc_correctable |
|
|
| 22 | "0" |
mem_9_err_ecc_correctable |
|
|
| 21 | "0" |
mem_8_err_ecc_correctable |
|
|
| 20 | "0" |
mem_7_err_ecc_correctable |
|
|
| 19 | "0" |
mem_6_err_ecc_correctable |
|
|
| 18 | "0" |
mem_5_err_ecc_correctable |
|
|
| 17 | "0" |
mem_4_err_ecc_correctable |
|
|
| 16 | "0" |
mem_3_err_ecc_correctable |
|
|
| 15 | "0" |
mem_2_err_ecc_correctable |
|
|
| 14 | "0" |
mem_1_err_ecc_correctable |
|
|
| 13 | "0" |
mem_0_err_ecc_correctable |
|
|
| 12 | "0" |
mem_44_err_ecc_non_correctable |
|
|
| 11 | "0" |
mem_43_err_ecc_non_correctable |
|
|
| 10 | "0" |
mem_42_err_ecc_non_correctable |
|
|
| 9 | "0" |
mem_41_err_ecc_non_correctable |
|
|
| 8 | "0" |
mem_40_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_39_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_38_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_37_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_36_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_35_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_34_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_33_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_32_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_44_err_ecc_correctable |
|
|
| 24 | "0" |
mem_43_err_ecc_correctable |
|
|
| 23 | "0" |
mem_42_err_ecc_correctable |
|
|
| 22 | "0" |
mem_41_err_ecc_correctable |
|
|
| 21 | "0" |
mem_40_err_ecc_correctable |
|
|
| 20 | "0" |
mem_39_err_ecc_correctable |
|
|
| 19 | "0" |
mem_38_err_ecc_correctable |
|
|
| 18 | "0" |
mem_37_err_ecc_correctable |
|
|
| 17 | "0" |
mem_36_err_ecc_correctable |
|
|
| 16 | "0" |
mem_35_err_ecc_correctable |
|
|
| 15 | "0" |
mem_34_err_ecc_correctable |
|
|
| 14 | "0" |
mem_33_err_ecc_correctable |
|
|
| 13 | "0" |
mem_32_err_ecc_correctable |
|
|
| 12 | "0" |
mem_31_err_ecc_correctable |
|
|
| 11 | "0" |
mem_30_err_ecc_correctable |
|
|
| 10 | "0" |
mem_29_err_ecc_correctable |
|
|
| 9 | "0" |
mem_28_err_ecc_correctable |
|
|
| 8 | "0" |
mem_27_err_ecc_correctable |
|
|
| 7 | "0" |
mem_26_err_ecc_correctable |
|
|
| 6 | "0" |
mem_25_err_ecc_correctable |
|
|
| 5 | "0" |
mem_24_err_ecc_correctable |
|
|
| 4 | "0" |
mem_23_err_ecc_correctable |
|
|
| 3 | "0" |
mem_22_err_ecc_correctable |
|
|
| 2 | "0" |
mem_21_err_ecc_correctable |
|
|
| 1 | "0" |
mem_20_err_ecc_correctable |
|
|
| 0 | "0" |
mem_19_err_ecc_correctable |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mem_37_mbist_or_init_finished |
|
|
| 30 | "0" |
mem_36_mbist_or_init_finished |
|
|
| 29 | "0" |
mem_35_mbist_or_init_finished |
|
|
| 28 | "0" |
mem_34_mbist_or_init_finished |
|
|
| 27 | "0" |
mem_33_mbist_or_init_finished |
|
|
| 26 | "0" |
mem_32_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_31_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_30_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_29_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_28_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_27_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_26_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_25_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_24_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_23_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_22_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_21_mbist_or_init_finished |
|
|
| 14 | "0" |
mem_20_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_19_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_18_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_17_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_16_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_15_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_14_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_13_mbist_or_init_finished |
|
|
| 6 | "0" |
mem_12_mbist_or_init_finished |
|
|
| 5 | "0" |
mem_11_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_10_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_9_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 0 | "0" |
mem_6_mbist_or_init_finished |
|
|
| gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d63e90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
mem_52_mbist_or_init_finished |
|
|
| 13 | "0" |
mem_51_mbist_or_init_finished |
|
|
| 12 | "0" |
mem_50_mbist_or_init_finished |
|
|
| 11 | "0" |
mem_49_mbist_or_init_finished |
|
|
| 10 | "0" |
mem_48_mbist_or_init_finished |
|
|
| 9 | "0" |
mem_47_mbist_or_init_finished |
|
|
| 8 | "0" |
mem_46_mbist_or_init_finished |
|
|
| 7 | "0" |
mem_45_mbist_or_init_finished |
|
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| 6 | "0" |
mem_44_mbist_or_init_finished |
|
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| 5 | "0" |
mem_43_mbist_or_init_finished |
|
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| 4 | "0" |
mem_42_mbist_or_init_finished |
|
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| 3 | "0" |
mem_41_mbist_or_init_finished |
|
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| 2 | "0" |
mem_40_mbist_or_init_finished |
|
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| 1 | "0" |
mem_39_mbist_or_init_finished |
|
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| 0 | "0" |
mem_38_mbist_or_init_finished |
|
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| gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg0 |
|
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| R/W |
0x00000000 |
Address : 0x07d63ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_31_err_ecc_non_correctable |
|
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| 30 | "0" |
mem_30_err_ecc_non_correctable |
|
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| 29 | "0" |
mem_29_err_ecc_non_correctable |
|
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| 28 | "0" |
mem_28_err_ecc_non_correctable |
|
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| 27 | "0" |
mem_27_err_ecc_non_correctable |
|
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| 26 | "0" |
mem_26_err_ecc_non_correctable |
|
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| 25 | "0" |
mem_25_err_ecc_non_correctable |
|
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| 24 | "0" |
mem_24_err_ecc_non_correctable |
|
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| 23 | "0" |
mem_23_err_ecc_non_correctable |
|
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| 22 | "0" |
mem_22_err_ecc_non_correctable |
|
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| 21 | "0" |
mem_21_err_ecc_non_correctable |
|
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| 20 | "0" |
mem_20_err_ecc_non_correctable |
|
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| 19 | "0" |
mem_19_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_18_err_ecc_non_correctable |
|
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| 17 | "0" |
mem_17_err_ecc_non_correctable |
|
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| 16 | "0" |
mem_16_err_ecc_non_correctable |
|
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| 15 | "0" |
mem_15_err_ecc_non_correctable |
|
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| 14 | "0" |
mem_14_err_ecc_non_correctable |
|
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| 13 | "0" |
mem_13_err_ecc_non_correctable |
|
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| 12 | "0" |
mem_12_err_ecc_non_correctable |
|
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| 11 | "0" |
mem_11_err_ecc_non_correctable |
|
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| 10 | "0" |
mem_10_err_ecc_non_correctable |
|
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| 9 | "0" |
mem_9_err_ecc_non_correctable |
|
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| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
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| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
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| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
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| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
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| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
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| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
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| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
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| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
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| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
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| gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg1 |
|
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| R/W |
0x00000000 |
Address : 0x07d63ec4 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_18_err_ecc_correctable |
|
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| 30 | "0" |
mem_17_err_ecc_correctable |
|
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| 29 | "0" |
mem_16_err_ecc_correctable |
|
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| 28 | "0" |
mem_15_err_ecc_correctable |
|
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| 27 | "0" |
mem_14_err_ecc_correctable |
|
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| 26 | "0" |
mem_13_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_12_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_11_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_10_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_9_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_8_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_7_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_6_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_5_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_4_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_44_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_43_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_42_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_41_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_40_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_39_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_38_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_37_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_36_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_35_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_34_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_33_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_32_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d63ec8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_44_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_43_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_42_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_41_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_40_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_39_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_38_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_37_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_36_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_35_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_34_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_33_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_32_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_31_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_30_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_29_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_28_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_27_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_26_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_25_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_24_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_23_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_22_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_21_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_20_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_19_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d63ecc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
mem_37_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
mem_36_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
mem_35_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
mem_34_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
mem_33_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
mem_32_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_31_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_30_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_29_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_28_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_27_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_26_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_25_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_24_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_23_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_22_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_21_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_20_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_19_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_18_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_17_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_16_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_15_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_14_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_13_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_12_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_11_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_10_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_9_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_8_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d63ed0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_52_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_51_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_50_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_49_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_48_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_47_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_46_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_45_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_44_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_43_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_42_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_41_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_40_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_39_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_38_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_gxc_sys_0_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x07d63efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| ethercat_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
mii0_link_down_cnt |
||
| 23 - 16 | "00000000" |
mii0_mii_err_cnt |
||
| 15 - 8 | "00000000" |
mii0_frwd_err_cnt |
||
| 7 - 0 | "00000000" |
mii0_frame_err_cnt |
||
| ethercat_reg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
mii1_link_down_cnt |
||
| 23 - 16 | "00000000" |
mii1_mii_err_cnt |
||
| 15 - 8 | "00000000" |
mii1_frwd_err_cnt |
||
| 7 - 0 | "00000000" |
mii1_frame_err_cnt |
||
| ethercat_reg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu0_log_startaddr |
||
| ethercat_reg3 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d8200c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu0_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu0_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu0_length |
|
|
| ethercat_reg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu0_proc_wr_enable |
|
|
| 24 | "0" |
fmmu0_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu0_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu0_phys_startaddr |
|
|
| ethercat_reg5 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu1_log_startaddr |
||
| ethercat_reg6 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d82018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu1_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu1_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu1_length |
|
|
| ethercat_reg7 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8201c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu1_proc_wr_enable |
|
|
| 24 | "0" |
fmmu1_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu1_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu1_phys_startaddr |
|
|
| ethercat_reg8 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu2_log_startaddr |
||
| ethercat_reg9 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d82024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu2_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu2_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu2_length |
|
|
| ethercat_reg10 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu2_proc_wr_enable |
|
|
| 24 | "0" |
fmmu2_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu2_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu2_phys_startaddr |
|
|
| ethercat_reg11 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8202c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu3_log_startaddr |
||
| ethercat_reg12 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d82030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu3_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu3_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu3_length |
|
|
| ethercat_reg13 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu3_proc_wr_enable |
|
|
| 24 | "0" |
fmmu3_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu3_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu3_phys_startaddr |
|
|
| ethercat_reg14 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu4_log_startaddr |
||
| ethercat_reg15 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d8203c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu4_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu4_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu4_length |
|
|
| ethercat_reg16 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu4_proc_wr_enable |
|
|
| 24 | "0" |
fmmu4_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu4_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu4_phys_startaddr |
|
|
| ethercat_reg17 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu5_log_startaddr |
||
| ethercat_reg18 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d82048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu5_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu5_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu5_length |
|
|
| ethercat_reg19 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8204c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu5_proc_wr_enable |
|
|
| 24 | "0" |
fmmu5_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu5_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu5_phys_startaddr |
|
|
| ethercat_reg20 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
fmmu6_log_startaddr |
||
| ethercat_reg21 |
|
|||
| R/W |
0x07000000 |
Address : 0x07d82054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
||
| 26 - 24 | "111" |
fmmu6_log_stop_bit |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu6_log_start_bit |
|
|
| 15 - 13 | "000" |
res15_13 |
||
| 12 - 0 | 0x0 |
fmmu6_length |
|
|
| ethercat_reg22 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||
| 25 | "0" |
fmmu6_proc_wr_enable |
|
|
| 24 | "0" |
fmmu6_proc_rd_enable |
|
|
| 23 - 19 | "00000" |
res23_19 |
||
| 18 - 16 | "000" |
fmmu6_phys_start_bit |
|
|
| 15 - 14 | "00" |
res15_14 |
||
| 13 - 0 | 0x0 |
fmmu6_phys_startaddr |
|
|
| ethercat_reg23 | |||
| R/W |
0x00000000 |
Address : 0x07d8205c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg24 | |||
| R/W |
0x00000000 |
Address : 0x07d82060 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg25 | |||
| R/W |
0x00000000 |
Address : 0x07d82064 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg26 | ||||
| R/W |
0x00000000 |
Address : 0x07d82068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | "0000000" |
res31_25 |
||
| 24 | "0" |
fmmu3_proc_enable |
|
|
| 23 - 17 | "0000000" |
res23_17 |
||
| 16 | "0" |
fmmu2_proc_enable |
|
|
| 15 - 9 | "0000000" |
res15_9 |
||
| 8 | "0" |
fmmu1_proc_enable |
|
|
| 7 - 1 | "0000000" |
res7_1 |
||
| 0 | "0" |
fmmu0_proc_enable |
|
|
| ethercat_reg27 | ||||
| R/W |
0x00000000 |
Address : 0x07d8206c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | "0000000" |
res31_25 |
||
| 24 | "0" |
fmmu7_proc_enable |
|
|
| 23 - 17 | "0000000" |
res23_17 |
||
| 16 | "0" |
fmmu6_proc_enable |
|
|
| 15 - 9 | "0000000" |
res15_9 |
||
| 8 | "0" |
fmmu5_proc_enable |
|
|
| 7 - 1 | "0000000" |
res7_1 |
||
| 0 | "0" |
fmmu4_proc_enable |
|
|
| ethercat_reg28 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm0_length |
|
|
| 15 - 0 | 0x0 |
sm0_startaddr |
|
|
| ethercat_reg29 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm1_length |
|
|
| 15 - 0 | 0x0 |
sm1_startaddr |
|
|
| ethercat_reg30 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm2_length |
|
|
| 15 - 0 | 0x0 |
sm2_startaddr |
|
|
| ethercat_reg31 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8207c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm3_length |
|
|
| 15 - 0 | 0x0 |
sm3_startaddr |
|
|
| ethercat_reg32 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm4_length |
|
|
| 15 - 0 | 0x0 |
sm4_startaddr |
|
|
| ethercat_reg33 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm5_length |
|
|
| 15 - 0 | 0x0 |
sm5_startaddr |
|
|
| ethercat_reg34 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm6_length |
|
|
| 15 - 0 | 0x0 |
sm6_startaddr |
|
|
| ethercat_reg35 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8208c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sm7_length |
|
|
| 15 - 0 | 0x0 |
sm7_startaddr |
|
|
| ethercat_reg36 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d82090 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
res31 |
||||||
| 30 | "0" |
sm3_cfg_wdg_en |
|
|||||
| 29 | "0" |
sm3_cfg_al_event_en |
|
|||||
| 28 | "0" |
sm3_cfg_ecat_event_en |
|
|||||
| 27 | "0" |
res27 |
||||||
| 26 | "0" |
sm3_cfg_write_read |
|
|||||
| 25 | "0" |
sm3_cfg_buf_method |
|
|||||
| 24 | "0" |
res24 |
||||||
| 23 | "0" |
res23 |
||||||
| 22 | "0" |
sm2_cfg_wdg_en |
|
|||||
| 21 | "0" |
sm2_cfg_al_event_en |
|
|||||
| 20 | "0" |
sm2_cfg_ecat_event_en |
|
|||||
| 19 | "0" |
res19 |
||||||
| 18 | "0" |
sm2_cfg_write_read |
|
|||||
| 17 | "0" |
sm2_cfg_buf_method |
|
|||||
| 16 | "0" |
res16 |
||||||
| 15 | "0" |
res15 |
||||||
| 14 | "0" |
sm1_cfg_wdg_en |
|
|||||
| 13 | "0" |
sm1_cfg_al_event_en |
|
|||||
| 12 | "0" |
sm1_cfg_ecat_event_en |
|
|||||
| 11 | "0" |
res11 |
||||||
| 10 | "0" |
sm1_cfg_write_read |
|
|||||
| 9 | "0" |
sm1_cfg_buf_method |
|
|||||
| 8 | "0" |
res8 |
||||||
| 7 | "0" |
res7 |
||||||
| 6 | "0" |
sm0_cfg_wdg_en |
|
|||||
| 5 | "0" |
sm0_cfg_al_event_en |
|
|||||
| 4 | "0" |
sm0_cfg_ecat_event_en |
|
|||||
| 3 | "0" |
res3 |
||||||
| 2 | "0" |
sm0_cfg_write_read |
|
|||||
| 1 | "0" |
sm0_cfg_buf_method |
|
|||||
| 0 | "0" |
res0 |
||||||
| ethercat_reg37 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d82094 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
res31 |
||||||
| 30 | "0" |
sm7_cfg_wdg_en |
|
|||||
| 29 | "0" |
sm7_cfg_al_event_en |
|
|||||
| 28 | "0" |
sm7_cfg_ecat_event_en |
|
|||||
| 27 | "0" |
res27 |
||||||
| 26 | "0" |
sm7_cfg_write_read |
|
|||||
| 25 | "0" |
sm7_cfg_buf_method |
|
|||||
| 24 | "0" |
res24 |
||||||
| 23 | "0" |
res23 |
||||||
| 22 | "0" |
sm6_cfg_wdg_en |
|
|||||
| 21 | "0" |
sm6_cfg_al_event_en |
|
|||||
| 20 | "0" |
sm6_cfg_ecat_event_en |
|
|||||
| 19 | "0" |
res19 |
||||||
| 18 | "0" |
sm6_cfg_write_read |
|
|||||
| 17 | "0" |
sm6_cfg_buf_method |
|
|||||
| 16 | "0" |
res16 |
||||||
| 15 | "0" |
res15 |
||||||
| 14 | "0" |
sm5_cfg_wdg_en |
|
|||||
| 13 | "0" |
sm5_cfg_al_event_en |
|
|||||
| 12 | "0" |
sm5_cfg_ecat_event_en |
|
|||||
| 11 | "0" |
res11 |
||||||
| 10 | "0" |
sm5_cfg_write_read |
|
|||||
| 9 | "0" |
sm5_cfg_buf_method |
|
|||||
| 8 | "0" |
res8 |
||||||
| 7 | "0" |
res7 |
||||||
| 6 | "0" |
sm4_cfg_wdg_en |
|
|||||
| 5 | "0" |
sm4_cfg_al_event_en |
|
|||||
| 4 | "0" |
sm4_cfg_ecat_event_en |
|
|||||
| 3 | "0" |
res3 |
||||||
| 2 | "0" |
sm4_cfg_write_read |
|
|||||
| 1 | "0" |
sm4_cfg_buf_method |
|
|||||
| 0 | "0" |
res0 |
||||||
| ethercat_reg38 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d82098 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||||||
| 25 | "0" |
sm3_repeat_req |
|
|||||
| 24 | "0" |
sm3_proc_enable |
|
|||||
| 23 - 18 | "000000" |
res23_18 |
||||||
| 17 | "0" |
sm2_repeat_req |
|
|||||
| 16 | "0" |
sm2_proc_enable |
|
|||||
| 15 - 10 | "000000" |
res15_10 |
||||||
| 9 | "0" |
sm1_repeat_req |
|
|||||
| 8 | "0" |
sm1_proc_enable |
|
|||||
| 7 - 2 | "000000" |
res7_2 |
||||||
| 1 | "0" |
sm0_repeat_req |
|
|||||
| 0 | "0" |
sm0_proc_enable |
|
|||||
| ethercat_reg39 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d8209c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||||||
| 25 | "0" |
sm7_repeat_req |
|
|||||
| 24 | "0" |
sm7_proc_enable |
|
|||||
| 23 - 18 | "000000" |
res23_18 |
||||||
| 17 | "0" |
sm6_repeat_req |
|
|||||
| 16 | "0" |
sm6_proc_enable |
|
|||||
| 15 - 10 | "000000" |
res15_10 |
||||||
| 9 | "0" |
sm5_repeat_req |
|
|||||
| 8 | "0" |
sm5_proc_enable |
|
|||||
| 7 - 2 | "000000" |
res7_2 |
||||||
| 1 | "0" |
sm4_repeat_req |
|
|||||
| 0 | "0" |
sm4_proc_enable |
|
|||||
| ethercat_reg40 | ||||
| R/W |
0x00000000 |
Address : 0x07d820a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
||
| 23 - 17 | "0000000" |
res23_17 |
|
|
| 16 | "0" |
alias_address_enable |
|
|
| 15 - 0 | 0x0 |
station_address |
||
| ethercat_reg41 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d820a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
trigger_0_starttime_ns |
||
| ethercat_reg42 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d820a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
trigger_0_starttime_s |
||
| ethercat_reg43 | ||||
| R/W |
0x00000000 |
Address : 0x07d820ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
|
| 23 - 16 | "00000000" |
byte_2 |
|
|
| 15 - 8 | "00000000" |
byte_1 |
|
|
| 7 - 0 | "00000000" |
proc_err_cnt |
||
| ethercat_reg44 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d820b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
|
| 23 - 16 | "00000000" |
byte_2 |
|
|
| 15 - 12 | "0000" |
res15_12 |
|
|
| 11 | "0" |
mask_sm_status_7 |
||
| 10 | "0" |
mask_sm_status_6 |
||
| 9 | "0" |
mask_sm_status_5 |
||
| 8 | "0" |
mask_sm_status_4 |
||
| 7 | "0" |
mask_sm_status_3 |
||
| 6 | "0" |
mask_sm_status_2 |
||
| 5 | "0" |
mask_sm_status_1 |
||
| 4 | "0" |
mask_sm_status_0 |
||
| 3 | "0" |
mask_al_status_event |
||
| 2 | "0" |
mask_dl_status_event |
||
| 1 | "0" |
res1 |
|
|
| 0 | "0" |
mask_dc_latch_event |
||
| ethercat_reg45 | |||
| R/W |
0x00000000 |
Address : 0x07d820b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg46 | |||
| R/W |
0x00000000 |
Address : 0x07d820b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg47 | |||
| R/W |
0x00000000 |
Address : 0x07d820bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg48 | |||
| R/W |
0x00000000 |
Address : 0x07d820c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg49 | |||
| R/W |
0x00000000 |
Address : 0x07d820c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg50 | |||
| R/W |
0x00000000 |
Address : 0x07d820c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg51 | |||
| R/W |
0x00000000 |
Address : 0x07d820cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg52 | |||
| R/W |
0x00000000 |
Address : 0x07d820d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg53 | |||
| R/W |
0x00000000 |
Address : 0x07d820d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg54 | |||
| R/W |
0x00000000 |
Address : 0x07d820d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg55 | |||
| R/W |
0x00000000 |
Address : 0x07d820dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg56 | |||
| R/W |
0x00000000 |
Address : 0x07d820e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg57 | |||
| R/W |
0x00000000 |
Address : 0x07d820e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg58 | |||
| R/W |
0x00000000 |
Address : 0x07d820e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg59 | |||
| R/W |
0x00000000 |
Address : 0x07d820ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg60 | |||
| R/W |
0x00000000 |
Address : 0x07d820f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg61 | |||
| R/W |
0x00000000 |
Address : 0x07d820f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg62 | |||
| R/W |
0x00000000 |
Address : 0x07d820f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg63 | |||
| R/W |
0x00000000 |
Address : 0x07d820fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg64 | |||||||||||||
| R/W |
0x30303030 |
Address : 0x07d82100 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | "00" |
res31_30 |
|||||||||||
| 29 - 28 | "11" |
sm3_buf_nr |
|
||||||||||
| 27 | "0" |
sm3_buf_full |
|
||||||||||
| 26 | "0" |
res26 |
|||||||||||
| 25 | "0" |
sm3_read_event |
|
||||||||||
| 24 | "0" |
sm3_write_event |
|
||||||||||
| 23 - 22 | "00" |
res23_22 |
|||||||||||
| 21 - 20 | "11" |
sm2_buf_nr |
|
||||||||||
| 19 | "0" |
sm2_buf_full |
|
||||||||||
| 18 | "0" |
res18 |
|||||||||||
| 17 | "0" |
sm2_read_event |
|
||||||||||
| 16 | "0" |
sm2_write_event |
|
||||||||||
| 15 - 14 | "00" |
res15_14 |
|||||||||||
| 13 - 12 | "11" |
sm1_buf_nr |
|
||||||||||
| 11 | "0" |
sm1_buf_full |
|
||||||||||
| 10 | "0" |
res10 |
|||||||||||
| 9 | "0" |
sm1_read_event |
|
||||||||||
| 8 | "0" |
sm1_write_event |
|
||||||||||
| 7 - 6 | "00" |
res7_6 |
|||||||||||
| 5 - 4 | "11" |
sm0_buf_nr |
|
||||||||||
| 3 | "0" |
sm0_buf_full |
|
||||||||||
| 2 | "0" |
res2 |
|||||||||||
| 1 | "0" |
sm0_read_event |
|
||||||||||
| 0 | "0" |
sm0_write_event |
|
||||||||||
| ethercat_reg65 | |||||||||||||
| R/W |
0x30303030 |
Address : 0x07d82104 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | "00" |
res31_30 |
|||||||||||
| 29 - 28 | "11" |
sm7_buf_nr |
|
||||||||||
| 27 | "0" |
sm7_buf_full |
|
||||||||||
| 26 | "0" |
res26 |
|||||||||||
| 25 | "0" |
sm7_read_event |
|
||||||||||
| 24 | "0" |
sm7_write_event |
|
||||||||||
| 23 - 22 | "00" |
res23_22 |
|||||||||||
| 21 - 20 | "11" |
sm6_buf_nr |
|
||||||||||
| 19 | "0" |
sm6_buf_full |
|
||||||||||
| 18 | "0" |
res18 |
|||||||||||
| 17 | "0" |
sm6_read_event |
|
||||||||||
| 16 | "0" |
sm6_write_event |
|
||||||||||
| 15 - 14 | "00" |
res15_14 |
|||||||||||
| 13 - 12 | "11" |
sm5_buf_nr |
|
||||||||||
| 11 | "0" |
sm5_buf_full |
|
||||||||||
| 10 | "0" |
res10 |
|||||||||||
| 9 | "0" |
sm5_read_event |
|
||||||||||
| 8 | "0" |
sm5_write_event |
|
||||||||||
| 7 - 6 | "00" |
res7_6 |
|||||||||||
| 5 - 4 | "11" |
sm4_buf_nr |
|
||||||||||
| 3 | "0" |
sm4_buf_full |
|
||||||||||
| 2 | "0" |
res2 |
|||||||||||
| 1 | "0" |
sm4_read_event |
|
||||||||||
| 0 | "0" |
sm4_write_event |
|
||||||||||
| ethercat_reg66 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d82108 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||||||
| 25 | "0" |
sm3_repeat_ack |
|
|||||
| 24 | "0" |
sm3_dis_by_arm |
|
|||||
| 23 - 18 | "000000" |
res23_18 |
||||||
| 17 | "0" |
sm2_repeat_ack |
|
|||||
| 16 | "0" |
sm2_dis_by_arm |
|
|||||
| 15 - 10 | "000000" |
res15_10 |
||||||
| 9 | "0" |
sm1_repeat_ack |
|
|||||
| 8 | "0" |
sm1_dis_by_arm |
|
|||||
| 7 - 2 | "000000" |
res7_2 |
||||||
| 1 | "0" |
sm0_repeat_ack |
|
|||||
| 0 | "0" |
sm0_dis_by_arm |
|
|||||
| ethercat_reg67 | ||||||||
| R/W |
0x00000000 |
Address : 0x07d8210c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | "000000" |
res31_26 |
||||||
| 25 | "0" |
sm7_repeat_ack |
|
|||||
| 24 | "0" |
sm7_dis_by_arm |
|
|||||
| 23 - 18 | "000000" |
res23_18 |
||||||
| 17 | "0" |
sm6_repeat_ack |
|
|||||
| 16 | "0" |
sm6_dis_by_arm |
|
|||||
| 15 - 10 | "000000" |
res15_10 |
||||||
| 9 | "0" |
sm5_repeat_ack |
|
|||||
| 8 | "0" |
sm5_dis_by_arm |
|
|||||
| 7 - 2 | "000000" |
res7_2 |
||||||
| 1 | "0" |
sm4_repeat_ack |
|
|||||
| 0 | "0" |
sm4_dis_by_arm |
|
|||||
| ethercat_reg68 | |||
| R/W |
0x00000000 |
Address : 0x07d82110 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 0 | 0x0 |
alias_address |
|
| ethercat_reg69 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
trigger_1_starttime_ns |
||
| ethercat_reg70 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82118 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
trigger_1_starttime_s |
||
| ethercat_reg71 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8211c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_0_pos_systime_ns |
||
| ethercat_reg72 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_0_pos_systime_s |
||
| ethercat_reg73 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_0_neg_systime_ns |
||
| ethercat_reg74 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_0_neg_systime_s |
||
| ethercat_reg75 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8212c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_1_pos_systime_ns |
||
| ethercat_reg76 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_1_pos_systime_s |
||
| ethercat_reg77 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_1_neg_systime_ns |
||
| ethercat_reg78 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82138 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sample_1_neg_systime_s |
||
| ethercat_reg79 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8213c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
|
| 23 - 16 | "00000000" |
byte_2 |
|
|
| 15 - 12 | "0000" |
res15_12 |
|
|
| 11 | "0" |
sm_status_7 |
||
| 10 | "0" |
sm_status_6 |
||
| 9 | "0" |
sm_status_5 |
||
| 8 | "0" |
sm_status_4 |
||
| 7 | "0" |
sm_status_3 |
||
| 6 | "0" |
sm_status_2 |
||
| 5 | "0" |
sm_status_1 |
||
| 4 | "0" |
sm_status_0 |
||
| 3 | "0" |
al_status_event |
||
| 2 | "0" |
dl_status_event |
||
| 1 | "0" |
res1 |
|
|
| 0 | "0" |
dc_latch_event |
||
| ethercat_reg80 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
|
| 23 - 16 | "00000000" |
byte_2 |
|
|
| 15 - 0 | 0x0 |
bit15_0 |
||
| ethercat_reg81 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | "00000" |
res31_27 |
|
|
| 26 | "0" |
sample_1_in |
||
| 25 | "0" |
sample_1_negedge_status |
||
| 24 | "0" |
sample_1_posedge_status |
||
| 23 - 19 | "00000" |
res23_19 |
|
|
| 18 | "0" |
sample_0_in |
||
| 17 | "0" |
sample_0_negedge_status |
||
| 16 | "0" |
sample_0_posedge_status |
||
| 15 - 9 | "0000000" |
res15_9 |
|
|
| 8 | "0" |
sync1_status |
||
| 7 - 1 | "0000000" |
res7_1 |
|
|
| 0 | "0" |
sync0_status |
||
| ethercat_reg82 | |||
| R/W |
0x00000000 |
Address : 0x07d82148 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg83 | |||
| R/W |
0x00000000 |
Address : 0x07d8214c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg84 | |||
| R/W |
0x00000000 |
Address : 0x07d82150 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg85 | |||
| R/W |
0x00000000 |
Address : 0x07d82154 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg86 | |||
| R/W |
0x00000000 |
Address : 0x07d82158 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg87 | |||
| R/W |
0x00000000 |
Address : 0x07d8215c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg88 | |||
| R/W |
0x00000000 |
Address : 0x07d82160 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg89 | |||
| R/W |
0x00000000 |
Address : 0x07d82164 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg90 | |||
| R/W |
0x00000000 |
Address : 0x07d82168 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg91 | |||
| R/W |
0x00000000 |
Address : 0x07d8216c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg92 | |||
| R/W |
0x00000000 |
Address : 0x07d82170 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg93 | |||
| R/W |
0x00000000 |
Address : 0x07d82174 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg94 | |||
| R/W |
0x00000000 |
Address : 0x07d82178 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg95 | |||
| R/W |
0x00000000 |
Address : 0x07d8217c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg96 | |||
| R/W |
0x00000000 |
Address : 0x07d82180 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg97 | |||
| R/W |
0x00000000 |
Address : 0x07d82184 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg98 | |||
| R/W |
0x00000000 |
Address : 0x07d82188 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg99 | |||
| R/W |
0x00000000 |
Address : 0x07d8218c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg100 | |||
| R/W |
0x00000000 |
Address : 0x07d82190 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg101 | |||
| R/W |
0x00000000 |
Address : 0x07d82194 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg102 | |||
| R/W |
0x00000000 |
Address : 0x07d82198 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg103 | |||
| R/W |
0x00000000 |
Address : 0x07d8219c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg104 | |||
| R/W |
0x00000000 |
Address : 0x07d821a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg105 | |||
| R/W |
0x00000000 |
Address : 0x07d821a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg106 | |||
| R/W |
0x00000000 |
Address : 0x07d821a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg107 | |||
| R/W |
0x00000000 |
Address : 0x07d821ac |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg108 | |||
| R/W |
0x00000000 |
Address : 0x07d821b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg109 | |||
| R/W |
0x00000000 |
Address : 0x07d821b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg110 | |||
| R/W |
0x00000000 |
Address : 0x07d821b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg111 | |||
| R/W |
0x00000000 |
Address : 0x07d821bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg112 | |||
| R/W |
0x00000000 |
Address : 0x07d821c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg113 | |||
| R/W |
0x00000000 |
Address : 0x07d821c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg114 | |||
| R/W |
0x00000000 |
Address : 0x07d821c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg115 | |||
| R/W |
0x00000000 |
Address : 0x07d821cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg116 | |||
| R/W |
0x00000000 |
Address : 0x07d821d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg117 | |||
| R/W |
0x00000000 |
Address : 0x07d821d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg118 | |||
| R/W |
0x00000000 |
Address : 0x07d821d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg119 | |||
| R/W |
0x00000000 |
Address : 0x07d821dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg120 | |||
| R/W |
0x00000000 |
Address : 0x07d821e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg121 | |||
| R/W |
0x00000000 |
Address : 0x07d821e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg122 | |||
| R/W |
0x00000000 |
Address : 0x07d821e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg123 | |||
| R/W |
0x00000000 |
Address : 0x07d821ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg124 | |||
| R/W |
0x00000000 |
Address : 0x07d821f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg125 | |||
| R/W |
0x00000000 |
Address : 0x07d821f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg126 | |||
| R/W |
0x00000000 |
Address : 0x07d821f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_reg127 | |||
| R/W |
0x00000000 |
Address : 0x07d821fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 24 | "00000000" |
byte_3 |
|
| 23 - 16 | "00000000" |
byte_2 |
|
| 15 - 8 | "00000000" |
byte_1 |
|
| 7 - 0 | "00000000" |
byte_0 |
|
| ethercat_shadow_reg0 |
|
|||
| R |
Address : 0x07d82200 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg0 | |||
| ethercat_shadow_reg1 |
|
|||
| R |
Address : 0x07d82204 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg1 | |||
| ethercat_shadow_reg2 |
|
|||
| R |
Address : 0x07d82208 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg2 | |||
| ethercat_shadow_reg3 |
|
|||
| R |
Address : 0x07d8220c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg3 | |||
| ethercat_shadow_reg4 |
|
|||
| R |
Address : 0x07d82210 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg4 | |||
| ethercat_shadow_reg5 |
|
|||
| R |
Address : 0x07d82214 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg5 | |||
| ethercat_shadow_reg6 |
|
|||
| R |
Address : 0x07d82218 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg6 | |||
| ethercat_shadow_reg7 |
|
|||
| R |
Address : 0x07d8221c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ethercat_shadow_reg7 | |||
| ethercat_shadow_reg8 | |||
| R/W |
0x00000000 |
Address : 0x07d82220 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg9 | |||
| R/W |
0x00000000 |
Address : 0x07d82224 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg10 | |||
| R/W |
0x00000000 |
Address : 0x07d82228 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg11 | |||
| R/W |
0x00000000 |
Address : 0x07d8222c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg12 | |||
| R/W |
0x00000000 |
Address : 0x07d82230 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg13 | |||
| R/W |
0x00000000 |
Address : 0x07d82234 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg14 | |||
| R/W |
0x00000000 |
Address : 0x07d82238 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg15 | |||
| R/W |
0x00000000 |
Address : 0x07d8223c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg16 | |||
| R/W |
0x00000000 |
Address : 0x07d82240 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg17 | |||
| R/W |
0x00000000 |
Address : 0x07d82244 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg18 | |||
| R/W |
0x00000000 |
Address : 0x07d82248 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg19 | |||
| R/W |
0x00000000 |
Address : 0x07d8224c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg20 | |||
| R/W |
0x00000000 |
Address : 0x07d82250 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg21 | |||
| R/W |
0x00000000 |
Address : 0x07d82254 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg22 | |||
| R/W |
0x00000000 |
Address : 0x07d82258 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg23 | |||
| R/W |
0x00000000 |
Address : 0x07d8225c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg24 | |||
| R/W |
0x00000000 |
Address : 0x07d82260 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg25 | |||
| R/W |
0x00000000 |
Address : 0x07d82264 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg26 | |||
| R/W |
0x00000000 |
Address : 0x07d82268 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg27 | |||
| R/W |
0x00000000 |
Address : 0x07d8226c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg28 | |||
| R/W |
0x00000000 |
Address : 0x07d82270 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg29 | |||
| R/W |
0x00000000 |
Address : 0x07d82274 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg30 | |||
| R/W |
0x00000000 |
Address : 0x07d82278 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg31 | |||
| R/W |
0x00000000 |
Address : 0x07d8227c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg32 | |||
| R/W |
0x00000000 |
Address : 0x07d82280 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg33 | |||
| R/W |
0x00000000 |
Address : 0x07d82284 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg34 | |||
| R/W |
0x00000000 |
Address : 0x07d82288 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg35 | |||
| R/W |
0x00000000 |
Address : 0x07d8228c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg36 | |||
| R/W |
0x00000000 |
Address : 0x07d82290 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg37 | |||
| R/W |
0x00000000 |
Address : 0x07d82294 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg38 | |||
| R/W |
0x00000000 |
Address : 0x07d82298 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg39 | |||
| R/W |
0x00000000 |
Address : 0x07d8229c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg40 | |||
| R/W |
0x00000000 |
Address : 0x07d822a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg41 | |||
| R/W |
0x00000000 |
Address : 0x07d822a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg42 | |||
| R/W |
0x00000000 |
Address : 0x07d822a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg43 | |||
| R/W |
0x00000000 |
Address : 0x07d822ac |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg44 | |||
| R/W |
0x00000000 |
Address : 0x07d822b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg45 | |||
| R/W |
0x00000000 |
Address : 0x07d822b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg46 | |||
| R/W |
0x00000000 |
Address : 0x07d822b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg47 | |||
| R/W |
0x00000000 |
Address : 0x07d822bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg48 | |||
| R/W |
0x00000000 |
Address : 0x07d822c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg49 | |||
| R/W |
0x00000000 |
Address : 0x07d822c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg50 | |||
| R/W |
0x00000000 |
Address : 0x07d822c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg51 | |||
| R/W |
0x00000000 |
Address : 0x07d822cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg52 | |||
| R/W |
0x00000000 |
Address : 0x07d822d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg53 | |||
| R/W |
0x00000000 |
Address : 0x07d822d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg54 | |||
| R/W |
0x00000000 |
Address : 0x07d822d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg55 | |||
| R/W |
0x00000000 |
Address : 0x07d822dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg56 | |||
| R/W |
0x00000000 |
Address : 0x07d822e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg57 | |||
| R/W |
0x00000000 |
Address : 0x07d822e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg58 | |||
| R/W |
0x00000000 |
Address : 0x07d822e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg59 | |||
| R/W |
0x00000000 |
Address : 0x07d822ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg60 | |||
| R/W |
0x00000000 |
Address : 0x07d822f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg61 | |||
| R/W |
0x00000000 |
Address : 0x07d822f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg62 | |||
| R/W |
0x00000000 |
Address : 0x07d822f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg63 | |||
| R/W |
0x00000000 |
Address : 0x07d822fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg64 | |||
| R/W |
0x00000000 |
Address : 0x07d82300 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg65 | |||
| R/W |
0x00000000 |
Address : 0x07d82304 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg66 | |||
| R/W |
0x00000000 |
Address : 0x07d82308 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg67 | |||
| R/W |
0x00000000 |
Address : 0x07d8230c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg68 | |||
| R/W |
0x00000000 |
Address : 0x07d82310 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg69 | |||
| R/W |
0x00000000 |
Address : 0x07d82314 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg70 | |||
| R/W |
0x00000000 |
Address : 0x07d82318 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg71 | |||
| R/W |
0x00000000 |
Address : 0x07d8231c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg72 | |||
| R/W |
0x00000000 |
Address : 0x07d82320 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg73 | |||
| R/W |
0x00000000 |
Address : 0x07d82324 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg74 | |||
| R/W |
0x00000000 |
Address : 0x07d82328 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg75 | |||
| R/W |
0x00000000 |
Address : 0x07d8232c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg76 | |||
| R/W |
0x00000000 |
Address : 0x07d82330 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg77 | |||
| R/W |
0x00000000 |
Address : 0x07d82334 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg78 | |||
| R/W |
0x00000000 |
Address : 0x07d82338 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg79 | |||
| R/W |
0x00000000 |
Address : 0x07d8233c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg80 | |||
| R/W |
0x00000000 |
Address : 0x07d82340 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg81 | |||
| R/W |
0x00000000 |
Address : 0x07d82344 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg82 | |||
| R/W |
0x00000000 |
Address : 0x07d82348 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg83 | |||
| R/W |
0x00000000 |
Address : 0x07d8234c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg84 | |||
| R/W |
0x00000000 |
Address : 0x07d82350 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg85 | |||
| R/W |
0x00000000 |
Address : 0x07d82354 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg86 | |||
| R/W |
0x00000000 |
Address : 0x07d82358 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg87 | |||
| R/W |
0x00000000 |
Address : 0x07d8235c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg88 | |||
| R/W |
0x00000000 |
Address : 0x07d82360 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg89 | |||
| R/W |
0x00000000 |
Address : 0x07d82364 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg90 | |||
| R/W |
0x00000000 |
Address : 0x07d82368 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg91 | |||
| R/W |
0x00000000 |
Address : 0x07d8236c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg92 | |||
| R/W |
0x00000000 |
Address : 0x07d82370 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg93 | |||
| R/W |
0x00000000 |
Address : 0x07d82374 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg94 | |||
| R/W |
0x00000000 |
Address : 0x07d82378 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg95 | |||
| R/W |
0x00000000 |
Address : 0x07d8237c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg96 | |||
| R/W |
0x00000000 |
Address : 0x07d82380 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg97 | |||
| R/W |
0x00000000 |
Address : 0x07d82384 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg98 | |||
| R/W |
0x00000000 |
Address : 0x07d82388 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg99 | |||
| R/W |
0x00000000 |
Address : 0x07d8238c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg100 | |||
| R/W |
0x00000000 |
Address : 0x07d82390 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg101 | |||
| R/W |
0x00000000 |
Address : 0x07d82394 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg102 | |||
| R/W |
0x00000000 |
Address : 0x07d82398 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg103 | |||
| R/W |
0x00000000 |
Address : 0x07d8239c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg104 | |||
| R/W |
0x00000000 |
Address : 0x07d823a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg105 | |||
| R/W |
0x00000000 |
Address : 0x07d823a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg106 | |||
| R/W |
0x00000000 |
Address : 0x07d823a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg107 | |||
| R/W |
0x00000000 |
Address : 0x07d823ac |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg108 | |||
| R/W |
0x00000000 |
Address : 0x07d823b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg109 | |||
| R/W |
0x00000000 |
Address : 0x07d823b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg110 | |||
| R/W |
0x00000000 |
Address : 0x07d823b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg111 | |||
| R/W |
0x00000000 |
Address : 0x07d823bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg112 | |||
| R/W |
0x00000000 |
Address : 0x07d823c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg113 | |||
| R/W |
0x00000000 |
Address : 0x07d823c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg114 | |||
| R/W |
0x00000000 |
Address : 0x07d823c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg115 | |||
| R/W |
0x00000000 |
Address : 0x07d823cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg116 | |||
| R/W |
0x00000000 |
Address : 0x07d823d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg117 | |||
| R/W |
0x00000000 |
Address : 0x07d823d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg118 | |||
| R/W |
0x00000000 |
Address : 0x07d823d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg119 | |||
| R/W |
0x00000000 |
Address : 0x07d823dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg120 | |||
| R/W |
0x00000000 |
Address : 0x07d823e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg121 | |||
| R/W |
0x00000000 |
Address : 0x07d823e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg122 | |||
| R/W |
0x00000000 |
Address : 0x07d823e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg123 | |||
| R/W |
0x00000000 |
Address : 0x07d823ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg124 | |||
| R/W |
0x00000000 |
Address : 0x07d823f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg125 | |||
| R/W |
0x00000000 |
Address : 0x07d823f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg126 | |||
| R/W |
0x00000000 |
Address : 0x07d823f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg127 | |||
| R/W |
0x00000000 |
Address : 0x07d823fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg128 | |||
| R/W |
0x00000000 |
Address : 0x07d82400 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg129 | |||
| R/W |
0x00000000 |
Address : 0x07d82404 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg130 | |||
| R/W |
0x00000000 |
Address : 0x07d82408 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg131 | |||
| R/W |
0x00000000 |
Address : 0x07d8240c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg132 | |||
| R/W |
0x00000000 |
Address : 0x07d82410 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg133 | |||
| R/W |
0x00000000 |
Address : 0x07d82414 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg134 | |||
| R/W |
0x00000000 |
Address : 0x07d82418 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg135 | |||
| R/W |
0x00000000 |
Address : 0x07d8241c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg136 | |||
| R/W |
0x00000000 |
Address : 0x07d82420 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg137 | |||
| R/W |
0x00000000 |
Address : 0x07d82424 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg138 | |||
| R/W |
0x00000000 |
Address : 0x07d82428 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg139 | |||
| R/W |
0x00000000 |
Address : 0x07d8242c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg140 | |||
| R/W |
0x00000000 |
Address : 0x07d82430 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg141 | |||
| R/W |
0x00000000 |
Address : 0x07d82434 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg142 | |||
| R/W |
0x00000000 |
Address : 0x07d82438 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg143 | |||
| R/W |
0x00000000 |
Address : 0x07d8243c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg144 | |||
| R/W |
0x00000000 |
Address : 0x07d82440 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg145 | |||
| R/W |
0x00000000 |
Address : 0x07d82444 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg146 | |||
| R/W |
0x00000000 |
Address : 0x07d82448 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg147 | |||
| R/W |
0x00000000 |
Address : 0x07d8244c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg148 | |||
| R/W |
0x00000000 |
Address : 0x07d82450 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg149 | |||
| R/W |
0x00000000 |
Address : 0x07d82454 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg150 | |||
| R/W |
0x00000000 |
Address : 0x07d82458 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg151 | |||
| R/W |
0x00000000 |
Address : 0x07d8245c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg152 | |||
| R/W |
0x00000000 |
Address : 0x07d82460 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg153 | |||
| R/W |
0x00000000 |
Address : 0x07d82464 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg154 | |||
| R/W |
0x00000000 |
Address : 0x07d82468 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg155 | |||
| R/W |
0x00000000 |
Address : 0x07d8246c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg156 | |||
| R/W |
0x00000000 |
Address : 0x07d82470 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg157 | |||
| R/W |
0x00000000 |
Address : 0x07d82474 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg158 | |||
| R/W |
0x00000000 |
Address : 0x07d82478 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg159 | |||
| R/W |
0x00000000 |
Address : 0x07d8247c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg160 | |||
| R/W |
0x00000000 |
Address : 0x07d82480 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg161 | |||
| R/W |
0x00000000 |
Address : 0x07d82484 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg162 | |||
| R/W |
0x00000000 |
Address : 0x07d82488 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg163 | |||
| R/W |
0x00000000 |
Address : 0x07d8248c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg164 | |||
| R/W |
0x00000000 |
Address : 0x07d82490 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg165 | |||
| R/W |
0x00000000 |
Address : 0x07d82494 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg166 | |||
| R/W |
0x00000000 |
Address : 0x07d82498 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg167 | |||
| R/W |
0x00000000 |
Address : 0x07d8249c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg168 | |||
| R/W |
0x00000000 |
Address : 0x07d824a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg169 | |||
| R/W |
0x00000000 |
Address : 0x07d824a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg170 | |||
| R/W |
0x00000000 |
Address : 0x07d824a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg171 | |||
| R/W |
0x00000000 |
Address : 0x07d824ac |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg172 | |||
| R/W |
0x00000000 |
Address : 0x07d824b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg173 | |||
| R/W |
0x00000000 |
Address : 0x07d824b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg174 | |||
| R/W |
0x00000000 |
Address : 0x07d824b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg175 | |||
| R/W |
0x00000000 |
Address : 0x07d824bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg176 | |||
| R/W |
0x00000000 |
Address : 0x07d824c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg177 | |||
| R/W |
0x00000000 |
Address : 0x07d824c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg178 | |||
| R/W |
0x00000000 |
Address : 0x07d824c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg179 | |||
| R/W |
0x00000000 |
Address : 0x07d824cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg180 | |||
| R/W |
0x00000000 |
Address : 0x07d824d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg181 | |||
| R/W |
0x00000000 |
Address : 0x07d824d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg182 | |||
| R/W |
0x00000000 |
Address : 0x07d824d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg183 | |||
| R/W |
0x00000000 |
Address : 0x07d824dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg184 | |||
| R/W |
0x00000000 |
Address : 0x07d824e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg185 | |||
| R/W |
0x00000000 |
Address : 0x07d824e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg186 | |||
| R/W |
0x00000000 |
Address : 0x07d824e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg187 | |||
| R/W |
0x00000000 |
Address : 0x07d824ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg188 | |||
| R/W |
0x00000000 |
Address : 0x07d824f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg189 | |||
| R/W |
0x00000000 |
Address : 0x07d824f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg190 | |||
| R/W |
0x00000000 |
Address : 0x07d824f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg191 | |||
| R/W |
0x00000000 |
Address : 0x07d824fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg192 | |||
| R/W |
0x00000000 |
Address : 0x07d82500 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg193 | |||
| R/W |
0x00000000 |
Address : 0x07d82504 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg194 | |||
| R/W |
0x00000000 |
Address : 0x07d82508 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg195 | |||
| R/W |
0x00000000 |
Address : 0x07d8250c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg196 | |||
| R/W |
0x00000000 |
Address : 0x07d82510 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg197 | |||
| R/W |
0x00000000 |
Address : 0x07d82514 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg198 | |||
| R/W |
0x00000000 |
Address : 0x07d82518 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg199 | |||
| R/W |
0x00000000 |
Address : 0x07d8251c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg200 | |||
| R/W |
0x00000000 |
Address : 0x07d82520 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg201 | |||
| R/W |
0x00000000 |
Address : 0x07d82524 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg202 | |||
| R/W |
0x00000000 |
Address : 0x07d82528 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg203 | |||
| R/W |
0x00000000 |
Address : 0x07d8252c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg204 | |||
| R/W |
0x00000000 |
Address : 0x07d82530 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg205 | |||
| R/W |
0x00000000 |
Address : 0x07d82534 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg206 | |||
| R/W |
0x00000000 |
Address : 0x07d82538 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg207 | |||
| R/W |
0x00000000 |
Address : 0x07d8253c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg208 | |||
| R/W |
0x00000000 |
Address : 0x07d82540 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg209 | |||
| R/W |
0x00000000 |
Address : 0x07d82544 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg210 | |||
| R/W |
0x00000000 |
Address : 0x07d82548 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg211 | |||
| R/W |
0x00000000 |
Address : 0x07d8254c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg212 | |||
| R/W |
0x00000000 |
Address : 0x07d82550 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg213 | |||
| R/W |
0x00000000 |
Address : 0x07d82554 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg214 | |||
| R/W |
0x00000000 |
Address : 0x07d82558 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg215 | |||
| R/W |
0x00000000 |
Address : 0x07d8255c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg216 | |||
| R/W |
0x00000000 |
Address : 0x07d82560 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg217 | |||
| R/W |
0x00000000 |
Address : 0x07d82564 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg218 | |||
| R/W |
0x00000000 |
Address : 0x07d82568 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg219 | |||
| R/W |
0x00000000 |
Address : 0x07d8256c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg220 | |||
| R/W |
0x00000000 |
Address : 0x07d82570 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg221 | |||
| R/W |
0x00000000 |
Address : 0x07d82574 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg222 | |||
| R/W |
0x00000000 |
Address : 0x07d82578 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg223 | |||
| R/W |
0x00000000 |
Address : 0x07d8257c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg224 | |||
| R/W |
0x00000000 |
Address : 0x07d82580 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg225 | |||
| R/W |
0x00000000 |
Address : 0x07d82584 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg226 | |||
| R/W |
0x00000000 |
Address : 0x07d82588 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg227 | |||
| R/W |
0x00000000 |
Address : 0x07d8258c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg228 | |||
| R/W |
0x00000000 |
Address : 0x07d82590 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg229 | |||
| R/W |
0x00000000 |
Address : 0x07d82594 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg230 | |||
| R/W |
0x00000000 |
Address : 0x07d82598 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg231 | |||
| R/W |
0x00000000 |
Address : 0x07d8259c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg232 | |||
| R/W |
0x00000000 |
Address : 0x07d825a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg233 | |||
| R/W |
0x00000000 |
Address : 0x07d825a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg234 | |||
| R/W |
0x00000000 |
Address : 0x07d825a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg235 | |||
| R/W |
0x00000000 |
Address : 0x07d825ac |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg236 | |||
| R/W |
0x00000000 |
Address : 0x07d825b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg237 | |||
| R/W |
0x00000000 |
Address : 0x07d825b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg238 | |||
| R/W |
0x00000000 |
Address : 0x07d825b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg239 | |||
| R/W |
0x00000000 |
Address : 0x07d825bc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg240 | |||
| R/W |
0x00000000 |
Address : 0x07d825c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg241 | |||
| R/W |
0x00000000 |
Address : 0x07d825c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg242 | |||
| R/W |
0x00000000 |
Address : 0x07d825c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg243 | |||
| R/W |
0x00000000 |
Address : 0x07d825cc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg244 | |||
| R/W |
0x00000000 |
Address : 0x07d825d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg245 | |||
| R/W |
0x00000000 |
Address : 0x07d825d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg246 | |||
| R/W |
0x00000000 |
Address : 0x07d825d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg247 | |||
| R/W |
0x00000000 |
Address : 0x07d825dc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg248 | |||
| R/W |
0x00000000 |
Address : 0x07d825e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg249 | |||
| R/W |
0x00000000 |
Address : 0x07d825e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg250 | |||
| R/W |
0x00000000 |
Address : 0x07d825e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg251 | |||
| R/W |
0x00000000 |
Address : 0x07d825ec |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg252 | |||
| R/W |
0x00000000 |
Address : 0x07d825f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg253 | |||
| R/W |
0x00000000 |
Address : 0x07d825f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg254 | |||
| R/W |
0x00000000 |
Address : 0x07d825f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_shadow_reg255 | |||
| R/W |
0x00000000 |
Address : 0x07d825fc |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved |
| 8 | "0" |
write |
|
| 7 - 0 | "00000000" |
byte |
|
| ethercat_config | ||||
| R/W |
0x00000000 |
Address : 0x07d82600 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
gpec |
|
|
| ethercat_info |
|
|||
| R |
Address : 0x07d82604 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| ethercat_phys_addr_offset |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8260c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
phys_addr_offset_register_area |
|
|
| 15 - 0 | 0x0 |
phys_addr_offset |
|
|
| ethercat_phys_last_addr | ||||
| R/W |
0x00001fff |
Address : 0x07d82610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | "00" |
sm7_cfg_add |
|
|
| 29 - 28 | "00" |
sm6_cfg_add |
|
|
| 27 - 26 | "00" |
sm5_cfg_add |
|
|
| 25 - 24 | "00" |
sm4_cfg_add |
|
|
| 23 - 22 | "00" |
sm3_cfg_add |
|
|
| 21 - 20 | "00" |
sm2_cfg_add |
|
|
| 19 - 18 | "00" |
sm1_cfg_add |
|
|
| 17 - 16 | "00" |
sm0_cfg_add |
|
|
| 15 - 0 | 0x1fff |
phys_last_addr |
|
|
| ethercat_sm_not_write_allowed_addr |
|
|||
| R/W |
0x00001fff |
Address : 0x07d82614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 - 0 | 0x1fff |
val |
||
| ethercat_fmmusm_read_addr_in |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82618 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
read_adr |
|
|
| ethercat_fmmusm_write_addr_in |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8261c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
write_adr |
|
|
| ethercat_sm_read_addr_out |
|
|||
| R |
Address : 0x07d82620 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 - 0 | sm_read_adr_out |
|
||
| ethercat_sm_write_addr_out |
|
|||
| R |
Address : 0x07d82624 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 - 0 | sm_write_adr_out |
|
||
| ethercat_fmmu_read_bit_rol_pos |
|
|||
| R |
Address : 0x07d82628 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 8 | fmmu_read_bit_mask |
|
||
| 7 - 5 | fmmu_read_bit_maskmode |
|
||
| 4 - 0 | fmmu_read_bit_rol |
|
||
| ethercat_fmmu_read_bit_mask |
|
||||||||
| R |
Address : 0x07d8262c |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | - |
reserved | |||||||
| 7 - 0 | fmmu_read_bit_mask |
|
|||||||
| ethercat_fmmu_write_bit_rol_pos |
|
|||
| R |
Address : 0x07d82630 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 8 | fmmu_write_bit_mask |
|
||
| 7 - 5 | fmmu_write_bit_maskmode |
|
||
| 4 - 0 | fmmu_write_bit_rol |
|
||
| ethercat_fmmu_write_bit_mask |
|
||||||||
| R |
Address : 0x07d82634 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | - |
reserved | |||||||
| 7 - 0 | fmmu_write_bit_mask |
|
|||||||
| ethercat_fmmusm_len_en |
|
|||||||
| R/W |
0x00000000 |
Address : 0x07d82638 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||
| 18 | "0" |
wr_en |
|
|||||
| 17 | "0" |
rd_en |
|
|||||
| 16 | "0" |
log_addr_en |
|
|||||
| 15 - 0 | 0x0 |
ecat_len |
|
|||||
| ethercat_fmmusm_status_out |
|
||||||
| R |
Address : 0x07d8263c |
Bits | Name | Description | |||
|---|---|---|---|---|---|---|---|
| 31 | ecat_fin |
|
|||||
| 30 | allowed |
|
|||||
| 29 | allowed_bitwise |
|
|||||
| 28 - 26 | - |
reserved | |||||
| 25 | write_fmmu_match_bitwise |
|
|||||
| 24 | read_fmmu_match_bitwise |
|
|||||
| 23 | write_fmmu_no_match |
|
|||||
| 22 - 20 | write_fmmu_match_nr |
|
|||||
| 19 | read_fmmu_no_match |
|
|||||
| 18 - 16 | read_fmmu_match_nr |
|
|||||
| 15 | write_allowed_bitwise |
|
|||||
| 14 | write_allowed |
|
|||||
| 13 | write_sm_lba |
|
|||||
| 12 | write_sm_fba |
|
|||||
| 11 | write_sm_no_match |
|
|||||
| 10 - 8 | write_sm_nr |
|
|||||
| 7 | read_allowed_bitwise |
|
|||||
| 6 | read_allowed |
|
|||||
| 5 | read_sm_lba |
|
|||||
| 4 | read_sm_fba |
|
|||||
| 3 | read_sm_no_match |
|
|||||
| 2 - 0 | read_sm_nr |
|
|||||
| ethercat_sm_buf_statcfg |
|
|||
| R/W |
0x00ffff00 |
Address : 0x07d82640 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
buf_mask7 |
|
|
| 30 | "0" |
buf_mask6 |
|
|
| 29 | "0" |
buf_mask5 |
|
|
| 28 | "0" |
buf_mask4 |
|
|
| 27 | "0" |
buf_mask3 |
|
|
| 26 | "0" |
buf_mask2 |
|
|
| 25 | "0" |
buf_mask1 |
|
|
| 24 | "0" |
buf_mask0 |
|
|
| 23 - 22 | "11" |
buf_nr_7 |
|
|
| 21 - 20 | "11" |
buf_nr_6 |
|
|
| 19 - 18 | "11" |
buf_nr_5 |
|
|
| 17 - 16 | "11" |
buf_nr_4 |
|
|
| 15 - 14 | "11" |
buf_nr_3 |
|
|
| 13 - 12 | "11" |
buf_nr_2 |
|
|
| 11 - 10 | "11" |
buf_nr_1 |
|
|
| 9 - 8 | "11" |
buf_nr_0 |
|
|
| 7 | "0" |
buf_full_7 |
|
|
| 6 | "0" |
buf_full_6 |
|
|
| 5 | "0" |
buf_full_5 |
|
|
| 4 | "0" |
buf_full_4 |
|
|
| 3 | "0" |
buf_full_3 |
|
|
| 2 | "0" |
buf_full_2 |
|
|
| 1 | "0" |
buf_full_1 |
|
|
| 0 | "0" |
buf_full_0 |
|
|
| ethercat_sm_read_event |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82644 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
read_event_mask7 |
|
|
| 22 | "0" |
read_event_mask6 |
|
|
| 21 | "0" |
read_event_mask5 |
|
|
| 20 | "0" |
read_event_mask4 |
|
|
| 19 | "0" |
read_event_mask3 |
|
|
| 18 | "0" |
read_event_mask2 |
|
|
| 17 | "0" |
read_event_mask1 |
|
|
| 16 | "0" |
read_event_mask0 |
|
|
| 15 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
read_event_7 |
|
|
| 6 | "0" |
read_event_6 |
|
|
| 5 | "0" |
read_event_5 |
|
|
| 4 | "0" |
read_event_4 |
|
|
| 3 | "0" |
read_event_3 |
|
|
| 2 | "0" |
read_event_2 |
|
|
| 1 | "0" |
read_event_1 |
|
|
| 0 | "0" |
read_event_0 |
|
|
| ethercat_sm_write_event |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82648 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
write_event_mask7 |
|
|
| 22 | "0" |
write_event_mask6 |
|
|
| 21 | "0" |
write_event_mask5 |
|
|
| 20 | "0" |
write_event_mask4 |
|
|
| 19 | "0" |
write_event_mask3 |
|
|
| 18 | "0" |
write_event_mask2 |
|
|
| 17 | "0" |
write_event_mask1 |
|
|
| 16 | "0" |
write_event_mask0 |
|
|
| 15 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
write_event_7 |
|
|
| 6 | "0" |
write_event_6 |
|
|
| 5 | "0" |
write_event_5 |
|
|
| 4 | "0" |
write_event_4 |
|
|
| 3 | "0" |
write_event_3 |
|
|
| 2 | "0" |
write_event_2 |
|
|
| 1 | "0" |
write_event_1 |
|
|
| 0 | "0" |
write_event_0 |
|
|
| ethercat_sm_first_byte_addressed |
|
|||||||
| R/W |
0x00000000 |
Address : 0x07d8264c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 30 | "00" |
buf_nr_3 |
|
|||||
| 29 | "0" |
buf_full_3 |
|
|||||
| 28 | 0 |
- |
reserved | |||||
| 27 | "0" |
read_event_3 |
|
|||||
| 26 | "0" |
write_event_3 |
|
|||||
| 25 - 24 | "00" |
buf_nr_2 |
|
|||||
| 23 | "0" |
buf_full_2 |
|
|||||
| 22 | 0 |
- |
reserved | |||||
| 21 | "0" |
read_event_2 |
|
|||||
| 20 | "0" |
write_event_2 |
|
|||||
| 19 - 18 | "00" |
buf_nr_1 |
|
|||||
| 17 | "0" |
buf_full_1 |
|
|||||
| 16 | 0 |
- |
reserved | |||||
| 15 | "0" |
read_event_1 |
|
|||||
| 14 | "0" |
write_event_1 |
|
|||||
| 13 - 12 | "00" |
buf_nr_0 |
|
|||||
| 11 | "0" |
buf_full_0 |
|
|||||
| 10 | 0 |
- |
reserved | |||||
| 9 | "0" |
read_event_0 |
|
|||||
| 8 | "0" |
write_event_0 |
|
|||||
| 7 | "0" |
fba_7 |
|
|||||
| 6 | "0" |
fba_6 |
|
|||||
| 5 | "0" |
fba_5 |
|
|||||
| 4 | "0" |
fba_4 |
|
|||||
| 3 | "0" |
fba_3 |
|
|||||
| 2 | "0" |
fba_2 |
|
|||||
| 1 | "0" |
fba_1 |
|
|||||
| 0 | "0" |
fba_0 |
|
|||||
| ethercat_sm_last_byte_addressed |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82650 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | "00" |
buf_nr_7 |
|
|
| 29 | "0" |
buf_full_7 |
|
|
| 28 | 0 |
- |
reserved | |
| 27 | "0" |
read_event_7 |
|
|
| 26 | "0" |
write_event_7 |
|
|
| 25 - 24 | "00" |
buf_nr_6 |
|
|
| 23 | "0" |
buf_full_6 |
|
|
| 22 | 0 |
- |
reserved | |
| 21 | "0" |
read_event_6 |
|
|
| 20 | "0" |
write_event_6 |
|
|
| 19 - 18 | "00" |
buf_nr_5 |
|
|
| 17 | "0" |
buf_full_5 |
|
|
| 16 | 0 |
- |
reserved | |
| 15 | "0" |
read_event_5 |
|
|
| 14 | "0" |
write_event_5 |
|
|
| 13 - 12 | "00" |
buf_nr_4 |
|
|
| 11 | "0" |
buf_full_4 |
|
|
| 10 | 0 |
- |
reserved | |
| 9 | "0" |
read_event_4 |
|
|
| 8 | "0" |
write_event_4 |
|
|
| 7 | "0" |
lba_7 |
|
|
| 6 | "0" |
lba_6 |
|
|
| 5 | "0" |
lba_5 |
|
|
| 4 | "0" |
lba_4 |
|
|
| 3 | "0" |
lba_3 |
|
|
| 2 | "0" |
lba_2 |
|
|
| 1 | "0" |
lba_1 |
|
|
| 0 | "0" |
lba_0 |
|
|
| ethercat_sm_served |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82654 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
any_proc_write_match |
|
|
| 8 | "0" |
any_proc_read_match |
|
|
| 7 | "0" |
srvd_7 |
|
|
| 6 | "0" |
srvd_6 |
|
|
| 5 | "0" |
srvd_5 |
|
|
| 4 | "0" |
srvd_4 |
|
|
| 3 | "0" |
srvd_3 |
|
|
| 2 | "0" |
srvd_2 |
|
|
| 1 | "0" |
srvd_1 |
|
|
| 0 | "0" |
srvd_0 |
|
|
| ethercat_event_req | ||||
| R/W |
0x00000000 |
Address : 0x07d82658 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
write_mask |
|
|
| 15 - 12 | "0000" |
res15_12 |
||
| 11 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
al_status_event |
||
| 2 | "0" |
dl_status_event |
||
| 1 | "0" |
bit1 |
||
| 0 | 0 |
- |
reserved | |
| ethercat_dl_stat | ||||
| R/W |
0x00000000 |
Address : 0x07d8265c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
write_mask |
|
|
| 15 - 0 | 0x0 |
bit15_0 |
||
| gxc_pfifo_config_mask |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82800 Address@gxc_pfifo1_config : 0x07d82880 Address@gxc_pfifo2_config : 0x07d82900 Address@gxc_pfifo3_config : 0x07d82980 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gxc_pfifo_config_ab_sel |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82804 Address@gxc_pfifo1_config : 0x07d82884 Address@gxc_pfifo2_config : 0x07d82904 Address@gxc_pfifo3_config : 0x07d82984 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||
| 15 - 0 | 0x0 |
val |
|
|||||
| gxc_pfifo_config_nempty_masked_a |
|
|||
| R |
Address@gxc_pfifo0_config : 0x07d82808 Address@gxc_pfifo1_config : 0x07d82888 Address@gxc_pfifo2_config : 0x07d82908 Address@gxc_pfifo3_config : 0x07d82988 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| gxc_pfifo_config_nempty_masked_b |
|
|||
| R |
Address@gxc_pfifo0_config : 0x07d8280c Address@gxc_pfifo1_config : 0x07d8288c Address@gxc_pfifo2_config : 0x07d8290c Address@gxc_pfifo3_config : 0x07d8298c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| gxc_pfifo_config_irq |
|
|||
| R |
Address@gxc_pfifo0_config : 0x07d82810 Address@gxc_pfifo1_config : 0x07d82890 Address@gxc_pfifo2_config : 0x07d82910 Address@gxc_pfifo3_config : 0x07d82990 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 - 8 | pfifo_irq_num_b |
|
||
| 7 - 5 | - |
reserved | ||
| 4 - 0 | pfifo_irq_num_a |
|
||
| gxc_pfifo_config_event_sel |
|
|||||||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82814 Address@gxc_pfifo1_config : 0x07d82894 Address@gxc_pfifo2_config : 0x07d82914 Address@gxc_pfifo3_config : 0x07d82994 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |||||
| 17 | "0" |
rate_limiter1_en |
|
|||||
| 16 | "0" |
rate_limiter0_en |
|
|||||
| 15 - 0 | 0x0 |
val |
|
|||||
| gxc_pfifo_config_prio_lock |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82818 Address@gxc_pfifo1_config : 0x07d82898 Address@gxc_pfifo2_config : 0x07d82918 Address@gxc_pfifo3_config : 0x07d82998 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
lock |
|
|
| 3 - 0 | "0000" |
nr |
|
|
| gxc_pfifo_config_queue_nempty_man |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d8281c Address@gxc_pfifo1_config : 0x07d8289c Address@gxc_pfifo2_config : 0x07d8291c Address@gxc_pfifo3_config : 0x07d8299c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gxc_pfifo_config_queue_nempty_sel |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82820 Address@gxc_pfifo1_config : 0x07d828a0 Address@gxc_pfifo2_config : 0x07d82920 Address@gxc_pfifo3_config : 0x07d829a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | "00" |
sel15 |
|
|
| 29 - 28 | "00" |
sel14 |
|
|
| 27 - 26 | "00" |
sel13 |
|
|
| 25 - 24 | "00" |
sel12 |
|
|
| 23 - 22 | "00" |
sel11 |
|
|
| 21 - 20 | "00" |
sel10 |
|
|
| 19 - 18 | "00" |
sel9 |
|
|
| 17 - 16 | "00" |
sel8 |
|
|
| 15 - 14 | "00" |
sel7 |
|
|
| 13 - 12 | "00" |
sel6 |
|
|
| 11 - 10 | "00" |
sel5 |
|
|
| 9 - 8 | "00" |
sel4 |
|
|
| 7 - 6 | "00" |
sel3 |
|
|
| 5 - 4 | "00" |
sel2 |
|
|
| 3 - 2 | "00" |
sel1 |
|
|
| 1 - 0 | "00" |
sel0 |
|
|
| gxc_pfifo_config_border0 |
|
|||
| R/W |
0x000000ff |
Address@gxc_pfifo0_config : 0x07d82824 Address@gxc_pfifo1_config : 0x07d828a4 Address@gxc_pfifo2_config : 0x07d82924 Address@gxc_pfifo3_config : 0x07d829a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xff |
border |
|
|
| gxc_pfifo_config_border1 |
|
|||
| R/W |
0x000001ff |
Address@gxc_pfifo0_config : 0x07d82828 Address@gxc_pfifo1_config : 0x07d828a8 Address@gxc_pfifo2_config : 0x07d82928 Address@gxc_pfifo3_config : 0x07d829a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x1ff |
border |
|
|
| gxc_pfifo_config_border2 |
|
|||
| R/W |
0x000002ff |
Address@gxc_pfifo0_config : 0x07d8282c Address@gxc_pfifo1_config : 0x07d828ac Address@gxc_pfifo2_config : 0x07d8292c Address@gxc_pfifo3_config : 0x07d829ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x2ff |
border |
|
|
| gxc_pfifo_config_border3 |
|
|||
| R/W |
0x000003ff |
Address@gxc_pfifo0_config : 0x07d82830 Address@gxc_pfifo1_config : 0x07d828b0 Address@gxc_pfifo2_config : 0x07d82930 Address@gxc_pfifo3_config : 0x07d829b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x3ff |
border |
|
|
| gxc_pfifo_config_border4 |
|
|||
| R/W |
0x000004ff |
Address@gxc_pfifo0_config : 0x07d82834 Address@gxc_pfifo1_config : 0x07d828b4 Address@gxc_pfifo2_config : 0x07d82934 Address@gxc_pfifo3_config : 0x07d829b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x4ff |
border |
|
|
| gxc_pfifo_config_border5 |
|
|||
| R/W |
0x000005ff |
Address@gxc_pfifo0_config : 0x07d82838 Address@gxc_pfifo1_config : 0x07d828b8 Address@gxc_pfifo2_config : 0x07d82938 Address@gxc_pfifo3_config : 0x07d829b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x5ff |
border |
|
|
| gxc_pfifo_config_border6 |
|
|||
| R/W |
0x000006ff |
Address@gxc_pfifo0_config : 0x07d8283c Address@gxc_pfifo1_config : 0x07d828bc Address@gxc_pfifo2_config : 0x07d8293c Address@gxc_pfifo3_config : 0x07d829bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x6ff |
border |
|
|
| gxc_pfifo_config_border7 |
|
|||
| R/W |
0x000007ff |
Address@gxc_pfifo0_config : 0x07d82840 Address@gxc_pfifo1_config : 0x07d828c0 Address@gxc_pfifo2_config : 0x07d82940 Address@gxc_pfifo3_config : 0x07d829c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x7ff |
border |
|
|
| gxc_pfifo_config_border8 |
|
|||
| R/W |
0x000008ff |
Address@gxc_pfifo0_config : 0x07d82844 Address@gxc_pfifo1_config : 0x07d828c4 Address@gxc_pfifo2_config : 0x07d82944 Address@gxc_pfifo3_config : 0x07d829c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x8ff |
border |
|
|
| gxc_pfifo_config_border9 |
|
|||
| R/W |
0x000009ff |
Address@gxc_pfifo0_config : 0x07d82848 Address@gxc_pfifo1_config : 0x07d828c8 Address@gxc_pfifo2_config : 0x07d82948 Address@gxc_pfifo3_config : 0x07d829c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x9ff |
border |
|
|
| gxc_pfifo_config_border10 |
|
|||
| R/W |
0x00000aff |
Address@gxc_pfifo0_config : 0x07d8284c Address@gxc_pfifo1_config : 0x07d828cc Address@gxc_pfifo2_config : 0x07d8294c Address@gxc_pfifo3_config : 0x07d829cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xaff |
border |
|
|
| gxc_pfifo_config_border11 |
|
|||
| R/W |
0x00000bff |
Address@gxc_pfifo0_config : 0x07d82850 Address@gxc_pfifo1_config : 0x07d828d0 Address@gxc_pfifo2_config : 0x07d82950 Address@gxc_pfifo3_config : 0x07d829d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xbff |
border |
|
|
| gxc_pfifo_config_border12 |
|
|||
| R/W |
0x00000cff |
Address@gxc_pfifo0_config : 0x07d82854 Address@gxc_pfifo1_config : 0x07d828d4 Address@gxc_pfifo2_config : 0x07d82954 Address@gxc_pfifo3_config : 0x07d829d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xcff |
border |
|
|
| gxc_pfifo_config_border13 |
|
|||
| R/W |
0x00000dff |
Address@gxc_pfifo0_config : 0x07d82858 Address@gxc_pfifo1_config : 0x07d828d8 Address@gxc_pfifo2_config : 0x07d82958 Address@gxc_pfifo3_config : 0x07d829d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xdff |
border |
|
|
| gxc_pfifo_config_border14 |
|
|||
| R/W |
0x00000eff |
Address@gxc_pfifo0_config : 0x07d8285c Address@gxc_pfifo1_config : 0x07d828dc Address@gxc_pfifo2_config : 0x07d8295c Address@gxc_pfifo3_config : 0x07d829dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xeff |
border |
|
|
| gxc_pfifo_config_border15 |
|
|||
| R/W |
0x00000fff |
Address@gxc_pfifo0_config : 0x07d82860 Address@gxc_pfifo1_config : 0x07d828e0 Address@gxc_pfifo2_config : 0x07d82960 Address@gxc_pfifo3_config : 0x07d829e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0xfff |
border |
|
|
| gxc_pfifo_config_nempty_irq_sel0 |
|
|||
| R/W |
0x88888888 |
Address@gxc_pfifo0_config : 0x07d82864 Address@gxc_pfifo1_config : 0x07d828e4 Address@gxc_pfifo2_config : 0x07d82964 Address@gxc_pfifo3_config : 0x07d829e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "1000" |
irq_nr_fifo7 |
|
|
| 27 - 24 | "1000" |
irq_nr_fifo6 |
|
|
| 23 - 20 | "1000" |
irq_nr_fifo5 |
|
|
| 19 - 16 | "1000" |
irq_nr_fifo4 |
|
|
| 15 - 12 | "1000" |
irq_nr_fifo3 |
|
|
| 11 - 8 | "1000" |
irq_nr_fifo2 |
|
|
| 7 - 4 | "1000" |
irq_nr_fifo1 |
|
|
| 3 - 0 | "1000" |
irq_nr_fifo0 |
|
|
| gxc_pfifo_config_nempty_irq_sel1 |
|
|||
| R/W |
0x88888888 |
Address@gxc_pfifo0_config : 0x07d82868 Address@gxc_pfifo1_config : 0x07d828e8 Address@gxc_pfifo2_config : 0x07d82968 Address@gxc_pfifo3_config : 0x07d829e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "1000" |
irq_nr_fifo15 |
|
|
| 27 - 24 | "1000" |
irq_nr_fifo14 |
|
|
| 23 - 20 | "1000" |
irq_nr_fifo13 |
|
|
| 19 - 16 | "1000" |
irq_nr_fifo12 |
|
|
| 15 - 12 | "1000" |
irq_nr_fifo11 |
|
|
| 11 - 8 | "1000" |
irq_nr_fifo10 |
|
|
| 7 - 4 | "1000" |
irq_nr_fifo9 |
|
|
| 3 - 0 | "1000" |
irq_nr_fifo8 |
|
|
| gxc_pfifo_config_irq_raw |
|
|||
| R |
Address@gxc_pfifo0_config : 0x07d8286c Address@gxc_pfifo1_config : 0x07d828ec Address@gxc_pfifo2_config : 0x07d8296c Address@gxc_pfifo3_config : 0x07d829ec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | nempty_prio_7 |
|
||
| 6 | nempty_prio_6 |
|
||
| 5 | nempty_prio_5 |
|
||
| 4 | nempty_prio_4 |
|
||
| 3 | nempty_prio_3 |
|
||
| 2 | nempty_prio_2 |
|
||
| 1 | nempty_prio_1 |
|
||
| 0 | nempty_prio_0 |
|
||
| gxc_pfifo_config_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82870 Address@gxc_pfifo1_config : 0x07d828f0 Address@gxc_pfifo2_config : 0x07d82970 Address@gxc_pfifo3_config : 0x07d829f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
nempty_prio_7 |
|
|
| 6 | "0" |
nempty_prio_6 |
|
|
| 5 | "0" |
nempty_prio_5 |
|
|
| 4 | "0" |
nempty_prio_4 |
|
|
| 3 | "0" |
nempty_prio_3 |
|
|
| 2 | "0" |
nempty_prio_2 |
|
|
| 1 | "0" |
nempty_prio_1 |
|
|
| 0 | "0" |
nempty_prio_0 |
|
|
| gxc_pfifo_config_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82874 Address@gxc_pfifo1_config : 0x07d828f4 Address@gxc_pfifo2_config : 0x07d82974 Address@gxc_pfifo3_config : 0x07d829f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
nempty_prio_7 |
|
|
| 6 | "0" |
nempty_prio_6 |
|
|
| 5 | "0" |
nempty_prio_5 |
|
|
| 4 | "0" |
nempty_prio_4 |
|
|
| 3 | "0" |
nempty_prio_3 |
|
|
| 2 | "0" |
nempty_prio_2 |
|
|
| 1 | "0" |
nempty_prio_1 |
|
|
| 0 | "0" |
nempty_prio_0 |
|
|
| gxc_pfifo_config_irq_mask_rst |
|
|||
| R/W |
0x00000000 |
Address@gxc_pfifo0_config : 0x07d82878 Address@gxc_pfifo1_config : 0x07d828f8 Address@gxc_pfifo2_config : 0x07d82978 Address@gxc_pfifo3_config : 0x07d829f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
nempty_prio_7 |
|
|
| 6 | "0" |
nempty_prio_6 |
|
|
| 5 | "0" |
nempty_prio_5 |
|
|
| 4 | "0" |
nempty_prio_4 |
|
|
| 3 | "0" |
nempty_prio_3 |
|
|
| 2 | "0" |
nempty_prio_2 |
|
|
| 1 | "0" |
nempty_prio_1 |
|
|
| 0 | "0" |
nempty_prio_0 |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_int_phy_ctrl_led_cfg |
| 1 | 4 | R/W | gxc_int_phy_ctrl_led_blink_cfg01 |
| 2 | 8 | R/W | gxc_int_phy_ctrl_led_blink_seq01 |
| 3 | c | R/W | gxc_int_phy_ctrl_led_blink_cfg23 |
| 4 | 10 | R/W | gxc_int_phy_ctrl_led_blink_seq23 |
| 5 | 14 | R/W | gxc_int_phy_ctrl_led0_cfg |
| 6 | 18 | R/W | gxc_int_phy_ctrl_led1_cfg |
| 7 | 1c | R/W | gxc_int_phy_ctrl_led2_cfg |
| 8 | 20 | R/W | gxc_int_phy_ctrl_led3_cfg |
| 9 | 24 | R/W | gxc_int_phy_ctrl_led |
| a | 28 | R/W | gxc_int_phy_ctrl_enhanced_link_detection0 |
| b | 2c | R/W | gxc_int_phy_ctrl_enhanced_link_detection1 |
| c-f | 30-3c | - | reserved |
| gxc_int_phy_ctrl_led_cfg |
|
|||||||||||
| R/W |
0x00000001 |
Address@gxc_phy_ctrl0 : 0x07d82a00 Address@gxc_phy_ctrl1 : 0x07d82a40 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |||||||||
| 11 | "0" |
man3 |
|
|||||||||
| 10 | "0" |
man2 |
|
|||||||||
| 9 | "0" |
man1 |
|
|||||||||
| 8 | "0" |
man0 |
|
|||||||||
| 7 - 6 | 0 |
- |
reserved | |||||||||
| 5 - 4 | - |
speed_ro |
|
|||||||||
| 3 | - |
link_ro |
|
|||||||||
| 2 | - |
duplex_ro |
|
|||||||||
| 1 | - |
rx_tx_active_ro |
|
|||||||||
| 0 | "1" |
legacy_enable |
|
|||||||||
| gxc_int_phy_ctrl_led_blink_cfg01 |
|
||||||||||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a04 Address@gxc_phy_ctrl1 : 0x07d82a44 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||||
| 11 - 8 | "0000" |
blink_len |
|
||||||||
| 7 - 4 | 0 |
- |
reserved | ||||||||
| 3 - 0 | "0000" |
period |
|
||||||||
| gxc_int_phy_ctrl_led_blink_seq01 |
|
|||
| R/W |
0x00000001 |
Address@gxc_phy_ctrl0 : 0x07d82a08 Address@gxc_phy_ctrl1 : 0x07d82a48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x1 |
val |
|
|
| gxc_int_phy_ctrl_led_blink_cfg23 |
|
||||||||||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a0c Address@gxc_phy_ctrl1 : 0x07d82a4c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||||
| 11 - 8 | "0000" |
blink_len |
|
||||||||
| 7 - 4 | 0 |
- |
reserved | ||||||||
| 3 - 0 | "0000" |
period |
|
||||||||
| gxc_int_phy_ctrl_led_blink_seq23 |
|
|||
| R/W |
0x00000001 |
Address@gxc_phy_ctrl0 : 0x07d82a10 Address@gxc_phy_ctrl1 : 0x07d82a50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x1 |
val |
|
|
| gxc_int_phy_ctrl_led0_cfg |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a14 Address@gxc_phy_ctrl1 : 0x07d82a54 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 - 8 | "00000000" |
blink_low_condition |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 - 0 | "00000000" |
blink_high_condition |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gxc_int_phy_ctrl_led1_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a18 Address@gxc_phy_ctrl1 : 0x07d82a58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
blink_low_condition |
|
|
| 7 - 0 | "00000000" |
blink_high_condition |
|
|
| gxc_int_phy_ctrl_led2_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a1c Address@gxc_phy_ctrl1 : 0x07d82a5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
blink_low_condition |
|
|
| 7 - 0 | "00000000" |
blink_high_condition |
|
|
| gxc_int_phy_ctrl_led3_cfg |
|
|||
| R/W |
0x00000000 |
Address@gxc_phy_ctrl0 : 0x07d82a20 Address@gxc_phy_ctrl1 : 0x07d82a60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
blink_low_condition |
|
|
| 7 - 0 | "00000000" |
blink_high_condition |
|
|
| gxc_int_phy_ctrl_led |
|
||||||||||||
| R/W |
0x00004000 |
Address@gxc_phy_ctrl0 : 0x07d82a24 Address@gxc_phy_ctrl1 : 0x07d82a64 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||||
| 15 - 12 | "0100" |
interval |
|
||||||||||
| 11 - 10 | 0 |
- |
reserved | ||||||||||
| 9 - 8 | "00" |
mode |
|
||||||||||
| 7 | "0" |
led1 |
|
||||||||||
| 6 | "0" |
led0 |
|
||||||||||
| 5 - 4 | - |
speed_ro |
|
||||||||||
| 3 | - |
link_ro |
|
||||||||||
| 2 | - |
duplex_ro |
|
||||||||||
| 1 | 0 |
- |
reserved | ||||||||||
| 0 | - |
rx_tx_active_ro |
|
||||||||||
| gxc_int_phy_ctrl_enhanced_link_detection0 |
|
|||
| R/W |
0x00100000 |
Address@gxc_phy_ctrl0 : 0x07d82a28 Address@gxc_phy_ctrl1 : 0x07d82a68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | - |
eld_bad_link_ro |
|
|
| 30 - 24 | 0 |
- |
reserved | |
| 23 - 20 | "0001" |
sub |
|
|
| 19 - 0 | - |
counter_ro |
|
|
| gxc_int_phy_ctrl_enhanced_link_detection1 |
|
|||
| R/W |
0x01000800 |
Address@gxc_phy_ctrl0 : 0x07d82a2c Address@gxc_phy_ctrl1 : 0x07d82a6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0x10 |
add |
|
|
| 19 - 0 | 0x800 |
threshold |
|
|
| gxc_sys_ctrl_mii0_in |
|
|||
| R |
Address : 0x07d82b00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 | gpio3 |
|
||
| 18 | gpio2 |
|
||
| 17 | gpio1 |
|
||
| 16 | gpio0 |
|
||
| 15 - 13 | - |
reserved | ||
| 12 | mii_txsfd |
|
||
| 11 | mii_rxsfd |
|
||
| 10 | mii_txclk |
|
||
| 9 | mii_link |
|
||
| 8 | mii_col |
|
||
| 7 | mii_crs |
|
||
| 6 | mii_rxer |
|
||
| 5 | mii_rxdv |
|
||
| 4 | mii_rxd3 |
|
||
| 3 | mii_rxd2 |
|
||
| 2 | mii_rxd1 |
|
||
| 1 | mii_rxd0 |
|
||
| 0 | mii_rxclk |
|
||
| gxc_sys_ctrl_mii0_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
gpio3 |
|
|
| 18 | "0" |
gpio2 |
|
|
| 17 | "0" |
gpio1 |
|
|
| 16 | "0" |
gpio0 |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mii_txer |
|
|
| 4 | "0" |
mii_txen |
|
|
| 3 | "0" |
mii_txd3 |
|
|
| 2 | "0" |
mii_txd2 |
|
|
| 1 | "0" |
mii_txd1 |
|
|
| 0 | "0" |
mii_txd0 |
|
|
| gxc_sys_ctrl_mii0_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b08 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | ||||||
| 19 | "0" |
gpio3 |
|
||||||
| 18 | "0" |
gpio2 |
|
||||||
| 17 | "0" |
gpio1 |
|
||||||
| 16 | "0" |
gpio0 |
|
||||||
| 15 - 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
mii_txer |
|
||||||
| 4 | "0" |
mii_txen |
|
||||||
| 3 | "0" |
mii_txd3 |
|
||||||
| 2 | "0" |
mii_txd2 |
|
||||||
| 1 | "0" |
mii_txd1 |
|
||||||
| 0 | "0" |
mii_txd0 |
|
||||||
| gxc_sys_ctrl_mii0_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
gpio3 |
|
|
| 18 | "0" |
gpio2 |
|
|
| 17 | "0" |
gpio1 |
|
|
| 16 | "0" |
gpio0 |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mii_txer |
|
|
| 4 | "0" |
mii_txen |
|
|
| 3 | "0" |
mii_txd3 |
|
|
| 2 | "0" |
mii_txd2 |
|
|
| 1 | "0" |
mii_txd1 |
|
|
| 0 | "0" |
mii_txd0 |
|
|
| gxc_sys_ctrl_mii1_in |
|
|||
| R |
Address : 0x07d82b10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 | gpio3 |
|
||
| 18 | gpio2 |
|
||
| 17 | gpio1 |
|
||
| 16 | gpio0 |
|
||
| 15 - 13 | - |
reserved | ||
| 12 | mii_txsfd |
|
||
| 11 | mii_rxsfd |
|
||
| 10 | mii_txclk |
|
||
| 9 | mii_link |
|
||
| 8 | mii_col |
|
||
| 7 | mii_crs |
|
||
| 6 | mii_rxer |
|
||
| 5 | mii_rxdv |
|
||
| 4 | mii_rxd3 |
|
||
| 3 | mii_rxd2 |
|
||
| 2 | mii_rxd1 |
|
||
| 1 | mii_rxd0 |
|
||
| 0 | mii_rxclk |
|
||
| gxc_sys_ctrl_mii1_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
gpio3 |
|
|
| 18 | "0" |
gpio2 |
|
|
| 17 | "0" |
gpio1 |
|
|
| 16 | "0" |
gpio0 |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mii_txer |
|
|
| 4 | "0" |
mii_txen |
|
|
| 3 | "0" |
mii_txd3 |
|
|
| 2 | "0" |
mii_txd2 |
|
|
| 1 | "0" |
mii_txd1 |
|
|
| 0 | "0" |
mii_txd0 |
|
|
| gxc_sys_ctrl_mii1_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b18 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | ||||||
| 19 | "0" |
gpio3 |
|
||||||
| 18 | "0" |
gpio2 |
|
||||||
| 17 | "0" |
gpio1 |
|
||||||
| 16 | "0" |
gpio0 |
|
||||||
| 15 - 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
mii_txer |
|
||||||
| 4 | "0" |
mii_txen |
|
||||||
| 3 | "0" |
mii_txd3 |
|
||||||
| 2 | "0" |
mii_txd2 |
|
||||||
| 1 | "0" |
mii_txd1 |
|
||||||
| 0 | "0" |
mii_txd0 |
|
||||||
| gxc_sys_ctrl_mii1_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
gpio3 |
|
|
| 18 | "0" |
gpio2 |
|
|
| 17 | "0" |
gpio1 |
|
|
| 16 | "0" |
gpio0 |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mii_txer |
|
|
| 4 | "0" |
mii_txen |
|
|
| 3 | "0" |
mii_txd3 |
|
|
| 2 | "0" |
mii_txd2 |
|
|
| 1 | "0" |
mii_txd1 |
|
|
| 0 | "0" |
mii_txd0 |
|
|
| gxc_sys_ctrl_rmii0_in |
|
|||
| R |
Address : 0x07d82b20 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | rmii_txsfd |
|
||
| 6 | rmii_rxsfd |
|
||
| 5 | rmii_link |
|
||
| 4 | rmii_rxer |
|
||
| 3 | rmii_crsdv |
|
||
| 2 | rmii_rxd1 |
|
||
| 1 | rmii_rxd0 |
|
||
| 0 | rmii_refclk |
|
||
| gxc_sys_ctrl_rmii0_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
rmii_txen |
|
|
| 1 | "0" |
rmii_txd1 |
|
|
| 0 | "0" |
rmii_txd0 |
|
|
| gxc_sys_ctrl_rmii0_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b28 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
rmii_txen |
|
||||||
| 1 | "0" |
rmii_txd1 |
|
||||||
| 0 | "0" |
rmii_txd0 |
|
||||||
| gxc_sys_ctrl_rmii0_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
rmii_txen |
|
|
| 1 | "0" |
rmii_txd1 |
|
|
| 0 | "0" |
rmii_txd0 |
|
|
| gxc_sys_ctrl_rmii1_in |
|
|||
| R |
Address : 0x07d82b30 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | rmii_txsfd |
|
||
| 6 | rmii_rxsfd |
|
||
| 5 | rmii_link |
|
||
| 4 | rmii_rxer |
|
||
| 3 | rmii_crsdv |
|
||
| 2 | rmii_rxd1 |
|
||
| 1 | rmii_rxd0 |
|
||
| 0 | rmii_refclk |
|
||
| gxc_sys_ctrl_rmii1_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
rmii_txen |
|
|
| 1 | "0" |
rmii_txd1 |
|
|
| 0 | "0" |
rmii_txd0 |
|
|
| gxc_sys_ctrl_rmii1_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b38 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
rmii_txen |
|
||||||
| 1 | "0" |
rmii_txd1 |
|
||||||
| 0 | "0" |
rmii_txd0 |
|
||||||
| gxc_sys_ctrl_rmii1_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
rmii_txen |
|
|
| 1 | "0" |
rmii_txd1 |
|
|
| 0 | "0" |
rmii_txd0 |
|
|
| gxc_sys_ctrl_rgmii0_in |
|
|||
| R |
Address : 0x07d82b40 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | rgmii_link |
|
||
| 7 | rgmii_txsfd |
|
||
| 6 | rgmii_rxsfd |
|
||
| 5 | rgmii_rxctl |
|
||
| 4 | rgmii_rxd3 |
|
||
| 3 | rgmii_rxd2 |
|
||
| 2 | rgmii_rxd1 |
|
||
| 1 | rgmii_rxd0 |
|
||
| 0 | rgmii_rxc |
|
||
| gxc_sys_ctrl_rgmii0_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rgmii_txctl |
|
|
| 4 | "0" |
rgmii_txd3 |
|
|
| 3 | "0" |
rgmii_txd2 |
|
|
| 2 | "0" |
rgmii_txd1 |
|
|
| 1 | "0" |
rgmii_txd0 |
|
|
| 0 | "0" |
rgmii_txc |
|
|
| gxc_sys_ctrl_rgmii0_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b48 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
rgmii_txctl |
|
||||||
| 4 | "0" |
rgmii_txd3 |
|
||||||
| 3 | "0" |
rgmii_txd2 |
|
||||||
| 2 | "0" |
rgmii_txd1 |
|
||||||
| 1 | "0" |
rgmii_txd0 |
|
||||||
| 0 | "0" |
rgmii_txc |
|
||||||
| gxc_sys_ctrl_rgmii0_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rgmii_txctl |
|
|
| 4 | "0" |
rgmii_txd3 |
|
|
| 3 | "0" |
rgmii_txd2 |
|
|
| 2 | "0" |
rgmii_txd1 |
|
|
| 1 | "0" |
rgmii_txd0 |
|
|
| 0 | "0" |
rgmii_txc |
|
|
| gxc_sys_ctrl_rgmii1_in |
|
|||
| R |
Address : 0x07d82b50 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | rgmii_link |
|
||
| 7 | rgmii_txsfd |
|
||
| 6 | rgmii_rxsfd |
|
||
| 5 | rgmii_rxctl |
|
||
| 4 | rgmii_rxd3 |
|
||
| 3 | rgmii_rxd2 |
|
||
| 2 | rgmii_rxd1 |
|
||
| 1 | rgmii_rxd0 |
|
||
| 0 | rgmii_rxc |
|
||
| gxc_sys_ctrl_rgmii1_oe |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rgmii_txctl |
|
|
| 4 | "0" |
rgmii_txd3 |
|
|
| 3 | "0" |
rgmii_txd2 |
|
|
| 2 | "0" |
rgmii_txd1 |
|
|
| 1 | "0" |
rgmii_txd0 |
|
|
| 0 | "0" |
rgmii_txc |
|
|
| gxc_sys_ctrl_rgmii1_piomode |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82b58 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
rgmii_txctl |
|
||||||
| 4 | "0" |
rgmii_txd3 |
|
||||||
| 3 | "0" |
rgmii_txd2 |
|
||||||
| 2 | "0" |
rgmii_txd1 |
|
||||||
| 1 | "0" |
rgmii_txd0 |
|
||||||
| 0 | "0" |
rgmii_txc |
|
||||||
| gxc_sys_ctrl_rgmii1_pioout |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rgmii_txctl |
|
|
| 4 | "0" |
rgmii_txd3 |
|
|
| 3 | "0" |
rgmii_txd2 |
|
|
| 2 | "0" |
rgmii_txd1 |
|
|
| 1 | "0" |
rgmii_txd0 |
|
|
| 0 | "0" |
rgmii_txc |
|
|
| gxc_sys_ctrl_sgmii0_in |
|
|||
| R |
Address : 0x07d82b60 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | sgmii_link |
|
||
| 1 | sgmii_rxsfd |
|
||
| 0 | sgmii_txsfd |
|
||
| gxc_sys_ctrl_sgmii1_in |
|
|||
| R |
Address : 0x07d82b64 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | sgmii_link |
|
||
| 1 | sgmii_rxsfd |
|
||
| 0 | sgmii_txsfd |
|
||
| gxc_sys_ctrl_link_mode0_config |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x07d82b80 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
rgmii_delay_txc_wm |
|
|||||||||||
| 30 - 28 | "000" |
ext_mode_wm |
|
|||||||||||
| 27 | "0" |
link_mode_man_duplex_wm |
|
|||||||||||
| 26 | "0" |
link_mode_man_link_wm |
|
|||||||||||
| 25 - 24 | "00" |
link_mode_man_speed_wm |
|
|||||||||||
| 23 | "0" |
auto_down_man_up_wm |
|
|||||||||||
| 22 | "0" |
inband_status_filter_dis_wm |
|
|||||||||||
| 21 - 20 | "00" |
sel_duplex_wm |
|
|||||||||||
| 19 - 18 | "00" |
sel_link_wm |
|
|||||||||||
| 17 - 16 | "00" |
sel_speed_wm |
|
|||||||||||
| 15 | "0" |
rgmii_delay_txc |
|
|||||||||||
| 14 - 12 | "000" |
ext_mode |
|
|||||||||||
| 11 | "0" |
link_mode_man_duplex |
|
|||||||||||
| 10 | "0" |
link_mode_man_link |
|
|||||||||||
| 9 - 8 | "00" |
link_mode_man_speed |
|
|||||||||||
| 7 | "0" |
auto_down_man_up |
|
|||||||||||
| 6 | "0" |
inband_status_filter_dis |
|
|||||||||||
| 5 - 4 | "00" |
sel_duplex |
|
|||||||||||
| 3 - 2 | "00" |
sel_link |
|
|||||||||||
| 1 - 0 | "00" |
sel_speed |
|
|||||||||||
| gxc_sys_ctrl_link_mode0_status |
|
||||||||||||
| R/W |
0x00003300 |
Address : 0x07d82b84 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
inband_err_up_lo_mismatch |
|
||||||||||
| 30 - 14 | 0 |
- |
reserved | ||||||||||
| 13 - 12 | "11" |
link_mode_rxclk_speed |
|
||||||||||
| 11 | "0" |
link_mode_inband_duplex |
|
||||||||||
| 10 | "0" |
link_mode_inband_link |
|
||||||||||
| 9 - 8 | "11" |
link_mode_inband_speed |
|
||||||||||
| 7 | 0 |
- |
reserved | ||||||||||
| 6 | "0" |
link_mode_ext_in_link |
|
||||||||||
| 5 | 0 |
- |
reserved | ||||||||||
| 4 | "0" |
link_mode_phy_link |
|
||||||||||
| 3 | "0" |
link_mode_out_duplex |
|
||||||||||
| 2 | "0" |
link_mode_out_link |
|
||||||||||
| 1 - 0 | "00" |
link_mode_out_speed |
|
||||||||||
| gxc_sys_ctrl_link_mode1_config |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x07d82b88 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
rgmii_delay_txc_wm |
|
|||||||||||
| 30 - 28 | "000" |
ext_mode_wm |
|
|||||||||||
| 27 | "0" |
link_mode_man_duplex_wm |
|
|||||||||||
| 26 | "0" |
link_mode_man_link_wm |
|
|||||||||||
| 25 - 24 | "00" |
link_mode_man_speed_wm |
|
|||||||||||
| 23 | "0" |
auto_down_man_up_wm |
|
|||||||||||
| 22 | "0" |
inband_status_filter_dis_wm |
|
|||||||||||
| 21 - 20 | "00" |
sel_duplex_wm |
|
|||||||||||
| 19 - 18 | "00" |
sel_link_wm |
|
|||||||||||
| 17 - 16 | "00" |
sel_speed_wm |
|
|||||||||||
| 15 | "0" |
rgmii_delay_txc |
|
|||||||||||
| 14 - 12 | "000" |
ext_mode |
|
|||||||||||
| 11 | "0" |
link_mode_man_duplex |
|
|||||||||||
| 10 | "0" |
link_mode_man_link |
|
|||||||||||
| 9 - 8 | "00" |
link_mode_man_speed |
|
|||||||||||
| 7 | "0" |
auto_down_man_up |
|
|||||||||||
| 6 | "0" |
inband_status_filter_dis |
|
|||||||||||
| 5 - 4 | "00" |
sel_duplex |
|
|||||||||||
| 3 - 2 | "00" |
sel_link |
|
|||||||||||
| 1 - 0 | "00" |
sel_speed |
|
|||||||||||
| gxc_sys_ctrl_link_mode1_status |
|
||||||||||||
| R/W |
0x00003300 |
Address : 0x07d82b8c |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
inband_err_up_lo_mismatch |
|
||||||||||
| 30 - 14 | 0 |
- |
reserved | ||||||||||
| 13 - 12 | "11" |
link_mode_rxclk_speed |
|
||||||||||
| 11 | "0" |
link_mode_inband_duplex |
|
||||||||||
| 10 | "0" |
link_mode_inband_link |
|
||||||||||
| 9 - 8 | "11" |
link_mode_inband_speed |
|
||||||||||
| 7 | 0 |
- |
reserved | ||||||||||
| 6 | "0" |
link_mode_ext_in_link |
|
||||||||||
| 5 | 0 |
- |
reserved | ||||||||||
| 4 | "0" |
link_mode_phy_link |
|
||||||||||
| 3 | "0" |
link_mode_out_duplex |
|
||||||||||
| 2 | "0" |
link_mode_out_link |
|
||||||||||
| 1 - 0 | "00" |
link_mode_out_speed |
|
||||||||||
| gxc_sys_ctrl_gpec_rx_frame_err_mii_err_counter |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
mii1_mii_err_cnt |
|
|
| 23 - 16 | "00000000" |
mii1_frame_err_cnt |
|
|
| 15 - 8 | "00000000" |
mii0_mii_err_cnt |
|
|
| 7 - 0 | "00000000" |
mii0_frame_err_cnt |
|
|
| gxc_sys_ctrl_gpec_rx_frwd_err_link_down_counter |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
mii1_link_down_cnt |
|
|
| 23 - 16 | "00000000" |
mii0_link_down_cnt |
|
|
| 15 - 8 | "00000000" |
mii1_frwd_err_cnt |
|
|
| 7 - 0 | "00000000" |
mii0_frwd_err_cnt |
|
|
| gxc_sys_ctrl_gpec_rx_proc_err_counter |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82b98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
proc_err_cnt |
|
|
| gxc_sys_ctrl_gmac_rpu0_counter_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82ba0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sys_ctrl_gmac_rpu0_counter_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82ba4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sys_ctrl_gmac_rpu1_counter_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82ba8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sys_ctrl_gmac_rpu1_counter_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sys_ctrl_swap |
|
|||||||
| R/W |
0x00000000 |
Address : 0x07d82bb0 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |||||
| 25 | "0" |
link_down_cnt1_dis_wm |
|
|||||
| 24 | "0" |
link_down_cnt0_dis_wm |
|
|||||
| 23 | "0" |
mii_err_cnt1_dis_wm |
|
|||||
| 22 | "0" |
mii_err_cnt0_dis_wm |
|
|||||
| 21 | "0" |
frwd_err_cnt_sel_wm |
|
|||||
| 20 | "0" |
frame_err_cnt_sel_wm |
|
|||||
| 19 | "0" |
tx_swap1_wm |
|
|||||
| 18 | "0" |
rx_swap1_wm |
|
|||||
| 17 | "0" |
tx_swap0_wm |
|
|||||
| 16 | "0" |
rx_swap0_wm |
|
|||||
| 15 - 10 | 0 |
- |
reserved | |||||
| 9 | "0" |
link_down_cnt1_dis |
|
|||||
| 8 | "0" |
link_down_cnt0_dis |
|
|||||
| 7 | "0" |
mii_err_cnt1_dis |
|
|||||
| 6 | "0" |
mii_err_cnt0_dis |
|
|||||
| 5 | "0" |
frwd_err_cnt_sel |
|
|||||
| 4 | "0" |
frame_err_cnt_sel |
|
|||||
| 3 | "0" |
tx_swap1 |
|
|||||
| 2 | "0" |
rx_swap1 |
|
|||||
| 1 | "0" |
tx_swap0 |
|
|||||
| 0 | "0" |
rx_swap0 |
|
|||||
| gxc_sys_ctrl_io_polarity |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 | "0" |
inv_gmac1_txsfd_wm |
|
|
| 29 | "0" |
inv_gmac1_rxsfd_wm |
|
|
| 28 | "0" |
inv_gmac1_link_wm |
|
|
| 27 | "0" |
inv_gmac1_gpio3_wm |
|
|
| 26 | "0" |
inv_gmac1_gpio2_wm |
|
|
| 25 | "0" |
inv_gmac1_gpio1_wm |
|
|
| 24 | "0" |
inv_gmac1_gpio0_wm |
|
|
| 23 | 0 |
- |
reserved | |
| 22 | "0" |
inv_gmac0_txsfd_wm |
|
|
| 21 | "0" |
inv_gmac0_rxsfd_wm |
|
|
| 20 | "0" |
inv_gmac0_link_wm |
|
|
| 19 | "0" |
inv_gmac0_gpio3_wm |
|
|
| 18 | "0" |
inv_gmac0_gpio2_wm |
|
|
| 17 | "0" |
inv_gmac0_gpio1_wm |
|
|
| 16 | "0" |
inv_gmac0_gpio0_wm |
|
|
| 15 | 0 |
- |
reserved | |
| 14 | "0" |
inv_gmac1_txsfd |
|
|
| 13 | "0" |
inv_gmac1_rxsfd |
|
|
| 12 | "0" |
inv_gmac1_link |
|
|
| 11 | "0" |
inv_gmac1_gpio3 |
|
|
| 10 | "0" |
inv_gmac1_gpio2 |
|
|
| 9 | "0" |
inv_gmac1_gpio1 |
|
|
| 8 | "0" |
inv_gmac1_gpio0 |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
inv_gmac0_txsfd |
|
|
| 5 | "0" |
inv_gmac0_rxsfd |
|
|
| 4 | "0" |
inv_gmac0_link |
|
|
| 3 | "0" |
inv_gmac0_gpio3 |
|
|
| 2 | "0" |
inv_gmac0_gpio2 |
|
|
| 1 | "0" |
inv_gmac0_gpio1 |
|
|
| 0 | "0" |
inv_gmac0_gpio0 |
|
|
| gxc_sys_ctrl_rxtx_data_bitswap |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x07d82bb8 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 | "0" |
bitswap_txd1_wm |
|
|||||||||
| 18 | "0" |
bitswap_txd0_wm |
|
|||||||||
| 17 | "0" |
bitswap_rxd1_wm |
|
|||||||||
| 16 | "0" |
bitswap_rxd0_wm |
|
|||||||||
| 15 - 4 | 0 |
- |
reserved | |||||||||
| 3 | "0" |
bitswap_txd1 |
|
|||||||||
| 2 | "0" |
bitswap_txd0 |
|
|||||||||
| 1 | "0" |
bitswap_rxd1 |
|
|||||||||
| 0 | "0" |
bitswap_rxd0 |
|
|||||||||
| gxc_sys_ctrl_txclk_sync |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
clk2txc_1_ro |
|
|
| 23 - 16 | - |
clk2txc_0_ro |
|
|
| 15 - 8 | "00000000" |
delay_val1 |
|
|
| 7 - 0 | "00000000" |
delay_val0 |
|
|
| gxc_sys_ctrl_miimu0 |
|
||||||||||||||||
| R/W |
0x00000018 |
Address : 0x07d82bc0 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
data |
|
||||||||||||||
| 15 - 11 | "00000" |
regaddr |
|
||||||||||||||
| 10 - 6 | "00000" |
phyaddr |
|
||||||||||||||
| 5 - 4 | "01" |
op |
|
||||||||||||||
| 3 | "1" |
st |
|
||||||||||||||
| 2 | "0" |
rd_nw |
|
||||||||||||||
| 1 | "0" |
arbiter_lock |
|
||||||||||||||
| 0 | "0" |
snrdy |
|
||||||||||||||
| gxc_sys_ctrl_miimu1 |
|
||||||||||||||||
| R/W |
0x00000018 |
Address : 0x07d82bc4 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
data |
|
||||||||||||||
| 15 - 11 | "00000" |
regaddr |
|
||||||||||||||
| 10 - 6 | "00000" |
phyaddr |
|
||||||||||||||
| 5 - 4 | "01" |
op |
|
||||||||||||||
| 3 | "1" |
st |
|
||||||||||||||
| 2 | "0" |
rd_nw |
|
||||||||||||||
| 1 | "0" |
arbiter_lock |
|
||||||||||||||
| 0 | "0" |
snrdy |
|
||||||||||||||
| gxc_sys_ctrl_miimu_cfg |
|
||||||||
| R/W |
0x000000a0 |
Address : 0x07d82bc8 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
mdc_oe |
|
||||||
| 7 | "1" |
rta |
|
||||||
| 6 | "0" |
mdc_period |
|
||||||
| 5 - 0 | "100000" |
preamble |
|
||||||
| gxc_sys_ctrl_miimu_sw |
|
||||||||
| R/W |
0x00000000 |
Address : 0x07d82bcc |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
loopback |
|
||||||
| 7 | - |
mdi_ro |
|
||||||
| 6 | "0" |
mdoe |
|
||||||
| 5 | "0" |
mdo |
|
||||||
| 4 | "0" |
mdc |
|
||||||
| 3 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
enable |
|
||||||
| gxc_sys_ctrl_intram_prio |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 6 | "00" |
intram3 |
|
|
| 5 - 4 | "00" |
intram2 |
|
|
| 3 - 2 | "00" |
intram1 |
|
|
| 1 - 0 | "00" |
intram0 |
|
|
| gxc_sys_ctrl_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
phy1_link_change |
|
|
| 0 | "0" |
phy0_link_change |
|
|
| gxc_sys_ctrl_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
phy1_link_change |
|
|
| 0 | "0" |
phy0_link_change |
|
|
| gxc_sys_ctrl_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82bdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
phy1_link_change |
|
|
| 0 | "0" |
phy0_link_change |
|
|
| gxc_sys_ctrl_irq_mask_rst |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x07d82be0 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||
| 1 | "0" |
phy1_link_change |
|
|||||||
| 0 | "0" |
phy0_link_change |
|
|||||||
| gxc_trigger_mode |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 12 | "0000" |
cyc1_count |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
trigger_mode |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
sync1_oe |
|
|
| 5 | "0" |
sync1_polarity |
|
|
| 4 | "0" |
sync1_output_driver |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
sync0_oe |
|
|
| 1 | "0" |
sync0_polarity |
|
|
| 0 | "0" |
sync0_output_driver |
|
|
| gxc_trigger_impulse_length |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sync1_impulse_length |
|
|
| 15 - 0 | 0x0 |
sync0_impulse_length |
|
|
| gxc_trigger_offset_lower |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_trigger_offset_upper |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_trigger_sync1_interval |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 - 0 | 0x0 |
sync1_interval |
|
|
| gxc_trigger_activate |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sync1_activate |
|
|
| 1 | "0" |
sync0_activate |
|
|
| 0 | "0" |
trigger_unit_activate |
|
|
| gxc_trigger_0_starttime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_trigger_0_starttime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_trigger_1_starttime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_trigger_1_starttime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_trigger_0_cyc_time |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_trigger_1_cyc_time |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_sample_mode |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sample_1_negedge_mode |
|
|
| 8 | "0" |
sample_1_posedge_mode |
|
|
| 7 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sample_0_negedge_mode |
|
|
| 0 | "0" |
sample_0_posedge_mode |
|
|
| gxc_sample_offset_lower |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sample_offset_upper |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_sample_activate |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
latch1_ecat_controlled |
|
|
| 1 | "0" |
latch0_ecat_controlled |
|
|
| 0 | "0" |
latch_unit_activate |
|
|
| gxc_sample_0_pos_systime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_sample_0_pos_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_sample_0_neg_systime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_sample_0_neg_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_sample_1_pos_systime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_sample_1_pos_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_sample_1_neg_systime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_s |
|
|
| gxc_sample_1_neg_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_trigger_sample_status |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
sample_1_in |
|
|
| 25 | "0" |
sample_1_negedge_status |
|
|
| 24 | "0" |
sample_1_posedge_status |
|
|
| 23 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
sample_0_in |
|
|
| 17 | "0" |
sample_0_negedge_status |
|
|
| 16 | "0" |
sample_0_posedge_status |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sync1_status |
|
|
| 7 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sync0_status |
|
|
| gxc_trigger_sample_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_trigger_sample_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_trigger_sample_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82c6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_trigger_sample_irq_mask_rst |
|
|||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d82c70 |
Bits | Reset value | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||
| 5 | "0" |
latch1_negedge_irq |
|
|||||||||||||||
| 4 | "0" |
latch1_posedge_irq |
|
|||||||||||||||
| 3 | "0" |
latch0_negedge_irq |
|
|||||||||||||||
| 2 | "0" |
latch0_posedge_irq |
|
|||||||||||||||
| 1 | "0" |
sync1_irq |
|
|||||||||||||||
| 0 | "0" |
sync0_irq |
|
|||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_global_trigger_mode |
| 1 | 4 | R/W | gxc_global_trigger_impulse_length |
| 2 | 8 | R/W | gxc_global_trigger_offset_lower |
| 3 | c | - | reserved |
| 4 | 10 | R/W | gxc_global_trigger_sync1_interval |
| 5 | 14 | R/W | gxc_global_trigger_activate |
| 6 | 18 | R/W | gxc_global_trigger_0_starttime_ns |
| 7 | 1c | R/W | gxc_global_trigger_1_starttime_ns |
| 8 | 20 | R/W | gxc_global_trigger_0_cyc_time |
| 9 | 24 | R/W | gxc_global_trigger_1_cyc_time |
| a | 28 | R/W | gxc_global_sample_mode |
| b | 2c | R/W | gxc_global_sample_offset_lower |
| c | 30 | - | reserved |
| d | 34 | R/W | gxc_global_sample_activate |
| e | 38 | R/W | gxc_global_sample_0_pos_systime_ns |
| f | 3c | R/W | gxc_global_sample_0_neg_systime_ns |
| 10 | 40 | R/W | gxc_global_sample_1_pos_systime_ns |
| 11 | 44 | R/W | gxc_global_sample_1_neg_systime_ns |
| 12 | 48 | R/W | gxc_global_trigger_sample_status |
| 13 | 4c | R/W | gxc_global_trigger_sample_irq_raw |
| 14 | 50 | R/W | gxc_global_trigger_sample_irq_masked |
| 15 | 54 | R/W | gxc_global_trigger_sample_irq_mask_set |
| 16 | 58 | R/W | gxc_global_trigger_sample_irq_mask_rst |
| 17-3f | 5c-fc | - | reserved |
| gxc_global_trigger_mode |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 12 | "0000" |
cyc1_count |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
trigger_mode |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
sync1_oe |
|
|
| 5 | "0" |
sync1_polarity |
|
|
| 4 | "0" |
sync1_output_driver |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
sync0_oe |
|
|
| 1 | "0" |
sync0_polarity |
|
|
| 0 | "0" |
sync0_output_driver |
|
|
| gxc_global_trigger_impulse_length |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sync1_impulse_length |
|
|
| 15 - 0 | 0x0 |
sync0_impulse_length |
|
|
| gxc_global_trigger_offset_lower |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_global_trigger_sync1_interval |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 - 0 | 0x0 |
sync1_interval |
|
|
| gxc_global_trigger_activate |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sync1_activate |
|
|
| 1 | "0" |
sync0_activate |
|
|
| 0 | "0" |
trigger_unit_activate |
|
|
| gxc_global_trigger_0_starttime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_trigger_1_starttime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_trigger_0_cyc_time |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_trigger_1_cyc_time |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_sample_mode |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sample_1_negedge_mode |
|
|
| 8 | "0" |
sample_1_posedge_mode |
|
|
| 7 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sample_0_negedge_mode |
|
|
| 0 | "0" |
sample_0_posedge_mode |
|
|
| gxc_global_sample_offset_lower |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_global_sample_activate |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
latch_unit_activate |
|
|
| gxc_global_sample_0_pos_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_sample_0_neg_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_sample_1_pos_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_sample_1_neg_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
systime_ns |
|
|
| gxc_global_trigger_sample_status |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
sample_1_in |
|
|
| 25 | "0" |
sample_1_negedge_status |
|
|
| 24 | "0" |
sample_1_posedge_status |
|
|
| 23 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
sample_0_in |
|
|
| 17 | "0" |
sample_0_negedge_status |
|
|
| 16 | "0" |
sample_0_posedge_status |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sync1_status |
|
|
| 7 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sync0_status |
|
|
| gxc_global_trigger_sample_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_global_trigger_sample_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_global_trigger_sample_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82d54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
latch1_negedge_irq |
|
|
| 4 | "0" |
latch1_posedge_irq |
|
|
| 3 | "0" |
latch0_negedge_irq |
|
|
| 2 | "0" |
latch0_posedge_irq |
|
|
| 1 | "0" |
sync1_irq |
|
|
| 0 | "0" |
sync0_irq |
|
|
| gxc_global_trigger_sample_irq_mask_rst |
|
|||||||||||||||||
| R/W |
0x00000000 |
Address : 0x07d82d58 |
Bits | Reset value | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||
| 5 | "0" |
latch1_negedge_irq |
|
|||||||||||||||
| 4 | "0" |
latch1_posedge_irq |
|
|||||||||||||||
| 3 | "0" |
latch0_negedge_irq |
|
|||||||||||||||
| 2 | "0" |
latch0_posedge_irq |
|
|||||||||||||||
| 1 | "0" |
sync1_irq |
|
|||||||||||||||
| 0 | "0" |
sync0_irq |
|
|||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_systime_s |
| 1 | 4 | R/W | gxc_systime_ns |
| 2 | 8 | R/W | gxc_systime_border |
| 3 | c | R/W | gxc_systime_count_value |
| 4 | 10 | R/W | gxc_systime_global_s |
| 5 | 14 | R/W | gxc_systime_global_ns |
| 6 | 18 | R/W | gxc_systime_global_border |
| 7 | 1c | R/W | gxc_systime_global_count_value |
| 8 | 20 | R/W | gxc_counter_hi |
| 9 | 24 | R/W | gxc_counter_lo |
| a | 28 | - | reserved |
| b | 2c | R/W | gxc_counter_count_value |
| c | 30 | R/W | gxc_reset_gpec_sample_regs0 |
| d | 34 | R/W | gxc_reset_gpec_sample_regs1 |
| e-3f | 38-fc | - | reserved |
| gxc_systime_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_systime_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_systime_border |
|
|||
| R/W |
0x3b9ac9ff |
Address : 0x07d82e08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x3b9ac9ff |
val |
|
|
| gxc_systime_count_value |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_systime_global_s |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_systime_global_ns |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_systime_global_border |
|
|||
| R/W |
0x3b9ac9ff |
Address : 0x07d82e18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x3b9ac9ff |
val |
|
|
| gxc_systime_global_count_value |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_counter_hi |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_counter_lo |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_counter_count_value |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "00000" |
val |
|
|
| gxc_reset_gpec_sample_regs0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
gpec07_counter_reset_wm |
|
|
| 30 | "0" |
gpec07_systime_reset_wm |
|
|
| 29 | "0" |
gpec06_counter_reset_wm |
|
|
| 28 | "0" |
gpec06_systime_reset_wm |
|
|
| 27 | "0" |
gpec05_counter_reset_wm |
|
|
| 26 | "0" |
gpec05_systime_reset_wm |
|
|
| 25 | "0" |
gpec04_counter_reset_wm |
|
|
| 24 | "0" |
gpec04_systime_reset_wm |
|
|
| 23 | "0" |
gpec03_counter_reset_wm |
|
|
| 22 | "0" |
gpec03_systime_reset_wm |
|
|
| 21 | "0" |
gpec02_counter_reset_wm |
|
|
| 20 | "0" |
gpec02_systime_reset_wm |
|
|
| 19 | "0" |
gpec01_counter_reset_wm |
|
|
| 18 | "0" |
gpec01_systime_reset_wm |
|
|
| 17 | "0" |
gpec00_counter_reset_wm |
|
|
| 16 | "0" |
gpec00_systime_reset_wm |
|
|
| 15 | "0" |
gpec07_counter_reset |
|
|
| 14 | "0" |
gpec07_systime_reset |
|
|
| 13 | "0" |
gpec06_counter_reset |
|
|
| 12 | "0" |
gpec06_systime_reset |
|
|
| 11 | "0" |
gpec05_counter_reset |
|
|
| 10 | "0" |
gpec05_systime_reset |
|
|
| 9 | "0" |
gpec04_counter_reset |
|
|
| 8 | "0" |
gpec04_systime_reset |
|
|
| 7 | "0" |
gpec03_counter_reset |
|
|
| 6 | "0" |
gpec03_systime_reset |
|
|
| 5 | "0" |
gpec02_counter_reset |
|
|
| 4 | "0" |
gpec02_systime_reset |
|
|
| 3 | "0" |
gpec01_counter_reset |
|
|
| 2 | "0" |
gpec01_systime_reset |
|
|
| 1 | "0" |
gpec00_counter_reset |
|
|
| 0 | "0" |
gpec00_systime_reset |
|
|
| gxc_reset_gpec_sample_regs1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d82e34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
gpec17_counter_reset_wm |
|
|
| 30 | "0" |
gpec17_systime_reset_wm |
|
|
| 29 | "0" |
gpec16_counter_reset_wm |
|
|
| 28 | "0" |
gpec16_systime_reset_wm |
|
|
| 27 | "0" |
gpec15_counter_reset_wm |
|
|
| 26 | "0" |
gpec15_systime_reset_wm |
|
|
| 25 | "0" |
gpec14_counter_reset_wm |
|
|
| 24 | "0" |
gpec14_systime_reset_wm |
|
|
| 23 | "0" |
gpec13_counter_reset_wm |
|
|
| 22 | "0" |
gpec13_systime_reset_wm |
|
|
| 21 | "0" |
gpec12_counter_reset_wm |
|
|
| 20 | "0" |
gpec12_systime_reset_wm |
|
|
| 19 | "0" |
gpec11_counter_reset_wm |
|
|
| 18 | "0" |
gpec11_systime_reset_wm |
|
|
| 17 | "0" |
gpec10_counter_reset_wm |
|
|
| 16 | "0" |
gpec10_systime_reset_wm |
|
|
| 15 | "0" |
gpec17_counter_reset |
|
|
| 14 | "0" |
gpec17_systime_reset |
|
|
| 13 | "0" |
gpec16_counter_reset |
|
|
| 12 | "0" |
gpec16_systime_reset |
|
|
| 11 | "0" |
gpec15_counter_reset |
|
|
| 10 | "0" |
gpec15_systime_reset |
|
|
| 9 | "0" |
gpec14_counter_reset |
|
|
| 8 | "0" |
gpec14_systime_reset |
|
|
| 7 | "0" |
gpec13_counter_reset |
|
|
| 6 | "0" |
gpec13_systime_reset |
|
|
| 5 | "0" |
gpec12_counter_reset |
|
|
| 4 | "0" |
gpec12_systime_reset |
|
|
| 3 | "0" |
gpec11_counter_reset |
|
|
| 2 | "0" |
gpec11_systime_reset |
|
|
| 1 | "0" |
gpec10_counter_reset |
|
|
| 0 | "0" |
gpec10_systime_reset |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | gxc_lt_systime_ns |
| 1 | 4 | R | gxc_lt_systime_s |
| 2 | 8 | R | gxc_lt_systime_global_ns |
| 3 | c | R | gxc_lt_systime_global_s |
| 4 | 10 | R | gxc_lt_counter_lo |
| 5 | 14 | R | gxc_lt_counter_hi |
| 6 | 18 | W | gxc_lt_systimes_latch |
| 7 | 1c | - | reserved |
| gxc_lt_systime_ns |
|
|||
| R |
Address : 0x07d82f00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_systime_s |
|
|||
| R |
Address : 0x07d82f04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_systime_global_ns |
|
|||
| R |
Address : 0x07d82f08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_systime_global_s |
|
|||
| R |
Address : 0x07d82f0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_counter_lo |
|
|||
| R |
Address : 0x07d82f10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_counter_hi |
|
|||
| R |
Address : 0x07d82f14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| gxc_lt_systimes_latch |
|
|||
| W |
0x00000000 |
Address : 0x07d82f18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
counter_hi |
||
| 4 | "0" |
counter_lo |
||
| 3 | "0" |
systime_global_s |
||
| 2 | "0" |
systime_global_ns |
||
| 1 | "0" |
systime_s |
||
| 0 | "0" |
systime_ns |
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gxc_distribute_sync_select |
| 1 | 4 | R/W | gxc_distribute_sync_periode |
| 2 | 8 | R/W | gxc_distribute_sync_time_ns |
| 3 | c | R/W | gxc_distribute_sync_time_s |
| 4 | 10 | R/W | gxc_distribute_sync_enable |
| 5-7 | 14-1c | - | reserved |
| gxc_distribute_sync_select | ||||
| R/W |
0x00000000 |
Address@gxc_distribute_sync : 0x07d82f20 Address@gxc_distribute_sync_global : 0x07d82f40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sync0_1 |
|
|
| gxc_distribute_sync_periode |
|
|||
| R/W |
0x00000000 |
Address@gxc_distribute_sync : 0x07d82f24 Address@gxc_distribute_sync_global : 0x07d82f44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| gxc_distribute_sync_time_ns |
|
|||
| R/W |
0x00000000 |
Address@gxc_distribute_sync : 0x07d82f28 Address@gxc_distribute_sync_global : 0x07d82f48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_distribute_sync_time_s |
|
|||
| R/W |
0x00000000 |
Address@gxc_distribute_sync : 0x07d82f2c Address@gxc_distribute_sync_global : 0x07d82f4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gxc_distribute_sync_enable | ||||
| R/W |
0x00000000 |
Address@gxc_distribute_sync : 0x07d82f30 Address@gxc_distribute_sync_global : 0x07d82f50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
cycle |
|
|
| 0 | "0" |
clk |
|
|
| global_read_buffer_0 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_1 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_2 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_3 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8400c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_4 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_5 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_6 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_7 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8401c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_8 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_9 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_10 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_11 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8402c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_12 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_13 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_14 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_15 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8403c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_16 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_17 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_18 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_19 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8404c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_20 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_21 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_22 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_23 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8405c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_24 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_25 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_26 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_27 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8406c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_28 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_29 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_30 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_31 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8407c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_32 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_33 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_34 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_35 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8408c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_36 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_37 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_38 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_39 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8409c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_40 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_41 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_42 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_43 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_44 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_45 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_46 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_47 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_48 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_49 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_50 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_51 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_52 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_53 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_54 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_55 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_56 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_57 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_58 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_59 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_60 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_61 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_62 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_63 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d840fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_64 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_65 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_66 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_67 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8410c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_68 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_69 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_70 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84118 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_71 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8411c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_72 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_73 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_74 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_75 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8412c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_76 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_77 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_78 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84138 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_79 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8413c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_80 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_81 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_82 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_83 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8414c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_84 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84150 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_85 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_86 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84158 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_87 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8415c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_88 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84160 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_89 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_90 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84168 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_91 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8416c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_92 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84170 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_93 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84174 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_94 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84178 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_95 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8417c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_96 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84180 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_97 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_98 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84188 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_99 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8418c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_100 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84190 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_101 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_102 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84198 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_103 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8419c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_104 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_105 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_106 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_107 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_108 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_109 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_110 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_111 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_112 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_113 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_114 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_115 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_116 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_117 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_118 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_119 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_120 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_121 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_122 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_123 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_124 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_125 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_126 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_127 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d841fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_128 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84200 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_129 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84204 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_130 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84208 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_131 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8420c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_132 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84210 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_133 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84214 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_134 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84218 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_135 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8421c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_136 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84220 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_137 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84224 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_138 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84228 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_139 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8422c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_140 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84230 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_141 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84234 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_142 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84238 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_143 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8423c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_144 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84240 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_145 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84244 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_146 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84248 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_147 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8424c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_148 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84250 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_149 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84254 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_150 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84258 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_151 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8425c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_152 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84260 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_153 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84264 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_154 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84268 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_155 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8426c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_156 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84270 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_157 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84274 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_158 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84278 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_159 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8427c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_160 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84280 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_161 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84284 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_162 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84288 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_163 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8428c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_164 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84290 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_165 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84294 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_166 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84298 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_167 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8429c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_168 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_169 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_170 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_171 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_172 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_173 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_174 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_175 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_176 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_177 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_178 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_179 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_180 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_181 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_182 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_183 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_184 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_185 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_186 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_187 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_188 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_189 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_190 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_191 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d842fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_192 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84300 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_193 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84304 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_194 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84308 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_195 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8430c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_196 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84310 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_197 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84314 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_198 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84318 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_199 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8431c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_200 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84320 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_201 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84324 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_202 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84328 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_203 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8432c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_204 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84330 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_205 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84334 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_206 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84338 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_207 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8433c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_208 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84340 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_209 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84344 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_210 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84348 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_211 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8434c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_212 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84350 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_213 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84354 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_214 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84358 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_215 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8435c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_216 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84360 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_217 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84364 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_218 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84368 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_219 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8436c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_220 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84370 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_221 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84374 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_222 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84378 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_223 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8437c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_224 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84380 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_225 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84384 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_226 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84388 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_227 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8438c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_228 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84390 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_229 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84394 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_230 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84398 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_231 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8439c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_232 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_233 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_234 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_235 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_236 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_237 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_238 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_239 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_240 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_241 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_242 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_243 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_244 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_245 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_246 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_247 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_248 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_249 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_250 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_251 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_252 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_253 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_254 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_255 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d843fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_256 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_257 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_258 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_259 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8440c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_260 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_261 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_262 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_263 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8441c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_264 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84420 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_265 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84424 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_266 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84428 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_267 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8442c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_268 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84430 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_269 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84434 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_270 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84438 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_271 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8443c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_272 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84440 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_273 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84444 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_274 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84448 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_275 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8444c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_276 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84450 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_277 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84454 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_278 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84458 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_279 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8445c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_280 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84460 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_281 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84464 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_282 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84468 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_283 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8446c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_284 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84470 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_285 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84474 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_286 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84478 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_287 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8447c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_288 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84480 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_289 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84484 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_290 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84488 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_291 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8448c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_292 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84490 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_293 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84494 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_294 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84498 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_295 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8449c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_296 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_297 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_298 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_299 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_300 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_301 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_302 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_303 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_304 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_305 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_306 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_307 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_308 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_309 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_310 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_311 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_312 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_313 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_314 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_315 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_316 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_317 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_318 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_319 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d844fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_320 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_321 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_322 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_323 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8450c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_324 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_325 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_326 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84518 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_327 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8451c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_328 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_329 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_330 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_331 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8452c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_332 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_333 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_334 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84538 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_335 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8453c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_336 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84540 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_337 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84544 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_338 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_339 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8454c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_340 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_341 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_342 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_343 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8455c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_344 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_345 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_346 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_347 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8456c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_348 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_349 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_350 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84578 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_351 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8457c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_352 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_353 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_354 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_355 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8458c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_356 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_357 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_358 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84598 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_359 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8459c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_360 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_361 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_362 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_363 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_364 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_365 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_366 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_367 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_368 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_369 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_370 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_371 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_372 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_373 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_374 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_375 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_376 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_377 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_378 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_379 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_380 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_381 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_382 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_383 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d845fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_384 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84600 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_385 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84604 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_386 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_387 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8460c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_388 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_389 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_390 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84618 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_391 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8461c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_392 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84620 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_393 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84624 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_394 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84628 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_395 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8462c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_396 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84630 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_397 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84634 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_398 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84638 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_399 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8463c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_400 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84640 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_401 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84644 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_402 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84648 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_403 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8464c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_404 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84650 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_405 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84654 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_406 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84658 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_407 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8465c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_408 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84660 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_409 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84664 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_410 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84668 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_411 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8466c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_412 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84670 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_413 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84674 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_414 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84678 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_415 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8467c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_416 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84680 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_417 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84684 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_418 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84688 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_419 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8468c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_420 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84690 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_421 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84694 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_422 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84698 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_423 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8469c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_424 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_425 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_426 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_427 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_428 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_429 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_430 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_431 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_432 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_433 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_434 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_435 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_436 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_437 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_438 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_439 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_440 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_441 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_442 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_443 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_444 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_445 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_446 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_447 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d846fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_448 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84700 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_449 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84704 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_450 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84708 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_451 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8470c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_452 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84710 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_453 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84714 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_454 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84718 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_455 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8471c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_456 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84720 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_457 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84724 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_458 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84728 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_459 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8472c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_460 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84730 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_461 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84734 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_462 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84738 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_463 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8473c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_464 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84740 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_465 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84744 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_466 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84748 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_467 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8474c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_468 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84750 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_469 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84754 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_470 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84758 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_471 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8475c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_472 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84760 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_473 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84764 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_474 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84768 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_475 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8476c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_476 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84770 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_477 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84774 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_478 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84778 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_479 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8477c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_480 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84780 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_481 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84784 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_482 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84788 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_483 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8478c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_484 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84790 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_485 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84794 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_486 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d84798 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_487 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d8479c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_488 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_489 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_490 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_491 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_492 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_493 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_494 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_495 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_496 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_497 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_498 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_499 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_500 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_501 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_502 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_503 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_504 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_505 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_506 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_507 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_508 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_509 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_510 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_read_buffer_511 |
|
|||
| R/W |
0x00000003 |
Address : 0x07d847fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "11" |
val |
|
|
| global_write_buffer_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_2 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_3 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8480c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_4 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_5 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_6 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_7 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8481c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_8 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_9 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84824 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_10 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84828 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_11 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8482c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_12 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84830 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_13 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84834 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_14 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84838 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_15 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8483c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_16 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84840 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_17 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84844 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_18 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84848 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_19 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8484c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_20 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84850 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_21 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84854 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_22 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84858 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_23 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8485c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_24 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84860 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_25 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84864 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_26 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84868 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_27 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8486c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_28 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84870 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_29 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84874 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_30 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84878 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_31 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8487c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_32 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84880 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_33 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84884 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_34 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84888 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_35 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8488c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_36 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84890 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_37 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84894 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_38 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84898 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_39 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8489c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_40 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_41 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_42 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_43 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_44 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_45 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_46 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_47 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_48 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_49 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_50 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_51 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_52 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_53 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_54 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_55 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_56 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_57 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_58 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_59 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_60 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_61 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_62 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_63 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d848fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_64 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84900 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_65 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84904 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_66 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84908 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_67 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8490c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_68 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84910 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_69 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84914 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_70 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84918 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_71 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8491c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_72 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84920 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_73 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84924 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_74 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84928 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_75 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8492c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_76 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84930 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_77 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84934 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_78 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84938 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_79 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8493c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_80 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84940 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_81 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84944 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_82 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84948 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_83 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8494c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_84 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84950 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_85 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84954 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_86 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84958 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_87 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8495c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_88 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84960 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_89 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84964 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_90 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84968 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_91 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8496c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_92 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84970 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_93 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84974 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_94 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84978 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_95 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8497c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_96 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84980 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_97 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84984 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_98 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84988 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_99 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8498c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_100 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84990 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_101 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84994 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_102 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84998 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_103 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d8499c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_104 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_105 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_106 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_107 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_108 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_109 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_110 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_111 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_112 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_113 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_114 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_115 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_116 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_117 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_118 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_119 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_120 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_121 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_122 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_123 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_124 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_125 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_126 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_127 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d849fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_128 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_129 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_130 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_131 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_132 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_133 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_134 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_135 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_136 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_137 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_138 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_139 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_140 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_141 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_142 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_143 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_144 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_145 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_146 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_147 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_148 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_149 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_150 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_151 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_152 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_153 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_154 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_155 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_156 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_157 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_158 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_159 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_160 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_161 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_162 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_163 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_164 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_165 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_166 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_167 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84a9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_168 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84aa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_169 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84aa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_170 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84aa8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_171 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84aac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_172 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ab0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_173 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ab4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_174 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ab8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_175 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84abc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_176 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ac0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_177 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ac4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_178 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ac8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_179 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84acc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_180 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ad0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_181 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ad4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_182 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ad8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_183 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84adc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_184 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ae0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_185 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ae4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_186 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ae8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_187 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84aec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_188 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84af0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_189 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84af4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_190 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84af8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_191 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84afc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_192 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_193 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_194 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_195 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_196 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_197 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_198 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_199 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_200 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_201 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_202 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_203 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_204 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_205 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_206 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_207 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_208 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_209 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_210 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_211 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_212 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_213 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_214 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_215 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_216 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_217 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_218 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_219 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_220 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_221 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_222 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_223 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_224 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_225 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_226 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_227 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_228 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_229 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_230 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_231 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84b9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_232 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ba0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_233 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ba4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_234 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ba8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_235 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_236 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_237 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_238 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_239 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_240 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_241 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_242 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_243 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bcc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_244 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_245 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_246 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_247 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_248 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84be0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_249 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84be4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_250 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84be8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_251 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_252 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bf0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_253 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bf4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_254 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bf8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_255 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84bfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_256 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_257 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_258 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_259 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_260 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_261 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_262 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_263 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_264 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_265 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_266 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_267 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_268 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_269 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_270 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_271 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_272 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_273 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_274 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_275 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_276 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_277 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_278 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_279 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_280 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_281 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_282 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_283 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_284 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_285 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_286 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_287 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_288 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_289 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_290 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_291 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_292 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_293 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_294 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_295 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84c9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_296 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ca0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_297 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ca4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_298 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ca8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_299 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_300 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_301 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_302 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_303 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_304 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_305 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_306 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_307 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ccc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_308 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_309 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_310 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_311 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_312 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ce0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_313 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ce4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_314 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ce8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_315 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_316 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cf0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_317 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cf4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_318 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cf8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_319 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84cfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_320 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_321 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_322 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_323 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_324 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_325 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_326 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_327 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_328 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_329 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_330 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_331 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_332 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_333 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_334 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_335 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_336 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_337 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_338 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_339 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_340 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_341 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_342 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_343 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_344 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_345 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_346 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_347 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_348 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_349 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_350 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_351 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_352 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_353 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_354 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_355 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_356 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_357 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_358 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_359 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84d9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_360 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84da0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_361 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84da4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_362 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84da8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_363 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_364 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84db0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_365 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84db4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_366 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84db8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_367 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_368 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_369 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_370 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_371 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dcc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_372 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_373 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_374 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_375 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ddc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_376 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84de0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_377 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84de4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_378 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84de8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_379 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_380 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84df0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_381 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84df4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_382 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84df8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_383 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84dfc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_384 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_385 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_386 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_387 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_388 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_389 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_390 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_391 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_392 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_393 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_394 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_395 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_396 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_397 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_398 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_399 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_400 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_401 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_402 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_403 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_404 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_405 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_406 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_407 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_408 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_409 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_410 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_411 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_412 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_413 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_414 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_415 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_416 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_417 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_418 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_419 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_420 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_421 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_422 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_423 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84e9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_424 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ea0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_425 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ea4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_426 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ea8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_427 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84eac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_428 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84eb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_429 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84eb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_430 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84eb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_431 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ebc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_432 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ec0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_433 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ec4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_434 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ec8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_435 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ecc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_436 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ed0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_437 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ed4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_438 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ed8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_439 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84edc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_440 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ee0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_441 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ee4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_442 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ee8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_443 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84eec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_444 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ef0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_445 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ef4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_446 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ef8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_447 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_448 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_449 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_450 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_451 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_452 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_453 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_454 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_455 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_456 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_457 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_458 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_459 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_460 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_461 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_462 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_463 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_464 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_465 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_466 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_467 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_468 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_469 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_470 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_471 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_472 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_473 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_474 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_475 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_476 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_477 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_478 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_479 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_480 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_481 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_482 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_483 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_484 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_485 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_486 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_487 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84f9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_488 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_489 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_490 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fa8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_491 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_492 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_493 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fb4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_494 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_495 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fbc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_496 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fc0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_497 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fc4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_498 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fc8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_499 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fcc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_500 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fd0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_501 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fd4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_502 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fd8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_503 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fdc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_504 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fe0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_505 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fe4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_506 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fe8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_507 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84fec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_508 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ff0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_509 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ff4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_510 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ff8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| global_write_buffer_511 |
|
|||
| R/W |
0x00000000 |
Address : 0x07d84ffc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0-300 | 0-c00 | - | reserved |
| 301 | c04 | W | stm_apb_stmdmastartr |
| 302 | c08 | W | stm_apb_stmdmastopr |
| 303 | c0c | R | stm_apb_stmdmastatr |
| 304 | c10 | R/W | stm_apb_stmdmactlr |
| 305-33e | c14-cf8 | - | reserved |
| 33f | cfc | R | stm_apb_stmdmaidr |
| 340 | d00 | R/W | stm_apb_stmheer |
| 341-347 | d04-d1c | - | reserved |
| 348 | d20 | R/W | stm_apb_stmheter |
| 349-357 | d24-d5c | - | reserved |
| 358 | d60 | R/W | stm_apb_stmhebsr |
| 359 | d64 | R/W | stm_apb_stmhemcr |
| 35a | d68 | R/W | stm_apb_stmheextmuxr |
| 35b-37c | d6c-df0 | - | reserved |
| 37d | df4 | R | stm_apb_stmhemastr |
| 37e | df8 | R | stm_apb_stmhefeat1r |
| 37f | dfc | R | stm_apb_stmheidr |
| 380 | e00 | R/W | stm_apb_stmsper |
| 381-387 | e04-e1c | - | reserved |
| 388 | e20 | R/W | stm_apb_stmspter |
| 389-397 | e24-e5c | - | reserved |
| 398 | e60 | R/W | stm_apb_stmspscr |
| 399 | e64 | R/W | stm_apb_stmspmscr |
| 39a | e68 | R/W | stm_apb_stmspoverrider |
| 39b | e6c | R/W | stm_apb_stmspmoverrider |
| 39c | e70 | R/W | stm_apb_stmsptrigcsr |
| 39d-39f | e74-e7c | - | reserved |
| 3a0 | e80 | R/W | stm_apb_stmtcsr |
| 3a1 | e84 | W | stm_apb_stmtsstimr |
| 3a2 | e88 | - | reserved |
| 3a3 | e8c | R/W | stm_apb_stmtsfreqr |
| 3a4 | e90 | R/W | stm_apb_stmsyncr |
| 3a5 | e94 | R/W | stm_apb_stmauxcr |
| 3a6-3a7 | e98-e9c | - | reserved |
| 3a8 | ea0 | R | stm_apb_stmfeat1r |
| 3a9 | ea4 | R | stm_apb_stmfeat2r |
| 3aa | ea8 | R | stm_apb_stmfeat3r |
| 3ab-3b9 | eac-ee4 | - | reserved |
| 3ba | ee8 | W | stm_apb_stmittrigger |
| 3bb | eec | W | stm_apb_stmitatbdata0 |
| 3bc | ef0 | R | stm_apb_stmitatbctr2 |
| 3bd | ef4 | W | stm_apb_stmitatbid |
| 3be | ef8 | W | stm_apb_stmitatbctr0 |
| 3bf | efc | - | reserved |
| 3c0 | f00 | R/W | stm_apb_stmitctrl |
| 3c1-3e7 | f04-f9c | - | reserved |
| 3e8 | fa0 | R/W | stm_apb_stmclaimset |
| 3e9 | fa4 | R/W | stm_apb_stmclaimclr |
| 3ea-3eb | fa8-fac | - | reserved |
| 3ec | fb0 | W | stm_apb_stmlar |
| 3ed | fb4 | R | stm_apb_stmlsr |
| 3ee | fb8 | R | stm_apb_stmauthstatus |
| 3ef | fbc | R | stm_apb_stmdevarch |
| 3f0-3f1 | fc0-fc4 | - | reserved |
| 3f2 | fc8 | R | stm_apb_stmdevid |
| 3f3 | fcc | R | stm_apb_stmdevtype |
| 3f4 | fd0 | R | stm_apb_stmpidr4 |
| 3f5-3f7 | fd4-fdc | - | reserved |
| 3f8 | fe0 | R | stm_apb_stmpidr0 |
| 3f9 | fe4 | R | stm_apb_stmpidr1 |
| 3fa | fe8 | R | stm_apb_stmpidr2 |
| 3fb | fec | R | stm_apb_stmpidr3 |
| 3fc | ff0 | R | stm_apb_stmcidr0 |
| 3fd | ff4 | R | stm_apb_stmcidr1 |
| 3fe | ff8 | R | stm_apb_stmcidr2 |
| 3ff | ffc | R | stm_apb_stmcidr3 |
| 400-3fff | 1000-fffc | - | reserved |
| stm_apb_stmdmastartr |
|
|||
| W |
0x00000000 |
Address : 0x10170c04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
start |
|
|
| stm_apb_stmdmastopr |
|
|||
| W |
0x00000000 |
Address : 0x10170c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
stop |
|
|
| stm_apb_stmdmastatr |
|
|||
| R |
Address : 0x10170c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | status |
|
||
| stm_apb_stmdmactlr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 2 | "00" |
sens |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| stm_apb_stmdmaidr |
|
|||
| R |
Address : 0x10170cfc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 12 | - |
reserved | ||
| 11 - 8 | vendspec |
|
||
| 7 - 4 | classrev |
|
||
| 3 - 0 | class |
|
||
| stm_apb_stmheer |
|
|||
| R/W |
0x00000000 |
Address : 0x10170d00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
hee |
|
|
| stm_apb_stmheter |
|
|||
| R/W |
0x00000000 |
Address : 0x10170d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
hete |
|
|
| stm_apb_stmhebsr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170d60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
hebs |
|
|
| stm_apb_stmhemcr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170d64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
atbtrigen |
|
|
| 6 | "0" |
trigclear |
|
|
| 5 | "0" |
trigstatus |
|
|
| 4 | "0" |
trigctl |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
errdetect |
|
|
| 1 | "0" |
compen |
|
|
| 0 | "0" |
en |
|
|
| stm_apb_stmheextmuxr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170d68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
extmux |
|
|
| stm_apb_stmhemastr |
|
|||
| R |
Address : 0x10170df4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | master |
|
||
| stm_apb_stmhefeat1r |
|
|||
| R |
Address : 0x10170df8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | - |
reserved | ||
| 30 - 28 | heextmuxsize |
|
||
| 27 - 24 | - |
reserved | ||
| 23 - 15 | numhe |
|
||
| 14 - 6 | - |
reserved | ||
| 5 - 4 | hecomp |
|
||
| 3 | hemastr |
|
||
| 2 | heerr |
|
||
| 1 | - |
reserved | ||
| 0 | heter |
|
||
| stm_apb_stmheidr |
|
|||
| R |
Address : 0x10170dfc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 12 | - |
reserved | ||
| 11 - 8 | vendspec |
|
||
| 7 - 4 | classrev |
|
||
| 3 - 0 | class |
|
||
| stm_apb_stmsper |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
spe |
|
|
| stm_apb_stmspter |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
spte |
|
|
| stm_apb_stmspscr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0x0 |
portsel |
|
|
| 19 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
portctl |
|
|
| stm_apb_stmspmscr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0x0 |
mastsel |
|
|
| 14 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mastctl |
|
|
| stm_apb_stmspoverrider |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0x0 |
portsel |
|
|
| 14 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
overts |
|
|
| 1 - 0 | "00" |
overctl |
|
|
| stm_apb_stmspmoverrider |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0x0 |
mastsel |
|
|
| 14 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mastctl |
|
|
| stm_apb_stmsptrigcsr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
atbtrigen_dir |
|
|
| 3 | "0" |
atbtrigen_te |
|
|
| 2 | "0" |
trigclear |
|
|
| 1 | "0" |
trigstatus |
|
|
| 0 | "0" |
trigctl |
|
|
| stm_apb_stmtcsr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
busy |
|
|
| 22 - 16 | "0000000" |
traceid |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
tsprescale |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
compen |
|
|
| 4 | "0" |
swoen |
|
|
| 3 | "0" |
hwten |
|
|
| 2 | "0" |
syncen |
|
|
| 1 | "0" |
tsen |
|
|
| 0 | "0" |
en |
|
|
| stm_apb_stmtsstimr |
|
|||
| W |
0x00000000 |
Address : 0x10170e84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
forcets |
|
|
| stm_apb_stmtsfreqr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
freq |
|
|
| stm_apb_stmsyncr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
mode |
|
|
| 11 - 0 | 0x0 |
count |
|
|
| stm_apb_stmauxcr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170e94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
qhwevoverride |
|
|
| 6 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
priorinvdis |
|
|
| 1 | "0" |
asyncpe |
|
|
| 0 | "0" |
fifoaf |
|
|
| stm_apb_stmfeat1r |
|
|||
| R |
Address : 0x10170ea0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 22 | swoen |
|
||
| 21 - 20 | syncen |
|
||
| 19 - 18 | hwten |
|
||
| 17 - 16 | tsprescale |
|
||
| 15 - 14 | trigctl |
|
||
| 13 - 10 | tracebus |
|
||
| 9 - 8 | sync |
|
||
| 7 | forcets |
|
||
| 6 | tsfreq |
|
||
| 5 - 4 | ts |
|
||
| 3 - 0 | prot |
|
||
| stm_apb_stmfeat2r |
|
|||
| R |
Address : 0x10170ea4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 18 | - |
reserved | ||
| 17 - 16 | sptype |
|
||
| 15 - 12 | dsize |
|
||
| 11 | - |
reserved | ||
| 10 - 9 | sptrtype |
|
||
| 8 - 7 | privmask |
|
||
| 6 | spoverride |
|
||
| 5 - 4 | spcomp |
|
||
| 3 | - |
reserved | ||
| 2 | sper |
|
||
| 1 - 0 | spter |
|
||
| stm_apb_stmfeat3r |
|
|||
| R |
Address : 0x10170ea8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | nummast |
|
||
| stm_apb_stmittrigger |
|
|||
| W |
0x00000000 |
Address : 0x10170ee8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
asyncout_w |
|
|
| 2 | "0" |
trigouthete_w |
|
|
| 1 | "0" |
trigoutsw_w |
|
|
| 0 | "0" |
trigoutspte_w |
|
|
| stm_apb_stmitatbdata0 |
|
|||
| W |
0x00000000 |
Address : 0x10170eec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
atdatam63_w |
|
|
| 7 | "0" |
atdatam55_w |
|
|
| 6 | "0" |
atdatam47_w |
|
|
| 5 | "0" |
atdatam39_w |
|
|
| 4 | "0" |
atdatam31_w |
|
|
| 3 | "0" |
atdatam23_w |
|
|
| 2 | "0" |
atdatam15_w |
|
|
| 1 | "0" |
atdatam7_w |
|
|
| 0 | "0" |
atdatam0_w |
|
|
| stm_apb_stmitatbctr2 |
|
|||
| R |
Address : 0x10170ef0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | afvalidm_r |
|
||
| 0 | atreadym_r |
|
||
| stm_apb_stmitatbid |
|
|||
| W |
0x00000000 |
Address : 0x10170ef4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 - 0 | "0000000" |
atidm_w |
|
|
| stm_apb_stmitatbctr0 |
|
|||
| W |
0x00000000 |
Address : 0x10170ef8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 8 | "000" |
atbytesm_w |
|
|
| 7 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
afreadym_w |
|
|
| 0 | "0" |
atvalidm_w |
|
|
| stm_apb_stmitctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x10170f00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ime |
|
|
| stm_apb_stmclaimset |
|
|||
| R/W |
0x00000000 |
Address : 0x10170fa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
claimset |
|
|
| stm_apb_stmclaimclr |
|
|||
| R/W |
0x00000000 |
Address : 0x10170fa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
claimclr |
|
|
| stm_apb_stmlar |
|
|||
| W |
0x00000000 |
Address : 0x10170fb0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
key |
|
|
| stm_apb_stmlsr |
|
|||
| R |
Address : 0x10170fb4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | type |
|
||
| 1 | locked |
|
||
| 0 | present |
|
||
| stm_apb_stmauthstatus |
|
|||
| R |
Address : 0x10170fb8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 6 | snid |
|
||
| 5 - 4 | sid |
|
||
| 3 - 2 | nsnid |
|
||
| 1 - 0 | nsid |
|
||
| stm_apb_stmdevarch |
|
|||
| R |
Address : 0x10170fbc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 21 | architect |
|
||
| 20 | present |
|
||
| 19 - 16 | revision |
|
||
| 15 - 0 | archid |
|
||
| stm_apb_stmdevid |
|
|||
| R |
Address : 0x10170fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 17 | - |
reserved | ||
| 16 - 0 | numsp |
|
||
| stm_apb_stmdevtype |
|
|||
| R |
Address : 0x10170fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | sub |
|
||
| 3 - 0 | major |
|
||
| stm_apb_stmpidr4 |
|
|||
| R |
Address : 0x10170fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| stm_apb_stmpidr0 |
|
|||
| R |
Address : 0x10170fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| stm_apb_stmpidr1 |
|
|||
| R |
Address : 0x10170fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| stm_apb_stmpidr2 |
|
|||
| R |
Address : 0x10170fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| stm_apb_stmpidr3 |
|
|||
| R |
Address : 0x10170fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| stm_apb_stmcidr0 |
|
|||
| R |
Address : 0x10170ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| stm_apb_stmcidr1 |
|
|||
| R |
Address : 0x10170ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| stm_apb_stmcidr2 |
|
|||
| R |
Address : 0x10170ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| stm_apb_stmcidr3 |
|
|||
| R |
Address : 0x10170ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | system_id_bsys_cfg0 |
| 1 | 4 | R | system_id_bsys_cfg1 |
| 2 | 8 | R | system_id_bsys_cfg2 |
| 3 | c | R | system_id_bsys_cfg3 |
| 4-f | 10-3c | - | reserved |
| 10 | 40 | R | system_id_soc_id |
| 11-3f1 | 44-fc4 | - | reserved |
| 3f2 | fc8 | R | system_id_iidr |
| 3f3 | fcc | - | reserved |
| 3f4 | fd0 | R | system_id_pid4 |
| 3f5 | fd4 | R | system_id_pid5 |
| 3f6 | fd8 | R | system_id_pid6 |
| 3f7 | fdc | R | system_id_pid7 |
| 3f8 | fe0 | R | system_id_pid0 |
| 3f9 | fe4 | R | system_id_pid1 |
| 3fa | fe8 | R | system_id_pid2 |
| 3fb | fec | R | system_id_pid3 |
| 3fc | ff0 | R | system_id_cid0 |
| 3fd | ff4 | R | system_id_cid1 |
| 3fe | ff8 | R | system_id_cid2 |
| 3ff | ffc | R | system_id_cid3 |
| system_id_bsys_cfg0 |
|
|||
| R |
Address : 0x1a000000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 - 0 | num_host_cpu |
|
||
| system_id_bsys_cfg1 |
|
|||
| R |
Address : 0x1a000004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 12 | ext_sys3 |
|
||
| 11 - 8 | ext_sys2 |
|
||
| 7 - 4 | ext_sys1 |
|
||
| 3 - 0 | ext_sys0 |
|
||
| system_id_bsys_cfg2 |
|
|||
| R |
Address : 0x1a000008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 25 | - |
reserved | ||
| 24 | ocvm_en |
|
||
| 23 - 20 | num_exp_mst |
|
||
| 19 - 16 | num_exp_slv |
|
||
| 15 - 0 | - |
reserved | ||
| system_id_bsys_cfg3 |
|
|||
| R |
Address : 0x1a00000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | system_id_bsys_cfg3 | |||
| system_id_soc_id |
|
|||
| R |
Address : 0x1a000040 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| system_id_iidr |
|
|||
| R |
Address : 0x1a000fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| system_id_pid4 |
|
|||
| R |
Address : 0x1a000fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| system_id_pid5 |
|
|||
| R |
Address : 0x1a000fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | system_id_pid5 | |||
| system_id_pid6 |
|
|||
| R |
Address : 0x1a000fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | system_id_pid6 | |||
| system_id_pid7 |
|
|||
| R |
Address : 0x1a000fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | system_id_pid7 | |||
| system_id_pid0 |
|
|||
| R |
Address : 0x1a000fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| system_id_pid1 |
|
|||
| R |
Address : 0x1a000fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| system_id_pid2 |
|
|||
| R |
Address : 0x1a000fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| system_id_pid3 |
|
|||
| R |
Address : 0x1a000fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| system_id_cid0 |
|
|||
| R |
Address : 0x1a000ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| system_id_cid1 |
|
|||
| R |
Address : 0x1a000ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| system_id_cid2 |
|
|||
| R |
Address : 0x1a000ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| system_id_cid3 |
|
|||
| R |
Address : 0x1a000ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| host_base_sys_ctrl_cluster_config |
|
|||
| R/W |
0x00000000 |
Address : 0x1a010000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
cryptodisable |
|
|
| host_base_sys_ctrl_pe0_config |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010010 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
aa64naa32 |
|
||||||
| 2 | "0" |
vinithi |
|
||||||
| 1 | "0" |
cfgte |
|
||||||
| 0 | "0" |
cfgend |
|
||||||
| host_base_sys_ctrl_pe0_rvbaraddr_lw | |||
| R/W |
0x00000000 |
Address : 0x1a010014 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_pe0_rvbaraddr_lw | |
| host_base_sys_ctrl_pe0_rvbaraddr_up | |||
| R |
Address : 0x1a010018 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pe0_rvbaraddr_up | ||
| host_base_sys_ctrl_pe1_config |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010020 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
aa64naa32 |
|
||||||
| 2 | "0" |
vinithi |
|
||||||
| 1 | "0" |
cfgte |
|
||||||
| 0 | "0" |
cfgend |
|
||||||
| host_base_sys_ctrl_pe1_rvbaraddr_lw | |||
| R/W |
0x00000000 |
Address : 0x1a010024 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_pe1_rvbaraddr_lw | |
| host_base_sys_ctrl_pe1_rvbaraddr_up | |||
| R |
Address : 0x1a010028 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pe1_rvbaraddr_up | ||
| host_base_sys_ctrl_pe2_config |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010030 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
aa64naa32 |
|
||||||
| 2 | "0" |
vinithi |
|
||||||
| 1 | "0" |
cfgte |
|
||||||
| 0 | "0" |
cfgend |
|
||||||
| host_base_sys_ctrl_pe2_rvbaraddr_lw | |||
| R/W |
0x00000000 |
Address : 0x1a010034 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_pe2_rvbaraddr_lw | |
| host_base_sys_ctrl_pe2_rvbaraddr_up | |||
| R |
Address : 0x1a010038 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pe2_rvbaraddr_up | ||
| host_base_sys_ctrl_pe3_config |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010040 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
aa64naa32 |
|
||||||
| 2 | "0" |
vinithi |
|
||||||
| 1 | "0" |
cfgte |
|
||||||
| 0 | "0" |
cfgend |
|
||||||
| host_base_sys_ctrl_pe3_rvbaraddr_lw | |||
| R/W |
0x00000000 |
Address : 0x1a010044 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_pe3_rvbaraddr_lw | |
| host_base_sys_ctrl_pe3_rvbaraddr_up | |||
| R |
Address : 0x1a010048 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pe3_rvbaraddr_up | ||
| host_base_sys_ctrl_host_rst_syn | |||
| R |
Address : 0x1a010200 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_host_rst_syn | ||
| host_base_sys_ctrl_host_cpu_boot_msk |
|
||||||||
| R/W |
0x00000001 |
Address : 0x1a010300 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | ||||||
| 3 - 0 | "0001" |
boot_msk |
|
||||||
| host_base_sys_ctrl_host_cpu_clus_pwr_req | ||||||||
| R/W |
0x00000000 |
Address : 0x1a010304 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||
| 1 | "0" |
mem_ret_req |
|
|||||
| 0 | "0" |
pwr_req |
|
|||||
| host_base_sys_ctrl_host_cpu_wakeup |
|
|||
| R/W |
0x00000000 |
Address : 0x1a010308 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
core_wakeup |
|
|
| host_base_sys_ctrl_ext_sys0_rst_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010310 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
rst_req |
|
||||||
| 0 | "0" |
cpuwait |
|
||||||
| host_base_sys_ctrl_ext_sys0_rst_st |
|
|||||||||||
| R |
Address : 0x1a010314 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 - 1 | rst_ack |
|
||||||||||
| 0 | - |
reserved | ||||||||||
| host_base_sys_ctrl_ext_sys1_rst_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010318 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
rst_req |
|
||||||
| 0 | "0" |
cpuwait |
|
||||||
| host_base_sys_ctrl_ext_sys1_rst_st |
|
|||||||||||
| R |
Address : 0x1a01031c |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 - 1 | rst_ack |
|
||||||||||
| 0 | - |
reserved | ||||||||||
| host_base_sys_ctrl_ext_sys2_rst_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010320 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
rst_req |
|
||||||
| 0 | "0" |
cpuwait |
|
||||||
| host_base_sys_ctrl_ext_sys2_rst_st |
|
|||||||||||
| R |
Address : 0x1a010324 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 - 1 | rst_ack |
|
||||||||||
| 0 | - |
reserved | ||||||||||
| host_base_sys_ctrl_ext_sys3_rst_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010328 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
rst_req |
|
||||||
| 0 | "0" |
cpuwait |
|
||||||
| host_base_sys_ctrl_ext_sys3_rst_st |
|
|||||||||||
| R |
Address : 0x1a01032c |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 - 1 | rst_ack |
|
||||||||||
| 0 | - |
reserved | ||||||||||
| host_base_sys_ctrl_bsys_pwr_req |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x1a010400 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||
| 5 - 3 | "000" |
systop_pwr_req |
|
|||||||||
| 2 | "0" |
dbgtop_pwr_req |
|
|||||||||
| 1 | "0" |
refclk_req |
|
|||||||||
| 0 | "0" |
wakeup_en |
|
|||||||||
| host_base_sys_ctrl_bsys_pwr_st |
|
|||||||||||
| R |
Address : 0x1a010404 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | - |
reserved | ||||||||||
| 5 - 3 | systop_pwr_st |
|
||||||||||
| 2 | dbgtop_pwr_st |
|
||||||||||
| 1 - 0 | - |
reserved | ||||||||||
| host_base_sys_ctrl_host_sys_lctrl_st | |||
| R |
Address : 0x1a010500 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_host_sys_lctrl_st | ||
| host_base_sys_ctrl_host_sys_lctrl_set | |||
| W |
0x00000000 |
Address : 0x1a010504 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_host_sys_lctrl_set | |
| host_base_sys_ctrl_host_sys_lctrl_clr | |||
| W |
0x00000000 |
Address : 0x1a010508 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_host_sys_lctrl_clr | |
| host_base_sys_ctrl_hostcpuclk_ctrl |
|
||||||||||||
| R/W |
0x00000001 |
Address : 0x1a010800 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||||
| host_base_sys_ctrl_hostcpuclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010804 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 8 | 0 |
- |
reserved | ||||||
| 7 - 0 | "00000000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_hostcpuclk_div1 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010808 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_gicclk_ctrl |
|
||||||||||
| R/W |
0x00000001 |
Address : 0x1a010810 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
||||||||
| 23 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||
| host_base_sys_ctrl_gicclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010814 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_aclk_ctrl |
|
||||||||||
| R/W |
0x00000001 |
Address : 0x1a010820 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
||||||||
| 23 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||
| host_base_sys_ctrl_aclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010824 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_ctrlclk_ctrl |
|
||||||||||
| R/W |
0x00000001 |
Address : 0x1a010830 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
||||||||
| 23 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||
| host_base_sys_ctrl_ctrlclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010834 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_dbgclk_ctrl |
|
||||||||||
| R/W |
0x00000001 |
Address : 0x1a010840 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
||||||||
| 23 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||
| host_base_sys_ctrl_dbgclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010844 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_hostuartclk_ctrl |
|
||||||||||||
| R/W |
0x00000001 |
Address : 0x1a010850 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||||
| host_base_sys_ctrl_hostuartclk_div0 |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a010854 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00000" |
clkdiv |
|
||||||
| host_base_sys_ctrl_refclk_ctrl |
|
|||
| R/W |
0x00000001 |
Address : 0x1a010860 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
|
| 23 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
clkselect_cur |
|
|
| 7 - 0 | "00000001" |
clkselect |
|
|
| host_base_sys_ctrl_clkforce_st | |||
| R |
Address : 0x1a010a00 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_clkforce_st | ||
| host_base_sys_ctrl_clkforce_set | |||
| W |
0x00000000 |
Address : 0x1a010a04 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_clkforce_set | |
| host_base_sys_ctrl_clkforce_clr | |||
| W |
0x00000000 |
Address : 0x1a010a08 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
host_base_sys_ctrl_clkforce_clr | |
| host_base_sys_ctrl_pll_st |
|
|||
| R |
Address : 0x1a010a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | cpuplllock_st |
|
||
| 0 | sysplllock_st |
|
||
| host_base_sys_ctrl_host_ppu_int_st | |||
| R |
Address : 0x1a010b00 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_host_ppu_int_st | ||
| host_base_sys_ctrl_pid4 |
|
|||
| R |
Address : 0x1a010fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| host_base_sys_ctrl_pid5 |
|
|||
| R |
Address : 0x1a010fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pid5 | |||
| host_base_sys_ctrl_pid6 |
|
|||
| R |
Address : 0x1a010fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pid6 | |||
| host_base_sys_ctrl_pid7 |
|
|||
| R |
Address : 0x1a010fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | host_base_sys_ctrl_pid7 | |||
| host_base_sys_ctrl_pid0 |
|
|||
| R |
Address : 0x1a010fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| host_base_sys_ctrl_pid1 |
|
|||
| R |
Address : 0x1a010fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| host_base_sys_ctrl_pid2 |
|
|||
| R |
Address : 0x1a010fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| host_base_sys_ctrl_pid3 |
|
|||
| R |
Address : 0x1a010fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| host_base_sys_ctrl_cid0 |
|
|||
| R |
Address : 0x1a010ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| host_base_sys_ctrl_cid1 |
|
|||
| R |
Address : 0x1a010ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| host_base_sys_ctrl_cid2 |
|
|||
| R |
Address : 0x1a010ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| host_base_sys_ctrl_cid3 |
|
|||
| R |
Address : 0x1a010ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | ppu_pwpr |
| 1 | 4 | R/W | ppu_pmer |
| 2 | 8 | R | ppu_pwsr |
| 3 | c | - | reserved |
| 4 | 10 | R | ppu_disr |
| 5 | 14 | R | ppu_misr |
| 6 | 18 | R | ppu_stsr |
| 7 | 1c | R/W | ppu_unlk |
| 8 | 20 | R/W | ppu_pwcr |
| 9 | 24 | R/W | ppu_ptcr |
| a-b | 28-2c | - | reserved |
| c | 30 | R/W | ppu_imr |
| d | 34 | R/W | ppu_aimr |
| e | 38 | R/W | ppu_isr |
| f | 3c | R/W | ppu_aisr |
| 10 | 40 | R/W | ppu_iesr |
| 11 | 44 | R/W | ppu_opsr |
| 12-13 | 48-4c | - | reserved |
| 14 | 50 | R/W | ppu_funrr |
| 15 | 54 | R/W | ppu_fulrr |
| 16 | 58 | R/W | ppu_memrr |
| 17-57 | 5c-15c | - | reserved |
| 58 | 160 | R/W | ppu_edtr0 |
| 59 | 164 | R/W | ppu_edtr1 |
| 5a-5b | 168-16c | - | reserved |
| 5c | 170 | R/W | ppu_dcdr0 |
| 5d | 174 | R/W | ppu_dcdr1 |
| 5e-3eb | 178-fac | - | reserved |
| 3ec | fb0 | R | ppu_idr0 |
| 3ed | fb4 | R | ppu_idr1 |
| 3ee-3f1 | fb8-fc4 | - | reserved |
| 3f2 | fc8 | R | ppu_iidr |
| 3f3 | fcc | R | ppu_aidr |
| 3f4 | fd0 | R | ppu_pid4 |
| 3f5 | fd4 | R | ppu_pid5 |
| 3f6 | fd8 | R | ppu_pid6 |
| 3f7 | fdc | R | ppu_pid7 |
| 3f8 | fe0 | R | ppu_pid0 |
| 3f9 | fe4 | R | ppu_pid1 |
| 3fa | fe8 | R | ppu_pid2 |
| 3fb | fec | R | ppu_pid3 |
| 3fc | ff0 | R | ppu_cid0 |
| 3fd | ff4 | R | ppu_cid1 |
| 3fe | ff8 | R | ppu_cid2 |
| 3ff | ffc | R | ppu_cid3 |
| ppu_pwpr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020000 Address@app_systop_ppu : 0x1a030000 Address@app_dbgtop_ppu : 0x1a040000 Address@app_clustop_ppu : 0x1bc00000 Address@app_core_ppu0 : 0x1bc10000 Address@secenc_secenctop_ppu : 0x5008d000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
op_dyn_en |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
op_policy |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
lock_en |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
pwr_dyn_en |
|
|
| 7 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
pwr_policy |
|
|
| ppu_pmer |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020004 Address@app_systop_ppu : 0x1a030004 Address@app_dbgtop_ppu : 0x1a040004 Address@app_clustop_ppu : 0x1bc00004 Address@app_core_ppu0 : 0x1bc10004 Address@secenc_secenctop_ppu : 0x5008d004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
emu_en |
|
|
| ppu_pwsr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020008 Address@app_systop_ppu : 0x1a030008 Address@app_dbgtop_ppu : 0x1a040008 Address@app_clustop_ppu : 0x1bc00008 Address@app_core_ppu0 : 0x1bc10008 Address@secenc_secenctop_ppu : 0x5008d008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 25 | - |
reserved | ||
| 24 | op_dyn_status |
|
||
| 23 - 20 | - |
reserved | ||
| 19 - 16 | op_status |
|
||
| 15 - 13 | - |
reserved | ||
| 12 | lock_status |
|
||
| 11 - 9 | - |
reserved | ||
| 8 | pwr_dyn_status |
|
||
| 7 - 4 | - |
reserved | ||
| 3 - 0 | pwr_status |
|
||
| ppu_disr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020010 Address@app_systop_ppu : 0x1a030010 Address@app_dbgtop_ppu : 0x1a040010 Address@app_clustop_ppu : 0x1bc00010 Address@app_core_ppu0 : 0x1bc10010 Address@secenc_secenctop_ppu : 0x5008d010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | op_devactive_status |
|
||
| 23 - 11 | - |
reserved | ||
| 10 - 0 | pwr_devactive_status |
|
||
| ppu_misr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020014 Address@app_systop_ppu : 0x1a030014 Address@app_dbgtop_ppu : 0x1a040014 Address@app_clustop_ppu : 0x1bc00014 Address@app_core_ppu0 : 0x1bc10014 Address@secenc_secenctop_ppu : 0x5008d014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 16 | devdeny_status |
|
||
| 15 - 8 | devaccept_status |
|
||
| 7 - 1 | - |
reserved | ||
| 0 | pcsmpaccept_status |
|
||
| ppu_stsr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020018 Address@app_systop_ppu : 0x1a030018 Address@app_dbgtop_ppu : 0x1a040018 Address@app_clustop_ppu : 0x1bc00018 Address@app_core_ppu0 : 0x1bc10018 Address@secenc_secenctop_ppu : 0x5008d018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | stored_devdeny |
|
||
| ppu_unlk |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a02001c Address@app_systop_ppu : 0x1a03001c Address@app_dbgtop_ppu : 0x1a04001c Address@app_clustop_ppu : 0x1bc0001c Address@app_core_ppu0 : 0x1bc1001c Address@secenc_secenctop_ppu : 0x5008d01c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
unlock |
|
|
| ppu_pwcr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020020 Address@app_systop_ppu : 0x1a030020 Address@app_dbgtop_ppu : 0x1a040020 Address@app_clustop_ppu : 0x1bc00020 Address@app_core_ppu0 : 0x1bc10020 Address@secenc_secenctop_ppu : 0x5008d020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
op_devactiveen |
|
|
| 23 - 19 | 0 |
- |
reserved | |
| 18 - 8 | 0x0 |
wr_devactiveen |
|
|
| 7 - 0 | "00000000" |
devreqen |
|
|
| ppu_ptcr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020024 Address@app_systop_ppu : 0x1a030024 Address@app_dbgtop_ppu : 0x1a040024 Address@app_clustop_ppu : 0x1bc00024 Address@app_core_ppu0 : 0x1bc10024 Address@secenc_secenctop_ppu : 0x5008d024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
dbg_recov_porst_en |
|
|
| 0 | "0" |
warm_rst_devreqen |
|
|
| ppu_imr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020030 Address@app_systop_ppu : 0x1a030030 Address@app_dbgtop_ppu : 0x1a040030 Address@app_clustop_ppu : 0x1bc00030 Address@app_core_ppu0 : 0x1bc10030 Address@secenc_secenctop_ppu : 0x5008d030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
locked_irq_mask |
|
|
| 4 | "0" |
emu_deny_irq_mask |
|
|
| 3 | "0" |
emu_accept_irq_mask |
|
|
| 2 | "0" |
sta_deny_irq_mask |
|
|
| 1 | "0" |
sta_accept_irq_mask |
|
|
| 0 | "0" |
sta_policy_trn_irq_mask |
|
|
| ppu_aimr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020034 Address@app_systop_ppu : 0x1a030034 Address@app_dbgtop_ppu : 0x1a040034 Address@app_clustop_ppu : 0x1bc00034 Address@app_core_ppu0 : 0x1bc10034 Address@secenc_secenctop_ppu : 0x5008d034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
sta_policy_op_irq_mask |
|
|
| 3 | "0" |
sta_policy_pwr_irq_mask |
|
|
| 2 | "0" |
dyn_deny_irq_mask |
|
|
| 1 | "0" |
dyn_accept_irq_mask |
|
|
| 0 | "0" |
unspt_policy_irq_mask |
|
|
| ppu_isr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020038 Address@app_systop_ppu : 0x1a030038 Address@app_dbgtop_ppu : 0x1a040038 Address@app_clustop_ppu : 0x1bc00038 Address@app_core_ppu0 : 0x1bc10038 Address@secenc_secenctop_ppu : 0x5008d038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
op_active_edge_irq |
|
|
| 23 - 19 | 0 |
- |
reserved | |
| 18 - 8 | 0x0 |
pwr_active_edge_irq |
|
|
| 7 | "0" |
other_irq |
|
|
| 6 | 0 |
- |
reserved | |
| 5 | "0" |
locked_irq |
|
|
| 4 | "0" |
emu_deny_irq |
|
|
| 3 | "0" |
emu_accept_irq |
|
|
| 2 | "0" |
sta_deny_irq |
|
|
| 1 | "0" |
sta_accept_irq |
|
|
| 0 | "0" |
sta_policy_trn_irq |
|
|
| ppu_aisr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a02003c Address@app_systop_ppu : 0x1a03003c Address@app_dbgtop_ppu : 0x1a04003c Address@app_clustop_ppu : 0x1bc0003c Address@app_core_ppu0 : 0x1bc1003c Address@secenc_secenctop_ppu : 0x5008d03c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
sta_policy_op_irq |
|
|
| 3 | "0" |
sta_policy_pwr_irq |
|
|
| 2 | "0" |
dyn_deny_irq |
|
|
| 1 | "0" |
dyn_accept_irq |
|
|
| 0 | "0" |
unspt_policy_irq |
|
|
| ppu_iesr |
|
||||||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020040 Address@app_systop_ppu : 0x1a030040 Address@app_dbgtop_ppu : 0x1a040040 Address@app_clustop_ppu : 0x1bc00040 Address@app_core_ppu0 : 0x1bc10040 Address@secenc_secenctop_ppu : 0x5008d040 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | ||||
| 21 - 20 | "00" |
devactive10_edge |
|
||||
| 19 - 18 | "00" |
devactive09_edge |
|
||||
| 17 - 16 | "00" |
devactive08_edge |
|
||||
| 15 - 14 | "00" |
devactive07_edge |
|
||||
| 13 - 12 | "00" |
devactive06_edge |
|
||||
| 11 - 10 | "00" |
devactive05_edge |
|
||||
| 9 - 8 | "00" |
devactive04_edge |
|
||||
| 7 - 6 | "00" |
devactive03_edge |
|
||||
| 5 - 4 | "00" |
devactive02_edge |
|
||||
| 3 - 2 | "00" |
devactive01_edge |
|
||||
| 1 - 0 | "00" |
devactive00_edge |
|
||||
| ppu_opsr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020044 Address@app_systop_ppu : 0x1a030044 Address@app_dbgtop_ppu : 0x1a040044 Address@app_clustop_ppu : 0x1bc00044 Address@app_core_ppu0 : 0x1bc10044 Address@secenc_secenctop_ppu : 0x5008d044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 14 | "00" |
devactive23_edge |
|
|
| 13 - 12 | "00" |
devactive22_edge |
|
|
| 11 - 10 | "00" |
devactive21_edge |
|
|
| 9 - 8 | "00" |
devactive20_edge |
|
|
| 7 - 6 | "00" |
devactive19_edge |
|
|
| 5 - 4 | "00" |
devactive18_edge |
|
|
| 3 - 2 | "00" |
devactive17_edge |
|
|
| 1 - 0 | "00" |
devactive16_edge |
|
|
| ppu_funrr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020050 Address@app_systop_ppu : 0x1a030050 Address@app_dbgtop_ppu : 0x1a040050 Address@app_clustop_ppu : 0x1bc00050 Address@app_core_ppu0 : 0x1bc10050 Address@secenc_secenctop_ppu : 0x5008d050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
ppu_funrr | ||
| ppu_fulrr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020054 Address@app_systop_ppu : 0x1a030054 Address@app_dbgtop_ppu : 0x1a040054 Address@app_clustop_ppu : 0x1bc00054 Address@app_core_ppu0 : 0x1bc10054 Address@secenc_secenctop_ppu : 0x5008d054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
ppu_fulrr | ||
| ppu_memrr |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020058 Address@app_systop_ppu : 0x1a030058 Address@app_dbgtop_ppu : 0x1a040058 Address@app_clustop_ppu : 0x1bc00058 Address@app_core_ppu0 : 0x1bc10058 Address@secenc_secenctop_ppu : 0x5008d058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
ppu_memrr | ||
| ppu_edtr0 |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020160 Address@app_systop_ppu : 0x1a030160 Address@app_dbgtop_ppu : 0x1a040160 Address@app_clustop_ppu : 0x1bc00160 Address@app_core_ppu0 : 0x1bc10160 Address@secenc_secenctop_ppu : 0x5008d160 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
full_ret_del |
|
|
| 23 - 16 | "00000000" |
logic_ret_del |
|
|
| 15 - 8 | "00000000" |
mem_ret_del |
|
|
| 7 - 0 | "00000000" |
off_del |
|
|
| ppu_edtr1 |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020164 Address@app_systop_ppu : 0x1a030164 Address@app_dbgtop_ppu : 0x1a040164 Address@app_clustop_ppu : 0x1bc00164 Address@app_core_ppu0 : 0x1bc10164 Address@secenc_secenctop_ppu : 0x5008d164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
func_ret_del |
|
|
| 7 - 0 | "00000000" |
mem_off_del |
|
|
| ppu_dcdr0 |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020170 Address@app_systop_ppu : 0x1a030170 Address@app_dbgtop_ppu : 0x1a040170 Address@app_clustop_ppu : 0x1bc00170 Address@app_core_ppu0 : 0x1bc10170 Address@secenc_secenctop_ppu : 0x5008d170 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
rst_hwstat_dly |
|
|
| 15 - 8 | "00000000" |
iso_clken_dly |
|
|
| 7 - 0 | "00000000" |
clken_rst_dly |
|
|
| ppu_dcdr1 |
|
|||
| R/W |
0x00000000 |
Address@app_firewall_ppu : 0x1a020174 Address@app_systop_ppu : 0x1a030174 Address@app_dbgtop_ppu : 0x1a040174 Address@app_clustop_ppu : 0x1bc00174 Address@app_core_ppu0 : 0x1bc10174 Address@secenc_secenctop_ppu : 0x5008d174 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
clken_iso_dly |
|
|
| 7 - 0 | "00000000" |
iso_rst_dly |
|
|
| ppu_idr0 |
|
|||||||
| R |
Address@app_firewall_ppu : 0x1a020fb0 Address@app_systop_ppu : 0x1a030fb0 Address@app_dbgtop_ppu : 0x1a040fb0 Address@app_clustop_ppu : 0x1bc00fb0 Address@app_core_ppu0 : 0x1bc10fb0 Address@secenc_secenctop_ppu : 0x5008dfb0 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 30 | - |
reserved | ||||||
| 29 | dyn_wrm_rst_spt |
|
||||||
| 28 | dyn_on_spt |
|
||||||
| 27 | dyn_func_ret_spt |
|
||||||
| 26 | dyn_full_ret_spt |
|
||||||
| 25 | dyn_mem_off_spt |
|
||||||
| 24 | dyn_lgc_ret_spt |
|
||||||
| 23 | dyn_mem_ret_emu_spt |
|
||||||
| 22 | dyn_mem_ret_spt |
|
||||||
| 21 | dyn_off_emu_spt |
|
||||||
| 20 | dyn_off_spt |
|
||||||
| 19 | - |
reserved | ||||||
| 18 | sta_dbg_recov_spt |
|
||||||
| 17 | sta_wrm_rst_spt |
|
||||||
| 16 | sta_on_spt |
|
||||||
| 15 | sta_func_ret_spt |
|
||||||
| 14 | sta_full_ret_spt |
|
||||||
| 13 | sta_mem_off_spt |
|
||||||
| 12 | sta_lgc_ret_spt |
|
||||||
| 11 | sta_mem_ret_emu_spt |
|
||||||
| 10 | sta_mem_ret_spt |
|
||||||
| 9 | sta_off_emu_spt |
|
||||||
| 8 | sta_off_spt |
|
||||||
| 7 - 4 | num_opmode |
|
||||||
| 3 - 0 | devchan |
|
||||||
| ppu_idr1 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fb4 Address@app_systop_ppu : 0x1a030fb4 Address@app_dbgtop_ppu : 0x1a040fb4 Address@app_clustop_ppu : 0x1bc00fb4 Address@app_core_ppu0 : 0x1bc10fb4 Address@secenc_secenctop_ppu : 0x5008dfb4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 | off_mem_ret_trans |
|
||
| 11 | - |
reserved | ||
| 10 | op_active |
|
||
| 9 | sta_policy_op_irq_spt |
|
||
| 8 | sta_policy_pwr_irq_spt |
|
||
| 7 | - |
reserved | ||
| 6 | func_ret_ram_reg |
|
||
| 5 | full_ret_ram_reg |
|
||
| 4 | mem_ret_ram_reg |
|
||
| 3 | - |
reserved | ||
| 2 | lock_spt |
|
||
| 1 | sw_dev_del_spt |
|
||
| 0 | pwr_mode_entry_del_spt |
|
||
| ppu_iidr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fc8 Address@app_systop_ppu : 0x1a030fc8 Address@app_dbgtop_ppu : 0x1a040fc8 Address@app_clustop_ppu : 0x1bc00fc8 Address@app_core_ppu0 : 0x1bc10fc8 Address@secenc_secenctop_ppu : 0x5008dfc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| ppu_aidr |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fcc Address@app_systop_ppu : 0x1a030fcc Address@app_dbgtop_ppu : 0x1a040fcc Address@app_clustop_ppu : 0x1bc00fcc Address@app_core_ppu0 : 0x1bc10fcc Address@secenc_secenctop_ppu : 0x5008dfcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | arch_rev_major |
|
||
| 3 - 0 | arch_rev_minor |
|
||
| ppu_pid4 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fd0 Address@app_systop_ppu : 0x1a030fd0 Address@app_dbgtop_ppu : 0x1a040fd0 Address@app_clustop_ppu : 0x1bc00fd0 Address@app_core_ppu0 : 0x1bc10fd0 Address@secenc_secenctop_ppu : 0x5008dfd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| ppu_pid5 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fd4 Address@app_systop_ppu : 0x1a030fd4 Address@app_dbgtop_ppu : 0x1a040fd4 Address@app_clustop_ppu : 0x1bc00fd4 Address@app_core_ppu0 : 0x1bc10fd4 Address@secenc_secenctop_ppu : 0x5008dfd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ppu_pid5 | |||
| ppu_pid6 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fd8 Address@app_systop_ppu : 0x1a030fd8 Address@app_dbgtop_ppu : 0x1a040fd8 Address@app_clustop_ppu : 0x1bc00fd8 Address@app_core_ppu0 : 0x1bc10fd8 Address@secenc_secenctop_ppu : 0x5008dfd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ppu_pid6 | |||
| ppu_pid7 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fdc Address@app_systop_ppu : 0x1a030fdc Address@app_dbgtop_ppu : 0x1a040fdc Address@app_clustop_ppu : 0x1bc00fdc Address@app_core_ppu0 : 0x1bc10fdc Address@secenc_secenctop_ppu : 0x5008dfdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ppu_pid7 | |||
| ppu_pid0 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fe0 Address@app_systop_ppu : 0x1a030fe0 Address@app_dbgtop_ppu : 0x1a040fe0 Address@app_clustop_ppu : 0x1bc00fe0 Address@app_core_ppu0 : 0x1bc10fe0 Address@secenc_secenctop_ppu : 0x5008dfe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| ppu_pid1 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fe4 Address@app_systop_ppu : 0x1a030fe4 Address@app_dbgtop_ppu : 0x1a040fe4 Address@app_clustop_ppu : 0x1bc00fe4 Address@app_core_ppu0 : 0x1bc10fe4 Address@secenc_secenctop_ppu : 0x5008dfe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| ppu_pid2 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fe8 Address@app_systop_ppu : 0x1a030fe8 Address@app_dbgtop_ppu : 0x1a040fe8 Address@app_clustop_ppu : 0x1bc00fe8 Address@app_core_ppu0 : 0x1bc10fe8 Address@secenc_secenctop_ppu : 0x5008dfe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| ppu_pid3 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020fec Address@app_systop_ppu : 0x1a030fec Address@app_dbgtop_ppu : 0x1a040fec Address@app_clustop_ppu : 0x1bc00fec Address@app_core_ppu0 : 0x1bc10fec Address@secenc_secenctop_ppu : 0x5008dfec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| ppu_cid0 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020ff0 Address@app_systop_ppu : 0x1a030ff0 Address@app_dbgtop_ppu : 0x1a040ff0 Address@app_clustop_ppu : 0x1bc00ff0 Address@app_core_ppu0 : 0x1bc10ff0 Address@secenc_secenctop_ppu : 0x5008dff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| ppu_cid1 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020ff4 Address@app_systop_ppu : 0x1a030ff4 Address@app_dbgtop_ppu : 0x1a040ff4 Address@app_clustop_ppu : 0x1bc00ff4 Address@app_core_ppu0 : 0x1bc10ff4 Address@secenc_secenctop_ppu : 0x5008dff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| ppu_cid2 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020ff8 Address@app_systop_ppu : 0x1a030ff8 Address@app_dbgtop_ppu : 0x1a040ff8 Address@app_clustop_ppu : 0x1bc00ff8 Address@app_core_ppu0 : 0x1bc10ff8 Address@secenc_secenctop_ppu : 0x5008dff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| ppu_cid3 |
|
|||
| R |
Address@app_firewall_ppu : 0x1a020ffc Address@app_systop_ppu : 0x1a030ffc Address@app_dbgtop_ppu : 0x1a040ffc Address@app_clustop_ppu : 0x1bc00ffc Address@app_core_ppu0 : 0x1bc10ffc Address@secenc_secenctop_ppu : 0x5008dffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | cnt_ctrl_cntcr |
| 1 | 4 | R | cnt_ctrl_cntsr |
| 2 | 8 | R/W | cnt_ctrl_cntcv0 |
| 3 | c | R/W | cnt_ctrl_cntcv1 |
| 4-6 | 10-18 | - | reserved |
| 7 | 1c | R | cnt_ctrl_cntid |
| 8 | 20 | R/W | cnt_ctrl_cntfid0 |
| 9 | 24 | R/W | cnt_ctrl_cntfid1 |
| a-2f | 28-bc | - | reserved |
| 30 | c0 | R/W | cnt_ctrl_cntscr |
| 31 | c4 | - | reserved |
| 32 | c8 | R | cnt_ctrl_cntsvl |
| 33 | cc | R | cnt_ctrl_cntsvu |
| 34-3f3 | d0-fcc | - | reserved |
| 3f4 | fd0 | R | cnt_ctrl_counterid0 |
| 3f5 | fd4 | R | cnt_ctrl_counterid1 |
| 3f6 | fd8 | R | cnt_ctrl_counterid2 |
| 3f7 | fdc | R | cnt_ctrl_counterid3 |
| 3f8 | fe0 | R | cnt_ctrl_counterid4 |
| 3f9 | fe4 | R | cnt_ctrl_counterid5 |
| 3fa | fe8 | R | cnt_ctrl_counterid6 |
| 3fb | fec | R | cnt_ctrl_counterid7 |
| 3fc | ff0 | R | cnt_ctrl_counterid8 |
| 3fd | ff4 | R | cnt_ctrl_counterid9 |
| 3fe | ff8 | R | cnt_ctrl_counterid10 |
| 3ff | ffc | R | cnt_ctrl_counterid11 |
| cnt_ctrl_cntcr |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a200000 Address@s32k_cnt_ctrl : 0x1a400000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 8 | 0x0 |
fcreq |
|
|
| 7 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
scen |
|
|
| 1 | "0" |
hdbg |
|
|
| 0 | "0" |
en |
|
|
| cnt_ctrl_cntsr |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200004 Address@s32k_cnt_ctrl : 0x1a400004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | fcack |
|
||
| 7 - 2 | - |
reserved | ||
| 1 | dbgh |
|
||
| 0 | - |
reserved | ||
| cnt_ctrl_cntcv0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a200008 Address@s32k_cnt_ctrl : 0x1a400008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
countvalue |
|
|
| cnt_ctrl_cntcv1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a20000c Address@s32k_cnt_ctrl : 0x1a40000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
countvalue |
|
|
| cnt_ctrl_cntid |
|
||||||||
| R |
Address@refclk_cnt_ctrl : 0x1a20001c Address@s32k_cnt_ctrl : 0x1a40001c |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | |||||||
| 3 - 0 | cntsc |
|
|||||||
| cnt_ctrl_cntfid0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a200020 Address@s32k_cnt_ctrl : 0x1a400020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
frequency |
|
|
| cnt_ctrl_cntfid1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a200024 Address@s32k_cnt_ctrl : 0x1a400024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
frequency |
|
|
| cnt_ctrl_cntscr |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctrl : 0x1a2000c0 Address@s32k_cnt_ctrl : 0x1a4000c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
scaleval |
|
|
| cnt_ctrl_cntsvl | |||
| R |
Address@refclk_cnt_ctrl : 0x1a2000c8 Address@s32k_cnt_ctrl : 0x1a4000c8 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | cnt_ctrl_cntsvl | ||
| cnt_ctrl_cntsvu | |||
| R |
Address@refclk_cnt_ctrl : 0x1a2000cc Address@s32k_cnt_ctrl : 0x1a4000cc |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | cnt_ctrl_cntsvu | ||
| cnt_ctrl_counterid0 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fd0 Address@s32k_cnt_ctrl : 0x1a400fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| cnt_ctrl_counterid1 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fd4 Address@s32k_cnt_ctrl : 0x1a400fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctrl_counterid1 | |||
| cnt_ctrl_counterid2 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fd8 Address@s32k_cnt_ctrl : 0x1a400fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctrl_counterid2 | |||
| cnt_ctrl_counterid3 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fdc Address@s32k_cnt_ctrl : 0x1a400fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctrl_counterid3 | |||
| cnt_ctrl_counterid4 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fe0 Address@s32k_cnt_ctrl : 0x1a400fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cnt_ctrl_counterid5 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fe4 Address@s32k_cnt_ctrl : 0x1a400fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cnt_ctrl_counterid6 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fe8 Address@s32k_cnt_ctrl : 0x1a400fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| cnt_ctrl_counterid7 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200fec Address@s32k_cnt_ctrl : 0x1a400fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| cnt_ctrl_counterid8 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200ff0 Address@s32k_cnt_ctrl : 0x1a400ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cnt_ctrl_counterid9 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200ff4 Address@s32k_cnt_ctrl : 0x1a400ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cnt_ctrl_counterid10 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200ff8 Address@s32k_cnt_ctrl : 0x1a400ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cnt_ctrl_counterid11 |
|
|||
| R |
Address@refclk_cnt_ctrl : 0x1a200ffc Address@s32k_cnt_ctrl : 0x1a400ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | cnt_read_cntcv0 |
| 1 | 4 | R/W | cnt_read_cntcv1 |
| 2-3f3 | 8-fcc | - | reserved |
| 3f4 | fd0 | R | cnt_read_counterid0 |
| 3f5 | fd4 | R | cnt_read_counterid1 |
| 3f6 | fd8 | R | cnt_read_counterid2 |
| 3f7 | fdc | R | cnt_read_counterid3 |
| 3f8 | fe0 | R | cnt_read_counterid4 |
| 3f9 | fe4 | R | cnt_read_counterid5 |
| 3fa | fe8 | R | cnt_read_counterid6 |
| 3fb | fec | R | cnt_read_counterid7 |
| 3fc | ff0 | R | cnt_read_counterid8 |
| 3fd | ff4 | R | cnt_read_counterid9 |
| 3fe | ff8 | R | cnt_read_counterid10 |
| 3ff | ffc | R | cnt_read_counterid11 |
| cnt_read_cntcv0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_read : 0x1a210000 Address@s32k_cnt_read : 0x1a410000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
countvalue |
|
|
| cnt_read_cntcv1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_read : 0x1a210004 Address@s32k_cnt_read : 0x1a410004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
countvalue |
|
|
| cnt_read_counterid0 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fd0 Address@s32k_cnt_read : 0x1a410fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| cnt_read_counterid1 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fd4 Address@s32k_cnt_read : 0x1a410fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_read_counterid1 | |||
| cnt_read_counterid2 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fd8 Address@s32k_cnt_read : 0x1a410fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_read_counterid2 | |||
| cnt_read_counterid3 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fdc Address@s32k_cnt_read : 0x1a410fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_read_counterid3 | |||
| cnt_read_counterid4 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fe0 Address@s32k_cnt_read : 0x1a410fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cnt_read_counterid5 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fe4 Address@s32k_cnt_read : 0x1a410fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cnt_read_counterid6 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fe8 Address@s32k_cnt_read : 0x1a410fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| cnt_read_counterid7 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210fec Address@s32k_cnt_read : 0x1a410fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| cnt_read_counterid8 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210ff0 Address@s32k_cnt_read : 0x1a410ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cnt_read_counterid9 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210ff4 Address@s32k_cnt_read : 0x1a410ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cnt_read_counterid10 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210ff8 Address@s32k_cnt_read : 0x1a410ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cnt_read_counterid11 |
|
|||
| R |
Address@refclk_cnt_read : 0x1a210ffc Address@s32k_cnt_read : 0x1a410ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | cnt_ctl_cntfrq |
| 1 | 4 | R/W | cnt_ctl_cntnsar |
| 2 | 8 | R/W | cnt_ctl_cnttidr |
| 3-f | c-3c | - | reserved |
| 10 | 40 | R/W | cnt_ctl_cntacr0 |
| 11 | 44 | R/W | cnt_ctl_cntacr1 |
| 12 | 48 | R/W | cnt_ctl_cntacr2 |
| 13 | 4c | R/W | cnt_ctl_cntacr3 |
| 14-3f3 | 50-fcc | - | reserved |
| 3f4 | fd0 | R | cnt_ctl_counterid0 |
| 3f5 | fd4 | R | cnt_ctl_counterid1 |
| 3f6 | fd8 | R | cnt_ctl_counterid2 |
| 3f7 | fdc | R | cnt_ctl_counterid3 |
| 3f8 | fe0 | R | cnt_ctl_counterid4 |
| 3f9 | fe4 | R | cnt_ctl_counterid5 |
| 3fa | fe8 | R | cnt_ctl_counterid6 |
| 3fb | fec | R | cnt_ctl_counterid7 |
| 3fc | ff0 | R | cnt_ctl_counterid8 |
| 3fd | ff4 | R | cnt_ctl_counterid9 |
| 3fe | ff8 | R | cnt_ctl_counterid10 |
| 3ff | ffc | R | cnt_ctl_counterid11 |
| cnt_ctl_cntfrq |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220000 Address@s32k_cnt_ctl : 0x1a420000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
clock_frequency |
|
|
| cnt_ctl_cntnsar |
|
|||||||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220004 Address@s32k_cnt_ctl : 0x1a420004 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||
| 7 - 0 | "00000000" |
ns_vector |
|
|||||
| cnt_ctl_cnttidr |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220008 Address@s32k_cnt_ctl : 0x1a420008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
frame7 |
|
|
| 27 - 24 | "0000" |
frame6 |
|
|
| 23 - 20 | "0000" |
frame5 |
|
|
| 19 - 16 | "0000" |
frame4 |
|
|
| 15 - 12 | "0000" |
frame3 |
|
|
| 11 - 8 | "0000" |
frame2 |
|
|
| 7 - 4 | "0000" |
frame1 |
|
|
| 3 - 0 | "0000" |
frame0 |
|
|
| cnt_ctl_cntacr0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220040 Address@s32k_cnt_ctl : 0x1a420040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rwpt |
|
|
| 4 | "0" |
rwvt |
|
|
| 3 | "0" |
rvoff |
|
|
| 2 | "0" |
rfrq |
|
|
| 1 | "0" |
rvct |
|
|
| 0 | "0" |
rpct |
|
|
| cnt_ctl_cntacr1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220044 Address@s32k_cnt_ctl : 0x1a420044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rwpt |
|
|
| 4 | "0" |
rwvt |
|
|
| 3 | "0" |
rvoff |
|
|
| 2 | "0" |
rfrq |
|
|
| 1 | "0" |
rvct |
|
|
| 0 | "0" |
rpct |
|
|
| cnt_ctl_cntacr2 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a220048 Address@s32k_cnt_ctl : 0x1a420048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rwpt |
|
|
| 4 | "0" |
rwvt |
|
|
| 3 | "0" |
rvoff |
|
|
| 2 | "0" |
rfrq |
|
|
| 1 | "0" |
rvct |
|
|
| 0 | "0" |
rpct |
|
|
| cnt_ctl_cntacr3 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt_ctl : 0x1a22004c Address@s32k_cnt_ctl : 0x1a42004c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
rwpt |
|
|
| 4 | "0" |
rwvt |
|
|
| 3 | "0" |
rvoff |
|
|
| 2 | "0" |
rfrq |
|
|
| 1 | "0" |
rvct |
|
|
| 0 | "0" |
rpct |
|
|
| cnt_ctl_counterid0 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fd0 Address@s32k_cnt_ctl : 0x1a420fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| cnt_ctl_counterid1 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fd4 Address@s32k_cnt_ctl : 0x1a420fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctl_counterid1 | |||
| cnt_ctl_counterid2 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fd8 Address@s32k_cnt_ctl : 0x1a420fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctl_counterid2 | |||
| cnt_ctl_counterid3 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fdc Address@s32k_cnt_ctl : 0x1a420fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_ctl_counterid3 | |||
| cnt_ctl_counterid4 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fe0 Address@s32k_cnt_ctl : 0x1a420fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cnt_ctl_counterid5 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fe4 Address@s32k_cnt_ctl : 0x1a420fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cnt_ctl_counterid6 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fe8 Address@s32k_cnt_ctl : 0x1a420fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| cnt_ctl_counterid7 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220fec Address@s32k_cnt_ctl : 0x1a420fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| cnt_ctl_counterid8 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220ff0 Address@s32k_cnt_ctl : 0x1a420ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cnt_ctl_counterid9 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220ff4 Address@s32k_cnt_ctl : 0x1a420ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cnt_ctl_counterid10 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220ff8 Address@s32k_cnt_ctl : 0x1a420ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cnt_ctl_counterid11 |
|
|||
| R |
Address@refclk_cnt_ctl : 0x1a220ffc Address@s32k_cnt_ctl : 0x1a420ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | cnt_cntpct0 |
| 1 | 4 | R | cnt_cntpct1 |
| 2 | 8 | R | cnt_cntvct0 |
| 3 | c | R | cnt_cntvct1 |
| 4 | 10 | R | cnt_cntfrq |
| 5 | 14 | R/W | cnt_cntel0acr |
| 6 | 18 | R | cnt_cntvoff0 |
| 7 | 1c | R | cnt_cntvoff1 |
| 8 | 20 | R/W | cnt_cntp_cval0 |
| 9 | 24 | R/W | cnt_cntp_cval1 |
| a | 28 | R/W | cnt_cntp_tval |
| b | 2c | R/W | cnt_cntp_ctl |
| c | 30 | R/W | cnt_cntv_cval0 |
| d | 34 | R/W | cnt_cntv_cval1 |
| e | 38 | R/W | cnt_cntv_tval |
| f | 3c | R/W | cnt_cntv_ctl |
| 10-3f3 | 40-fcc | - | reserved |
| 3f4 | fd0 | R | cnt_counterid0 |
| 3f5 | fd4 | R | cnt_counterid1 |
| 3f6 | fd8 | R | cnt_counterid2 |
| 3f7 | fdc | R | cnt_counterid3 |
| 3f8 | fe0 | R | cnt_counterid4 |
| 3f9 | fe4 | R | cnt_counterid5 |
| 3fa | fe8 | R | cnt_counterid6 |
| 3fb | fec | R | cnt_counterid7 |
| 3fc | ff0 | R | cnt_counterid8 |
| 3fd | ff4 | R | cnt_counterid9 |
| 3fe | ff8 | R | cnt_counterid10 |
| 3ff | ffc | R | cnt_counterid11 |
| cnt_cntpct0 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230000 Address@refclk_cnt1 : 0x1a240000 Address@refclk_cnt2 : 0x1a250000 Address@refclk_cnt3 : 0x1a260000 Address@s32k_cnt0 : 0x1a430000 Address@s32k_cnt1 : 0x1a440000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | count_value |
|
||
| cnt_cntpct1 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230004 Address@refclk_cnt1 : 0x1a240004 Address@refclk_cnt2 : 0x1a250004 Address@refclk_cnt3 : 0x1a260004 Address@s32k_cnt0 : 0x1a430004 Address@s32k_cnt1 : 0x1a440004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | count_value |
|
||
| cnt_cntvct0 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230008 Address@refclk_cnt1 : 0x1a240008 Address@refclk_cnt2 : 0x1a250008 Address@refclk_cnt3 : 0x1a260008 Address@s32k_cnt0 : 0x1a430008 Address@s32k_cnt1 : 0x1a440008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | count_value |
|
||
| cnt_cntvct1 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a23000c Address@refclk_cnt1 : 0x1a24000c Address@refclk_cnt2 : 0x1a25000c Address@refclk_cnt3 : 0x1a26000c Address@s32k_cnt0 : 0x1a43000c Address@s32k_cnt1 : 0x1a44000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | count_value |
|
||
| cnt_cntfrq |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230010 Address@refclk_cnt1 : 0x1a240010 Address@refclk_cnt2 : 0x1a250010 Address@refclk_cnt3 : 0x1a260010 Address@s32k_cnt0 : 0x1a430010 Address@s32k_cnt1 : 0x1a440010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | clock_frequency |
|
||
| cnt_cntel0acr |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230014 Address@refclk_cnt1 : 0x1a240014 Address@refclk_cnt2 : 0x1a250014 Address@refclk_cnt3 : 0x1a260014 Address@s32k_cnt0 : 0x1a430014 Address@s32k_cnt1 : 0x1a440014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cnt_cntel0acr | ||
| cnt_cntvoff0 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230018 Address@refclk_cnt1 : 0x1a240018 Address@refclk_cnt2 : 0x1a250018 Address@refclk_cnt3 : 0x1a260018 Address@s32k_cnt0 : 0x1a430018 Address@s32k_cnt1 : 0x1a440018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_cntvoff0 | |||
| cnt_cntvoff1 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a23001c Address@refclk_cnt1 : 0x1a24001c Address@refclk_cnt2 : 0x1a25001c Address@refclk_cnt3 : 0x1a26001c Address@s32k_cnt0 : 0x1a43001c Address@s32k_cnt1 : 0x1a44001c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_cntvoff1 | |||
| cnt_cntp_cval0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230020 Address@refclk_cnt1 : 0x1a240020 Address@refclk_cnt2 : 0x1a250020 Address@refclk_cnt3 : 0x1a260020 Address@s32k_cnt0 : 0x1a430020 Address@s32k_cnt1 : 0x1a440020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| cnt_cntp_cval1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230024 Address@refclk_cnt1 : 0x1a240024 Address@refclk_cnt2 : 0x1a250024 Address@refclk_cnt3 : 0x1a260024 Address@s32k_cnt0 : 0x1a430024 Address@s32k_cnt1 : 0x1a440024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| cnt_cntp_tval |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230028 Address@refclk_cnt1 : 0x1a240028 Address@refclk_cnt2 : 0x1a250028 Address@refclk_cnt3 : 0x1a260028 Address@s32k_cnt0 : 0x1a430028 Address@s32k_cnt1 : 0x1a440028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_value |
|
|
| cnt_cntp_ctl |
|
|||||||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a23002c Address@refclk_cnt1 : 0x1a24002c Address@refclk_cnt2 : 0x1a25002c Address@refclk_cnt3 : 0x1a26002c Address@s32k_cnt0 : 0x1a43002c Address@s32k_cnt1 : 0x1a44002c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||
| 2 | "0" |
istatus |
|
|||||
| 1 | "0" |
imask |
|
|||||
| 0 | "0" |
enable |
|
|||||
| cnt_cntv_cval0 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230030 Address@refclk_cnt1 : 0x1a240030 Address@refclk_cnt2 : 0x1a250030 Address@refclk_cnt3 : 0x1a260030 Address@s32k_cnt0 : 0x1a430030 Address@s32k_cnt1 : 0x1a440030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| cnt_cntv_cval1 |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230034 Address@refclk_cnt1 : 0x1a240034 Address@refclk_cnt2 : 0x1a250034 Address@refclk_cnt3 : 0x1a260034 Address@s32k_cnt0 : 0x1a430034 Address@s32k_cnt1 : 0x1a440034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| cnt_cntv_tval |
|
|||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a230038 Address@refclk_cnt1 : 0x1a240038 Address@refclk_cnt2 : 0x1a250038 Address@refclk_cnt3 : 0x1a260038 Address@s32k_cnt0 : 0x1a430038 Address@s32k_cnt1 : 0x1a440038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
timer_value |
|
|
| cnt_cntv_ctl |
|
|||||||
| R/W |
0x00000000 |
Address@refclk_cnt0 : 0x1a23003c Address@refclk_cnt1 : 0x1a24003c Address@refclk_cnt2 : 0x1a25003c Address@refclk_cnt3 : 0x1a26003c Address@s32k_cnt0 : 0x1a43003c Address@s32k_cnt1 : 0x1a44003c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||
| 2 | "0" |
istatus |
|
|||||
| 1 | "0" |
imask |
|
|||||
| 0 | "0" |
enable |
|
|||||
| cnt_counterid0 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fd0 Address@refclk_cnt1 : 0x1a240fd0 Address@refclk_cnt2 : 0x1a250fd0 Address@refclk_cnt3 : 0x1a260fd0 Address@s32k_cnt0 : 0x1a430fd0 Address@s32k_cnt1 : 0x1a440fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| cnt_counterid1 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fd4 Address@refclk_cnt1 : 0x1a240fd4 Address@refclk_cnt2 : 0x1a250fd4 Address@refclk_cnt3 : 0x1a260fd4 Address@s32k_cnt0 : 0x1a430fd4 Address@s32k_cnt1 : 0x1a440fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_counterid1 | |||
| cnt_counterid2 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fd8 Address@refclk_cnt1 : 0x1a240fd8 Address@refclk_cnt2 : 0x1a250fd8 Address@refclk_cnt3 : 0x1a260fd8 Address@s32k_cnt0 : 0x1a430fd8 Address@s32k_cnt1 : 0x1a440fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_counterid2 | |||
| cnt_counterid3 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fdc Address@refclk_cnt1 : 0x1a240fdc Address@refclk_cnt2 : 0x1a250fdc Address@refclk_cnt3 : 0x1a260fdc Address@s32k_cnt0 : 0x1a430fdc Address@s32k_cnt1 : 0x1a440fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cnt_counterid3 | |||
| cnt_counterid4 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fe0 Address@refclk_cnt1 : 0x1a240fe0 Address@refclk_cnt2 : 0x1a250fe0 Address@refclk_cnt3 : 0x1a260fe0 Address@s32k_cnt0 : 0x1a430fe0 Address@s32k_cnt1 : 0x1a440fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cnt_counterid5 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fe4 Address@refclk_cnt1 : 0x1a240fe4 Address@refclk_cnt2 : 0x1a250fe4 Address@refclk_cnt3 : 0x1a260fe4 Address@s32k_cnt0 : 0x1a430fe4 Address@s32k_cnt1 : 0x1a440fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cnt_counterid6 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fe8 Address@refclk_cnt1 : 0x1a240fe8 Address@refclk_cnt2 : 0x1a250fe8 Address@refclk_cnt3 : 0x1a260fe8 Address@s32k_cnt0 : 0x1a430fe8 Address@s32k_cnt1 : 0x1a440fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| cnt_counterid7 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230fec Address@refclk_cnt1 : 0x1a240fec Address@refclk_cnt2 : 0x1a250fec Address@refclk_cnt3 : 0x1a260fec Address@s32k_cnt0 : 0x1a430fec Address@s32k_cnt1 : 0x1a440fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| cnt_counterid8 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230ff0 Address@refclk_cnt1 : 0x1a240ff0 Address@refclk_cnt2 : 0x1a250ff0 Address@refclk_cnt3 : 0x1a260ff0 Address@s32k_cnt0 : 0x1a430ff0 Address@s32k_cnt1 : 0x1a440ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cnt_counterid9 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230ff4 Address@refclk_cnt1 : 0x1a240ff4 Address@refclk_cnt2 : 0x1a250ff4 Address@refclk_cnt3 : 0x1a260ff4 Address@s32k_cnt0 : 0x1a430ff4 Address@s32k_cnt1 : 0x1a440ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cnt_counterid10 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230ff8 Address@refclk_cnt1 : 0x1a240ff8 Address@refclk_cnt2 : 0x1a250ff8 Address@refclk_cnt3 : 0x1a260ff8 Address@s32k_cnt0 : 0x1a430ff8 Address@s32k_cnt1 : 0x1a440ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cnt_counterid11 |
|
|||
| R |
Address@refclk_cnt0 : 0x1a230ffc Address@refclk_cnt1 : 0x1a240ffc Address@refclk_cnt2 : 0x1a250ffc Address@refclk_cnt3 : 0x1a260ffc Address@s32k_cnt0 : 0x1a430ffc Address@s32k_cnt1 : 0x1a440ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | wdg_ctrl_wcs |
| 1 | 4 | - | reserved |
| 2 | 8 | R/W | wdg_ctrl_wor0 |
| 3 | c | R/W | wdg_ctrl_wor1 |
| 4 | 10 | R/W | wdg_ctrl_wcv0 |
| 5 | 14 | R/W | wdg_ctrl_wcv1 |
| 6-3f2 | 18-fc8 | - | reserved |
| 3f3 | fcc | R | wdg_ctrl_w_iidr |
| 3f4 | fd0 | R | wdg_ctrl_id0 |
| 3f5 | fd4 | R | wdg_ctrl_id1 |
| 3f6 | fd8 | R | wdg_ctrl_id2 |
| 3f7 | fdc | R | wdg_ctrl_id3 |
| 3f8 | fe0 | R | wdg_ctrl_id4 |
| 3f9 | fe4 | R | wdg_ctrl_id5 |
| 3fa | fe8 | R | wdg_ctrl_id6 |
| 3fb | fec | R | wdg_ctrl_id7 |
| 3fc | ff0 | R | wdg_ctrl_id8 |
| 3fd | ff4 | R | wdg_ctrl_id9 |
| 3fe | ff8 | R | wdg_ctrl_id10 |
| 3ff | ffc | R | wdg_ctrl_id11 |
| wdg_ctrl_wcs |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_ctrl : 0x1a300000 Address@app_secure_wdog_ctrl : 0x1a320000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 - 1 | "00" |
status |
|
|
| 0 | "0" |
enable |
|
|
| wdg_ctrl_wor0 |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_ctrl : 0x1a300008 Address@app_secure_wdog_ctrl : 0x1a320008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
offset_value |
|
|
| wdg_ctrl_wor1 |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_ctrl : 0x1a30000c Address@app_secure_wdog_ctrl : 0x1a32000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
offset_value |
|
|
| wdg_ctrl_wcv0 |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_ctrl : 0x1a300010 Address@app_secure_wdog_ctrl : 0x1a320010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| wdg_ctrl_wcv1 |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_ctrl : 0x1a300014 Address@app_secure_wdog_ctrl : 0x1a320014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
compare_value |
|
|
| wdg_ctrl_w_iidr |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fcc Address@app_secure_wdog_ctrl : 0x1a320fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | productid |
|
||
| 19 - 16 | arch_version |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| wdg_ctrl_id0 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fd0 Address@app_secure_wdog_ctrl : 0x1a320fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| wdg_ctrl_id1 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fd4 Address@app_secure_wdog_ctrl : 0x1a320fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_ctrl_id1 | |||
| wdg_ctrl_id2 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fd8 Address@app_secure_wdog_ctrl : 0x1a320fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_ctrl_id2 | |||
| wdg_ctrl_id3 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fdc Address@app_secure_wdog_ctrl : 0x1a320fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_ctrl_id3 | |||
| wdg_ctrl_id4 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fe0 Address@app_secure_wdog_ctrl : 0x1a320fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| wdg_ctrl_id5 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fe4 Address@app_secure_wdog_ctrl : 0x1a320fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| wdg_ctrl_id6 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fe8 Address@app_secure_wdog_ctrl : 0x1a320fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| wdg_ctrl_id7 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300fec Address@app_secure_wdog_ctrl : 0x1a320fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| wdg_ctrl_id8 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300ff0 Address@app_secure_wdog_ctrl : 0x1a320ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| wdg_ctrl_id9 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300ff4 Address@app_secure_wdog_ctrl : 0x1a320ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| wdg_ctrl_id10 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300ff8 Address@app_secure_wdog_ctrl : 0x1a320ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| wdg_ctrl_id11 |
|
|||
| R |
Address@app_ns_wdog_ctrl : 0x1a300ffc Address@app_secure_wdog_ctrl : 0x1a320ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | wdg_refresh_wrr |
| 1-3f2 | 4-fc8 | - | reserved |
| 3f3 | fcc | R | wdg_refresh_w_iidr |
| 3f4 | fd0 | R | wdg_refresh_id0 |
| 3f5 | fd4 | R | wdg_refresh_id1 |
| 3f6 | fd8 | R | wdg_refresh_id2 |
| 3f7 | fdc | R | wdg_refresh_id3 |
| 3f8 | fe0 | R | wdg_refresh_id4 |
| 3f9 | fe4 | R | wdg_refresh_id5 |
| 3fa | fe8 | R | wdg_refresh_id6 |
| 3fb | fec | R | wdg_refresh_id7 |
| 3fc | ff0 | R | wdg_refresh_id8 |
| 3fd | ff4 | R | wdg_refresh_id9 |
| 3fe | ff8 | R | wdg_refresh_id10 |
| 3ff | ffc | R | wdg_refresh_id11 |
| wdg_refresh_wrr |
|
|||
| R/W |
0x00000000 |
Address@app_ns_wdog_refresh : 0x1a310000 Address@app_secure_wdog_refresh : 0x1a330000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
reg |
|
|
| wdg_refresh_w_iidr |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fcc Address@app_secure_wdog_refresh : 0x1a330fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | productid |
|
||
| 19 - 16 | arch_version |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| wdg_refresh_id0 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fd0 Address@app_secure_wdog_refresh : 0x1a330fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| wdg_refresh_id1 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fd4 Address@app_secure_wdog_refresh : 0x1a330fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_refresh_id1 | |||
| wdg_refresh_id2 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fd8 Address@app_secure_wdog_refresh : 0x1a330fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_refresh_id2 | |||
| wdg_refresh_id3 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fdc Address@app_secure_wdog_refresh : 0x1a330fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | wdg_refresh_id3 | |||
| wdg_refresh_id4 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fe0 Address@app_secure_wdog_refresh : 0x1a330fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| wdg_refresh_id5 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fe4 Address@app_secure_wdog_refresh : 0x1a330fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| wdg_refresh_id6 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fe8 Address@app_secure_wdog_refresh : 0x1a330fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| wdg_refresh_id7 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310fec Address@app_secure_wdog_refresh : 0x1a330fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| wdg_refresh_id8 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310ff0 Address@app_secure_wdog_refresh : 0x1a330ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| wdg_refresh_id9 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310ff4 Address@app_secure_wdog_refresh : 0x1a330ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| wdg_refresh_id10 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310ff8 Address@app_secure_wdog_refresh : 0x1a330ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| wdg_refresh_id11 |
|
|||
| R |
Address@app_ns_wdog_refresh : 0x1a310ffc Address@app_secure_wdog_refresh : 0x1a330ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | interrupt_router_int_rtr_ctrl |
| 1-3 | 4-c | - | reserved |
| 4 | 10 | R/W | interrupt_router_ld_ctrl |
| 5-3f | 14-fc | - | reserved |
| 40 | 100 | R | interrupt_router_shd_int_info |
| 41 | 104 | R/W | interrupt_router_shd_int_cfg |
| 42 | 108 | R/W | interrupt_router_shd_int_lctrl |
| 43 | 10c | R/W | interrupt_router_shd_int_sel |
| 44-3a3 | 110-e8c | - | reserved |
| 3a4 | e90 | R/W | interrupt_router_int_rtr_tmp_st |
| 3a5-3e7 | e94-f9c | - | reserved |
| 3e8 | fa0 | R/W | interrupt_router_int_rtr_cap |
| 3e9-3eb | fa4-fac | - | reserved |
| 3ec | fb0 | R/W | interrupt_router_int_rtr_cfg |
| 3ed-3f3 | fb4-fcc | - | reserved |
| 3f4 | fd0 | R | interrupt_router_pid4 |
| 3f5 | fd4 | R | interrupt_router_pid5 |
| 3f6 | fd8 | R | interrupt_router_pid6 |
| 3f7 | fdc | R | interrupt_router_pid7 |
| 3f8 | fe0 | R | interrupt_router_pid0 |
| 3f9 | fe4 | R | interrupt_router_pid1 |
| 3fa | fe8 | R | interrupt_router_pid2 |
| 3fb | fec | R | interrupt_router_pid3 |
| 3fc | ff0 | R | interrupt_router_cid0 |
| 3fd | ff4 | R | interrupt_router_cid1 |
| 3fe | ff8 | R | interrupt_router_cid2 |
| 3ff | ffc | R | interrupt_router_cid3 |
| interrupt_router_int_rtr_ctrl |
|
|||||||
| R/W |
0x00000000 |
Address : 0x1a500000 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
err |
|
|||||
| interrupt_router_ld_ctrl |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x1a500010 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
ldi_st |
|
|||||||||
| 1 - 0 | "00" |
lock |
|
|||||||||
| interrupt_router_shd_int_info |
|
||||||||
| R |
Address : 0x1a500100 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | - |
reserved | |||||||
| 15 - 0 | ici_dst |
|
|||||||
| interrupt_router_shd_int_cfg |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a500104 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||
| 15 - 0 | 0x0 |
ici_en |
|
||||||
| interrupt_router_shd_int_lctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a500108 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
lock |
|
||||||
| 30 - 0 | 0 |
- |
reserved | ||||||
| interrupt_router_shd_int_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x1a50010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
int_sel |
|
|
| interrupt_router_int_rtr_tmp_st |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a500e90 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
tmp_st_vld |
|
||||||
| 30 | "0" |
tmp_st_overflw |
|
||||||
| 29 - 13 | 0 |
- |
reserved | ||||||
| 12 - 11 | "00" |
tmp_trans_addr |
|
||||||
| 10 - 0 | 0 |
- |
reserved | ||||||
| interrupt_router_int_rtr_cap |
|
|||
| R/W |
0x00000000 |
Address : 0x1a500fa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
lde_lvl |
|
|
| interrupt_router_int_rtr_cfg |
|
||||||||
| R/W |
0x00000000 |
Address : 0x1a500fb0 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | ||||||
| 19 - 16 | "0000" |
num_ici |
|
||||||
| 15 - 0 | 0x0 |
num_shd_int |
|
||||||
| interrupt_router_pid4 |
|
|||
| R |
Address : 0x1a500fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| interrupt_router_pid5 |
|
|||
| R |
Address : 0x1a500fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | interrupt_router_pid5 | |||
| interrupt_router_pid6 |
|
|||
| R |
Address : 0x1a500fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | interrupt_router_pid6 | |||
| interrupt_router_pid7 |
|
|||
| R |
Address : 0x1a500fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | interrupt_router_pid7 | |||
| interrupt_router_pid0 |
|
|||
| R |
Address : 0x1a500fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| interrupt_router_pid1 |
|
|||
| R |
Address : 0x1a500fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| interrupt_router_pid2 |
|
|||
| R |
Address : 0x1a500fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| interrupt_router_pid3 |
|
|||
| R |
Address : 0x1a500fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| interrupt_router_cid0 |
|
|||
| R |
Address : 0x1a500ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| interrupt_router_cid1 |
|
|||
| R |
Address : 0x1a500ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| interrupt_router_cid2 |
|
|||
| R |
Address : 0x1a500ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| interrupt_router_cid3 |
|
|||
| R |
Address : 0x1a500ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | uart_pl011_uartdr |
| 1 | 4 | R/W | uart_pl011_uartrsr |
| 2-5 | 8-14 | - | reserved |
| 6 | 18 | R | uart_pl011_uartfr |
| 7 | 1c | - | reserved |
| 8 | 20 | R/W | uart_pl011_uartilpr |
| 9 | 24 | R/W | uart_pl011_uartibrd |
| a | 28 | R/W | uart_pl011_uartfbrd |
| b | 2c | R/W | uart_pl011_uartlcr_h |
| c | 30 | R/W | uart_pl011_uartcr |
| d | 34 | R/W | uart_pl011_uartifls |
| e | 38 | R/W | uart_pl011_uartimsc |
| f | 3c | R | uart_pl011_uartris |
| 10 | 40 | R | uart_pl011_uartmis |
| 11 | 44 | W | uart_pl011_uarticr |
| 12 | 48 | R/W | uart_pl011_uartdmacr |
| 13-3f7 | 4c-fdc | - | reserved |
| 3f8 | fe0 | R | uart_pl011_uartperiphid0 |
| 3f9 | fe4 | R | uart_pl011_uartperiphid1 |
| 3fa | fe8 | R | uart_pl011_uartperiphid2 |
| 3fb | fec | R | uart_pl011_uartperiphid3 |
| 3fc | ff0 | R | uart_pl011_uartpcellid0 |
| 3fd | ff4 | R | uart_pl011_uartpcellid1 |
| 3fe | ff8 | R | uart_pl011_uartpcellid2 |
| 3ff | ffc | R | uart_pl011_uartpcellid3 |
| uart_pl011_uartdr |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510000 Address@cor_uart1 : 0x1a520000 Address@secenc_uart : 0x50090000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 | "0" |
oe |
|
|
| 10 | "0" |
be |
|
|
| 9 | "0" |
pe |
|
|
| 8 | "0" |
fe |
|
|
| 7 - 0 | "00000000" |
data |
|
|
| uart_pl011_uartrsr |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510004 Address@cor_uart1 : 0x1a520004 Address@secenc_uart : 0x50090004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
oe |
|
|
| 2 | "0" |
be |
|
|
| 1 | "0" |
pe |
|
|
| 0 | "0" |
fe |
|
|
| uart_pl011_uartfr |
|
|||
| R |
Address@cor_uart0 : 0x1a510018 Address@cor_uart1 : 0x1a520018 Address@secenc_uart : 0x50090018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | ri |
|
||
| 7 | txfe |
|
||
| 6 | rxff |
|
||
| 5 | txff |
|
||
| 4 | rxfe |
|
||
| 3 | busy |
|
||
| 2 | dcd |
|
||
| 1 | dsr |
|
||
| 0 | cts |
|
||
| uart_pl011_uartilpr |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510020 Address@cor_uart1 : 0x1a520020 Address@secenc_uart : 0x50090020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
ilpdvsr |
|
|
| uart_pl011_uartibrd |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510024 Address@cor_uart1 : 0x1a520024 Address@secenc_uart : 0x50090024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
baud_divint |
|
|
| uart_pl011_uartfbrd |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510028 Address@cor_uart1 : 0x1a520028 Address@secenc_uart : 0x50090028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
baud_divfrac |
|
|
| uart_pl011_uartlcr_h |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a51002c Address@cor_uart1 : 0x1a52002c Address@secenc_uart : 0x5009002c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
sps |
|
|
| 6 - 5 | "00" |
wlen |
|
|
| 4 | "0" |
fen |
|
|
| 3 | "0" |
stp2 |
|
|
| 2 | "0" |
eps |
|
|
| 1 | "0" |
pen |
|
|
| 0 | "0" |
brk |
|
|
| uart_pl011_uartcr |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510030 Address@cor_uart1 : 0x1a520030 Address@secenc_uart : 0x50090030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
ctsen |
|
|
| 14 | "0" |
rtsen |
|
|
| 13 | "0" |
out2 |
|
|
| 12 | "0" |
out1 |
|
|
| 11 | "0" |
rts |
|
|
| 10 | "0" |
dtr |
|
|
| 9 | "0" |
rxe |
|
|
| 8 | "0" |
txe |
|
|
| 7 | "0" |
lbe |
|
|
| 6 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sirlp |
|
|
| 1 | "0" |
siren |
|
|
| 0 | "0" |
uarten |
|
|
| uart_pl011_uartifls |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510034 Address@cor_uart1 : 0x1a520034 Address@secenc_uart : 0x50090034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 3 | "000" |
rxiflsel |
|
|
| 2 - 0 | "000" |
txiflsel |
|
|
| uart_pl011_uartimsc |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510038 Address@cor_uart1 : 0x1a520038 Address@secenc_uart : 0x50090038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
oeim |
|
|
| 9 | "0" |
beim |
|
|
| 8 | "0" |
peim |
|
|
| 7 | "0" |
feim |
|
|
| 6 | "0" |
rtim |
|
|
| 5 | "0" |
txim |
|
|
| 4 | "0" |
rxim |
|
|
| 3 | "0" |
dsrmim |
|
|
| 2 | "0" |
dcdmim |
|
|
| 1 | "0" |
ctsmim |
|
|
| 0 | "0" |
rimim |
|
|
| uart_pl011_uartris |
|
|||
| R |
Address@cor_uart0 : 0x1a51003c Address@cor_uart1 : 0x1a52003c Address@secenc_uart : 0x5009003c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 11 | - |
reserved | ||
| 10 | oeris |
|
||
| 9 | beris |
|
||
| 8 | peris |
|
||
| 7 | feris |
|
||
| 6 | rtris |
|
||
| 5 | txris |
|
||
| 4 | rxris |
|
||
| 3 | dsrrmis |
|
||
| 2 | dcdrmis |
|
||
| 1 | ctsrmis |
|
||
| 0 | rirmis |
|
||
| uart_pl011_uartmis |
|
|||
| R |
Address@cor_uart0 : 0x1a510040 Address@cor_uart1 : 0x1a520040 Address@secenc_uart : 0x50090040 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 11 | - |
reserved | ||
| 10 | oemis |
|
||
| 9 | bemis |
|
||
| 8 | pemis |
|
||
| 7 | femis |
|
||
| 6 | rtmis |
|
||
| 5 | txmis |
|
||
| 4 | rxmis |
|
||
| 3 | dsrmmis |
|
||
| 2 | dcdmmis |
|
||
| 1 | ctsmmis |
|
||
| 0 | rimmis |
|
||
| uart_pl011_uarticr |
|
|||
| W |
0x00000000 |
Address@cor_uart0 : 0x1a510044 Address@cor_uart1 : 0x1a520044 Address@secenc_uart : 0x50090044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
oeic |
|
|
| 9 | "0" |
beic |
|
|
| 8 | "0" |
peic |
|
|
| 7 | "0" |
feic |
|
|
| 6 | "0" |
rtic |
|
|
| 5 | "0" |
txic |
|
|
| 4 | "0" |
rxic |
|
|
| 3 | "0" |
dsrmic |
|
|
| 2 | "0" |
dcdmic |
|
|
| 1 | "0" |
ctsmic |
|
|
| 0 | "0" |
rimic |
|
|
| uart_pl011_uartdmacr |
|
|||
| R/W |
0x00000000 |
Address@cor_uart0 : 0x1a510048 Address@cor_uart1 : 0x1a520048 Address@secenc_uart : 0x50090048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
dmaonerr |
|
|
| 1 | "0" |
txdmae |
|
|
| 0 | "0" |
rxdmae |
|
|
| uart_pl011_uartperiphid0 |
|
|||
| R |
Address@cor_uart0 : 0x1a510fe0 Address@cor_uart1 : 0x1a520fe0 Address@secenc_uart : 0x50090fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | partnumber0 |
|
||
| uart_pl011_uartperiphid1 |
|
|||
| R |
Address@cor_uart0 : 0x1a510fe4 Address@cor_uart1 : 0x1a520fe4 Address@secenc_uart : 0x50090fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | designer0 |
|
||
| 3 - 0 | partnumber1 |
|
||
| uart_pl011_uartperiphid2 |
|
|||
| R |
Address@cor_uart0 : 0x1a510fe8 Address@cor_uart1 : 0x1a520fe8 Address@secenc_uart : 0x50090fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 - 0 | designer1 |
|
||
| uart_pl011_uartperiphid3 |
|
|||
| R |
Address@cor_uart0 : 0x1a510fec Address@cor_uart1 : 0x1a520fec Address@secenc_uart : 0x50090fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | configuration |
|
||
| uart_pl011_uartpcellid0 |
|
|||
| R |
Address@cor_uart0 : 0x1a510ff0 Address@cor_uart1 : 0x1a520ff0 Address@secenc_uart : 0x50090ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | uartpcellid0 |
|
||
| uart_pl011_uartpcellid1 |
|
|||
| R |
Address@cor_uart0 : 0x1a510ff4 Address@cor_uart1 : 0x1a520ff4 Address@secenc_uart : 0x50090ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | uartpcellid1 |
|
||
| uart_pl011_uartpcellid2 |
|
|||
| R |
Address@cor_uart0 : 0x1a510ff8 Address@cor_uart1 : 0x1a520ff8 Address@secenc_uart : 0x50090ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | uartpcellid2 |
|
||
| uart_pl011_uartpcellid3 |
|
|||
| R |
Address@cor_uart0 : 0x1a510ffc Address@cor_uart1 : 0x1a520ffc Address@secenc_uart : 0x50090ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | uartpcellid3 |
|
||
| fw_ctrl_fw_ctrl |
|
|||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800000 Address@secenc_fw_ctrl : 0x50200000 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||
| 1 | "0" |
raz |
|
|||||
| 0 | "0" |
err |
|
|||||
| fw_ctrl_fw_st |
|
|||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800004 Address@secenc_fw_ctrl : 0x50200004 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||||||
| 1 | raz |
|
||||||
| 0 | err |
|
||||||
| fw_ctrl_fw_sr_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a80000c Address@secenc_fw_ctrl : 0x5020000c |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sr_rdy |
|
||||||
| 30 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
sr_pwr |
|
||||||
| fw_ctrl_ld_ctrl |
|
|||||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800010 Address@secenc_fw_ctrl : 0x50200010 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 | ldi_st |
|
||||||||||
| 1 - 0 | lock |
|
||||||||||
| fw_ctrl_pe_ctrl |
|
|||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800100 Address@secenc_fw_ctrl : 0x50200100 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
en |
|
|||||||||
| 30 - 6 | 0 |
- |
reserved | |||||||||
| 5 | "0" |
bypass_msk |
|
|||||||||
| 4 | "0" |
fe_pwr |
|
|||||||||
| 3 - 2 | "00" |
flt_cfg |
|
|||||||||
| 1 | "0" |
raz |
|
|||||||||
| 0 | "0" |
err |
|
|||||||||
| fw_ctrl_pe_st |
|
|||||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800104 Address@secenc_fw_ctrl : 0x50200104 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | en |
|
||||||||||
| 30 - 6 | - |
reserved | ||||||||||
| 5 | bypass_msk |
|
||||||||||
| 4 | fe_pwr |
|
||||||||||
| 3 - 2 | flt_cfg |
|
||||||||||
| 1 | raz |
|
||||||||||
| 0 | err |
|
||||||||||
| fw_ctrl_pe_bps |
|
||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800108 Address@secenc_fw_ctrl : 0x50200108 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
bypass_vld |
|
||||||||||
| 30 - 2 | 0 |
- |
reserved | ||||||||||
| 1 | "0" |
bypass_st |
|
||||||||||
| 0 | "0" |
bypass_if_st |
|
||||||||||
| fw_ctrl_rwe_ctrl |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a80010c Address@secenc_fw_ctrl : 0x5020010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
rgn_indx |
|
|
| fw_ctrl_rgn_ctrl0 |
|
|||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800110 Address@secenc_fw_ctrl : 0x50200110 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
en |
|
|||||
| fw_ctrl_rgn_ctrl1 |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800114 Address@secenc_fw_ctrl : 0x50200114 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | ||||||
| 4 | "0" |
mpe3_en |
|
||||||
| 3 | "0" |
mpe2_en |
|
||||||
| 2 | "0" |
mpe1_en |
|
||||||
| 1 | "0" |
mpe0_en |
|
||||||
| 0 | 0 |
- |
reserved | ||||||
| fw_ctrl_rgn_lctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800118 Address@secenc_fw_ctrl : 0x50200118 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
lock |
|
||||||
| fw_ctrl_rgn_st |
|
||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a80011c Address@secenc_fw_ctrl : 0x5020011c |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | - |
reserved | |||||||
| 4 | mpe3_en |
|
|||||||
| 3 | mpe2_en |
|
|||||||
| 2 | mpe1_en |
|
|||||||
| 1 | en |
|
|||||||
| 0 | - |
reserved | |||||||
| fw_ctrl_rgn_cfg0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800120 Address@secenc_fw_ctrl : 0x50200120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0x0 |
base_addr |
|
|
| 4 - 0 | 0 |
- |
reserved | |
| fw_ctrl_rgn_cfg1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800124 Address@secenc_fw_ctrl : 0x50200124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
base_addr |
|
|
| fw_ctrl_rgn_size |
|
|||||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800128 Address@secenc_fw_ctrl : 0x50200128 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |||||||||||||
| 8 | "0" |
mulnpo2 |
|
|||||||||||||
| 7 - 0 | "00000000" |
size |
|
|||||||||||||
| fw_ctrl_rgn_tcfg0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800130 Address@secenc_fw_ctrl : 0x50200130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0x0 |
output_addr |
|
|
| 4 - 0 | 0 |
- |
reserved | |
| fw_ctrl_rgn_tcfg1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800134 Address@secenc_fw_ctrl : 0x50200134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
upper_addr |
|
|
| fw_ctrl_rgn_tcfg2 |
|
||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800138 Address@secenc_fw_ctrl : 0x50200138 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | ||||||||||
| 17 | "0" |
addr_trans_en |
|
||||||||||
| 16 | "0" |
ma_trans_en |
|
||||||||||
| 15 - 14 | "00" |
instr |
|
||||||||||
| 13 - 12 | "00" |
priv |
|
||||||||||
| 11 - 4 | "00000000" |
ma |
|
||||||||||
| 3 - 2 | "00" |
sh |
|
||||||||||
| 1 - 0 | "00" |
ns |
|
||||||||||
| fw_ctrl_rgn_mid0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800140 Address@secenc_fw_ctrl : 0x50200140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
mst_id |
|
|
| fw_ctrl_rgn_mpl0 |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800144 Address@secenc_fw_ctrl : 0x50200144 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||
| 12 | "0" |
any_mst |
|
||||||
| 11 | "0" |
spx |
|
||||||
| 10 | "0" |
spw |
|
||||||
| 9 | "0" |
spr |
|
||||||
| 8 | "0" |
sux |
|
||||||
| 7 | "0" |
suw |
|
||||||
| 6 | "0" |
sur |
|
||||||
| 5 | "0" |
nspx |
|
||||||
| 4 | "0" |
nspw |
|
||||||
| 3 | "0" |
nspr |
|
||||||
| 2 | "0" |
nsux |
|
||||||
| 1 | "0" |
nsuw |
|
||||||
| 0 | "0" |
nsur |
|
||||||
| fw_ctrl_rgn_mid1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800148 Address@secenc_fw_ctrl : 0x50200148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mid1 | ||
| fw_ctrl_rgn_mpl1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a80014c Address@secenc_fw_ctrl : 0x5020014c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mpl1 | ||
| fw_ctrl_rgn_mid2 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800150 Address@secenc_fw_ctrl : 0x50200150 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mid2 | ||
| fw_ctrl_rgn_mpl2 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800154 Address@secenc_fw_ctrl : 0x50200154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mpl2 | ||
| fw_ctrl_rgn_mid3 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800158 Address@secenc_fw_ctrl : 0x50200158 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mid3 | ||
| fw_ctrl_rgn_mpl3 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a80015c Address@secenc_fw_ctrl : 0x5020015c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_rgn_mpl3 | ||
| fw_ctrl_fe_tal |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800180 Address@secenc_fw_ctrl : 0x50200180 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fault_addr_lwr |
|
||
| fw_ctrl_fe_tau |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800184 Address@secenc_fw_ctrl : 0x50200184 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fault_addr_upr |
|
||
| fw_ctrl_fe_tp |
|
||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800188 Address@secenc_fw_ctrl : 0x50200188 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | - |
reserved | |||||||
| 21 | w |
|
|||||||
| 20 - 19 | - |
reserved | |||||||
| 18 | instr |
|
|||||||
| 17 | priv |
|
|||||||
| 16 | ns |
|
|||||||
| 15 - 0 | - |
reserved | |||||||
| fw_ctrl_fe_mid |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a80018c Address@secenc_fw_ctrl : 0x5020018c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mst_id |
|
||
| fw_ctrl_fe_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800190 Address@secenc_fw_ctrl : 0x50200190 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
last_fe |
|
||||||
| 30 | "0" |
fe_vld |
|
||||||
| 29 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
flt_type |
|
||||||
| 2 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
ack |
|
||||||
| fw_ctrl_me_ctrl |
|
|||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800200 Address@secenc_fw_ctrl : 0x50200200 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
en |
|
|||||
| 30 - 5 | 0 |
- |
reserved | |||||
| 4 | "0" |
edr_pwr |
|
|||||
| 3 - 2 | 0 |
- |
reserved | |||||
| 1 | "0" |
rdum |
|
|||||
| 0 | 0 |
- |
reserved | |||||
| fw_ctrl_me_st |
|
||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800204 Address@secenc_fw_ctrl : 0x50200204 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 | en |
|
|||||||
| 30 - 5 | - |
reserved | |||||||
| 4 | edr_pwr |
|
|||||||
| 3 - 2 | - |
reserved | |||||||
| 1 | rdum |
|
|||||||
| 0 | - |
reserved | |||||||
| fw_ctrl_edr_tal |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800260 Address@secenc_fw_ctrl : 0x50200260 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | error_addr_lwr |
|
||
| fw_ctrl_edr_tau |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800264 Address@secenc_fw_ctrl : 0x50200264 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | error_addr_upr |
|
||
| fw_ctrl_edr_tp |
|
|||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800268 Address@secenc_fw_ctrl : 0x50200268 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||||||
| 21 | w |
|
||||||
| 20 - 19 | - |
reserved | ||||||
| 18 | instr |
|
||||||
| 17 | priv |
|
||||||
| 16 | ns |
|
||||||
| 15 - 0 | - |
reserved | ||||||
| fw_ctrl_edr_mid |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a80026c Address@secenc_fw_ctrl : 0x5020026c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mst_id |
|
||
| fw_ctrl_edr_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800270 Address@secenc_fw_ctrl : 0x50200270 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
last_edr |
|
||||||
| 30 | "0" |
edr_vld |
|
||||||
| 29 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
ack |
|
||||||
| fw_ctrl_fc0_int_st |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d00 Address@secenc_fw_ctrl : 0x50200d00 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | ||||||
| 4 | "0" |
ed_ovrflw_st |
|
||||||
| 3 | "0" |
ed_st |
|
||||||
| 2 | "0" |
flt_ovrflw_st |
|
||||||
| 1 | "0" |
prog_err_st |
|
||||||
| 0 | "0" |
acc_err_st |
|
||||||
| fw_ctrl_fc1_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d04 Address@secenc_fw_ctrl : 0x50200d04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc1_int_st | ||
| fw_ctrl_fc2_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d08 Address@secenc_fw_ctrl : 0x50200d08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc2_int_st | ||
| fw_ctrl_fc3_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d0c Address@secenc_fw_ctrl : 0x50200d0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc3_int_st | ||
| fw_ctrl_fc4_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d10 Address@secenc_fw_ctrl : 0x50200d10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc4_int_st | ||
| fw_ctrl_fc5_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d14 Address@secenc_fw_ctrl : 0x50200d14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc5_int_st | ||
| fw_ctrl_fc6_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d18 Address@secenc_fw_ctrl : 0x50200d18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc6_int_st | ||
| fw_ctrl_fc7_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d1c Address@secenc_fw_ctrl : 0x50200d1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc7_int_st | ||
| fw_ctrl_fc8_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d20 Address@secenc_fw_ctrl : 0x50200d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc8_int_st | ||
| fw_ctrl_fc9_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d24 Address@secenc_fw_ctrl : 0x50200d24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc9_int_st | ||
| fw_ctrl_fc10_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d28 Address@secenc_fw_ctrl : 0x50200d28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc10_int_st | ||
| fw_ctrl_fc11_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d2c Address@secenc_fw_ctrl : 0x50200d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc11_int_st | ||
| fw_ctrl_fc12_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d30 Address@secenc_fw_ctrl : 0x50200d30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc12_int_st | ||
| fw_ctrl_fc13_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d34 Address@secenc_fw_ctrl : 0x50200d34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc13_int_st | ||
| fw_ctrl_fc14_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d38 Address@secenc_fw_ctrl : 0x50200d38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc14_int_st | ||
| fw_ctrl_fc15_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d3c Address@secenc_fw_ctrl : 0x50200d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc15_int_st | ||
| fw_ctrl_fc16_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d40 Address@secenc_fw_ctrl : 0x50200d40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc16_int_st | ||
| fw_ctrl_fc17_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d44 Address@secenc_fw_ctrl : 0x50200d44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc17_int_st | ||
| fw_ctrl_fc18_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d48 Address@secenc_fw_ctrl : 0x50200d48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc18_int_st | ||
| fw_ctrl_fc19_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d4c Address@secenc_fw_ctrl : 0x50200d4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc19_int_st | ||
| fw_ctrl_fc20_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d50 Address@secenc_fw_ctrl : 0x50200d50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc20_int_st | ||
| fw_ctrl_fc21_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d54 Address@secenc_fw_ctrl : 0x50200d54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc21_int_st | ||
| fw_ctrl_fc22_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d58 Address@secenc_fw_ctrl : 0x50200d58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc22_int_st | ||
| fw_ctrl_fc23_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d5c Address@secenc_fw_ctrl : 0x50200d5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc23_int_st | ||
| fw_ctrl_fc24_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d60 Address@secenc_fw_ctrl : 0x50200d60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc24_int_st | ||
| fw_ctrl_fc25_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d64 Address@secenc_fw_ctrl : 0x50200d64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc25_int_st | ||
| fw_ctrl_fc26_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d68 Address@secenc_fw_ctrl : 0x50200d68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc26_int_st | ||
| fw_ctrl_fc27_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d6c Address@secenc_fw_ctrl : 0x50200d6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc27_int_st | ||
| fw_ctrl_fc28_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d70 Address@secenc_fw_ctrl : 0x50200d70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc28_int_st | ||
| fw_ctrl_fc29_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d74 Address@secenc_fw_ctrl : 0x50200d74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc29_int_st | ||
| fw_ctrl_fc30_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d78 Address@secenc_fw_ctrl : 0x50200d78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc30_int_st | ||
| fw_ctrl_fc31_int_st |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800d7c Address@secenc_fw_ctrl : 0x50200d7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc31_int_st | ||
| fw_ctrl_fw_int_st |
|
||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800d90 Address@secenc_fw_ctrl : 0x50200d90 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | fc_int_st |
|
|||||||
| fw_ctrl_fc0_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e00 Address@secenc_fw_ctrl : 0x50200e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
ed_ovrflw_msk |
|
|
| 3 | "0" |
ed_msk |
|
|
| 2 | "0" |
flt_ovrflw_msk |
|
|
| 1 | "0" |
prog_err_msk |
|
|
| 0 | "0" |
acc_err_msk |
|
|
| fw_ctrl_fc1_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e04 Address@secenc_fw_ctrl : 0x50200e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc1_int_msk | ||
| fw_ctrl_fc2_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e08 Address@secenc_fw_ctrl : 0x50200e08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc2_int_msk | ||
| fw_ctrl_fc3_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e0c Address@secenc_fw_ctrl : 0x50200e0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc3_int_msk | ||
| fw_ctrl_fc4_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e10 Address@secenc_fw_ctrl : 0x50200e10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc4_int_msk | ||
| fw_ctrl_fc5_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e14 Address@secenc_fw_ctrl : 0x50200e14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc5_int_msk | ||
| fw_ctrl_fc6_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e18 Address@secenc_fw_ctrl : 0x50200e18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc6_int_msk | ||
| fw_ctrl_fc7_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e1c Address@secenc_fw_ctrl : 0x50200e1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc7_int_msk | ||
| fw_ctrl_fc8_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e20 Address@secenc_fw_ctrl : 0x50200e20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc8_int_msk | ||
| fw_ctrl_fc9_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e24 Address@secenc_fw_ctrl : 0x50200e24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc9_int_msk | ||
| fw_ctrl_fc10_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e28 Address@secenc_fw_ctrl : 0x50200e28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc10_int_msk | ||
| fw_ctrl_fc11_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e2c Address@secenc_fw_ctrl : 0x50200e2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc11_int_msk | ||
| fw_ctrl_fc12_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e30 Address@secenc_fw_ctrl : 0x50200e30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc12_int_msk | ||
| fw_ctrl_fc13_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e34 Address@secenc_fw_ctrl : 0x50200e34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc13_int_msk | ||
| fw_ctrl_fc14_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e38 Address@secenc_fw_ctrl : 0x50200e38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc14_int_msk | ||
| fw_ctrl_fc15_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e3c Address@secenc_fw_ctrl : 0x50200e3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc15_int_msk | ||
| fw_ctrl_fc16_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e40 Address@secenc_fw_ctrl : 0x50200e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc16_int_msk | ||
| fw_ctrl_fc17_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e44 Address@secenc_fw_ctrl : 0x50200e44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc17_int_msk | ||
| fw_ctrl_fc18_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e48 Address@secenc_fw_ctrl : 0x50200e48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc18_int_msk | ||
| fw_ctrl_fc19_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e4c Address@secenc_fw_ctrl : 0x50200e4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc19_int_msk | ||
| fw_ctrl_fc20_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e50 Address@secenc_fw_ctrl : 0x50200e50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc20_int_msk | ||
| fw_ctrl_fc21_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e54 Address@secenc_fw_ctrl : 0x50200e54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc21_int_msk | ||
| fw_ctrl_fc22_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e58 Address@secenc_fw_ctrl : 0x50200e58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc22_int_msk | ||
| fw_ctrl_fc23_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e5c Address@secenc_fw_ctrl : 0x50200e5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc23_int_msk | ||
| fw_ctrl_fc24_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e60 Address@secenc_fw_ctrl : 0x50200e60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc24_int_msk | ||
| fw_ctrl_fc25_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e64 Address@secenc_fw_ctrl : 0x50200e64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc25_int_msk | ||
| fw_ctrl_fc26_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e68 Address@secenc_fw_ctrl : 0x50200e68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc26_int_msk | ||
| fw_ctrl_fc27_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e6c Address@secenc_fw_ctrl : 0x50200e6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc27_int_msk | ||
| fw_ctrl_fc28_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e70 Address@secenc_fw_ctrl : 0x50200e70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc28_int_msk | ||
| fw_ctrl_fc29_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e74 Address@secenc_fw_ctrl : 0x50200e74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc29_int_msk | ||
| fw_ctrl_fc30_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e78 Address@secenc_fw_ctrl : 0x50200e78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc30_int_msk | ||
| fw_ctrl_fc31_int_msk |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800e7c Address@secenc_fw_ctrl : 0x50200e7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_ctrl_fc31_int_msk | ||
| fw_ctrl_fw_tmp_ta |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800e90 Address@secenc_fw_ctrl : 0x50200e90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 21 | - |
reserved | ||
| 20 - 2 | tmp_trans_addr |
|
||
| 1 - 0 | - |
reserved | ||
| fw_ctrl_fw_tmp_tp |
|
|||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800e98 Address@secenc_fw_ctrl : 0x50200e98 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 18 | - |
reserved | ||||||
| 17 | priv |
|
||||||
| 16 | ns |
|
||||||
| 15 - 0 | - |
reserved | ||||||
| fw_ctrl_fw_tmp_mid |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800e9c Address@secenc_fw_ctrl : 0x50200e9c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mst_id |
|
||
| fw_ctrl_fw_tmp_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_ctrl : 0x1a800ea0 Address@secenc_fw_ctrl : 0x50200ea0 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
tr_vld |
|
||||||
| 30 | "0" |
ack |
|
||||||
| 29 - 0 | 0 |
- |
reserved | ||||||
| fw_ctrl_fc_cap0 |
|
||||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800fa0 Address@secenc_fw_ctrl : 0x50200fa0 |
Bits | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | - |
reserved | |||||||||
| 27 - 24 | se_lvl |
|
|||||||||
| 23 - 20 | sre_lvl |
|
|||||||||
| 19 - 16 | lde_lvl |
|
|||||||||
| 15 - 12 | te_lvl |
|
|||||||||
| 11 - 8 | rse_lvl |
|
|||||||||
| 7 - 4 | me_lvl |
|
|||||||||
| 3 - 0 | pe_lvl |
|
|||||||||
| fw_ctrl_fc_cap1 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fa4 Address@secenc_fw_ctrl : 0x50200fa4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_fc_cap1 | |||
| fw_ctrl_fc_cap2 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fa8 Address@secenc_fw_ctrl : 0x50200fa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_fc_cap2 | |||
| fw_ctrl_fc_cap3 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fac Address@secenc_fw_ctrl : 0x50200fac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_fc_cap3 | |||
| fw_ctrl_fc_cfg0 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fb0 Address@secenc_fw_ctrl : 0x50200fb0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 5 | - |
reserved | ||
| 4 - 0 | fc_id |
|
||
| fw_ctrl_fc_cfg1 |
|
||||||||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800fb4 Address@secenc_fw_ctrl : 0x50200fb4 |
Bits | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | - |
reserved | |||||||||||
| 20 | sec_spt |
|
|||||||||||
| 19 | ma_spt |
|
|||||||||||
| 18 | sh_spt |
|
|||||||||||
| 17 | inst_spt |
|
|||||||||||
| 16 | priv_spt |
|
|||||||||||
| 15 - 14 | - |
reserved | |||||||||||
| 13 - 12 | num_mpe |
|
|||||||||||
| 11 | - |
reserved | |||||||||||
| 10 - 8 | mnrs |
|
|||||||||||
| 7 - 0 | num_rgn |
|
|||||||||||
| fw_ctrl_fc_cfg2 |
|
|||||||
| R |
Address@host_sys_fw_ctrl : 0x1a800fb8 Address@secenc_fw_ctrl : 0x50200fb8 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 | single_mst |
|
||||||
| 30 - 21 | - |
reserved | ||||||
| 20 - 13 | prot_size |
|
||||||
| 12 - 8 | mst_id_width |
|
||||||
| 7 | - |
reserved | ||||||
| 6 - 0 | mxrs |
|
||||||
| fw_ctrl_fc_cfg3 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fbc Address@secenc_fw_ctrl : 0x50200fbc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 6 | - |
reserved | ||
| 5 - 0 | num_fc |
|
||
| fw_ctrl_iidr |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fc8 Address@secenc_fw_ctrl : 0x50200fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| fw_ctrl_aidr |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fcc Address@secenc_fw_ctrl : 0x50200fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | arch_major_rev |
|
||
| 3 - 0 | arch_minor_rev |
|
||
| fw_ctrl_pid4 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fd0 Address@secenc_fw_ctrl : 0x50200fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| fw_ctrl_pid5 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fd4 Address@secenc_fw_ctrl : 0x50200fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_pid5 | |||
| fw_ctrl_pid6 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fd8 Address@secenc_fw_ctrl : 0x50200fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_pid6 | |||
| fw_ctrl_pid7 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fdc Address@secenc_fw_ctrl : 0x50200fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_ctrl_pid7 | |||
| fw_ctrl_pid0 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fe0 Address@secenc_fw_ctrl : 0x50200fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| fw_ctrl_pid1 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fe4 Address@secenc_fw_ctrl : 0x50200fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| fw_ctrl_pid2 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fe8 Address@secenc_fw_ctrl : 0x50200fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| fw_ctrl_pid3 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800fec Address@secenc_fw_ctrl : 0x50200fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| fw_ctrl_cid0 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800ff0 Address@secenc_fw_ctrl : 0x50200ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| fw_ctrl_cid1 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800ff4 Address@secenc_fw_ctrl : 0x50200ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| fw_ctrl_cid2 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800ff8 Address@secenc_fw_ctrl : 0x50200ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| fw_ctrl_cid3 |
|
|||
| R |
Address@host_sys_fw_ctrl : 0x1a800ffc Address@secenc_fw_ctrl : 0x50200ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0-3 | 0-c | - | reserved |
| 4 | 10 | R/W | fw_comp_ld_ctrl |
| 5-3f | 14-fc | - | reserved |
| 40 | 100 | R/W | fw_comp_pe_ctrl |
| 41 | 104 | R | fw_comp_pe_st |
| 42 | 108 | R/W | fw_comp_pe_bps |
| 43 | 10c | R/W | fw_comp_rwe_ctrl |
| 44 | 110 | R/W | fw_comp_rgn_ctrl0 |
| 45 | 114 | R/W | fw_comp_rgn_ctrl1 |
| 46 | 118 | R/W | fw_comp_rgn_lctrl |
| 47 | 11c | R | fw_comp_rgn_st |
| 48 | 120 | R/W | fw_comp_rgn_cfg0 |
| 49 | 124 | R/W | fw_comp_rgn_cfg1 |
| 4a | 128 | R/W | fw_comp_rgn_size |
| 4b | 12c | - | reserved |
| 4c | 130 | R/W | fw_comp_rgn_tcfg0 |
| 4d | 134 | R/W | fw_comp_rgn_tcfg1 |
| 4e | 138 | R/W | fw_comp_rgn_tcfg2 |
| 4f | 13c | - | reserved |
| 50 | 140 | R/W | fw_comp_rgn_mid0 |
| 51 | 144 | R/W | fw_comp_rgn_mpl0 |
| 52 | 148 | R/W | fw_comp_rgn_mid1 |
| 53 | 14c | R/W | fw_comp_rgn_mpl1 |
| 54 | 150 | R/W | fw_comp_rgn_mid2 |
| 55 | 154 | R/W | fw_comp_rgn_mpl2 |
| 56 | 158 | R/W | fw_comp_rgn_mid3 |
| 57 | 15c | R/W | fw_comp_rgn_mpl3 |
| 58-5f | 160-17c | - | reserved |
| 60 | 180 | R | fw_comp_fe_tal |
| 61 | 184 | R | fw_comp_fe_tau |
| 62 | 188 | R | fw_comp_fe_tp |
| 63 | 18c | R | fw_comp_fe_mid |
| 64 | 190 | R/W | fw_comp_fe_ctrl |
| 65-7f | 194-1fc | - | reserved |
| 80 | 200 | R/W | fw_comp_me_ctrl |
| 81 | 204 | R | fw_comp_me_st |
| 82-97 | 208-25c | - | reserved |
| 98 | 260 | R | fw_comp_edr_tal |
| 99 | 264 | R | fw_comp_edr_tau |
| 9a | 268 | R | fw_comp_edr_tp |
| 9b | 26c | R | fw_comp_edr_mid |
| 9c | 270 | R/W | fw_comp_edr_ctrl |
| 9d-3e7 | 274-f9c | - | reserved |
| 3e8 | fa0 | R | fw_comp_fc_cap0 |
| 3e9 | fa4 | R | fw_comp_fc_cap1 |
| 3ea | fa8 | R | fw_comp_fc_cap2 |
| 3eb | fac | R | fw_comp_fc_cap3 |
| 3ec | fb0 | R | fw_comp_fc_cfg0 |
| 3ed | fb4 | R | fw_comp_fc_cfg1 |
| 3ee | fb8 | R | fw_comp_fc_cfg2 |
| 3ef | fbc | R | fw_comp_fc_cfg3 |
| 3f0-3ff | fc0-ffc | - | reserved |
| fw_comp_ld_ctrl |
|
|||||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810010 Address@host_sys_fw_comp_dbgperi : 0x1a820010 Address@host_sys_fw_comp_aonperi : 0x1a830010 Address@host_sys_fw_comp_envm : 0x1a840010 Address@host_sys_fw_comp_cvm : 0x1a850010 Address@host_sys_fw_comp_hostcpu : 0x1a860010 Address@host_sys_fw_comp_com : 0x1a870010 Address@host_sys_fw_comp_mot : 0x1a880010 Address@host_sys_fw_comp_hperi_slv : 0x1a890010 Address@host_sys_fw_comp_sms_slv : 0x1a8a0010 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0010 Address@host_sys_fw_comp_sms_mst : 0x1a8c0010 Address@host_sys_fw_comp_evm : 0x1a8d0010 Address@host_sys_fw_comp_debug : 0x1a8e0010 Address@secenc_fw_comp_fc1 : 0x50210010 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||||||||
| 1 | "0" |
ldi_st |
|
|||||||||||||
| 0 | "0" |
lock |
|
|||||||||||||
| fw_comp_pe_ctrl |
|
|||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810100 Address@host_sys_fw_comp_dbgperi : 0x1a820100 Address@host_sys_fw_comp_aonperi : 0x1a830100 Address@host_sys_fw_comp_envm : 0x1a840100 Address@host_sys_fw_comp_cvm : 0x1a850100 Address@host_sys_fw_comp_hostcpu : 0x1a860100 Address@host_sys_fw_comp_com : 0x1a870100 Address@host_sys_fw_comp_mot : 0x1a880100 Address@host_sys_fw_comp_hperi_slv : 0x1a890100 Address@host_sys_fw_comp_sms_slv : 0x1a8a0100 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0100 Address@host_sys_fw_comp_sms_mst : 0x1a8c0100 Address@host_sys_fw_comp_evm : 0x1a8d0100 Address@host_sys_fw_comp_debug : 0x1a8e0100 Address@secenc_fw_comp_fc1 : 0x50210100 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
en |
|
|||||||||
| 30 - 6 | 0 |
- |
reserved | |||||||||
| 5 | "0" |
bypass_msk |
|
|||||||||
| 4 | "0" |
fe_pwr |
|
|||||||||
| 3 - 2 | "00" |
flt_cfg |
|
|||||||||
| 1 | "0" |
raz |
|
|||||||||
| 0 | "0" |
err |
|
|||||||||
| fw_comp_pe_st |
|
|||||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810104 Address@host_sys_fw_comp_dbgperi : 0x1a820104 Address@host_sys_fw_comp_aonperi : 0x1a830104 Address@host_sys_fw_comp_envm : 0x1a840104 Address@host_sys_fw_comp_cvm : 0x1a850104 Address@host_sys_fw_comp_hostcpu : 0x1a860104 Address@host_sys_fw_comp_com : 0x1a870104 Address@host_sys_fw_comp_mot : 0x1a880104 Address@host_sys_fw_comp_hperi_slv : 0x1a890104 Address@host_sys_fw_comp_sms_slv : 0x1a8a0104 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0104 Address@host_sys_fw_comp_sms_mst : 0x1a8c0104 Address@host_sys_fw_comp_evm : 0x1a8d0104 Address@host_sys_fw_comp_debug : 0x1a8e0104 Address@secenc_fw_comp_fc1 : 0x50210104 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | en |
|
||||||||||
| 30 - 6 | - |
reserved | ||||||||||
| 5 | bypass_msk |
|
||||||||||
| 4 | fe_pwr |
|
||||||||||
| 3 - 2 | flt_cfg |
|
||||||||||
| 1 | raz |
|
||||||||||
| 0 | err |
|
||||||||||
| fw_comp_pe_bps |
|
||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810108 Address@host_sys_fw_comp_dbgperi : 0x1a820108 Address@host_sys_fw_comp_aonperi : 0x1a830108 Address@host_sys_fw_comp_envm : 0x1a840108 Address@host_sys_fw_comp_cvm : 0x1a850108 Address@host_sys_fw_comp_hostcpu : 0x1a860108 Address@host_sys_fw_comp_com : 0x1a870108 Address@host_sys_fw_comp_mot : 0x1a880108 Address@host_sys_fw_comp_hperi_slv : 0x1a890108 Address@host_sys_fw_comp_sms_slv : 0x1a8a0108 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0108 Address@host_sys_fw_comp_sms_mst : 0x1a8c0108 Address@host_sys_fw_comp_evm : 0x1a8d0108 Address@host_sys_fw_comp_debug : 0x1a8e0108 Address@secenc_fw_comp_fc1 : 0x50210108 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
bypass_vld |
|
||||||||||
| 30 - 2 | 0 |
- |
reserved | ||||||||||
| 1 | "0" |
bypass_st |
|
||||||||||
| 0 | "0" |
bypass_if_st |
|
||||||||||
| fw_comp_rwe_ctrl |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a81010c Address@host_sys_fw_comp_dbgperi : 0x1a82010c Address@host_sys_fw_comp_aonperi : 0x1a83010c Address@host_sys_fw_comp_envm : 0x1a84010c Address@host_sys_fw_comp_cvm : 0x1a85010c Address@host_sys_fw_comp_hostcpu : 0x1a86010c Address@host_sys_fw_comp_com : 0x1a87010c Address@host_sys_fw_comp_mot : 0x1a88010c Address@host_sys_fw_comp_hperi_slv : 0x1a89010c Address@host_sys_fw_comp_sms_slv : 0x1a8a010c Address@host_sys_fw_comp_hperi_mst : 0x1a8b010c Address@host_sys_fw_comp_sms_mst : 0x1a8c010c Address@host_sys_fw_comp_evm : 0x1a8d010c Address@host_sys_fw_comp_debug : 0x1a8e010c Address@secenc_fw_comp_fc1 : 0x5021010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
rgn_indx |
|
|
| fw_comp_rgn_ctrl0 |
|
|||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810110 Address@host_sys_fw_comp_dbgperi : 0x1a820110 Address@host_sys_fw_comp_aonperi : 0x1a830110 Address@host_sys_fw_comp_envm : 0x1a840110 Address@host_sys_fw_comp_cvm : 0x1a850110 Address@host_sys_fw_comp_hostcpu : 0x1a860110 Address@host_sys_fw_comp_com : 0x1a870110 Address@host_sys_fw_comp_mot : 0x1a880110 Address@host_sys_fw_comp_hperi_slv : 0x1a890110 Address@host_sys_fw_comp_sms_slv : 0x1a8a0110 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0110 Address@host_sys_fw_comp_sms_mst : 0x1a8c0110 Address@host_sys_fw_comp_evm : 0x1a8d0110 Address@host_sys_fw_comp_debug : 0x1a8e0110 Address@secenc_fw_comp_fc1 : 0x50210110 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
en |
|
|||||
| fw_comp_rgn_ctrl1 |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810114 Address@host_sys_fw_comp_dbgperi : 0x1a820114 Address@host_sys_fw_comp_aonperi : 0x1a830114 Address@host_sys_fw_comp_envm : 0x1a840114 Address@host_sys_fw_comp_cvm : 0x1a850114 Address@host_sys_fw_comp_hostcpu : 0x1a860114 Address@host_sys_fw_comp_com : 0x1a870114 Address@host_sys_fw_comp_mot : 0x1a880114 Address@host_sys_fw_comp_hperi_slv : 0x1a890114 Address@host_sys_fw_comp_sms_slv : 0x1a8a0114 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0114 Address@host_sys_fw_comp_sms_mst : 0x1a8c0114 Address@host_sys_fw_comp_evm : 0x1a8d0114 Address@host_sys_fw_comp_debug : 0x1a8e0114 Address@secenc_fw_comp_fc1 : 0x50210114 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | ||||||
| 4 | "0" |
mpe3_en |
|
||||||
| 3 | "0" |
mpe2_en |
|
||||||
| 2 | "0" |
mpe1_en |
|
||||||
| 1 | "0" |
mpe0_en |
|
||||||
| 0 | 0 |
- |
reserved | ||||||
| fw_comp_rgn_lctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810118 Address@host_sys_fw_comp_dbgperi : 0x1a820118 Address@host_sys_fw_comp_aonperi : 0x1a830118 Address@host_sys_fw_comp_envm : 0x1a840118 Address@host_sys_fw_comp_cvm : 0x1a850118 Address@host_sys_fw_comp_hostcpu : 0x1a860118 Address@host_sys_fw_comp_com : 0x1a870118 Address@host_sys_fw_comp_mot : 0x1a880118 Address@host_sys_fw_comp_hperi_slv : 0x1a890118 Address@host_sys_fw_comp_sms_slv : 0x1a8a0118 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0118 Address@host_sys_fw_comp_sms_mst : 0x1a8c0118 Address@host_sys_fw_comp_evm : 0x1a8d0118 Address@host_sys_fw_comp_debug : 0x1a8e0118 Address@secenc_fw_comp_fc1 : 0x50210118 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
lock |
|
||||||
| fw_comp_rgn_st |
|
||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a81011c Address@host_sys_fw_comp_dbgperi : 0x1a82011c Address@host_sys_fw_comp_aonperi : 0x1a83011c Address@host_sys_fw_comp_envm : 0x1a84011c Address@host_sys_fw_comp_cvm : 0x1a85011c Address@host_sys_fw_comp_hostcpu : 0x1a86011c Address@host_sys_fw_comp_com : 0x1a87011c Address@host_sys_fw_comp_mot : 0x1a88011c Address@host_sys_fw_comp_hperi_slv : 0x1a89011c Address@host_sys_fw_comp_sms_slv : 0x1a8a011c Address@host_sys_fw_comp_hperi_mst : 0x1a8b011c Address@host_sys_fw_comp_sms_mst : 0x1a8c011c Address@host_sys_fw_comp_evm : 0x1a8d011c Address@host_sys_fw_comp_debug : 0x1a8e011c Address@secenc_fw_comp_fc1 : 0x5021011c |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | - |
reserved | |||||||
| 4 | mpe3_en |
|
|||||||
| 3 | mpe2_en |
|
|||||||
| 2 | mpe1_en |
|
|||||||
| 1 | en |
|
|||||||
| 0 | - |
reserved | |||||||
| fw_comp_rgn_cfg0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810120 Address@host_sys_fw_comp_dbgperi : 0x1a820120 Address@host_sys_fw_comp_aonperi : 0x1a830120 Address@host_sys_fw_comp_envm : 0x1a840120 Address@host_sys_fw_comp_cvm : 0x1a850120 Address@host_sys_fw_comp_hostcpu : 0x1a860120 Address@host_sys_fw_comp_com : 0x1a870120 Address@host_sys_fw_comp_mot : 0x1a880120 Address@host_sys_fw_comp_hperi_slv : 0x1a890120 Address@host_sys_fw_comp_sms_slv : 0x1a8a0120 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0120 Address@host_sys_fw_comp_sms_mst : 0x1a8c0120 Address@host_sys_fw_comp_evm : 0x1a8d0120 Address@host_sys_fw_comp_debug : 0x1a8e0120 Address@secenc_fw_comp_fc1 : 0x50210120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0x0 |
base_addr |
|
|
| 4 - 0 | 0 |
- |
reserved | |
| fw_comp_rgn_cfg1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810124 Address@host_sys_fw_comp_dbgperi : 0x1a820124 Address@host_sys_fw_comp_aonperi : 0x1a830124 Address@host_sys_fw_comp_envm : 0x1a840124 Address@host_sys_fw_comp_cvm : 0x1a850124 Address@host_sys_fw_comp_hostcpu : 0x1a860124 Address@host_sys_fw_comp_com : 0x1a870124 Address@host_sys_fw_comp_mot : 0x1a880124 Address@host_sys_fw_comp_hperi_slv : 0x1a890124 Address@host_sys_fw_comp_sms_slv : 0x1a8a0124 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0124 Address@host_sys_fw_comp_sms_mst : 0x1a8c0124 Address@host_sys_fw_comp_evm : 0x1a8d0124 Address@host_sys_fw_comp_debug : 0x1a8e0124 Address@secenc_fw_comp_fc1 : 0x50210124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
base_addr |
|
|
| fw_comp_rgn_size |
|
|||||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810128 Address@host_sys_fw_comp_dbgperi : 0x1a820128 Address@host_sys_fw_comp_aonperi : 0x1a830128 Address@host_sys_fw_comp_envm : 0x1a840128 Address@host_sys_fw_comp_cvm : 0x1a850128 Address@host_sys_fw_comp_hostcpu : 0x1a860128 Address@host_sys_fw_comp_com : 0x1a870128 Address@host_sys_fw_comp_mot : 0x1a880128 Address@host_sys_fw_comp_hperi_slv : 0x1a890128 Address@host_sys_fw_comp_sms_slv : 0x1a8a0128 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0128 Address@host_sys_fw_comp_sms_mst : 0x1a8c0128 Address@host_sys_fw_comp_evm : 0x1a8d0128 Address@host_sys_fw_comp_debug : 0x1a8e0128 Address@secenc_fw_comp_fc1 : 0x50210128 |
Bits | Reset value | Name | Description | ||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |||||||||||||
| 8 | "0" |
mulnpo2 |
|
|||||||||||||
| 7 - 0 | "00000000" |
size |
|
|||||||||||||
| fw_comp_rgn_tcfg0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810130 Address@host_sys_fw_comp_dbgperi : 0x1a820130 Address@host_sys_fw_comp_aonperi : 0x1a830130 Address@host_sys_fw_comp_envm : 0x1a840130 Address@host_sys_fw_comp_cvm : 0x1a850130 Address@host_sys_fw_comp_hostcpu : 0x1a860130 Address@host_sys_fw_comp_com : 0x1a870130 Address@host_sys_fw_comp_mot : 0x1a880130 Address@host_sys_fw_comp_hperi_slv : 0x1a890130 Address@host_sys_fw_comp_sms_slv : 0x1a8a0130 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0130 Address@host_sys_fw_comp_sms_mst : 0x1a8c0130 Address@host_sys_fw_comp_evm : 0x1a8d0130 Address@host_sys_fw_comp_debug : 0x1a8e0130 Address@secenc_fw_comp_fc1 : 0x50210130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0x0 |
output_addr |
|
|
| 4 - 0 | 0 |
- |
reserved | |
| fw_comp_rgn_tcfg1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810134 Address@host_sys_fw_comp_dbgperi : 0x1a820134 Address@host_sys_fw_comp_aonperi : 0x1a830134 Address@host_sys_fw_comp_envm : 0x1a840134 Address@host_sys_fw_comp_cvm : 0x1a850134 Address@host_sys_fw_comp_hostcpu : 0x1a860134 Address@host_sys_fw_comp_com : 0x1a870134 Address@host_sys_fw_comp_mot : 0x1a880134 Address@host_sys_fw_comp_hperi_slv : 0x1a890134 Address@host_sys_fw_comp_sms_slv : 0x1a8a0134 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0134 Address@host_sys_fw_comp_sms_mst : 0x1a8c0134 Address@host_sys_fw_comp_evm : 0x1a8d0134 Address@host_sys_fw_comp_debug : 0x1a8e0134 Address@secenc_fw_comp_fc1 : 0x50210134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
upper_addr |
|
|
| fw_comp_rgn_tcfg2 |
|
||||||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810138 Address@host_sys_fw_comp_dbgperi : 0x1a820138 Address@host_sys_fw_comp_aonperi : 0x1a830138 Address@host_sys_fw_comp_envm : 0x1a840138 Address@host_sys_fw_comp_cvm : 0x1a850138 Address@host_sys_fw_comp_hostcpu : 0x1a860138 Address@host_sys_fw_comp_com : 0x1a870138 Address@host_sys_fw_comp_mot : 0x1a880138 Address@host_sys_fw_comp_hperi_slv : 0x1a890138 Address@host_sys_fw_comp_sms_slv : 0x1a8a0138 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0138 Address@host_sys_fw_comp_sms_mst : 0x1a8c0138 Address@host_sys_fw_comp_evm : 0x1a8d0138 Address@host_sys_fw_comp_debug : 0x1a8e0138 Address@secenc_fw_comp_fc1 : 0x50210138 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | ||||||||||
| 17 | "0" |
addr_trans_en |
|
||||||||||
| 16 | "0" |
ma_trans_en |
|
||||||||||
| 15 - 14 | "00" |
instr |
|
||||||||||
| 13 - 12 | "00" |
priv |
|
||||||||||
| 11 - 4 | "00000000" |
ma |
|
||||||||||
| 3 - 2 | "00" |
sh |
|
||||||||||
| 1 - 0 | "00" |
ns |
|
||||||||||
| fw_comp_rgn_mid0 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810140 Address@host_sys_fw_comp_dbgperi : 0x1a820140 Address@host_sys_fw_comp_aonperi : 0x1a830140 Address@host_sys_fw_comp_envm : 0x1a840140 Address@host_sys_fw_comp_cvm : 0x1a850140 Address@host_sys_fw_comp_hostcpu : 0x1a860140 Address@host_sys_fw_comp_com : 0x1a870140 Address@host_sys_fw_comp_mot : 0x1a880140 Address@host_sys_fw_comp_hperi_slv : 0x1a890140 Address@host_sys_fw_comp_sms_slv : 0x1a8a0140 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0140 Address@host_sys_fw_comp_sms_mst : 0x1a8c0140 Address@host_sys_fw_comp_evm : 0x1a8d0140 Address@host_sys_fw_comp_debug : 0x1a8e0140 Address@secenc_fw_comp_fc1 : 0x50210140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
mst_id |
|
|
| fw_comp_rgn_mpl0 |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810144 Address@host_sys_fw_comp_dbgperi : 0x1a820144 Address@host_sys_fw_comp_aonperi : 0x1a830144 Address@host_sys_fw_comp_envm : 0x1a840144 Address@host_sys_fw_comp_cvm : 0x1a850144 Address@host_sys_fw_comp_hostcpu : 0x1a860144 Address@host_sys_fw_comp_com : 0x1a870144 Address@host_sys_fw_comp_mot : 0x1a880144 Address@host_sys_fw_comp_hperi_slv : 0x1a890144 Address@host_sys_fw_comp_sms_slv : 0x1a8a0144 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0144 Address@host_sys_fw_comp_sms_mst : 0x1a8c0144 Address@host_sys_fw_comp_evm : 0x1a8d0144 Address@host_sys_fw_comp_debug : 0x1a8e0144 Address@secenc_fw_comp_fc1 : 0x50210144 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||
| 12 | "0" |
any_mst |
|
||||||
| 11 | "0" |
spx |
|
||||||
| 10 | "0" |
spw |
|
||||||
| 9 | "0" |
spr |
|
||||||
| 8 | "0" |
sux |
|
||||||
| 7 | "0" |
suw |
|
||||||
| 6 | "0" |
sur |
|
||||||
| 5 | "0" |
nspx |
|
||||||
| 4 | "0" |
nspw |
|
||||||
| 3 | "0" |
nspr |
|
||||||
| 2 | "0" |
nsux |
|
||||||
| 1 | "0" |
nsuw |
|
||||||
| 0 | "0" |
nsur |
|
||||||
| fw_comp_rgn_mid1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810148 Address@host_sys_fw_comp_dbgperi : 0x1a820148 Address@host_sys_fw_comp_aonperi : 0x1a830148 Address@host_sys_fw_comp_envm : 0x1a840148 Address@host_sys_fw_comp_cvm : 0x1a850148 Address@host_sys_fw_comp_hostcpu : 0x1a860148 Address@host_sys_fw_comp_com : 0x1a870148 Address@host_sys_fw_comp_mot : 0x1a880148 Address@host_sys_fw_comp_hperi_slv : 0x1a890148 Address@host_sys_fw_comp_sms_slv : 0x1a8a0148 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0148 Address@host_sys_fw_comp_sms_mst : 0x1a8c0148 Address@host_sys_fw_comp_evm : 0x1a8d0148 Address@host_sys_fw_comp_debug : 0x1a8e0148 Address@secenc_fw_comp_fc1 : 0x50210148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mid1 | ||
| fw_comp_rgn_mpl1 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a81014c Address@host_sys_fw_comp_dbgperi : 0x1a82014c Address@host_sys_fw_comp_aonperi : 0x1a83014c Address@host_sys_fw_comp_envm : 0x1a84014c Address@host_sys_fw_comp_cvm : 0x1a85014c Address@host_sys_fw_comp_hostcpu : 0x1a86014c Address@host_sys_fw_comp_com : 0x1a87014c Address@host_sys_fw_comp_mot : 0x1a88014c Address@host_sys_fw_comp_hperi_slv : 0x1a89014c Address@host_sys_fw_comp_sms_slv : 0x1a8a014c Address@host_sys_fw_comp_hperi_mst : 0x1a8b014c Address@host_sys_fw_comp_sms_mst : 0x1a8c014c Address@host_sys_fw_comp_evm : 0x1a8d014c Address@host_sys_fw_comp_debug : 0x1a8e014c Address@secenc_fw_comp_fc1 : 0x5021014c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mpl1 | ||
| fw_comp_rgn_mid2 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810150 Address@host_sys_fw_comp_dbgperi : 0x1a820150 Address@host_sys_fw_comp_aonperi : 0x1a830150 Address@host_sys_fw_comp_envm : 0x1a840150 Address@host_sys_fw_comp_cvm : 0x1a850150 Address@host_sys_fw_comp_hostcpu : 0x1a860150 Address@host_sys_fw_comp_com : 0x1a870150 Address@host_sys_fw_comp_mot : 0x1a880150 Address@host_sys_fw_comp_hperi_slv : 0x1a890150 Address@host_sys_fw_comp_sms_slv : 0x1a8a0150 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0150 Address@host_sys_fw_comp_sms_mst : 0x1a8c0150 Address@host_sys_fw_comp_evm : 0x1a8d0150 Address@host_sys_fw_comp_debug : 0x1a8e0150 Address@secenc_fw_comp_fc1 : 0x50210150 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mid2 | ||
| fw_comp_rgn_mpl2 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810154 Address@host_sys_fw_comp_dbgperi : 0x1a820154 Address@host_sys_fw_comp_aonperi : 0x1a830154 Address@host_sys_fw_comp_envm : 0x1a840154 Address@host_sys_fw_comp_cvm : 0x1a850154 Address@host_sys_fw_comp_hostcpu : 0x1a860154 Address@host_sys_fw_comp_com : 0x1a870154 Address@host_sys_fw_comp_mot : 0x1a880154 Address@host_sys_fw_comp_hperi_slv : 0x1a890154 Address@host_sys_fw_comp_sms_slv : 0x1a8a0154 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0154 Address@host_sys_fw_comp_sms_mst : 0x1a8c0154 Address@host_sys_fw_comp_evm : 0x1a8d0154 Address@host_sys_fw_comp_debug : 0x1a8e0154 Address@secenc_fw_comp_fc1 : 0x50210154 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mpl2 | ||
| fw_comp_rgn_mid3 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810158 Address@host_sys_fw_comp_dbgperi : 0x1a820158 Address@host_sys_fw_comp_aonperi : 0x1a830158 Address@host_sys_fw_comp_envm : 0x1a840158 Address@host_sys_fw_comp_cvm : 0x1a850158 Address@host_sys_fw_comp_hostcpu : 0x1a860158 Address@host_sys_fw_comp_com : 0x1a870158 Address@host_sys_fw_comp_mot : 0x1a880158 Address@host_sys_fw_comp_hperi_slv : 0x1a890158 Address@host_sys_fw_comp_sms_slv : 0x1a8a0158 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0158 Address@host_sys_fw_comp_sms_mst : 0x1a8c0158 Address@host_sys_fw_comp_evm : 0x1a8d0158 Address@host_sys_fw_comp_debug : 0x1a8e0158 Address@secenc_fw_comp_fc1 : 0x50210158 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mid3 | ||
| fw_comp_rgn_mpl3 |
|
|||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a81015c Address@host_sys_fw_comp_dbgperi : 0x1a82015c Address@host_sys_fw_comp_aonperi : 0x1a83015c Address@host_sys_fw_comp_envm : 0x1a84015c Address@host_sys_fw_comp_cvm : 0x1a85015c Address@host_sys_fw_comp_hostcpu : 0x1a86015c Address@host_sys_fw_comp_com : 0x1a87015c Address@host_sys_fw_comp_mot : 0x1a88015c Address@host_sys_fw_comp_hperi_slv : 0x1a89015c Address@host_sys_fw_comp_sms_slv : 0x1a8a015c Address@host_sys_fw_comp_hperi_mst : 0x1a8b015c Address@host_sys_fw_comp_sms_mst : 0x1a8c015c Address@host_sys_fw_comp_evm : 0x1a8d015c Address@host_sys_fw_comp_debug : 0x1a8e015c Address@secenc_fw_comp_fc1 : 0x5021015c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
fw_comp_rgn_mpl3 | ||
| fw_comp_fe_tal |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810180 Address@host_sys_fw_comp_dbgperi : 0x1a820180 Address@host_sys_fw_comp_aonperi : 0x1a830180 Address@host_sys_fw_comp_envm : 0x1a840180 Address@host_sys_fw_comp_cvm : 0x1a850180 Address@host_sys_fw_comp_hostcpu : 0x1a860180 Address@host_sys_fw_comp_com : 0x1a870180 Address@host_sys_fw_comp_mot : 0x1a880180 Address@host_sys_fw_comp_hperi_slv : 0x1a890180 Address@host_sys_fw_comp_sms_slv : 0x1a8a0180 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0180 Address@host_sys_fw_comp_sms_mst : 0x1a8c0180 Address@host_sys_fw_comp_evm : 0x1a8d0180 Address@host_sys_fw_comp_debug : 0x1a8e0180 Address@secenc_fw_comp_fc1 : 0x50210180 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fault_addr_lwr |
|
||
| fw_comp_fe_tau |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810184 Address@host_sys_fw_comp_dbgperi : 0x1a820184 Address@host_sys_fw_comp_aonperi : 0x1a830184 Address@host_sys_fw_comp_envm : 0x1a840184 Address@host_sys_fw_comp_cvm : 0x1a850184 Address@host_sys_fw_comp_hostcpu : 0x1a860184 Address@host_sys_fw_comp_com : 0x1a870184 Address@host_sys_fw_comp_mot : 0x1a880184 Address@host_sys_fw_comp_hperi_slv : 0x1a890184 Address@host_sys_fw_comp_sms_slv : 0x1a8a0184 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0184 Address@host_sys_fw_comp_sms_mst : 0x1a8c0184 Address@host_sys_fw_comp_evm : 0x1a8d0184 Address@host_sys_fw_comp_debug : 0x1a8e0184 Address@secenc_fw_comp_fc1 : 0x50210184 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fault_addr_upr |
|
||
| fw_comp_fe_tp |
|
||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810188 Address@host_sys_fw_comp_dbgperi : 0x1a820188 Address@host_sys_fw_comp_aonperi : 0x1a830188 Address@host_sys_fw_comp_envm : 0x1a840188 Address@host_sys_fw_comp_cvm : 0x1a850188 Address@host_sys_fw_comp_hostcpu : 0x1a860188 Address@host_sys_fw_comp_com : 0x1a870188 Address@host_sys_fw_comp_mot : 0x1a880188 Address@host_sys_fw_comp_hperi_slv : 0x1a890188 Address@host_sys_fw_comp_sms_slv : 0x1a8a0188 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0188 Address@host_sys_fw_comp_sms_mst : 0x1a8c0188 Address@host_sys_fw_comp_evm : 0x1a8d0188 Address@host_sys_fw_comp_debug : 0x1a8e0188 Address@secenc_fw_comp_fc1 : 0x50210188 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | - |
reserved | |||||||
| 21 | w |
|
|||||||
| 20 - 19 | - |
reserved | |||||||
| 18 | instr |
|
|||||||
| 17 | priv |
|
|||||||
| 16 | ns |
|
|||||||
| 15 - 0 | - |
reserved | |||||||
| fw_comp_fe_mid |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a81018c Address@host_sys_fw_comp_dbgperi : 0x1a82018c Address@host_sys_fw_comp_aonperi : 0x1a83018c Address@host_sys_fw_comp_envm : 0x1a84018c Address@host_sys_fw_comp_cvm : 0x1a85018c Address@host_sys_fw_comp_hostcpu : 0x1a86018c Address@host_sys_fw_comp_com : 0x1a87018c Address@host_sys_fw_comp_mot : 0x1a88018c Address@host_sys_fw_comp_hperi_slv : 0x1a89018c Address@host_sys_fw_comp_sms_slv : 0x1a8a018c Address@host_sys_fw_comp_hperi_mst : 0x1a8b018c Address@host_sys_fw_comp_sms_mst : 0x1a8c018c Address@host_sys_fw_comp_evm : 0x1a8d018c Address@host_sys_fw_comp_debug : 0x1a8e018c Address@secenc_fw_comp_fc1 : 0x5021018c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mst_id |
|
||
| fw_comp_fe_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810190 Address@host_sys_fw_comp_dbgperi : 0x1a820190 Address@host_sys_fw_comp_aonperi : 0x1a830190 Address@host_sys_fw_comp_envm : 0x1a840190 Address@host_sys_fw_comp_cvm : 0x1a850190 Address@host_sys_fw_comp_hostcpu : 0x1a860190 Address@host_sys_fw_comp_com : 0x1a870190 Address@host_sys_fw_comp_mot : 0x1a880190 Address@host_sys_fw_comp_hperi_slv : 0x1a890190 Address@host_sys_fw_comp_sms_slv : 0x1a8a0190 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0190 Address@host_sys_fw_comp_sms_mst : 0x1a8c0190 Address@host_sys_fw_comp_evm : 0x1a8d0190 Address@host_sys_fw_comp_debug : 0x1a8e0190 Address@secenc_fw_comp_fc1 : 0x50210190 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
last_fe |
|
||||||
| 30 | "0" |
fe_vld |
|
||||||
| 29 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
flt_type |
|
||||||
| 2 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
ack |
|
||||||
| fw_comp_me_ctrl |
|
|||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810200 Address@host_sys_fw_comp_dbgperi : 0x1a820200 Address@host_sys_fw_comp_aonperi : 0x1a830200 Address@host_sys_fw_comp_envm : 0x1a840200 Address@host_sys_fw_comp_cvm : 0x1a850200 Address@host_sys_fw_comp_hostcpu : 0x1a860200 Address@host_sys_fw_comp_com : 0x1a870200 Address@host_sys_fw_comp_mot : 0x1a880200 Address@host_sys_fw_comp_hperi_slv : 0x1a890200 Address@host_sys_fw_comp_sms_slv : 0x1a8a0200 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0200 Address@host_sys_fw_comp_sms_mst : 0x1a8c0200 Address@host_sys_fw_comp_evm : 0x1a8d0200 Address@host_sys_fw_comp_debug : 0x1a8e0200 Address@secenc_fw_comp_fc1 : 0x50210200 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
en |
|
|||||
| 30 - 5 | 0 |
- |
reserved | |||||
| 4 | "0" |
edr_pwr |
|
|||||
| 3 - 2 | 0 |
- |
reserved | |||||
| 1 | "0" |
rdum |
|
|||||
| 0 | 0 |
- |
reserved | |||||
| fw_comp_me_st |
|
||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810204 Address@host_sys_fw_comp_dbgperi : 0x1a820204 Address@host_sys_fw_comp_aonperi : 0x1a830204 Address@host_sys_fw_comp_envm : 0x1a840204 Address@host_sys_fw_comp_cvm : 0x1a850204 Address@host_sys_fw_comp_hostcpu : 0x1a860204 Address@host_sys_fw_comp_com : 0x1a870204 Address@host_sys_fw_comp_mot : 0x1a880204 Address@host_sys_fw_comp_hperi_slv : 0x1a890204 Address@host_sys_fw_comp_sms_slv : 0x1a8a0204 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0204 Address@host_sys_fw_comp_sms_mst : 0x1a8c0204 Address@host_sys_fw_comp_evm : 0x1a8d0204 Address@host_sys_fw_comp_debug : 0x1a8e0204 Address@secenc_fw_comp_fc1 : 0x50210204 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 | en |
|
|||||||
| 30 - 5 | - |
reserved | |||||||
| 4 | edr_pwr |
|
|||||||
| 3 - 2 | - |
reserved | |||||||
| 1 | rdum |
|
|||||||
| 0 | - |
reserved | |||||||
| fw_comp_edr_tal |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810260 Address@host_sys_fw_comp_dbgperi : 0x1a820260 Address@host_sys_fw_comp_aonperi : 0x1a830260 Address@host_sys_fw_comp_envm : 0x1a840260 Address@host_sys_fw_comp_cvm : 0x1a850260 Address@host_sys_fw_comp_hostcpu : 0x1a860260 Address@host_sys_fw_comp_com : 0x1a870260 Address@host_sys_fw_comp_mot : 0x1a880260 Address@host_sys_fw_comp_hperi_slv : 0x1a890260 Address@host_sys_fw_comp_sms_slv : 0x1a8a0260 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0260 Address@host_sys_fw_comp_sms_mst : 0x1a8c0260 Address@host_sys_fw_comp_evm : 0x1a8d0260 Address@host_sys_fw_comp_debug : 0x1a8e0260 Address@secenc_fw_comp_fc1 : 0x50210260 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | error_addr_lwr |
|
||
| fw_comp_edr_tau |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810264 Address@host_sys_fw_comp_dbgperi : 0x1a820264 Address@host_sys_fw_comp_aonperi : 0x1a830264 Address@host_sys_fw_comp_envm : 0x1a840264 Address@host_sys_fw_comp_cvm : 0x1a850264 Address@host_sys_fw_comp_hostcpu : 0x1a860264 Address@host_sys_fw_comp_com : 0x1a870264 Address@host_sys_fw_comp_mot : 0x1a880264 Address@host_sys_fw_comp_hperi_slv : 0x1a890264 Address@host_sys_fw_comp_sms_slv : 0x1a8a0264 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0264 Address@host_sys_fw_comp_sms_mst : 0x1a8c0264 Address@host_sys_fw_comp_evm : 0x1a8d0264 Address@host_sys_fw_comp_debug : 0x1a8e0264 Address@secenc_fw_comp_fc1 : 0x50210264 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | error_addr_upr |
|
||
| fw_comp_edr_tp |
|
|||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810268 Address@host_sys_fw_comp_dbgperi : 0x1a820268 Address@host_sys_fw_comp_aonperi : 0x1a830268 Address@host_sys_fw_comp_envm : 0x1a840268 Address@host_sys_fw_comp_cvm : 0x1a850268 Address@host_sys_fw_comp_hostcpu : 0x1a860268 Address@host_sys_fw_comp_com : 0x1a870268 Address@host_sys_fw_comp_mot : 0x1a880268 Address@host_sys_fw_comp_hperi_slv : 0x1a890268 Address@host_sys_fw_comp_sms_slv : 0x1a8a0268 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0268 Address@host_sys_fw_comp_sms_mst : 0x1a8c0268 Address@host_sys_fw_comp_evm : 0x1a8d0268 Address@host_sys_fw_comp_debug : 0x1a8e0268 Address@secenc_fw_comp_fc1 : 0x50210268 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||||||
| 21 | w |
|
||||||
| 20 - 19 | - |
reserved | ||||||
| 18 | instr |
|
||||||
| 17 | priv |
|
||||||
| 16 | ns |
|
||||||
| 15 - 0 | - |
reserved | ||||||
| fw_comp_edr_mid |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a81026c Address@host_sys_fw_comp_dbgperi : 0x1a82026c Address@host_sys_fw_comp_aonperi : 0x1a83026c Address@host_sys_fw_comp_envm : 0x1a84026c Address@host_sys_fw_comp_cvm : 0x1a85026c Address@host_sys_fw_comp_hostcpu : 0x1a86026c Address@host_sys_fw_comp_com : 0x1a87026c Address@host_sys_fw_comp_mot : 0x1a88026c Address@host_sys_fw_comp_hperi_slv : 0x1a89026c Address@host_sys_fw_comp_sms_slv : 0x1a8a026c Address@host_sys_fw_comp_hperi_mst : 0x1a8b026c Address@host_sys_fw_comp_sms_mst : 0x1a8c026c Address@host_sys_fw_comp_evm : 0x1a8d026c Address@host_sys_fw_comp_debug : 0x1a8e026c Address@secenc_fw_comp_fc1 : 0x5021026c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mst_id |
|
||
| fw_comp_edr_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address@host_sys_fw_comp_sysperi : 0x1a810270 Address@host_sys_fw_comp_dbgperi : 0x1a820270 Address@host_sys_fw_comp_aonperi : 0x1a830270 Address@host_sys_fw_comp_envm : 0x1a840270 Address@host_sys_fw_comp_cvm : 0x1a850270 Address@host_sys_fw_comp_hostcpu : 0x1a860270 Address@host_sys_fw_comp_com : 0x1a870270 Address@host_sys_fw_comp_mot : 0x1a880270 Address@host_sys_fw_comp_hperi_slv : 0x1a890270 Address@host_sys_fw_comp_sms_slv : 0x1a8a0270 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0270 Address@host_sys_fw_comp_sms_mst : 0x1a8c0270 Address@host_sys_fw_comp_evm : 0x1a8d0270 Address@host_sys_fw_comp_debug : 0x1a8e0270 Address@secenc_fw_comp_fc1 : 0x50210270 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
last_edr |
|
||||||
| 30 | "0" |
edr_vld |
|
||||||
| 29 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
ack |
|
||||||
| fw_comp_fc_cap0 |
|
||||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fa0 Address@host_sys_fw_comp_dbgperi : 0x1a820fa0 Address@host_sys_fw_comp_aonperi : 0x1a830fa0 Address@host_sys_fw_comp_envm : 0x1a840fa0 Address@host_sys_fw_comp_cvm : 0x1a850fa0 Address@host_sys_fw_comp_hostcpu : 0x1a860fa0 Address@host_sys_fw_comp_com : 0x1a870fa0 Address@host_sys_fw_comp_mot : 0x1a880fa0 Address@host_sys_fw_comp_hperi_slv : 0x1a890fa0 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa0 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa0 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa0 Address@host_sys_fw_comp_evm : 0x1a8d0fa0 Address@host_sys_fw_comp_debug : 0x1a8e0fa0 Address@secenc_fw_comp_fc1 : 0x50210fa0 |
Bits | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | - |
reserved | |||||||||
| 27 - 24 | se_lvl |
|
|||||||||
| 23 - 20 | sre_lvl |
|
|||||||||
| 19 - 16 | lde_lvl |
|
|||||||||
| 15 - 12 | te_lvl |
|
|||||||||
| 11 - 8 | rse_lvl |
|
|||||||||
| 7 - 4 | me_lvl |
|
|||||||||
| 3 - 0 | pe_lvl |
|
|||||||||
| fw_comp_fc_cap1 |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fa4 Address@host_sys_fw_comp_dbgperi : 0x1a820fa4 Address@host_sys_fw_comp_aonperi : 0x1a830fa4 Address@host_sys_fw_comp_envm : 0x1a840fa4 Address@host_sys_fw_comp_cvm : 0x1a850fa4 Address@host_sys_fw_comp_hostcpu : 0x1a860fa4 Address@host_sys_fw_comp_com : 0x1a870fa4 Address@host_sys_fw_comp_mot : 0x1a880fa4 Address@host_sys_fw_comp_hperi_slv : 0x1a890fa4 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa4 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa4 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa4 Address@host_sys_fw_comp_evm : 0x1a8d0fa4 Address@host_sys_fw_comp_debug : 0x1a8e0fa4 Address@secenc_fw_comp_fc1 : 0x50210fa4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_comp_fc_cap1 | |||
| fw_comp_fc_cap2 |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fa8 Address@host_sys_fw_comp_dbgperi : 0x1a820fa8 Address@host_sys_fw_comp_aonperi : 0x1a830fa8 Address@host_sys_fw_comp_envm : 0x1a840fa8 Address@host_sys_fw_comp_cvm : 0x1a850fa8 Address@host_sys_fw_comp_hostcpu : 0x1a860fa8 Address@host_sys_fw_comp_com : 0x1a870fa8 Address@host_sys_fw_comp_mot : 0x1a880fa8 Address@host_sys_fw_comp_hperi_slv : 0x1a890fa8 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa8 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa8 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa8 Address@host_sys_fw_comp_evm : 0x1a8d0fa8 Address@host_sys_fw_comp_debug : 0x1a8e0fa8 Address@secenc_fw_comp_fc1 : 0x50210fa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_comp_fc_cap2 | |||
| fw_comp_fc_cap3 |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fac Address@host_sys_fw_comp_dbgperi : 0x1a820fac Address@host_sys_fw_comp_aonperi : 0x1a830fac Address@host_sys_fw_comp_envm : 0x1a840fac Address@host_sys_fw_comp_cvm : 0x1a850fac Address@host_sys_fw_comp_hostcpu : 0x1a860fac Address@host_sys_fw_comp_com : 0x1a870fac Address@host_sys_fw_comp_mot : 0x1a880fac Address@host_sys_fw_comp_hperi_slv : 0x1a890fac Address@host_sys_fw_comp_sms_slv : 0x1a8a0fac Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fac Address@host_sys_fw_comp_sms_mst : 0x1a8c0fac Address@host_sys_fw_comp_evm : 0x1a8d0fac Address@host_sys_fw_comp_debug : 0x1a8e0fac Address@secenc_fw_comp_fc1 : 0x50210fac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | fw_comp_fc_cap3 | |||
| fw_comp_fc_cfg0 |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fb0 Address@host_sys_fw_comp_dbgperi : 0x1a820fb0 Address@host_sys_fw_comp_aonperi : 0x1a830fb0 Address@host_sys_fw_comp_envm : 0x1a840fb0 Address@host_sys_fw_comp_cvm : 0x1a850fb0 Address@host_sys_fw_comp_hostcpu : 0x1a860fb0 Address@host_sys_fw_comp_com : 0x1a870fb0 Address@host_sys_fw_comp_mot : 0x1a880fb0 Address@host_sys_fw_comp_hperi_slv : 0x1a890fb0 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb0 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb0 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb0 Address@host_sys_fw_comp_evm : 0x1a8d0fb0 Address@host_sys_fw_comp_debug : 0x1a8e0fb0 Address@secenc_fw_comp_fc1 : 0x50210fb0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 5 | - |
reserved | ||
| 4 - 0 | fc_id |
|
||
| fw_comp_fc_cfg1 |
|
||||||||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fb4 Address@host_sys_fw_comp_dbgperi : 0x1a820fb4 Address@host_sys_fw_comp_aonperi : 0x1a830fb4 Address@host_sys_fw_comp_envm : 0x1a840fb4 Address@host_sys_fw_comp_cvm : 0x1a850fb4 Address@host_sys_fw_comp_hostcpu : 0x1a860fb4 Address@host_sys_fw_comp_com : 0x1a870fb4 Address@host_sys_fw_comp_mot : 0x1a880fb4 Address@host_sys_fw_comp_hperi_slv : 0x1a890fb4 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb4 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb4 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb4 Address@host_sys_fw_comp_evm : 0x1a8d0fb4 Address@host_sys_fw_comp_debug : 0x1a8e0fb4 Address@secenc_fw_comp_fc1 : 0x50210fb4 |
Bits | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | - |
reserved | |||||||||||
| 20 | sec_spt |
|
|||||||||||
| 19 | ma_spt |
|
|||||||||||
| 18 | sh_spt |
|
|||||||||||
| 17 | inst_spt |
|
|||||||||||
| 16 | priv_spt |
|
|||||||||||
| 15 - 14 | - |
reserved | |||||||||||
| 13 - 12 | num_mpe |
|
|||||||||||
| 11 | - |
reserved | |||||||||||
| 10 - 8 | mnrs |
|
|||||||||||
| 7 - 0 | num_rgn |
|
|||||||||||
| fw_comp_fc_cfg2 |
|
|||||||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fb8 Address@host_sys_fw_comp_dbgperi : 0x1a820fb8 Address@host_sys_fw_comp_aonperi : 0x1a830fb8 Address@host_sys_fw_comp_envm : 0x1a840fb8 Address@host_sys_fw_comp_cvm : 0x1a850fb8 Address@host_sys_fw_comp_hostcpu : 0x1a860fb8 Address@host_sys_fw_comp_com : 0x1a870fb8 Address@host_sys_fw_comp_mot : 0x1a880fb8 Address@host_sys_fw_comp_hperi_slv : 0x1a890fb8 Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb8 Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb8 Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb8 Address@host_sys_fw_comp_evm : 0x1a8d0fb8 Address@host_sys_fw_comp_debug : 0x1a8e0fb8 Address@secenc_fw_comp_fc1 : 0x50210fb8 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 | single_mst |
|
||||||
| 30 - 21 | - |
reserved | ||||||
| 20 - 13 | prot_size |
|
||||||
| 12 - 8 | mst_id_width |
|
||||||
| 7 | - |
reserved | ||||||
| 6 - 0 | mxrs |
|
||||||
| fw_comp_fc_cfg3 |
|
|||
| R |
Address@host_sys_fw_comp_sysperi : 0x1a810fbc Address@host_sys_fw_comp_dbgperi : 0x1a820fbc Address@host_sys_fw_comp_aonperi : 0x1a830fbc Address@host_sys_fw_comp_envm : 0x1a840fbc Address@host_sys_fw_comp_cvm : 0x1a850fbc Address@host_sys_fw_comp_hostcpu : 0x1a860fbc Address@host_sys_fw_comp_com : 0x1a870fbc Address@host_sys_fw_comp_mot : 0x1a880fbc Address@host_sys_fw_comp_hperi_slv : 0x1a890fbc Address@host_sys_fw_comp_sms_slv : 0x1a8a0fbc Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fbc Address@host_sys_fw_comp_sms_mst : 0x1a8c0fbc Address@host_sys_fw_comp_evm : 0x1a8d0fbc Address@host_sys_fw_comp_debug : 0x1a8e0fbc Address@secenc_fw_comp_fc1 : 0x50210fbc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 6 | - |
reserved | ||
| 5 - 0 | num_fc |
|
||
| mhu_sender_ch0_st |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000000 Address@mot_mhu_sender_mot2app0 : 0x1b010000 Address@com_mhu_sender_com2app0 : 0x1b010000 Address@app_mhu_sender_app2com1 : 0x1b020000 Address@mot_mhu_sender_mot2app1 : 0x1b030000 Address@com_mhu_sender_com2app1 : 0x1b030000 Address@app_mhu_sender_app2mot0 : 0x1b040000 Address@mot_mhu_sender_mot2se0 : 0x1b050000 Address@com_mhu_sender_com2se0 : 0x1b050000 Address@app_mhu_sender_app2mot1 : 0x1b060000 Address@mot_mhu_sender_mot2se1 : 0x1b070000 Address@com_mhu_sender_com2se1 : 0x1b070000 Address@app_mhu_sender_app2se0 : 0x1b800000 Address@app_mhu_sender_app2se1 : 0x1b820000 Address@secenc_mhu_sender_se2app0 : 0x50003000 Address@secenc_mhu_sender_se2app1 : 0x50005000 Address@secenc_mhu_sender_se2com0 : 0x50010000 Address@secenc_mhu_sender_se2com1 : 0x50012000 Address@secenc_mhu_sender_se2mot0 : 0x50014000 Address@secenc_mhu_sender_se2mot1 : 0x50016000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flags |
|
||
| mhu_sender_ch0_set |
|
|||
| W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b00000c Address@mot_mhu_sender_mot2app0 : 0x1b01000c Address@com_mhu_sender_com2app0 : 0x1b01000c Address@app_mhu_sender_app2com1 : 0x1b02000c Address@mot_mhu_sender_mot2app1 : 0x1b03000c Address@com_mhu_sender_com2app1 : 0x1b03000c Address@app_mhu_sender_app2mot0 : 0x1b04000c Address@mot_mhu_sender_mot2se0 : 0x1b05000c Address@com_mhu_sender_com2se0 : 0x1b05000c Address@app_mhu_sender_app2mot1 : 0x1b06000c Address@mot_mhu_sender_mot2se1 : 0x1b07000c Address@com_mhu_sender_com2se1 : 0x1b07000c Address@app_mhu_sender_app2se0 : 0x1b80000c Address@app_mhu_sender_app2se1 : 0x1b82000c Address@secenc_mhu_sender_se2app0 : 0x5000300c Address@secenc_mhu_sender_se2app1 : 0x5000500c Address@secenc_mhu_sender_se2com0 : 0x5001000c Address@secenc_mhu_sender_se2com1 : 0x5001200c Address@secenc_mhu_sender_se2mot0 : 0x5001400c Address@secenc_mhu_sender_se2mot1 : 0x5001600c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flags |
|
|
| mhu_sender_ch0_int_st |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000010 Address@mot_mhu_sender_mot2app0 : 0x1b010010 Address@com_mhu_sender_com2app0 : 0x1b010010 Address@app_mhu_sender_app2com1 : 0x1b020010 Address@mot_mhu_sender_mot2app1 : 0x1b030010 Address@com_mhu_sender_com2app1 : 0x1b030010 Address@app_mhu_sender_app2mot0 : 0x1b040010 Address@mot_mhu_sender_mot2se0 : 0x1b050010 Address@com_mhu_sender_com2se0 : 0x1b050010 Address@app_mhu_sender_app2mot1 : 0x1b060010 Address@mot_mhu_sender_mot2se1 : 0x1b070010 Address@com_mhu_sender_com2se1 : 0x1b070010 Address@app_mhu_sender_app2se0 : 0x1b800010 Address@app_mhu_sender_app2se1 : 0x1b820010 Address@secenc_mhu_sender_se2app0 : 0x50003010 Address@secenc_mhu_sender_se2app1 : 0x50005010 Address@secenc_mhu_sender_se2com0 : 0x50010010 Address@secenc_mhu_sender_se2com1 : 0x50012010 Address@secenc_mhu_sender_se2mot0 : 0x50014010 Address@secenc_mhu_sender_se2mot1 : 0x50016010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | ch_clr |
|
||
| mhu_sender_ch0_int_clr |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000014 Address@mot_mhu_sender_mot2app0 : 0x1b010014 Address@com_mhu_sender_com2app0 : 0x1b010014 Address@app_mhu_sender_app2com1 : 0x1b020014 Address@mot_mhu_sender_mot2app1 : 0x1b030014 Address@com_mhu_sender_com2app1 : 0x1b030014 Address@app_mhu_sender_app2mot0 : 0x1b040014 Address@mot_mhu_sender_mot2se0 : 0x1b050014 Address@com_mhu_sender_com2se0 : 0x1b050014 Address@app_mhu_sender_app2mot1 : 0x1b060014 Address@mot_mhu_sender_mot2se1 : 0x1b070014 Address@com_mhu_sender_com2se1 : 0x1b070014 Address@app_mhu_sender_app2se0 : 0x1b800014 Address@app_mhu_sender_app2se1 : 0x1b820014 Address@secenc_mhu_sender_se2app0 : 0x50003014 Address@secenc_mhu_sender_se2app1 : 0x50005014 Address@secenc_mhu_sender_se2com0 : 0x50010014 Address@secenc_mhu_sender_se2com1 : 0x50012014 Address@secenc_mhu_sender_se2mot0 : 0x50014014 Address@secenc_mhu_sender_se2mot1 : 0x50016014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | ch_clr |
|
||
| mhu_sender_ch0_int_en |
|
|||
| R/W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b000018 Address@mot_mhu_sender_mot2app0 : 0x1b010018 Address@com_mhu_sender_com2app0 : 0x1b010018 Address@app_mhu_sender_app2com1 : 0x1b020018 Address@mot_mhu_sender_mot2app1 : 0x1b030018 Address@com_mhu_sender_com2app1 : 0x1b030018 Address@app_mhu_sender_app2mot0 : 0x1b040018 Address@mot_mhu_sender_mot2se0 : 0x1b050018 Address@com_mhu_sender_com2se0 : 0x1b050018 Address@app_mhu_sender_app2mot1 : 0x1b060018 Address@mot_mhu_sender_mot2se1 : 0x1b070018 Address@com_mhu_sender_com2se1 : 0x1b070018 Address@app_mhu_sender_app2se0 : 0x1b800018 Address@app_mhu_sender_app2se1 : 0x1b820018 Address@secenc_mhu_sender_se2app0 : 0x50003018 Address@secenc_mhu_sender_se2app1 : 0x50005018 Address@secenc_mhu_sender_se2com0 : 0x50010018 Address@secenc_mhu_sender_se2com1 : 0x50012018 Address@secenc_mhu_sender_se2mot0 : 0x50014018 Address@secenc_mhu_sender_se2mot1 : 0x50016018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ch_clr |
|
|
| mhu_sender_ch1_st |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000020 Address@mot_mhu_sender_mot2app0 : 0x1b010020 Address@com_mhu_sender_com2app0 : 0x1b010020 Address@app_mhu_sender_app2com1 : 0x1b020020 Address@mot_mhu_sender_mot2app1 : 0x1b030020 Address@com_mhu_sender_com2app1 : 0x1b030020 Address@app_mhu_sender_app2mot0 : 0x1b040020 Address@mot_mhu_sender_mot2se0 : 0x1b050020 Address@com_mhu_sender_com2se0 : 0x1b050020 Address@app_mhu_sender_app2mot1 : 0x1b060020 Address@mot_mhu_sender_mot2se1 : 0x1b070020 Address@com_mhu_sender_com2se1 : 0x1b070020 Address@app_mhu_sender_app2se0 : 0x1b800020 Address@app_mhu_sender_app2se1 : 0x1b820020 Address@secenc_mhu_sender_se2app0 : 0x50003020 Address@secenc_mhu_sender_se2app1 : 0x50005020 Address@secenc_mhu_sender_se2com0 : 0x50010020 Address@secenc_mhu_sender_se2com1 : 0x50012020 Address@secenc_mhu_sender_se2mot0 : 0x50014020 Address@secenc_mhu_sender_se2mot1 : 0x50016020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flags |
|
||
| mhu_sender_ch1_set |
|
|||
| W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b00002c Address@mot_mhu_sender_mot2app0 : 0x1b01002c Address@com_mhu_sender_com2app0 : 0x1b01002c Address@app_mhu_sender_app2com1 : 0x1b02002c Address@mot_mhu_sender_mot2app1 : 0x1b03002c Address@com_mhu_sender_com2app1 : 0x1b03002c Address@app_mhu_sender_app2mot0 : 0x1b04002c Address@mot_mhu_sender_mot2se0 : 0x1b05002c Address@com_mhu_sender_com2se0 : 0x1b05002c Address@app_mhu_sender_app2mot1 : 0x1b06002c Address@mot_mhu_sender_mot2se1 : 0x1b07002c Address@com_mhu_sender_com2se1 : 0x1b07002c Address@app_mhu_sender_app2se0 : 0x1b80002c Address@app_mhu_sender_app2se1 : 0x1b82002c Address@secenc_mhu_sender_se2app0 : 0x5000302c Address@secenc_mhu_sender_se2app1 : 0x5000502c Address@secenc_mhu_sender_se2com0 : 0x5001002c Address@secenc_mhu_sender_se2com1 : 0x5001202c Address@secenc_mhu_sender_se2mot0 : 0x5001402c Address@secenc_mhu_sender_se2mot1 : 0x5001602c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flags |
|
|
| mhu_sender_ch1_int_st |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000030 Address@mot_mhu_sender_mot2app0 : 0x1b010030 Address@com_mhu_sender_com2app0 : 0x1b010030 Address@app_mhu_sender_app2com1 : 0x1b020030 Address@mot_mhu_sender_mot2app1 : 0x1b030030 Address@com_mhu_sender_com2app1 : 0x1b030030 Address@app_mhu_sender_app2mot0 : 0x1b040030 Address@mot_mhu_sender_mot2se0 : 0x1b050030 Address@com_mhu_sender_com2se0 : 0x1b050030 Address@app_mhu_sender_app2mot1 : 0x1b060030 Address@mot_mhu_sender_mot2se1 : 0x1b070030 Address@com_mhu_sender_com2se1 : 0x1b070030 Address@app_mhu_sender_app2se0 : 0x1b800030 Address@app_mhu_sender_app2se1 : 0x1b820030 Address@secenc_mhu_sender_se2app0 : 0x50003030 Address@secenc_mhu_sender_se2app1 : 0x50005030 Address@secenc_mhu_sender_se2com0 : 0x50010030 Address@secenc_mhu_sender_se2com1 : 0x50012030 Address@secenc_mhu_sender_se2mot0 : 0x50014030 Address@secenc_mhu_sender_se2mot1 : 0x50016030 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | ch_clr |
|
||
| mhu_sender_ch1_int_clr |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000034 Address@mot_mhu_sender_mot2app0 : 0x1b010034 Address@com_mhu_sender_com2app0 : 0x1b010034 Address@app_mhu_sender_app2com1 : 0x1b020034 Address@mot_mhu_sender_mot2app1 : 0x1b030034 Address@com_mhu_sender_com2app1 : 0x1b030034 Address@app_mhu_sender_app2mot0 : 0x1b040034 Address@mot_mhu_sender_mot2se0 : 0x1b050034 Address@com_mhu_sender_com2se0 : 0x1b050034 Address@app_mhu_sender_app2mot1 : 0x1b060034 Address@mot_mhu_sender_mot2se1 : 0x1b070034 Address@com_mhu_sender_com2se1 : 0x1b070034 Address@app_mhu_sender_app2se0 : 0x1b800034 Address@app_mhu_sender_app2se1 : 0x1b820034 Address@secenc_mhu_sender_se2app0 : 0x50003034 Address@secenc_mhu_sender_se2app1 : 0x50005034 Address@secenc_mhu_sender_se2com0 : 0x50010034 Address@secenc_mhu_sender_se2com1 : 0x50012034 Address@secenc_mhu_sender_se2mot0 : 0x50014034 Address@secenc_mhu_sender_se2mot1 : 0x50016034 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | ch_clr |
|
||
| mhu_sender_ch1_int_en |
|
|||
| R/W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b000038 Address@mot_mhu_sender_mot2app0 : 0x1b010038 Address@com_mhu_sender_com2app0 : 0x1b010038 Address@app_mhu_sender_app2com1 : 0x1b020038 Address@mot_mhu_sender_mot2app1 : 0x1b030038 Address@com_mhu_sender_com2app1 : 0x1b030038 Address@app_mhu_sender_app2mot0 : 0x1b040038 Address@mot_mhu_sender_mot2se0 : 0x1b050038 Address@com_mhu_sender_com2se0 : 0x1b050038 Address@app_mhu_sender_app2mot1 : 0x1b060038 Address@mot_mhu_sender_mot2se1 : 0x1b070038 Address@com_mhu_sender_com2se1 : 0x1b070038 Address@app_mhu_sender_app2se0 : 0x1b800038 Address@app_mhu_sender_app2se1 : 0x1b820038 Address@secenc_mhu_sender_se2app0 : 0x50003038 Address@secenc_mhu_sender_se2app1 : 0x50005038 Address@secenc_mhu_sender_se2com0 : 0x50010038 Address@secenc_mhu_sender_se2com1 : 0x50012038 Address@secenc_mhu_sender_se2mot0 : 0x50014038 Address@secenc_mhu_sender_se2mot1 : 0x50016038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ch_clr |
|
|
| mhu_sender_mhu_cfg |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000f80 Address@mot_mhu_sender_mot2app0 : 0x1b010f80 Address@com_mhu_sender_com2app0 : 0x1b010f80 Address@app_mhu_sender_app2com1 : 0x1b020f80 Address@mot_mhu_sender_mot2app1 : 0x1b030f80 Address@com_mhu_sender_com2app1 : 0x1b030f80 Address@app_mhu_sender_app2mot0 : 0x1b040f80 Address@mot_mhu_sender_mot2se0 : 0x1b050f80 Address@com_mhu_sender_com2se0 : 0x1b050f80 Address@app_mhu_sender_app2mot1 : 0x1b060f80 Address@mot_mhu_sender_mot2se1 : 0x1b070f80 Address@com_mhu_sender_com2se1 : 0x1b070f80 Address@app_mhu_sender_app2se0 : 0x1b800f80 Address@app_mhu_sender_app2se1 : 0x1b820f80 Address@secenc_mhu_sender_se2app0 : 0x50003f80 Address@secenc_mhu_sender_se2app1 : 0x50005f80 Address@secenc_mhu_sender_se2com0 : 0x50010f80 Address@secenc_mhu_sender_se2com1 : 0x50012f80 Address@secenc_mhu_sender_se2mot0 : 0x50014f80 Address@secenc_mhu_sender_se2mot1 : 0x50016f80 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||
| 6 - 0 | num_ch |
|
||
| mhu_sender_resp_cfg |
|
|||
| R/W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b000f84 Address@mot_mhu_sender_mot2app0 : 0x1b010f84 Address@com_mhu_sender_com2app0 : 0x1b010f84 Address@app_mhu_sender_app2com1 : 0x1b020f84 Address@mot_mhu_sender_mot2app1 : 0x1b030f84 Address@com_mhu_sender_com2app1 : 0x1b030f84 Address@app_mhu_sender_app2mot0 : 0x1b040f84 Address@mot_mhu_sender_mot2se0 : 0x1b050f84 Address@com_mhu_sender_com2se0 : 0x1b050f84 Address@app_mhu_sender_app2mot1 : 0x1b060f84 Address@mot_mhu_sender_mot2se1 : 0x1b070f84 Address@com_mhu_sender_com2se1 : 0x1b070f84 Address@app_mhu_sender_app2se0 : 0x1b800f84 Address@app_mhu_sender_app2se1 : 0x1b820f84 Address@secenc_mhu_sender_se2app0 : 0x50003f84 Address@secenc_mhu_sender_se2app1 : 0x50005f84 Address@secenc_mhu_sender_se2com0 : 0x50010f84 Address@secenc_mhu_sender_se2com1 : 0x50012f84 Address@secenc_mhu_sender_se2mot0 : 0x50014f84 Address@secenc_mhu_sender_se2mot1 : 0x50016f84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
nr_resp |
|
|
| mhu_sender_access_request |
|
|||
| R/W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b000f88 Address@mot_mhu_sender_mot2app0 : 0x1b010f88 Address@com_mhu_sender_com2app0 : 0x1b010f88 Address@app_mhu_sender_app2com1 : 0x1b020f88 Address@mot_mhu_sender_mot2app1 : 0x1b030f88 Address@com_mhu_sender_com2app1 : 0x1b030f88 Address@app_mhu_sender_app2mot0 : 0x1b040f88 Address@mot_mhu_sender_mot2se0 : 0x1b050f88 Address@com_mhu_sender_com2se0 : 0x1b050f88 Address@app_mhu_sender_app2mot1 : 0x1b060f88 Address@mot_mhu_sender_mot2se1 : 0x1b070f88 Address@com_mhu_sender_com2se1 : 0x1b070f88 Address@app_mhu_sender_app2se0 : 0x1b800f88 Address@app_mhu_sender_app2se1 : 0x1b820f88 Address@secenc_mhu_sender_se2app0 : 0x50003f88 Address@secenc_mhu_sender_se2app1 : 0x50005f88 Address@secenc_mhu_sender_se2com0 : 0x50010f88 Address@secenc_mhu_sender_se2com1 : 0x50012f88 Address@secenc_mhu_sender_se2mot0 : 0x50014f88 Address@secenc_mhu_sender_se2mot1 : 0x50016f88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
acc_req |
|
|
| mhu_sender_access_ready |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000f8c Address@mot_mhu_sender_mot2app0 : 0x1b010f8c Address@com_mhu_sender_com2app0 : 0x1b010f8c Address@app_mhu_sender_app2com1 : 0x1b020f8c Address@mot_mhu_sender_mot2app1 : 0x1b030f8c Address@com_mhu_sender_com2app1 : 0x1b030f8c Address@app_mhu_sender_app2mot0 : 0x1b040f8c Address@mot_mhu_sender_mot2se0 : 0x1b050f8c Address@com_mhu_sender_com2se0 : 0x1b050f8c Address@app_mhu_sender_app2mot1 : 0x1b060f8c Address@mot_mhu_sender_mot2se1 : 0x1b070f8c Address@com_mhu_sender_com2se1 : 0x1b070f8c Address@app_mhu_sender_app2se0 : 0x1b800f8c Address@app_mhu_sender_app2se1 : 0x1b820f8c Address@secenc_mhu_sender_se2app0 : 0x50003f8c Address@secenc_mhu_sender_se2app1 : 0x50005f8c Address@secenc_mhu_sender_se2com0 : 0x50010f8c Address@secenc_mhu_sender_se2com1 : 0x50012f8c Address@secenc_mhu_sender_se2mot0 : 0x50014f8c Address@secenc_mhu_sender_se2mot1 : 0x50016f8c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | acc_rdy |
|
||
| mhu_sender_int_st |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000f90 Address@mot_mhu_sender_mot2app0 : 0x1b010f90 Address@com_mhu_sender_com2app0 : 0x1b010f90 Address@app_mhu_sender_app2com1 : 0x1b020f90 Address@mot_mhu_sender_mot2app1 : 0x1b030f90 Address@com_mhu_sender_com2app1 : 0x1b030f90 Address@app_mhu_sender_app2mot0 : 0x1b040f90 Address@mot_mhu_sender_mot2se0 : 0x1b050f90 Address@com_mhu_sender_com2se0 : 0x1b050f90 Address@app_mhu_sender_app2mot1 : 0x1b060f90 Address@mot_mhu_sender_mot2se1 : 0x1b070f90 Address@com_mhu_sender_com2se1 : 0x1b070f90 Address@app_mhu_sender_app2se0 : 0x1b800f90 Address@app_mhu_sender_app2se1 : 0x1b820f90 Address@secenc_mhu_sender_se2app0 : 0x50003f90 Address@secenc_mhu_sender_se2app1 : 0x50005f90 Address@secenc_mhu_sender_se2com0 : 0x50010f90 Address@secenc_mhu_sender_se2com1 : 0x50012f90 Address@secenc_mhu_sender_se2mot0 : 0x50014f90 Address@secenc_mhu_sender_se2mot1 : 0x50016f90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | chcomb |
|
||
| 1 | r2nr |
|
||
| 0 | nr2r |
|
||
| mhu_sender_int_clr |
|
|||
| W |
0x00000000 |
Address@app_mhu_sender_app2com0 : 0x1b000f94 Address@mot_mhu_sender_mot2app0 : 0x1b010f94 Address@com_mhu_sender_com2app0 : 0x1b010f94 Address@app_mhu_sender_app2com1 : 0x1b020f94 Address@mot_mhu_sender_mot2app1 : 0x1b030f94 Address@com_mhu_sender_com2app1 : 0x1b030f94 Address@app_mhu_sender_app2mot0 : 0x1b040f94 Address@mot_mhu_sender_mot2se0 : 0x1b050f94 Address@com_mhu_sender_com2se0 : 0x1b050f94 Address@app_mhu_sender_app2mot1 : 0x1b060f94 Address@mot_mhu_sender_mot2se1 : 0x1b070f94 Address@com_mhu_sender_com2se1 : 0x1b070f94 Address@app_mhu_sender_app2se0 : 0x1b800f94 Address@app_mhu_sender_app2se1 : 0x1b820f94 Address@secenc_mhu_sender_se2app0 : 0x50003f94 Address@secenc_mhu_sender_se2app1 : 0x50005f94 Address@secenc_mhu_sender_se2com0 : 0x50010f94 Address@secenc_mhu_sender_se2com1 : 0x50012f94 Address@secenc_mhu_sender_se2mot0 : 0x50014f94 Address@secenc_mhu_sender_se2mot1 : 0x50016f94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
r2nr |
|
|
| 0 | "0" |
nr2r |
|
|
| mhu_sender_int_en |
|
|||
| R/W |
0x00000004 |
Address@app_mhu_sender_app2com0 : 0x1b000f98 Address@mot_mhu_sender_mot2app0 : 0x1b010f98 Address@com_mhu_sender_com2app0 : 0x1b010f98 Address@app_mhu_sender_app2com1 : 0x1b020f98 Address@mot_mhu_sender_mot2app1 : 0x1b030f98 Address@com_mhu_sender_com2app1 : 0x1b030f98 Address@app_mhu_sender_app2mot0 : 0x1b040f98 Address@mot_mhu_sender_mot2se0 : 0x1b050f98 Address@com_mhu_sender_com2se0 : 0x1b050f98 Address@app_mhu_sender_app2mot1 : 0x1b060f98 Address@mot_mhu_sender_mot2se1 : 0x1b070f98 Address@com_mhu_sender_com2se1 : 0x1b070f98 Address@app_mhu_sender_app2se0 : 0x1b800f98 Address@app_mhu_sender_app2se1 : 0x1b820f98 Address@secenc_mhu_sender_se2app0 : 0x50003f98 Address@secenc_mhu_sender_se2app1 : 0x50005f98 Address@secenc_mhu_sender_se2com0 : 0x50010f98 Address@secenc_mhu_sender_se2com1 : 0x50012f98 Address@secenc_mhu_sender_se2mot0 : 0x50014f98 Address@secenc_mhu_sender_se2mot1 : 0x50016f98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "1" |
chcomb |
|
|
| 1 | "0" |
r2nr |
|
|
| 0 | "0" |
nr2r |
|
|
| mhu_sender_chcomb_int_st0 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fa0 Address@mot_mhu_sender_mot2app0 : 0x1b010fa0 Address@com_mhu_sender_com2app0 : 0x1b010fa0 Address@app_mhu_sender_app2com1 : 0x1b020fa0 Address@mot_mhu_sender_mot2app1 : 0x1b030fa0 Address@com_mhu_sender_com2app1 : 0x1b030fa0 Address@app_mhu_sender_app2mot0 : 0x1b040fa0 Address@mot_mhu_sender_mot2se0 : 0x1b050fa0 Address@com_mhu_sender_com2se0 : 0x1b050fa0 Address@app_mhu_sender_app2mot1 : 0x1b060fa0 Address@mot_mhu_sender_mot2se1 : 0x1b070fa0 Address@com_mhu_sender_com2se1 : 0x1b070fa0 Address@app_mhu_sender_app2se0 : 0x1b800fa0 Address@app_mhu_sender_app2se1 : 0x1b820fa0 Address@secenc_mhu_sender_se2app0 : 0x50003fa0 Address@secenc_mhu_sender_se2app1 : 0x50005fa0 Address@secenc_mhu_sender_se2com0 : 0x50010fa0 Address@secenc_mhu_sender_se2com1 : 0x50012fa0 Address@secenc_mhu_sender_se2mot0 : 0x50014fa0 Address@secenc_mhu_sender_se2mot1 : 0x50016fa0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st0 |
|
||
| mhu_sender_chcomb_int_st1 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fa4 Address@mot_mhu_sender_mot2app0 : 0x1b010fa4 Address@com_mhu_sender_com2app0 : 0x1b010fa4 Address@app_mhu_sender_app2com1 : 0x1b020fa4 Address@mot_mhu_sender_mot2app1 : 0x1b030fa4 Address@com_mhu_sender_com2app1 : 0x1b030fa4 Address@app_mhu_sender_app2mot0 : 0x1b040fa4 Address@mot_mhu_sender_mot2se0 : 0x1b050fa4 Address@com_mhu_sender_com2se0 : 0x1b050fa4 Address@app_mhu_sender_app2mot1 : 0x1b060fa4 Address@mot_mhu_sender_mot2se1 : 0x1b070fa4 Address@com_mhu_sender_com2se1 : 0x1b070fa4 Address@app_mhu_sender_app2se0 : 0x1b800fa4 Address@app_mhu_sender_app2se1 : 0x1b820fa4 Address@secenc_mhu_sender_se2app0 : 0x50003fa4 Address@secenc_mhu_sender_se2app1 : 0x50005fa4 Address@secenc_mhu_sender_se2com0 : 0x50010fa4 Address@secenc_mhu_sender_se2com1 : 0x50012fa4 Address@secenc_mhu_sender_se2mot0 : 0x50014fa4 Address@secenc_mhu_sender_se2mot1 : 0x50016fa4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st1 |
|
||
| mhu_sender_chcomb_int_st2 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fa8 Address@mot_mhu_sender_mot2app0 : 0x1b010fa8 Address@com_mhu_sender_com2app0 : 0x1b010fa8 Address@app_mhu_sender_app2com1 : 0x1b020fa8 Address@mot_mhu_sender_mot2app1 : 0x1b030fa8 Address@com_mhu_sender_com2app1 : 0x1b030fa8 Address@app_mhu_sender_app2mot0 : 0x1b040fa8 Address@mot_mhu_sender_mot2se0 : 0x1b050fa8 Address@com_mhu_sender_com2se0 : 0x1b050fa8 Address@app_mhu_sender_app2mot1 : 0x1b060fa8 Address@mot_mhu_sender_mot2se1 : 0x1b070fa8 Address@com_mhu_sender_com2se1 : 0x1b070fa8 Address@app_mhu_sender_app2se0 : 0x1b800fa8 Address@app_mhu_sender_app2se1 : 0x1b820fa8 Address@secenc_mhu_sender_se2app0 : 0x50003fa8 Address@secenc_mhu_sender_se2app1 : 0x50005fa8 Address@secenc_mhu_sender_se2com0 : 0x50010fa8 Address@secenc_mhu_sender_se2com1 : 0x50012fa8 Address@secenc_mhu_sender_se2mot0 : 0x50014fa8 Address@secenc_mhu_sender_se2mot1 : 0x50016fa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st2 |
|
||
| mhu_sender_chcomb_int_st3 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fac Address@mot_mhu_sender_mot2app0 : 0x1b010fac Address@com_mhu_sender_com2app0 : 0x1b010fac Address@app_mhu_sender_app2com1 : 0x1b020fac Address@mot_mhu_sender_mot2app1 : 0x1b030fac Address@com_mhu_sender_com2app1 : 0x1b030fac Address@app_mhu_sender_app2mot0 : 0x1b040fac Address@mot_mhu_sender_mot2se0 : 0x1b050fac Address@com_mhu_sender_com2se0 : 0x1b050fac Address@app_mhu_sender_app2mot1 : 0x1b060fac Address@mot_mhu_sender_mot2se1 : 0x1b070fac Address@com_mhu_sender_com2se1 : 0x1b070fac Address@app_mhu_sender_app2se0 : 0x1b800fac Address@app_mhu_sender_app2se1 : 0x1b820fac Address@secenc_mhu_sender_se2app0 : 0x50003fac Address@secenc_mhu_sender_se2app1 : 0x50005fac Address@secenc_mhu_sender_se2com0 : 0x50010fac Address@secenc_mhu_sender_se2com1 : 0x50012fac Address@secenc_mhu_sender_se2mot0 : 0x50014fac Address@secenc_mhu_sender_se2mot1 : 0x50016fac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st3 |
|
||
| mhu_sender_iidr |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fc8 Address@mot_mhu_sender_mot2app0 : 0x1b010fc8 Address@com_mhu_sender_com2app0 : 0x1b010fc8 Address@app_mhu_sender_app2com1 : 0x1b020fc8 Address@mot_mhu_sender_mot2app1 : 0x1b030fc8 Address@com_mhu_sender_com2app1 : 0x1b030fc8 Address@app_mhu_sender_app2mot0 : 0x1b040fc8 Address@mot_mhu_sender_mot2se0 : 0x1b050fc8 Address@com_mhu_sender_com2se0 : 0x1b050fc8 Address@app_mhu_sender_app2mot1 : 0x1b060fc8 Address@mot_mhu_sender_mot2se1 : 0x1b070fc8 Address@com_mhu_sender_com2se1 : 0x1b070fc8 Address@app_mhu_sender_app2se0 : 0x1b800fc8 Address@app_mhu_sender_app2se1 : 0x1b820fc8 Address@secenc_mhu_sender_se2app0 : 0x50003fc8 Address@secenc_mhu_sender_se2app1 : 0x50005fc8 Address@secenc_mhu_sender_se2com0 : 0x50010fc8 Address@secenc_mhu_sender_se2com1 : 0x50012fc8 Address@secenc_mhu_sender_se2mot0 : 0x50014fc8 Address@secenc_mhu_sender_se2mot1 : 0x50016fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| mhu_sender_aidr |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fcc Address@mot_mhu_sender_mot2app0 : 0x1b010fcc Address@com_mhu_sender_com2app0 : 0x1b010fcc Address@app_mhu_sender_app2com1 : 0x1b020fcc Address@mot_mhu_sender_mot2app1 : 0x1b030fcc Address@com_mhu_sender_com2app1 : 0x1b030fcc Address@app_mhu_sender_app2mot0 : 0x1b040fcc Address@mot_mhu_sender_mot2se0 : 0x1b050fcc Address@com_mhu_sender_com2se0 : 0x1b050fcc Address@app_mhu_sender_app2mot1 : 0x1b060fcc Address@mot_mhu_sender_mot2se1 : 0x1b070fcc Address@com_mhu_sender_com2se1 : 0x1b070fcc Address@app_mhu_sender_app2se0 : 0x1b800fcc Address@app_mhu_sender_app2se1 : 0x1b820fcc Address@secenc_mhu_sender_se2app0 : 0x50003fcc Address@secenc_mhu_sender_se2app1 : 0x50005fcc Address@secenc_mhu_sender_se2com0 : 0x50010fcc Address@secenc_mhu_sender_se2com1 : 0x50012fcc Address@secenc_mhu_sender_se2mot0 : 0x50014fcc Address@secenc_mhu_sender_se2mot1 : 0x50016fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | arch_major_rev |
|
||
| 3 - 0 | arch_minor_rev |
|
||
| mhu_sender_pid4 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fd0 Address@mot_mhu_sender_mot2app0 : 0x1b010fd0 Address@com_mhu_sender_com2app0 : 0x1b010fd0 Address@app_mhu_sender_app2com1 : 0x1b020fd0 Address@mot_mhu_sender_mot2app1 : 0x1b030fd0 Address@com_mhu_sender_com2app1 : 0x1b030fd0 Address@app_mhu_sender_app2mot0 : 0x1b040fd0 Address@mot_mhu_sender_mot2se0 : 0x1b050fd0 Address@com_mhu_sender_com2se0 : 0x1b050fd0 Address@app_mhu_sender_app2mot1 : 0x1b060fd0 Address@mot_mhu_sender_mot2se1 : 0x1b070fd0 Address@com_mhu_sender_com2se1 : 0x1b070fd0 Address@app_mhu_sender_app2se0 : 0x1b800fd0 Address@app_mhu_sender_app2se1 : 0x1b820fd0 Address@secenc_mhu_sender_se2app0 : 0x50003fd0 Address@secenc_mhu_sender_se2app1 : 0x50005fd0 Address@secenc_mhu_sender_se2com0 : 0x50010fd0 Address@secenc_mhu_sender_se2com1 : 0x50012fd0 Address@secenc_mhu_sender_se2mot0 : 0x50014fd0 Address@secenc_mhu_sender_se2mot1 : 0x50016fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| mhu_sender_pid5 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fd4 Address@mot_mhu_sender_mot2app0 : 0x1b010fd4 Address@com_mhu_sender_com2app0 : 0x1b010fd4 Address@app_mhu_sender_app2com1 : 0x1b020fd4 Address@mot_mhu_sender_mot2app1 : 0x1b030fd4 Address@com_mhu_sender_com2app1 : 0x1b030fd4 Address@app_mhu_sender_app2mot0 : 0x1b040fd4 Address@mot_mhu_sender_mot2se0 : 0x1b050fd4 Address@com_mhu_sender_com2se0 : 0x1b050fd4 Address@app_mhu_sender_app2mot1 : 0x1b060fd4 Address@mot_mhu_sender_mot2se1 : 0x1b070fd4 Address@com_mhu_sender_com2se1 : 0x1b070fd4 Address@app_mhu_sender_app2se0 : 0x1b800fd4 Address@app_mhu_sender_app2se1 : 0x1b820fd4 Address@secenc_mhu_sender_se2app0 : 0x50003fd4 Address@secenc_mhu_sender_se2app1 : 0x50005fd4 Address@secenc_mhu_sender_se2com0 : 0x50010fd4 Address@secenc_mhu_sender_se2com1 : 0x50012fd4 Address@secenc_mhu_sender_se2mot0 : 0x50014fd4 Address@secenc_mhu_sender_se2mot1 : 0x50016fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_sender_pid5 | |||
| mhu_sender_pid6 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fd8 Address@mot_mhu_sender_mot2app0 : 0x1b010fd8 Address@com_mhu_sender_com2app0 : 0x1b010fd8 Address@app_mhu_sender_app2com1 : 0x1b020fd8 Address@mot_mhu_sender_mot2app1 : 0x1b030fd8 Address@com_mhu_sender_com2app1 : 0x1b030fd8 Address@app_mhu_sender_app2mot0 : 0x1b040fd8 Address@mot_mhu_sender_mot2se0 : 0x1b050fd8 Address@com_mhu_sender_com2se0 : 0x1b050fd8 Address@app_mhu_sender_app2mot1 : 0x1b060fd8 Address@mot_mhu_sender_mot2se1 : 0x1b070fd8 Address@com_mhu_sender_com2se1 : 0x1b070fd8 Address@app_mhu_sender_app2se0 : 0x1b800fd8 Address@app_mhu_sender_app2se1 : 0x1b820fd8 Address@secenc_mhu_sender_se2app0 : 0x50003fd8 Address@secenc_mhu_sender_se2app1 : 0x50005fd8 Address@secenc_mhu_sender_se2com0 : 0x50010fd8 Address@secenc_mhu_sender_se2com1 : 0x50012fd8 Address@secenc_mhu_sender_se2mot0 : 0x50014fd8 Address@secenc_mhu_sender_se2mot1 : 0x50016fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_sender_pid6 | |||
| mhu_sender_pid7 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fdc Address@mot_mhu_sender_mot2app0 : 0x1b010fdc Address@com_mhu_sender_com2app0 : 0x1b010fdc Address@app_mhu_sender_app2com1 : 0x1b020fdc Address@mot_mhu_sender_mot2app1 : 0x1b030fdc Address@com_mhu_sender_com2app1 : 0x1b030fdc Address@app_mhu_sender_app2mot0 : 0x1b040fdc Address@mot_mhu_sender_mot2se0 : 0x1b050fdc Address@com_mhu_sender_com2se0 : 0x1b050fdc Address@app_mhu_sender_app2mot1 : 0x1b060fdc Address@mot_mhu_sender_mot2se1 : 0x1b070fdc Address@com_mhu_sender_com2se1 : 0x1b070fdc Address@app_mhu_sender_app2se0 : 0x1b800fdc Address@app_mhu_sender_app2se1 : 0x1b820fdc Address@secenc_mhu_sender_se2app0 : 0x50003fdc Address@secenc_mhu_sender_se2app1 : 0x50005fdc Address@secenc_mhu_sender_se2com0 : 0x50010fdc Address@secenc_mhu_sender_se2com1 : 0x50012fdc Address@secenc_mhu_sender_se2mot0 : 0x50014fdc Address@secenc_mhu_sender_se2mot1 : 0x50016fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_sender_pid7 | |||
| mhu_sender_pid0 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fe0 Address@mot_mhu_sender_mot2app0 : 0x1b010fe0 Address@com_mhu_sender_com2app0 : 0x1b010fe0 Address@app_mhu_sender_app2com1 : 0x1b020fe0 Address@mot_mhu_sender_mot2app1 : 0x1b030fe0 Address@com_mhu_sender_com2app1 : 0x1b030fe0 Address@app_mhu_sender_app2mot0 : 0x1b040fe0 Address@mot_mhu_sender_mot2se0 : 0x1b050fe0 Address@com_mhu_sender_com2se0 : 0x1b050fe0 Address@app_mhu_sender_app2mot1 : 0x1b060fe0 Address@mot_mhu_sender_mot2se1 : 0x1b070fe0 Address@com_mhu_sender_com2se1 : 0x1b070fe0 Address@app_mhu_sender_app2se0 : 0x1b800fe0 Address@app_mhu_sender_app2se1 : 0x1b820fe0 Address@secenc_mhu_sender_se2app0 : 0x50003fe0 Address@secenc_mhu_sender_se2app1 : 0x50005fe0 Address@secenc_mhu_sender_se2com0 : 0x50010fe0 Address@secenc_mhu_sender_se2com1 : 0x50012fe0 Address@secenc_mhu_sender_se2mot0 : 0x50014fe0 Address@secenc_mhu_sender_se2mot1 : 0x50016fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| mhu_sender_pid1 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fe4 Address@mot_mhu_sender_mot2app0 : 0x1b010fe4 Address@com_mhu_sender_com2app0 : 0x1b010fe4 Address@app_mhu_sender_app2com1 : 0x1b020fe4 Address@mot_mhu_sender_mot2app1 : 0x1b030fe4 Address@com_mhu_sender_com2app1 : 0x1b030fe4 Address@app_mhu_sender_app2mot0 : 0x1b040fe4 Address@mot_mhu_sender_mot2se0 : 0x1b050fe4 Address@com_mhu_sender_com2se0 : 0x1b050fe4 Address@app_mhu_sender_app2mot1 : 0x1b060fe4 Address@mot_mhu_sender_mot2se1 : 0x1b070fe4 Address@com_mhu_sender_com2se1 : 0x1b070fe4 Address@app_mhu_sender_app2se0 : 0x1b800fe4 Address@app_mhu_sender_app2se1 : 0x1b820fe4 Address@secenc_mhu_sender_se2app0 : 0x50003fe4 Address@secenc_mhu_sender_se2app1 : 0x50005fe4 Address@secenc_mhu_sender_se2com0 : 0x50010fe4 Address@secenc_mhu_sender_se2com1 : 0x50012fe4 Address@secenc_mhu_sender_se2mot0 : 0x50014fe4 Address@secenc_mhu_sender_se2mot1 : 0x50016fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| mhu_sender_pid2 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fe8 Address@mot_mhu_sender_mot2app0 : 0x1b010fe8 Address@com_mhu_sender_com2app0 : 0x1b010fe8 Address@app_mhu_sender_app2com1 : 0x1b020fe8 Address@mot_mhu_sender_mot2app1 : 0x1b030fe8 Address@com_mhu_sender_com2app1 : 0x1b030fe8 Address@app_mhu_sender_app2mot0 : 0x1b040fe8 Address@mot_mhu_sender_mot2se0 : 0x1b050fe8 Address@com_mhu_sender_com2se0 : 0x1b050fe8 Address@app_mhu_sender_app2mot1 : 0x1b060fe8 Address@mot_mhu_sender_mot2se1 : 0x1b070fe8 Address@com_mhu_sender_com2se1 : 0x1b070fe8 Address@app_mhu_sender_app2se0 : 0x1b800fe8 Address@app_mhu_sender_app2se1 : 0x1b820fe8 Address@secenc_mhu_sender_se2app0 : 0x50003fe8 Address@secenc_mhu_sender_se2app1 : 0x50005fe8 Address@secenc_mhu_sender_se2com0 : 0x50010fe8 Address@secenc_mhu_sender_se2com1 : 0x50012fe8 Address@secenc_mhu_sender_se2mot0 : 0x50014fe8 Address@secenc_mhu_sender_se2mot1 : 0x50016fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| mhu_sender_pid3 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000fec Address@mot_mhu_sender_mot2app0 : 0x1b010fec Address@com_mhu_sender_com2app0 : 0x1b010fec Address@app_mhu_sender_app2com1 : 0x1b020fec Address@mot_mhu_sender_mot2app1 : 0x1b030fec Address@com_mhu_sender_com2app1 : 0x1b030fec Address@app_mhu_sender_app2mot0 : 0x1b040fec Address@mot_mhu_sender_mot2se0 : 0x1b050fec Address@com_mhu_sender_com2se0 : 0x1b050fec Address@app_mhu_sender_app2mot1 : 0x1b060fec Address@mot_mhu_sender_mot2se1 : 0x1b070fec Address@com_mhu_sender_com2se1 : 0x1b070fec Address@app_mhu_sender_app2se0 : 0x1b800fec Address@app_mhu_sender_app2se1 : 0x1b820fec Address@secenc_mhu_sender_se2app0 : 0x50003fec Address@secenc_mhu_sender_se2app1 : 0x50005fec Address@secenc_mhu_sender_se2com0 : 0x50010fec Address@secenc_mhu_sender_se2com1 : 0x50012fec Address@secenc_mhu_sender_se2mot0 : 0x50014fec Address@secenc_mhu_sender_se2mot1 : 0x50016fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| mhu_sender_cid0 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000ff0 Address@mot_mhu_sender_mot2app0 : 0x1b010ff0 Address@com_mhu_sender_com2app0 : 0x1b010ff0 Address@app_mhu_sender_app2com1 : 0x1b020ff0 Address@mot_mhu_sender_mot2app1 : 0x1b030ff0 Address@com_mhu_sender_com2app1 : 0x1b030ff0 Address@app_mhu_sender_app2mot0 : 0x1b040ff0 Address@mot_mhu_sender_mot2se0 : 0x1b050ff0 Address@com_mhu_sender_com2se0 : 0x1b050ff0 Address@app_mhu_sender_app2mot1 : 0x1b060ff0 Address@mot_mhu_sender_mot2se1 : 0x1b070ff0 Address@com_mhu_sender_com2se1 : 0x1b070ff0 Address@app_mhu_sender_app2se0 : 0x1b800ff0 Address@app_mhu_sender_app2se1 : 0x1b820ff0 Address@secenc_mhu_sender_se2app0 : 0x50003ff0 Address@secenc_mhu_sender_se2app1 : 0x50005ff0 Address@secenc_mhu_sender_se2com0 : 0x50010ff0 Address@secenc_mhu_sender_se2com1 : 0x50012ff0 Address@secenc_mhu_sender_se2mot0 : 0x50014ff0 Address@secenc_mhu_sender_se2mot1 : 0x50016ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| mhu_sender_cid1 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000ff4 Address@mot_mhu_sender_mot2app0 : 0x1b010ff4 Address@com_mhu_sender_com2app0 : 0x1b010ff4 Address@app_mhu_sender_app2com1 : 0x1b020ff4 Address@mot_mhu_sender_mot2app1 : 0x1b030ff4 Address@com_mhu_sender_com2app1 : 0x1b030ff4 Address@app_mhu_sender_app2mot0 : 0x1b040ff4 Address@mot_mhu_sender_mot2se0 : 0x1b050ff4 Address@com_mhu_sender_com2se0 : 0x1b050ff4 Address@app_mhu_sender_app2mot1 : 0x1b060ff4 Address@mot_mhu_sender_mot2se1 : 0x1b070ff4 Address@com_mhu_sender_com2se1 : 0x1b070ff4 Address@app_mhu_sender_app2se0 : 0x1b800ff4 Address@app_mhu_sender_app2se1 : 0x1b820ff4 Address@secenc_mhu_sender_se2app0 : 0x50003ff4 Address@secenc_mhu_sender_se2app1 : 0x50005ff4 Address@secenc_mhu_sender_se2com0 : 0x50010ff4 Address@secenc_mhu_sender_se2com1 : 0x50012ff4 Address@secenc_mhu_sender_se2mot0 : 0x50014ff4 Address@secenc_mhu_sender_se2mot1 : 0x50016ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| mhu_sender_cid2 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000ff8 Address@mot_mhu_sender_mot2app0 : 0x1b010ff8 Address@com_mhu_sender_com2app0 : 0x1b010ff8 Address@app_mhu_sender_app2com1 : 0x1b020ff8 Address@mot_mhu_sender_mot2app1 : 0x1b030ff8 Address@com_mhu_sender_com2app1 : 0x1b030ff8 Address@app_mhu_sender_app2mot0 : 0x1b040ff8 Address@mot_mhu_sender_mot2se0 : 0x1b050ff8 Address@com_mhu_sender_com2se0 : 0x1b050ff8 Address@app_mhu_sender_app2mot1 : 0x1b060ff8 Address@mot_mhu_sender_mot2se1 : 0x1b070ff8 Address@com_mhu_sender_com2se1 : 0x1b070ff8 Address@app_mhu_sender_app2se0 : 0x1b800ff8 Address@app_mhu_sender_app2se1 : 0x1b820ff8 Address@secenc_mhu_sender_se2app0 : 0x50003ff8 Address@secenc_mhu_sender_se2app1 : 0x50005ff8 Address@secenc_mhu_sender_se2com0 : 0x50010ff8 Address@secenc_mhu_sender_se2com1 : 0x50012ff8 Address@secenc_mhu_sender_se2mot0 : 0x50014ff8 Address@secenc_mhu_sender_se2mot1 : 0x50016ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| mhu_sender_cid3 |
|
|||
| R |
Address@app_mhu_sender_app2com0 : 0x1b000ffc Address@mot_mhu_sender_mot2app0 : 0x1b010ffc Address@com_mhu_sender_com2app0 : 0x1b010ffc Address@app_mhu_sender_app2com1 : 0x1b020ffc Address@mot_mhu_sender_mot2app1 : 0x1b030ffc Address@com_mhu_sender_com2app1 : 0x1b030ffc Address@app_mhu_sender_app2mot0 : 0x1b040ffc Address@mot_mhu_sender_mot2se0 : 0x1b050ffc Address@com_mhu_sender_com2se0 : 0x1b050ffc Address@app_mhu_sender_app2mot1 : 0x1b060ffc Address@mot_mhu_sender_mot2se1 : 0x1b070ffc Address@com_mhu_sender_com2se1 : 0x1b070ffc Address@app_mhu_sender_app2se0 : 0x1b800ffc Address@app_mhu_sender_app2se1 : 0x1b820ffc Address@secenc_mhu_sender_se2app0 : 0x50003ffc Address@secenc_mhu_sender_se2app1 : 0x50005ffc Address@secenc_mhu_sender_se2com0 : 0x50010ffc Address@secenc_mhu_sender_se2com1 : 0x50012ffc Address@secenc_mhu_sender_se2mot0 : 0x50014ffc Address@secenc_mhu_sender_se2mot1 : 0x50016ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| mhu_receiver_ch0_st |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000000 Address@com_mhu_receiver_app2com0 : 0x1b000000 Address@app_mhu_receiver_com2app0 : 0x1b010000 Address@mot_mhu_receiver_app2mot1 : 0x1b020000 Address@com_mhu_receiver_app2com1 : 0x1b020000 Address@app_mhu_receiver_com2app1 : 0x1b030000 Address@mot_mhu_receiver_se2mot0 : 0x1b040000 Address@com_mhu_receiver_se2com0 : 0x1b040000 Address@app_mhu_receiver_mot2app0 : 0x1b050000 Address@mot_mhu_receiver_se2mot1 : 0x1b060000 Address@com_mhu_receiver_se2com1 : 0x1b060000 Address@app_mhu_receiver_mot2app1 : 0x1b070000 Address@app_mhu_receiver_se2app0 : 0x1b810000 Address@app_mhu_receiver_se2app1 : 0x1b830000 Address@secenc_mhu_receiver_app2se0 : 0x50004000 Address@secenc_mhu_receiver_app2se1 : 0x50006000 Address@secenc_mhu_receiver_com2se0 : 0x50011000 Address@secenc_mhu_receiver_com2se1 : 0x50013000 Address@secenc_mhu_receiver_mot2se0 : 0x50015000 Address@secenc_mhu_receiver_mot2se1 : 0x50017000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_vec |
|
||
| mhu_receiver_ch0_st_msk |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000004 Address@com_mhu_receiver_app2com0 : 0x1b000004 Address@app_mhu_receiver_com2app0 : 0x1b010004 Address@mot_mhu_receiver_app2mot1 : 0x1b020004 Address@com_mhu_receiver_app2com1 : 0x1b020004 Address@app_mhu_receiver_com2app1 : 0x1b030004 Address@mot_mhu_receiver_se2mot0 : 0x1b040004 Address@com_mhu_receiver_se2com0 : 0x1b040004 Address@app_mhu_receiver_mot2app0 : 0x1b050004 Address@mot_mhu_receiver_se2mot1 : 0x1b060004 Address@com_mhu_receiver_se2com1 : 0x1b060004 Address@app_mhu_receiver_mot2app1 : 0x1b070004 Address@app_mhu_receiver_se2app0 : 0x1b810004 Address@app_mhu_receiver_se2app1 : 0x1b830004 Address@secenc_mhu_receiver_app2se0 : 0x50004004 Address@secenc_mhu_receiver_app2se1 : 0x50006004 Address@secenc_mhu_receiver_com2se0 : 0x50011004 Address@secenc_mhu_receiver_com2se1 : 0x50013004 Address@secenc_mhu_receiver_mot2se0 : 0x50015004 Address@secenc_mhu_receiver_mot2se1 : 0x50017004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_vec |
|
||
| mhu_receiver_ch0_clr |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000008 Address@com_mhu_receiver_app2com0 : 0x1b000008 Address@app_mhu_receiver_com2app0 : 0x1b010008 Address@mot_mhu_receiver_app2mot1 : 0x1b020008 Address@com_mhu_receiver_app2com1 : 0x1b020008 Address@app_mhu_receiver_com2app1 : 0x1b030008 Address@mot_mhu_receiver_se2mot0 : 0x1b040008 Address@com_mhu_receiver_se2com0 : 0x1b040008 Address@app_mhu_receiver_mot2app0 : 0x1b050008 Address@mot_mhu_receiver_se2mot1 : 0x1b060008 Address@com_mhu_receiver_se2com1 : 0x1b060008 Address@app_mhu_receiver_mot2app1 : 0x1b070008 Address@app_mhu_receiver_se2app0 : 0x1b810008 Address@app_mhu_receiver_se2app1 : 0x1b830008 Address@secenc_mhu_receiver_app2se0 : 0x50004008 Address@secenc_mhu_receiver_app2se1 : 0x50006008 Address@secenc_mhu_receiver_com2se0 : 0x50011008 Address@secenc_mhu_receiver_com2se1 : 0x50013008 Address@secenc_mhu_receiver_mot2se0 : 0x50015008 Address@secenc_mhu_receiver_mot2se1 : 0x50017008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_clr_vec |
|
|
| mhu_receiver_ch0_msk_st |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000010 Address@com_mhu_receiver_app2com0 : 0x1b000010 Address@app_mhu_receiver_com2app0 : 0x1b010010 Address@mot_mhu_receiver_app2mot1 : 0x1b020010 Address@com_mhu_receiver_app2com1 : 0x1b020010 Address@app_mhu_receiver_com2app1 : 0x1b030010 Address@mot_mhu_receiver_se2mot0 : 0x1b040010 Address@com_mhu_receiver_se2com0 : 0x1b040010 Address@app_mhu_receiver_mot2app0 : 0x1b050010 Address@mot_mhu_receiver_se2mot1 : 0x1b060010 Address@com_mhu_receiver_se2com1 : 0x1b060010 Address@app_mhu_receiver_mot2app1 : 0x1b070010 Address@app_mhu_receiver_se2app0 : 0x1b810010 Address@app_mhu_receiver_se2app1 : 0x1b830010 Address@secenc_mhu_receiver_app2se0 : 0x50004010 Address@secenc_mhu_receiver_app2se1 : 0x50006010 Address@secenc_mhu_receiver_com2se0 : 0x50011010 Address@secenc_mhu_receiver_com2se1 : 0x50013010 Address@secenc_mhu_receiver_mot2se0 : 0x50015010 Address@secenc_mhu_receiver_mot2se1 : 0x50017010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_msk_vec |
|
||
| mhu_receiver_ch0_msk_set |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000014 Address@com_mhu_receiver_app2com0 : 0x1b000014 Address@app_mhu_receiver_com2app0 : 0x1b010014 Address@mot_mhu_receiver_app2mot1 : 0x1b020014 Address@com_mhu_receiver_app2com1 : 0x1b020014 Address@app_mhu_receiver_com2app1 : 0x1b030014 Address@mot_mhu_receiver_se2mot0 : 0x1b040014 Address@com_mhu_receiver_se2com0 : 0x1b040014 Address@app_mhu_receiver_mot2app0 : 0x1b050014 Address@mot_mhu_receiver_se2mot1 : 0x1b060014 Address@com_mhu_receiver_se2com1 : 0x1b060014 Address@app_mhu_receiver_mot2app1 : 0x1b070014 Address@app_mhu_receiver_se2app0 : 0x1b810014 Address@app_mhu_receiver_se2app1 : 0x1b830014 Address@secenc_mhu_receiver_app2se0 : 0x50004014 Address@secenc_mhu_receiver_app2se1 : 0x50006014 Address@secenc_mhu_receiver_com2se0 : 0x50011014 Address@secenc_mhu_receiver_com2se1 : 0x50013014 Address@secenc_mhu_receiver_mot2se0 : 0x50015014 Address@secenc_mhu_receiver_mot2se1 : 0x50017014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_msk_set_vec |
|
|
| mhu_receiver_ch0_msk_clr |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000018 Address@com_mhu_receiver_app2com0 : 0x1b000018 Address@app_mhu_receiver_com2app0 : 0x1b010018 Address@mot_mhu_receiver_app2mot1 : 0x1b020018 Address@com_mhu_receiver_app2com1 : 0x1b020018 Address@app_mhu_receiver_com2app1 : 0x1b030018 Address@mot_mhu_receiver_se2mot0 : 0x1b040018 Address@com_mhu_receiver_se2com0 : 0x1b040018 Address@app_mhu_receiver_mot2app0 : 0x1b050018 Address@mot_mhu_receiver_se2mot1 : 0x1b060018 Address@com_mhu_receiver_se2com1 : 0x1b060018 Address@app_mhu_receiver_mot2app1 : 0x1b070018 Address@app_mhu_receiver_se2app0 : 0x1b810018 Address@app_mhu_receiver_se2app1 : 0x1b830018 Address@secenc_mhu_receiver_app2se0 : 0x50004018 Address@secenc_mhu_receiver_app2se1 : 0x50006018 Address@secenc_mhu_receiver_com2se0 : 0x50011018 Address@secenc_mhu_receiver_com2se1 : 0x50013018 Address@secenc_mhu_receiver_mot2se0 : 0x50015018 Address@secenc_mhu_receiver_mot2se1 : 0x50017018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_msk_clr_vec |
|
|
| mhu_receiver_ch1_st |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000020 Address@com_mhu_receiver_app2com0 : 0x1b000020 Address@app_mhu_receiver_com2app0 : 0x1b010020 Address@mot_mhu_receiver_app2mot1 : 0x1b020020 Address@com_mhu_receiver_app2com1 : 0x1b020020 Address@app_mhu_receiver_com2app1 : 0x1b030020 Address@mot_mhu_receiver_se2mot0 : 0x1b040020 Address@com_mhu_receiver_se2com0 : 0x1b040020 Address@app_mhu_receiver_mot2app0 : 0x1b050020 Address@mot_mhu_receiver_se2mot1 : 0x1b060020 Address@com_mhu_receiver_se2com1 : 0x1b060020 Address@app_mhu_receiver_mot2app1 : 0x1b070020 Address@app_mhu_receiver_se2app0 : 0x1b810020 Address@app_mhu_receiver_se2app1 : 0x1b830020 Address@secenc_mhu_receiver_app2se0 : 0x50004020 Address@secenc_mhu_receiver_app2se1 : 0x50006020 Address@secenc_mhu_receiver_com2se0 : 0x50011020 Address@secenc_mhu_receiver_com2se1 : 0x50013020 Address@secenc_mhu_receiver_mot2se0 : 0x50015020 Address@secenc_mhu_receiver_mot2se1 : 0x50017020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_vec |
|
||
| mhu_receiver_ch1_st_msk |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000024 Address@com_mhu_receiver_app2com0 : 0x1b000024 Address@app_mhu_receiver_com2app0 : 0x1b010024 Address@mot_mhu_receiver_app2mot1 : 0x1b020024 Address@com_mhu_receiver_app2com1 : 0x1b020024 Address@app_mhu_receiver_com2app1 : 0x1b030024 Address@mot_mhu_receiver_se2mot0 : 0x1b040024 Address@com_mhu_receiver_se2com0 : 0x1b040024 Address@app_mhu_receiver_mot2app0 : 0x1b050024 Address@mot_mhu_receiver_se2mot1 : 0x1b060024 Address@com_mhu_receiver_se2com1 : 0x1b060024 Address@app_mhu_receiver_mot2app1 : 0x1b070024 Address@app_mhu_receiver_se2app0 : 0x1b810024 Address@app_mhu_receiver_se2app1 : 0x1b830024 Address@secenc_mhu_receiver_app2se0 : 0x50004024 Address@secenc_mhu_receiver_app2se1 : 0x50006024 Address@secenc_mhu_receiver_com2se0 : 0x50011024 Address@secenc_mhu_receiver_com2se1 : 0x50013024 Address@secenc_mhu_receiver_mot2se0 : 0x50015024 Address@secenc_mhu_receiver_mot2se1 : 0x50017024 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_vec |
|
||
| mhu_receiver_ch1_clr |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000028 Address@com_mhu_receiver_app2com0 : 0x1b000028 Address@app_mhu_receiver_com2app0 : 0x1b010028 Address@mot_mhu_receiver_app2mot1 : 0x1b020028 Address@com_mhu_receiver_app2com1 : 0x1b020028 Address@app_mhu_receiver_com2app1 : 0x1b030028 Address@mot_mhu_receiver_se2mot0 : 0x1b040028 Address@com_mhu_receiver_se2com0 : 0x1b040028 Address@app_mhu_receiver_mot2app0 : 0x1b050028 Address@mot_mhu_receiver_se2mot1 : 0x1b060028 Address@com_mhu_receiver_se2com1 : 0x1b060028 Address@app_mhu_receiver_mot2app1 : 0x1b070028 Address@app_mhu_receiver_se2app0 : 0x1b810028 Address@app_mhu_receiver_se2app1 : 0x1b830028 Address@secenc_mhu_receiver_app2se0 : 0x50004028 Address@secenc_mhu_receiver_app2se1 : 0x50006028 Address@secenc_mhu_receiver_com2se0 : 0x50011028 Address@secenc_mhu_receiver_com2se1 : 0x50013028 Address@secenc_mhu_receiver_mot2se0 : 0x50015028 Address@secenc_mhu_receiver_mot2se1 : 0x50017028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_clr_vec |
|
|
| mhu_receiver_ch1_msk_st |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000030 Address@com_mhu_receiver_app2com0 : 0x1b000030 Address@app_mhu_receiver_com2app0 : 0x1b010030 Address@mot_mhu_receiver_app2mot1 : 0x1b020030 Address@com_mhu_receiver_app2com1 : 0x1b020030 Address@app_mhu_receiver_com2app1 : 0x1b030030 Address@mot_mhu_receiver_se2mot0 : 0x1b040030 Address@com_mhu_receiver_se2com0 : 0x1b040030 Address@app_mhu_receiver_mot2app0 : 0x1b050030 Address@mot_mhu_receiver_se2mot1 : 0x1b060030 Address@com_mhu_receiver_se2com1 : 0x1b060030 Address@app_mhu_receiver_mot2app1 : 0x1b070030 Address@app_mhu_receiver_se2app0 : 0x1b810030 Address@app_mhu_receiver_se2app1 : 0x1b830030 Address@secenc_mhu_receiver_app2se0 : 0x50004030 Address@secenc_mhu_receiver_app2se1 : 0x50006030 Address@secenc_mhu_receiver_com2se0 : 0x50011030 Address@secenc_mhu_receiver_com2se1 : 0x50013030 Address@secenc_mhu_receiver_mot2se0 : 0x50015030 Address@secenc_mhu_receiver_mot2se1 : 0x50017030 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | flag_msk_vec |
|
||
| mhu_receiver_ch1_msk_set |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000034 Address@com_mhu_receiver_app2com0 : 0x1b000034 Address@app_mhu_receiver_com2app0 : 0x1b010034 Address@mot_mhu_receiver_app2mot1 : 0x1b020034 Address@com_mhu_receiver_app2com1 : 0x1b020034 Address@app_mhu_receiver_com2app1 : 0x1b030034 Address@mot_mhu_receiver_se2mot0 : 0x1b040034 Address@com_mhu_receiver_se2com0 : 0x1b040034 Address@app_mhu_receiver_mot2app0 : 0x1b050034 Address@mot_mhu_receiver_se2mot1 : 0x1b060034 Address@com_mhu_receiver_se2com1 : 0x1b060034 Address@app_mhu_receiver_mot2app1 : 0x1b070034 Address@app_mhu_receiver_se2app0 : 0x1b810034 Address@app_mhu_receiver_se2app1 : 0x1b830034 Address@secenc_mhu_receiver_app2se0 : 0x50004034 Address@secenc_mhu_receiver_app2se1 : 0x50006034 Address@secenc_mhu_receiver_com2se0 : 0x50011034 Address@secenc_mhu_receiver_com2se1 : 0x50013034 Address@secenc_mhu_receiver_mot2se0 : 0x50015034 Address@secenc_mhu_receiver_mot2se1 : 0x50017034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_msk_set_vec |
|
|
| mhu_receiver_ch1_msk_clr |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000038 Address@com_mhu_receiver_app2com0 : 0x1b000038 Address@app_mhu_receiver_com2app0 : 0x1b010038 Address@mot_mhu_receiver_app2mot1 : 0x1b020038 Address@com_mhu_receiver_app2com1 : 0x1b020038 Address@app_mhu_receiver_com2app1 : 0x1b030038 Address@mot_mhu_receiver_se2mot0 : 0x1b040038 Address@com_mhu_receiver_se2com0 : 0x1b040038 Address@app_mhu_receiver_mot2app0 : 0x1b050038 Address@mot_mhu_receiver_se2mot1 : 0x1b060038 Address@com_mhu_receiver_se2com1 : 0x1b060038 Address@app_mhu_receiver_mot2app1 : 0x1b070038 Address@app_mhu_receiver_se2app0 : 0x1b810038 Address@app_mhu_receiver_se2app1 : 0x1b830038 Address@secenc_mhu_receiver_app2se0 : 0x50004038 Address@secenc_mhu_receiver_app2se1 : 0x50006038 Address@secenc_mhu_receiver_com2se0 : 0x50011038 Address@secenc_mhu_receiver_com2se1 : 0x50013038 Address@secenc_mhu_receiver_mot2se0 : 0x50015038 Address@secenc_mhu_receiver_mot2se1 : 0x50017038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
flag_msk_clr_vec |
|
|
| mhu_receiver_mhu_cfg |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000f80 Address@com_mhu_receiver_app2com0 : 0x1b000f80 Address@app_mhu_receiver_com2app0 : 0x1b010f80 Address@mot_mhu_receiver_app2mot1 : 0x1b020f80 Address@com_mhu_receiver_app2com1 : 0x1b020f80 Address@app_mhu_receiver_com2app1 : 0x1b030f80 Address@mot_mhu_receiver_se2mot0 : 0x1b040f80 Address@com_mhu_receiver_se2com0 : 0x1b040f80 Address@app_mhu_receiver_mot2app0 : 0x1b050f80 Address@mot_mhu_receiver_se2mot1 : 0x1b060f80 Address@com_mhu_receiver_se2com1 : 0x1b060f80 Address@app_mhu_receiver_mot2app1 : 0x1b070f80 Address@app_mhu_receiver_se2app0 : 0x1b810f80 Address@app_mhu_receiver_se2app1 : 0x1b830f80 Address@secenc_mhu_receiver_app2se0 : 0x50004f80 Address@secenc_mhu_receiver_app2se1 : 0x50006f80 Address@secenc_mhu_receiver_com2se0 : 0x50011f80 Address@secenc_mhu_receiver_com2se1 : 0x50013f80 Address@secenc_mhu_receiver_mot2se0 : 0x50015f80 Address@secenc_mhu_receiver_mot2se1 : 0x50017f80 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||
| 6 - 0 | num_ch |
|
||
| mhu_receiver_int_st |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000f90 Address@com_mhu_receiver_app2com0 : 0x1b000f90 Address@app_mhu_receiver_com2app0 : 0x1b010f90 Address@mot_mhu_receiver_app2mot1 : 0x1b020f90 Address@com_mhu_receiver_app2com1 : 0x1b020f90 Address@app_mhu_receiver_com2app1 : 0x1b030f90 Address@mot_mhu_receiver_se2mot0 : 0x1b040f90 Address@com_mhu_receiver_se2com0 : 0x1b040f90 Address@app_mhu_receiver_mot2app0 : 0x1b050f90 Address@mot_mhu_receiver_se2mot1 : 0x1b060f90 Address@com_mhu_receiver_se2com1 : 0x1b060f90 Address@app_mhu_receiver_mot2app1 : 0x1b070f90 Address@app_mhu_receiver_se2app0 : 0x1b810f90 Address@app_mhu_receiver_se2app1 : 0x1b830f90 Address@secenc_mhu_receiver_app2se0 : 0x50004f90 Address@secenc_mhu_receiver_app2se1 : 0x50006f90 Address@secenc_mhu_receiver_com2se0 : 0x50011f90 Address@secenc_mhu_receiver_com2se1 : 0x50013f90 Address@secenc_mhu_receiver_mot2se0 : 0x50015f90 Address@secenc_mhu_receiver_mot2se1 : 0x50017f90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | chcomb |
|
||
| 1 - 0 | - |
reserved | ||
| mhu_receiver_int_clr |
|
|||
| W |
0x00000000 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000f94 Address@com_mhu_receiver_app2com0 : 0x1b000f94 Address@app_mhu_receiver_com2app0 : 0x1b010f94 Address@mot_mhu_receiver_app2mot1 : 0x1b020f94 Address@com_mhu_receiver_app2com1 : 0x1b020f94 Address@app_mhu_receiver_com2app1 : 0x1b030f94 Address@mot_mhu_receiver_se2mot0 : 0x1b040f94 Address@com_mhu_receiver_se2com0 : 0x1b040f94 Address@app_mhu_receiver_mot2app0 : 0x1b050f94 Address@mot_mhu_receiver_se2mot1 : 0x1b060f94 Address@com_mhu_receiver_se2com1 : 0x1b060f94 Address@app_mhu_receiver_mot2app1 : 0x1b070f94 Address@app_mhu_receiver_se2app0 : 0x1b810f94 Address@app_mhu_receiver_se2app1 : 0x1b830f94 Address@secenc_mhu_receiver_app2se0 : 0x50004f94 Address@secenc_mhu_receiver_app2se1 : 0x50006f94 Address@secenc_mhu_receiver_com2se0 : 0x50011f94 Address@secenc_mhu_receiver_com2se1 : 0x50013f94 Address@secenc_mhu_receiver_mot2se0 : 0x50015f94 Address@secenc_mhu_receiver_mot2se1 : 0x50017f94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
mhu_receiver_int_clr | ||
| mhu_receiver_int_en |
|
|||
| R/W |
0x00000004 |
Address@mot_mhu_receiver_app2mot0 : 0x1b000f98 Address@com_mhu_receiver_app2com0 : 0x1b000f98 Address@app_mhu_receiver_com2app0 : 0x1b010f98 Address@mot_mhu_receiver_app2mot1 : 0x1b020f98 Address@com_mhu_receiver_app2com1 : 0x1b020f98 Address@app_mhu_receiver_com2app1 : 0x1b030f98 Address@mot_mhu_receiver_se2mot0 : 0x1b040f98 Address@com_mhu_receiver_se2com0 : 0x1b040f98 Address@app_mhu_receiver_mot2app0 : 0x1b050f98 Address@mot_mhu_receiver_se2mot1 : 0x1b060f98 Address@com_mhu_receiver_se2com1 : 0x1b060f98 Address@app_mhu_receiver_mot2app1 : 0x1b070f98 Address@app_mhu_receiver_se2app0 : 0x1b810f98 Address@app_mhu_receiver_se2app1 : 0x1b830f98 Address@secenc_mhu_receiver_app2se0 : 0x50004f98 Address@secenc_mhu_receiver_app2se1 : 0x50006f98 Address@secenc_mhu_receiver_com2se0 : 0x50011f98 Address@secenc_mhu_receiver_com2se1 : 0x50013f98 Address@secenc_mhu_receiver_mot2se0 : 0x50015f98 Address@secenc_mhu_receiver_mot2se1 : 0x50017f98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "1" |
chcomb |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| mhu_receiver_chcomb_int_st0 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa0 Address@com_mhu_receiver_app2com0 : 0x1b000fa0 Address@app_mhu_receiver_com2app0 : 0x1b010fa0 Address@mot_mhu_receiver_app2mot1 : 0x1b020fa0 Address@com_mhu_receiver_app2com1 : 0x1b020fa0 Address@app_mhu_receiver_com2app1 : 0x1b030fa0 Address@mot_mhu_receiver_se2mot0 : 0x1b040fa0 Address@com_mhu_receiver_se2com0 : 0x1b040fa0 Address@app_mhu_receiver_mot2app0 : 0x1b050fa0 Address@mot_mhu_receiver_se2mot1 : 0x1b060fa0 Address@com_mhu_receiver_se2com1 : 0x1b060fa0 Address@app_mhu_receiver_mot2app1 : 0x1b070fa0 Address@app_mhu_receiver_se2app0 : 0x1b810fa0 Address@app_mhu_receiver_se2app1 : 0x1b830fa0 Address@secenc_mhu_receiver_app2se0 : 0x50004fa0 Address@secenc_mhu_receiver_app2se1 : 0x50006fa0 Address@secenc_mhu_receiver_com2se0 : 0x50011fa0 Address@secenc_mhu_receiver_com2se1 : 0x50013fa0 Address@secenc_mhu_receiver_mot2se0 : 0x50015fa0 Address@secenc_mhu_receiver_mot2se1 : 0x50017fa0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st0 |
|
||
| mhu_receiver_chcomb_int_st1 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa4 Address@com_mhu_receiver_app2com0 : 0x1b000fa4 Address@app_mhu_receiver_com2app0 : 0x1b010fa4 Address@mot_mhu_receiver_app2mot1 : 0x1b020fa4 Address@com_mhu_receiver_app2com1 : 0x1b020fa4 Address@app_mhu_receiver_com2app1 : 0x1b030fa4 Address@mot_mhu_receiver_se2mot0 : 0x1b040fa4 Address@com_mhu_receiver_se2com0 : 0x1b040fa4 Address@app_mhu_receiver_mot2app0 : 0x1b050fa4 Address@mot_mhu_receiver_se2mot1 : 0x1b060fa4 Address@com_mhu_receiver_se2com1 : 0x1b060fa4 Address@app_mhu_receiver_mot2app1 : 0x1b070fa4 Address@app_mhu_receiver_se2app0 : 0x1b810fa4 Address@app_mhu_receiver_se2app1 : 0x1b830fa4 Address@secenc_mhu_receiver_app2se0 : 0x50004fa4 Address@secenc_mhu_receiver_app2se1 : 0x50006fa4 Address@secenc_mhu_receiver_com2se0 : 0x50011fa4 Address@secenc_mhu_receiver_com2se1 : 0x50013fa4 Address@secenc_mhu_receiver_mot2se0 : 0x50015fa4 Address@secenc_mhu_receiver_mot2se1 : 0x50017fa4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st1 |
|
||
| mhu_receiver_chcomb_int_st2 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa8 Address@com_mhu_receiver_app2com0 : 0x1b000fa8 Address@app_mhu_receiver_com2app0 : 0x1b010fa8 Address@mot_mhu_receiver_app2mot1 : 0x1b020fa8 Address@com_mhu_receiver_app2com1 : 0x1b020fa8 Address@app_mhu_receiver_com2app1 : 0x1b030fa8 Address@mot_mhu_receiver_se2mot0 : 0x1b040fa8 Address@com_mhu_receiver_se2com0 : 0x1b040fa8 Address@app_mhu_receiver_mot2app0 : 0x1b050fa8 Address@mot_mhu_receiver_se2mot1 : 0x1b060fa8 Address@com_mhu_receiver_se2com1 : 0x1b060fa8 Address@app_mhu_receiver_mot2app1 : 0x1b070fa8 Address@app_mhu_receiver_se2app0 : 0x1b810fa8 Address@app_mhu_receiver_se2app1 : 0x1b830fa8 Address@secenc_mhu_receiver_app2se0 : 0x50004fa8 Address@secenc_mhu_receiver_app2se1 : 0x50006fa8 Address@secenc_mhu_receiver_com2se0 : 0x50011fa8 Address@secenc_mhu_receiver_com2se1 : 0x50013fa8 Address@secenc_mhu_receiver_mot2se0 : 0x50015fa8 Address@secenc_mhu_receiver_mot2se1 : 0x50017fa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st2 |
|
||
| mhu_receiver_chcomb_int_st3 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fac Address@com_mhu_receiver_app2com0 : 0x1b000fac Address@app_mhu_receiver_com2app0 : 0x1b010fac Address@mot_mhu_receiver_app2mot1 : 0x1b020fac Address@com_mhu_receiver_app2com1 : 0x1b020fac Address@app_mhu_receiver_com2app1 : 0x1b030fac Address@mot_mhu_receiver_se2mot0 : 0x1b040fac Address@com_mhu_receiver_se2com0 : 0x1b040fac Address@app_mhu_receiver_mot2app0 : 0x1b050fac Address@mot_mhu_receiver_se2mot1 : 0x1b060fac Address@com_mhu_receiver_se2com1 : 0x1b060fac Address@app_mhu_receiver_mot2app1 : 0x1b070fac Address@app_mhu_receiver_se2app0 : 0x1b810fac Address@app_mhu_receiver_se2app1 : 0x1b830fac Address@secenc_mhu_receiver_app2se0 : 0x50004fac Address@secenc_mhu_receiver_app2se1 : 0x50006fac Address@secenc_mhu_receiver_com2se0 : 0x50011fac Address@secenc_mhu_receiver_com2se1 : 0x50013fac Address@secenc_mhu_receiver_mot2se0 : 0x50015fac Address@secenc_mhu_receiver_mot2se1 : 0x50017fac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ch_int_st3 |
|
||
| mhu_receiver_iidr |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fc8 Address@com_mhu_receiver_app2com0 : 0x1b000fc8 Address@app_mhu_receiver_com2app0 : 0x1b010fc8 Address@mot_mhu_receiver_app2mot1 : 0x1b020fc8 Address@com_mhu_receiver_app2com1 : 0x1b020fc8 Address@app_mhu_receiver_com2app1 : 0x1b030fc8 Address@mot_mhu_receiver_se2mot0 : 0x1b040fc8 Address@com_mhu_receiver_se2com0 : 0x1b040fc8 Address@app_mhu_receiver_mot2app0 : 0x1b050fc8 Address@mot_mhu_receiver_se2mot1 : 0x1b060fc8 Address@com_mhu_receiver_se2com1 : 0x1b060fc8 Address@app_mhu_receiver_mot2app1 : 0x1b070fc8 Address@app_mhu_receiver_se2app0 : 0x1b810fc8 Address@app_mhu_receiver_se2app1 : 0x1b830fc8 Address@secenc_mhu_receiver_app2se0 : 0x50004fc8 Address@secenc_mhu_receiver_app2se1 : 0x50006fc8 Address@secenc_mhu_receiver_com2se0 : 0x50011fc8 Address@secenc_mhu_receiver_com2se1 : 0x50013fc8 Address@secenc_mhu_receiver_mot2se0 : 0x50015fc8 Address@secenc_mhu_receiver_mot2se1 : 0x50017fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | product_id |
|
||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| mhu_receiver_aidr |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fcc Address@com_mhu_receiver_app2com0 : 0x1b000fcc Address@app_mhu_receiver_com2app0 : 0x1b010fcc Address@mot_mhu_receiver_app2mot1 : 0x1b020fcc Address@com_mhu_receiver_app2com1 : 0x1b020fcc Address@app_mhu_receiver_com2app1 : 0x1b030fcc Address@mot_mhu_receiver_se2mot0 : 0x1b040fcc Address@com_mhu_receiver_se2com0 : 0x1b040fcc Address@app_mhu_receiver_mot2app0 : 0x1b050fcc Address@mot_mhu_receiver_se2mot1 : 0x1b060fcc Address@com_mhu_receiver_se2com1 : 0x1b060fcc Address@app_mhu_receiver_mot2app1 : 0x1b070fcc Address@app_mhu_receiver_se2app0 : 0x1b810fcc Address@app_mhu_receiver_se2app1 : 0x1b830fcc Address@secenc_mhu_receiver_app2se0 : 0x50004fcc Address@secenc_mhu_receiver_app2se1 : 0x50006fcc Address@secenc_mhu_receiver_com2se0 : 0x50011fcc Address@secenc_mhu_receiver_com2se1 : 0x50013fcc Address@secenc_mhu_receiver_mot2se0 : 0x50015fcc Address@secenc_mhu_receiver_mot2se1 : 0x50017fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | arch_major_rev |
|
||
| 3 - 0 | arch_minor_rev |
|
||
| mhu_receiver_pid4 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd0 Address@com_mhu_receiver_app2com0 : 0x1b000fd0 Address@app_mhu_receiver_com2app0 : 0x1b010fd0 Address@mot_mhu_receiver_app2mot1 : 0x1b020fd0 Address@com_mhu_receiver_app2com1 : 0x1b020fd0 Address@app_mhu_receiver_com2app1 : 0x1b030fd0 Address@mot_mhu_receiver_se2mot0 : 0x1b040fd0 Address@com_mhu_receiver_se2com0 : 0x1b040fd0 Address@app_mhu_receiver_mot2app0 : 0x1b050fd0 Address@mot_mhu_receiver_se2mot1 : 0x1b060fd0 Address@com_mhu_receiver_se2com1 : 0x1b060fd0 Address@app_mhu_receiver_mot2app1 : 0x1b070fd0 Address@app_mhu_receiver_se2app0 : 0x1b810fd0 Address@app_mhu_receiver_se2app1 : 0x1b830fd0 Address@secenc_mhu_receiver_app2se0 : 0x50004fd0 Address@secenc_mhu_receiver_app2se1 : 0x50006fd0 Address@secenc_mhu_receiver_com2se0 : 0x50011fd0 Address@secenc_mhu_receiver_com2se1 : 0x50013fd0 Address@secenc_mhu_receiver_mot2se0 : 0x50015fd0 Address@secenc_mhu_receiver_mot2se1 : 0x50017fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| mhu_receiver_pid5 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd4 Address@com_mhu_receiver_app2com0 : 0x1b000fd4 Address@app_mhu_receiver_com2app0 : 0x1b010fd4 Address@mot_mhu_receiver_app2mot1 : 0x1b020fd4 Address@com_mhu_receiver_app2com1 : 0x1b020fd4 Address@app_mhu_receiver_com2app1 : 0x1b030fd4 Address@mot_mhu_receiver_se2mot0 : 0x1b040fd4 Address@com_mhu_receiver_se2com0 : 0x1b040fd4 Address@app_mhu_receiver_mot2app0 : 0x1b050fd4 Address@mot_mhu_receiver_se2mot1 : 0x1b060fd4 Address@com_mhu_receiver_se2com1 : 0x1b060fd4 Address@app_mhu_receiver_mot2app1 : 0x1b070fd4 Address@app_mhu_receiver_se2app0 : 0x1b810fd4 Address@app_mhu_receiver_se2app1 : 0x1b830fd4 Address@secenc_mhu_receiver_app2se0 : 0x50004fd4 Address@secenc_mhu_receiver_app2se1 : 0x50006fd4 Address@secenc_mhu_receiver_com2se0 : 0x50011fd4 Address@secenc_mhu_receiver_com2se1 : 0x50013fd4 Address@secenc_mhu_receiver_mot2se0 : 0x50015fd4 Address@secenc_mhu_receiver_mot2se1 : 0x50017fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_receiver_pid5 | |||
| mhu_receiver_pid6 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd8 Address@com_mhu_receiver_app2com0 : 0x1b000fd8 Address@app_mhu_receiver_com2app0 : 0x1b010fd8 Address@mot_mhu_receiver_app2mot1 : 0x1b020fd8 Address@com_mhu_receiver_app2com1 : 0x1b020fd8 Address@app_mhu_receiver_com2app1 : 0x1b030fd8 Address@mot_mhu_receiver_se2mot0 : 0x1b040fd8 Address@com_mhu_receiver_se2com0 : 0x1b040fd8 Address@app_mhu_receiver_mot2app0 : 0x1b050fd8 Address@mot_mhu_receiver_se2mot1 : 0x1b060fd8 Address@com_mhu_receiver_se2com1 : 0x1b060fd8 Address@app_mhu_receiver_mot2app1 : 0x1b070fd8 Address@app_mhu_receiver_se2app0 : 0x1b810fd8 Address@app_mhu_receiver_se2app1 : 0x1b830fd8 Address@secenc_mhu_receiver_app2se0 : 0x50004fd8 Address@secenc_mhu_receiver_app2se1 : 0x50006fd8 Address@secenc_mhu_receiver_com2se0 : 0x50011fd8 Address@secenc_mhu_receiver_com2se1 : 0x50013fd8 Address@secenc_mhu_receiver_mot2se0 : 0x50015fd8 Address@secenc_mhu_receiver_mot2se1 : 0x50017fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_receiver_pid6 | |||
| mhu_receiver_pid7 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fdc Address@com_mhu_receiver_app2com0 : 0x1b000fdc Address@app_mhu_receiver_com2app0 : 0x1b010fdc Address@mot_mhu_receiver_app2mot1 : 0x1b020fdc Address@com_mhu_receiver_app2com1 : 0x1b020fdc Address@app_mhu_receiver_com2app1 : 0x1b030fdc Address@mot_mhu_receiver_se2mot0 : 0x1b040fdc Address@com_mhu_receiver_se2com0 : 0x1b040fdc Address@app_mhu_receiver_mot2app0 : 0x1b050fdc Address@mot_mhu_receiver_se2mot1 : 0x1b060fdc Address@com_mhu_receiver_se2com1 : 0x1b060fdc Address@app_mhu_receiver_mot2app1 : 0x1b070fdc Address@app_mhu_receiver_se2app0 : 0x1b810fdc Address@app_mhu_receiver_se2app1 : 0x1b830fdc Address@secenc_mhu_receiver_app2se0 : 0x50004fdc Address@secenc_mhu_receiver_app2se1 : 0x50006fdc Address@secenc_mhu_receiver_com2se0 : 0x50011fdc Address@secenc_mhu_receiver_com2se1 : 0x50013fdc Address@secenc_mhu_receiver_mot2se0 : 0x50015fdc Address@secenc_mhu_receiver_mot2se1 : 0x50017fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | mhu_receiver_pid7 | |||
| mhu_receiver_pid0 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe0 Address@com_mhu_receiver_app2com0 : 0x1b000fe0 Address@app_mhu_receiver_com2app0 : 0x1b010fe0 Address@mot_mhu_receiver_app2mot1 : 0x1b020fe0 Address@com_mhu_receiver_app2com1 : 0x1b020fe0 Address@app_mhu_receiver_com2app1 : 0x1b030fe0 Address@mot_mhu_receiver_se2mot0 : 0x1b040fe0 Address@com_mhu_receiver_se2com0 : 0x1b040fe0 Address@app_mhu_receiver_mot2app0 : 0x1b050fe0 Address@mot_mhu_receiver_se2mot1 : 0x1b060fe0 Address@com_mhu_receiver_se2com1 : 0x1b060fe0 Address@app_mhu_receiver_mot2app1 : 0x1b070fe0 Address@app_mhu_receiver_se2app0 : 0x1b810fe0 Address@app_mhu_receiver_se2app1 : 0x1b830fe0 Address@secenc_mhu_receiver_app2se0 : 0x50004fe0 Address@secenc_mhu_receiver_app2se1 : 0x50006fe0 Address@secenc_mhu_receiver_com2se0 : 0x50011fe0 Address@secenc_mhu_receiver_com2se1 : 0x50013fe0 Address@secenc_mhu_receiver_mot2se0 : 0x50015fe0 Address@secenc_mhu_receiver_mot2se1 : 0x50017fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| mhu_receiver_pid1 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe4 Address@com_mhu_receiver_app2com0 : 0x1b000fe4 Address@app_mhu_receiver_com2app0 : 0x1b010fe4 Address@mot_mhu_receiver_app2mot1 : 0x1b020fe4 Address@com_mhu_receiver_app2com1 : 0x1b020fe4 Address@app_mhu_receiver_com2app1 : 0x1b030fe4 Address@mot_mhu_receiver_se2mot0 : 0x1b040fe4 Address@com_mhu_receiver_se2com0 : 0x1b040fe4 Address@app_mhu_receiver_mot2app0 : 0x1b050fe4 Address@mot_mhu_receiver_se2mot1 : 0x1b060fe4 Address@com_mhu_receiver_se2com1 : 0x1b060fe4 Address@app_mhu_receiver_mot2app1 : 0x1b070fe4 Address@app_mhu_receiver_se2app0 : 0x1b810fe4 Address@app_mhu_receiver_se2app1 : 0x1b830fe4 Address@secenc_mhu_receiver_app2se0 : 0x50004fe4 Address@secenc_mhu_receiver_app2se1 : 0x50006fe4 Address@secenc_mhu_receiver_com2se0 : 0x50011fe4 Address@secenc_mhu_receiver_com2se1 : 0x50013fe4 Address@secenc_mhu_receiver_mot2se0 : 0x50015fe4 Address@secenc_mhu_receiver_mot2se1 : 0x50017fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| mhu_receiver_pid2 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe8 Address@com_mhu_receiver_app2com0 : 0x1b000fe8 Address@app_mhu_receiver_com2app0 : 0x1b010fe8 Address@mot_mhu_receiver_app2mot1 : 0x1b020fe8 Address@com_mhu_receiver_app2com1 : 0x1b020fe8 Address@app_mhu_receiver_com2app1 : 0x1b030fe8 Address@mot_mhu_receiver_se2mot0 : 0x1b040fe8 Address@com_mhu_receiver_se2com0 : 0x1b040fe8 Address@app_mhu_receiver_mot2app0 : 0x1b050fe8 Address@mot_mhu_receiver_se2mot1 : 0x1b060fe8 Address@com_mhu_receiver_se2com1 : 0x1b060fe8 Address@app_mhu_receiver_mot2app1 : 0x1b070fe8 Address@app_mhu_receiver_se2app0 : 0x1b810fe8 Address@app_mhu_receiver_se2app1 : 0x1b830fe8 Address@secenc_mhu_receiver_app2se0 : 0x50004fe8 Address@secenc_mhu_receiver_app2se1 : 0x50006fe8 Address@secenc_mhu_receiver_com2se0 : 0x50011fe8 Address@secenc_mhu_receiver_com2se1 : 0x50013fe8 Address@secenc_mhu_receiver_mot2se0 : 0x50015fe8 Address@secenc_mhu_receiver_mot2se1 : 0x50017fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| mhu_receiver_pid3 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000fec Address@com_mhu_receiver_app2com0 : 0x1b000fec Address@app_mhu_receiver_com2app0 : 0x1b010fec Address@mot_mhu_receiver_app2mot1 : 0x1b020fec Address@com_mhu_receiver_app2com1 : 0x1b020fec Address@app_mhu_receiver_com2app1 : 0x1b030fec Address@mot_mhu_receiver_se2mot0 : 0x1b040fec Address@com_mhu_receiver_se2com0 : 0x1b040fec Address@app_mhu_receiver_mot2app0 : 0x1b050fec Address@mot_mhu_receiver_se2mot1 : 0x1b060fec Address@com_mhu_receiver_se2com1 : 0x1b060fec Address@app_mhu_receiver_mot2app1 : 0x1b070fec Address@app_mhu_receiver_se2app0 : 0x1b810fec Address@app_mhu_receiver_se2app1 : 0x1b830fec Address@secenc_mhu_receiver_app2se0 : 0x50004fec Address@secenc_mhu_receiver_app2se1 : 0x50006fec Address@secenc_mhu_receiver_com2se0 : 0x50011fec Address@secenc_mhu_receiver_com2se1 : 0x50013fec Address@secenc_mhu_receiver_mot2se0 : 0x50015fec Address@secenc_mhu_receiver_mot2se1 : 0x50017fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| mhu_receiver_cid0 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff0 Address@com_mhu_receiver_app2com0 : 0x1b000ff0 Address@app_mhu_receiver_com2app0 : 0x1b010ff0 Address@mot_mhu_receiver_app2mot1 : 0x1b020ff0 Address@com_mhu_receiver_app2com1 : 0x1b020ff0 Address@app_mhu_receiver_com2app1 : 0x1b030ff0 Address@mot_mhu_receiver_se2mot0 : 0x1b040ff0 Address@com_mhu_receiver_se2com0 : 0x1b040ff0 Address@app_mhu_receiver_mot2app0 : 0x1b050ff0 Address@mot_mhu_receiver_se2mot1 : 0x1b060ff0 Address@com_mhu_receiver_se2com1 : 0x1b060ff0 Address@app_mhu_receiver_mot2app1 : 0x1b070ff0 Address@app_mhu_receiver_se2app0 : 0x1b810ff0 Address@app_mhu_receiver_se2app1 : 0x1b830ff0 Address@secenc_mhu_receiver_app2se0 : 0x50004ff0 Address@secenc_mhu_receiver_app2se1 : 0x50006ff0 Address@secenc_mhu_receiver_com2se0 : 0x50011ff0 Address@secenc_mhu_receiver_com2se1 : 0x50013ff0 Address@secenc_mhu_receiver_mot2se0 : 0x50015ff0 Address@secenc_mhu_receiver_mot2se1 : 0x50017ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| mhu_receiver_cid1 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff4 Address@com_mhu_receiver_app2com0 : 0x1b000ff4 Address@app_mhu_receiver_com2app0 : 0x1b010ff4 Address@mot_mhu_receiver_app2mot1 : 0x1b020ff4 Address@com_mhu_receiver_app2com1 : 0x1b020ff4 Address@app_mhu_receiver_com2app1 : 0x1b030ff4 Address@mot_mhu_receiver_se2mot0 : 0x1b040ff4 Address@com_mhu_receiver_se2com0 : 0x1b040ff4 Address@app_mhu_receiver_mot2app0 : 0x1b050ff4 Address@mot_mhu_receiver_se2mot1 : 0x1b060ff4 Address@com_mhu_receiver_se2com1 : 0x1b060ff4 Address@app_mhu_receiver_mot2app1 : 0x1b070ff4 Address@app_mhu_receiver_se2app0 : 0x1b810ff4 Address@app_mhu_receiver_se2app1 : 0x1b830ff4 Address@secenc_mhu_receiver_app2se0 : 0x50004ff4 Address@secenc_mhu_receiver_app2se1 : 0x50006ff4 Address@secenc_mhu_receiver_com2se0 : 0x50011ff4 Address@secenc_mhu_receiver_com2se1 : 0x50013ff4 Address@secenc_mhu_receiver_mot2se0 : 0x50015ff4 Address@secenc_mhu_receiver_mot2se1 : 0x50017ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| mhu_receiver_cid2 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff8 Address@com_mhu_receiver_app2com0 : 0x1b000ff8 Address@app_mhu_receiver_com2app0 : 0x1b010ff8 Address@mot_mhu_receiver_app2mot1 : 0x1b020ff8 Address@com_mhu_receiver_app2com1 : 0x1b020ff8 Address@app_mhu_receiver_com2app1 : 0x1b030ff8 Address@mot_mhu_receiver_se2mot0 : 0x1b040ff8 Address@com_mhu_receiver_se2com0 : 0x1b040ff8 Address@app_mhu_receiver_mot2app0 : 0x1b050ff8 Address@mot_mhu_receiver_se2mot1 : 0x1b060ff8 Address@com_mhu_receiver_se2com1 : 0x1b060ff8 Address@app_mhu_receiver_mot2app1 : 0x1b070ff8 Address@app_mhu_receiver_se2app0 : 0x1b810ff8 Address@app_mhu_receiver_se2app1 : 0x1b830ff8 Address@secenc_mhu_receiver_app2se0 : 0x50004ff8 Address@secenc_mhu_receiver_app2se1 : 0x50006ff8 Address@secenc_mhu_receiver_com2se0 : 0x50011ff8 Address@secenc_mhu_receiver_com2se1 : 0x50013ff8 Address@secenc_mhu_receiver_mot2se0 : 0x50015ff8 Address@secenc_mhu_receiver_mot2se1 : 0x50017ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| mhu_receiver_cid3 |
|
|||
| R |
Address@mot_mhu_receiver_app2mot0 : 0x1b000ffc Address@com_mhu_receiver_app2com0 : 0x1b000ffc Address@app_mhu_receiver_com2app0 : 0x1b010ffc Address@mot_mhu_receiver_app2mot1 : 0x1b020ffc Address@com_mhu_receiver_app2com1 : 0x1b020ffc Address@app_mhu_receiver_com2app1 : 0x1b030ffc Address@mot_mhu_receiver_se2mot0 : 0x1b040ffc Address@com_mhu_receiver_se2com0 : 0x1b040ffc Address@app_mhu_receiver_mot2app0 : 0x1b050ffc Address@mot_mhu_receiver_se2mot1 : 0x1b060ffc Address@com_mhu_receiver_se2com1 : 0x1b060ffc Address@app_mhu_receiver_mot2app1 : 0x1b070ffc Address@app_mhu_receiver_se2app0 : 0x1b810ffc Address@app_mhu_receiver_se2app1 : 0x1b830ffc Address@secenc_mhu_receiver_app2se0 : 0x50004ffc Address@secenc_mhu_receiver_app2se1 : 0x50006ffc Address@secenc_mhu_receiver_com2se0 : 0x50011ffc Address@secenc_mhu_receiver_com2se1 : 0x50013ffc Address@secenc_mhu_receiver_mot2se0 : 0x50015ffc Address@secenc_mhu_receiver_mot2se1 : 0x50017ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | apbcom_romentry0 |
| 1-33f | 4-cfc | - | reserved |
| 340 | d00 | R | apbcom_vidr |
| 341 | d04 | - | reserved |
| 342 | d08 | R | apbcom_fidtxr |
| 343 | d0c | R | apbcom_fidrxr |
| 344 | d10 | R/W | apbcom_icsr |
| 345-347 | d14-d1c | - | reserved |
| 348 | d20 | R/W | apbcom_dr |
| 349-34a | d24-d28 | - | reserved |
| 34b | d2c | R/W | apbcom_sr0 |
| 34c | d30 | R/W | apbcom_dbr |
| 34d-34e | d34-d38 | - | reserved |
| 34f | d3c | R/W | apbcom_sr1 |
| 350-3be | d40-ef8 | - | reserved |
| 3bf | efc | R | apbcom_itstatus |
| 3c0 | f00 | R/W | apbcom_itctrl |
| 3c1-3e7 | f04-f9c | - | reserved |
| 3e8 | fa0 | R/W | apbcom_claimset |
| 3e9 | fa4 | R/W | apbcom_claimclr |
| 3ea | fa8 | R | apbcom_devaff0 |
| 3eb | fac | R | apbcom_devaff1 |
| 3ec | fb0 | R | apbcom_lar |
| 3ed | fb4 | R | apbcom_lsr |
| 3ee | fb8 | R | apbcom_authstatus |
| 3ef | fbc | R | apbcom_devarch |
| 3f0 | fc0 | R | apbcom_devid2 |
| 3f1 | fc4 | R | apbcom_devid1 |
| 3f2 | fc8 | R | apbcom_devid |
| 3f3 | fcc | R | apbcom_devtype |
| 3f4 | fd0 | R | apbcom_pidr4 |
| 3f5 | fd4 | R | apbcom_pidr5 |
| 3f6 | fd8 | R | apbcom_pidr6 |
| 3f7 | fdc | R | apbcom_pidr7 |
| 3f8 | fe0 | R | apbcom_pidr0 |
| 3f9 | fe4 | R | apbcom_pidr1 |
| 3fa | fe8 | R | apbcom_pidr2 |
| 3fb | fec | R | apbcom_pidr3 |
| 3fc | ff0 | R | apbcom_cidr0 |
| 3fd | ff4 | R | apbcom_cidr1 |
| 3fe | ff8 | R | apbcom_cidr2 |
| 3ff | ffc | R | apbcom_cidr3 |
| apbcom_romentry0 |
|
|||
| R |
Address : 0x1b900000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 22 | - |
reserved | ||
| 21 - 12 | offset |
|
||
| 11 - 3 | - |
reserved | ||
| 2 | poweridvalid |
|
||
| 1 - 0 | present |
|
||
| apbcom_vidr |
|
|||
| R |
Address : 0x1b900d00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | protversion |
|
||
| 3 - 0 | pmversion |
|
||
| apbcom_fidtxr |
|
|||||||
| R |
Address : 0x1b900d08 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||||||
| 19 - 16 | txfd |
|
||||||
| 15 - 11 | - |
reserved | ||||||
| 10 | txsz32 |
|
||||||
| 9 | txsz16 |
|
||||||
| 8 | txsz8 |
|
||||||
| 7 - 4 | txw |
|
||||||
| 3 - 2 | - |
reserved | ||||||
| 1 | txint |
|
||||||
| 0 | txi |
|
||||||
| apbcom_fidrxr |
|
|||||||
| R |
Address : 0x1b900d0c |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||||||
| 19 - 16 | rxfd |
|
||||||
| 15 - 11 | - |
reserved | ||||||
| 10 | rxsz32 |
|
||||||
| 9 | rxsz16 |
|
||||||
| 8 | rxsz8 |
|
||||||
| 7 - 2 | - |
reserved | ||||||
| 1 | rxint |
|
||||||
| 0 | rxi |
|
||||||
| apbcom_icsr |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900d10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
rxfis |
|
|
| 30 - 20 | 0 |
- |
reserved | |
| 19 - 16 | "0000" |
rxfil |
|
|
| 15 | "0" |
txfis |
|
|
| 14 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
txfil |
|
|
| apbcom_dr |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| apbcom_sr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
pen |
|
|
| 30 | "0" |
rxle |
|
|
| 29 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
rxf |
|
|
| 15 | "0" |
trinprog |
|
|
| 14 | "0" |
txle |
|
|
| 13 | "0" |
txoe |
|
|
| 12 | "0" |
rrdis |
|
|
| 11 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
txs |
|
|
| apbcom_dbr |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900d30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| apbcom_sr1 |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
pen |
|
|
| 30 | "0" |
rxle |
|
|
| 29 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
rxf |
|
|
| 15 | "0" |
trinprog |
|
|
| 14 | "0" |
txle |
|
|
| 13 | "0" |
txoe |
|
|
| 12 | "0" |
rrdis |
|
|
| 11 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
txs |
|
|
| apbcom_itstatus |
|
|||
| R |
Address : 0x1b900efc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | dpabort |
|
||
| apbcom_itctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900f00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
ime |
|
|
| apbcom_claimset |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900fa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
apbcom_claimset | ||
| apbcom_claimclr |
|
|||
| R/W |
0x00000000 |
Address : 0x1b900fa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
apbcom_claimclr | ||
| apbcom_devaff0 |
|
|||
| R |
Address : 0x1b900fa8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_devaff0 | |||
| apbcom_devaff1 |
|
|||
| R |
Address : 0x1b900fac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_devaff1 | |||
| apbcom_lar |
|
|||
| R |
Address : 0x1b900fb0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_lar | |||
| apbcom_lsr |
|
|||
| R |
Address : 0x1b900fb4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_lsr | |||
| apbcom_authstatus |
|
|||
| R |
Address : 0x1b900fb8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_authstatus | |||
| apbcom_devarch |
|
|||
| R |
Address : 0x1b900fbc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | value |
|||
| apbcom_devid2 |
|
|||
| R |
Address : 0x1b900fc0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | value |
|||
| apbcom_devid1 |
|
|||
| R |
Address : 0x1b900fc4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | value |
|||
| apbcom_devid |
|
|||
| R |
Address : 0x1b900fc8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | - |
reserved | ||
| 6 | cp |
|
||
| 5 | prr |
|
||
| 4 | sysmem |
|
||
| 3 - 0 | format |
|
||
| apbcom_devtype |
|
|||
| R |
Address : 0x1b900fcc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | value |
|||
| apbcom_pidr4 |
|
|||
| R |
Address : 0x1b900fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| apbcom_pidr5 |
|
|||
| R |
Address : 0x1b900fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_pidr5 | |||
| apbcom_pidr6 |
|
|||
| R |
Address : 0x1b900fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_pidr6 | |||
| apbcom_pidr7 |
|
|||
| R |
Address : 0x1b900fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | apbcom_pidr7 | |||
| apbcom_pidr0 |
|
|||
| R |
Address : 0x1b900fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| apbcom_pidr1 |
|
|||
| R |
Address : 0x1b900fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| apbcom_pidr2 |
|
|||
| R |
Address : 0x1b900fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| apbcom_pidr3 |
|
|||
| R |
Address : 0x1b900fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| apbcom_cidr0 |
|
|||
| R |
Address : 0x1b900ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| apbcom_cidr1 |
|
|||
| R |
Address : 0x1b900ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| apbcom_cidr2 |
|
|||
| R |
Address : 0x1b900ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| apbcom_cidr3 |
|
|||
| R |
Address : 0x1b900ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| gic_distributor_gicd_ctlr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_ctlr | ||
| gic_distributor_gicd_typer |
|
|||
| R |
Address : 0x1c010004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 11 | lspi |
|
||
| 10 | securityextn |
|
||
| 9 - 8 | - |
reserved | ||
| 7 - 5 | cpunumber |
|
||
| 4 - 0 | itlinesnumber |
|
||
| gic_distributor_gicd_iidr |
|
|||
| R |
Address : 0x1c010008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | productid |
|
||
| 23 - 20 | - |
reserved | ||
| 19 - 16 | variant |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| gic_distributor_gicd_igroupr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_igroupr0 | ||
| gic_distributor_gicd_igroupr15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0100bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_igroupr15 | ||
| gic_distributor_gicd_isenabler0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_isenabler0 | ||
| gic_distributor_gicd_isenabler15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c01013c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_isenabler15 | ||
| gic_distributor_gicd_icenabler0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010180 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icenabler0 | ||
| gic_distributor_gicd_icenabler15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0101bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icenabler15 | ||
| gic_distributor_gicd_ispendr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010200 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_ispendr0 | ||
| gic_distributor_gicd_ispendr15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c01023c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_ispendr15 | ||
| gic_distributor_gicd_icpendr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010280 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icpendr0 | ||
| gic_distributor_gicd_icpendr15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0102bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icpendr15 | ||
| gic_distributor_gicd_isactiver0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010300 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_isactiver0 | ||
| gic_distributor_gicd_isactiver15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c01033c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_isactiver15 | ||
| gic_distributor_gicd_icactiver0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010380 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icactiver0 | ||
| gic_distributor_gicd_icactiver15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0103bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icactiver15 | ||
| gic_distributor_gicd_ipriorityr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_ipriorityr0 | ||
| gic_distributor_gicd_ipriorityr127 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0105fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_ipriorityr127 | ||
| gic_distributor_gicd_itargetsr0 |
|
|||
| R |
Address : 0x1c010800 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_itargetsr0 | |||
| gic_distributor_gicd_itargetsr127 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c0109fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_itargetsr127 | ||
| gic_distributor_gicd_icfgr0 |
|
|||
| R |
Address : 0x1c010c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_icfgr0 | |||
| gic_distributor_gicd_icfgr15 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010c3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_icfgr15 | ||
| gic_distributor_gicd_ppisr |
|
|||
| R |
Address : 0x1c010d00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_ppisr | |||
| gic_distributor_gicd_spisr0 |
|
|||
| R |
Address : 0x1c010d04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_spisr0 | |||
| gic_distributor_gicd_spisr14 |
|
|||
| R |
Address : 0x1c010d3c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_spisr14 | |||
| gic_distributor_gicd_sgir |
|
|||
| W |
0x00000000 |
Address : 0x1c010f00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_sgir | ||
| gic_distributor_gicd_cpendsgir0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_cpendsgir0 | ||
| gic_distributor_gicd_cpendsgir1 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_cpendsgir1 | ||
| gic_distributor_gicd_cpendsgir2 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_cpendsgir2 | ||
| gic_distributor_gicd_cpendsgir3 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_cpendsgir3 | ||
| gic_distributor_gicd_spendsgir0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_spendsgir0 | ||
| gic_distributor_gicd_spendsgir1 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_spendsgir1 | ||
| gic_distributor_gicd_spendsgir2 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_spendsgir2 | ||
| gic_distributor_gicd_spendsgir3 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c010f2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_distributor_gicd_spendsgir3 | ||
| gic_distributor_gicd_pidr4 |
|
|||
| R |
Address : 0x1c010fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| gic_distributor_gicd_pidr5 |
|
|||
| R |
Address : 0x1c010fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_pidr5 | |||
| gic_distributor_gicd_pidr6 |
|
|||
| R |
Address : 0x1c010fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_pidr6 | |||
| gic_distributor_gicd_pidr7 |
|
|||
| R |
Address : 0x1c010fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_distributor_gicd_pidr7 | |||
| gic_distributor_gicd_pidr0 |
|
|||
| R |
Address : 0x1c010fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| gic_distributor_gicd_pidr1 |
|
|||
| R |
Address : 0x1c010fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| gic_distributor_gicd_pidr2 |
|
|||
| R |
Address : 0x1c010fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| gic_distributor_gicd_pidr3 |
|
|||
| R |
Address : 0x1c010fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| gic_distributor_gicd_cidr0 |
|
|||
| R |
Address : 0x1c010ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| gic_distributor_gicd_cidr1 |
|
|||
| R |
Address : 0x1c010ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| gic_distributor_gicd_cidr2 |
|
|||
| R |
Address : 0x1c010ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| gic_distributor_gicd_cidr3 |
|
|||
| R |
Address : 0x1c010ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gic_cpu_interface_gicc_ctlr |
| 1 | 4 | R/W | gic_cpu_interface_gicc_pmr |
| 2 | 8 | R/W | gic_cpu_interface_gicc_bpr |
| 3 | c | R | gic_cpu_interface_gicc_iar |
| 4 | 10 | W | gic_cpu_interface_gicc_eoir |
| 5 | 14 | R | gic_cpu_interface_gicc_rpr |
| 6 | 18 | R | gic_cpu_interface_gicc_hppir |
| 7 | 1c | R/W | gic_cpu_interface_gicc_abpr |
| 8 | 20 | R | gic_cpu_interface_gicc_aiar |
| 9 | 24 | W | gic_cpu_interface_gicc_aeoir |
| a | 28 | R | gic_cpu_interface_gicc_ahppir |
| b-33 | 2c-cc | - | reserved |
| 34 | d0 | R/W | gic_cpu_interface_gicc_apr0 |
| 35-37 | d4-dc | - | reserved |
| 38 | e0 | R/W | gic_cpu_interface_gicc_nsapr0 |
| 39-3e | e4-f8 | - | reserved |
| 3f | fc | R | gic_cpu_interface_gicc_iidr |
| 40-3ff | 100-ffc | - | reserved |
| gic_cpu_interface_gicc_ctlr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_ctlr | ||
| gic_cpu_interface_gicc_pmr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_pmr | ||
| gic_cpu_interface_gicc_bpr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_bpr | ||
| gic_cpu_interface_gicc_iar |
|
|||
| R |
Address : 0x1c02f00c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_cpu_interface_gicc_iar | |||
| gic_cpu_interface_gicc_eoir |
|
|||
| W |
0x00000000 |
Address : 0x1c02f010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_eoir | ||
| gic_cpu_interface_gicc_rpr |
|
|||
| R |
Address : 0x1c02f014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_cpu_interface_gicc_rpr | |||
| gic_cpu_interface_gicc_hppir |
|
|||
| R |
Address : 0x1c02f018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_cpu_interface_gicc_hppir | |||
| gic_cpu_interface_gicc_abpr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f01c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_abpr | ||
| gic_cpu_interface_gicc_aiar |
|
|||
| R |
Address : 0x1c02f020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_cpu_interface_gicc_aiar | |||
| gic_cpu_interface_gicc_aeoir |
|
|||
| W |
0x00000000 |
Address : 0x1c02f024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_aeoir | ||
| gic_cpu_interface_gicc_ahppir |
|
|||
| R |
Address : 0x1c02f028 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_cpu_interface_gicc_ahppir | |||
| gic_cpu_interface_gicc_apr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f0d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_apr0 | ||
| gic_cpu_interface_gicc_nsapr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c02f0e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_cpu_interface_gicc_nsapr0 | ||
| gic_cpu_interface_gicc_iidr |
|
|||
| R |
Address : 0x1c02f0fc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | productid |
|
||
| 19 - 16 | arch_version |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gic_virt_interface_ctrl_gich_hcr |
| 1 | 4 | R | gic_virt_interface_ctrl_gich_vtr |
| 2 | 8 | R/W | gic_virt_interface_ctrl_gich_vmcr |
| 3 | c | - | reserved |
| 4 | 10 | R | gic_virt_interface_ctrl_gich_misr |
| 5-7 | 14-1c | - | reserved |
| 8 | 20 | R | gic_virt_interface_ctrl_gich_eisr0 |
| 9-b | 24-2c | - | reserved |
| c | 30 | R | gic_virt_interface_ctrl_gich_elsr0 |
| d-3b | 34-ec | - | reserved |
| 3c | f0 | R/W | gic_virt_interface_ctrl_gich_apr0 |
| 3d-3f | f4-fc | - | reserved |
| 40 | 100 | R/W | gic_virt_interface_ctrl_gich_lr0 |
| 41 | 104 | R/W | gic_virt_interface_ctrl_gich_lr1 |
| 42 | 108 | R/W | gic_virt_interface_ctrl_gich_lr2 |
| 43 | 10c | R/W | gic_virt_interface_ctrl_gich_lr3 |
| 44-3ff | 110-ffc | - | reserved |
| gic_virt_interface_ctrl_gich_hcr |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f000 Address@app_gic_virt_interface_ctrl_alias : 0x1c050000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_hcr | ||
| gic_virt_interface_ctrl_gich_vtr |
|
|||
| R |
Address@app_gic_virt_interface_ctrl : 0x1c04f004 Address@app_gic_virt_interface_ctrl_alias : 0x1c050004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 29 | pribits |
|
||
| 28 - 26 | prebits |
|
||
| 25 - 6 | - |
reserved | ||
| 5 - 0 | listregs |
|
||
| gic_virt_interface_ctrl_gich_vmcr |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f008 Address@app_gic_virt_interface_ctrl_alias : 0x1c050008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_vmcr | ||
| gic_virt_interface_ctrl_gich_misr |
|
|||
| R |
Address@app_gic_virt_interface_ctrl : 0x1c04f010 Address@app_gic_virt_interface_ctrl_alias : 0x1c050010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_interface_ctrl_gich_misr | |||
| gic_virt_interface_ctrl_gich_eisr0 |
|
|||
| R |
Address@app_gic_virt_interface_ctrl : 0x1c04f020 Address@app_gic_virt_interface_ctrl_alias : 0x1c050020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_interface_ctrl_gich_eisr0 | |||
| gic_virt_interface_ctrl_gich_elsr0 |
|
|||
| R |
Address@app_gic_virt_interface_ctrl : 0x1c04f030 Address@app_gic_virt_interface_ctrl_alias : 0x1c050030 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_interface_ctrl_gich_elsr0 | |||
| gic_virt_interface_ctrl_gich_apr0 |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f0f0 Address@app_gic_virt_interface_ctrl_alias : 0x1c0500f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_apr0 | ||
| gic_virt_interface_ctrl_gich_lr0 |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f100 Address@app_gic_virt_interface_ctrl_alias : 0x1c050100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_lr0 | ||
| gic_virt_interface_ctrl_gich_lr1 |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f104 Address@app_gic_virt_interface_ctrl_alias : 0x1c050104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_lr1 | ||
| gic_virt_interface_ctrl_gich_lr2 |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f108 Address@app_gic_virt_interface_ctrl_alias : 0x1c050108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_lr2 | ||
| gic_virt_interface_ctrl_gich_lr3 |
|
|||
| R/W |
0x00000000 |
Address@app_gic_virt_interface_ctrl : 0x1c04f10c Address@app_gic_virt_interface_ctrl_alias : 0x1c05010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_interface_ctrl_gich_lr3 | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gic_virt_cpu_interface_gicv_ctlr |
| 1 | 4 | R/W | gic_virt_cpu_interface_gicv_pmr |
| 2 | 8 | R/W | gic_virt_cpu_interface_gicv_bpr |
| 3 | c | R | gic_virt_cpu_interface_gicv_iar |
| 4 | 10 | W | gic_virt_cpu_interface_gicv_eoir |
| 5 | 14 | R | gic_virt_cpu_interface_gicv_rpr |
| 6 | 18 | R | gic_virt_cpu_interface_gicv_hppir |
| 7 | 1c | R/W | gic_virt_cpu_interface_gicv_abpr |
| 8 | 20 | R | gic_virt_cpu_interface_gicv_aiar |
| 9 | 24 | W | gic_virt_cpu_interface_gicv_aeoir |
| a | 28 | R | gic_virt_cpu_interface_gicv_ahppir |
| b-33 | 2c-cc | - | reserved |
| 34 | d0 | R/W | gic_virt_cpu_interface_gicv_apr0 |
| 35-3e | d4-f8 | - | reserved |
| 3f | fc | R | gic_virt_cpu_interface_gicv_iidr |
| 40-3ff | 100-ffc | - | reserved |
| gic_virt_cpu_interface_gicv_ctlr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c06f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_ctlr | ||
| gic_virt_cpu_interface_gicv_pmr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c06f004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_pmr | ||
| gic_virt_cpu_interface_gicv_bpr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c06f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_bpr | ||
| gic_virt_cpu_interface_gicv_iar |
|
|||
| R |
Address : 0x1c06f00c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_cpu_interface_gicv_iar | |||
| gic_virt_cpu_interface_gicv_eoir |
|
|||
| W |
0x00000000 |
Address : 0x1c06f010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_eoir | ||
| gic_virt_cpu_interface_gicv_rpr |
|
|||
| R |
Address : 0x1c06f014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_cpu_interface_gicv_rpr | |||
| gic_virt_cpu_interface_gicv_hppir |
|
|||
| R |
Address : 0x1c06f018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_cpu_interface_gicv_hppir | |||
| gic_virt_cpu_interface_gicv_abpr |
|
|||
| R/W |
0x00000000 |
Address : 0x1c06f01c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_abpr | ||
| gic_virt_cpu_interface_gicv_aiar |
|
|||
| R |
Address : 0x1c06f020 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_cpu_interface_gicv_aiar | |||
| gic_virt_cpu_interface_gicv_aeoir |
|
|||
| W |
0x00000000 |
Address : 0x1c06f024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_aeoir | ||
| gic_virt_cpu_interface_gicv_ahppir |
|
|||
| R |
Address : 0x1c06f028 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | gic_virt_cpu_interface_gicv_ahppir | |||
| gic_virt_cpu_interface_gicv_apr0 |
|
|||
| R/W |
0x00000000 |
Address : 0x1c06f0d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
gic_virt_cpu_interface_gicv_apr0 | ||
| gic_virt_cpu_interface_gicv_iidr |
|
|||
| R |
Address : 0x1c06f0fc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | productid |
|
||
| 19 - 16 | arch_version |
|
||
| 15 - 12 | revision |
|
||
| 11 - 0 | implementer |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | W | main_nic_gpv_remap |
| 1 | 4 | - | reserved |
| 2 | 8 | W | main_nic_gpv_security0 |
| 3-40 | c-100 | - | reserved |
| 41 | 104 | W | main_nic_gpv_security63 |
| 42-7f3 | 108-1fcc | - | reserved |
| 7f4 | 1fd0 | R | main_nic_gpv_pidr4 |
| 7f5 | 1fd4 | R | main_nic_gpv_pidr5 |
| 7f6 | 1fd8 | R | main_nic_gpv_pidr6 |
| 7f7 | 1fdc | R | main_nic_gpv_pidr7 |
| 7f8 | 1fe0 | R | main_nic_gpv_pidr0 |
| 7f9 | 1fe4 | R | main_nic_gpv_pidr1 |
| 7fa | 1fe8 | R | main_nic_gpv_pidr2 |
| 7fb | 1fec | R | main_nic_gpv_pidr3 |
| 7fc | 1ff0 | R | main_nic_gpv_cidr0 |
| 7fd | 1ff4 | R | main_nic_gpv_cidr1 |
| 7fe | 1ff8 | R | main_nic_gpv_cidr2 |
| 7ff | 1ffc | R | main_nic_gpv_cidr3 |
| 800-3ffff | 2000-ffffc | - | reserved |
| main_nic_gpv_remap |
|
|||
| W |
0x00000000 |
Address : 0x1e000000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
main_nic_gpv_remap | ||
| main_nic_gpv_security0 |
|
|||
| W |
0x00000000 |
Address : 0x1e000008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
main_nic_gpv_security0 | ||
| main_nic_gpv_security63 |
|
|||
| W |
0x00000000 |
Address : 0x1e000104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
main_nic_gpv_security63 | ||
| main_nic_gpv_pidr4 |
|
|||
| R |
Address : 0x1e001fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| main_nic_gpv_pidr5 |
|
|||
| R |
Address : 0x1e001fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | main_nic_gpv_pidr5 | |||
| main_nic_gpv_pidr6 |
|
|||
| R |
Address : 0x1e001fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | main_nic_gpv_pidr6 | |||
| main_nic_gpv_pidr7 |
|
|||
| R |
Address : 0x1e001fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | main_nic_gpv_pidr7 | |||
| main_nic_gpv_pidr0 |
|
|||
| R |
Address : 0x1e001fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| main_nic_gpv_pidr1 |
|
|||
| R |
Address : 0x1e001fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| main_nic_gpv_pidr2 |
|
|||
| R |
Address : 0x1e001fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| main_nic_gpv_pidr3 |
|
|||
| R |
Address : 0x1e001fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| main_nic_gpv_cidr0 |
|
|||
| R |
Address : 0x1e001ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| main_nic_gpv_cidr1 |
|
|||
| R |
Address : 0x1e001ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| main_nic_gpv_cidr2 |
|
|||
| R |
Address : 0x1e001ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| main_nic_gpv_cidr3 |
|
|||
| R |
Address : 0x1e001ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| cryptocell_misc_aes_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f000810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| cryptocell_misc_hash_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f000818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| cryptocell_misc_pka_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f00081c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| cryptocell_misc_dma_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f000820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| cryptocell_misc_clk_status |
|
|||
| R |
Address : 0x2f000824 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | dma_clk_status |
|||
| 7 | chacha_clk_status |
|||
| 6 - 4 | - |
reserved | ||
| 3 | pka_clk_status |
|||
| 2 | hash_clk_status |
|||
| 1 | - |
reserved | ||
| 0 | aes_clk_status |
|||
| cryptocell_misc_chacha_clk_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f000858 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| cryptocell_host_core_clk_gating_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x2f000a78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
host_core_clk_gating_enable |
|
|
| cryptocell_host_dcu_en0 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_en0 | ||
| cryptocell_host_dcu_en1 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_en1 | ||
| cryptocell_host_dcu_en2 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_en2 | ||
| cryptocell_host_dcu_en3 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_en3 | ||
| cryptocell_host_dcu_lock0 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_lock0 | ||
| cryptocell_host_dcu_lock1 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_lock1 | ||
| cryptocell_host_dcu_lock2 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_lock2 | ||
| cryptocell_host_dcu_lock3 |
|
|||
| R/W |
0x00000000 |
Address : 0x2f001e1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_dcu_lock3 | ||
| cryptocell_aib_fuse_prog_completed |
|
|||
| R |
Address : 0x2f001f04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | aib_fuse_prog_completed |
|
||
| cryptocell_nvm_debug_status |
|
|||
| R |
Address : 0x2f001f08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 - 1 | nvm_sm |
|
||
| 0 | - |
reserved | ||
| cryptocell_lcs_is_valid |
|
|||
| R |
Address : 0x2f001f0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | lcs_is_valid_reg |
|
||
| cryptocell_nvm_is_idle |
|
|||
| R |
Address : 0x2f001f10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | nvm_is_idle_reg |
|
||
| cryptocell_lcs_reg |
|
|||
| R |
Address : 0x2f001f14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 | error_kceicv_zero_cnt |
|
||
| 11 | error_kpicv_zero_cnt |
|
||
| 10 | error_kce_zero_cnt |
|
||
| 9 | error_prov_zero_cnt |
|
||
| 8 | error_kdr_zero_cnt |
|
||
| 7 - 3 | - |
reserved | ||
| 2 - 0 | lcs_reg |
|
||
| cryptocell_host_shadow_kdr_reg | |||
| W |
0x00000000 |
Address : 0x2f001f18 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_shadow_kdr_reg | |
| cryptocell_host_shadow_kcp_reg | |||
| W |
0x00000000 |
Address : 0x2f001f1c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_shadow_kcp_reg | |
| cryptocell_host_shadow_kce_reg | |||
| W |
0x00000000 |
Address : 0x2f001f20 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_shadow_kce_reg | |
| cryptocell_host_shadow_kpicv_reg | |||
| W |
0x00000000 |
Address : 0x2f001f24 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_shadow_kpicv_reg | |
| cryptocell_host_shadow_kceicv_reg | |||
| W |
0x00000000 |
Address : 0x2f001f28 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_host_shadow_kceicv_reg | |
| cryptocell_otp_addr_width_def | |||
| R |
Address : 0x2f001f2c |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | cryptocell_otp_addr_width_def | ||
| cryptocell_nvm_base |
|
|||
| R/W |
0x00000000 |
Address : 0x2f002000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cryptocell_nvm_base | ||
| cryptocell_nvm_end | |||
|
Address : 0x2f003ffc |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | cryptocell_nvm_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | otp_ctrl_cfg |
| 1 | 4 | R | otp_ctrl_status |
| 2 | 8 | R/W | otp_ctrl_timings_power0 |
| 3 | c | R/W | otp_ctrl_timings_power1 |
| 4 | 10 | R/W | otp_ctrl_timings_power2 |
| 5 | 14 | R/W | otp_ctrl_timings_power3 |
| 6 | 18 | R/W | otp_ctrl_timings_read0 |
| 7 | 1c | R/W | otp_ctrl_timings_read1 |
| 8 | 20 | R/W | otp_ctrl_timings_read2 |
| 9 | 24 | R/W | otp_ctrl_timings_program0 |
| a | 28 | R/W | otp_ctrl_timings_program1 |
| b | 2c | R/W | otp_ctrl_timings_program2 |
| c | 30 | R/W | otp_ctrl_timings_program3 |
| d-3f | 34-fc | - | reserved |
| otp_ctrl_cfg |
|
|||
| R/W |
0x00000000 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004000 Address@secenc_otp_ctrl0 : 0x5001c000 Address@secenc_otp_ctrl1 : 0x5001d000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
disable_auto_standby |
|
|
| 2 | "0" |
disable_pprog_multi_writes |
|
|
| 1 | "0" |
disable_skip_unprog |
|
|
| 0 | "0" |
disable_rmw |
|
|
| otp_ctrl_status |
|
|||
| R |
Address@secenc_cryptocell_otp_ctrl : 0x2f004004 Address@secenc_otp_ctrl0 : 0x5001c004 Address@secenc_otp_ctrl1 : 0x5001d004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 2 | ip_fsm_state |
|
||
| 1 | disable_auto_standby_until_first_access |
|
||
| 0 | auto_leave_standby_after_reset |
|
||
| otp_ctrl_timings_power0 |
|
|||||||
| R/W |
0x000000c8 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004008 Address@secenc_otp_ctrl0 : 0x5001c008 Address@secenc_otp_ctrl1 : 0x5001d008 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||
| 19 - 16 | "0000" |
t_penh |
|
|||||
| 15 - 10 | 0 |
- |
reserved | |||||
| 9 - 0 | 0xc8 |
t_pens |
|
|||||
| otp_ctrl_timings_power1 |
|
|||||||
| R/W |
0x00020190 |
Address@secenc_cryptocell_otp_ctrl : 0x2f00400c Address@secenc_otp_ctrl0 : 0x5001c00c Address@secenc_otp_ctrl1 : 0x5001d00c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||
| 19 - 16 | "0010" |
t_ash |
|
|||||
| 15 - 10 | 0 |
- |
reserved | |||||
| 9 - 0 | 0x190 |
t_sas |
|
|||||
| otp_ctrl_timings_power2 |
|
|||||||
| R/W |
0x00002710 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004010 Address@secenc_otp_ctrl0 : 0x5001c010 Address@secenc_otp_ctrl1 : 0x5001d010 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||
| 15 - 0 | 0x2710 |
t_tas |
|
|||||
| otp_ctrl_timings_power3 |
|
|||||||
| R/W |
0x4e1f031f |
Address@secenc_cryptocell_otp_ctrl : 0x2f004014 Address@secenc_otp_ctrl0 : 0x5001c014 Address@secenc_otp_ctrl1 : 0x5001d014 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x4e1f |
auto_standby_inactivity_cycles |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x31f |
auto_deep_standby_inactivity_cycles |
|
|||||
| otp_ctrl_timings_read0 |
|
|||||||
| R/W |
0x000207d0 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004018 Address@secenc_otp_ctrl0 : 0x5001c018 Address@secenc_otp_ctrl1 : 0x5001d018 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||
| 19 - 16 | "0010" |
t_as |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x7d0 |
t_cs |
|
|||||
| otp_ctrl_timings_read1 |
|
|||||||
| R/W |
0x00000155 |
Address@secenc_cryptocell_otp_ctrl : 0x2f00401c Address@secenc_otp_ctrl0 : 0x5001c01c Address@secenc_otp_ctrl1 : 0x5001d01c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||
| 12 - 8 | "00001" |
t_dout_sample_pre_kl_end |
|
|||||
| 7 - 4 | "0101" |
t_kl |
|
|||||
| 3 - 0 | "0101" |
t_kh |
|
|||||
| otp_ctrl_timings_read2 |
|
|||||||
| R/W |
0x000927bf |
Address@secenc_cryptocell_otp_ctrl : 0x2f004020 Address@secenc_otp_ctrl0 : 0x5001c020 Address@secenc_otp_ctrl1 : 0x5001d020 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||
| 19 - 0 | 0x927bf |
read_selected_inactivity_cycles |
|
|||||
| otp_ctrl_timings_program0 |
|
|||||||
| R/W |
0x000307d0 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004024 Address@secenc_otp_ctrl0 : 0x5001c024 Address@secenc_otp_ctrl1 : 0x5001d024 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||
| 19 - 16 | "0011" |
t_asp |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x7d0 |
t_csp |
|
|||||
| otp_ctrl_timings_program1 |
|
|||||||
| R/W |
0x03e807d0 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004028 Address@secenc_otp_ctrl0 : 0x5001c028 Address@secenc_otp_ctrl1 : 0x5001d028 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |||||
| 27 - 16 | 0x3e8 |
t_ppr |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x7d0 |
t_pps |
|
|||||
| otp_ctrl_timings_program2 |
|
|||||||
| R/W |
0x00c807d0 |
Address@secenc_cryptocell_otp_ctrl : 0x2f00402c Address@secenc_otp_ctrl0 : 0x5001c02c Address@secenc_otp_ctrl1 : 0x5001d02c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |||||
| 25 - 16 | 0xc8 |
t_pwi |
|
|||||
| 15 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x7d0 |
t_pw |
|
|||||
| otp_ctrl_timings_program3 |
|
|||||||
| R/W |
0x00000320 |
Address@secenc_cryptocell_otp_ctrl : 0x2f004030 Address@secenc_otp_ctrl0 : 0x5001c030 Address@secenc_otp_ctrl1 : 0x5001d030 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |||||
| 11 - 0 | 0x320 |
t_pph_minus_pwi |
|
|||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | secenc_ram_base |
| 1-1fffe | 4-7fff8 | - | reserved |
| 1ffff | 7fffc | R/W | secenc_ram_end |
| secenc_ram_base |
|
|||
| R/W |
0x00000000 |
Address : 0x30000000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
secenc_ram_base | ||
| secenc_ram_end |
|
|||
| R/W |
0x00000000 |
Address : 0x3007fffc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
secenc_ram_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sqi_cr0 |
| 1 | 4 | R/W | sqi_cr1 |
| 2 | 8 | R/W | sqi_dr |
| 3 | c | R | sqi_sr |
| 4 | 10 | R/W | sqi_tcr |
| 5 | 14 | R/W | sqi_irq_mask |
| 6 | 18 | R | sqi_irq_raw |
| 7 | 1c | R | sqi_irq_masked |
| 8 | 20 | R/W | sqi_irq_clear |
| 9 | 24 | R/W | sqi_dmacr |
| a | 28 | R/W | sqi_pio_out |
| b | 2c | - | reserved |
| c | 30 | R/W | sqi_pio_oe |
| d | 34 | R | sqi_pio_in |
| e | 38 | R/W | sqi_sqirom_cfg |
| f | 3c | - | reserved |
| sqi_cr0 |
|
|||||||||||
| R/W |
0x00080007 |
Address@sqi : 0x40010000 Address@app_sqi0 : 0x40080480 Address@app_sqi1 : 0x400804c0 Address@mot_sqi0 : 0x49200480 Address@mot_sqi1 : 0x492004c0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |||||||||
| 27 | "0" |
filter_in |
|
|||||||||
| 26 - 24 | 0 |
- |
reserved | |||||||||
| 23 - 22 | "00" |
sio_cfg |
|
|||||||||
| 21 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 8 | 0x800 |
sck_muladd |
|
|||||||||
| 7 | "0" |
sck_phase |
|
|||||||||
| 6 | "0" |
sck_pol |
|
|||||||||
| 5 - 4 | 0 |
- |
reserved | |||||||||
| 3 - 0 | "0111" |
datasize |
|
|||||||||
| sqi_cr1 |
|
||||||||
| R/W |
0x08080000 |
Address@sqi : 0x40010004 Address@app_sqi0 : 0x40080484 Address@app_sqi1 : 0x400804c4 Address@mot_sqi0 : 0x49200484 Address@mot_sqi1 : 0x492004c4 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | ||||||
| 28 | "0" |
rx_fifo_clr |
|
||||||
| 27 - 24 | "1000" |
rx_fifo_wm |
|
||||||
| 23 - 21 | 0 |
- |
reserved | ||||||
| 20 | "0" |
tx_fifo_clr |
|
||||||
| 19 - 16 | "1000" |
tx_fifo_wm |
|
||||||
| 15 - 13 | 0 |
- |
reserved | ||||||
| 12 | "0" |
spi_trans_ctrl |
|
||||||
| 11 | "0" |
fss_static |
|
||||||
| 10 - 8 | "000" |
fss |
|
||||||
| 7 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
sqi_en |
|
||||||
| 0 | 0 |
- |
reserved | ||||||
| sqi_dr |
|
|||
| R/W |
0x00000000 |
Address@sqi : 0x40010008 Address@app_sqi0 : 0x40080488 Address@app_sqi1 : 0x400804c8 Address@mot_sqi0 : 0x49200488 Address@mot_sqi1 : 0x492004c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| sqi_sr |
|
|||
| R |
Address@sqi : 0x4001000c Address@app_sqi0 : 0x4008048c Address@app_sqi1 : 0x400804cc Address@mot_sqi0 : 0x4920048c Address@mot_sqi1 : 0x492004cc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | rx_fifo_err_undr |
|
||
| 30 | rx_fifo_err_ovfl |
|
||
| 29 | - |
reserved | ||
| 28 - 24 | rx_fifo_level |
|
||
| 23 | tx_fifo_err_undr |
|
||
| 22 | tx_fifo_err_ovfl |
|
||
| 21 | - |
reserved | ||
| 20 - 16 | tx_fifo_level |
|
||
| 15 | sqirom_disabled_err |
|
||
| 14 | sqirom_write_err |
|
||
| 13 | sqirom_timeout_err |
|
||
| 12 - 5 | - |
reserved | ||
| 4 | busy |
|
||
| 3 | rx_fifo_full |
|
||
| 2 | rx_fifo_not_empty |
|
||
| 1 | tx_fifo_not_full |
|
||
| 0 | tx_fifo_empty |
|
||
| sqi_tcr |
|
||||||||||||
| R/W |
0x1c000000 |
Address@sqi : 0x40010010 Address@app_sqi0 : 0x40080490 Address@app_sqi1 : 0x400804d0 Address@mot_sqi0 : 0x49200490 Address@mot_sqi1 : 0x492004d0 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | ||||||||||
| 29 | "0" |
ms_byte_first |
|
||||||||||
| 28 | "1" |
ms_bit_first |
|
||||||||||
| 27 - 26 | "11" |
duplex |
|
||||||||||
| 25 - 24 | "00" |
mode |
|
||||||||||
| 23 | "0" |
start_transfer |
|
||||||||||
| 22 | "0" |
tx_oe |
|
||||||||||
| 21 | "0" |
tx_out |
|
||||||||||
| 20 - 19 | 0 |
- |
reserved | ||||||||||
| 18 - 0 | 0x0 |
transfer_size |
|
||||||||||
| sqi_irq_mask |
|
|||
| R/W |
0x00000000 |
Address@sqi : 0x40010014 Address@app_sqi0 : 0x40080494 Address@app_sqi1 : 0x400804d4 Address@mot_sqi0 : 0x49200494 Address@mot_sqi1 : 0x492004d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sqirom_error |
|
|
| 7 | "0" |
trans_end |
|
|
| 6 | "0" |
txeim |
|
|
| 5 | "0" |
rxfim |
|
|
| 4 | "0" |
rxneim |
|
|
| 3 | "0" |
TXIM |
|
|
| 2 | "0" |
RXIM |
|
|
| 1 | "0" |
RTIM |
|
|
| 0 | "0" |
RORIM |
|
|
| sqi_irq_raw |
|
||||||||
| R |
Address@sqi : 0x40010018 Address@app_sqi0 : 0x40080498 Address@app_sqi1 : 0x400804d8 Address@mot_sqi0 : 0x49200498 Address@mot_sqi1 : 0x492004d8 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | - |
reserved | |||||||
| 8 | sqirom_error |
|
|||||||
| 7 | trans_end |
|
|||||||
| 6 | txeris |
|
|||||||
| 5 | rxfris |
|
|||||||
| 4 | rxneris |
|
|||||||
| 3 | TXRIS |
|
|||||||
| 2 | RXRIS |
|
|||||||
| 1 | RTRIS |
|
|||||||
| 0 | RORRIS |
|
|||||||
| sqi_irq_masked |
|
|||
| R |
Address@sqi : 0x4001001c Address@app_sqi0 : 0x4008049c Address@app_sqi1 : 0x400804dc Address@mot_sqi0 : 0x4920049c Address@mot_sqi1 : 0x492004dc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | sqirom_error |
|
||
| 7 | trans_end |
|
||
| 6 | txemis |
|
||
| 5 | rxfmis |
|
||
| 4 | rxnemis |
|
||
| 3 | TXMIS |
|
||
| 2 | RXMIS |
|
||
| 1 | RTMIS |
|
||
| 0 | RORMIS |
|
||
| sqi_irq_clear |
|
|||
| R/W |
0x00000000 |
Address@sqi : 0x40010020 Address@app_sqi0 : 0x400804a0 Address@app_sqi1 : 0x400804e0 Address@mot_sqi0 : 0x492004a0 Address@mot_sqi1 : 0x492004e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sqirom_error |
|
|
| 7 | "0" |
trans_end |
|
|
| 6 | "0" |
txeic |
|
|
| 5 | "0" |
rxfic |
|
|
| 4 | "0" |
rxneic |
|
|
| 3 | "0" |
TXIC |
|
|
| 2 | "0" |
RXIC |
|
|
| 1 | "0" |
RTIC |
|
|
| 0 | "0" |
RORIC |
|
|
| sqi_dmacr |
|
|||
| R/W |
0x00000000 |
Address@sqi : 0x40010024 Address@app_sqi0 : 0x400804a4 Address@app_sqi1 : 0x400804e4 Address@mot_sqi0 : 0x492004a4 Address@mot_sqi1 : 0x492004e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
tx_dma_en |
|
|
| 0 | "0" |
rx_dma_en |
|
|
| sqi_pio_out |
|
|||
| R/W |
0x0000000e |
Address@sqi : 0x40010028 Address@app_sqi0 : 0x400804a8 Address@app_sqi1 : 0x400804e8 Address@mot_sqi0 : 0x492004a8 Address@mot_sqi1 : 0x492004e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
sio3 |
|
|
| 6 | "0" |
sio2 |
|
|
| 5 | "0" |
miso |
|
|
| 4 | "0" |
mosi |
|
|
| 3 - 1 | "111" |
csn |
|
|
| 0 | "0" |
sclk |
|
|
| sqi_pio_oe |
|
|||
| R/W |
0x00000000 |
Address@sqi : 0x40010030 Address@app_sqi0 : 0x400804b0 Address@app_sqi1 : 0x400804f0 Address@mot_sqi0 : 0x492004b0 Address@mot_sqi1 : 0x492004f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
sio3 |
|
|
| 6 | "0" |
sio2 |
|
|
| 5 | "0" |
miso |
|
|
| 4 | "0" |
mosi |
|
|
| 3 - 1 | "000" |
csn |
|
|
| 0 | "0" |
sclk |
|
|
| sqi_pio_in |
|
|||
| R |
Address@sqi : 0x40010034 Address@app_sqi0 : 0x400804b4 Address@app_sqi1 : 0x400804f4 Address@mot_sqi0 : 0x492004b4 Address@mot_sqi1 : 0x492004f4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | sio3 |
|
||
| 6 | sio2 |
|
||
| 5 | miso |
|
||
| 4 | mosi |
|
||
| 3 - 1 | csn |
|
||
| 0 | sclk |
|
||
| sqi_sqirom_cfg |
|
|||||||||||||||||||
| R/W |
0x18020004 |
Address@sqi : 0x40010038 Address@app_sqi0 : 0x400804b8 Address@app_sqi1 : 0x400804f8 Address@mot_sqi0 : 0x492004b8 Address@mot_sqi1 : 0x492004f8 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00011000" |
clk_div_val |
|
|||||||||||||||||
| 23 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 20 | "00" |
t_csh |
|
|||||||||||||||||
| 19 - 16 | "0010" |
dummy_cycles |
|
|||||||||||||||||
| 15 - 8 | "00000000" |
cmd_byte |
|
|||||||||||||||||
| 7 | 0 |
- |
reserved | |||||||||||||||||
| 6 - 4 | "000" |
addr_bits |
|
|||||||||||||||||
| 3 - 2 | "01" |
addr_nibbles |
|
|||||||||||||||||
| 1 | "0" |
addr_before_cmd |
|
|||||||||||||||||
| 0 | "0" |
enable |
|
|||||||||||||||||
| global_asic_ctrl_netx_version (netx_version) |
|
||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000011 |
Address : 0x40030000 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x11 |
netx_version |
|
||||||||||||||||||||||||||||||||||||||||||||||||||
| global_asic_ctrl_netx_unique_id0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
id |
|
|
| global_asic_ctrl_netx_unique_id1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
id |
|
|
| global_asic_ctrl_netx_unique_id2 |
|
|||
| R/W |
0x00000000 |
Address : 0x4003000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
id |
|
|
| global_asic_ctrl_only_por |
|
|||
| R/W |
0x00000000 |
Address : 0x40030010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| global_asic_ctrl_system_status |
|
|||
| R |
Address : 0x40030014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | top_dftenable |
|
||
| 0 | testmode |
|
||
| global_asic_ctrl_rst_out_cfg (NETX_RESET_CTRL) |
|
|||
| R/W |
0x00000000 |
Address : 0x40030018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 | - |
rst_out_n_in_ro |
|
|
| 26 | "0" |
EN_RES_REQ_OUT |
|
|
| 25 | "0" |
RES_REQ_OUT |
|
|
| 24 - 0 | 0 |
- |
reserved | |
| global_asic_ctrl_io_voltage_cfg |
|
|||||||
| R/W |
0x00000000 |
Address : 0x4003001c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|||||
| 15 - 4 | 0 |
- |
reserved | |||||
| 3 | "0" |
pwr_grp5_v18 |
|
|||||
| 2 | "0" |
pwr_grp4_v18 |
|
|||||
| 1 | "0" |
pwr_grp3_v18 |
|
|||||
| 0 | "0" |
pwr_grp2_v18 |
|
|||||
| global_asic_ctrl_app_mmio_io_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_app_mmio0_15_wm |
|
|
| 15 - 0 | 0x0 |
sel_app_mmio0_15 |
|
|
| global_asic_ctrl_app_mmio_io_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_app_mmio16_31_wm |
|
|
| 15 - 0 | 0x0 |
sel_app_mmio16_31 |
|
|
| global_asic_ctrl_app_mmio_io_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_app_mmio32_47_wm |
|
|
| 15 - 0 | 0x0 |
sel_app_mmio32_47 |
|
|
| global_asic_ctrl_app_mmio_io_cfg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x4003002c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_app_mmio48_63_wm |
|
|
| 15 - 0 | 0x0 |
sel_app_mmio48_63 |
|
|
| global_asic_ctrl_app_mmio_io_cfg4 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 16 | 0x0 |
sel_app_mmio64_75_wm |
|
|
| 15 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
sel_app_mmio64_75 |
|
|
| global_asic_ctrl_app_pio_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 16 | 0x0 |
sel_app_pio_wm |
|
|
| 15 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
sel_app_pio |
|
|
| global_asic_ctrl_app_eth_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sel_app_sgmii_fx_sd_wm |
|
|
| 20 | "0" |
sel_app_mdio_rgmii_wm |
|
|
| 19 | "0" |
sel_app_mdio_sgmii_wm |
|
|
| 18 | "0" |
sel_app_mdc_wm |
|
|
| 17 | "0" |
sel_app_rgmii_1_wm |
|
|
| 16 | "0" |
sel_app_rgmii_0_wm |
|
|
| 15 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
sel_app_sgmii_fx_sd |
|
|
| 4 | "0" |
sel_app_mdio_rgmii |
|
|
| 3 | "0" |
sel_app_mdio_sgmii |
|
|
| 2 | "0" |
sel_app_mdc |
|
|
| 1 | "0" |
sel_app_rgmii_1 |
|
|
| 0 | "0" |
sel_app_rgmii_0 |
|
|
| global_asic_ctrl_app_biss_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x4003003c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
sel_app_biss1_mo_b_wm |
|
|
| 23 | "0" |
sel_app_biss1_mo_a_wm |
|
|
| 22 | "0" |
sel_app_biss1_b_wm |
|
|
| 21 | "0" |
sel_app_biss1_a_wm |
|
|
| 20 | "0" |
sel_app_biss1_wm |
|
|
| 19 | "0" |
sel_app_biss0_mo_b_wm |
|
|
| 18 | "0" |
sel_app_biss0_mo_a_wm |
|
|
| 17 | "0" |
sel_app_biss0_b_wm |
|
|
| 16 | "0" |
sel_app_biss0_a_wm |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sel_app_biss1_mo_b |
|
|
| 7 | "0" |
sel_app_biss1_mo_a |
|
|
| 6 | "0" |
sel_app_biss1_b |
|
|
| 5 | "0" |
sel_app_biss1_a |
|
|
| 4 | "0" |
sel_app_biss1 |
|
|
| 3 | "0" |
sel_app_biss0_mo_b |
|
|
| 2 | "0" |
sel_app_biss0_mo_a |
|
|
| 1 | "0" |
sel_app_biss0_b |
|
|
| 0 | "0" |
sel_app_biss0_a |
|
|
| global_asic_ctrl_app_endat_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
sel_app_endat1_devel_b_wm |
|
|
| 24 | "0" |
sel_app_endat1_devel_a_wm |
|
|
| 23 | "0" |
sel_app_endat1_b_wm |
|
|
| 22 | "0" |
sel_app_endat1_a_wm |
|
|
| 21 | "0" |
sel_app_endat1_wm |
|
|
| 20 | "0" |
sel_app_endat0_devel_b_wm |
|
|
| 19 | "0" |
sel_app_endat0_devel_a_wm |
|
|
| 18 | "0" |
sel_app_endat0_devel_wm |
|
|
| 17 | "0" |
sel_app_endat0_b_wm |
|
|
| 16 | "0" |
sel_app_endat0_a_wm |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sel_app_endat1_devel_b |
|
|
| 8 | "0" |
sel_app_endat1_devel_a |
|
|
| 7 | "0" |
sel_app_endat1_b |
|
|
| 6 | "0" |
sel_app_endat1_a |
|
|
| 5 | "0" |
sel_app_endat1 |
|
|
| 4 | "0" |
sel_app_endat0_devel_b |
|
|
| 3 | "0" |
sel_app_endat0_devel_a |
|
|
| 2 | "0" |
sel_app_endat0_devel |
|
|
| 1 | "0" |
sel_app_endat0_b |
|
|
| 0 | "0" |
sel_app_endat0_a |
|
|
| global_asic_ctrl_app_peri_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
sel_app_xspi_rst_n_wm |
|
|
| 22 | "0" |
sel_app_xspi_int_wm |
|
|
| 21 | "0" |
sel_app_xspi_cs1_wm |
|
|
| 20 | "0" |
sel_app_xspi_wm |
|
|
| 19 | "0" |
sel_app_canfd1_a_wm |
|
|
| 18 | "0" |
sel_app_canfd1_wm |
|
|
| 17 | "0" |
sel_app_canfd0_a_wm |
|
|
| 16 | "0" |
sel_app_canfd0_wm |
|
|
| 15 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
sel_app_xspi_rst_n |
|
|
| 6 | "0" |
sel_app_xspi_int |
|
|
| 5 | "0" |
sel_app_xspi_cs1 |
|
|
| 4 | "0" |
sel_app_xspi |
|
|
| 3 | "0" |
sel_app_canfd1_a |
|
|
| 2 | "0" |
sel_app_canfd1 |
|
|
| 1 | "0" |
sel_app_canfd0_a |
|
|
| 0 | "0" |
sel_app_canfd0 |
|
|
| global_asic_ctrl_app_misc_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
sel_app_phy_rst_out_n_cs1_wm |
|
|
| 16 | "0" |
sel_app_phy_rst_out_n_int_wm |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sel_app_phy_rst_out_n_cs1 |
|
|
| 0 | "0" |
sel_app_phy_rst_out_n_int |
|
|
| global_asic_ctrl_com_mmio_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 16 | "00000000" |
sel_com_mmio_wm |
|
|
| 15 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
sel_com_mmio |
|
|
| global_asic_ctrl_com_sgmii_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
sel_com_sgmii1_fx_sd_wm |
|
|
| 22 | "0" |
sel_com_sgmii1_3_wm |
|
|
| 21 | "0" |
sel_com_sgmii1_2_wm |
|
|
| 20 | "0" |
sel_com_sgmii1_1_wm |
|
|
| 19 | "0" |
sel_com_sgmii0_fx_sd_wm |
|
|
| 18 | "0" |
sel_com_sgmii0_3_wm |
|
|
| 17 | "0" |
sel_com_sgmii0_2_wm |
|
|
| 16 | "0" |
sel_com_sgmii0_1_wm |
|
|
| 15 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
sel_com_sgmii1_fx_sd |
|
|
| 6 | "0" |
sel_com_sgmii1_3 |
|
|
| 5 | "0" |
sel_com_sgmii1_2 |
|
|
| 4 | "0" |
sel_com_sgmii1_1 |
|
|
| 3 | "0" |
sel_com_sgmii0_fx_sd |
|
|
| 2 | "0" |
sel_com_sgmii0_3 |
|
|
| 1 | "0" |
sel_com_sgmii0_2 |
|
|
| 0 | "0" |
sel_com_sgmii0_1 |
|
|
| global_asic_ctrl_com_rgmii_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 | "0" |
sel_com_rgmii1_txc_out_p1ns_wm |
|
|
| 28 | "0" |
sel_com_rgmii1_4_wm |
|
|
| 27 | "0" |
sel_com_rgmii1_3_wm |
|
|
| 26 | "0" |
sel_com_rgmii1_2_wm |
|
|
| 25 | "0" |
sel_com_rgmii1_1_wm |
|
|
| 24 | "0" |
sel_com_rgmii1_0_wm |
|
|
| 23 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sel_com_rgmii0_txc_out_p1ns_wm |
|
|
| 20 | "0" |
sel_com_rgmii0_4_wm |
|
|
| 19 | "0" |
sel_com_rgmii0_3_wm |
|
|
| 18 | "0" |
sel_com_rgmii0_2_wm |
|
|
| 17 | "0" |
sel_com_rgmii0_1_wm |
|
|
| 16 | "0" |
sel_com_rgmii0_0_wm |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
sel_com_rgmii1_txc_out_p1ns |
|
|
| 12 | "0" |
sel_com_rgmii1_4 |
|
|
| 11 | "0" |
sel_com_rgmii1_3 |
|
|
| 10 | "0" |
sel_com_rgmii1_2 |
|
|
| 9 | "0" |
sel_com_rgmii1_1 |
|
|
| 8 | "0" |
sel_com_rgmii1_0 |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
sel_com_rgmii0_txc_out_p1ns |
|
|
| 4 | "0" |
sel_com_rgmii0_4 |
|
|
| 3 | "0" |
sel_com_rgmii0_3 |
|
|
| 2 | "0" |
sel_com_rgmii0_2 |
|
|
| 1 | "0" |
sel_com_rgmii0_1 |
|
|
| 0 | "0" |
sel_com_rgmii0_0 |
|
|
| global_asic_ctrl_com_mii0_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x4003005c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
sel_com_mii0_9_wm |
|
|
| 24 | "0" |
sel_com_mii0_8_wm |
|
|
| 23 | "0" |
sel_com_mii0_7_wm |
|
|
| 22 | "0" |
sel_com_mii0_6_wm |
|
|
| 21 | "0" |
sel_com_mii0_5_wm |
|
|
| 20 | "0" |
sel_com_mii0_4_wm |
|
|
| 19 | "0" |
sel_com_mii0_3_wm |
|
|
| 18 | "0" |
sel_com_mii0_2_wm |
|
|
| 17 | "0" |
sel_com_mii0_1_wm |
|
|
| 16 | "0" |
sel_com_mii0_0_wm |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sel_com_mii0_9 |
|
|
| 8 | "0" |
sel_com_mii0_8 |
|
|
| 7 | "0" |
sel_com_mii0_7 |
|
|
| 6 | "0" |
sel_com_mii0_6 |
|
|
| 5 | "0" |
sel_com_mii0_5 |
|
|
| 4 | "0" |
sel_com_mii0_4 |
|
|
| 3 | "0" |
sel_com_mii0_3 |
|
|
| 2 | "0" |
sel_com_mii0_2 |
|
|
| 1 | "0" |
sel_com_mii0_1 |
|
|
| 0 | "0" |
sel_com_mii0_0 |
|
|
| global_asic_ctrl_com_mii1_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
sel_com_mii1_9_wm |
|
|
| 24 | "0" |
sel_com_mii1_8_wm |
|
|
| 23 | "0" |
sel_com_mii1_7_wm |
|
|
| 22 | "0" |
sel_com_mii1_6_wm |
|
|
| 21 | "0" |
sel_com_mii1_5_wm |
|
|
| 20 | "0" |
sel_com_mii1_4_wm |
|
|
| 19 | "0" |
sel_com_mii1_3_wm |
|
|
| 18 | "0" |
sel_com_mii1_2_wm |
|
|
| 17 | "0" |
sel_com_mii1_1_wm |
|
|
| 16 | "0" |
sel_com_mii1_0_wm |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sel_com_mii1_9 |
|
|
| 8 | "0" |
sel_com_mii1_8 |
|
|
| 7 | "0" |
sel_com_mii1_7 |
|
|
| 6 | "0" |
sel_com_mii1_6 |
|
|
| 5 | "0" |
sel_com_mii1_5 |
|
|
| 4 | "0" |
sel_com_mii1_4 |
|
|
| 3 | "0" |
sel_com_mii1_3 |
|
|
| 2 | "0" |
sel_com_mii1_2 |
|
|
| 1 | "0" |
sel_com_mii1_1 |
|
|
| 0 | "0" |
sel_com_mii1_0 |
|
|
| global_asic_ctrl_com_rmii_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 | "0" |
sel_com_rmii1_5_wm |
|
|
| 28 | "0" |
sel_com_rmii1_4_wm |
|
|
| 27 | "0" |
sel_com_rmii1_3_wm |
|
|
| 26 | "0" |
sel_com_rmii1_2_wm |
|
|
| 25 | "0" |
sel_com_rmii1_1_wm |
|
|
| 24 | "0" |
sel_com_rmii1_0_wm |
|
|
| 23 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sel_com_rmii0_5_wm |
|
|
| 20 | "0" |
sel_com_rmii0_4_wm |
|
|
| 19 | "0" |
sel_com_rmii0_3_wm |
|
|
| 18 | "0" |
sel_com_rmii0_2_wm |
|
|
| 17 | "0" |
sel_com_rmii0_1_wm |
|
|
| 16 | "0" |
sel_com_rmii0_0_wm |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
sel_com_rmii1_5 |
|
|
| 12 | "0" |
sel_com_rmii1_4 |
|
|
| 11 | "0" |
sel_com_rmii1_3 |
|
|
| 10 | "0" |
sel_com_rmii1_2 |
|
|
| 9 | "0" |
sel_com_rmii1_1 |
|
|
| 8 | "0" |
sel_com_rmii1_0 |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
sel_com_rmii0_5 |
|
|
| 4 | "0" |
sel_com_rmii0_4 |
|
|
| 3 | "0" |
sel_com_rmii0_3 |
|
|
| 2 | "0" |
sel_com_rmii0_2 |
|
|
| 1 | "0" |
sel_com_rmii0_1 |
|
|
| 0 | "0" |
sel_com_rmii0_0 |
|
|
| global_asic_ctrl_com_gxc_io_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sel_com_xc1_gpio_wm |
|
|
| 27 - 24 | "0000" |
sel_com_xc0_b_gpio_wm |
|
|
| 23 - 20 | "0000" |
sel_com_xc0_gpio_wm |
|
|
| 19 | "0" |
sel_com_gxc_sample1_wm |
|
|
| 18 | "0" |
sel_com_gxc_sample0_wm |
|
|
| 17 | "0" |
sel_com_gxc_trigger1_wm |
|
|
| 16 | "0" |
sel_com_gxc_trigger0_wm |
|
|
| 15 - 12 | "0000" |
sel_com_xc1_gpio |
|
|
| 11 - 8 | "0000" |
sel_com_xc0_b_gpio |
|
|
| 7 - 4 | "0000" |
sel_com_xc0_gpio |
|
|
| 3 | "0" |
sel_com_gxc_sample1 |
|
|
| 2 | "0" |
sel_com_gxc_sample0 |
|
|
| 1 | "0" |
sel_com_gxc_trigger1 |
|
|
| 0 | "0" |
sel_com_gxc_trigger0 |
|
|
| global_asic_ctrl_com_gxc_io_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4003006c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |
| 16 | "0" |
sel_com_miim_wm |
|
|
| 15 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sel_com_miim |
|
|
| global_asic_ctrl_com_misc_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 | "0" |
sel_com_phy_rst_out_n_cs1_wm |
|
|
| 19 | "0" |
sel_com_phy_rst_out_n_int_wm |
|
|
| 18 | "0" |
clk50out_oe_wm |
|
|
| 17 | "0" |
sel_clk50out_wm |
|
|
| 16 | "0" |
clk25out_oe_wm |
|
|
| 15 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
sel_com_phy_rst_out_n_cs1 |
|
|
| 3 | "0" |
sel_com_phy_rst_out_n_int |
|
|
| 2 | "0" |
clk50out_oe |
|
|
| 1 | "0" |
sel_clk50out |
|
|
| 0 | "0" |
clk25out_oe |
|
|
| global_asic_ctrl_com_peri_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
sel_com_iol_spi_cs0_wm |
|
|
| 23 | "0" |
sel_com_iol_spi_wm |
|
|
| 22 | "0" |
sel_com_xspi_rst_n_wm |
|
|
| 21 | "0" |
sel_com_xspi_int_wm |
|
|
| 20 | "0" |
sel_com_xspi_cs1_wm |
|
|
| 19 | "0" |
sel_com_xspi_wm |
|
|
| 18 | "0" |
sel_com_uart0_wm |
|
|
| 17 | "0" |
sel_com_spi1_wm |
|
|
| 16 | "0" |
sel_com_spi0_wm |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sel_com_iol_spi_cs0 |
|
|
| 7 | "0" |
sel_com_iol_spi |
|
|
| 6 | "0" |
sel_com_xspi_rst_n |
|
|
| 5 | "0" |
sel_com_xspi_int |
|
|
| 4 | "0" |
sel_com_xspi_cs1 |
|
|
| 3 | "0" |
sel_com_xspi |
|
|
| 2 | "0" |
sel_com_uart0 |
|
|
| 1 | "0" |
sel_com_spi1 |
|
|
| 0 | "0" |
sel_com_spi0 |
|
|
| global_asic_ctrl_com_canfd_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 23 | 0 |
- |
reserved | |
| 22 | "0" |
sel_com_canfd1_pg2_wm |
|
|
| 21 | "0" |
sel_com_canfd1_pg0_wm |
|
|
| 20 | "0" |
sel_com_canfd1_wm |
|
|
| 19 | 0 |
- |
reserved | |
| 18 | "0" |
sel_com_canfd0_pg2_wm |
|
|
| 17 | "0" |
sel_com_canfd0_pg0_wm |
|
|
| 16 | "0" |
sel_com_canfd0_wm |
|
|
| 15 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
sel_com_canfd1_pg2 |
|
|
| 5 | "0" |
sel_com_canfd1_pg0 |
|
|
| 4 | "0" |
sel_com_canfd1 |
|
|
| 3 | 0 |
- |
reserved | |
| 2 | "0" |
sel_com_canfd0_pg2 |
|
|
| 1 | "0" |
sel_com_canfd0_pg0 |
|
|
| 0 | "0" |
sel_com_canfd0 |
|
|
| global_asic_ctrl_mot_mmio_io_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4003007c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_mot_mmio0_15_wm |
|
|
| 15 - 0 | 0x0 |
sel_mot_mmio0_15 |
|
|
| global_asic_ctrl_mot_mmio_io_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_mot_mmio16_31_wm |
|
|
| 15 - 0 | 0x0 |
sel_mot_mmio16_31 |
|
|
| global_asic_ctrl_mot_mmio_io_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_mot_mmio32_47_wm |
|
|
| 15 - 0 | 0x0 |
sel_mot_mmio32_47 |
|
|
| global_asic_ctrl_mot_mmio_io_cfg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 16 | 0x0 |
sel_mot_mmio48_62_wm |
|
|
| 15 | 0 |
- |
reserved | |
| 14 - 0 | 0x0 |
sel_mot_mmio48_62 |
|
|
| global_asic_ctrl_mot_pio_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x4003008c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 - 16 | 0x0 |
sel_mot_pio_wm |
|
|
| 15 - 11 | 0 |
- |
reserved | |
| 10 - 0 | 0x0 |
sel_mot_pio |
|
|
| global_asic_ctrl_mot_sdm_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 23 | 0 |
- |
reserved | |
| 22 | "0" |
sel_sdm2_d2_wm |
|
|
| 21 | "0" |
sel_sdm2_d1_wm |
|
|
| 20 | "0" |
sel_sdm2_wm |
|
|
| 19 | "0" |
sel_sdm1_d1_wm |
|
|
| 18 | "0" |
sel_sdm1_wm |
|
|
| 17 | "0" |
sel_sdm0_d1_wm |
|
|
| 16 | "0" |
sel_sdm0_wm |
|
|
| 15 - 7 | 0 |
- |
reserved | |
| 6 | "0" |
sel_sdm2_d2 |
|
|
| 5 | "0" |
sel_sdm2_d1 |
|
|
| 4 | "0" |
sel_sdm2 |
|
|
| 3 | "0" |
sel_sdm1_d1 |
|
|
| 2 | "0" |
sel_sdm1 |
|
|
| 1 | "0" |
sel_sdm0_d1 |
|
|
| 0 | "0" |
sel_sdm0 |
|
|
| global_asic_ctrl_mot_biss_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
sel_mot_biss1_mo_b_wm |
|
|
| 23 | "0" |
sel_mot_biss1_mo_a_wm |
|
|
| 22 | "0" |
sel_mot_biss1_b_wm |
|
|
| 21 | "0" |
sel_mot_biss1_a_wm |
|
|
| 20 | "0" |
sel_mot_biss1_wm |
|
|
| 19 | "0" |
sel_mot_biss0_mo_b_wm |
|
|
| 18 | "0" |
sel_mot_biss0_mo_a_wm |
|
|
| 17 | "0" |
sel_mot_biss0_b_wm |
|
|
| 16 | "0" |
sel_mot_biss0_a_wm |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
sel_mot_biss1_mo_b |
|
|
| 7 | "0" |
sel_mot_biss1_mo_a |
|
|
| 6 | "0" |
sel_mot_biss1_b |
|
|
| 5 | "0" |
sel_mot_biss1_a |
|
|
| 4 | "0" |
sel_mot_biss1 |
|
|
| 3 | "0" |
sel_mot_biss0_mo_b |
|
|
| 2 | "0" |
sel_mot_biss0_mo_a |
|
|
| 1 | "0" |
sel_mot_biss0_b |
|
|
| 0 | "0" |
sel_mot_biss0_a |
|
|
| global_asic_ctrl_mot_endat_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40030098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
sel_mot_endat1_devel_b_wm |
|
|
| 24 | "0" |
sel_mot_endat1_devel_a_wm |
|
|
| 23 | "0" |
sel_mot_endat1_b_wm |
|
|
| 22 | "0" |
sel_mot_endat1_a_wm |
|
|
| 21 | "0" |
sel_mot_endat1_wm |
|
|
| 20 | "0" |
sel_mot_endat0_devel_b_wm |
|
|
| 19 | "0" |
sel_mot_endat0_devel_a_wm |
|
|
| 18 | "0" |
sel_mot_endat0_devel_wm |
|
|
| 17 | "0" |
sel_mot_endat0_b_wm |
|
|
| 16 | "0" |
sel_mot_endat0_a_wm |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
sel_mot_endat1_devel_b |
|
|
| 8 | "0" |
sel_mot_endat1_devel_a |
|
|
| 7 | "0" |
sel_mot_endat1_b |
|
|
| 6 | "0" |
sel_mot_endat1_a |
|
|
| 5 | "0" |
sel_mot_endat1 |
|
|
| 4 | "0" |
sel_mot_endat0_devel_b |
|
|
| 3 | "0" |
sel_mot_endat0_devel_a |
|
|
| 2 | "0" |
sel_mot_endat0_devel |
|
|
| 1 | "0" |
sel_mot_endat0_b |
|
|
| 0 | "0" |
sel_mot_endat0_a |
|
|
| global_asic_ctrl_dbg_io_cfg |
|
|||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4003009c |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||||||||||
| 19 | "0" |
sel_dbg_trace_ctl_wm |
|
|||||||||||||||||
| 18 - 16 | "000" |
sel_dbg_trace_cfg_wm |
|
|||||||||||||||||
| 15 - 4 | 0 |
- |
reserved | |||||||||||||||||
| 3 | "0" |
sel_dbg_trace_ctl |
|
|||||||||||||||||
| 2 - 0 | "000" |
sel_dbg_trace_cfg |
|
|||||||||||||||||
| global_asic_ctrl_ioextender_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x400300a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 16 | 0x0 |
sel_ioe_io_wm |
|
|
| 15 | 0 |
- |
reserved | |
| 14 - 0 | 0x0 |
sel_ioe_io |
|
|
| global_asic_ctrl_global_peri_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x400300a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 16 | "00" |
sel_sqi_cs_wm |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
sel_sqi_cs |
|
|
| global_asic_ctrl_hif_io_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400300a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
sel_hif_b_sirq_wm |
|
|
| 25 | "0" |
sel_hif_sirq_wm |
|
|
| 24 | "0" |
sel_hif_dirq_wm |
|
|
| 23 | "0" |
sel_hif_wrhn_wm |
|
|
| 22 | "0" |
sel_hif_bhe_wm |
|
|
| 21 | "0" |
sel_hif_ale_wm |
|
|
| 20 | "0" |
sel_hif_rdy_wm |
|
|
| 19 | "0" |
sel_hif_b_d16_wm |
|
|
| 18 | "0" |
sel_hif_a_d16_wm |
|
|
| 17 | "0" |
sel_hif_d16_wm |
|
|
| 16 | "0" |
sel_hif_wm |
|
|
| 15 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
sel_hif_b_sirq |
|
|
| 9 | "0" |
sel_hif_sirq |
|
|
| 8 | "0" |
sel_hif_dirq |
|
|
| 7 | "0" |
sel_hif_wrhn |
|
|
| 6 | "0" |
sel_hif_bhe |
|
|
| 5 | "0" |
sel_hif_ale |
|
|
| 4 | "0" |
sel_hif_rdy |
|
|
| 3 | "0" |
sel_hif_b_d16 |
|
|
| 2 | "0" |
sel_hif_a_d16 |
|
|
| 1 | "0" |
sel_hif_d16 |
|
|
| 0 | "0" |
sel_hif |
|
|
| global_asic_ctrl_hif_io_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x400300ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sel_hif_a0_15_wm |
|
|
| 15 - 0 | 0x0 |
sel_hif_a0_15 |
|
|
| global_asic_ctrl_hif_io_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x400300b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 16 | "00" |
sel_hif_a16_17_wm |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
sel_hif_a16_17 |
|
|
| global_asic_ctrl_hif_io_cfg3 |
|
|||
| R/W |
0x00000000 |
Address : 0x400300b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 - 16 | 0x0 |
sel_hif_b_a9_17_wm |
|
|
| 15 - 9 | 0 |
- |
reserved | |
| 8 - 0 | 0x0 |
sel_hif_b_a9_17 |
|
|
| global_asic_ctrl_pcie_dbg_io_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x400300b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |
| 16 | "0" |
test_sel_pcie_link0_dbg_wm |
|
|
| 15 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
test_sel_pcie_link0_dbg |
|
|
| global_asic_ctrl_pcie_isolation |
|
||||||
| R/W |
0x00000000 |
Address : 0x400300bc |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||
| 18 | - |
axi_app_mst_isolated_ro |
|
||||
| 17 | - |
axi_com_mst_isolated_ro |
|
||||
| 16 | - |
axi_slv_isolated_ro |
|
||||
| 15 - 3 | 0 |
- |
reserved | ||||
| 2 | "0" |
axi_app_mst_isolate |
|
||||
| 1 | "0" |
axi_com_mst_isolate |
|
||||
| 0 | "0" |
axi_slv_isolate |
|
||||
| global_asic_ctrl_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x400300c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
com_gic_ecc_fatal |
|
|
| global_asic_ctrl_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x400300c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
com_gic_ecc_fatal |
|
|
| global_asic_ctrl_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x400300c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
com_gic_ecc_fatal |
|
|
| global_asic_ctrl_irq_mask_rst |
|
|||||||
| R/W |
0x00000000 |
Address : 0x400300cc |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
com_gic_ecc_fatal |
|
|||||
| global_asic_ctrl_sdio_pad_cfg |
|
||||||||
| R/W |
0x00000000 |
Address : 0x400300d0 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
sel_ip_ie_ctrl |
|
||||||
| 0 | "0" |
sel_ip_drvss |
|
||||||
| pad_ctrl_dpm0_spi_mosi |
|
|||
| R/W |
0x00001070 |
Address : 0x40030400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_miso |
|
|||
| R/W |
0x00001070 |
Address : 0x40030404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x40030408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_sio3 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003040c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_sio2 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_csn |
|
|||
| R/W |
0x00001070 |
Address : 0x40030414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm0_spi_dirq |
|
|||
| R/W |
0x00001070 |
Address : 0x40030418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_mosi |
|
|||
| R/W |
0x00001070 |
Address : 0x4003041c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_miso |
|
|||
| R/W |
0x00001070 |
Address : 0x40030420 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x40030424 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_sio3 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030428 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_sio2 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003042c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_csn |
|
|||
| R/W |
0x00001070 |
Address : 0x40030430 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_dpm1_spi_dirq |
|
|||
| R/W |
0x00001070 |
Address : 0x40030434 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_rgmii0_rxd3 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030438 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_gm0_in0 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003043c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_rxc |
|
|||
| R/W |
0x00001050 |
Address : 0x40030440 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_rxd0 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030444 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_rxctl |
|
|||
| R/W |
0x00001050 |
Address : 0x40030448 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_mdio |
|
|||
| R/W |
0x00001050 |
Address : 0x4003044c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_gm0_in3 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030450 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txctl |
|
|||
| R/W |
0x00001050 |
Address : 0x40030454 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txc |
|
|||
| R/W |
0x00001050 |
Address : 0x40030458 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_gm1_in0 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003045c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txd1 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030460 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txd0 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030464 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txd2 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030468 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii0_txd3 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003046c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_rxd3 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030470 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_gm1_in3 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030474 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_mdc |
|
|||
| R/W |
0x00001050 |
Address : 0x40030478 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_rxc |
|
|||
| R/W |
0x00001040 |
Address : 0x4003047c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_rxd0 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030480 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_rxctl |
|
|||
| R/W |
0x00001050 |
Address : 0x40030484 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txctl |
|
|||
| R/W |
0x00001050 |
Address : 0x40030488 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txc |
|
|||
| R/W |
0x00001050 |
Address : 0x4003048c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txd1 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030490 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txd0 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030494 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txd2 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030498 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_clk25out |
|
|||
| R/W |
0x00001050 |
Address : 0x4003049c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_rgmii1_txd3 |
|
|||
| R/W |
0x00001040 |
Address : 0x400304a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_csn1 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_csn0 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_int |
|
|||
| R/W |
0x00001050 |
Address : 0x400304ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x400304b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_rwds |
|
|||
| R/W |
0x00001070 |
Address : 0x400304b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq1 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq6 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq7 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq0 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq5 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq4 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq2 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_xspi_dq3 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_sio2 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_miso_sio1 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x400304e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_mosi_sio0 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_sio3 |
|
|||
| R/W |
0x00001070 |
Address : 0x400304e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_sqi_cs0n |
|
|||
| R/W |
0x00001070 |
Address : 0x400304ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_app_mdc |
|
|||
| R/W |
0x00001050 |
Address : 0x400304f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_app_mdio |
|
|||
| R/W |
0x00001050 |
Address : 0x400304f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_dbg_trace_clk |
|
|||
| R/W |
0x00001040 |
Address : 0x400304f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_dbg_trace_d0 |
|
|||
| R/W |
0x00001040 |
Address : 0x400304fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_dbg_trace_d1 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_dbg_trace_d2 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_dbg_trace_d3 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_io3 |
|
|||
| R/W |
0x00001040 |
Address : 0x4003050c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_io1 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_io2 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_com_io0 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030518 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
he |
|
|
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
ds |
|
|
| pad_ctrl_xspi_csn1 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003051c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_csn0 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_int |
|
|||
| R/W |
0x00001050 |
Address : 0x40030524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_rwds |
|
|||
| R/W |
0x00001070 |
Address : 0x40030528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x4003052c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq1 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq7 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq6 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030538 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq0 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003053c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq5 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030540 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq2 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030544 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq3 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_xspi_dq4 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003054c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_io5 |
|
|||
| R/W |
0x00001040 |
Address : 0x40030550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "0" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_io4 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_ioe_strb |
|
|||
| R/W |
0x00001070 |
Address : 0x40030558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_ioe_sck_nrdy |
|
|||
| R/W |
0x00001070 |
Address : 0x4003055c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_io6 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_ioe_miso |
|
|||
| R/W |
0x00001070 |
Address : 0x40030564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_ioe_mosi_nrun |
|
|||
| R/W |
0x00001070 |
Address : 0x40030568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_rst_out_n |
|
|||
| R/W |
0x00001050 |
Address : 0x4003056c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_io7 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_uart_tx |
|
|||
| R/W |
0x00001070 |
Address : 0x40030574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_uart_rx |
|
|||
| R/W |
0x00001070 |
Address : 0x40030578 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio0 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003057c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio2 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio1 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio5 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio6 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003058c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio7 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio3 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio4 |
|
|||
| R/W |
0x00001050 |
Address : 0x40030598 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio8 |
|
|||
| R/W |
0x00001050 |
Address : 0x4003059c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio9 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio10 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio12 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio11 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio13 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio15 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_app_mmio14 |
|
|||
| R/W |
0x00001050 |
Address : 0x400305b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "0" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_com_rgmii0_rxd1 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030600 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_rgmii0_rxd2 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030604 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_gm0_in1 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_gm0_in2 |
|
|||
| R/W |
0x00001000 |
Address : 0x4003060c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_rgmii1_rxd1 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_rgmii1_rxd2 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_gm1_in1 |
|
|||
| R/W |
0x00001000 |
Address : 0x40030618 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_com_gm1_in2 |
|
|||
| R/W |
0x00001000 |
Address : 0x4003061c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_app_sgmii_rx_p |
|
|||
| R/W |
0x00001000 |
Address : 0x40030620 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_app_sgmii_rx_n |
|
|||
| R/W |
0x00001000 |
Address : 0x40030624 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_app_sgmii_tx_p |
|
|||
| R/W |
0x00001000 |
Address : 0x40030628 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_app_sgmii_tx_n |
|
|||
| R/W |
0x00001000 |
Address : 0x4003062c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 10 | 0 |
- |
reserved | |
| 9 - 8 | "00" |
st |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| pad_ctrl_sdio_clk |
|
|||
| R/W |
0x00001070 |
Address : 0x40030640 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_cmd |
|
|||
| R/W |
0x00001070 |
Address : 0x40030644 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_dat0 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030648 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_dat1 |
|
|||
| R/W |
0x00001070 |
Address : 0x4003064c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_dat2 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030650 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_dat3 |
|
|||
| R/W |
0x00001070 |
Address : 0x40030654 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_ds |
|
|||
| R/W |
0x00001070 |
Address : 0x40030658 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_lpbk_dqs_o |
|
|||
| R/W |
0x00001070 |
Address : 0x4003065c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| pad_ctrl_sdio_lpbk_dqs_i |
|
|||
| R/W |
0x00001070 |
Address : 0x40030660 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
pw |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "1" |
ie |
|
|
| 11 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
st |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
sl |
|
|
| 5 | "1" |
ps |
|
|
| 4 | "1" |
pe |
|
|
| 3 | 0 |
- |
reserved | |
| 2 - 0 | "000" |
ds |
|
|
| ioextender_ioe_o0_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x40030800 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
inv |
|
|||||||||||||||||||||||||||||||||||||||||||||
| 6 - 0 | "0000000" |
sel |
|
|||||||||||||||||||||||||||||||||||||||||||||
| ioextender_ioe_o1_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o2_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o3_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003080c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o4_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o5_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o6_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o7_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003081c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o8_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o9_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030824 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o10_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030828 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o11_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003082c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o12_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030830 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o13_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030834 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o14_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030838 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o15_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003083c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o16_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030840 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o17_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030844 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o18_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030848 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o19_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003084c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o20_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030850 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o21_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030854 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o22_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030858 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o23_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003085c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o24_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030860 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o25_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030864 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o26_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030868 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o27_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003086c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o28_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030870 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o29_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030874 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o30_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030878 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o31_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003087c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o32_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030880 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o33_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030884 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o34_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030888 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o35_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003088c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o36_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030890 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o37_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030894 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o38_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030898 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o39_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x4003089c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o40_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o41_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o42_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o43_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o44_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o45_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o46_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o47_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o48_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o49_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o50_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o51_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o52_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o53_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o54_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o55_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308dc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o56_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o57_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o58_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o59_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o60_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o61_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o62_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_o63_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x400308fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_ioe_mosi_dc_oe_sel |
|
|||
| R/W |
0x0000004e |
Address : 0x40030900 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1001110" |
sel |
|
|
| ioextender_ioe_mosi_dc_o_sel |
|
|||
| R/W |
0x0000004f |
Address : 0x40030904 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1001111" |
sel |
|
|
| ioextender_ioe_sck_dc_oe_sel |
|
|||
| R/W |
0x00000050 |
Address : 0x40030908 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1010000" |
sel |
|
|
| ioextender_ioe_sck_dc_o_sel |
|
|||
| R/W |
0x00000051 |
Address : 0x4003090c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1010001" |
sel |
|
|
| ioextender_app_mdio_in_sel |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x40030a00 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||||||||
| 7 | "0" |
inv |
|
|||||||||||
| 6 - 0 | "0000000" |
sel |
|
|||||||||||
| ioextender_com_mdio_in_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in0_sel |
|
|||
| R/W |
0x00000001 |
Address : 0x40030a08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000001" |
sel |
|
|
| ioextender_mot_pio_in1_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in2_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in3_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in4_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in5_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in6_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in7_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in8_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in9_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in10_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in11_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in12_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in13_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in14_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_mot_pio_in15_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in0_sel |
|
|||
| R/W |
0x00000001 |
Address : 0x40030a48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000001" |
sel |
|
|
| ioextender_app_pio_in1_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a4c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in2_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a50 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in3_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a54 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in4_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a58 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in5_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in6_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a60 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in7_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a64 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in8_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a68 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in9_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a6c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in10_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in11_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a74 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in12_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in13_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in14_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_app_pio_in15_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a84 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in0_sel |
|
|||
| R/W |
0x00000001 |
Address : 0x40030a88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000001" |
sel |
|
|
| ioextender_com_pio_in1_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in2_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a90 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in3_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in4_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in5_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030a9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in6_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030aa0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in7_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030aa4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in8_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030aa8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in9_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030aac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in10_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030ab0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in11_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030ab4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in12_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030ab8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in13_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030abc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in14_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030ac0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_com_pio_in15_sel |
|
|||
| R/W |
0x00000000 |
Address : 0x40030ac4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "0000000" |
sel |
|
|
| ioextender_run_n_in_sel |
|
|||
| R/W |
0x00000042 |
Address : 0x40030ac8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1000010" |
sel |
|
|
| ioextender_rdy_n_in_sel |
|
|||
| R/W |
0x00000043 |
Address : 0x40030acc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
inv |
|
|
| 6 - 0 | "1000011" |
sel |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | ioextender_cfg_sck0 |
| 1 | 4 | R/W | ioextender_cfg_sck1 |
| 2 | 8 | R/W | ioextender_cfg_sck2 |
| 3 | c | R/W | ioextender_cfg_sck3 |
| 4 | 10 | R/W | ioextender_cfg_p0_len |
| 5 | 14 | R/W | ioextender_cfg_p8_len |
| 6 | 18 | R/W | ioextender_cfg_frame |
| 7 | 1c | R/W | ioextender_cfg_ioe_io_dir |
| 8 | 20 | R/W | ioextender_cmd |
| 9 | 24 | R | ioextender_state |
| a | 28 | R/W | ioextender_dc_i_tgl |
| b | 2c | R/W | ioextender_i0 |
| c | 30 | R/W | ioextender_i1 |
| d | 34 | R | ioextender_dc_o |
| e | 38 | R | ioextender_o0 |
| f | 3c | R | ioextender_o1 |
| 10 | 40 | R | ioextender_pad_in |
| 11 | 44 | R/W | ioextender_pad_out |
| 12-3f | 48-fc | - | reserved |
| ioextender_cfg_sck0 |
|
|||
| R/W |
0x00040004 |
Address : 0x40030c00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | |
| 28 - 16 | 0x4 |
miso_sample |
|
|
| 15 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x4 |
half_period |
|
|
| ioextender_cfg_sck1 | |||
| R/W |
0x00050005 |
Address : 0x40030c04 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved |
| 28 - 16 | 0x5 |
miso_sample |
|
| 15 - 12 | 0 |
- |
reserved |
| 11 - 0 | 0x5 |
half_period |
|
| ioextender_cfg_sck2 | |||
| R/W |
0x00060006 |
Address : 0x40030c08 |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved |
| 28 - 16 | 0x6 |
miso_sample |
|
| 15 - 12 | 0 |
- |
reserved |
| 11 - 0 | 0x6 |
half_period |
|
| ioextender_cfg_sck3 | |||
| R/W |
0x00070007 |
Address : 0x40030c0c |
Bits | Reset value | Name | Description |
|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved |
| 28 - 16 | 0x7 |
miso_sample |
|
| 15 - 12 | 0 |
- |
reserved |
| 11 - 0 | 0x7 |
half_period |
|
| ioextender_cfg_p0_len | ||||
| R/W |
0x00000000 |
Address : 0x40030c10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 0 | 0x0 |
val |
|
|
| ioextender_cfg_p8_len | ||||
| R/W |
0x00005adf |
Address : 0x40030c14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 - 0 | 0x5adf |
val |
|
|
| ioextender_cfg_frame | ||||
| R/W |
0x0103c1bf |
Address : 0x40030c18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 - 18 | "1000000" |
n_len |
|
|
| 17 | "1" |
sck_middle |
|
|
| 16 - 9 | "11100000" |
sck_start |
|
|
| 8 - 0 | 0x1bf |
s |
|
|
| ioextender_cfg_ioe_io_dir |
|
|||
| R/W |
0x00000000 |
Address : 0x40030c1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| ioextender_cmd | ||||
| R/W |
0x00000000 |
Address : 0x40030c20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
en |
|
|
| ioextender_state | ||||
| R |
Address : 0x40030c24 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 12 | - |
reserved | ||
| 11 - 10 | hp |
|
||
| 9 - 4 | n |
|
||
| 3 - 0 | phase |
|
||
| ioextender_dc_i_tgl |
|
|||
| R/W |
0x00000000 |
Address : 0x40030c28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ioe_tgl |
|
|
| 1 | "0" |
mosi |
|
|
| 0 | "0" |
sck |
|
|
| ioextender_i0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030c2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| ioextender_i1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40030c30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| ioextender_dc_o | ||||
| R |
Address : 0x40030c34 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | mosi_oe |
|
||
| 2 | sck_oe |
|
||
| 1 | mosi |
|
||
| 0 | sck |
|
||
| ioextender_o0 | ||||
| R |
Address : 0x40030c38 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| ioextender_o1 | ||||
| R |
Address : 0x40030c3c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| ioextender_pad_in |
|
|||
| R |
Address : 0x40030c40 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | miso |
|||
| 2 | mosi |
|||
| 1 | sck |
|||
| 0 | strb |
|||
| ioextender_pad_out |
|
|||||||
| R/W |
0x00000000 |
Address : 0x40030c44 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |||||
| 8 | "0" |
sel_sck_mosi |
|
|||||
| 7 | "0" |
miso_oe |
||||||
| 6 | "0" |
mosi_oe |
||||||
| 5 | "0" |
sck_oe |
||||||
| 4 | "0" |
strb_oe |
||||||
| 3 | "0" |
miso |
||||||
| 2 | "0" |
mosi |
||||||
| 1 | "0" |
sck |
||||||
| 0 | "0" |
strb |
||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | crg_clock_enable |
| 1 | 4 | R | crg_clock_status |
| 2-3 | 8-c | - | reserved |
| 4 | 10 | R | crg_reset_status |
| 5 | 14 | R/W | crg_reset_ctrl_pcie |
| 6-7 | 18-1c | - | reserved |
| 8 | 20 | R/W | crg_clk500_div |
| 9 | 24 | R/W | crg_clk166_dpm_div |
| a | 28 | R/W | crg_sse_syspll_div |
| b | 2c | R/W | crg_sse_cpupll_div |
| c | 30 | R/W | crg_clk200_div |
| d | 34 | R/W | crg_clk100_div |
| e | 38 | R/W | crg_clk80_div |
| f | 3c | R/W | crg_clk250_div |
| 10 | 40 | R/W | crg_clk200_sdio_div |
| 11 | 44 | R/W | crg_clk200_gem_gxl_div |
| 12-17 | 48-5c | - | reserved |
| 18 | 60 | R/W | crg_tpiu |
| 19-1f | 64-7c | - | reserved |
| 20 | 80 | R/W | crg_sys_pll_cfg |
| 21 | 84 | R | crg_all_pll_status |
| 22 | 88 | R/W | crg_ext_bypass_set |
| 23 | 8c | R/W | crg_ext_bypass_clr |
| 24 | 90 | R | crg_irq_status |
| 25 | 94 | R/W | crg_irq_clr |
| 26-3f | 98-fc | - | reserved |
| crg_clock_enable |
|
|||
| R/W |
0x00000000 |
Address : 0x40030d00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
run_clk400_pcie |
|
|
| 14 | "0" |
run_clk200_gem_gxl |
|
|
| 13 | "0" |
run_clk200_sdio |
|
|
| 12 | "0" |
run_clk250_iol |
|
|
| 11 | "0" |
run_clk80_canfd_app |
|
|
| 10 | "0" |
run_clk80_canfd_com |
|
|
| 9 | "0" |
run_clk100_mot |
|
|
| 8 | "0" |
run_clk200_mot |
|
|
| 7 | "0" |
run_clk166_dpm |
|
|
| 6 | "0" |
run_clk500_app_hsgmii |
|
|
| 5 | "0" |
run_clk500_com_hsgmii1 |
|
|
| 4 | "0" |
run_clk500_com_hsgmii0 |
|
|
| 3 | "0" |
run_clk500_ada |
|
|
| 2 | "0" |
run_clk500_cada_rx |
|
|
| 1 | "0" |
run_clk500_cada_tx |
|
|
| 0 | "0" |
run_clk500_gxc |
|
|
| crg_clock_status |
|
|||
| R |
Address : 0x40030d04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 15 | - |
reserved | ||
| 14 | run_clk200_gem_gxl |
|
||
| 13 | run_clk200_sdio |
|
||
| 12 | - |
reserved | ||
| 11 | run_clk80_canfd_app |
|
||
| 10 - 0 | - |
reserved | ||
| crg_reset_status |
|
|||
| R |
Address : 0x40030d10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||
| 2 | wdg1_tbd |
|
||
| 1 | rst_in_n |
|
||
| 0 | por |
|
||
| crg_reset_ctrl_pcie |
|
|||
| R/W |
0x0000001f |
Address : 0x40030d14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "1" |
allow_pcie_warm_nres_req |
|
|
| 3 | "1" |
allow_systop_warmresetn |
|
|
| 2 | "1" |
allow_aontop_warmresetn |
|
|
| 1 | "1" |
allow_aontop_poresetn |
|
|
| 0 | "1" |
allow_rst_in_n |
|
|
| crg_clk500_div |
|
|||
| R/W |
0x00000003 |
Address : 0x40030d20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 - 0 | "011" |
div_val |
|
|
| crg_clk166_dpm_div |
|
|||
| R/W |
0x00000002 |
Address : 0x40030d24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 - 0 | "010" |
div_val |
|
|
| crg_sse_syspll_div |
|
|||
| R/W |
0x00000004 |
Address : 0x40030d28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0100" |
div_val |
|
|
| crg_sse_cpupll_div |
|
|||
| R/W |
0x00000003 |
Address : 0x40030d2c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0011" |
div_val |
|
|
| crg_clk200_div |
|
|||
| R/W |
0x00000009 |
Address : 0x40030d30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001001" |
div_val |
|
|
| crg_clk100_div |
|
|||
| R/W |
0x00000001 |
Address : 0x40030d34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 - 0 | "01" |
div_val |
|
|
| crg_clk80_div |
|
|||
| R/W |
0x00000018 |
Address : 0x40030d38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "011000" |
div_val |
|
|
| crg_clk250_div |
|
|||
| R/W |
0x00000007 |
Address : 0x40030d3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0111" |
div_val |
|
|
| crg_clk200_sdio_div |
|
|||
| R/W |
0x00000009 |
Address : 0x40030d40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "01001" |
div_val |
|
|
| crg_clk200_gem_gxl_div |
|
|||
| R/W |
0x00000009 |
Address : 0x40030d44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "01001" |
div_val |
|
|
| crg_tpiu |
|
||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x40030d60 |
Bits | Reset value | Name | Description | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | ||||||||||||||||
| 4 - 0 | "00000" |
traceclk_div |
|
||||||||||||||||
| crg_sys_pll_cfg |
|
|||||||||
| R/W |
0x00005001 |
Address : 0x40030d80 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |||||||
| 24 | "0" |
pd |
|
|||||||
| 23 - 20 | 0 |
- |
reserved | |||||||
| 19 - 8 | 0x50 |
fbdiv |
|
|||||||
| 7 - 6 | 0 |
- |
reserved | |||||||
| 5 - 0 | "000001" |
refdiv |
|
|||||||
| crg_all_pll_status |
|
|||
| R |
Address : 0x40030d84 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 | sys_pll_ext_bypass_stat |
|
||
| 7 - 1 | - |
reserved | ||
| 0 | sys_pll_lock_stat |
|
||
| crg_ext_bypass_set |
|
|||
| R/W |
0x00000000 |
Address : 0x40030d88 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sys_pll |
|
|
| crg_ext_bypass_clr |
|
|||
| R/W |
0x00000000 |
Address : 0x40030d8c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sys_pll |
|
|
| crg_irq_status |
|
|||
| R |
Address : 0x40030d90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | sys_pll_lock_loss |
|
||
| crg_irq_clr |
|
|||
| R/W |
0x00000000 |
Address : 0x40030d94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sys_pll_lock_loss |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | com_asic_ctrl_only_por |
| 1 | 4 | R | com_asic_ctrl_rstsyn |
| 2-3 | 8-c | - | reserved |
| 4 | 10 | R/W | com_asic_ctrl_netx_status |
| 5 | 14 | R/W | com_asic_ctrl_rdy_run_cfg |
| 6 | 18 | R/W | com_asic_ctrl_rst_out_cfg |
| 7-3f | 1c-fc | - | reserved |
| com_asic_ctrl_only_por |
|
|||
| R/W |
0x00000000 |
Address : 0x40040000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| com_asic_ctrl_rstsyn |
|
|||
| R |
Address : 0x40040004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 5 | - |
reserved | ||
| 4 | ext |
|
||
| 3 | host |
|
||
| 2 | res |
|
||
| 1 | nsrst |
|
||
| 0 | por |
|
||
| com_asic_ctrl_netx_status (adr_netx_status) |
|
|||
| R/W |
0x00030000 |
Address : 0x40040010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
RUN_DRV |
|
|
| 24 | "0" |
RDY_DRV |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
RUN_POL |
|
|
| 18 | "0" |
RDY_POL |
|
|
| 17 | "1" |
RUN_IN |
|
|
| 16 | "1" |
RDY_IN |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
RUN |
|
|
| 0 | "0" |
RDY |
|
|
| com_asic_ctrl_rdy_run_cfg (adr_rdy_run_cfg) |
|
|||
| R/W |
0x00030000 |
Address : 0x40040014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
RUN_DRV |
|
|
| 24 | "0" |
RDY_DRV |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
RUN_POL |
|
|
| 18 | "0" |
RDY_POL |
|
|
| 17 | "1" |
RUN_IN |
|
|
| 16 | "1" |
RDY_IN |
|
|
| 15 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
RUN |
|
|
| 0 | "0" |
RDY |
|
|
| com_asic_ctrl_rst_out_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40040018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 | - |
com_phy_rst_out_n_in_ro |
|
|
| 26 | "0" |
EN_RES_REQ_com_phy_rst_out_n |
|
|
| 25 | "0" |
RES_REQ_com_phy_rst_out_n |
|
|
| 24 - 0 | 0 |
- |
reserved | |
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | com_mmio0_cfg |
| 1 | 4 | R/W | com_mmio1_cfg |
| 2 | 8 | R/W | com_mmio2_cfg |
| 3 | c | R/W | com_mmio3_cfg |
| 4 | 10 | R/W | com_mmio4_cfg |
| 5 | 14 | R/W | com_mmio5_cfg |
| 6 | 18 | R/W | com_mmio6_cfg |
| 7 | 1c | R/W | com_mmio7_cfg |
| 8 | 20 | R/W | com_mmio_pio_out_line_cfg0 |
| 9 | 24 | R/W | com_mmio_pio_out_line_set_cfg0 |
| a | 28 | R/W | com_mmio_pio_out_line_reset_cfg0 |
| b | 2c | R/W | com_mmio_pio_oe_line_cfg0 |
| c | 30 | R/W | com_mmio_pio_oe_line_set_cfg0 |
| d | 34 | R/W | com_mmio_pio_oe_line_reset_cfg0 |
| e | 38 | R | com_mmio_in_line_status0 |
| f | 3c | R | com_mmio_is_pio_status0 |
| com_mmio0_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x40040100 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | - |
status_in_ro |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
pio_out |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
pio_oe |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 - 11 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
com_mmio_in_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
com_mmio_out_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| com_mmio1_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40040104 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio2_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40040108 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio3_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4004010c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio4_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40040110 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio5_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40040114 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio6_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40040118 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio7_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4004011c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
com_mmio_in_inv |
|
||||||||
| 9 | "0" |
com_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
com_mmio_sel |
|
||||||||
| com_mmio_pio_out_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40040120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_pio_out_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40040124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_pio_out_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40040128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_pio_oe_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4004012c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_pio_oe_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40040130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_pio_oe_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40040134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
line |
|
|
| com_mmio_in_line_status0 |
|
|||
| R |
Address : 0x40040138 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | line |
|
||
| com_mmio_is_pio_status0 |
|
||||||||||||||||||||||
| R |
Address : 0x4004013c |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | - |
reserved | |||||||||||||||||||||
| 7 - 0 | line |
|
|||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | app_asic_ctrl_only_por |
| 1 | 4 | R/W | app_asic_ctrl_rst_out_cfg |
| 2-3f | 8-fc | - | reserved |
| app_asic_ctrl_only_por |
|
|||
| R/W |
0x00000000 |
Address : 0x40050000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| app_asic_ctrl_rst_out_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x40050004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 | - |
app_phy_rst_out_n_in_ro |
|
|
| 26 | "0" |
EN_RES_REQ_app_phy_rst_out_n |
|
|
| 25 | "0" |
RES_REQ_app_phy_rst_out_n |
|
|
| 24 - 0 | 0 |
- |
reserved | |
| app_mmio0_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x40050200 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | - |
status_in_ro |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
pio_out |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
pio_oe |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 - 11 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
app_mmio_in_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
app_mmio_out_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| app_mmio1_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050204 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio2_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050208 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio3_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005020c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio4_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050210 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio5_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050214 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio6_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050218 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio7_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005021c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio8_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050220 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio9_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050224 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio10_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050228 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio11_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005022c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio12_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050230 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio13_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050234 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio14_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050238 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio15_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005023c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio16_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050240 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio17_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050244 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio18_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050248 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio19_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005024c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio20_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050250 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio21_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050254 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio22_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050258 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio23_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005025c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio24_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050260 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio25_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050264 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio26_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050268 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio27_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005026c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio28_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050270 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio29_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050274 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio30_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050278 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio31_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005027c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio32_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050280 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio33_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050284 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio34_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050288 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio35_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005028c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio36_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050290 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio37_cfg |
|
||||||||||
| R/W |
0x00000032 |
Address : 0x40050294 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "110010" |
app_mmio_sel |
|
||||||||
| app_mmio38_cfg |
|
||||||||||
| R/W |
0x00000031 |
Address : 0x40050298 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "110001" |
app_mmio_sel |
|
||||||||
| app_mmio39_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005029c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio40_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502a0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio41_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502a4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio42_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502a8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio43_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502ac |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio44_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502b0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio45_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502b4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio46_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502b8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio47_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502bc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio48_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502c0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio49_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502c4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio50_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502c8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio51_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502cc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio52_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502d0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio53_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502d4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio54_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502d8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio55_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502dc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio56_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502e0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio57_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502e4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio58_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502e8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio59_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502ec |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio60_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502f0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio61_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502f4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio62_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502f8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio63_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400502fc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio64_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050300 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio65_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050304 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio66_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050308 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio67_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005030c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio68_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050310 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio69_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050314 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio70_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050318 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio71_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005031c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio72_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050320 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio73_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050324 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio74_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40050328 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio75_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4005032c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
app_mmio_in_inv |
|
||||||||
| 9 | "0" |
app_mmio_out_inv |
|
||||||||
| 8 - 6 | 0 |
- |
reserved | ||||||||
| 5 - 0 | "000000" |
app_mmio_sel |
|
||||||||
| app_mmio_pio_out_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050330 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050334 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050338 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4005033c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_set_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050340 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_set_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050344 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050348 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_reset_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4005034c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_out_line_reset_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050350 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050354 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050358 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x4005035c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050360 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_set_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050364 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_set_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050368 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4005036c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_reset_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050370 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| app_mmio_pio_oe_line_reset_cfg2 |
|
|||
| R/W |
0x00000000 |
Address : 0x40050374 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | |
| 11 - 0 | 0x0 |
line |
|
|
| app_mmio_in_line_status0 |
|
|||
| R |
Address : 0x40050378 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | line |
|
||
| app_mmio_in_line_status1 |
|
|||
| R |
Address : 0x4005037c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | line |
|
||
| app_mmio_in_line_status2 |
|
|||
| R |
Address : 0x40050380 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 12 | - |
reserved | ||
| 11 - 0 | line |
|
||
| app_mmio_is_pio_status0 |
|
||||||||||||||||||||||
| R |
Address : 0x40050384 |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | line |
|
|||||||||||||||||||||
| app_mmio_is_pio_status1 |
|
||||||||||||||||||||||
| R |
Address : 0x40050388 |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | line |
|
|||||||||||||||||||||
| app_mmio_is_pio_status2 |
|
||||||||||||||||||||||
| R |
Address : 0x4005038c |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | - |
reserved | |||||||||||||||||||||
| 11 - 0 | line |
|
|||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | mot_asic_ctrl_rstsyn |
| 1-3f | 4-fc | - | reserved |
| mot_asic_ctrl_rstsyn |
|
|||
| R |
Address : 0x40060000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 5 | - |
reserved | ||
| 4 | ext |
|
||
| 3 | host |
|
||
| 2 | res |
|
||
| 1 | nsrst |
|
||
| 0 | por |
|
||
| mot_mmio0_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x40060200 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | - |
status_in_ro |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
pio_out |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
pio_oe |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 - 11 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 - 7 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_mmio1_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060204 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio2_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060208 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio3_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006020c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio4_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060210 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio5_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060214 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio6_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060218 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio7_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006021c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio8_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060220 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio9_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060224 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio10_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060228 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio11_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006022c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio12_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060230 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio13_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060234 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio14_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060238 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio15_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006023c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio16_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060240 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio17_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060244 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio18_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060248 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio19_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006024c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio20_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060250 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio21_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060254 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio22_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060258 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio23_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006025c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio24_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060260 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio25_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060264 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio26_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060268 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio27_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006026c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio28_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060270 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio29_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060274 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio30_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060278 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio31_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006027c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio32_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060280 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio33_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060284 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio34_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060288 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio35_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006028c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio36_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060290 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio37_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060294 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio38_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x40060298 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio39_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x4006029c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio40_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602a0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio41_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602a4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio42_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602a8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio43_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602ac |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio44_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602b0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio45_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602b4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio46_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602b8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio47_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602bc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio48_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602c0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio49_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602c4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio50_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602c8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio51_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602cc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio52_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602d0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio53_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602d4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio54_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602d8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio55_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602dc |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio56_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602e0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio57_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602e4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio58_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602e8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio59_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602ec |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio60_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602f0 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio61_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602f4 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio62_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address : 0x400602f8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||||
| 18 | - |
status_in_ro |
|
||||||||
| 17 | "0" |
pio_out |
|
||||||||
| 16 | "0" |
pio_oe |
|
||||||||
| 15 - 11 | 0 |
- |
reserved | ||||||||
| 10 | "0" |
mot_mmio_in_inv |
|
||||||||
| 9 | "0" |
mot_mmio_out_inv |
|
||||||||
| 8 - 7 | 0 |
- |
reserved | ||||||||
| 6 - 0 | "0000000" |
mot_mmio_sel |
|
||||||||
| mot_mmio_pio_out_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400602fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_out_line_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060300 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_out_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060304 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_out_line_set_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060308 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_out_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4006030c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_out_line_reset_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060310 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060314 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060318 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_set_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x4006031c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_set_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060320 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_reset_cfg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060324 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
line |
|
|
| mot_mmio_pio_oe_line_reset_cfg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40060328 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |
| 30 - 0 | 0x0 |
line |
|
|
| mot_mmio_in_line_status0 |
|
|||
| R |
Address : 0x4006032c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | line |
|
||
| mot_mmio_in_line_status1 |
|
|||
| R |
Address : 0x40060330 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | - |
reserved | ||
| 30 - 0 | line |
|
||
| mot_mmio_is_pio_status0 |
|
||||||||||||||||||||||
| R |
Address : 0x40060334 |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | line |
|
|||||||||||||||||||||
| mot_mmio_is_pio_status1 |
|
||||||||||||||||||||||
| R |
Address : 0x40060338 |
Bits | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | - |
reserved | |||||||||||||||||||||
| 30 - 0 | line |
|
|||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | secenc_asic_ctrl_protect_com_intram0_0 |
| 1 | 4 | R/W | secenc_asic_ctrl_protect_com_intram0_1 |
| 2 | 8 | R/W | secenc_asic_ctrl_protect_com_intram2_0 |
| 3 | c | R/W | secenc_asic_ctrl_protect_com_intram2_1 |
| 4-3f | 10-fc | - | reserved |
| secenc_asic_ctrl_protect_com_intram0_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40070000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
secure_only |
|
|
| secenc_asic_ctrl_protect_com_intram0_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x40070004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
secure_only |
|
|
| secenc_asic_ctrl_protect_com_intram2_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x40070008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
secure_only |
|
|
| secenc_asic_ctrl_protect_com_intram2_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4007000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
secure_only |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | biss_scdata0_0 |
| 1 | 4 | R/W | biss_scdata0_1 |
| 2 | 8 | R/W | biss_scdata1_0 |
| 3 | c | R/W | biss_scdata1_1 |
| 4 | 10 | R/W | biss_scdata2_0 |
| 5 | 14 | R/W | biss_scdata2_1 |
| 6 | 18 | R/W | biss_scdata3_0 |
| 7 | 1c | R/W | biss_scdata3_1 |
| 8 | 20 | R/W | biss_scdata4_0 |
| 9 | 24 | R/W | biss_scdata4_1 |
| a | 28 | R/W | biss_scdata5_0 |
| b | 2c | R/W | biss_scdata5_1 |
| c | 30 | R/W | biss_scdata6_0 |
| d | 34 | R/W | biss_scdata6_1 |
| e | 38 | R/W | biss_scdata7_0 |
| f | 3c | R/W | biss_scdata7_1 |
| 10-1f | 40-7c | - | reserved |
| 20 | 80 | R/W | biss_rdata0 |
| 21 | 84 | R/W | biss_rdata1 |
| 22 | 88 | R/W | biss_rdata2 |
| 23 | 8c | R/W | biss_rdata3 |
| 24 | 90 | R/W | biss_rdata4 |
| 25 | 94 | R/W | biss_rdata5 |
| 26 | 98 | R/W | biss_rdata6 |
| 27 | 9c | R/W | biss_rdata7 |
| 28 | a0 | R/W | biss_rdata8 |
| 29 | a4 | R/W | biss_rdata9 |
| 2a | a8 | R/W | biss_rdata10 |
| 2b | ac | R/W | biss_rdata11 |
| 2c | b0 | R/W | biss_rdata12 |
| 2d | b4 | R/W | biss_rdata13 |
| 2e | b8 | R/W | biss_rdata14 |
| 2f | bc | R/W | biss_rdata15 |
| 30 | c0 | R/W | biss_sc0 |
| 31 | c4 | R/W | biss_sc1 |
| 32 | c8 | R/W | biss_sc2 |
| 33 | cc | R/W | biss_sc3 |
| 34 | d0 | R/W | biss_sc4 |
| 35 | d4 | R/W | biss_sc5 |
| 36 | d8 | R/W | biss_sc6 |
| 37 | dc | R/W | biss_sc7 |
| 38 | e0 | R/W | biss_ccc0 |
| 39 | e4 | R/W | biss_ccc1_mc0 |
| 3a | e8 | R/W | biss_mc1 |
| 3b | ec | R/W | biss_cc_sl |
| 3c | f0 | R | biss_status0 |
| 3d | f4 | R/W | biss_ir |
| 3e | f8 | R | biss_status1 |
| 3f | fc | - | reserved |
| biss_scdata0_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080000 Address@app_biss1 : 0x40080100 Address@mot_biss0 : 0x49200000 Address@mot_biss1 : 0x49200100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA0_0 |
|
|
| biss_scdata0_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080004 Address@app_biss1 : 0x40080104 Address@mot_biss0 : 0x49200004 Address@mot_biss1 : 0x49200104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA0_1 |
|
|
| biss_scdata1_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080008 Address@app_biss1 : 0x40080108 Address@mot_biss0 : 0x49200008 Address@mot_biss1 : 0x49200108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA1_0 |
|
|
| biss_scdata1_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008000c Address@app_biss1 : 0x4008010c Address@mot_biss0 : 0x4920000c Address@mot_biss1 : 0x4920010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA1_1 |
|
|
| biss_scdata2_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080010 Address@app_biss1 : 0x40080110 Address@mot_biss0 : 0x49200010 Address@mot_biss1 : 0x49200110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA2_0 |
|
|
| biss_scdata2_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080014 Address@app_biss1 : 0x40080114 Address@mot_biss0 : 0x49200014 Address@mot_biss1 : 0x49200114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA2_1 |
|
|
| biss_scdata3_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080018 Address@app_biss1 : 0x40080118 Address@mot_biss0 : 0x49200018 Address@mot_biss1 : 0x49200118 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA3_0 |
|
|
| biss_scdata3_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008001c Address@app_biss1 : 0x4008011c Address@mot_biss0 : 0x4920001c Address@mot_biss1 : 0x4920011c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA3_1 |
|
|
| biss_scdata4_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080020 Address@app_biss1 : 0x40080120 Address@mot_biss0 : 0x49200020 Address@mot_biss1 : 0x49200120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA4_0 |
|
|
| biss_scdata4_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080024 Address@app_biss1 : 0x40080124 Address@mot_biss0 : 0x49200024 Address@mot_biss1 : 0x49200124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA4_1 |
|
|
| biss_scdata5_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080028 Address@app_biss1 : 0x40080128 Address@mot_biss0 : 0x49200028 Address@mot_biss1 : 0x49200128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA5_0 |
|
|
| biss_scdata5_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008002c Address@app_biss1 : 0x4008012c Address@mot_biss0 : 0x4920002c Address@mot_biss1 : 0x4920012c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA5_1 |
|
|
| biss_scdata6_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080030 Address@app_biss1 : 0x40080130 Address@mot_biss0 : 0x49200030 Address@mot_biss1 : 0x49200130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA6_0 |
|
|
| biss_scdata6_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080034 Address@app_biss1 : 0x40080134 Address@mot_biss0 : 0x49200034 Address@mot_biss1 : 0x49200134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA6_1 |
|
|
| biss_scdata7_0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080038 Address@app_biss1 : 0x40080138 Address@mot_biss0 : 0x49200038 Address@mot_biss1 : 0x49200138 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA7_0 |
|
|
| biss_scdata7_1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008003c Address@app_biss1 : 0x4008013c Address@mot_biss0 : 0x4920003c Address@mot_biss1 : 0x4920013c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
SCDATA7_1 |
|
|
| biss_rdata0 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080080 Address@app_biss1 : 0x40080180 Address@mot_biss0 : 0x49200080 Address@mot_biss1 : 0x49200180 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA0 |
|
|
| biss_rdata1 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080084 Address@app_biss1 : 0x40080184 Address@mot_biss0 : 0x49200084 Address@mot_biss1 : 0x49200184 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA1 |
|
|
| biss_rdata2 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080088 Address@app_biss1 : 0x40080188 Address@mot_biss0 : 0x49200088 Address@mot_biss1 : 0x49200188 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA2 |
|
|
| biss_rdata3 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008008c Address@app_biss1 : 0x4008018c Address@mot_biss0 : 0x4920008c Address@mot_biss1 : 0x4920018c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA3 |
|
|
| biss_rdata4 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080090 Address@app_biss1 : 0x40080190 Address@mot_biss0 : 0x49200090 Address@mot_biss1 : 0x49200190 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA4 |
|
|
| biss_rdata5 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080094 Address@app_biss1 : 0x40080194 Address@mot_biss0 : 0x49200094 Address@mot_biss1 : 0x49200194 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA5 |
|
|
| biss_rdata6 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x40080098 Address@app_biss1 : 0x40080198 Address@mot_biss0 : 0x49200098 Address@mot_biss1 : 0x49200198 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA6 |
|
|
| biss_rdata7 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x4008009c Address@app_biss1 : 0x4008019c Address@mot_biss0 : 0x4920009c Address@mot_biss1 : 0x4920019c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA7 |
|
|
| biss_rdata8 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800a0 Address@app_biss1 : 0x400801a0 Address@mot_biss0 : 0x492000a0 Address@mot_biss1 : 0x492001a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA8 |
|
|
| biss_rdata9 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800a4 Address@app_biss1 : 0x400801a4 Address@mot_biss0 : 0x492000a4 Address@mot_biss1 : 0x492001a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA9 |
|
|
| biss_rdata10 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800a8 Address@app_biss1 : 0x400801a8 Address@mot_biss0 : 0x492000a8 Address@mot_biss1 : 0x492001a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA10 |
|
|
| biss_rdata11 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800ac Address@app_biss1 : 0x400801ac Address@mot_biss0 : 0x492000ac Address@mot_biss1 : 0x492001ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA11 |
|
|
| biss_rdata12 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800b0 Address@app_biss1 : 0x400801b0 Address@mot_biss0 : 0x492000b0 Address@mot_biss1 : 0x492001b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA12 |
|
|
| biss_rdata13 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800b4 Address@app_biss1 : 0x400801b4 Address@mot_biss0 : 0x492000b4 Address@mot_biss1 : 0x492001b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA13 |
|
|
| biss_rdata14 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800b8 Address@app_biss1 : 0x400801b8 Address@mot_biss0 : 0x492000b8 Address@mot_biss1 : 0x492001b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA14 |
|
|
| biss_rdata15 |
|
|||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800bc Address@app_biss1 : 0x400801bc Address@mot_biss0 : 0x492000bc Address@mot_biss1 : 0x492001bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
RDATA15 |
|
|
| biss_sc0 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800c0 Address@app_biss1 : 0x400801c0 Address@mot_biss0 : 0x492000c0 Address@mot_biss1 : 0x492001c0 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART0 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS0 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY0 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP0 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD0 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN0 |
|
||||||||||||||||||||||||
| biss_sc1 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800c4 Address@app_biss1 : 0x400801c4 Address@mot_biss0 : 0x492000c4 Address@mot_biss1 : 0x492001c4 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART1 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS1 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY1 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP1 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD1 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN1 |
|
||||||||||||||||||||||||
| biss_sc2 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800c8 Address@app_biss1 : 0x400801c8 Address@mot_biss0 : 0x492000c8 Address@mot_biss1 : 0x492001c8 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART2 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS2 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY2 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP2 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD2 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN2 |
|
||||||||||||||||||||||||
| biss_sc3 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800cc Address@app_biss1 : 0x400801cc Address@mot_biss0 : 0x492000cc Address@mot_biss1 : 0x492001cc |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART3 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS3 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY3 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP3 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD3 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN3 |
|
||||||||||||||||||||||||
| biss_sc4 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800d0 Address@app_biss1 : 0x400801d0 Address@mot_biss0 : 0x492000d0 Address@mot_biss1 : 0x492001d0 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART4 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS4 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY4 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP4 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD4 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN4 |
|
||||||||||||||||||||||||
| biss_sc5 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800d4 Address@app_biss1 : 0x400801d4 Address@mot_biss0 : 0x492000d4 Address@mot_biss1 : 0x492001d4 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART5 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS5 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY5 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP5 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD5 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN5 |
|
||||||||||||||||||||||||
| biss_sc6 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800d8 Address@app_biss1 : 0x400801d8 Address@mot_biss0 : 0x492000d8 Address@mot_biss1 : 0x492001d8 |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART6 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS6 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY6 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP6 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSCD6 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN6 |
|
||||||||||||||||||||||||
| biss_sc7 |
|
||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800dc Address@app_biss1 : 0x400801dc Address@mot_biss0 : 0x492000dc Address@mot_biss1 : 0x492001dc |
Bits | Reset value | Name | Description | |||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0x0 |
SCRCSTART7 |
|
||||||||||||||||||||||||
| 15 | "0" |
SELCRCS7 |
|
||||||||||||||||||||||||
| 14 - 8 | "0000000" |
SCRCPOLY7 |
|
||||||||||||||||||||||||
| 7 | "0" |
LSTOP7 |
|
||||||||||||||||||||||||
| 6 | "0" |
ENSC7 |
|
||||||||||||||||||||||||
| 5 - 0 | "000000" |
SCDLEN7 |
|
||||||||||||||||||||||||
| biss_ccc0 |
|
|||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800e0 Address@app_biss1 : 0x400801e0 Address@mot_biss0 : 0x492000e0 Address@mot_biss1 : 0x492001e0 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |||||
| 29 - 24 | "000000" |
REGNUM |
|
|||||
| 23 | "0" |
WNR |
|
|||||
| 22 - 16 | "0000000" |
REGADR |
|
|||||
| 15 - 0 | 0 |
- |
reserved | |||||
| biss_ccc1_mc0 |
|
|||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800e4 Address@app_biss1 : 0x400801e4 Address@mot_biss0 : 0x492000e4 Address@mot_biss1 : 0x492001e4 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||
| 25 | "0" |
NOCRC |
|
|||||||||||||||||||||||||||||||
| 24 | "0" |
SINGLEBANK |
|
|||||||||||||||||||||||||||||||
| 23 - 21 | "000" |
FREQR |
|
|||||||||||||||||||||||||||||||
| 20 - 16 | "00000" |
FREQS |
|
|||||||||||||||||||||||||||||||
| 15 | "0" |
CTS |
|
|||||||||||||||||||||||||||||||
| 14 | "0" |
REGVERS |
|
|||||||||||||||||||||||||||||||
| 13 - 12 | "00" |
CMD |
|
|||||||||||||||||||||||||||||||
| 11 | "0" |
IDA_TEST |
|
|||||||||||||||||||||||||||||||
| 10 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||
| 9 | "0" |
EN_MO |
|
|||||||||||||||||||||||||||||||
| 8 | "0" |
HOLDCDM |
|
|||||||||||||||||||||||||||||||
| 7 - 2 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||
| 1 - 0 | "00" |
CHSEL |
|
|||||||||||||||||||||||||||||||
| biss_mc1 |
|
|||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800e8 Address@app_biss1 : 0x400801e8 Address@mot_biss0 : 0x492000e8 Address@mot_biss1 : 0x492001e8 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
VERSION |
|
|||||||||
| 23 - 16 | "00000000" |
REVISION |
|
|||||||||
| 15 - 8 | "00000000" |
MO_BUSY |
|
|||||||||
| 7 - 0 | "00000000" |
FREQAGS |
|
|||||||||
| biss_cc_sl |
|
|||||||||||||||||||||||
| R/W |
0x00000001 |
Address@app_biss0 : 0x400800ec Address@app_biss1 : 0x400801ec Address@mot_biss0 : 0x492000ec Address@mot_biss1 : 0x492001ec |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
ACTnSENS |
|
|||||||||||||||||||||
| 23 - 12 | 0 |
- |
reserved | |||||||||||||||||||||
| 11 - 10 | "00" |
CFGCH2 |
|
|||||||||||||||||||||
| 9 - 8 | "00" |
CFGCH1 |
|
|||||||||||||||||||||
| 7 - 5 | 0 |
- |
reserved | |||||||||||||||||||||
| 4 | "0" |
SLAVELOC5 |
|
|||||||||||||||||||||
| 3 - 0 | "0001" |
cc_sl_reserved1 |
||||||||||||||||||||||
| biss_status0 |
|
||||||||
| R |
Address@app_biss0 : 0x400800f0 Address@app_biss1 : 0x400801f0 Address@mot_biss0 : 0x492000f0 Address@mot_biss1 : 0x492001f0 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 | CDMTIMEOUT |
|
|||||||
| 30 | CDSSEL |
|
|||||||
| 29 - 24 | REGBYTES |
|
|||||||
| 23 | SVALID7 |
|
|||||||
| 22 | - |
reserved | |||||||
| 21 | SVALID6 |
|
|||||||
| 20 | - |
reserved | |||||||
| 19 | SVALID5 |
|
|||||||
| 18 | - |
reserved | |||||||
| 17 | SVALID4 |
|
|||||||
| 16 | - |
reserved | |||||||
| 15 | SVALID3 |
|
|||||||
| 14 | - |
reserved | |||||||
| 13 | SVALID2 |
|
|||||||
| 12 | - |
reserved | |||||||
| 11 | SVALID1 |
|
|||||||
| 10 | - |
reserved | |||||||
| 9 | SVALID0 |
|
|||||||
| 8 | - |
reserved | |||||||
| 7 | nERR |
|
|||||||
| 6 | nAGSERR |
|
|||||||
| 5 | nDELAYERR |
|
|||||||
| 4 | nSCDERR |
|
|||||||
| 3 | nREGERR |
|
|||||||
| 2 | REGEND |
|
|||||||
| 1 | status0_reserved1 |
|
|||||||
| 0 | EOT |
|
|||||||
| biss_ir |
|
|||||||||||
| R/W |
0x00000000 |
Address@app_biss0 : 0x400800f4 Address@app_biss1 : 0x400801f4 Address@mot_biss0 : 0x492000f4 Address@mot_biss1 : 0x492001f4 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||
| 15 | "0" |
MAVO |
|
|||||||||
| 14 | "0" |
MAFO |
|
|||||||||
| 13 | "0" |
MAVS |
|
|||||||||
| 12 | "0" |
MAFS |
|
|||||||||
| 11 - 10 | "00" |
CFGIF |
|
|||||||||
| 9 | "0" |
ENTEST |
|
|||||||||
| 8 | "0" |
CLKENI |
|
|||||||||
| 7 | "0" |
BREAK |
|
|||||||||
| 6 | "0" |
HOLDBANK |
|
|||||||||
| 5 | "0" |
SWBANK |
|
|||||||||
| 4 | "0" |
INIT |
|
|||||||||
| 3 - 1 | "000" |
INSTR |
|
|||||||||
| 0 | "0" |
AGS |
|
|||||||||
| biss_status1 |
|
|||||||
| R |
Address@app_biss0 : 0x400800f8 Address@app_biss1 : 0x400801f8 Address@mot_biss0 : 0x492000f8 Address@mot_biss1 : 0x492001f8 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 25 | - |
reserved | ||||||
| 24 | SWBANKFAILS |
|
||||||
| 23 - 2 | - |
reserved | ||||||
| 1 | CDS1 |
|
||||||
| 0 | SL1 |
|
||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | biss_ctrl_trigger_cfg |
| 1 | 4 | R/W | biss_ctrl_trigger |
| 2 | 8 | R/W | biss_ctrl_irq_raw |
| 3 | c | R | biss_ctrl_irq_masked |
| 4 | 10 | R/W | biss_ctrl_irq_msk_set |
| 5 | 14 | R/W | biss_ctrl_irq_msk_reset |
| 6-7 | 18-1c | - | reserved |
| biss_ctrl_trigger_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_biss_ctrl0 : 0x40080200 Address@app_biss_ctrl1 : 0x40080220 Address@mot_biss_ctrl0 : 0x49200200 Address@mot_biss_ctrl1 : 0x49200220 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 - 0 | "00000" |
sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| biss_ctrl_trigger |
|
|||
| R/W |
0x00000000 |
Address@app_biss_ctrl0 : 0x40080204 Address@app_biss_ctrl1 : 0x40080224 Address@mot_biss_ctrl0 : 0x49200204 Address@mot_biss_ctrl1 : 0x49200224 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
manual |
|
|
| biss_ctrl_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@app_biss_ctrl0 : 0x40080208 Address@app_biss_ctrl1 : 0x40080228 Address@mot_biss_ctrl0 : 0x49200208 Address@mot_biss_ctrl1 : 0x49200228 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
err |
|
|
| 0 | "0" |
eot |
|
|
| biss_ctrl_irq_masked |
|
|||
| R |
Address@app_biss_ctrl0 : 0x4008020c Address@app_biss_ctrl1 : 0x4008022c Address@mot_biss_ctrl0 : 0x4920020c Address@mot_biss_ctrl1 : 0x4920022c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | err |
|
||
| 0 | eot |
|
||
| biss_ctrl_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address@app_biss_ctrl0 : 0x40080210 Address@app_biss_ctrl1 : 0x40080230 Address@mot_biss_ctrl0 : 0x49200210 Address@mot_biss_ctrl1 : 0x49200230 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
err |
|
|
| 0 | "0" |
eot |
|
|
| biss_ctrl_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address@app_biss_ctrl0 : 0x40080214 Address@app_biss_ctrl1 : 0x40080234 Address@mot_biss_ctrl0 : 0x49200214 Address@mot_biss_ctrl1 : 0x49200234 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
err |
|
|
| 0 | "0" |
eot |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | endat_send |
| 1 | 4 | R | endat_receive1_0 |
| 2 | 8 | R | endat_receive1_1 |
| 3 | c | R | endat_receive2 |
| 4 | 10 | R | endat_receive3 |
| 5 | 14 | R/W | endat_conf1 |
| 6 | 18 | R/W | endat_conf2 |
| 7 | 1c | R/W | endat_conf3 |
| 8 | 20 | R/W | endat_stat |
| 9 | 24 | R/W | endat_int |
| a | 28 | R | endat_test1 |
| b | 2c | R/W | endat_test2 |
| c | 30 | R | endat_receive4_0 |
| d | 34 | R | endat_receive4_1 |
| e | 38 | W | endat_sw_strobe |
| f | 3c | R | endat_id |
| endat_send |
|
|||
| R/W |
0x07000000 |
Address@app_endat0 : 0x40080240 Address@app_endat1 : 0x40080280 Address@mot_endat0 : 0x49200240 Address@mot_endat1 : 0x49200280 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 24 | "000111" |
byte4 |
|
|
| 23 - 16 | "00000000" |
byte3 |
|
|
| 15 - 8 | "00000000" |
byte2 |
|
|
| 7 - 0 | "00000000" |
byte1 |
|
|
| endat_receive1_0 |
|
|||
| R |
Address@app_endat0 : 0x40080244 Address@app_endat1 : 0x40080284 Address@mot_endat0 : 0x49200244 Address@mot_endat1 : 0x49200284 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | byte4 |
|
||
| 23 - 16 | byte3 |
|
||
| 15 - 8 | byte2 |
|
||
| 7 - 0 | byte1 |
|
||
| endat_receive1_1 |
|
|||
| R |
Address@app_endat0 : 0x40080248 Address@app_endat1 : 0x40080288 Address@mot_endat0 : 0x49200248 Address@mot_endat1 : 0x49200288 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 16 | byte7 |
|
||
| 15 - 8 | byte6 |
|
||
| 7 - 0 | byte5 |
|
||
| endat_receive2 |
|
|||
| R |
Address@app_endat0 : 0x4008024c Address@app_endat1 : 0x4008028c Address@mot_endat0 : 0x4920024c Address@mot_endat1 : 0x4920028c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | byte4 |
|
||
| 23 - 16 | byte3 |
|
||
| 15 - 8 | byte2 |
|
||
| 7 - 0 | byte1 |
|
||
| endat_receive3 |
|
|||
| R |
Address@app_endat0 : 0x40080250 Address@app_endat1 : 0x40080290 Address@mot_endat0 : 0x49200250 Address@mot_endat1 : 0x49200290 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | byte4 |
|
||
| 23 - 16 | byte3 |
|
||
| 15 - 8 | byte2 |
|
||
| 7 - 0 | byte1 |
|
||
| endat_conf1 |
|
|||||||
| R/W |
0x00000df0 |
Address@app_endat0 : 0x40080254 Address@app_endat1 : 0x40080294 Address@mot_endat0 : 0x49200254 Address@mot_endat1 : 0x49200294 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 30 | "00" |
endat_ssi |
|
|||||
| 29 | "0" |
ic_reset |
|
|||||
| 28 - 26 | "000" |
f_sys |
|
|||||
| 25 | 0 |
- |
reserved | |||||
| 24 | "0" |
delay_comp |
|
|||||
| 23 - 16 | "00000000" |
cable_prop_time |
|
|||||
| 15 | "0" |
auto_reset |
|
|||||
| 14 | "0" |
reset_window |
|
|||||
| 13 - 8 | "001101" |
data_word_len |
|
|||||
| 7 - 4 | "1111" |
f_tclk |
|
|||||
| 3 | 0 |
- |
reserved | |||||
| 2 | "0" |
endat_cont_clk_mode |
|
|||||
| 1 | "0" |
uncond_transfer |
|
|||||
| 0 | "0" |
hw_strobe |
|
|||||
| endat_conf2 |
|
|||
| R/W |
0x00040000 |
Address@app_endat0 : 0x40080258 Address@app_endat1 : 0x40080298 Address@mot_endat0 : 0x49200258 Address@mot_endat1 : 0x49200298 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
hw_strobe_delay |
|
|
| 23 | 0 |
- |
reserved | |
| 22 | "0" |
rtm |
|
|
| 21 - 19 | "000" |
filter |
|
|
| 18 - 16 | "100" |
t_st |
|
|
| 15 - 8 | "00000000" |
watchdog |
|
|
| 7 - 0 | "00000000" |
timer_for_sampling_rate |
|
|
| endat_conf3 |
|
|||
| R/W |
0x000000cc |
Address@app_endat0 : 0x4008025c Address@app_endat1 : 0x4008029c Address@mot_endat0 : 0x4920025c Address@mot_endat1 : 0x4920029c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
speed |
|
|
| 14 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
dw |
|
|
| 7 - 3 | "11001" |
singleturn_res |
|
|
| 2 | "1" |
gray_to_binary |
|
|
| 1 | "0" |
format |
|
|
| 0 | "0" |
parity |
|
|
| endat_stat |
|
|||
| R/W |
0x40000400 |
Address@app_endat0 : 0x40080260 Address@app_endat1 : 0x400802a0 Address@mot_endat0 : 0x49200260 Address@mot_endat1 : 0x492002a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
ready |
|
|
| 30 | "1" |
ready_for_strobe |
|
|
| 29 | "0" |
speed_ready |
|
|
| 28 | "0" |
rtm_stop |
|
|
| 27 | "0" |
rtm_start |
|
|
| 26 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
prop_time_measurement |
|
|
| 22 | "0" |
delay_comp |
|
|
| 21 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
f_type3 |
|
|
| 17 | "0" |
watchdog |
|
|
| 16 | "0" |
spike |
|
|
| 15 | "0" |
wrn |
|
|
| 14 | "0" |
rm |
|
|
| 13 | "0" |
busy |
|
|
| 12 | "0" |
crc_zi2 |
|
|
| 11 | "0" |
crc_zi1 |
|
|
| 10 | "1" |
error2 |
|
|
| 9 | "0" |
receive3_reg |
|
|
| 8 | "0" |
receive2_reg |
|
|
| 7 | "0" |
ir7 |
|
|
| 6 | "0" |
ir6 |
|
|
| 5 | "0" |
mrs_adr |
|
|
| 4 | "0" |
f_type2 |
|
|
| 3 | "0" |
f_type1 |
|
|
| 2 | "0" |
crcpw_parity |
|
|
| 1 | "0" |
error1 |
|
|
| 0 | "0" |
receive1_reg |
|
|
| endat_int |
|
|||
| R/W |
0x00000000 |
Address@app_endat0 : 0x40080264 Address@app_endat1 : 0x400802a4 Address@mot_endat0 : 0x49200264 Address@mot_endat1 : 0x492002a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
ready |
|
|
| 30 | 0 |
- |
reserved | |
| 29 | "0" |
speed_ready |
|
|
| 28 - 19 | 0 |
- |
reserved | |
| 18 | "0" |
f_type3 |
|
|
| 17 | "0" |
watchdog |
|
|
| 16 | "0" |
spike |
|
|
| 15 | "0" |
wrn |
|
|
| 14 | "0" |
RM |
|
|
| 13 | "0" |
busy |
|
|
| 12 | "0" |
crc_zi2 |
|
|
| 11 | "0" |
crc_zi1 |
|
|
| 10 | "0" |
error2 |
|
|
| 9 | "0" |
receive3_reg |
|
|
| 8 | "0" |
receive2_reg |
|
|
| 7 | "0" |
ir7 |
|
|
| 6 | "0" |
ir6 |
|
|
| 5 | "0" |
mrs_adr |
|
|
| 4 | "0" |
f_type2 |
|
|
| 3 | "0" |
f_type1 |
|
|
| 2 | "0" |
crcpw_parity |
|
|
| 1 | "0" |
error1 |
|
|
| 0 | "0" |
receive1_reg |
|
|
| endat_test1 |
|
|||
| R |
Address@app_endat0 : 0x40080268 Address@app_endat1 : 0x400802a8 Address@mot_endat0 : 0x49200268 Address@mot_endat1 : 0x492002a8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 10 | ic_test_values |
|
||
| 9 - 4 | enDat_automation_engine |
|
||
| 3 | - |
reserved | ||
| 2 - 1 | status_zi |
|
||
| 0 | dl_high |
|
||
| endat_test2 |
|
|||
| R/W |
0x00000000 |
Address@app_endat0 : 0x4008026c Address@app_endat1 : 0x400802ac Address@mot_endat0 : 0x4920026c Address@mot_endat1 : 0x492002ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
ic_test_data |
|
|
| 15 - 14 | "00" |
sel_test_mux3 |
|
|
| 13 - 12 | "00" |
sel_test_mux2 |
|
|
| 11 | "0" |
test_mode_divider |
|
|
| 10 - 8 | "000" |
selection_add_info |
|
|
| 7 | "0" |
ic_test_mode |
|
|
| 6 | 0 |
- |
reserved | |
| 5 - 4 | "00" |
sel_test_mux |
|
|
| 3 | "0" |
test_receive_reg |
|
|
| 2 | "0" |
selection_tst_out |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| endat_receive4_0 |
|
|||
| R |
Address@app_endat0 : 0x40080270 Address@app_endat1 : 0x400802b0 Address@mot_endat0 : 0x49200270 Address@mot_endat1 : 0x492002b0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | byte4 |
|
||
| 23 - 16 | byte3 |
|
||
| 15 - 8 | byte2 |
|
||
| 7 - 0 | byte1 |
|
||
| endat_receive4_1 |
|
|||
| R |
Address@app_endat0 : 0x40080274 Address@app_endat1 : 0x400802b4 Address@mot_endat0 : 0x49200274 Address@mot_endat1 : 0x492002b4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 8 | byte6 |
|
||
| 7 - 0 | byte5 |
|
||
| endat_sw_strobe |
|
|||
| W |
0x00000000 |
Address@app_endat0 : 0x40080278 Address@app_endat1 : 0x400802b8 Address@mot_endat0 : 0x49200278 Address@mot_endat1 : 0x492002b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sw_strobe |
|
|
| endat_id |
|
|||||||||
| R |
Address@app_endat0 : 0x4008027c Address@app_endat1 : 0x400802bc Address@mot_endat0 : 0x4920027c Address@mot_endat1 : 0x492002bc |
Bits | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | id |
|
||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | endat_ctrl_trigger_cfg |
| 1 | 4 | R/W | endat_ctrl_trigger |
| 2 | 8 | R/W | endat_ctrl_strobe_cfg |
| 3 | c | - | reserved |
| endat_ctrl_trigger_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_endat_ctrl0 : 0x400802c0 Address@app_endat_ctrl1 : 0x400802d0 Address@mot_endat_ctrl0 : 0x492002c0 Address@mot_endat_ctrl1 : 0x492002d0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 - 0 | "00000" |
sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| endat_ctrl_trigger |
|
|||
| R/W |
0x00000000 |
Address@app_endat_ctrl0 : 0x400802c4 Address@app_endat_ctrl1 : 0x400802d4 Address@mot_endat_ctrl0 : 0x492002c4 Address@mot_endat_ctrl1 : 0x492002d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
manual |
|
|
| endat_ctrl_strobe_cfg |
|
|||||||
| R/W |
0x00000303 |
Address@app_endat_ctrl0 : 0x400802c8 Address@app_endat_ctrl1 : 0x400802d8 Address@mot_endat_ctrl0 : 0x492002c8 Address@mot_endat_ctrl1 : 0x492002d8 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||
| 15 - 8 | "00000011" |
high_len |
|
|||||
| 7 - 0 | "00000011" |
low_len |
|
|||||
| gpio_app_cfg0 |
|
|||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080500 Address@mot_gpio : 0x49200500 |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |||||||||||||||||||||
| 14 | "0" |
blink_once |
|
|||||||||||||||||||||
| 13 - 9 | "00000" |
blink_len |
|
|||||||||||||||||||||
| 8 - 5 | "0000" |
count_ref |
|
|||||||||||||||||||||
| 4 | "0" |
inv |
|
|||||||||||||||||||||
| 3 - 0 | "0000" |
mode |
|
|||||||||||||||||||||
| gpio_app_cfg1 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080504 Address@mot_gpio : 0x49200504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg2 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080508 Address@mot_gpio : 0x49200508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg3 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008050c Address@mot_gpio : 0x4920050c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg4 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080510 Address@mot_gpio : 0x49200510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg5 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080514 Address@mot_gpio : 0x49200514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg6 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080518 Address@mot_gpio : 0x49200518 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_cfg7 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008051c Address@mot_gpio : 0x4920051c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
blink_once |
|
|
| 13 - 9 | "00000" |
blink_len |
|
|
| 8 - 5 | "0000" |
count_ref |
|
|
| 4 | "0" |
inv |
|
|
| 3 - 0 | "0000" |
mode |
|
|
| gpio_app_tc0 |
|
|||||||||||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080520 Address@mot_gpio : 0x49200520 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|||||||||
| gpio_app_tc1 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080524 Address@mot_gpio : 0x49200524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc2 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080528 Address@mot_gpio : 0x49200528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc3 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008052c Address@mot_gpio : 0x4920052c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc4 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080530 Address@mot_gpio : 0x49200530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc5 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080534 Address@mot_gpio : 0x49200534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc6 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080538 Address@mot_gpio : 0x49200538 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_tc7 |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008053c Address@mot_gpio : 0x4920053c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter0_ctrl |
|
|||||||||||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080540 Address@mot_gpio : 0x49200540 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |||||||||
| 9 - 7 | "000" |
gpio_ref |
|
|||||||||
| 6 - 5 | "00" |
event_act |
|
|||||||||
| 4 | "0" |
once |
|
|||||||||
| 3 | "0" |
sel_event |
|
|||||||||
| 2 | "0" |
irq_en |
|
|||||||||
| 1 | "0" |
sym_nasym |
|
|||||||||
| 0 | "0" |
run |
|
|||||||||
| gpio_app_counter1_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080544 Address@mot_gpio : 0x49200544 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter2_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080548 Address@mot_gpio : 0x49200548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter3_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008054c Address@mot_gpio : 0x4920054c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter4_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080550 Address@mot_gpio : 0x49200550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter5_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080554 Address@mot_gpio : 0x49200554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter6_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080558 Address@mot_gpio : 0x49200558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter7_ctrl |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008055c Address@mot_gpio : 0x4920055c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 - 7 | "000" |
gpio_ref |
|
|
| 6 - 5 | "00" |
event_act |
|
|
| 4 | "0" |
once |
|
|
| 3 | "0" |
sel_event |
|
|
| 2 | "0" |
irq_en |
|
|
| 1 | "0" |
sym_nasym |
|
|
| 0 | "0" |
run |
|
|
| gpio_app_counter0_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080560 Address@mot_gpio : 0x49200560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter1_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080564 Address@mot_gpio : 0x49200564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter2_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080568 Address@mot_gpio : 0x49200568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter3_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008056c Address@mot_gpio : 0x4920056c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter4_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080570 Address@mot_gpio : 0x49200570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter5_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080574 Address@mot_gpio : 0x49200574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter6_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080578 Address@mot_gpio : 0x49200578 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter7_max |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008057c Address@mot_gpio : 0x4920057c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter0_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080580 Address@mot_gpio : 0x49200580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter1_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080584 Address@mot_gpio : 0x49200584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter2_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080588 Address@mot_gpio : 0x49200588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter3_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008058c Address@mot_gpio : 0x4920058c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter4_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080590 Address@mot_gpio : 0x49200590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter5_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080594 Address@mot_gpio : 0x49200594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter6_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x40080598 Address@mot_gpio : 0x49200598 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_counter7_cnt |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x4008059c Address@mot_gpio : 0x4920059c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| gpio_app_line |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805a0 Address@mot_gpio : 0x492005a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
val |
|
|
| gpio_app_in |
|
|||
| R |
Address@app_gpio : 0x400805a4 Address@mot_gpio : 0x492005a4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | val |
|
||
| gpio_app_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805a8 Address@mot_gpio : 0x492005a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
gpio_app7 |
|
|
| 6 | "0" |
gpio_app6 |
|
|
| 5 | "0" |
gpio_app5 |
|
|
| 4 | "0" |
gpio_app4 |
|
|
| 3 | "0" |
gpio_app3 |
|
|
| 2 | "0" |
gpio_app2 |
|
|
| 1 | "0" |
gpio_app1 |
|
|
| 0 | "0" |
gpio_app0 |
|
|
| gpio_app_irq_masked |
|
|||
| R |
Address@app_gpio : 0x400805ac Address@mot_gpio : 0x492005ac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | gpio_app7 |
|
||
| 6 | gpio_app6 |
|
||
| 5 | gpio_app5 |
|
||
| 4 | gpio_app4 |
|
||
| 3 | gpio_app3 |
|
||
| 2 | gpio_app2 |
|
||
| 1 | gpio_app1 |
|
||
| 0 | gpio_app0 |
|
||
| gpio_app_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805b0 Address@mot_gpio : 0x492005b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
gpio_app7 |
|
|
| 6 | "0" |
gpio_app6 |
|
|
| 5 | "0" |
gpio_app5 |
|
|
| 4 | "0" |
gpio_app4 |
|
|
| 3 | "0" |
gpio_app3 |
|
|
| 2 | "0" |
gpio_app2 |
|
|
| 1 | "0" |
gpio_app1 |
|
|
| 0 | "0" |
gpio_app0 |
|
|
| gpio_app_irq_mask_rst |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805b4 Address@mot_gpio : 0x492005b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
gpio_app7 |
|
|
| 6 | "0" |
gpio_app6 |
|
|
| 5 | "0" |
gpio_app5 |
|
|
| 4 | "0" |
gpio_app4 |
|
|
| 3 | "0" |
gpio_app3 |
|
|
| 2 | "0" |
gpio_app2 |
|
|
| 1 | "0" |
gpio_app1 |
|
|
| 0 | "0" |
gpio_app0 |
|
|
| gpio_app_cnt_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805b8 Address@mot_gpio : 0x492005b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
cnt7 |
|
|
| 6 | "0" |
cnt6 |
|
|
| 5 | "0" |
cnt5 |
|
|
| 4 | "0" |
cnt4 |
|
|
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| gpio_app_cnt_irq_masked |
|
|||
| R |
Address@app_gpio : 0x400805bc Address@mot_gpio : 0x492005bc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | cnt7 |
|
||
| 6 | cnt6 |
|
||
| 5 | cnt5 |
|
||
| 4 | cnt4 |
|
||
| 3 | cnt3 |
|
||
| 2 | cnt2 |
|
||
| 1 | cnt1 |
|
||
| 0 | cnt0 |
|
||
| gpio_app_cnt_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805c0 Address@mot_gpio : 0x492005c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
cnt7 |
|
|
| 6 | "0" |
cnt6 |
|
|
| 5 | "0" |
cnt5 |
|
|
| 4 | "0" |
cnt4 |
|
|
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| gpio_app_cnt_irq_mask_rst |
|
|||
| R/W |
0x00000000 |
Address@app_gpio : 0x400805c4 Address@mot_gpio : 0x492005c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
cnt7 |
|
|
| 6 | "0" |
cnt6 |
|
|
| 5 | "0" |
cnt5 |
|
|
| 4 | "0" |
cnt4 |
|
|
| 3 | "0" |
cnt3 |
|
|
| 2 | "0" |
cnt2 |
|
|
| 1 | "0" |
cnt1 |
|
|
| 0 | "0" |
cnt0 |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | trigger_irq_cfg |
| 1 | 4 | R/W | trigger_irq_irq_raw |
| 2 | 8 | R/W | trigger_irq_irq_masked |
| 3 | c | R/W | trigger_irq_irq_mask_set |
| 4 | 10 | R/W | trigger_irq_irq_mask_rst |
| 5-7 | 14-1c | - | reserved |
| trigger_irq_cfg |
|
||||||||
| R/W |
0x00000000 |
Address@app_trigger_irq : 0x40080760 Address@app_trigger_irq_global : 0x40080780 Address@mot_trigger_irq : 0x49200760 Address@mot_trigger_irq_global : 0x49200780 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | ||||||
| 1 - 0 | "00" |
trigger_out_polarity |
|
||||||
| trigger_irq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@app_trigger_irq : 0x40080764 Address@app_trigger_irq_global : 0x40080784 Address@mot_trigger_irq : 0x49200764 Address@mot_trigger_irq_global : 0x49200784 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
trigger_out_edge1 |
|
|
| 0 | "0" |
trigger_out_edge0 |
|
|
| trigger_irq_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@app_trigger_irq : 0x40080768 Address@app_trigger_irq_global : 0x40080788 Address@mot_trigger_irq : 0x49200768 Address@mot_trigger_irq_global : 0x49200788 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
trigger_out_edge1 |
|
|
| 0 | "0" |
trigger_out_edge0 |
|
|
| trigger_irq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@app_trigger_irq : 0x4008076c Address@app_trigger_irq_global : 0x4008078c Address@mot_trigger_irq : 0x4920076c Address@mot_trigger_irq_global : 0x4920078c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
trigger_out_edge1 |
|
|
| 0 | "0" |
trigger_out_edge0 |
|
|
| trigger_irq_irq_mask_rst |
|
|||||||||
| R/W |
0x00000000 |
Address@app_trigger_irq : 0x40080770 Address@app_trigger_irq_global : 0x40080790 Address@mot_trigger_irq : 0x49200770 Address@mot_trigger_irq_global : 0x49200790 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||
| 1 | "0" |
trigger_out_edge1 |
|
|||||||
| 0 | "0" |
trigger_out_edge0 |
|
|||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | dmac_chsrc_ad |
| 1 | 4 | R/W | dmac_chdest_ad |
| 2 | 8 | R/W | dmac_chlink |
| 3 | c | R/W | dmac_chctrl |
| 4 | 10 | R/W | dmac_chcfg |
| 5-7 | 14-1c | - | reserved |
| dmac_chsrc_ad |
|
|||
| R/W |
0x00000000 |
Address@app_dmac0_dmac_ch0 : 0x40081100 Address@app_dmac0_dmac_ch1 : 0x40081120 Address@app_dmac0_dmac_ch2 : 0x40081140 Address@app_dmac0_dmac_ch3 : 0x40081160 Address@app_dmac1_dmac_ch0 : 0x40082100 Address@app_dmac1_dmac_ch1 : 0x40082120 Address@app_dmac1_dmac_ch2 : 0x40082140 Address@app_dmac1_dmac_ch3 : 0x40082160 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
DMACCHSRCADDR |
|
|
| dmac_chdest_ad |
|
|||
| R/W |
0x00000000 |
Address@app_dmac0_dmac_ch0 : 0x40081104 Address@app_dmac0_dmac_ch1 : 0x40081124 Address@app_dmac0_dmac_ch2 : 0x40081144 Address@app_dmac0_dmac_ch3 : 0x40081164 Address@app_dmac1_dmac_ch0 : 0x40082104 Address@app_dmac1_dmac_ch1 : 0x40082124 Address@app_dmac1_dmac_ch2 : 0x40082144 Address@app_dmac1_dmac_ch3 : 0x40082164 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
DMACCHDESTADDR |
|
|
| dmac_chlink |
|
|||
| R/W |
0x00000000 |
Address@app_dmac0_dmac_ch0 : 0x40081108 Address@app_dmac0_dmac_ch1 : 0x40081128 Address@app_dmac0_dmac_ch2 : 0x40081148 Address@app_dmac0_dmac_ch3 : 0x40081168 Address@app_dmac1_dmac_ch0 : 0x40082108 Address@app_dmac1_dmac_ch1 : 0x40082128 Address@app_dmac1_dmac_ch2 : 0x40082148 Address@app_dmac1_dmac_ch3 : 0x40082168 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
LLIADDR |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| dmac_chctrl |
|
|||
| R/W |
0x00000000 |
Address@app_dmac0_dmac_ch0 : 0x4008110c Address@app_dmac0_dmac_ch1 : 0x4008112c Address@app_dmac0_dmac_ch2 : 0x4008114c Address@app_dmac0_dmac_ch3 : 0x4008116c Address@app_dmac1_dmac_ch0 : 0x4008210c Address@app_dmac1_dmac_ch1 : 0x4008212c Address@app_dmac1_dmac_ch2 : 0x4008214c Address@app_dmac1_dmac_ch3 : 0x4008216c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
I |
|
|
| 30 - 28 | "000" |
Prot |
|
|
| 27 | "0" |
DI |
|
|
| 26 | "0" |
SI |
|
|
| 25 | 0 |
- |
reserved | |
| 24 | "0" |
ARM_EQ |
|
|
| 23 - 21 | "000" |
DWidth |
|
|
| 20 - 18 | "000" |
SWidth |
|
|
| 17 - 15 | "000" |
DBSize |
|
|
| 14 - 12 | "000" |
SBSize |
|
|
| 11 - 0 | 0x0 |
TransferSize |
|
|
| dmac_chcfg |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@app_dmac0_dmac_ch0 : 0x40081110 Address@app_dmac0_dmac_ch1 : 0x40081130 Address@app_dmac0_dmac_ch2 : 0x40081150 Address@app_dmac0_dmac_ch3 : 0x40081170 Address@app_dmac1_dmac_ch0 : 0x40082110 Address@app_dmac1_dmac_ch1 : 0x40082130 Address@app_dmac1_dmac_ch2 : 0x40082150 Address@app_dmac1_dmac_ch3 : 0x40082170 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 18 | "0" |
H |
|
|||||||||||||||||||||||||||||||||||
| 17 | "0" |
A |
|
|||||||||||||||||||||||||||||||||||
| 16 | "0" |
L |
|
|||||||||||||||||||||||||||||||||||
| 15 | "0" |
ITC |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
IE |
|
|||||||||||||||||||||||||||||||||||
| 13 - 11 | "000" |
FlowCntrl |
|
|||||||||||||||||||||||||||||||||||
| 10 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 9 - 6 | "0000" |
DestPeripheral |
|
|||||||||||||||||||||||||||||||||||
| 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 4 - 1 | "0000" |
SrcPeripheral |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
E |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | dmac_int_status |
| 1 | 4 | R | dmac_inttc_status |
| 2 | 8 | W | dmac_inttc_clear |
| 3 | c | R | dmac_interr_status |
| 4 | 10 | W | dmac_interr_clear |
| 5 | 14 | R | dmac_rawinttc_status |
| 6 | 18 | R | dmac_rawinterr_status |
| 7 | 1c | R | dmac_enabled_channel |
| 8 | 20 | R/W | dmac_softb_req |
| 9 | 24 | R/W | dmac_softs_req |
| a | 28 | R/W | dmac_softlb_req |
| b | 2c | R/W | dmac_softls_req |
| c | 30 | R/W | dmac_config |
| d | 34 | R/W | dmac_sync |
| e-1ff | 38-7fc | - | reserved |
| dmac_int_status |
|
|||
| R |
Address@dmac_reg : 0x40081800 Address@app_dmac0_dmac_reg : 0x40081800 Address@app_dmac1_dmac_reg : 0x40082800 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACINT_ch3 |
|
||
| 2 | DMACINT_ch2 |
|
||
| 1 | DMACINT_ch1 |
|
||
| 0 | DMACINT_ch0 |
|
||
| dmac_inttc_status |
|
|||
| R |
Address@dmac_reg : 0x40081804 Address@app_dmac0_dmac_reg : 0x40081804 Address@app_dmac1_dmac_reg : 0x40082804 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACINTTC_ch3 |
|
||
| 2 | DMACINTTC_ch2 |
|
||
| 1 | DMACINTTC_ch1 |
|
||
| 0 | DMACINTTC_ch0 |
|
||
| dmac_inttc_clear |
|
|||
| W |
0x00000000 |
Address@dmac_reg : 0x40081808 Address@app_dmac0_dmac_reg : 0x40081808 Address@app_dmac1_dmac_reg : 0x40082808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
DMACINTTCCLR_ch3 |
|
|
| 2 | "0" |
DMACINTTCCLR_ch2 |
|
|
| 1 | "0" |
DMACINTTCCLR_ch1 |
|
|
| 0 | "0" |
DMACINTTCCLR_ch0 |
|
|
| dmac_interr_status |
|
|||
| R |
Address@dmac_reg : 0x4008180c Address@app_dmac0_dmac_reg : 0x4008180c Address@app_dmac1_dmac_reg : 0x4008280c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACINTERR_ch3 |
|
||
| 2 | DMACINTERR_ch2 |
|
||
| 1 | DMACINTERR_ch1 |
|
||
| 0 | DMACINTERR_ch0 |
|
||
| dmac_interr_clear |
|
|||
| W |
0x00000000 |
Address@dmac_reg : 0x40081810 Address@app_dmac0_dmac_reg : 0x40081810 Address@app_dmac1_dmac_reg : 0x40082810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
DMACINTERRCLR_ch3 |
|
|
| 2 | "0" |
DMACINTERRCLR_ch2 |
|
|
| 1 | "0" |
DMACINTERRCLR_ch1 |
|
|
| 0 | "0" |
DMACINTERRCLR_ch0 |
|
|
| dmac_rawinttc_status |
|
|||
| R |
Address@dmac_reg : 0x40081814 Address@app_dmac0_dmac_reg : 0x40081814 Address@app_dmac1_dmac_reg : 0x40082814 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACRAWINTTC_ch3 |
|
||
| 2 | DMACRAWINTTC_ch2 |
|
||
| 1 | DMACRAWINTTC_ch1 |
|
||
| 0 | DMACRAWINTTC_ch0 |
|
||
| dmac_rawinterr_status |
|
|||
| R |
Address@dmac_reg : 0x40081818 Address@app_dmac0_dmac_reg : 0x40081818 Address@app_dmac1_dmac_reg : 0x40082818 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACRAWINTERR_ch3 |
|
||
| 2 | DMACRAWINTERR_ch2 |
|
||
| 1 | DMACRAWINTERR_ch1 |
|
||
| 0 | DMACRAWINTERR_ch0 |
|
||
| dmac_enabled_channel |
|
|||
| R |
Address@dmac_reg : 0x4008181c Address@app_dmac0_dmac_reg : 0x4008181c Address@app_dmac1_dmac_reg : 0x4008281c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 | DMACENABLEDCHNS_ch3 |
|
||
| 2 | DMACENABLEDCHNS_ch2 |
|
||
| 1 | DMACENABLEDCHNS_ch1 |
|
||
| 0 | DMACENABLEDCHNS_ch0 |
|
||
| dmac_softb_req |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x40081820 Address@app_dmac0_dmac_reg : 0x40081820 Address@app_dmac1_dmac_reg : 0x40082820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
DMACSoftBReq |
|
|
| dmac_softs_req |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x40081824 Address@app_dmac0_dmac_reg : 0x40081824 Address@app_dmac1_dmac_reg : 0x40082824 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
DMACSoftSReq |
|
|
| dmac_softlb_req |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x40081828 Address@app_dmac0_dmac_reg : 0x40081828 Address@app_dmac1_dmac_reg : 0x40082828 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
DMACSoftLBReq |
|
|
| dmac_softls_req |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x4008182c Address@app_dmac0_dmac_reg : 0x4008182c Address@app_dmac1_dmac_reg : 0x4008282c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
DMACSoftLSReq |
|
|
| dmac_config |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x40081830 Address@app_dmac0_dmac_reg : 0x40081830 Address@app_dmac1_dmac_reg : 0x40082830 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
DMACENABLE |
|
|
| dmac_sync |
|
|||
| R/W |
0x00000000 |
Address@dmac_reg : 0x40081834 Address@app_dmac0_dmac_reg : 0x40081834 Address@app_dmac1_dmac_reg : 0x40082834 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
DIS_SYNC |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_gem_gxl_top_0_mbist_power0 |
| 1 | 4 | R/W | gen_ram_ctrl_gem_gxl_top_0_mbist_power1 |
| 2 | 8 | R/W | gen_ram_ctrl_gem_gxl_top_0_mbist_power2 |
| 3 | c | R/W | gen_ram_ctrl_gem_gxl_top_0_mbist_power3 |
| 4-1ff | 10-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_gem_gxl_top_0_ecc0 |
| 201-27f | 804-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_gem_gxl_top_0_ecc_status_corr0 |
| 281-2ff | a04-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_gem_gxl_top_0_ecc_status_noncorr0 |
| 301-37f | c04-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_gem_gxl_top_0_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_gem_gxl_top_0_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_gem_gxl_top_0_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_gem_gxl_top_0_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_gem_gxl_top_0_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x400c8000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gem_gxl_top_0_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x400c8004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gem_gxl_top_0_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x400c8008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gem_gxl_top_0_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x400c800c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_gem_gxl_top_0_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400c8800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_gem_gxl_top_0_ecc_status_corr0 |
|
|||
| R |
Address : 0x400c8a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gem_gxl_top_0_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x400c8c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400c8e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gem_gxl_top_0_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400c8e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gem_gxl_top_0_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x400c8e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_gem_gxl_top_0_irq_mask_rst_reg0 |
|
|||||||||||||||||
| R/W |
0x00000000 |
Address : 0x400c8ec0 |
Bits | Reset value | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||
| gen_ram_ctrl_gem_gxl_top_0_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x400c8efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_netx22xx_7_mbist_power0 |
| 1 | 4 | R/W | gen_ram_ctrl_netx22xx_7_mbist_power1 |
| 2 | 8 | R/W | gen_ram_ctrl_netx22xx_7_mbist_power2 |
| 3 | c | R/W | gen_ram_ctrl_netx22xx_7_mbist_power3 |
| 4-1ff | 10-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_netx22xx_7_ecc0 |
| 201-27f | 804-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_netx22xx_7_ecc_status_corr0 |
| 281-2ff | a04-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_netx22xx_7_ecc_status_noncorr0 |
| 301-37f | c04-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_netx22xx_7_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_netx22xx_7_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_netx22xx_7_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_netx22xx_7_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_netx22xx_7_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_netx22xx_7_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x48044000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_7_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x48044004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_7_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x48044008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_7_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x4804400c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_7_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x48044800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_7_ecc_status_corr0 |
|
|||
| R |
Address : 0x48044a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_7_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x48044c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_7_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x48044e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_7_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x48044e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_7_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x48044e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_7_irq_mask_rst_reg0 |
|
|||||||||||||||||
| R/W |
0x00000000 |
Address : 0x48044ec0 |
Bits | Reset value | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||
| 5 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||
| 4 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||
| 3 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||
| gen_ram_ctrl_netx22xx_7_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x48044efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_ctrl_cfg |
| 1 | 4 | R/W | mot_ctrl_singen_sync |
| 2 | 8 | R/W | mot_ctrl_sdmf0_sync |
| 3 | c | R/W | mot_ctrl_sdmf1_sync |
| 4 | 10 | R/W | mot_ctrl_sdmf2_sync |
| 5 | 14 | R/W | mot_ctrl_cpu0_boot_addr |
| 6 | 18 | R/W | mot_ctrl_cpu0_mtvec_addr |
| 7 | 1c | R/W | mot_ctrl_cpu0_dm_halt_addr |
| 8 | 20 | R/W | mot_ctrl_cpu0_dm_exception_addr |
| 9 | 24 | R/W | mot_ctrl_cpu1_boot_addr |
| a | 28 | R/W | mot_ctrl_cpu1_mtvec_addr |
| b | 2c | R/W | mot_ctrl_cpu1_dm_halt_addr |
| c | 30 | R/W | mot_ctrl_cpu1_dm_exception_addr |
| d | 34 | R/W | mot_ctrl_cpu_ctrl |
| e | 38 | R | mot_ctrl_cpu_status |
| f | 3c | - | reserved |
| mot_ctrl_cfg |
|
|||||||||||
| R/W |
0x00000001 |
Address : 0x49000000 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||
| 5 | "0" |
enc1_src |
|
|||||||||
| 4 | "0" |
enc0_src |
|
|||||||||
| 3 - 0 | "0001" |
eci_src |
|
|||||||||
| mot_ctrl_singen_sync |
|
|||||||||||||||||||||||
| R/W |
0x0001ffff |
Address : 0x49000004 |
Bits | Reset value | Name | Description | ||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |||||||||||||||||||||
| 16 - 0 | 0x1ffff |
src |
|
|||||||||||||||||||||
| mot_ctrl_sdmf0_sync |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x49000008 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |||||
| 16 - 0 | 0x1ffff |
src |
|
|||||
| mot_ctrl_sdmf1_sync |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x4900000c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |||||
| 16 - 0 | 0x1ffff |
src |
|
|||||
| mot_ctrl_sdmf2_sync |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x49000010 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | |||||
| 16 - 0 | 0x1ffff |
src |
|
|||||
| mot_ctrl_cpu0_boot_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0x0 |
val |
|
|
| 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu0_mtvec_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0x0 |
val |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu0_dm_halt_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x4900001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
val |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu0_dm_exception_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
val |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu1_boot_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0x0 |
val |
|
|
| 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu1_mtvec_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0x0 |
val |
|
|
| 7 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu1_dm_halt_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x4900002c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
val |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu1_dm_exception_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x49000030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
val |
|
|
| 1 - 0 | 0 |
- |
reserved | |
| mot_ctrl_cpu_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x49000034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
cpu1_enif |
|
|
| 2 | "0" |
cpu1_nres |
|
|
| 1 | "0" |
cpu0_enif |
|
|
| 0 | "0" |
cpu0_nres |
|
|
| mot_ctrl_cpu_status |
|
|||
| R |
Address : 0x49000038 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | cpu1_sleeping |
|
||
| 0 | cpu0_sleeping |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | singen_cfg |
| 1 | 4 | R/W | singen_demod_cfg |
| 2 | 8 | W | singen_cmd |
| 3 | c | R/W | singen_inc |
| 4 | 10 | R/W | singen_acc |
| 5 | 14 | R/W | singen_phase |
| 6 | 18 | R | singen_phase_acc_rs |
| 7 | 1c | R/W | singen_dac |
| singen_cfg | ||||
| R/W |
0x00000000 |
Address : 0x49000040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |
| 12 - 8 | "00000" |
sdm_div |
|
|
| 7 - 4 | "0000" |
ampli_coeff |
|
|
| 3 | "0" |
ampli_en |
|
|
| 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_en |
|
|
| 0 | "0" |
en |
|
|
| singen_demod_cfg | ||||
| R/W |
0x00000000 |
Address : 0x49000044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 15 | 0 |
- |
reserved | |
| 14 | "0" |
val |
||
| 13 - 7 | "0000000" |
phase_high |
||
| 6 - 0 | "0000000" |
phase_low |
|
|
| singen_cmd | ||||
| W |
0x00000000 |
Address : 0x49000048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
sync |
|
|
| singen_inc | ||||
| R/W |
0x00000000 |
Address : 0x4900004c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| singen_acc | ||||
| R/W |
0x00000000 |
Address : 0x49000050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| singen_phase | ||||
| R/W |
0x00000000 |
Address : 0x49000054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0 |
- |
reserved | |
| 6 - 0 | "0000000" |
val |
|
|
| singen_phase_acc_rs |
|
|||
| R |
Address : 0x49000058 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 7 | acc |
|
||
| 6 - 0 | phase |
|
||
| singen_dac | ||||
| R/W |
0x00000000 |
Address : 0x4900005c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
val |
|
|
| sdmf_cfg |
|
||||||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000100 Address@sdmf1 : 0x49000200 Address@sdmf2 : 0x49000300 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | ||||
| 28 - 24 | "00000" |
cic_shift |
|
||||
| 23 - 20 | "0000" |
cic_dr |
|
||||
| 19 - 17 | "000" |
cic_order |
|
||||
| 16 - 9 | "00000000" |
ssphase |
|
||||
| 8 | "0" |
rf_sel |
|
||||
| 7 - 0 | "00000000" |
sdm_clk_period |
|
||||
| sdmf_bq_cfg_0 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000104 Address@sdmf1 : 0x49000204 Address@sdmf2 : 0x49000304 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 12 | "000000" |
bq2 |
||
| 11 - 6 | "000000" |
bq1 |
||
| 5 - 0 | "000000" |
bq0 |
|
|
| sdmf_bq_cfg_1 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000108 Address@sdmf1 : 0x49000208 Address@sdmf2 : 0x49000308 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 12 | "000000" |
bq2 |
||
| 11 - 6 | "000000" |
bq1 |
||
| 5 - 0 | "000000" |
bq0 |
|
|
| sdmf_bq_cfg_2 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x4900010c Address@sdmf1 : 0x4900020c Address@sdmf2 : 0x4900030c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 12 | "000000" |
bq2 |
||
| 11 - 6 | "000000" |
bq1 |
||
| 5 - 0 | "000000" |
bq0 |
|
|
| sdmf_bq_cfg_3 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000110 Address@sdmf1 : 0x49000210 Address@sdmf2 : 0x49000310 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 12 | "000000" |
bq2 |
||
| 11 - 6 | "000000" |
bq1 |
||
| 5 - 0 | "000000" |
bq0 |
|
|
| sdmf_wc_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000114 Address@sdmf1 : 0x49000214 Address@sdmf2 : 0x49000314 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
eco_lt_3 |
||
| 18 | "0" |
eco_gt_3 |
||
| 17 | "0" |
winv_3 |
||
| 16 - 15 | "00" |
wsrc_3 |
||
| 14 | "0" |
eco_lt_2 |
||
| 13 | "0" |
eco_gt_2 |
||
| 12 | "0" |
winv_2 |
||
| 11 - 10 | "00" |
wsrc_2 |
||
| 9 | "0" |
eco_lt_1 |
||
| 8 | "0" |
eco_gt_1 |
||
| 7 | "0" |
winv_1 |
||
| 6 - 5 | "00" |
wsrc_1 |
||
| 4 | "0" |
eco_lt_0 |
|
|
| 3 | "0" |
eco_gt_0 |
|
|
| 2 | "0" |
winv_0 |
|
|
| 1 - 0 | "00" |
wsrc_0 |
|
|
| sdmf_wc_thr_0 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000118 Address@sdmf1 : 0x49000218 Address@sdmf2 : 0x49000318 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
ht |
|
|
| 15 - 0 | 0x0 |
lt |
|
|
| sdmf_wc_thr_1 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x4900011c Address@sdmf1 : 0x4900021c Address@sdmf2 : 0x4900031c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
ht |
|
|
| 15 - 0 | 0x0 |
lt |
|
|
| sdmf_wc_thr_2 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000120 Address@sdmf1 : 0x49000220 Address@sdmf2 : 0x49000320 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
ht |
|
|
| 15 - 0 | 0x0 |
lt |
|
|
| sdmf_wc_thr_3 |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000124 Address@sdmf1 : 0x49000224 Address@sdmf2 : 0x49000324 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
ht |
|
|
| 15 - 0 | 0x0 |
lt |
|
|
| sdmf_sr_cfg |
|
|||||||||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000128 Address@sdmf1 : 0x49000228 Address@sdmf2 : 0x49000328 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||
| 21 - 14 | "00000000" |
rskip |
|
|||||||
| 13 - 12 | "00" |
bq_init |
|
|||||||
| 11 - 7 | "00000" |
cic_skip |
|
|||||||
| 6 | "0" |
cic_init |
|
|||||||
| 5 | "0" |
r32 |
|
|||||||
| 4 - 2 | "000" |
sr_no |
|
|||||||
| 1 - 0 | "00" |
sr_src |
|
|||||||
| sdmf_dma_acc_lo |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x4900012c Address@sdmf1 : 0x4900022c Address@sdmf2 : 0x4900032c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0x0 |
val |
|
|
| 3 - 0 | 0 |
- |
reserved | |
| sdmf_dma_acc_hi |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000130 Address@sdmf1 : 0x49000230 Address@sdmf2 : 0x49000330 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0x0 |
val |
|
|
| 3 - 0 | 0 |
- |
reserved | |
| sdmf_s_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000134 Address@sdmf1 : 0x49000234 Address@sdmf2 : 0x49000334 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
sno |
|
|
| 15 - 0 | 0x0 |
soffset |
|
|
| sdmf_r_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000138 Address@sdmf1 : 0x49000238 Address@sdmf2 : 0x49000338 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
rno |
|
|
| 15 - 0 | 0x0 |
roffset |
|
|
| sdmf_sadr_ws |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x4900013c Address@sdmf1 : 0x4900023c Address@sdmf2 : 0x4900033c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
adr |
|
|
| 1 | 0 |
- |
reserved | |
| 0 | "0" |
sen |
|
|
| sdmf_radr_ws |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000140 Address@sdmf1 : 0x49000240 Address@sdmf2 : 0x49000340 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
adr |
|
|
| 1 | 0 |
- |
reserved | |
| 0 | "0" |
ren |
|
|
| sdmf_cmd | |||||||||
| W |
0x00000000 |
Address@sdmf0 : 0x49000144 Address@sdmf1 : 0x49000244 Address@sdmf2 : 0x49000344 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||
| 15 - 14 | "00" |
wc_3 |
|
||||||
| 13 - 12 | "00" |
wc_2 |
|
||||||
| 11 - 10 | "00" |
wc_1 |
|
||||||
| 9 - 8 | "00" |
wc_0 |
|
||||||
| 7 - 6 | "00" |
bq2 |
|
||||||
| 5 - 4 | "00" |
bq1 |
|
||||||
| 3 - 2 | "00" |
bq0 |
|
||||||
| 1 | "0" |
cic_clr |
|
||||||
| 0 | "0" |
sync |
|
||||||
| sdmf_en | |||||||
| R/W |
0x00000000 |
Address@sdmf0 : 0x49000148 Address@sdmf1 : 0x49000248 Address@sdmf2 : 0x49000348 |
Bits | Reset value | Name | Description | |
|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||
| 2 | "0" |
sr_en |
|
||||
| 1 | "0" |
cic_bq_en |
|
||||
| 0 | "0" |
sdm_clk_en |
|
||||
| sdmf_cic_0 | ||||
| R |
Address@sdmf0 : 0x4900014c Address@sdmf1 : 0x4900024c Address@sdmf2 : 0x4900034c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_cic_1 | ||||
| R |
Address@sdmf0 : 0x49000150 Address@sdmf1 : 0x49000250 Address@sdmf2 : 0x49000350 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_cic_2 | ||||
| R |
Address@sdmf0 : 0x49000154 Address@sdmf1 : 0x49000254 Address@sdmf2 : 0x49000354 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_cic_3 | ||||
| R |
Address@sdmf0 : 0x49000158 Address@sdmf1 : 0x49000258 Address@sdmf2 : 0x49000358 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq0_0 | ||||
| R |
Address@sdmf0 : 0x4900015c Address@sdmf1 : 0x4900025c Address@sdmf2 : 0x4900035c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq0_1 | ||||
| R |
Address@sdmf0 : 0x49000160 Address@sdmf1 : 0x49000260 Address@sdmf2 : 0x49000360 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq0_2 | ||||
| R |
Address@sdmf0 : 0x49000164 Address@sdmf1 : 0x49000264 Address@sdmf2 : 0x49000364 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq0_3 | ||||
| R |
Address@sdmf0 : 0x49000168 Address@sdmf1 : 0x49000268 Address@sdmf2 : 0x49000368 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq1_0 | ||||
| R |
Address@sdmf0 : 0x4900016c Address@sdmf1 : 0x4900026c Address@sdmf2 : 0x4900036c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq1_1 | ||||
| R |
Address@sdmf0 : 0x49000170 Address@sdmf1 : 0x49000270 Address@sdmf2 : 0x49000370 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq1_2 | ||||
| R |
Address@sdmf0 : 0x49000174 Address@sdmf1 : 0x49000274 Address@sdmf2 : 0x49000374 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq1_3 | ||||
| R |
Address@sdmf0 : 0x49000178 Address@sdmf1 : 0x49000278 Address@sdmf2 : 0x49000378 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq2_0 | ||||
| R |
Address@sdmf0 : 0x4900017c Address@sdmf1 : 0x4900027c Address@sdmf2 : 0x4900037c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq2_1 | ||||
| R |
Address@sdmf0 : 0x49000180 Address@sdmf1 : 0x49000280 Address@sdmf2 : 0x49000380 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq2_2 | ||||
| R |
Address@sdmf0 : 0x49000184 Address@sdmf1 : 0x49000284 Address@sdmf2 : 0x49000384 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_bq2_3 | ||||
| R |
Address@sdmf0 : 0x49000188 Address@sdmf1 : 0x49000288 Address@sdmf2 : 0x49000388 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_wc |
|
|||
| R |
Address@sdmf0 : 0x4900018c Address@sdmf1 : 0x4900028c Address@sdmf2 : 0x4900038c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 13 | - |
reserved | ||
| 12 | eco |
|||
| 11 | wc_3 |
|||
| 10 | lt_3 |
|||
| 9 | gt_3 |
|||
| 8 | wc_2 |
|||
| 7 | lt_2 |
|||
| 6 | gt_2 |
|||
| 5 | wc_1 |
|||
| 4 | lt_1 |
|||
| 3 | gt_1 |
|||
| 2 | wc_0 |
|
||
| 1 | lt_0 |
|
||
| 0 | gt_0 |
|
||
| sdmf_sadr | ||||
| R |
Address@sdmf0 : 0x49000190 Address@sdmf1 : 0x49000290 Address@sdmf2 : 0x49000390 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | adr |
|
||
| 1 | - |
reserved | ||
| 0 | sen |
|
||
| sdmf_radr | ||||
| R |
Address@sdmf0 : 0x49000194 Address@sdmf1 : 0x49000294 Address@sdmf2 : 0x49000394 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | adr |
|
||
| 1 | - |
reserved | ||
| 0 | ren |
|
||
| sdmf_dtime_now | ||||
| R |
Address@sdmf0 : 0x49000198 Address@sdmf1 : 0x49000298 Address@sdmf2 : 0x49000398 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_dtime | ||||
| R |
Address@sdmf0 : 0x4900019c Address@sdmf1 : 0x4900029c Address@sdmf2 : 0x4900039c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_sum_0 | ||||
| R |
Address@sdmf0 : 0x490001a0 Address@sdmf1 : 0x490002a0 Address@sdmf2 : 0x490003a0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_sum_1 | ||||
| R |
Address@sdmf0 : 0x490001a4 Address@sdmf1 : 0x490002a4 Address@sdmf2 : 0x490003a4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_sum_2 | ||||
| R |
Address@sdmf0 : 0x490001a8 Address@sdmf1 : 0x490002a8 Address@sdmf2 : 0x490003a8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_sum_3 | ||||
| R |
Address@sdmf0 : 0x490001ac Address@sdmf1 : 0x490002ac Address@sdmf2 : 0x490003ac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| sdmf_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001b0 Address@sdmf1 : 0x490002b0 Address@sdmf2 : 0x490003b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | - |
eco |
|
|
| 12 | - |
wc_3 |
|
|
| 11 | - |
wc_2 |
|
|
| 10 | - |
wc_1 |
|
|
| 9 | - |
wc_0 |
|
|
| 8 | "0" |
rdma_accviol_evt |
|
|
| 7 | "0" |
rdma_err_evt |
|
|
| 6 | "0" |
rdone_evt |
|
|
| 5 | "0" |
sdone_evt |
|
|
| 4 | "0" |
snew_evt |
|
|
| 3 | "0" |
fil_done_evt |
|
|
| 2 | - |
radr_ws_empty |
|
|
| 1 | - |
sadr_ws_empty |
|
|
| 0 | - |
sr_idle |
|
|
| sdmf_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001b4 Address@sdmf1 : 0x490002b4 Address@sdmf2 : 0x490003b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
eco |
|
|
| 12 | "0" |
wc_3 |
|
|
| 11 | "0" |
wc_2 |
|
|
| 10 | "0" |
wc_1 |
|
|
| 9 | "0" |
wc_0 |
|
|
| 8 | "0" |
rdma_accviol_evt |
|
|
| 7 | "0" |
rdma_err_evt |
|
|
| 6 | "0" |
rdone_evt |
|
|
| 5 | "0" |
sdone_evt |
|
|
| 4 | "0" |
snew_evt |
|
|
| 3 | "0" |
fil_done_evt |
|
|
| 2 | "0" |
radr_ws_empty |
|
|
| 1 | "0" |
sadr_ws_empty |
|
|
| 0 | "0" |
sr_idle |
|
|
| sdmf_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001b8 Address@sdmf1 : 0x490002b8 Address@sdmf2 : 0x490003b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |
| 13 | "0" |
eco |
|
|
| 12 | "0" |
wc_3 |
|
|
| 11 | "0" |
wc_2 |
|
|
| 10 | "0" |
wc_1 |
|
|
| 9 | "0" |
wc_0 |
|
|
| 8 | "0" |
rdma_accviol_evt |
|
|
| 7 | "0" |
rdma_err_evt |
|
|
| 6 | "0" |
rdone_evt |
|
|
| 5 | "0" |
sdone_evt |
|
|
| 4 | "0" |
snew_evt |
|
|
| 3 | "0" |
fil_done_evt |
|
|
| 2 | "0" |
radr_ws_empty |
|
|
| 1 | "0" |
sadr_ws_empty |
|
|
| 0 | "0" |
sr_idle |
|
|
| sdmf_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001bc Address@sdmf1 : 0x490002bc Address@sdmf2 : 0x490003bc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 14 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||
| 13 | "0" |
eco |
|
|||||||||||||||||||||||||||||||
| 12 | "0" |
wc_3 |
|
|||||||||||||||||||||||||||||||
| 11 | "0" |
wc_2 |
|
|||||||||||||||||||||||||||||||
| 10 | "0" |
wc_1 |
|
|||||||||||||||||||||||||||||||
| 9 | "0" |
wc_0 |
|
|||||||||||||||||||||||||||||||
| 8 | "0" |
rdma_accviol_evt |
|
|||||||||||||||||||||||||||||||
| 7 | "0" |
rdma_err_evt |
|
|||||||||||||||||||||||||||||||
| 6 | "0" |
rdone_evt |
|
|||||||||||||||||||||||||||||||
| 5 | "0" |
sdone_evt |
|
|||||||||||||||||||||||||||||||
| 4 | "0" |
snew_evt |
|
|||||||||||||||||||||||||||||||
| 3 | "0" |
fil_done_evt |
|
|||||||||||||||||||||||||||||||
| 2 | "0" |
radr_ws_empty |
|
|||||||||||||||||||||||||||||||
| 1 | "0" |
sadr_ws_empty |
|
|||||||||||||||||||||||||||||||
| 0 | "0" |
sr_idle |
|
|||||||||||||||||||||||||||||||
| sdmf_ch_bq_sel |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001c0 Address@sdmf1 : 0x490002c0 Address@sdmf2 : 0x490003c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0x0 |
guard |
|
|
| 1 - 0 | "00" |
sel |
|
|
| sdmf_bq0_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001c4 Address@sdmf1 : 0x490002c4 Address@sdmf2 : 0x490003c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 25 | "00000" |
init_exp |
|
|
| 24 - 20 | "00000" |
init_mant |
|
|
| 19 - 15 | "00000" |
c2_exp |
|
|
| 14 - 10 | "00000" |
c2_mant |
|
|
| 9 - 5 | "00000" |
c1_exp |
|
|
| 4 - 0 | "00000" |
c1_mant |
|
|
| sdmf_bq1_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001c8 Address@sdmf1 : 0x490002c8 Address@sdmf2 : 0x490003c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 25 | "00000" |
init_exp |
|
|
| 24 - 20 | "00000" |
init_mant |
|
|
| 19 - 15 | "00000" |
c2_exp |
|
|
| 14 - 10 | "00000" |
c2_mant |
|
|
| 9 - 5 | "00000" |
c1_exp |
|
|
| 4 - 0 | "00000" |
c1_mant |
|
|
| sdmf_bq2_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001cc Address@sdmf1 : 0x490002cc Address@sdmf2 : 0x490003cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 25 | "00000" |
init_exp |
|
|
| 24 - 20 | "00000" |
init_mant |
|
|
| 19 - 15 | "00000" |
c2_exp |
|
|
| 14 - 10 | "00000" |
c2_mant |
|
|
| 9 - 5 | "00000" |
c1_exp |
|
|
| 4 - 0 | "00000" |
c1_mant |
|
|
| sdmf_bq0_gain_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001d0 Address@sdmf1 : 0x490002d0 Address@sdmf2 : 0x490003d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "00000" |
out_scale |
||
| sdmf_bq1_gain_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001d4 Address@sdmf1 : 0x490002d4 Address@sdmf2 : 0x490003d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "00000" |
out_scale |
||
| sdmf_bq2_gain_cfg |
|
|||
| R/W |
0x00000000 |
Address@sdmf0 : 0x490001d8 Address@sdmf1 : 0x490002d8 Address@sdmf2 : 0x490003d8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "00000" |
out_scale |
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mpwm_cfg |
| 1 | 4 | R/W | mpwm_cnt_max |
| 2 | 8 | R/W | mpwm_cnt_ps_max |
| 3 | c | R/W | mpwm_dt |
| 4 | 10 | R/W | mpwm_ocfg |
| 5 | 14 | R/W | mpwm_cnt_max_s |
| 6 | 18 | R/W | mpwm_dt_s |
| 7 | 1c | R | mpwm_status |
| 8 | 20 | W | mpwm_cmd |
| 9 | 24 | R | mpwm_cnt |
| a | 28 | R | mpwm_ecnt |
| b | 2c | R | mpwm_cnt_rs |
| c | 30 | R | mpwm_cnt_ps |
| d | 34 | R | mpwm_evt_cnt |
| e | 38 | R/W | mpwm_bc_s |
| f | 3c | R/W | mpwm_bc |
| 10-3f | 40-fc | - | reserved |
| 40 | 100 | R/W | mpwm_ch0_cmp0_s |
| 41 | 104 | R/W | mpwm_ch0_cmp1_s |
| 42 | 108 | R/W | mpwm_ch0_cmp0 |
| 43 | 10c | R/W | mpwm_ch0_cmp1 |
| 44 | 110 | R/W | mpwm_ch0_muxin_s |
| 45 | 114 | R/W | mpwm_ch0_muxin |
| 46-47 | 118-11c | - | reserved |
| 48 | 120 | R/W | mpwm_ch1_cmp0_s |
| 49 | 124 | R/W | mpwm_ch1_cmp1_s |
| 4a | 128 | R/W | mpwm_ch1_cmp0 |
| 4b | 12c | R/W | mpwm_ch1_cmp1 |
| 4c | 130 | R/W | mpwm_ch1_muxin_s |
| 4d | 134 | R/W | mpwm_ch1_muxin |
| 4e-4f | 138-13c | - | reserved |
| 50 | 140 | R/W | mpwm_ch2_cmp0_s |
| 51 | 144 | R/W | mpwm_ch2_cmp1_s |
| 52 | 148 | R/W | mpwm_ch2_cmp0 |
| 53 | 14c | R/W | mpwm_ch2_cmp1 |
| 54 | 150 | R/W | mpwm_ch2_muxin_s |
| 55 | 154 | R/W | mpwm_ch2_muxin |
| 56-57 | 158-15c | - | reserved |
| 58 | 160 | R/W | mpwm_ch3_cmp0_s |
| 59 | 164 | R/W | mpwm_ch3_cmp1_s |
| 5a | 168 | R/W | mpwm_ch3_cmp0 |
| 5b | 16c | R/W | mpwm_ch3_cmp1 |
| 5c | 170 | R/W | mpwm_ch3_muxin_s |
| 5d | 174 | R/W | mpwm_ch3_muxin |
| 5e-5f | 178-17c | - | reserved |
| 60 | 180 | R/W | mpwm_ch4_cmp0_s |
| 61 | 184 | R/W | mpwm_ch4_cmp1_s |
| 62 | 188 | R/W | mpwm_ch4_cmp0 |
| 63 | 18c | R/W | mpwm_ch4_cmp1 |
| 64 | 190 | R/W | mpwm_ch4_muxin_s |
| 65 | 194 | R/W | mpwm_ch4_muxin |
| 66-67 | 198-19c | - | reserved |
| 68 | 1a0 | R/W | mpwm_ch5_cmp0_s |
| 69 | 1a4 | R/W | mpwm_ch5_cmp1_s |
| 6a | 1a8 | R/W | mpwm_ch5_cmp0 |
| 6b | 1ac | R/W | mpwm_ch5_cmp1 |
| 6c | 1b0 | R/W | mpwm_ch5_muxin_s |
| 6d | 1b4 | R/W | mpwm_ch5_muxin |
| 6e-6f | 1b8-1bc | - | reserved |
| 70 | 1c0 | R/W | mpwm_irq_raw |
| 71 | 1c4 | R | mpwm_irq_masked |
| 72 | 1c8 | R/W | mpwm_irq_msk_set |
| 73 | 1cc | R/W | mpwm_irq_msk_reset |
| 74 | 1d0 | R | mpwm_irq_no |
| 75-7f | 1d4-1fc | - | reserved |
| mpwm_cfg |
|
|||||||||||
| R/W |
0x00000800 |
Address : 0x49000400 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||
| 23 - 16 | "00000000" |
eci_fil_thresh |
|
|||||||||
| 15 - 11 | "00001" |
evt_cnt_top |
|
|||||||||
| 10 | "0" |
sce_src_mop |
|
|||||||||
| 9 | "0" |
sce_src_bop |
|
|||||||||
| 8 | "0" |
sce_src_ecz |
|
|||||||||
| 7 | "0" |
eci_ks_en |
|
|||||||||
| 6 | "0" |
eci_gate_en |
|
|||||||||
| 5 | "0" |
eci_inv |
|
|||||||||
| 4 | "0" |
sync_in_pol |
|
|||||||||
| 3 | "0" |
sync_in_restart |
|
|||||||||
| 2 | "0" |
cnt_en_rs |
|
|||||||||
| 1 - 0 | "00" |
cnt_mode |
|
|||||||||
| mpwm_cnt_max |
|
|||
| R/W |
0x00000000 |
Address : 0x49000404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_cnt_ps_max |
|
|||
| R/W |
0x00000000 |
Address : 0x49000408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
val |
|
|
| mpwm_dt |
|
|||
| R/W |
0x00000000 |
Address : 0x4900040c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
fall_val |
|
|
| 7 - 0 | "00000000" |
rise_val |
|
|
| mpwm_ocfg |
|
|||||||
| R/W |
0x00000000 |
Address : 0x49000410 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 | 0 |
- |
reserved | |||||
| 30 | "0" |
oedpol5 |
|
|||||
| 29 | "0" |
oedpol4 |
|
|||||
| 28 | "0" |
oedpol3 |
|
|||||
| 27 | "0" |
oedpol2 |
|
|||||
| 26 | "0" |
oedpol1 |
|
|||||
| 25 | "0" |
oedpol0 |
|
|||||
| 24 | "0" |
oeden5 |
|
|||||
| 23 | "0" |
oeden4 |
|
|||||
| 22 | "0" |
oeden3 |
|
|||||
| 21 | "0" |
oeden2 |
|
|||||
| 20 | "0" |
oeden1 |
|
|||||
| 19 | "0" |
oeden0 |
|
|||||
| 18 | "0" |
oinv5 |
|
|||||
| 17 | "0" |
oinv4 |
|
|||||
| 16 | "0" |
oinv3 |
|
|||||
| 15 | "0" |
oinv2 |
|
|||||
| 14 | "0" |
oinv1 |
|
|||||
| 13 | "0" |
oinv0 |
|
|||||
| 12 | "0" |
oe5 |
|
|||||
| 11 | "0" |
oe4 |
|
|||||
| 10 | "0" |
oe3 |
|
|||||
| 9 | "0" |
oe2 |
|
|||||
| 8 | "0" |
oe1 |
|
|||||
| 7 | "0" |
oe0 |
|
|||||
| 6 | 0 |
- |
reserved | |||||
| 5 | "0" |
osel5 |
|
|||||
| 4 | "0" |
osel4 |
|
|||||
| 3 | "0" |
osel3 |
|
|||||
| 2 | "0" |
osel2 |
|
|||||
| 1 | "0" |
osel1 |
|
|||||
| 0 | "0" |
osel0 |
|
|||||
| mpwm_cnt_max_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_dt_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 8 | "00000000" |
fall_val |
|
|
| 7 - 0 | "00000000" |
rise_val |
|
|
| mpwm_status |
|
|||||||
| R |
Address : 0x4900041c |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||||||
| 3 | cnt_half |
|
||||||
| 2 | cnt_updown |
|
||||||
| 1 | eci_val_unfil |
|
||||||
| 0 | running |
|
||||||
| mpwm_cmd |
|
|||
| W |
0x00000000 |
Address : 0x49000420 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
eci_ks_rst |
|
|
| 4 | "0" |
evt_cnt_rst |
|
|
| 3 | "0" |
sce_emit |
|
|
| 2 | "0" |
restart |
|
|
| 1 | "0" |
stop |
|
|
| 0 | "0" |
start |
|
|
| mpwm_cnt |
|
|||
| R |
Address : 0x49000424 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| mpwm_ecnt |
|
|||
| R |
Address : 0x49000428 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | val |
|
||
| mpwm_cnt_rs |
|
|||
| R |
Address : 0x4900042c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | - |
reserved | ||
| 23 - 16 | ps_val |
|
||
| 15 - 0 | cnt_val |
|
||
| mpwm_cnt_ps |
|
|||
| R |
Address : 0x49000430 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | val |
|
||
| mpwm_evt_cnt |
|
|||
| R |
Address : 0x49000434 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 5 | - |
reserved | ||
| 4 - 0 | val |
|
||
| mpwm_bc_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000438 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
val |
|
|
| mpwm_bc |
|
|||
| R/W |
0x00000000 |
Address : 0x4900043c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
val |
|
|
| mpwm_ch0_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch0_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch0_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x49000508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch0_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4900050c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch0_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000510 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch0_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x49000514 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch1_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch1_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000524 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch1_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x49000528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch1_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4900052c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch1_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000530 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch1_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x49000534 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch2_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000540 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch2_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000544 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch2_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x49000548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch2_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4900054c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch2_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch2_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x49000554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch3_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000560 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch3_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000564 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch3_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x49000568 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch3_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4900056c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch3_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000570 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch3_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x49000574 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch4_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000580 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch4_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch4_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x49000588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch4_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x4900058c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch4_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x49000590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch4_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x49000594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch5_cmp0_s |
|
|||
| R/W |
0x00000000 |
Address : 0x490005a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch5_cmp1_s |
|
|||
| R/W |
0x00000000 |
Address : 0x490005a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch5_cmp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x490005a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch5_cmp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x490005ac |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
val |
|
|
| mpwm_ch5_muxin_s |
|
|||
| R/W |
0x00000000 |
Address : 0x490005b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_ch5_muxin |
|
|||
| R/W |
0x00000000 |
Address : 0x490005b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
ab |
|
|
| 1 | "0" |
bt |
|
|
| 0 | "0" |
bl |
|
|
| mpwm_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x490005c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 5 | "000000" |
oede |
|
|
| 4 | - |
eci_ks_state |
|
|
| 3 | - |
eci_val |
|
|
| 2 | "0" |
mop |
|
|
| 1 | "0" |
bop |
|
|
| 0 | "0" |
ecz |
|
|
| mpwm_irq_masked |
|
|||
| R |
Address : 0x490005c4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 11 | - |
reserved | ||
| 10 - 5 | oede |
|
||
| 4 | eci_ks_state |
|
||
| 3 | eci_val |
|
||
| 2 | mop |
|
||
| 1 | bop |
|
||
| 0 | ecz |
|
||
| mpwm_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address : 0x490005c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 5 | "000000" |
oede |
|
|
| 4 | "0" |
eci_ks_state |
|
|
| 3 | "0" |
eci_val |
|
|
| 2 | "0" |
mop |
|
|
| 1 | "0" |
bop |
|
|
| 0 | "0" |
ecz |
|
|
| mpwm_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address : 0x490005cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 5 | "000000" |
oede |
|
|
| 4 | "0" |
eci_ks_state |
|
|
| 3 | "0" |
eci_val |
|
|
| 2 | "0" |
mop |
|
|
| 1 | "0" |
bop |
|
|
| 0 | "0" |
ecz |
|
|
| mpwm_irq_no |
|
|||
| R |
Address : 0x490005d0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||
| 3 - 0 | val |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | menc_config |
| 1 | 4 | R/W | menc_enc0_position |
| 2 | 8 | R/W | menc_enc1_position |
| 3 | c | R/W | menc_capture_now |
| 4 | 10 | R/W | menc_capture0_config |
| 5 | 14 | R | menc_capture0_val |
| 6 | 18 | R | menc_capture0_ta |
| 7 | 1c | R | menc_capture0_te |
| 8 | 20 | R/W | menc_capture1_config |
| 9 | 24 | R | menc_capture1_val |
| a | 28 | R | menc_capture1_ta |
| b | 2c | R | menc_capture1_te |
| c | 30 | R/W | menc_capture2_config |
| d | 34 | R | menc_capture2_val |
| e | 38 | R | menc_capture2_ta |
| f | 3c | R | menc_capture2_te |
| 10 | 40 | R/W | menc_capture3_config |
| 11 | 44 | R | menc_capture3_val |
| 12 | 48 | R | menc_capture3_ta |
| 13 | 4c | R | menc_capture3_te |
| 14 | 50 | R/W | menc_status |
| 15 | 54 | R | menc_irq_masked |
| 16 | 58 | R/W | menc_irq_msk_set |
| 17 | 5c | R/W | menc_irq_msk_reset |
| 18-1f | 60-7c | - | reserved |
| menc_config |
|
|||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x49000600 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |||||||||||||||||
| 27 - 25 | "000" |
mp1_filter_sample_rate |
|
|||||||||||||||||
| 24 | "0" |
mp1_en |
|
|||||||||||||||||
| 23 - 20 | 0 |
- |
reserved | |||||||||||||||||
| 19 - 17 | "000" |
mp0_filter_sample_rate |
|
|||||||||||||||||
| 16 | "0" |
mp0_en |
|
|||||||||||||||||
| 15 - 13 | 0 |
- |
reserved | |||||||||||||||||
| 12 | "0" |
enc1_count_dir |
|
|||||||||||||||||
| 11 - 9 | "000" |
enc1_filter_sample_rate |
|
|||||||||||||||||
| 8 | "0" |
enc1_en |
|
|||||||||||||||||
| 7 - 5 | 0 |
- |
reserved | |||||||||||||||||
| 4 | "0" |
enc0_count_dir |
|
|||||||||||||||||
| 3 - 1 | "000" |
enc0_filter_sample_rate |
|
|||||||||||||||||
| 0 | "0" |
enc0_en |
|
|||||||||||||||||
| menc_enc0_position |
|
|||
| R/W |
0x00000000 |
Address : 0x49000604 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| menc_enc1_position |
|
|||
| R/W |
0x00000000 |
Address : 0x49000608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| menc_capture_now |
|
|||
| R/W |
0x00000000 |
Address : 0x4900060c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
cap3_now |
|
|
| 2 | "0" |
cap2_now |
|
|
| 1 | "0" |
cap1_now |
|
|
| 0 | "0" |
cap0_now |
|
|
| menc_capture0_config |
|
|||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x0001ffff |
Address : 0x49000610 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
conce |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
src_nr |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 19 - 17 | "000" |
src |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 16 - 0 | 0x1ffff |
trigger |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| menc_capture0_val |
|
|||
| R |
Address : 0x49000614 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| menc_capture0_ta |
|
|||
| R |
Address : 0x49000618 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture0_te |
|
|||
| R |
Address : 0x4900061c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture1_config |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x49000620 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||
| 21 | "0" |
conce |
|
|||||
| 20 | "0" |
src_nr |
|
|||||
| 19 - 17 | "000" |
src |
|
|||||
| 16 - 0 | 0x1ffff |
trigger |
|
|||||
| menc_capture1_val |
|
|||
| R |
Address : 0x49000624 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| menc_capture1_ta |
|
|||
| R |
Address : 0x49000628 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture1_te |
|
|||
| R |
Address : 0x4900062c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture2_config |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x49000630 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||
| 21 | "0" |
conce |
|
|||||
| 20 | "0" |
src_nr |
|
|||||
| 19 - 17 | "000" |
src |
|
|||||
| 16 - 0 | 0x1ffff |
trigger |
|
|||||
| menc_capture2_val |
|
|||
| R |
Address : 0x49000634 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| menc_capture2_ta |
|
|||
| R |
Address : 0x49000638 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture2_te |
|
|||
| R |
Address : 0x4900063c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture3_config |
|
|||||||
| R/W |
0x0001ffff |
Address : 0x49000640 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||
| 21 | "0" |
conce |
|
|||||
| 20 | "0" |
src_nr |
|
|||||
| 19 - 17 | "000" |
src |
|
|||||
| 16 - 0 | 0x1ffff |
trigger |
|
|||||
| menc_capture3_val |
|
|||
| R |
Address : 0x49000644 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| menc_capture3_ta |
|
|||
| R |
Address : 0x49000648 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_capture3_te |
|
|||
| R |
Address : 0x4900064c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | val |
|
||
| menc_status |
|
|||
| R/W |
0x00000000 |
Address : 0x49000650 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
mp1 |
|
|
| 24 | "0" |
mp0 |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
cap3 |
|
|
| 18 | "0" |
cap2 |
|
|
| 17 | "0" |
cap1 |
|
|
| 16 | "0" |
cap0 |
|
|
| 15 | - |
enc1_dir_ro |
|
|
| 14 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
enc1_n |
|
|
| 11 | "0" |
enc1_phase_error |
|
|
| 10 | "0" |
enc1_ovfl_neg |
|
|
| 9 | "0" |
enc1_ovfl_pos |
|
|
| 8 | "0" |
enc1_edge |
|
|
| 7 | - |
enc0_dir_ro |
|
|
| 6 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
enc0_n |
|
|
| 3 | "0" |
enc0_phase_error |
|
|
| 2 | "0" |
enc0_ovfl_neg |
|
|
| 1 | "0" |
enc0_ovfl_pos |
|
|
| 0 | "0" |
enc0_edge |
|
|
| menc_irq_masked |
|
|||
| R |
Address : 0x49000654 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 26 | - |
reserved | ||
| 25 | mp1 |
|
||
| 24 | mp0 |
|
||
| 23 - 20 | - |
reserved | ||
| 19 | cap3 |
|
||
| 18 | cap2 |
|
||
| 17 | cap1 |
|
||
| 16 | cap0 |
|
||
| 15 - 13 | - |
reserved | ||
| 12 | enc1_n |
|
||
| 11 | enc1_phase_error |
|
||
| 10 | enc1_ovfl_neg |
|
||
| 9 | enc1_ovfl_pos |
|
||
| 8 | enc1_edge |
|
||
| 7 - 5 | - |
reserved | ||
| 4 | enc0_n |
|
||
| 3 | enc0_phase_error |
|
||
| 2 | enc0_ovfl_neg |
|
||
| 1 | enc0_ovfl_pos |
|
||
| 0 | enc0_edge |
|
||
| menc_irq_msk_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49000658 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
mp1 |
|
|
| 24 | "0" |
mp0 |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
cap3 |
|
|
| 18 | "0" |
cap2 |
|
|
| 17 | "0" |
cap1 |
|
|
| 16 | "0" |
cap0 |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
enc1_n |
|
|
| 11 | "0" |
enc1_phase_error |
|
|
| 10 | "0" |
enc1_ovfl_neg |
|
|
| 9 | "0" |
enc1_ovfl_pos |
|
|
| 8 | "0" |
enc1_edge |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
enc0_n |
|
|
| 3 | "0" |
enc0_phase_error |
|
|
| 2 | "0" |
enc0_ovfl_neg |
|
|
| 1 | "0" |
enc0_ovfl_pos |
|
|
| 0 | "0" |
enc0_edge |
|
|
| menc_irq_msk_reset |
|
|||
| R/W |
0x00000000 |
Address : 0x4900065c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | |
| 25 | "0" |
mp1 |
|
|
| 24 | "0" |
mp0 |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 | "0" |
cap3 |
|
|
| 18 | "0" |
cap2 |
|
|
| 17 | "0" |
cap1 |
|
|
| 16 | "0" |
cap0 |
|
|
| 15 - 13 | 0 |
- |
reserved | |
| 12 | "0" |
enc1_n |
|
|
| 11 | "0" |
enc1_phase_error |
|
|
| 10 | "0" |
enc1_ovfl_neg |
|
|
| 9 | "0" |
enc1_ovfl_pos |
|
|
| 8 | "0" |
enc1_edge |
|
|
| 7 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
enc0_n |
|
|
| 3 | "0" |
enc0_phase_error |
|
|
| 2 | "0" |
enc0_ovfl_neg |
|
|
| 1 | "0" |
enc0_ovfl_pos |
|
|
| 0 | "0" |
enc0_edge |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | madc_cfg |
| 1 | 4 | R/W | madc_adc0_static_cfg |
| 2 | 8 | R/W | madc_adc1_static_cfg |
| 3 | c | R/W | madc_adc2_static_cfg |
| 4 | 10 | R/W | madc_adc3_static_cfg |
| 5 | 14 | R/W | madc_start |
| 6 | 18 | R/W | madc_deadtime01_delay |
| 7 | 1c | R/W | madc_deadtime23_delay |
| 8 | 20 | R/W | madc_deadtime45_delay |
| 9 | 24 | R/W | madc_cal_vref_config |
| a | 28 | R/W | madc_cal_iref_config |
| b-f | 2c-3c | - | reserved |
| madc_cfg |
|
|||
| R/W |
0x00000002 |
Address : 0x49000680 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000010" |
adcclk_period |
|
|
| madc_adc0_static_cfg |
|
||||||||
| R/W |
0x000006f0 |
Address : 0x49000684 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||
| 11 - 9 | "011" |
ibtune_cmp |
|
||||||
| 8 - 6 | "011" |
ibtune_ref |
|
||||||
| 5 - 4 | "11" |
bw_tune |
|
||||||
| 3 | "0" |
inv_clko |
|
||||||
| 2 | "0" |
buffer_enable |
|
||||||
| 1 | "0" |
reset_n |
|
||||||
| 0 | "0" |
enable |
|
||||||
| madc_adc1_static_cfg |
|
||||||||
| R/W |
0x000006f0 |
Address : 0x49000688 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||
| 11 - 9 | "011" |
ibtune_cmp |
|
||||||
| 8 - 6 | "011" |
ibtune_ref |
|
||||||
| 5 - 4 | "11" |
bw_tune |
|
||||||
| 3 | "0" |
inv_clko |
|
||||||
| 2 | "0" |
buffer_enable |
|
||||||
| 1 | "0" |
reset_n |
|
||||||
| 0 | "0" |
enable |
|
||||||
| madc_adc2_static_cfg |
|
||||||||
| R/W |
0x000006f0 |
Address : 0x4900068c |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||
| 11 - 9 | "011" |
ibtune_cmp |
|
||||||
| 8 - 6 | "011" |
ibtune_ref |
|
||||||
| 5 - 4 | "11" |
bw_tune |
|
||||||
| 3 | "0" |
inv_clko |
|
||||||
| 2 | "0" |
buffer_enable |
|
||||||
| 1 | "0" |
reset_n |
|
||||||
| 0 | "0" |
enable |
|
||||||
| madc_adc3_static_cfg |
|
||||||||
| R/W |
0x000006f0 |
Address : 0x49000690 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | 0 |
- |
reserved | ||||||
| 11 - 9 | "011" |
ibtune_cmp |
|
||||||
| 8 - 6 | "011" |
ibtune_ref |
|
||||||
| 5 - 4 | "11" |
bw_tune |
|
||||||
| 3 | "0" |
inv_clko |
|
||||||
| 2 | "0" |
buffer_enable |
|
||||||
| 1 | "0" |
reset_n |
|
||||||
| 0 | "0" |
enable |
|
||||||
| madc_start |
|
|||
| R/W |
0x00000000 |
Address : 0x49000694 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
start_adc3 |
|
|
| 2 | "0" |
start_adc2 |
|
|
| 1 | "0" |
start_adc1 |
|
|
| 0 | "0" |
start_adc0 |
|
|
| madc_deadtime01_delay |
|
|||
| R/W |
0x000a000a |
Address : 0x49000698 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xa |
dt1 |
|
|
| 15 - 0 | 0xa |
dt0 |
|
|
| madc_deadtime23_delay |
|
|||
| R/W |
0x000a000a |
Address : 0x4900069c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xa |
dt3 |
|
|
| 15 - 0 | 0xa |
dt2 |
|
|
| madc_deadtime45_delay |
|
|||
| R/W |
0x000a000a |
Address : 0x490006a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xa |
dt5 |
|
|
| 15 - 0 | 0xa |
dt4 |
|
|
| madc_cal_vref_config |
|
|||
| R/W |
0x80808080 |
Address : 0x490006a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "10000000" |
dual_adc1_cal_vref_tc |
||
| 23 - 16 | "10000000" |
dual_adc1_cal_vref |
||
| 15 - 8 | "10000000" |
dual_adc0_cal_vref_tc |
||
| 7 - 0 | "10000000" |
dual_adc0_cal_vref |
||
| madc_cal_iref_config |
|
|||
| R/W |
0x00000210 |
Address : 0x490006a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 - 5 | "010000" |
dual_adc1_cal_iref |
||
| 4 - 0 | "10000" |
dual_adc0_cal_iref |
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | madc_seq_cfg |
| 1 | 4 | R/W | madc_seq_tracking_time_mux0 |
| 2 | 8 | R/W | madc_seq_tracking_time_mux1 |
| 3 | c | R/W | madc_seq_tracking_time_mux2 |
| 4 | 10 | R/W | madc_seq_tracking_time_mux3 |
| 5 | 14 | R/W | madc_seq_tracking_time_mux4 |
| 6 | 18 | R/W | madc_seq_tracking_time_mux5 |
| 7 | 1c | R/W | madc_seq_tracking_time_mux6 |
| 8 | 20 | R/W | madc_seq_tracking_time_mux7 |
| 9 | 24 | R/W | madc_seq_ms_en |
| a | 28 | R/W | madc_seq_ms_baseadr |
| b | 2c | R/W | madc_seq_m0 |
| c | 30 | R/W | madc_seq_m1 |
| d | 34 | R/W | madc_seq_m2 |
| e | 38 | R/W | madc_seq_m3 |
| f | 3c | R/W | madc_seq_m4 |
| 10 | 40 | R/W | madc_seq_m5 |
| 11 | 44 | R/W | madc_seq_m6 |
| 12 | 48 | R/W | madc_seq_m7 |
| 13 | 4c | R/W | madc_seq_cmd |
| 14 | 50 | R | madc_seq_status |
| 15 | 54 | R | madc_seq_result_current |
| 16 | 58 | R | madc_seq_result_last |
| 17 | 5c | R/W | madc_seq_debug |
| 18-1b | 60-6c | - | reserved |
| 1c | 70 | R/W | madc_seq_irq_raw |
| 1d | 74 | R | madc_seq_irq_masked |
| 1e | 78 | R/W | madc_seq_irq_mask_set |
| 1f | 7c | R/W | madc_seq_irq_mask_reset |
| 20-3f | 80-fc | - | reserved |
| madc_seq_cfg |
|
|||||||
| R/W |
0x0000ff01 |
Address@madc_seq0 : 0x49000700 Address@madc_seq1 : 0x49000800 Address@madc_seq2 : 0x49000900 Address@madc_seq3 : 0x49000a00 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 23 | 0 |
- |
reserved | |||||
| 22 - 20 | "000" |
adc_mode |
|
|||||
| 19 | "0" |
dma_disable |
|
|||||
| 18 | "0" |
dma_32bit_adr |
|
|||||
| 17 | "0" |
reseved |
||||||
| 16 | "0" |
adcclk_sync |
|
|||||
| 15 - 8 | "11111111" |
adcclk_phase |
|
|||||
| 7 - 0 | "00000001" |
adcclk_period |
|
|||||
| madc_seq_tracking_time_mux0 |
|
||||||||||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000704 Address@madc_seq1 : 0x49000804 Address@madc_seq2 : 0x49000904 Address@madc_seq3 : 0x49000a04 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | ||||||||
| 7 - 0 | "00000100" |
tt_add |
|
||||||||
| madc_seq_tracking_time_mux1 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000708 Address@madc_seq1 : 0x49000808 Address@madc_seq2 : 0x49000908 Address@madc_seq3 : 0x49000a08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux2 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x4900070c Address@madc_seq1 : 0x4900080c Address@madc_seq2 : 0x4900090c Address@madc_seq3 : 0x49000a0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux3 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000710 Address@madc_seq1 : 0x49000810 Address@madc_seq2 : 0x49000910 Address@madc_seq3 : 0x49000a10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux4 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000714 Address@madc_seq1 : 0x49000814 Address@madc_seq2 : 0x49000914 Address@madc_seq3 : 0x49000a14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux5 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000718 Address@madc_seq1 : 0x49000818 Address@madc_seq2 : 0x49000918 Address@madc_seq3 : 0x49000a18 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux6 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x4900071c Address@madc_seq1 : 0x4900081c Address@madc_seq2 : 0x4900091c Address@madc_seq3 : 0x49000a1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_tracking_time_mux7 |
|
|||
| R/W |
0x00000004 |
Address@madc_seq0 : 0x49000720 Address@madc_seq1 : 0x49000820 Address@madc_seq2 : 0x49000920 Address@madc_seq3 : 0x49000a20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000100" |
tt_add |
|
|
| madc_seq_ms_en |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x49000724 Address@madc_seq1 : 0x49000824 Address@madc_seq2 : 0x49000924 Address@madc_seq3 : 0x49000a24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
m7 |
|
|
| 6 | "0" |
m6 |
|
|
| 5 | "0" |
m5 |
|
|
| 4 | "0" |
m4 |
|
|
| 3 | "0" |
m3 |
|
|
| 2 | "0" |
m2 |
|
|
| 1 | "0" |
m1 |
|
|
| 0 | "0" |
m0 |
|
|
| madc_seq_ms_baseadr |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x49000728 Address@madc_seq1 : 0x49000828 Address@madc_seq2 : 0x49000928 Address@madc_seq3 : 0x49000a28 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0x0 |
adr |
|
|
| 0 | 0 |
- |
reserved | |
| madc_seq_m0 |
|
||||||||||||||||||||||||||||||||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x4900072c Address@madc_seq1 : 0x4900082c Address@madc_seq2 : 0x4900092c Address@madc_seq3 : 0x49000a2c |
Bits | Reset value | Name | Description | |||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | ||||||||||||||||||||||||||||||
| 27 - 23 | "00000" |
adr_offset |
|
||||||||||||||||||||||||||||||
| 22 - 20 | "000" |
mux |
|
||||||||||||||||||||||||||||||
| 19 - 17 | "000" |
oversample |
|
||||||||||||||||||||||||||||||
| 16 - 0 | 0x1ffff |
trigger |
|
||||||||||||||||||||||||||||||
| madc_seq_m1 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000730 Address@madc_seq1 : 0x49000830 Address@madc_seq2 : 0x49000930 Address@madc_seq3 : 0x49000a30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m2 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000734 Address@madc_seq1 : 0x49000834 Address@madc_seq2 : 0x49000934 Address@madc_seq3 : 0x49000a34 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m3 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000738 Address@madc_seq1 : 0x49000838 Address@madc_seq2 : 0x49000938 Address@madc_seq3 : 0x49000a38 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m4 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x4900073c Address@madc_seq1 : 0x4900083c Address@madc_seq2 : 0x4900093c Address@madc_seq3 : 0x49000a3c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m5 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000740 Address@madc_seq1 : 0x49000840 Address@madc_seq2 : 0x49000940 Address@madc_seq3 : 0x49000a40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m6 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000744 Address@madc_seq1 : 0x49000844 Address@madc_seq2 : 0x49000944 Address@madc_seq3 : 0x49000a44 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_m7 |
|
|||
| R/W |
0x0001ffff |
Address@madc_seq0 : 0x49000748 Address@madc_seq1 : 0x49000848 Address@madc_seq2 : 0x49000948 Address@madc_seq3 : 0x49000a48 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | 0 |
- |
reserved | |
| 27 - 23 | "00000" |
adr_offset |
|
|
| 22 - 20 | "000" |
mux |
|
|
| 19 - 17 | "000" |
oversample |
|
|
| 16 - 0 | 0x1ffff |
trigger |
|
|
| madc_seq_cmd |
|
|||||||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x4900074c Address@madc_seq1 : 0x4900084c Address@madc_seq2 : 0x4900094c Address@madc_seq3 : 0x49000a4c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||
| 3 | "0" |
debug |
|
|||||
| 2 | "0" |
reset |
|
|||||
| 1 | "0" |
continuous |
|
|||||
| 0 | "0" |
run |
|
|||||
| madc_seq_status |
|
|||
| R |
Address@madc_seq0 : 0x49000750 Address@madc_seq1 : 0x49000850 Address@madc_seq2 : 0x49000950 Address@madc_seq3 : 0x49000a50 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 - 4 | adc_half_clock_cycle |
|
||
| 3 - 0 | m_nr |
|
||
| madc_seq_result_current |
|
|||
| R |
Address@madc_seq0 : 0x49000754 Address@madc_seq1 : 0x49000854 Address@madc_seq2 : 0x49000954 Address@madc_seq3 : 0x49000a54 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | valid |
|
||
| 30 - 19 | - |
reserved | ||
| 18 - 16 | mnr |
|
||
| 15 - 0 | val |
|
||
| madc_seq_result_last |
|
|||
| R |
Address@madc_seq0 : 0x49000758 Address@madc_seq1 : 0x49000858 Address@madc_seq2 : 0x49000958 Address@madc_seq3 : 0x49000a58 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | valid |
|
||
| 30 - 19 | - |
reserved | ||
| 18 - 16 | mnr |
|
||
| 15 - 0 | val |
|
||
| madc_seq_debug |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x4900075c Address@madc_seq1 : 0x4900085c Address@madc_seq2 : 0x4900095c Address@madc_seq3 : 0x49000a5c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
adc_set_mux3 |
|
|
| 4 | "0" |
adc_set_mux2 |
|
|
| 3 | "0" |
adc_set_mux1 |
|
|
| 2 | "0" |
adc_set_mux0 |
|
|
| 1 | "0" |
adc_res |
|
|
| 0 | "0" |
adc_clk |
|
|
| madc_seq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x49000770 Address@madc_seq1 : 0x49000870 Address@madc_seq2 : 0x49000970 Address@madc_seq3 : 0x49000a70 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
dma_hresp |
|
|
| 9 | "0" |
dma_overrun |
|
|
| 8 | "0" |
seq_cmpl |
|
|
| 7 | "0" |
m7_cmpl |
|
|
| 6 | "0" |
m6_cmpl |
|
|
| 5 | "0" |
m5_cmpl |
|
|
| 4 | "0" |
m4_cmpl |
|
|
| 3 | "0" |
m3_cmpl |
|
|
| 2 | "0" |
m2_cmpl |
|
|
| 1 | "0" |
m1_cmpl |
|
|
| 0 | "0" |
m0_cmpl |
|
|
| madc_seq_irq_masked |
|
|||
| R |
Address@madc_seq0 : 0x49000774 Address@madc_seq1 : 0x49000874 Address@madc_seq2 : 0x49000974 Address@madc_seq3 : 0x49000a74 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 11 | - |
reserved | ||
| 10 | dma_hresp |
|
||
| 9 | dma_overrun |
|
||
| 8 | seq_cmpl |
|
||
| 7 | m7_cmpl |
|
||
| 6 | m6_cmpl |
|
||
| 5 | m5_cmpl |
|
||
| 4 | m4_cmpl |
|
||
| 3 | m3_cmpl |
|
||
| 2 | m2_cmpl |
|
||
| 1 | m1_cmpl |
|
||
| 0 | m0_cmpl |
|
||
| madc_seq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x49000778 Address@madc_seq1 : 0x49000878 Address@madc_seq2 : 0x49000978 Address@madc_seq3 : 0x49000a78 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
dma_hresp |
|
|
| 9 | "0" |
dma_overrun |
|
|
| 8 | "0" |
seq_cmpl |
|
|
| 7 | "0" |
m7_cmpl |
|
|
| 6 | "0" |
m6_cmpl |
|
|
| 5 | "0" |
m5_cmpl |
|
|
| 4 | "0" |
m4_cmpl |
|
|
| 3 | "0" |
m3_cmpl |
|
|
| 2 | "0" |
m2_cmpl |
|
|
| 1 | "0" |
m1_cmpl |
|
|
| 0 | "0" |
m0_cmpl |
|
|
| madc_seq_irq_mask_reset |
|
|||
| R/W |
0x00000000 |
Address@madc_seq0 : 0x4900077c Address@madc_seq1 : 0x4900087c Address@madc_seq2 : 0x4900097c Address@madc_seq3 : 0x49000a7c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 11 | 0 |
- |
reserved | |
| 10 | "0" |
dma_hresp |
|
|
| 9 | "0" |
dma_overrun |
|
|
| 8 | "0" |
seq_cmpl |
|
|
| 7 | "0" |
m7_cmpl |
|
|
| 6 | "0" |
m6_cmpl |
|
|
| 5 | "0" |
m5_cmpl |
|
|
| 4 | "0" |
m4_cmpl |
|
|
| 3 | "0" |
m3_cmpl |
|
|
| 2 | "0" |
m2_cmpl |
|
|
| 1 | "0" |
m1_cmpl |
|
|
| 0 | "0" |
m0_cmpl |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_motion_exp_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_motion_exp_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_motion_exp_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_motion_exp_0_irq_mask_rst |
| mot_irq_router_cpu0_motion_exp_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_motion_exp_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_motion_exp_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_motion_exp_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921000c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
sync_timer_global_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
sync_timer_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
menc_err_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
menc_cap_mp_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mpwm_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
trigger_irq_global_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
trigger_irq_global_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
trigger_irq_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
trigger_irq_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
endat_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
endat_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
biss_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
biss_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
menc_enc_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
menc_enc_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
sdfm_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
sdfm_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
sdfm_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
madc_seq_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
madc_seq_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
madc_seq_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
madc_seq_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_sync_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_sync_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_sync_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_sync_0_irq_mask_rst |
| mot_irq_router_cpu0_sync_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu0_sync_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu0_sync_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu0_sync_0_irq_mask_rst |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x4921001c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||
| 1 | "0" |
sync_timer_global_0 |
|
|||||||
| 0 | "0" |
sync_timer_0 |
|
|||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_mpwm_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_mpwm_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_mpwm_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_mpwm_0_irq_mask_rst |
| mot_irq_router_cpu0_mpwm_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu0_mpwm_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu0_mpwm_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu0_mpwm_0_irq_mask_rst |
|
|||||||
| R/W |
0x00000000 |
Address : 0x4921002c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
mpwm_0 |
|
|||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_adc_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_adc_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_adc_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_adc_0_irq_mask_rst |
| mot_irq_router_cpu0_adc_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_adc_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_adc_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu0_adc_0_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921003c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
sdfm_1 |
|
|||||||||||
| 2 | "0" |
sdfm_0 |
|
|||||||||||
| 1 | "0" |
madc_seq_1 |
|
|||||||||||
| 0 | "0" |
madc_seq_0 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_adc_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_adc_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_adc_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_adc_1_irq_mask_rst |
| mot_irq_router_cpu0_adc_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu0_adc_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu0_adc_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu0_adc_1_irq_mask_rst |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x4921004c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
sdfm_2 |
|
|||||||||
| 1 | "0" |
madc_seq_3 |
|
|||||||||
| 0 | "0" |
madc_seq_2 |
|
|||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_enc_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_enc_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_enc_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_enc_0_irq_mask_rst |
| mot_irq_router_cpu0_enc_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu0_enc_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu0_enc_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu0_enc_0_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921005c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
endat_0 |
|
|||||||||||
| 2 | "0" |
biss_0 |
|
|||||||||||
| 1 | "0" |
menc_cap_mp_0 |
|
|||||||||||
| 0 | "0" |
menc_enc_0 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_enc_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_enc_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_enc_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_enc_1_irq_mask_rst |
| mot_irq_router_cpu0_enc_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu0_enc_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu0_enc_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu0_enc_1_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921006c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
endat_1 |
|
|||||||||||
| 2 | "0" |
biss_1 |
|
|||||||||||
| 1 | "0" |
menc_cap_mp_0 |
|
|||||||||||
| 0 | "0" |
menc_enc_1 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_com_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_com_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_com_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_com_0_irq_mask_rst |
| mot_irq_router_cpu0_com_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921007c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_com_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_com_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_com_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_com_1_irq_mask_rst |
| mot_irq_router_cpu0_com_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921008c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_com_2_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_com_2_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_com_2_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_com_2_irq_mask_rst |
| mot_irq_router_cpu0_com_2_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_2_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_2_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_2_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921009c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_com_3_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_com_3_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_com_3_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_com_3_irq_mask_rst |
| mot_irq_router_cpu0_com_3_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492100a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_3_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492100a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_3_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492100a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu0_com_3_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492100ac |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_peri_0_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_peri_0_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu0_peri_0_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu0_peri_0_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu0_peri_0_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu0_peri_0_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu0_peri_0_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu0_peri_0_1_irq_mask_rst |
| mot_irq_router_cpu0_peri_0_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492100c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_0_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492100c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_0_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492100c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_0_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492100cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_0_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492100d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_0_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492100d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_0_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492100d8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu0_peri_0_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492100dc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_peri_1_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_peri_1_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu0_peri_1_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu0_peri_1_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu0_peri_1_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu0_peri_1_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu0_peri_1_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu0_peri_1_1_irq_mask_rst |
| mot_irq_router_cpu0_peri_1_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492100e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_1_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492100e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_1_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492100e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_1_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492100ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_1_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492100f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_1_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492100f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_1_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492100f8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu0_peri_1_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492100fc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_peri_2_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_peri_2_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu0_peri_2_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu0_peri_2_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu0_peri_2_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu0_peri_2_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu0_peri_2_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu0_peri_2_1_irq_mask_rst |
| mot_irq_router_cpu0_peri_2_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_2_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_2_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_2_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x4921010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_2_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_2_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_2_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x49210118 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu0_peri_2_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921011c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_peri_3_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_peri_3_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu0_peri_3_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu0_peri_3_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu0_peri_3_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu0_peri_3_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu0_peri_3_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu0_peri_3_1_irq_mask_rst |
| mot_irq_router_cpu0_peri_3_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_3_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_3_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_3_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x4921012c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_3_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu0_peri_3_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu0_peri_3_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x49210138 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu0_peri_3_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921013c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu0_shdint_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu0_shdint_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu0_shdint_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu0_shdint_0_irq_mask_rst |
| mot_irq_router_cpu0_shdint_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49210140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu0_shdint_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49210144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu0_shdint_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49210148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu0_shdint_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921014c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
shdint_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
shdint_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
shdint_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
shdint_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
shdint_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
shdint_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
shdint_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
shdint_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
shdint_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
shdint_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
shdint_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
shdint_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
shdint_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
shdint_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
shdint_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
shdint_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
shdint_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
shdint_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
shdint_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
shdint_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
shdint_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
shdint_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
shdint_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
shdint_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_motion_exp_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_motion_exp_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_motion_exp_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_motion_exp_0_irq_mask_rst |
| mot_irq_router_cpu1_motion_exp_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_motion_exp_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_motion_exp_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |
| 21 | "0" |
sync_timer_global_0 |
|
|
| 20 | "0" |
sync_timer_0 |
|
|
| 19 | "0" |
menc_err_0 |
|
|
| 18 | "0" |
menc_cap_mp_0 |
|
|
| 17 | "0" |
mpwm_0 |
|
|
| 16 | "0" |
trigger_irq_global_1 |
|
|
| 15 | "0" |
trigger_irq_global_0 |
|
|
| 14 | "0" |
trigger_irq_1 |
|
|
| 13 | "0" |
trigger_irq_0 |
|
|
| 12 | "0" |
endat_1 |
|
|
| 11 | "0" |
endat_0 |
|
|
| 10 | "0" |
biss_1 |
|
|
| 9 | "0" |
biss_0 |
|
|
| 8 | "0" |
menc_enc_1 |
|
|
| 7 | "0" |
menc_enc_0 |
|
|
| 6 | "0" |
sdfm_2 |
|
|
| 5 | "0" |
sdfm_1 |
|
|
| 4 | "0" |
sdfm_0 |
|
|
| 3 | "0" |
madc_seq_3 |
|
|
| 2 | "0" |
madc_seq_2 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_motion_exp_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921100c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
sync_timer_global_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
sync_timer_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
menc_err_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
menc_cap_mp_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mpwm_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
trigger_irq_global_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
trigger_irq_global_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
trigger_irq_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
trigger_irq_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
endat_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
endat_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
biss_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
biss_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
menc_enc_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
menc_enc_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
sdfm_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
sdfm_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
sdfm_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
madc_seq_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
madc_seq_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
madc_seq_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
madc_seq_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_sync_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_sync_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_sync_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_sync_0_irq_mask_rst |
| mot_irq_router_cpu1_sync_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu1_sync_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu1_sync_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
sync_timer_global_0 |
|
|
| 0 | "0" |
sync_timer_0 |
|
|
| mot_irq_router_cpu1_sync_0_irq_mask_rst |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x4921101c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |||||||
| 1 | "0" |
sync_timer_global_0 |
|
|||||||
| 0 | "0" |
sync_timer_0 |
|
|||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_mpwm_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_mpwm_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_mpwm_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_mpwm_0_irq_mask_rst |
| mot_irq_router_cpu1_mpwm_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu1_mpwm_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu1_mpwm_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
mpwm_0 |
|
|
| mot_irq_router_cpu1_mpwm_0_irq_mask_rst |
|
|||||||
| R/W |
0x00000000 |
Address : 0x4921102c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
mpwm_0 |
|
|||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_adc_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_adc_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_adc_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_adc_0_irq_mask_rst |
| mot_irq_router_cpu1_adc_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_adc_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_adc_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
sdfm_1 |
|
|
| 2 | "0" |
sdfm_0 |
|
|
| 1 | "0" |
madc_seq_1 |
|
|
| 0 | "0" |
madc_seq_0 |
|
|
| mot_irq_router_cpu1_adc_0_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921103c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
sdfm_1 |
|
|||||||||||
| 2 | "0" |
sdfm_0 |
|
|||||||||||
| 1 | "0" |
madc_seq_1 |
|
|||||||||||
| 0 | "0" |
madc_seq_0 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_adc_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_adc_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_adc_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_adc_1_irq_mask_rst |
| mot_irq_router_cpu1_adc_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu1_adc_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu1_adc_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sdfm_2 |
|
|
| 1 | "0" |
madc_seq_3 |
|
|
| 0 | "0" |
madc_seq_2 |
|
|
| mot_irq_router_cpu1_adc_1_irq_mask_rst |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x4921104c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
sdfm_2 |
|
|||||||||
| 1 | "0" |
madc_seq_3 |
|
|||||||||
| 0 | "0" |
madc_seq_2 |
|
|||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_enc_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_enc_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_enc_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_enc_0_irq_mask_rst |
| mot_irq_router_cpu1_enc_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211050 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu1_enc_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu1_enc_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_0 |
|
|
| 2 | "0" |
biss_0 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_0 |
|
|
| mot_irq_router_cpu1_enc_0_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921105c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
endat_0 |
|
|||||||||||
| 2 | "0" |
biss_0 |
|
|||||||||||
| 1 | "0" |
menc_cap_mp_0 |
|
|||||||||||
| 0 | "0" |
menc_enc_0 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_enc_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_enc_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_enc_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_enc_1_irq_mask_rst |
| mot_irq_router_cpu1_enc_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu1_enc_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu1_enc_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
endat_1 |
|
|
| 2 | "0" |
biss_1 |
|
|
| 1 | "0" |
menc_cap_mp_0 |
|
|
| 0 | "0" |
menc_enc_1 |
|
|
| mot_irq_router_cpu1_enc_1_irq_mask_rst |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x4921106c |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||||||
| 3 | "0" |
endat_1 |
|
|||||||||||
| 2 | "0" |
biss_1 |
|
|||||||||||
| 1 | "0" |
menc_cap_mp_0 |
|
|||||||||||
| 0 | "0" |
menc_enc_1 |
|
|||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_com_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_com_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_com_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_com_0_irq_mask_rst |
| mot_irq_router_cpu1_com_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921107c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_com_1_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_com_1_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_com_1_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_com_1_irq_mask_rst |
| mot_irq_router_cpu1_com_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921108c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_com_2_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_com_2_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_com_2_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_com_2_irq_mask_rst |
| mot_irq_router_cpu1_com_2_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_2_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_2_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_2_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921109c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_com_3_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_com_3_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_com_3_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_com_3_irq_mask_rst |
| mot_irq_router_cpu1_com_3_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492110a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_3_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492110a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_3_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492110a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hsc_3 |
|
|
| 14 | "0" |
hsc_2 |
|
|
| 13 | "0" |
hsc_1 |
|
|
| 12 | "0" |
hsc_0 |
|
|
| 11 | "0" |
sms_3 |
|
|
| 10 | "0" |
sms_2 |
|
|
| 9 | "0" |
sms_1 |
|
|
| 8 | "0" |
sms_0 |
|
|
| 7 | "0" |
mhu_7 |
|
|
| 6 | "0" |
mhu_6 |
|
|
| 5 | "0" |
mhu_5 |
|
|
| 4 | "0" |
mhu_4 |
|
|
| 3 | "0" |
mhu_3 |
|
|
| 2 | "0" |
mhu_2 |
|
|
| 1 | "0" |
mhu_1 |
|
|
| 0 | "0" |
mhu_0 |
|
|
| mot_irq_router_cpu1_com_3_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492110ac |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||
| 15 | "0" |
hsc_3 |
|
|||||||||||||||||||||||||||||||||||
| 14 | "0" |
hsc_2 |
|
|||||||||||||||||||||||||||||||||||
| 13 | "0" |
hsc_1 |
|
|||||||||||||||||||||||||||||||||||
| 12 | "0" |
hsc_0 |
|
|||||||||||||||||||||||||||||||||||
| 11 | "0" |
sms_3 |
|
|||||||||||||||||||||||||||||||||||
| 10 | "0" |
sms_2 |
|
|||||||||||||||||||||||||||||||||||
| 9 | "0" |
sms_1 |
|
|||||||||||||||||||||||||||||||||||
| 8 | "0" |
sms_0 |
|
|||||||||||||||||||||||||||||||||||
| 7 | "0" |
mhu_7 |
|
|||||||||||||||||||||||||||||||||||
| 6 | "0" |
mhu_6 |
|
|||||||||||||||||||||||||||||||||||
| 5 | "0" |
mhu_5 |
|
|||||||||||||||||||||||||||||||||||
| 4 | "0" |
mhu_4 |
|
|||||||||||||||||||||||||||||||||||
| 3 | "0" |
mhu_3 |
|
|||||||||||||||||||||||||||||||||||
| 2 | "0" |
mhu_2 |
|
|||||||||||||||||||||||||||||||||||
| 1 | "0" |
mhu_1 |
|
|||||||||||||||||||||||||||||||||||
| 0 | "0" |
mhu_0 |
|
|||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_peri_0_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_peri_0_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu1_peri_0_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu1_peri_0_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu1_peri_0_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu1_peri_0_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu1_peri_0_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu1_peri_0_1_irq_mask_rst |
| mot_irq_router_cpu1_peri_0_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492110c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_0_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492110c4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_0_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492110c8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_0_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492110cc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_0_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492110d0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_0_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492110d4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_0_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492110d8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu1_peri_0_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492110dc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_peri_1_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_peri_1_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu1_peri_1_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu1_peri_1_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu1_peri_1_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu1_peri_1_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu1_peri_1_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu1_peri_1_1_irq_mask_rst |
| mot_irq_router_cpu1_peri_1_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492110e0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_1_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x492110e4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_1_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492110e8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_1_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x492110ec |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_1_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492110f0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_1_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x492110f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_1_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492110f8 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu1_peri_1_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x492110fc |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_peri_2_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_peri_2_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu1_peri_2_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu1_peri_2_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu1_peri_2_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu1_peri_2_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu1_peri_2_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu1_peri_2_1_irq_mask_rst |
| mot_irq_router_cpu1_peri_2_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_2_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_2_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_2_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x4921110c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_2_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211110 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_2_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_2_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x49211118 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu1_peri_2_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921111c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_peri_3_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_peri_3_1_irq_raw |
| 2 | 8 | R/W | mot_irq_router_cpu1_peri_3_0_irq_masked |
| 3 | c | R/W | mot_irq_router_cpu1_peri_3_1_irq_masked |
| 4 | 10 | R/W | mot_irq_router_cpu1_peri_3_0_irq_mask_set |
| 5 | 14 | R/W | mot_irq_router_cpu1_peri_3_1_irq_mask_set |
| 6 | 18 | R/W | mot_irq_router_cpu1_peri_3_0_irq_mask_rst |
| 7 | 1c | R/W | mot_irq_router_cpu1_peri_3_1_irq_mask_rst |
| mot_irq_router_cpu1_peri_3_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211120 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_3_1_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211124 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_3_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211128 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_3_1_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x4921112c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_3_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211130 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|
| 30 | "0" |
sqi_0 |
|
|
| 29 | "0" |
spi_1 |
|
|
| 28 | "0" |
spi_0 |
|
|
| 27 | "0" |
i2c_1 |
|
|
| 26 | "0" |
i2c_0 |
|
|
| 25 | "0" |
uart_1 |
|
|
| 24 | "0" |
uart_0 |
|
|
| 23 | "0" |
timer1_3 |
|
|
| 22 | "0" |
timer1_2 |
|
|
| 21 | "0" |
timer1_1 |
|
|
| 20 | "0" |
timer1_0 |
|
|
| 19 | "0" |
timer0_3 |
|
|
| 18 | "0" |
timer0_2 |
|
|
| 17 | "0" |
timer0_1 |
|
|
| 16 | "0" |
timer0_0 |
|
|
| 15 | "0" |
gpio_15 |
|
|
| 14 | "0" |
gpio_14 |
|
|
| 13 | "0" |
gpio_13 |
|
|
| 12 | "0" |
gpio_12 |
|
|
| 11 | "0" |
gpio_11 |
|
|
| 10 | "0" |
gpio_10 |
|
|
| 9 | "0" |
gpio_9 |
|
|
| 8 | "0" |
gpio_8 |
|
|
| 7 | "0" |
gpio_7 |
|
|
| 6 | "0" |
gpio_6 |
|
|
| 5 | "0" |
gpio_5 |
|
|
| 4 | "0" |
gpio_4 |
|
|
| 3 | "0" |
gpio_3 |
|
|
| 2 | "0" |
gpio_2 |
|
|
| 1 | "0" |
gpio_1 |
|
|
| 0 | "0" |
gpio_0 |
|
|
| mot_irq_router_cpu1_peri_3_1_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211134 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
ram_ctrl_0 |
|
|
| 4 | "0" |
pio_0 |
|
|
| 3 | "0" |
wdg1_1 |
|
|
| 2 | "0" |
wdg1_0 |
|
|
| 1 | "0" |
wdg0_1 |
|
|
| 0 | "0" |
wdg0_0 |
|
|
| mot_irq_router_cpu1_peri_3_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x49211138 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sqi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
sqi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
spi_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
spi_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
i2c_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
i2c_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
uart_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
uart_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
timer1_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
timer1_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
timer1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
timer1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
timer0_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
timer0_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
timer0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
timer0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
gpio_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
gpio_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
gpio_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
gpio_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
gpio_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
gpio_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
gpio_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
gpio_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
gpio_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
gpio_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
gpio_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
gpio_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
gpio_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
gpio_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
gpio_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
gpio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| mot_irq_router_cpu1_peri_3_1_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921113c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
ram_ctrl_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
pio_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
wdg1_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
wdg1_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
wdg0_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
wdg0_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | mot_irq_router_cpu1_shdint_0_irq_raw |
| 1 | 4 | R/W | mot_irq_router_cpu1_shdint_0_irq_masked |
| 2 | 8 | R/W | mot_irq_router_cpu1_shdint_0_irq_mask_set |
| 3 | c | R/W | mot_irq_router_cpu1_shdint_0_irq_mask_rst |
| mot_irq_router_cpu1_shdint_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x49211140 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu1_shdint_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x49211144 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu1_shdint_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x49211148 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
shdint_23 |
|
|
| 22 | "0" |
shdint_22 |
|
|
| 21 | "0" |
shdint_21 |
|
|
| 20 | "0" |
shdint_20 |
|
|
| 19 | "0" |
shdint_19 |
|
|
| 18 | "0" |
shdint_18 |
|
|
| 17 | "0" |
shdint_17 |
|
|
| 16 | "0" |
shdint_16 |
|
|
| 15 | "0" |
shdint_15 |
|
|
| 14 | "0" |
shdint_14 |
|
|
| 13 | "0" |
shdint_13 |
|
|
| 12 | "0" |
shdint_12 |
|
|
| 11 | "0" |
shdint_11 |
|
|
| 10 | "0" |
shdint_10 |
|
|
| 9 | "0" |
shdint_9 |
|
|
| 8 | "0" |
shdint_8 |
|
|
| 7 | "0" |
shdint_7 |
|
|
| 6 | "0" |
shdint_6 |
|
|
| 5 | "0" |
shdint_5 |
|
|
| 4 | "0" |
shdint_4 |
|
|
| 3 | "0" |
shdint_3 |
|
|
| 2 | "0" |
shdint_2 |
|
|
| 1 | "0" |
shdint_1 |
|
|
| 0 | "0" |
shdint_0 |
|
|
| mot_irq_router_cpu1_shdint_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x4921114c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
shdint_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
shdint_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
shdint_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
shdint_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
shdint_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
shdint_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
shdint_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
shdint_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
shdint_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
shdint_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
shdint_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
shdint_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
shdint_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
shdint_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
shdint_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
shdint_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
shdint_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
shdint_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
shdint_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
shdint_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
shdint_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
shdint_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
shdint_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
shdint_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | cmsdk_timer_ctrl |
| 1 | 4 | R/W | cmsdk_timer_value |
| 2 | 8 | R/W | cmsdk_timer_reload |
| 3 | c | R/W | cmsdk_timer_int |
| 4-3f3 | 10-fcc | - | reserved |
| 3f4 | fd0 | R | cmsdk_timer_pid4 |
| 3f5 | fd4 | R | cmsdk_timer_pid5 |
| 3f6 | fd8 | R | cmsdk_timer_pid6 |
| 3f7 | fdc | R | cmsdk_timer_pid7 |
| 3f8 | fe0 | R | cmsdk_timer_pid0 |
| 3f9 | fe4 | R | cmsdk_timer_pid1 |
| 3fa | fe8 | R | cmsdk_timer_pid2 |
| 3fb | fec | R | cmsdk_timer_pid3 |
| 3fc | ff0 | R | cmsdk_timer_cid0 |
| 3fd | ff4 | R | cmsdk_timer_cid1 |
| 3fe | ff8 | R | cmsdk_timer_cid2 |
| 3ff | ffc | R | cmsdk_timer_cid3 |
| cmsdk_timer_ctrl |
|
|||
| R/W |
0x00000000 |
Address@secenc_timer0 : 0x50000000 Address@secenc_timer1 : 0x50001000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
timer_interrupt_enable |
|
|
| 2 | "0" |
select_external_input_as_clock |
|
|
| 1 | "0" |
select_external_input_as_enable |
|
|
| 0 | "0" |
enable |
|
|
| cmsdk_timer_value |
|
|||
| R/W |
0x00000000 |
Address@secenc_timer0 : 0x50000004 Address@secenc_timer1 : 0x50001004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
value |
|
|
| cmsdk_timer_reload |
|
|||
| R/W |
0x00000000 |
Address@secenc_timer0 : 0x50000008 Address@secenc_timer1 : 0x50001008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
reload |
|
|
| cmsdk_timer_int |
|
|||
| R/W |
0x00000000 |
Address@secenc_timer0 : 0x5000000c Address@secenc_timer1 : 0x5000100c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
stat_clr |
|
|
| cmsdk_timer_pid4 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fd0 Address@secenc_timer1 : 0x50001fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | block_count |
|
||
| 3 - 0 | jep106_c_code |
|
||
| cmsdk_timer_pid5 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fd4 Address@secenc_timer1 : 0x50001fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_timer_pid5 | |||
| cmsdk_timer_pid6 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fd8 Address@secenc_timer1 : 0x50001fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_timer_pid6 | |||
| cmsdk_timer_pid7 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fdc Address@secenc_timer1 : 0x50001fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_timer_pid7 | |||
| cmsdk_timer_pid0 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fe0 Address@secenc_timer1 : 0x50001fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cmsdk_timer_pid1 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fe4 Address@secenc_timer1 : 0x50001fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | jep106_id_3_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cmsdk_timer_pid2 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fe8 Address@secenc_timer1 : 0x50001fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec_used |
|
||
| 2 - 0 | jep106_id_6_4 |
|
||
| cmsdk_timer_pid3 |
|
|||
| R |
Address@secenc_timer0 : 0x50000fec Address@secenc_timer1 : 0x50001fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | eco_rev_num |
|
||
| 3 - 0 | cmod |
|
||
| cmsdk_timer_cid0 |
|
|||
| R |
Address@secenc_timer0 : 0x50000ff0 Address@secenc_timer1 : 0x50001ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cmsdk_timer_cid1 |
|
|||
| R |
Address@secenc_timer0 : 0x50000ff4 Address@secenc_timer1 : 0x50001ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cmsdk_timer_cid2 |
|
|||
| R |
Address@secenc_timer0 : 0x50000ff8 Address@secenc_timer1 : 0x50001ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cmsdk_timer_cid3 |
|
|||
| R |
Address@secenc_timer0 : 0x50000ffc Address@secenc_timer1 : 0x50001ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | secenc_otp_base |
| 1-7fe | 4-1ff8 | - | reserved |
| 7ff | 1ffc | R/W | secenc_otp_end |
| secenc_otp_base |
|
|||
| R/W |
0x00000000 |
Address@secenc_otp0 : 0x50018000 Address@secenc_otp1 : 0x5001a000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
secenc_otp_base | ||
| secenc_otp_end |
|
|||
| R/W |
0x00000000 |
Address@secenc_otp0 : 0x50019ffc Address@secenc_otp1 : 0x5001bffc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
secenc_otp_end | ||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | secenc_asic_ctrl_sse_system_status |
| 1-3ff | 4-ffc | - | reserved |
| secenc_asic_ctrl_sse_system_status |
|
|||
| R |
Address : 0x5001e000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | top_dftenable |
|
||
| 0 | testmode |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | W | hash_din |
| 1 | 4 | R/W | hash_cfg |
| 2 | 8 | W | hash_ctrl |
| 3 | c | R | hash_stat |
| 4 | 10 | - | reserved |
| 5 | 14 | R/W | hash_irq_raw |
| 6 | 18 | R/W | hash_irq_masked |
| 7 | 1c | R/W | hash_irq_mask_set |
| 8 | 20 | R/W | hash_irq_mask_rst |
| 9 | 24 | R | hash_dout0 |
| a | 28 | R | hash_dout1 |
| b | 2c | R | hash_dout2 |
| c | 30 | R | hash_dout3 |
| d | 34 | R | hash_dout4 |
| e | 38 | R | hash_dout5 |
| f | 3c | R | hash_dout6 |
| 10 | 40 | R | hash_dout7 |
| 11 | 44 | R | hash_dout8 |
| 12 | 48 | R | hash_dout9 |
| 13 | 4c | R | hash_dout10 |
| 14 | 50 | R | hash_dout11 |
| 15 | 54 | R | hash_dout12 |
| 16 | 58 | R | hash_dout13 |
| 17 | 5c | R | hash_dout14 |
| 18 | 60 | R | hash_dout15 |
| 19 | 64 | R/W | hash_hmac_key0 |
| 1a | 68 | R/W | hash_hmac_key1 |
| 1b | 6c | R/W | hash_hmac_key2 |
| 1c | 70 | R/W | hash_hmac_key3 |
| 1d | 74 | R/W | hash_hmac_key4 |
| 1e | 78 | R/W | hash_hmac_key5 |
| 1f | 7c | R/W | hash_hmac_key6 |
| 20 | 80 | R/W | hash_hmac_key7 |
| 21 | 84 | R/W | hash_hmac_key8 |
| 22 | 88 | R/W | hash_hmac_key9 |
| 23 | 8c | R/W | hash_hmac_key10 |
| 24 | 90 | R/W | hash_hmac_key11 |
| 25 | 94 | R/W | hash_hmac_key12 |
| 26 | 98 | R/W | hash_hmac_key13 |
| 27 | 9c | R/W | hash_hmac_key14 |
| 28 | a0 | R/W | hash_hmac_key15 |
| 29-3f | a4-fc | - | reserved |
| hash_din |
|
|||
| W |
0x00000000 |
Address : 0x5001f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_cfg |
|
||||||||||||||||
| R/W |
0x00000000 |
Address : 0x5001f004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | ||||||||||||||
| 5 | "0" |
hmac_en |
|
||||||||||||||
| 4 | "0" |
reset |
|
||||||||||||||
| 3 - 1 | "000" |
mode |
|
||||||||||||||
| 0 | "0" |
enable |
|
||||||||||||||
| hash_ctrl |
|
|||
| W |
0x00000000 |
Address : 0x5001f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
hmac_finish |
|
|
| 0 | "0" |
trigger_padding |
|
|
| hash_stat |
|
|||
| R |
Address : 0x5001f00c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 9 | - |
reserved | ||
| 8 - 0 | fifo_fill |
|
||
| hash_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
fifo_overflow |
|
|
| 1 | "0" |
fifo_underrun |
|
|
| 0 | "0" |
hash_ready |
|
|
| hash_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
fifo_overflow |
|
|
| 1 | "0" |
fifo_underrun |
|
|
| 0 | "0" |
hash_ready |
|
|
| hash_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f01c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
fifo_overflow |
|
|
| 1 | "0" |
fifo_underrun |
|
|
| 0 | "0" |
hash_ready |
|
|
| hash_irq_mask_rst |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x5001f020 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
fifo_overflow |
|
|||||||||
| 1 | "0" |
fifo_underrun |
|
|||||||||
| 0 | "0" |
hash_ready |
|
|||||||||
| hash_dout0 |
|
|||
| R |
Address : 0x5001f024 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout1 |
|
|||
| R |
Address : 0x5001f028 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout2 |
|
|||
| R |
Address : 0x5001f02c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout3 |
|
|||
| R |
Address : 0x5001f030 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout4 |
|
|||
| R |
Address : 0x5001f034 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout5 |
|
|||
| R |
Address : 0x5001f038 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout6 |
|
|||
| R |
Address : 0x5001f03c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout7 |
|
|||
| R |
Address : 0x5001f040 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout8 |
|
|||
| R |
Address : 0x5001f044 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout9 |
|
|||
| R |
Address : 0x5001f048 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout10 |
|
|||
| R |
Address : 0x5001f04c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout11 |
|
|||
| R |
Address : 0x5001f050 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout12 |
|
|||
| R |
Address : 0x5001f054 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout13 |
|
|||
| R |
Address : 0x5001f058 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout14 |
|
|||
| R |
Address : 0x5001f05c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_dout15 |
|
|||
| R |
Address : 0x5001f060 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | val |
|
||
| hash_hmac_key0 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key1 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key2 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f06c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key3 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f070 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key4 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f074 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key5 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f078 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key6 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f07c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key7 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key8 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key9 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key10 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f08c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key11 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key12 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key13 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key14 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f09c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| hash_hmac_key15 |
|
|||
| R/W |
0x00000000 |
Address : 0x5001f0a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sys2jtag_cfg |
| 1 | 4 | W | sys2jtag_cmd_data |
| 2 | 8 | R | sys2jtag_status_data |
| 3 | c | R | sys2jtag_status |
| 4 | 10 | R | sys2jtag_chain_status |
| 5 | 14 | R/W | sys2jtag_chain_cfg |
| 6 | 18 | R | sys2jtag_handshake_rx |
| 7 | 1c | R/W | sys2jtag_handshake_tx |
| sys2jtag_cfg |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x50020000 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||||
| 2 - 1 | "00" |
speed |
|
|||||||||||
| 0 | "0" |
enable |
|
|||||||||||
| sys2jtag_cmd_data |
|
||||||||||||||
| W |
0x00000000 |
Address : 0x50020004 |
Bits | Reset value | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
cmd |
|
||||||||||||
| 23 - 0 | 0x0 |
data |
|
||||||||||||
| sys2jtag_status_data |
|
|||||||||||||||||||||||||||||||||||||
| R |
Address : 0x50020008 |
Bits | Name | Description | ||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | idle |
|
||||||||||||||||||||||||||||||||||||
| 30 - 27 | tap_state |
|
||||||||||||||||||||||||||||||||||||
| 26 - 24 | - |
reserved | ||||||||||||||||||||||||||||||||||||
| 23 - 0 | data |
|
||||||||||||||||||||||||||||||||||||
| sys2jtag_status |
|
|||||||||||||||||||||||||||||||||||||
| R |
Address : 0x5002000c |
Bits | Name | Description | ||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | idle |
|
||||||||||||||||||||||||||||||||||||
| 30 - 27 | tap_state |
|
||||||||||||||||||||||||||||||||||||
| 26 - 0 | - |
reserved | ||||||||||||||||||||||||||||||||||||
| sys2jtag_chain_status |
|
|||
| R |
Address : 0x50020010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | sel_sys2jtag |
|
||
| 0 | en_sys2jtag |
|
||
| sys2jtag_chain_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x50020014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
tap_active |
|
|
| sys2jtag_handshake_rx |
|
|||
| R |
Address : 0x50020018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | val |
|
||
| sys2jtag_handshake_tx |
|
|||
| R/W |
0x00000000 |
Address : 0x5002001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
val |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | secenc_sys_ctrl_se_rst_syn |
| 1 | 4 | R/W | secenc_sys_ctrl_se_rst_msk |
| 2 | 8 | R/W | secenc_sys_ctrl_se_pwr_ctrl |
| 3-4 | c-10 | - | reserved |
| 5 | 14 | R/W | secenc_sys_ctrl_se_gp0 |
| 6 | 18 | R/W | secenc_sys_ctrl_se_gp1 |
| 7 | 1c | R/W | secenc_sys_ctrl_se_gp2 |
| 8 | 20 | R/W | secenc_sys_ctrl_se_gp3 |
| 9-b | 24-2c | - | reserved |
| c | 30 | R/W | secenc_sys_ctrl_se_clk_div |
| d-3d | 34-f4 | - | reserved |
| 3e | f8 | R | secenc_sys_ctrl_se_bld_cfg |
| 3f-3f3 | fc-fcc | - | reserved |
| 3f4 | fd0 | R | secenc_sys_ctrl_pid4 |
| 3f5 | fd4 | R | secenc_sys_ctrl_pid5 |
| 3f6 | fd8 | R | secenc_sys_ctrl_pid6 |
| 3f7 | fdc | R | secenc_sys_ctrl_pid7 |
| 3f8 | fe0 | R | secenc_sys_ctrl_pid0 |
| 3f9 | fe4 | R | secenc_sys_ctrl_pid1 |
| 3fa | fe8 | R | secenc_sys_ctrl_pid2 |
| 3fb | fec | R | secenc_sys_ctrl_pid3 |
| 3fc | ff0 | R | secenc_sys_ctrl_cid0 |
| 3fd | ff4 | R | secenc_sys_ctrl_cid1 |
| 3fe | ff8 | R | secenc_sys_ctrl_cid2 |
| 3ff | ffc | R | secenc_sys_ctrl_cid3 |
| secenc_sys_ctrl_se_rst_syn |
|
|||||||
| R |
Address : 0x50080000 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||
| 2 | ca_err |
|
||||||
| 1 | wd_reset |
|
||||||
| 0 | sw_reset |
|
||||||
| secenc_sys_ctrl_se_rst_msk |
|
||||||||
| R/W |
0x00000000 |
Address : 0x50080004 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
ca_err_msk |
|
||||||
| 1 - 0 | 0 |
- |
reserved | ||||||
| secenc_sys_ctrl_se_pwr_ctrl |
|
|||||||
| R/W |
0x00000000 |
Address : 0x50080008 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |||||
| 0 | "0" |
pwr_gate_en |
|
|||||
| secenc_sys_ctrl_se_gp0 |
|
|||
| R/W |
0x00000000 |
Address : 0x50080014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
gp |
|
|
| secenc_sys_ctrl_se_gp1 |
|
|||
| R/W |
0x00000000 |
Address : 0x50080018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
gp |
|
|
| secenc_sys_ctrl_se_gp2 |
|
|||
| R/W |
0x00000000 |
Address : 0x5008001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
gp |
|
|
| secenc_sys_ctrl_se_gp3 |
|
|||
| R/W |
0x00000000 |
Address : 0x50080020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
gp |
|
|
| secenc_sys_ctrl_se_clk_div |
|
||||||||
| R/W |
0x00000001 |
Address : 0x50080030 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||
| 20 - 16 | "00000" |
clkdiv_cur |
|
||||||
| 15 - 5 | 0 |
- |
reserved | ||||||
| 4 - 0 | "00001" |
clk_divider |
|
||||||
| secenc_sys_ctrl_se_bld_cfg |
|
|||
| R |
Address : 0x500800f8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | ram_size |
|
||
| 15 - 0 | rom_size |
|
||
| secenc_sys_ctrl_pid4 |
|
|||
| R |
Address : 0x50080fd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| secenc_sys_ctrl_pid5 |
|
|||
| R |
Address : 0x50080fd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_sys_ctrl_pid5 | |||
| secenc_sys_ctrl_pid6 |
|
|||
| R |
Address : 0x50080fd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_sys_ctrl_pid6 | |||
| secenc_sys_ctrl_pid7 |
|
|||
| R |
Address : 0x50080fdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_sys_ctrl_pid7 | |||
| secenc_sys_ctrl_pid0 |
|
|||
| R |
Address : 0x50080fe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| secenc_sys_ctrl_pid1 |
|
|||
| R |
Address : 0x50080fe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| secenc_sys_ctrl_pid2 |
|
|||
| R |
Address : 0x50080fe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| secenc_sys_ctrl_pid3 |
|
|||
| R |
Address : 0x50080fec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| secenc_sys_ctrl_cid0 |
|
|||
| R |
Address : 0x50080ff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| secenc_sys_ctrl_cid1 |
|
|||
| R |
Address : 0x50080ff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| secenc_sys_ctrl_cid2 |
|
|||
| R |
Address : 0x50080ff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| secenc_sys_ctrl_cid3 |
|
|||
| R |
Address : 0x50080ffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | cmsdk_wdog_wdogload |
| 1 | 4 | R | cmsdk_wdog_wdogvalue |
| 2 | 8 | R/W | cmsdk_wdog_wdogcontrol |
| 3 | c | W | cmsdk_wdog_wdogintclr |
| 4 | 10 | R | cmsdk_wdog_wdogris |
| 5 | 14 | R | cmsdk_wdog_wdogmis |
| 6-2ff | 18-bfc | - | reserved |
| 300 | c00 | R/W | cmsdk_wdog_wdoglock |
| 301-3bf | c04-efc | - | reserved |
| 3c0 | f00 | R/W | cmsdk_wdog_wdogitcr |
| 3c1 | f04 | W | cmsdk_wdog_wdogitor |
| 3c2-3f3 | f08-fcc | - | reserved |
| 3f4 | fd0 | R | cmsdk_wdog_pid4 |
| 3f5 | fd4 | R | cmsdk_wdog_pid5 |
| 3f6 | fd8 | R | cmsdk_wdog_pid6 |
| 3f7 | fdc | R | cmsdk_wdog_pid7 |
| 3f8 | fe0 | R | cmsdk_wdog_pid0 |
| 3f9 | fe4 | R | cmsdk_wdog_pid1 |
| 3fa | fe8 | R | cmsdk_wdog_pid2 |
| 3fb | fec | R | cmsdk_wdog_pid3 |
| 3fc | ff0 | R | cmsdk_wdog_cid0 |
| 3fd | ff4 | R | cmsdk_wdog_cid1 |
| 3fe | ff8 | R | cmsdk_wdog_cid2 |
| 3ff | ffc | R | cmsdk_wdog_cid3 |
| cmsdk_wdog_wdogload |
|
|||
| R/W |
0x00000000 |
Address@secenc_watchdog : 0x50081000 Address@secenc_soc_watchdog : 0x5008f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
value |
|
|
| cmsdk_wdog_wdogvalue |
|
|||
| R |
Address@secenc_watchdog : 0x50081004 Address@secenc_soc_watchdog : 0x5008f004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | value |
|
||
| cmsdk_wdog_wdogcontrol |
|
|||
| R/W |
0x00000000 |
Address@secenc_watchdog : 0x50081008 Address@secenc_soc_watchdog : 0x5008f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
resen |
|
|
| 0 | "0" |
inten |
|
|
| cmsdk_wdog_wdogintclr |
|
|||
| W |
0x00000000 |
Address@secenc_watchdog : 0x5008100c Address@secenc_soc_watchdog : 0x5008f00c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
value |
|
|
| cmsdk_wdog_wdogris |
|
|||
| R |
Address@secenc_watchdog : 0x50081010 Address@secenc_soc_watchdog : 0x5008f010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | stat |
|
||
| cmsdk_wdog_wdogmis |
|
|||
| R |
Address@secenc_watchdog : 0x50081014 Address@secenc_soc_watchdog : 0x5008f014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | stat |
|
||
| cmsdk_wdog_wdoglock |
|
|||||||
| R/W |
0x00000000 |
Address@secenc_watchdog : 0x50081c00 Address@secenc_soc_watchdog : 0x5008fc00 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | 0x0 |
write_value |
|
|||||
| 0 | "0" |
write_enable |
|
|||||
| cmsdk_wdog_wdogitcr |
|
|||
| R/W |
0x00000000 |
Address@secenc_watchdog : 0x50081f00 Address@secenc_soc_watchdog : 0x5008ff00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
enable |
|
|
| cmsdk_wdog_wdogitor |
|
|||
| W |
0x00000000 |
Address@secenc_watchdog : 0x50081f04 Address@secenc_soc_watchdog : 0x5008ff04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
wdogint_value |
|
|
| 0 | "0" |
wdogres_value |
|
|
| cmsdk_wdog_pid4 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fd0 Address@secenc_soc_watchdog : 0x5008ffd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | block_count |
|
||
| 3 - 0 | jep106_c_code |
|
||
| cmsdk_wdog_pid5 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fd4 Address@secenc_soc_watchdog : 0x5008ffd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_wdog_pid5 | |||
| cmsdk_wdog_pid6 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fd8 Address@secenc_soc_watchdog : 0x5008ffd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_wdog_pid6 | |||
| cmsdk_wdog_pid7 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fdc Address@secenc_soc_watchdog : 0x5008ffdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cmsdk_wdog_pid7 | |||
| cmsdk_wdog_pid0 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fe0 Address@secenc_soc_watchdog : 0x5008ffe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| cmsdk_wdog_pid1 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fe4 Address@secenc_soc_watchdog : 0x5008ffe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | jep106_id_3_0 |
|
||
| 3 - 0 | part_1 |
|
||
| cmsdk_wdog_pid2 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fe8 Address@secenc_soc_watchdog : 0x5008ffe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec_used |
|
||
| 2 - 0 | jep106_id_6_4 |
|
||
| cmsdk_wdog_pid3 |
|
|||
| R |
Address@secenc_watchdog : 0x50081fec Address@secenc_soc_watchdog : 0x5008ffec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | eco_rev_num |
|
||
| 3 - 0 | cmod |
|
||
| cmsdk_wdog_cid0 |
|
|||
| R |
Address@secenc_watchdog : 0x50081ff0 Address@secenc_soc_watchdog : 0x5008fff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cmsdk_wdog_cid1 |
|
|||
| R |
Address@secenc_watchdog : 0x50081ff4 Address@secenc_soc_watchdog : 0x5008fff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cmsdk_wdog_cid2 |
|
|||
| R |
Address@secenc_watchdog : 0x50081ff8 Address@secenc_soc_watchdog : 0x5008fff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cmsdk_wdog_cid3 |
|
|||
| R |
Address@secenc_watchdog : 0x50081ffc Address@secenc_soc_watchdog : 0x5008fffc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| secenc_base_sys_ctrl_host_sys_rst_ctrl |
|
|||
| R/W |
0x00000001 |
Address : 0x5008e000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
rst_req |
|
|
| 0 | "1" |
cpuwait |
|
|
| secenc_base_sys_ctrl_host_sys_rst_st |
|
|||||||||||
| R |
Address : 0x5008e004 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | - |
reserved | ||||||||||
| 2 - 1 | rst_ack |
|
||||||||||
| 0 | - |
reserved | ||||||||||
| secenc_base_sys_ctrl_soc_rst_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
rst_req |
|
|
| 0 | 0 |
- |
reserved | |
| secenc_base_sys_ctrl_soc_rst_syn |
|
|||
| R |
Address : 0x5008e00c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | sec_enc |
|
||
| 30 - 4 | - |
reserved | ||
| 3 | soc_wdog |
|
||
| 2 | - |
reserved | ||
| 1 | nsrst |
|
||
| 0 | por |
|
||
| secenc_base_sys_ctrl_int_col_st0 |
|
|||
| R |
Address : 0x5008e010 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ssi_st |
|
||
| secenc_base_sys_ctrl_int_col_st1 |
|
|||
| R |
Address : 0x5008e014 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ssi_st |
|
||
| secenc_base_sys_ctrl_int_col_st2 |
|
|||
| R |
Address : 0x5008e018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | ssi_st |
|
||
| secenc_base_sys_ctrl_int_col_st3 |
|
|||
| R |
Address : 0x5008e01c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_base_sys_ctrl_int_col_st3 | |||
| secenc_base_sys_ctrl_int_col_msk0 |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ssi_msk |
|
|
| secenc_base_sys_ctrl_int_col_msk1 |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ssi_msk |
|
|
| secenc_base_sys_ctrl_int_col_msk2 |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ssi_msk |
|
|
| secenc_base_sys_ctrl_int_col_msk3 |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e02c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
secenc_base_sys_ctrl_int_col_msk3 | ||
| secenc_base_sys_ctrl_bsys_pwr_req |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x5008e400 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||
| 5 - 3 | "000" |
systop_pwr_req |
|
|||||||||
| 2 | "0" |
dbgtop_pwr_req |
|
|||||||||
| 1 | "0" |
refclk_req |
|
|||||||||
| 0 | "0" |
wakeup_en |
|
|||||||||
| secenc_base_sys_ctrl_bsys_pwr_st |
|
||||||||||||
| R |
Address : 0x5008e404 |
Bits | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | - |
reserved | |||||||||||
| 5 - 3 | systop_pwr_st |
|
|||||||||||
| 2 | dbgtop_pwr_st |
|
|||||||||||
| 1 - 0 | - |
reserved | |||||||||||
| secenc_base_sys_ctrl_clk_ctrl |
|
||||||||||
| R/W |
0x00000001 |
Address : 0x5008e800 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | "00000000" |
entry_delay |
|
||||||||
| 23 - 16 | 0 |
- |
reserved | ||||||||
| 15 - 8 | "00000000" |
clkselect_cur |
|
||||||||
| 7 - 0 | "00000001" |
clkselect |
|
||||||||
| secenc_base_sys_ctrl_clk_div |
|
|||
| R/W |
0x00000000 |
Address : 0x5008e804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 - 16 | "00000" |
clkdiv_cur |
||
| 15 - 5 | 0 |
- |
reserved | |
| 4 - 0 | "00000" |
clkdiv |
||
| secenc_base_sys_ctrl_clkforce_st |
|
|||||||
| R |
Address : 0x5008ea00 |
Bits | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||||||
| 0 | secencclk_force_st |
|
||||||
| secenc_base_sys_ctrl_clkforce_set |
|
|||
| W |
0x00000000 |
Address : 0x5008ea04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
secencclk_force_set |
|
|
| secenc_base_sys_ctrl_clkforce_clr |
|
|||
| W |
0x00000000 |
Address : 0x5008ea08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
secencclk_force_clr |
|
|
| secenc_base_sys_ctrl_pll_st |
|
|||
| R |
Address : 0x5008ea10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 1 | - |
reserved | ||
| 0 | sysplllock_st |
|
||
| secenc_base_sys_ctrl_pid4 |
|
|||
| R |
Address : 0x5008efd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | size |
|
||
| 3 - 0 | des_2 |
|
||
| secenc_base_sys_ctrl_pid5 |
|
|||
| R |
Address : 0x5008efd4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_base_sys_ctrl_pid5 | |||
| secenc_base_sys_ctrl_pid6 |
|
|||
| R |
Address : 0x5008efd8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_base_sys_ctrl_pid6 | |||
| secenc_base_sys_ctrl_pid7 |
|
|||
| R |
Address : 0x5008efdc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | secenc_base_sys_ctrl_pid7 | |||
| secenc_base_sys_ctrl_pid0 |
|
|||
| R |
Address : 0x5008efe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | part_0 |
|
||
| secenc_base_sys_ctrl_pid1 |
|
|||
| R |
Address : 0x5008efe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | des_0 |
|
||
| 3 - 0 | part_1 |
|
||
| secenc_base_sys_ctrl_pid2 |
|
|||
| R |
Address : 0x5008efe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revision |
|
||
| 3 | jedec |
|
||
| 2 - 0 | des_1 |
|
||
| secenc_base_sys_ctrl_pid3 |
|
|||
| R |
Address : 0x5008efec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | revand |
|
||
| 3 - 0 | cmod |
|
||
| secenc_base_sys_ctrl_cid0 |
|
|||
| R |
Address : 0x5008eff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| secenc_base_sys_ctrl_cid1 |
|
|||
| R |
Address : 0x5008eff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| secenc_base_sys_ctrl_cid2 |
|
|||
| R |
Address : 0x5008eff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| secenc_base_sys_ctrl_cid3 |
|
|||
| R |
Address : 0x5008effc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_netx22xx_5_mbist_power0 |
| 1 | 4 | R/W | gen_ram_ctrl_netx22xx_5_mbist_power1 |
| 2-1ff | 8-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_netx22xx_5_ecc0 |
| 201 | 804 | R/W | gen_ram_ctrl_netx22xx_5_ecc1 |
| 202-27f | 808-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_netx22xx_5_ecc_status_corr0 |
| 281 | a04 | R | gen_ram_ctrl_netx22xx_5_ecc_status_corr1 |
| 282-2ff | a08-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_netx22xx_5_ecc_status_noncorr0 |
| 301 | c04 | R | gen_ram_ctrl_netx22xx_5_ecc_status_noncorr1 |
| 302-37f | c08-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_netx22xx_5_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_netx22xx_5_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_netx22xx_5_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_netx22xx_5_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_netx22xx_5_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_netx22xx_5_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@secenc_secenc_ram_ctrl : 0x50091000 Address@secenc_ram_ctrl : 0x50091000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_5_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address@secenc_secenc_ram_ctrl : 0x50091004 Address@secenc_ram_ctrl : 0x50091004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_5_ecc0 |
|
|||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091800 Address@secenc_ram_ctrl : 0x50091800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_5_ecc1 |
|
|||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091804 Address@secenc_ram_ctrl : 0x50091804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_5_ecc_status_corr0 |
|
|||
| R |
Address@secenc_secenc_ram_ctrl : 0x50091a00 Address@secenc_ram_ctrl : 0x50091a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_5_ecc_status_corr1 |
|
|||
| R |
Address@secenc_secenc_ram_ctrl : 0x50091a04 Address@secenc_ram_ctrl : 0x50091a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_5_ecc_status_noncorr0 |
|
|||
| R |
Address@secenc_secenc_ram_ctrl : 0x50091c00 Address@secenc_ram_ctrl : 0x50091c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_5_ecc_status_noncorr1 |
|
|||
| R |
Address@secenc_secenc_ram_ctrl : 0x50091c04 Address@secenc_ram_ctrl : 0x50091c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_5_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091e00 Address@secenc_ram_ctrl : 0x50091e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_err_ecc_correctable |
|
|
| 2 | "0" |
mem_0_err_ecc_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_5_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091e40 Address@secenc_ram_ctrl : 0x50091e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_err_ecc_correctable |
|
|
| 2 | "0" |
mem_0_err_ecc_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_5_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091e80 Address@secenc_ram_ctrl : 0x50091e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 4 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 3 | "0" |
mem_1_err_ecc_correctable |
|
|
| 2 | "0" |
mem_0_err_ecc_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_5_irq_mask_rst_reg0 |
|
|||||||||||||||||
| R/W |
0x00000000 |
Address@secenc_secenc_ram_ctrl : 0x50091ec0 Address@secenc_ram_ctrl : 0x50091ec0 |
Bits | Reset value | Name | Description | ||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||
| 5 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||
| 4 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||
| 3 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||
| 2 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||
| gen_ram_ctrl_netx22xx_5_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address@secenc_secenc_ram_ctrl : 0x50091efc Address@secenc_ram_ctrl : 0x50091efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | dpm_cfg0x0 |
| 1 | 4 | R/W | dpm_if_cfg |
| 2 | 8 | R/W | dpm_pio_cfg0 |
| 3 | c | R/W | dpm_pio_cfg1 |
| 4 | 10 | R/W | dpm_addr_cfg |
| 5 | 14 | R/W | dpm_timing_cfg |
| 6 | 18 | R/W | dpm_rdy_cfg |
| 7 | 1c | R | dpm_status |
| 8 | 20 | R/W | dpm_status_err_reset |
| 9 | 24 | R | dpm_status_err_addr |
| a | 28 | R/W | dpm_misc_cfg |
| b | 2c | R/W | dpm_io_cfg_misc |
| c-d | 30-34 | - | reserved |
| e | 38 | R/W | dpm_tunnel_cfg |
| f | 3c | R/W | dpm_itbaddr |
| 10 | 40 | R/W | dpm_win1_end |
| 11 | 44 | R/W | dpm_win1_map |
| 12 | 48 | R/W | dpm_win2_end |
| 13 | 4c | R/W | dpm_win2_map |
| 14 | 50 | R/W | dpm_win3_end |
| 15 | 54 | R/W | dpm_win3_map |
| 16 | 58 | R/W | dpm_win4_end |
| 17 | 5c | R/W | dpm_win4_map |
| 18-1f | 60-7c | - | reserved |
| 20 | 80 | R | dpm_irq_raw |
| 21 | 84 | R/W | dpm_irq_host_sirq_mask_set |
| 22 | 88 | R/W | dpm_irq_host_sirq_mask_reset |
| 23 | 8c | R | dpm_irq_host_sirq_masked |
| 24 | 90 | R/W | dpm_irq_host_dirq_mask_set |
| 25 | 94 | R/W | dpm_irq_host_dirq_mask_reset |
| 26 | 98 | R | dpm_irq_host_dirq_masked |
| 27-2d | 9c-b4 | - | reserved |
| 2e | b8 | R/W | dpm_sw_irq |
| 2f | bc | R/W | dpm_crc |
| 30-36 | c0-d8 | - | reserved |
| 37 | dc | R/W | dpm_reset_request |
| 38-3c | e0-f0 | - | reserved |
| 3d | f4 | R | dpm_netx_version_bigend16 |
| 3e | f8 | - | reserved |
| 3f | fc | R | dpm_netx_version |
| dpm_cfg0x0 |
|
||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138400 Address@dpm1 : 0x60138500 |
Bits | Reset value | Name | Description | |||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | ||||||||||||||||||||||||||||||||
| 5 - 4 | "00" |
endian |
|
||||||||||||||||||||||||||||||||
| 3 - 0 | "0000" |
mode |
|
||||||||||||||||||||||||||||||||
| dpm_if_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138404 Address@dpm1 : 0x60138504 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 - 16 | "000" |
cs_ctrl |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
addr_sh |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
aen_pol |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 - 12 | "00" |
aen_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 - 8 | "0000" |
be_pol |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
be_wr_dis |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
be_rd_dis |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
be_sel |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 - 2 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 - 0 | "00" |
dir_ctrl |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| dpm_pio_cfg0 |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138408 Address@dpm1 : 0x60138508 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
sel_d_pio |
|
|
| dpm_pio_cfg1 |
|
|||
| R/W |
0xe0000000 |
Address@dpm0 : 0x6013840c Address@dpm1 : 0x6013850c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "1" |
sel_sirq_pio |
|
|
| 30 | "1" |
sel_dirq_pio |
|
|
| 29 | "1" |
sel_rdy_pio |
|
|
| 28 | "0" |
sel_wrn_pio |
|
|
| 27 | "0" |
sel_rdn_pio |
|
|
| 26 | "0" |
sel_csn_pio |
|
|
| 25 | "0" |
sel_bhe3_pio |
|
|
| 24 | "0" |
sel_bhe1_pio |
|
|
| 23 - 20 | 0 |
- |
reserved | |
| 19 - 0 | 0x0 |
sel_a_pio |
|
|
| dpm_addr_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000002 |
Address@dpm0 : 0x60138410 Address@dpm1 : 0x60138510 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 - 4 | "00" |
cfg_win_addr_cfg |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 - 0 | "0010" |
addr_range |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| dpm_timing_cfg (dpm_access_cfg) |
|
||||||||||||||
| R/W |
0x0000003d |
Address@dpm0 : 0x60138414 Address@dpm1 : 0x60138514 |
Bits | Reset value | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sdpm_miso_early |
|
||||||||||||
| 30 | "0" |
en_dpm_serial_sqi |
|
||||||||||||
| 29 - 9 | 0 |
- |
reserved | ||||||||||||
| 8 | "0" |
rd_burst_en |
|
||||||||||||
| 7 - 4 | "0011" |
t_rds |
|
||||||||||||
| 3 | "1" |
filter |
|
||||||||||||
| 2 - 0 | "101" |
t_osa |
|
||||||||||||
| dpm_rdy_cfg |
|
||||||||||||
| R/W |
0x00000001 |
Address@dpm0 : 0x60138418 Address@dpm1 : 0x60138518 |
Bits | Reset value | Name | Description | |||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | ||||||||||
| 5 - 4 | "00" |
rdy_to_cfg |
|
||||||||||
| 3 | "0" |
rdy_sig_mode |
|
||||||||||
| 2 - 1 | "00" |
rdy_drv_mode |
|
||||||||||
| 0 | "1" |
rdy_pol |
|
||||||||||
| dpm_status |
|
||||||||||||||||||||||||||||||||||
| R |
Address@dpm0 : 0x6013841c Address@dpm1 : 0x6013851c |
Bits | Name | Description | |||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | - |
reserved | |||||||||||||||||||||||||||||||||
| 8 | abort_err |
|
|||||||||||||||||||||||||||||||||
| 7 | sel_dpm_serial |
|
|||||||||||||||||||||||||||||||||
| 6 | bus_conflict_rd_addr_err |
|
|||||||||||||||||||||||||||||||||
| 5 | bus_conflict_rd_err |
|
|||||||||||||||||||||||||||||||||
| 4 | bus_conflict_wr_err |
|
|||||||||||||||||||||||||||||||||
| 3 | rdy_to_err |
|
|||||||||||||||||||||||||||||||||
| 2 | wr_err |
|
|||||||||||||||||||||||||||||||||
| 1 | rd_err |
|
|||||||||||||||||||||||||||||||||
| 0 | unlocked |
|
|||||||||||||||||||||||||||||||||
| dpm_status_err_reset |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138420 Address@dpm1 : 0x60138520 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
abort_err_rst |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
bus_conflict_rd_addr_err_rst |
|
|
| 5 | "0" |
bus_conflict_rd_err_rst |
|
|
| 4 | "0" |
bus_conflict_wr_err_rst |
|
|
| 3 | "0" |
rdy_to_err_rst |
|
|
| 2 | "0" |
wr_err_rst |
|
|
| 1 | "0" |
rd_err_rst |
|
|
| 0 | 0 |
- |
reserved | |
| dpm_status_err_addr |
|
|||
| R |
Address@dpm0 : 0x60138424 Address@dpm1 : 0x60138524 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 20 | - |
reserved | ||
| 19 - 0 | err_addr |
|
||
| dpm_misc_cfg |
|
|||
| R/W |
0x00000006 |
Address@dpm0 : 0x60138428 Address@dpm1 : 0x60138528 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "1" |
dis_bus_conflict_err_detect |
|
|
| 1 | "1" |
dis_access_err_halt |
|
|
| 0 | "0" |
enable_flag_reset_on_rd |
|
|
| dpm_io_cfg_misc |
|
|||||||
| R/W |
0x000000a0 |
Address@dpm0 : 0x6013842c Address@dpm1 : 0x6013852c |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||
| 7 | "1" |
fiq_oec |
|
|||||
| 6 | "0" |
fiq_pol |
|
|||||
| 5 | "1" |
irq_oec |
|
|||||
| 4 | "0" |
irq_pol |
|
|||||
| 3 - 0 | 0 |
- |
reserved | |||||
| dpm_tunnel_cfg |
|
||||||||||
| R/W |
0x80000101 |
Address@dpm0 : 0x60138438 Address@dpm1 : 0x60138538 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "1" |
wp_cfg_win |
|
||||||||
| 30 - 20 | 0 |
- |
reserved | ||||||||
| 19 - 6 | 0x4 |
base |
|
||||||||
| 5 | "0" |
dis_rd_latch |
|
||||||||
| 4 | "0" |
byte_area |
|
||||||||
| 3 | "0" |
tunnel_all |
|
||||||||
| 2 | "0" |
enable |
|
||||||||
| 1 | "0" |
wp_itbaddr |
|
||||||||
| 0 | "1" |
wp_data |
|
||||||||
| dpm_itbaddr |
|
|||
| R/W |
0x00000001 |
Address@dpm0 : 0x6013843c Address@dpm1 : 0x6013853c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0x0 |
base |
|
|
| 5 - 2 | "0000" |
map |
|
|
| 1 | - |
wp_itbaddr_ro |
|
|
| 0 | - |
wp_data_ro |
|
|
| dpm_win1_end |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138440 Address@dpm1 : 0x60138540 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 - 7 | 0x0 |
win_end |
|
|
| 6 - 0 | 0 |
- |
reserved | |
| dpm_win1_map |
|
||||||||
| R/W |
0x01800000 |
Address@dpm0 : 0x60138444 Address@dpm1 : 0x60138544 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0x18 |
win_page |
|
||||||
| 19 - 7 | 0x0 |
win_map |
|
||||||
| 6 | 0 |
- |
reserved | ||||||
| 5 | "0" |
wp_cfg_win |
|
||||||
| 4 | "0" |
dis_rd_latch |
|
||||||
| 3 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
read_ahead |
|
||||||
| 0 | "0" |
byte_area |
|
||||||
| dpm_win2_end |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138448 Address@dpm1 : 0x60138548 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 - 7 | 0x0 |
win_end |
|
|
| 6 - 0 | 0 |
- |
reserved | |
| dpm_win2_map |
|
|||
| R/W |
0x01800000 |
Address@dpm0 : 0x6013844c Address@dpm1 : 0x6013854c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0x18 |
win_page |
|
|
| 19 - 7 | 0x0 |
win_map |
|
|
| 6 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
dis_rd_latch |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
read_ahead |
|
|
| 0 | "0" |
byte_area |
|
|
| dpm_win3_end |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138450 Address@dpm1 : 0x60138550 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 - 7 | 0x0 |
win_end |
|
|
| 6 - 0 | 0 |
- |
reserved | |
| dpm_win3_map |
|
|||
| R/W |
0x01800000 |
Address@dpm0 : 0x60138454 Address@dpm1 : 0x60138554 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0x18 |
win_page |
|
|
| 19 - 7 | 0x0 |
win_map |
|
|
| 6 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
dis_rd_latch |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
read_ahead |
|
|
| 0 | "0" |
byte_area |
|
|
| dpm_win4_end |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138458 Address@dpm1 : 0x60138558 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | |
| 20 - 7 | 0x0 |
win_end |
|
|
| 6 - 0 | 0 |
- |
reserved | |
| dpm_win4_map |
|
|||
| R/W |
0x01800000 |
Address@dpm0 : 0x6013845c Address@dpm1 : 0x6013855c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 20 | 0x18 |
win_page |
|
|
| 19 - 7 | 0x0 |
win_map |
|
|
| 6 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
dis_rd_latch |
|
|
| 3 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
read_ahead |
|
|
| 0 | "0" |
byte_area |
|
|
| dpm_irq_raw |
|
|||
| R |
Address@dpm0 : 0x60138480 Address@dpm1 : 0x60138580 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | dpm_sw |
|
||
| 30 | dpm_err |
|
||
| 29 - 0 | sms |
|
||
| dpm_irq_host_sirq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138484 Address@dpm1 : 0x60138584 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
dpm_sw |
|
|
| 30 | "0" |
dpm_err |
|
|
| 29 - 0 | 0x0 |
sms |
|
|
| dpm_irq_host_sirq_mask_reset |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138488 Address@dpm1 : 0x60138588 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
dpm_sw |
|
|
| 30 | "0" |
dpm_err |
|
|
| 29 - 0 | 0x0 |
sms |
|
|
| dpm_irq_host_sirq_masked |
|
|||
| R |
Address@dpm0 : 0x6013848c Address@dpm1 : 0x6013858c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | dpm_sw |
|
||
| 30 | dpm_err |
|
||
| 29 - 0 | sms |
|
||
| dpm_irq_host_dirq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138490 Address@dpm1 : 0x60138590 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
dpm_sw |
|
|
| 30 | "0" |
dpm_err |
|
|
| 29 - 0 | 0x0 |
sms |
|
|
| dpm_irq_host_dirq_mask_reset |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x60138494 Address@dpm1 : 0x60138594 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
dpm_sw |
|
|
| 30 | "0" |
dpm_err |
|
|
| 29 - 0 | 0x0 |
sms |
|
|
| dpm_irq_host_dirq_masked |
|
|||
| R |
Address@dpm0 : 0x60138498 Address@dpm1 : 0x60138598 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | dpm_sw |
|
||
| 30 | dpm_err |
|
||
| 29 - 0 | sms |
|
||
| dpm_sw_irq |
|
|||
| R/W |
0x00000000 |
Address@dpm0 : 0x601384b8 Address@dpm1 : 0x601385b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
reset_host_dirq |
|
|
| 8 | "0" |
reset_host_sirq |
|
|
| 7 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
set_host_dirq |
|
|
| 0 | "0" |
set_host_sirq |
|
|
| dpm_crc |
|
|||
| R/W |
0xffffffff |
Address@dpm0 : 0x601384bc Address@dpm1 : 0x601385bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xffff |
crc_wdata |
|
|
| 15 - 0 | 0xffff |
crc_rdata |
|
|
| dpm_reset_request (DPM_HOST_RESET_REQ) |
|
|||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@dpm0 : 0x601384dc Address@dpm1 : 0x601385dc |
Bits | Reset value | Name | Description | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||||||||||||||||||||
| 7 - 0 | "00000000" |
reset_key |
|
|||||||||||||||||||||||
| dpm_netx_version_bigend16 |
|
|||||||||||||||||||||||
| R |
Address@dpm0 : 0x601384f4 Address@dpm1 : 0x601385f4 |
Bits | Name | Description | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | netx_version_byte2_swap |
|
||||||||||||||||||||||
| 23 - 16 | netx_version_byte3_swap |
|
||||||||||||||||||||||
| 15 - 8 | netx_version_byte0_swap |
|
||||||||||||||||||||||
| 7 - 0 | netx_version_byte1_swap |
|
||||||||||||||||||||||
| dpm_netx_version |
|
|||||||||||||||||||||||
| R |
Address@dpm0 : 0x601384fc Address@dpm1 : 0x601385fc |
Bits | Name | Description | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | netx_version_byte3 |
|
||||||||||||||||||||||
| 23 - 16 | netx_version_byte2 |
|
||||||||||||||||||||||
| 15 - 8 | netx_version_byte1 |
|
||||||||||||||||||||||
| 7 - 0 | netx_version_byte0 |
|
||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | hif_io_cfg |
| 1 | 4 | R/W | hif_pio_cfg |
| 2 | 8 | R/W | hif_pio_out0 |
| 3 | c | R/W | hif_pio_out1 |
| 4 | 10 | R/W | hif_pio_oe0 |
| 5 | 14 | R/W | hif_pio_oe1 |
| 6 | 18 | R | hif_pio_in0 |
| 7 | 1c | R | hif_pio_in1 |
| 8 | 20 | - | reserved |
| 9 | 24 | R | hif_pio_irq_raw |
| a | 28 | R/W | hif_pio_irq_arm_mask_set |
| b | 2c | R/W | hif_pio_irq_arm_mask_reset |
| c | 30 | R | hif_pio_irq_arm_masked |
| d | 34 | R/W | hif_pio_irq_xpic_mask_set |
| e | 38 | R/W | hif_pio_irq_xpic_mask_reset |
| f | 3c | R | hif_pio_irq_xpic_masked |
| hif_io_cfg |
|
|||||||||||||
| R/W |
0x00000000 |
Address : 0x60138600 |
Bits | Reset value | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | |||||||||||
| 12 | "0" |
unlock_dpm |
|
|||||||||||
| 11 - 5 | 0 |
- |
reserved | |||||||||||
| 4 | "0" |
en_sdpm1 |
|
|||||||||||
| 3 | "0" |
sel_dpm_serial_spo |
|
|||||||||||
| 2 | "0" |
sel_dpm_serial_sph |
|
|||||||||||
| 1 | "0" |
sel_dpm_serial |
|
|||||||||||
| 0 | "0" |
sel_hif_dpm |
|
|||||||||||
| hif_pio_cfg |
|
||||||||||||||||||
| R/W |
0x80000008 |
Address : 0x60138604 |
Bits | Reset value | Name | Description | |||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "1" |
filter_irqs |
|
||||||||||||||||
| 30 - 28 | 0 |
- |
reserved | ||||||||||||||||
| 27 - 26 | "00" |
irq_hif_dirq_cfg |
|
||||||||||||||||
| 25 - 22 | 0 |
- |
reserved | ||||||||||||||||
| 21 - 20 | "00" |
irq_hif_a17_cfg |
|
||||||||||||||||
| 19 - 18 | "00" |
irq_hif_a16_cfg |
|
||||||||||||||||
| 17 - 16 | "00" |
irq_hif_d12_cfg |
|
||||||||||||||||
| 15 - 4 | 0 |
- |
reserved | ||||||||||||||||
| 3 | "1" |
filter_en_in |
|
||||||||||||||||
| 2 | 0 |
- |
reserved | ||||||||||||||||
| 1 - 0 | "00" |
in_ctrl |
|
||||||||||||||||
| hif_pio_out0 |
|
|||
| R/W |
0x00000000 |
Address : 0x60138608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hif_d15 |
|
|
| 14 | "0" |
hif_d14 |
|
|
| 13 | "0" |
hif_d13 |
|
|
| 12 | "0" |
hif_d12 |
|
|
| 11 | "0" |
hif_d11 |
|
|
| 10 | "0" |
hif_d10 |
|
|
| 9 | "0" |
hif_d9 |
|
|
| 8 | "0" |
hif_d8 |
|
|
| 7 | "0" |
hif_d7 |
|
|
| 6 | "0" |
hif_d6 |
|
|
| 5 | "0" |
hif_d5 |
|
|
| 4 | "0" |
hif_d4 |
|
|
| 3 | "0" |
hif_d3 |
|
|
| 2 | "0" |
hif_d2 |
|
|
| 1 | "0" |
hif_d1 |
|
|
| 0 | "0" |
hif_d0 |
|
|
| hif_pio_out1 |
|
|||
| R/W |
0x00000000 |
Address : 0x6013860c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
hif_sirq |
|
|
| 30 | "0" |
hif_dirq |
|
|
| 29 | "0" |
hif_rdy |
|
|
| 28 | "0" |
hif_csn |
|
|
| 27 | "0" |
hif_wrn |
|
|
| 26 | "0" |
hif_rdn |
|
|
| 25 | "0" |
hif_bhe |
|
|
| 24 | "0" |
hif_ale |
|
|
| 23 | "0" |
hif_wrhn |
|
|
| 22 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
hif_a17 |
|
|
| 16 | "0" |
hif_a16 |
|
|
| 15 | "0" |
hif_a15 |
|
|
| 14 | "0" |
hif_a14 |
|
|
| 13 | "0" |
hif_a13 |
|
|
| 12 | "0" |
hif_a12 |
|
|
| 11 | "0" |
hif_a11 |
|
|
| 10 | "0" |
hif_a10 |
|
|
| 9 | "0" |
hif_a9 |
|
|
| 8 | "0" |
hif_a8 |
|
|
| 7 | "0" |
hif_a7 |
|
|
| 6 | "0" |
hif_a6 |
|
|
| 5 | "0" |
hif_a5 |
|
|
| 4 | "0" |
hif_a4 |
|
|
| 3 | "0" |
hif_a3 |
|
|
| 2 | "0" |
hif_a2 |
|
|
| 1 | "0" |
hif_a1 |
|
|
| 0 | "0" |
hif_a0 |
|
|
| hif_pio_oe0 |
|
|||
| R/W |
0x00000000 |
Address : 0x60138610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
hif_d15 |
|
|
| 14 | "0" |
hif_d14 |
|
|
| 13 | "0" |
hif_d13 |
|
|
| 12 | "0" |
hif_d12 |
|
|
| 11 | "0" |
hif_d11 |
|
|
| 10 | "0" |
hif_d10 |
|
|
| 9 | "0" |
hif_d9 |
|
|
| 8 | "0" |
hif_d8 |
|
|
| 7 | "0" |
hif_d7 |
|
|
| 6 | "0" |
hif_d6 |
|
|
| 5 | "0" |
hif_d5 |
|
|
| 4 | "0" |
hif_d4 |
|
|
| 3 | "0" |
hif_d3 |
|
|
| 2 | "0" |
hif_d2 |
|
|
| 1 | "0" |
hif_d1 |
|
|
| 0 | "0" |
hif_d0 |
|
|
| hif_pio_oe1 |
|
|||
| R/W |
0x00000000 |
Address : 0x60138614 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
hif_sirq |
|
|
| 30 | "0" |
hif_dirq |
|
|
| 29 | "0" |
hif_rdy |
|
|
| 28 | "0" |
hif_csn |
|
|
| 27 | "0" |
hif_wrn |
|
|
| 26 | "0" |
hif_rdn |
|
|
| 25 | "0" |
hif_bhe |
|
|
| 24 | "0" |
hif_ale |
|
|
| 23 | "0" |
hif_wrhn |
|
|
| 22 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
hif_a17 |
|
|
| 16 | "0" |
hif_a16 |
|
|
| 15 | "0" |
hif_a15 |
|
|
| 14 | "0" |
hif_a14 |
|
|
| 13 | "0" |
hif_a13 |
|
|
| 12 | "0" |
hif_a12 |
|
|
| 11 | "0" |
hif_a11 |
|
|
| 10 | "0" |
hif_a10 |
|
|
| 9 | "0" |
hif_a9 |
|
|
| 8 | "0" |
hif_a8 |
|
|
| 7 | "0" |
hif_a7 |
|
|
| 6 | "0" |
hif_a6 |
|
|
| 5 | "0" |
hif_a5 |
|
|
| 4 | "0" |
hif_a4 |
|
|
| 3 | "0" |
hif_a3 |
|
|
| 2 | "0" |
hif_a2 |
|
|
| 1 | "0" |
hif_a1 |
|
|
| 0 | "0" |
hif_a0 |
|
|
| hif_pio_in0 |
|
|||
| R |
Address : 0x60138618 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 | hif_d15 |
|
||
| 14 | hif_d14 |
|
||
| 13 | hif_d13 |
|
||
| 12 | hif_d12 |
|
||
| 11 | hif_d11 |
|
||
| 10 | hif_d10 |
|
||
| 9 | hif_d9 |
|
||
| 8 | hif_d8 |
|
||
| 7 | hif_d7 |
|
||
| 6 | hif_d6 |
|
||
| 5 | hif_d5 |
|
||
| 4 | hif_d4 |
|
||
| 3 | hif_d3 |
|
||
| 2 | hif_d2 |
|
||
| 1 | hif_d1 |
|
||
| 0 | hif_d0 |
|
||
| hif_pio_in1 |
|
|||
| R |
Address : 0x6013861c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | hif_sirq |
|
||
| 30 | hif_dirq |
|
||
| 29 | hif_rdy |
|
||
| 28 | hif_csn |
|
||
| 27 | hif_wrn |
|
||
| 26 | hif_rdn |
|
||
| 25 | hif_bhe |
|
||
| 24 | hif_ale |
|
||
| 23 | hif_wrhn |
|
||
| 22 - 18 | - |
reserved | ||
| 17 | hif_a17 |
|
||
| 16 | hif_a16 |
|
||
| 15 | hif_a15 |
|
||
| 14 | hif_a14 |
|
||
| 13 | hif_a13 |
|
||
| 12 | hif_a12 |
|
||
| 11 | hif_a11 |
|
||
| 10 | hif_a10 |
|
||
| 9 | hif_a9 |
|
||
| 8 | hif_a8 |
|
||
| 7 | hif_a7 |
|
||
| 6 | hif_a6 |
|
||
| 5 | hif_a5 |
|
||
| 4 | hif_a4 |
|
||
| 3 | hif_a3 |
|
||
| 2 | hif_a2 |
|
||
| 1 | hif_a1 |
|
||
| 0 | hif_a0 |
|
||
| hif_pio_irq_raw |
|
|||||||||||
| R |
Address : 0x60138624 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||||||||||
| 3 | irq_hif_dirq |
|
||||||||||
| 2 | irq_hif_a17 |
|
||||||||||
| 1 | irq_hif_a16 |
|
||||||||||
| 0 | irq_hif_d12 |
|
||||||||||
| hif_pio_irq_arm_mask_set |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x60138628 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||
| 3 | "0" |
irq_hif_dirq |
|
|||||||
| 2 | "0" |
irq_hif_a17 |
|
|||||||
| 1 | "0" |
irq_hif_a16 |
|
|||||||
| 0 | "0" |
irq_hif_d12 |
|
|||||||
| hif_pio_irq_arm_mask_reset |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x6013862c |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||
| 3 | "0" |
irq_hif_dirq |
|
|||||||
| 2 | "0" |
irq_hif_a17 |
|
|||||||
| 1 | "0" |
irq_hif_a16 |
|
|||||||
| 0 | "0" |
irq_hif_d12 |
|
|||||||
| hif_pio_irq_arm_masked |
|
|||||||||
| R |
Address : 0x60138630 |
Bits | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||||||||
| 3 | irq_hif_dirq |
|
||||||||
| 2 | irq_hif_a17 |
|
||||||||
| 1 | irq_hif_a16 |
|
||||||||
| 0 | irq_hif_d12 |
|
||||||||
| hif_pio_irq_xpic_mask_set |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x60138634 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||
| 3 | "0" |
irq_hif_dirq |
|
|||||||
| 2 | "0" |
irq_hif_a17 |
|
|||||||
| 1 | "0" |
irq_hif_a16 |
|
|||||||
| 0 | "0" |
irq_hif_d12 |
|
|||||||
| hif_pio_irq_xpic_mask_reset |
|
|||||||||
| R/W |
0x00000000 |
Address : 0x60138638 |
Bits | Reset value | Name | Description | ||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |||||||
| 3 | "0" |
irq_hif_dirq |
|
|||||||
| 2 | "0" |
irq_hif_a17 |
|
|||||||
| 1 | "0" |
irq_hif_a16 |
|
|||||||
| 0 | "0" |
irq_hif_d12 |
|
|||||||
| hif_pio_irq_xpic_masked |
|
|||||||||
| R |
Address : 0x6013863c |
Bits | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 4 | - |
reserved | ||||||||
| 3 | irq_hif_dirq |
|
||||||||
| 2 | irq_hif_a17 |
|
||||||||
| 1 | irq_hif_a16 |
|
||||||||
| 0 | irq_hif_d12 |
|
||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | sms_host_irq_pending |
| 1 | 4 | R | sms_host_irq_pending_masked |
| 2 | 8 | R | sms_host_irq_latch_state |
| 3 | c | R | sms_host_irq_mask_state |
| 4 | 10 | W | sms_host_irq_latch_rst |
| 5 | 14 | W | sms_host_irq_latch_set |
| 6 | 18 | W | sms_host_irq_mask_rst |
| 7 | 1c | W | sms_host_irq_mask_set |
| 8 | 20 | R/W | sms_host_irq_is_edge |
| 9-f | 24-3c | - | reserved |
| sms_host_irq_pending |
|
|||
| R |
Address : 0x60180400 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 30 | - |
reserved | ||
| 29 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 - 16 | sync_selected |
|
||
| 15 - 12 | tbuf_tx_prod |
|
||
| 11 - 8 | tbuf_rx_cons |
|
||
| 7 - 0 | hsc |
|
||
| sms_host_irq_pending_masked |
|
|||
| R |
Address : 0x60180404 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 30 | - |
reserved | ||
| 29 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 - 16 | sync_selected |
|
||
| 15 - 12 | tbuf_tx_prod |
|
||
| 11 - 8 | tbuf_rx_cons |
|
||
| 7 - 0 | hsc |
|
||
| sms_host_irq_latch_state |
|
|||
| R |
Address : 0x60180408 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 30 | - |
reserved | ||
| 29 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 - 16 | sync_selected |
|
||
| 15 - 12 | tbuf_tx_prod |
|
||
| 11 - 8 | tbuf_rx_cons |
|
||
| 7 - 0 | hsc |
|
||
| sms_host_irq_mask_state |
|
|||
| R |
Address : 0x6018040c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 30 | - |
reserved | ||
| 29 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 - 16 | sync_selected |
|
||
| 15 - 12 | tbuf_tx_prod |
|
||
| 11 - 8 | tbuf_rx_cons |
|
||
| 7 - 0 | hsc |
|
||
| sms_host_irq_latch_rst |
|
|||
| W |
0x00000000 |
Address : 0x60180410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 28 | "00" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 - 16 | "0000" |
sync_selected |
|
|
| 15 - 12 | "0000" |
tbuf_tx_prod |
|
|
| 11 - 8 | "0000" |
tbuf_rx_cons |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_host_irq_latch_set |
|
|||
| W |
0x00000000 |
Address : 0x60180414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 28 | "00" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 - 16 | "0000" |
sync_selected |
|
|
| 15 - 12 | "0000" |
tbuf_tx_prod |
|
|
| 11 - 8 | "0000" |
tbuf_rx_cons |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_host_irq_mask_rst |
|
|||
| W |
0x00000000 |
Address : 0x60180418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 28 | "00" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 - 16 | "0000" |
sync_selected |
|
|
| 15 - 12 | "0000" |
tbuf_tx_prod |
|
|
| 11 - 8 | "0000" |
tbuf_rx_cons |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_host_irq_mask_set |
|
|||
| W |
0x00000000 |
Address : 0x6018041c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 28 | "00" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 - 16 | "0000" |
sync_selected |
|
|
| 15 - 12 | "0000" |
tbuf_tx_prod |
|
|
| 11 - 8 | "0000" |
tbuf_rx_cons |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_host_irq_is_edge |
|
|||
| R/W |
0x00000000 |
Address : 0x60180420 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 30 | 0 |
- |
reserved | |
| 29 - 28 | "00" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 - 16 | "0000" |
sync_selected |
|
|
| 15 - 12 | "0000" |
tbuf_tx_prod |
|
|
| 11 - 8 | "0000" |
tbuf_rx_cons |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | sms_irq_logic_pending |
| 1 | 4 | R | sms_irq_logic_pending_masked |
| 2 | 8 | R | sms_irq_logic_latch_state |
| 3 | c | R | sms_irq_logic_mask_state |
| 4 | 10 | W | sms_irq_logic_latch_rst |
| 5 | 14 | W | sms_irq_logic_latch_set |
| 6 | 18 | W | sms_irq_logic_mask_rst |
| 7 | 1c | W | sms_irq_logic_mask_set |
| 8 | 20 | R/W | sms_irq_logic_is_edge |
| 9-f | 24-3c | - | reserved |
| sms_irq_logic_pending |
|
|||
| R |
Address@sms_host_irq_logic : 0x60180400 Address@sms_device_irq_logic : 0x601b0000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | pending |
|
||
| sms_irq_logic_pending_masked |
|
|||
| R |
Address@sms_host_irq_logic : 0x60180404 Address@sms_device_irq_logic : 0x601b0004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | pending_masked |
|
||
| sms_irq_logic_latch_state |
|
|||
| R |
Address@sms_host_irq_logic : 0x60180408 Address@sms_device_irq_logic : 0x601b0008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | state |
|
||
| sms_irq_logic_mask_state |
|
|||
| R |
Address@sms_host_irq_logic : 0x6018040c Address@sms_device_irq_logic : 0x601b000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | msk_state |
|
||
| sms_irq_logic_latch_rst |
|
|||
| W |
0x00000000 |
Address@sms_host_irq_logic : 0x60180410 Address@sms_device_irq_logic : 0x601b0010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
rst |
|
|
| sms_irq_logic_latch_set |
|
|||
| W |
0x00000000 |
Address@sms_host_irq_logic : 0x60180414 Address@sms_device_irq_logic : 0x601b0014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
set |
|
|
| sms_irq_logic_mask_rst |
|
|||
| W |
0x00000000 |
Address@sms_host_irq_logic : 0x60180418 Address@sms_device_irq_logic : 0x601b0018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
msk_rst |
|
|
| sms_irq_logic_mask_set |
|
|||
| W |
0x00000000 |
Address@sms_host_irq_logic : 0x6018041c Address@sms_device_irq_logic : 0x601b001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
msk_set |
|
|
| sms_irq_logic_is_edge |
|
|||
| R/W |
0x00000000 |
Address@sms_host_irq_logic : 0x60180420 Address@sms_device_irq_logic : 0x601b0020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
cfg |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | sms_tba_slv_0_status |
| 1 | 4 | - | reserved |
| 2 | 8 | R/W | sms_tba_slv_0_action |
| 3 | c | - | reserved |
| 4 | 10 | R/W | sms_tba_slv_0_ctrl |
| 5-3f | 14-fc | - | reserved |
| sms_tba_slv_0_status |
|
||||||||
| R |
Address : 0x60181000 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | - |
reserved | |||||||
| 15 | master_is_consumer |
|
|||||||
| 14 - 12 | bal_pre_master |
|
|||||||
| 11 - 9 | bal_pre_slave |
|
|||||||
| 8 - 6 | bal |
|
|||||||
| 5 - 4 | master_idx |
|
|||||||
| 3 - 2 | mid_idx |
|
|||||||
| 1 - 0 | slave_idx |
|
|||||||
| sms_tba_slv_0_action |
|
|||
| R/W |
0x00000000 |
Address : 0x60181008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
tgl_slave |
|
|
| sms_tba_slv_0_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x60181010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
slv_irq_en |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_host_cfg_device_reset |
| 1 | 4 | R/W | sms_host_cfg_device_reset_excl_pcie |
| 2 | 8 | R | sms_host_cfg_capabilities |
| 3 | c | - | reserved |
| sms_host_cfg_device_reset |
|
||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x60182000 |
Bits | Reset value | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | ||||||||||||||||||||||
| 7 - 0 | "00000000" |
reset_key |
|
||||||||||||||||||||||
| sms_host_cfg_device_reset_excl_pcie |
|
||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x60182004 |
Bits | Reset value | Name | Description | |||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | ||||||||||||||||||||||
| 7 - 0 | "00000000" |
reset_key |
|
||||||||||||||||||||||
| sms_host_cfg_capabilities |
|
|||
| R |
Address : 0x60182008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 2 | - |
reserved | ||
| 1 | reset_excl_pcie |
|
||
| 0 | reset |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_host_irq_router_pcie_int_a_0_irq_raw |
| 1 | 4 | R/W | sms_host_irq_router_pcie_int_a_0_irq_masked |
| 2 | 8 | R/W | sms_host_irq_router_pcie_int_a_0_irq_mask_set |
| 3 | c | R/W | sms_host_irq_router_pcie_int_a_0_irq_mask_rst |
| sms_host_irq_router_pcie_int_a_0_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x6018f000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_host_irq_router_pcie_int_a_0_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x6018f004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_host_irq_router_pcie_int_a_0_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x6018f008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_host_irq_router_pcie_int_a_0_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x6018f00c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
host_irq_vector_30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
host_irq_vector_29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
host_irq_vector_28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
host_irq_vector_27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
host_irq_vector_26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
host_irq_vector_25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
host_irq_vector_24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
host_irq_vector_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
host_irq_vector_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
host_irq_vector_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
host_irq_vector_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
host_irq_vector_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
host_irq_vector_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
host_irq_vector_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
host_irq_vector_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
host_irq_vector_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
host_irq_vector_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
host_irq_vector_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
host_irq_vector_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
host_irq_vector_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
host_irq_vector_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
host_irq_vector_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
host_irq_vector_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
host_irq_vector_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
host_irq_vector_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
host_irq_vector_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
host_irq_vector_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
host_irq_vector_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
host_irq_vector_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
host_irq_vector_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
host_irq_vector_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_device_irq_router_ada_plic_irq_irq_raw |
| 1 | 4 | R/W | sms_device_irq_router_ada_plic_irq_irq_masked |
| 2 | 8 | R/W | sms_device_irq_router_ada_plic_irq_irq_mask_set |
| 3 | c | R/W | sms_device_irq_router_ada_plic_irq_irq_mask_rst |
| sms_device_irq_router_ada_plic_irq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x601a0000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_ada_plic_irq_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x601a0004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_ada_plic_irq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x601a0008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_ada_plic_irq_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601a000c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
host_irq_vector_30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
host_irq_vector_29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
host_irq_vector_28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
host_irq_vector_27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
host_irq_vector_26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
host_irq_vector_25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
host_irq_vector_24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
host_irq_vector_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
host_irq_vector_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
host_irq_vector_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
host_irq_vector_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
host_irq_vector_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
host_irq_vector_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
host_irq_vector_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
host_irq_vector_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
host_irq_vector_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
host_irq_vector_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
host_irq_vector_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
host_irq_vector_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
host_irq_vector_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
host_irq_vector_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
host_irq_vector_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
host_irq_vector_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
host_irq_vector_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
host_irq_vector_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
host_irq_vector_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
host_irq_vector_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
host_irq_vector_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
host_irq_vector_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
host_irq_vector_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
host_irq_vector_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_device_irq_router_cda_rx_plic_irq_irq_raw |
| 1 | 4 | R/W | sms_device_irq_router_cda_rx_plic_irq_irq_masked |
| 2 | 8 | R/W | sms_device_irq_router_cda_rx_plic_irq_irq_mask_set |
| 3 | c | R/W | sms_device_irq_router_cda_rx_plic_irq_irq_mask_rst |
| sms_device_irq_router_cda_rx_plic_irq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x601a1000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_rx_plic_irq_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x601a1004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_rx_plic_irq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x601a1008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_rx_plic_irq_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601a100c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
host_irq_vector_30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
host_irq_vector_29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
host_irq_vector_28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
host_irq_vector_27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
host_irq_vector_26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
host_irq_vector_25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
host_irq_vector_24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
host_irq_vector_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
host_irq_vector_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
host_irq_vector_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
host_irq_vector_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
host_irq_vector_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
host_irq_vector_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
host_irq_vector_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
host_irq_vector_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
host_irq_vector_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
host_irq_vector_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
host_irq_vector_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
host_irq_vector_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
host_irq_vector_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
host_irq_vector_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
host_irq_vector_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
host_irq_vector_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
host_irq_vector_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
host_irq_vector_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
host_irq_vector_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
host_irq_vector_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
host_irq_vector_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
host_irq_vector_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
host_irq_vector_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
host_irq_vector_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_device_irq_router_cda_tx_plic_irq_irq_raw |
| 1 | 4 | R/W | sms_device_irq_router_cda_tx_plic_irq_irq_masked |
| 2 | 8 | R/W | sms_device_irq_router_cda_tx_plic_irq_irq_mask_set |
| 3 | c | R/W | sms_device_irq_router_cda_tx_plic_irq_irq_mask_rst |
| sms_device_irq_router_cda_tx_plic_irq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x601a2000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_tx_plic_irq_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x601a2004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_tx_plic_irq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x601a2008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_cda_tx_plic_irq_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601a200c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
host_irq_vector_30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
host_irq_vector_29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
host_irq_vector_28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
host_irq_vector_27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
host_irq_vector_26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
host_irq_vector_25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
host_irq_vector_24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
host_irq_vector_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
host_irq_vector_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
host_irq_vector_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
host_irq_vector_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
host_irq_vector_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
host_irq_vector_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
host_irq_vector_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
host_irq_vector_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
host_irq_vector_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
host_irq_vector_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
host_irq_vector_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
host_irq_vector_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
host_irq_vector_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
host_irq_vector_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
host_irq_vector_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
host_irq_vector_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
host_irq_vector_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
host_irq_vector_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
host_irq_vector_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
host_irq_vector_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
host_irq_vector_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
host_irq_vector_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
host_irq_vector_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
host_irq_vector_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_device_irq_router_iol_plic_irq_irq_raw |
| 1 | 4 | R/W | sms_device_irq_router_iol_plic_irq_irq_masked |
| 2 | 8 | R/W | sms_device_irq_router_iol_plic_irq_irq_mask_set |
| 3 | c | R/W | sms_device_irq_router_iol_plic_irq_irq_mask_rst |
| sms_device_irq_router_iol_plic_irq_irq_raw |
|
|||
| R/W |
0x00000000 |
Address : 0x601a3000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_iol_plic_irq_irq_masked |
|
|||
| R/W |
0x00000000 |
Address : 0x601a3004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_iol_plic_irq_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address : 0x601a3008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|
| 30 | "0" |
host_irq_vector_30 |
|
|
| 29 | "0" |
host_irq_vector_29 |
|
|
| 28 | "0" |
host_irq_vector_28 |
|
|
| 27 | "0" |
host_irq_vector_27 |
|
|
| 26 | "0" |
host_irq_vector_26 |
|
|
| 25 | "0" |
host_irq_vector_25 |
|
|
| 24 | "0" |
host_irq_vector_24 |
|
|
| 23 | "0" |
host_irq_vector_23 |
|
|
| 22 | "0" |
host_irq_vector_22 |
|
|
| 21 | "0" |
host_irq_vector_21 |
|
|
| 20 | "0" |
host_irq_vector_20 |
|
|
| 19 | "0" |
host_irq_vector_19 |
|
|
| 18 | "0" |
host_irq_vector_18 |
|
|
| 17 | "0" |
host_irq_vector_17 |
|
|
| 16 | "0" |
host_irq_vector_16 |
|
|
| 15 | "0" |
host_irq_vector_15 |
|
|
| 14 | "0" |
host_irq_vector_14 |
|
|
| 13 | "0" |
host_irq_vector_13 |
|
|
| 12 | "0" |
host_irq_vector_12 |
|
|
| 11 | "0" |
host_irq_vector_11 |
|
|
| 10 | "0" |
host_irq_vector_10 |
|
|
| 9 | "0" |
host_irq_vector_9 |
|
|
| 8 | "0" |
host_irq_vector_8 |
|
|
| 7 | "0" |
host_irq_vector_7 |
|
|
| 6 | "0" |
host_irq_vector_6 |
|
|
| 5 | "0" |
host_irq_vector_5 |
|
|
| 4 | "0" |
host_irq_vector_4 |
|
|
| 3 | "0" |
host_irq_vector_3 |
|
|
| 2 | "0" |
host_irq_vector_2 |
|
|
| 1 | "0" |
host_irq_vector_1 |
|
|
| 0 | "0" |
host_irq_vector_0 |
|
|
| sms_device_irq_router_iol_plic_irq_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601a300c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
host_irq_vector_31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
host_irq_vector_30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
host_irq_vector_29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
host_irq_vector_28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
host_irq_vector_27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
host_irq_vector_26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
host_irq_vector_25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
host_irq_vector_24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
host_irq_vector_23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
host_irq_vector_22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
host_irq_vector_21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
host_irq_vector_20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
host_irq_vector_19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
host_irq_vector_18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
host_irq_vector_17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
host_irq_vector_16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
host_irq_vector_15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
host_irq_vector_14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
host_irq_vector_13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
host_irq_vector_12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
host_irq_vector_11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
host_irq_vector_10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
host_irq_vector_9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
host_irq_vector_8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
host_irq_vector_7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
host_irq_vector_6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
host_irq_vector_5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
host_irq_vector_4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
host_irq_vector_3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
host_irq_vector_2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
host_irq_vector_1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
host_irq_vector_0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | sms_device_irq_pending |
| 1 | 4 | R | sms_device_irq_pending_masked |
| 2 | 8 | R | sms_device_irq_latch_state |
| 3 | c | R | sms_device_irq_mask_state |
| 4 | 10 | W | sms_device_irq_latch_rst |
| 5 | 14 | W | sms_device_irq_latch_set |
| 6 | 18 | W | sms_device_irq_mask_rst |
| 7 | 1c | W | sms_device_irq_mask_set |
| 8 | 20 | R/W | sms_device_irq_is_edge |
| 9-f | 24-3c | - | reserved |
| sms_device_irq_pending |
|
|||
| R |
Address : 0x601b0000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 | tbuf_tx_prod_err |
|
||
| 18 | tbuf_tx_cons_err |
|
||
| 17 | tbuf_rx_prod_err |
|
||
| 16 | tbuf_rx_cons_err |
|
||
| 15 - 12 | tbuf_tx_cons |
|
||
| 11 - 8 | tbuf_rx_prod |
|
||
| 7 - 0 | hsc |
|
||
| sms_device_irq_pending_masked |
|
|||
| R |
Address : 0x601b0004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 | tbuf_tx_prod_err |
|
||
| 18 | tbuf_tx_cons_err |
|
||
| 17 | tbuf_rx_prod_err |
|
||
| 16 | tbuf_rx_cons_err |
|
||
| 15 - 12 | tbuf_tx_cons |
|
||
| 11 - 8 | tbuf_rx_prod |
|
||
| 7 - 0 | hsc |
|
||
| sms_device_irq_latch_state |
|
|||
| R |
Address : 0x601b0008 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 | tbuf_tx_prod_err |
|
||
| 18 | tbuf_tx_cons_err |
|
||
| 17 | tbuf_rx_prod_err |
|
||
| 16 | tbuf_rx_cons_err |
|
||
| 15 - 12 | tbuf_tx_cons |
|
||
| 11 - 8 | tbuf_rx_prod |
|
||
| 7 - 0 | hsc |
|
||
| sms_device_irq_mask_state |
|
|||
| R |
Address : 0x601b000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 28 | sw |
|
||
| 27 - 20 | tba |
|
||
| 19 | tbuf_tx_prod_err |
|
||
| 18 | tbuf_tx_cons_err |
|
||
| 17 | tbuf_rx_prod_err |
|
||
| 16 | tbuf_rx_cons_err |
|
||
| 15 - 12 | tbuf_tx_cons |
|
||
| 11 - 8 | tbuf_rx_prod |
|
||
| 7 - 0 | hsc |
|
||
| sms_device_irq_latch_rst |
|
|||
| W |
0x00000000 |
Address : 0x601b0010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 | "0" |
tbuf_tx_prod_err |
|
|
| 18 | "0" |
tbuf_tx_cons_err |
|
|
| 17 | "0" |
tbuf_rx_prod_err |
|
|
| 16 | "0" |
tbuf_rx_cons_err |
|
|
| 15 - 12 | "0000" |
tbuf_tx_cons |
|
|
| 11 - 8 | "0000" |
tbuf_rx_prod |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_device_irq_latch_set |
|
|||
| W |
0x00000000 |
Address : 0x601b0014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 | "0" |
tbuf_tx_prod_err |
|
|
| 18 | "0" |
tbuf_tx_cons_err |
|
|
| 17 | "0" |
tbuf_rx_prod_err |
|
|
| 16 | "0" |
tbuf_rx_cons_err |
|
|
| 15 - 12 | "0000" |
tbuf_tx_cons |
|
|
| 11 - 8 | "0000" |
tbuf_rx_prod |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_device_irq_mask_rst |
|
|||
| W |
0x00000000 |
Address : 0x601b0018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 | "0" |
tbuf_tx_prod_err |
|
|
| 18 | "0" |
tbuf_tx_cons_err |
|
|
| 17 | "0" |
tbuf_rx_prod_err |
|
|
| 16 | "0" |
tbuf_rx_cons_err |
|
|
| 15 - 12 | "0000" |
tbuf_tx_cons |
|
|
| 11 - 8 | "0000" |
tbuf_rx_prod |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_device_irq_mask_set |
|
|||
| W |
0x00000000 |
Address : 0x601b001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 | "0" |
tbuf_tx_prod_err |
|
|
| 18 | "0" |
tbuf_tx_cons_err |
|
|
| 17 | "0" |
tbuf_rx_prod_err |
|
|
| 16 | "0" |
tbuf_rx_cons_err |
|
|
| 15 - 12 | "0000" |
tbuf_tx_cons |
|
|
| 11 - 8 | "0000" |
tbuf_rx_prod |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_device_irq_is_edge |
|
|||
| R/W |
0x00000000 |
Address : 0x601b0020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 28 | "0000" |
sw |
|
|
| 27 - 20 | "00000000" |
tba |
|
|
| 19 | "0" |
tbuf_tx_prod_err |
|
|
| 18 | "0" |
tbuf_tx_cons_err |
|
|
| 17 | "0" |
tbuf_rx_prod_err |
|
|
| 16 | "0" |
tbuf_rx_cons_err |
|
|
| 15 - 12 | "0000" |
tbuf_tx_cons |
|
|
| 11 - 8 | "0000" |
tbuf_rx_prod |
|
|
| 7 - 0 | "00000000" |
hsc |
|
|
| sms_tbuf0_prod_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0200 Address@sms_tbuf_tx : 0x601b0400 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf0_prod_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0204 Address@sms_tbuf_tx : 0x601b0404 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf0_prod_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0208 Address@sms_tbuf_tx : 0x601b0408 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf0_prod_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b020c Address@sms_tbuf_tx : 0x601b040c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf0_cons_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0210 Address@sms_tbuf_tx : 0x601b0410 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf0_cons_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0214 Address@sms_tbuf_tx : 0x601b0414 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf0_cons_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0218 Address@sms_tbuf_tx : 0x601b0418 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf0_cons_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b021c Address@sms_tbuf_tx : 0x601b041c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf0_prod_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0220 Address@sms_tbuf_tx : 0x601b0420 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf0_cons_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0224 Address@sms_tbuf_tx : 0x601b0424 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf0_prod_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0228 Address@sms_tbuf_tx : 0x601b0428 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf0_cons_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b022c Address@sms_tbuf_tx : 0x601b042c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf0_prod_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0230 Address@sms_tbuf_tx : 0x601b0430 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf0_cons_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0234 Address@sms_tbuf_tx : 0x601b0434 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf0_trigger |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0238 Address@sms_tbuf_tx : 0x601b0438 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
tgl_cond_en |
|
|
| 16 | "0" |
tgl |
|
|
| 15 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
unlock_cons |
|
|
| 2 | "0" |
unlock_prod |
|
|
| 1 | "0" |
fetch_lock_cons |
|
|
| 0 | "0" |
commit_lock_prod |
|
|
| sms_tbuf0_state |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b023c Address@sms_tbuf_tx : 0x601b043c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
prod_seq_err_mask |
|
|||||||||
| 30 | "0" |
cons_seq_err_mask |
|
|||||||||
| 29 | "0" |
prod_err_mask |
|
|||||||||
| 28 | "0" |
cons_err_mask |
|
|||||||||
| 27 | "0" |
locked_mask |
|
|||||||||
| 26 | "0" |
bal_mask |
|
|||||||||
| 25 | "0" |
cons_idx_mask |
|
|||||||||
| 24 | "0" |
mid_idx_mask |
|
|||||||||
| 23 | "0" |
prod_idx_mask |
|
|||||||||
| 22 | "0" |
bal_latched_mask |
|
|||||||||
| 21 - 19 | "000" |
bal_prod |
|
|||||||||
| 18 - 16 | "000" |
bal_cons |
|
|||||||||
| 15 | "0" |
prod_seq_err |
|
|||||||||
| 14 | "0" |
cons_seq_err |
|
|||||||||
| 13 - 12 | "00" |
cons_idx |
|
|||||||||
| 11 - 10 | "00" |
mid_idx |
|
|||||||||
| 9 - 8 | "00" |
prod_idx |
|
|||||||||
| 7 | "0" |
prod_err |
|
|||||||||
| 6 | "0" |
cons_err |
|
|||||||||
| 5 - 4 | "00" |
locked |
|
|||||||||
| 3 - 1 | "000" |
bal |
|
|||||||||
| 0 | 0 |
- |
reserved | |||||||||
| sms_tbuf0_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0240 Address@sms_tbuf_tx : 0x601b0440 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||||
| 20 | "0" |
cirq_fullover |
|
||||||||
| 19 | "0" |
cirq_unlocked |
|
||||||||
| 18 | "0" |
cirq_en |
|
||||||||
| 17 | "0" |
ceirq_seq_en |
|
||||||||
| 16 | "0" |
ceirq_en |
|
||||||||
| 15 - 13 | 0 |
- |
reserved | ||||||||
| 12 | "0" |
pirq_emptyunder |
|
||||||||
| 11 | "0" |
pirq_unlocked |
|
||||||||
| 10 | "0" |
pirq_en |
|
||||||||
| 9 | "0" |
peirq_seq_en |
|
||||||||
| 8 | "0" |
peirq_en |
|
||||||||
| 7 - 2 | 0 |
- |
reserved | ||||||||
| 1 - 0 | "00" |
buffer_mode |
|
||||||||
| sms_tbuf1_prod_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0244 Address@sms_tbuf_tx : 0x601b0444 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf1_prod_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0248 Address@sms_tbuf_tx : 0x601b0448 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf1_prod_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b024c Address@sms_tbuf_tx : 0x601b044c |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf1_prod_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0250 Address@sms_tbuf_tx : 0x601b0450 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf1_cons_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0254 Address@sms_tbuf_tx : 0x601b0454 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf1_cons_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0258 Address@sms_tbuf_tx : 0x601b0458 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf1_cons_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b025c Address@sms_tbuf_tx : 0x601b045c |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf1_cons_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0260 Address@sms_tbuf_tx : 0x601b0460 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf1_prod_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0264 Address@sms_tbuf_tx : 0x601b0464 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf1_cons_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0268 Address@sms_tbuf_tx : 0x601b0468 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf1_prod_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b026c Address@sms_tbuf_tx : 0x601b046c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf1_cons_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0270 Address@sms_tbuf_tx : 0x601b0470 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf1_prod_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0274 Address@sms_tbuf_tx : 0x601b0474 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf1_cons_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0278 Address@sms_tbuf_tx : 0x601b0478 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf1_trigger |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b027c Address@sms_tbuf_tx : 0x601b047c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
tgl_cond_en |
|
|
| 16 | "0" |
tgl |
|
|
| 15 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
unlock_cons |
|
|
| 2 | "0" |
unlock_prod |
|
|
| 1 | "0" |
fetch_lock_cons |
|
|
| 0 | "0" |
commit_lock_prod |
|
|
| sms_tbuf1_state |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0280 Address@sms_tbuf_tx : 0x601b0480 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
prod_seq_err_mask |
|
|||||||||
| 30 | "0" |
cons_seq_err_mask |
|
|||||||||
| 29 | "0" |
prod_err_mask |
|
|||||||||
| 28 | "0" |
cons_err_mask |
|
|||||||||
| 27 | "0" |
locked_mask |
|
|||||||||
| 26 | "0" |
bal_mask |
|
|||||||||
| 25 | "0" |
cons_idx_mask |
|
|||||||||
| 24 | "0" |
mid_idx_mask |
|
|||||||||
| 23 | "0" |
prod_idx_mask |
|
|||||||||
| 22 | "0" |
bal_latched_mask |
|
|||||||||
| 21 - 19 | "000" |
bal_prod |
|
|||||||||
| 18 - 16 | "000" |
bal_cons |
|
|||||||||
| 15 | "0" |
prod_seq_err |
|
|||||||||
| 14 | "0" |
cons_seq_err |
|
|||||||||
| 13 - 12 | "00" |
cons_idx |
|
|||||||||
| 11 - 10 | "00" |
mid_idx |
|
|||||||||
| 9 - 8 | "00" |
prod_idx |
|
|||||||||
| 7 | "0" |
prod_err |
|
|||||||||
| 6 | "0" |
cons_err |
|
|||||||||
| 5 - 4 | "00" |
locked |
|
|||||||||
| 3 - 1 | "000" |
bal |
|
|||||||||
| 0 | 0 |
- |
reserved | |||||||||
| sms_tbuf1_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0284 Address@sms_tbuf_tx : 0x601b0484 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||||
| 20 | "0" |
cirq_fullover |
|
||||||||
| 19 | "0" |
cirq_unlocked |
|
||||||||
| 18 | "0" |
cirq_en |
|
||||||||
| 17 | "0" |
ceirq_seq_en |
|
||||||||
| 16 | "0" |
ceirq_en |
|
||||||||
| 15 - 13 | 0 |
- |
reserved | ||||||||
| 12 | "0" |
pirq_emptyunder |
|
||||||||
| 11 | "0" |
pirq_unlocked |
|
||||||||
| 10 | "0" |
pirq_en |
|
||||||||
| 9 | "0" |
peirq_seq_en |
|
||||||||
| 8 | "0" |
peirq_en |
|
||||||||
| 7 - 2 | 0 |
- |
reserved | ||||||||
| 1 - 0 | "00" |
buffer_mode |
|
||||||||
| sms_tbuf2_prod_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0288 Address@sms_tbuf_tx : 0x601b0488 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf2_prod_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b028c Address@sms_tbuf_tx : 0x601b048c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf2_prod_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0290 Address@sms_tbuf_tx : 0x601b0490 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf2_prod_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0294 Address@sms_tbuf_tx : 0x601b0494 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf2_cons_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b0298 Address@sms_tbuf_tx : 0x601b0498 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf2_cons_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b029c Address@sms_tbuf_tx : 0x601b049c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf2_cons_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b02a0 Address@sms_tbuf_tx : 0x601b04a0 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf2_cons_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02a4 Address@sms_tbuf_tx : 0x601b04a4 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf2_prod_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02a8 Address@sms_tbuf_tx : 0x601b04a8 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf2_cons_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02ac Address@sms_tbuf_tx : 0x601b04ac |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf2_prod_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02b0 Address@sms_tbuf_tx : 0x601b04b0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf2_cons_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02b4 Address@sms_tbuf_tx : 0x601b04b4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf2_prod_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02b8 Address@sms_tbuf_tx : 0x601b04b8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf2_cons_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02bc Address@sms_tbuf_tx : 0x601b04bc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf2_trigger |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02c0 Address@sms_tbuf_tx : 0x601b04c0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
tgl_cond_en |
|
|
| 16 | "0" |
tgl |
|
|
| 15 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
unlock_cons |
|
|
| 2 | "0" |
unlock_prod |
|
|
| 1 | "0" |
fetch_lock_cons |
|
|
| 0 | "0" |
commit_lock_prod |
|
|
| sms_tbuf2_state |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02c4 Address@sms_tbuf_tx : 0x601b04c4 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
prod_seq_err_mask |
|
|||||||||
| 30 | "0" |
cons_seq_err_mask |
|
|||||||||
| 29 | "0" |
prod_err_mask |
|
|||||||||
| 28 | "0" |
cons_err_mask |
|
|||||||||
| 27 | "0" |
locked_mask |
|
|||||||||
| 26 | "0" |
bal_mask |
|
|||||||||
| 25 | "0" |
cons_idx_mask |
|
|||||||||
| 24 | "0" |
mid_idx_mask |
|
|||||||||
| 23 | "0" |
prod_idx_mask |
|
|||||||||
| 22 | "0" |
bal_latched_mask |
|
|||||||||
| 21 - 19 | "000" |
bal_prod |
|
|||||||||
| 18 - 16 | "000" |
bal_cons |
|
|||||||||
| 15 | "0" |
prod_seq_err |
|
|||||||||
| 14 | "0" |
cons_seq_err |
|
|||||||||
| 13 - 12 | "00" |
cons_idx |
|
|||||||||
| 11 - 10 | "00" |
mid_idx |
|
|||||||||
| 9 - 8 | "00" |
prod_idx |
|
|||||||||
| 7 | "0" |
prod_err |
|
|||||||||
| 6 | "0" |
cons_err |
|
|||||||||
| 5 - 4 | "00" |
locked |
|
|||||||||
| 3 - 1 | "000" |
bal |
|
|||||||||
| 0 | 0 |
- |
reserved | |||||||||
| sms_tbuf2_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02c8 Address@sms_tbuf_tx : 0x601b04c8 |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||||
| 20 | "0" |
cirq_fullover |
|
||||||||
| 19 | "0" |
cirq_unlocked |
|
||||||||
| 18 | "0" |
cirq_en |
|
||||||||
| 17 | "0" |
ceirq_seq_en |
|
||||||||
| 16 | "0" |
ceirq_en |
|
||||||||
| 15 - 13 | 0 |
- |
reserved | ||||||||
| 12 | "0" |
pirq_emptyunder |
|
||||||||
| 11 | "0" |
pirq_unlocked |
|
||||||||
| 10 | "0" |
pirq_en |
|
||||||||
| 9 | "0" |
peirq_seq_en |
|
||||||||
| 8 | "0" |
peirq_en |
|
||||||||
| 7 - 2 | 0 |
- |
reserved | ||||||||
| 1 - 0 | "00" |
buffer_mode |
|
||||||||
| sms_tbuf3_prod_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b02cc Address@sms_tbuf_tx : 0x601b04cc |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf3_prod_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02d0 Address@sms_tbuf_tx : 0x601b04d0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf3_prod_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b02d4 Address@sms_tbuf_tx : 0x601b04d4 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf3_prod_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02d8 Address@sms_tbuf_tx : 0x601b04d8 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf3_cons_start |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b02dc Address@sms_tbuf_tx : 0x601b04dc |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf3_cons_start_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02e0 Address@sms_tbuf_tx : 0x601b04e0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf3_cons_end |
|
|||||||||||||||||||
| R/W |
0x0003fff8 |
Address@sms_tbuf_rx : 0x601b02e4 Address@sms_tbuf_tx : 0x601b04e4 |
Bits | Reset value | Name | Description | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0 |
- |
reserved | |||||||||||||||||
| 21 - 19 | "000" |
overlay_shift |
|
|||||||||||||||||
| 18 | "0" |
overlay_en |
|
|||||||||||||||||
| 17 - 3 | 0x7fff |
adr |
|
|||||||||||||||||
| 2 | 0 |
- |
reserved | |||||||||||||||||
| 1 | "0" |
tgl_mask |
|
|||||||||||||||||
| 0 | "0" |
tgl |
|
|||||||||||||||||
| sms_tbuf3_cons_end_action_cfg |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02e8 Address@sms_tbuf_tx : 0x601b04e8 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 20 | 0 |
- |
reserved | |||||||||
| 19 - 18 | "00" |
read_clears |
|
|||||||||
| 17 - 16 | "00" |
write_clears |
|
|||||||||
| 15 - 14 | "00" |
tgl_clears |
|
|||||||||
| 13 - 12 | "00" |
read_action |
|
|||||||||
| 11 - 10 | "00" |
write_action |
|
|||||||||
| 9 - 8 | "00" |
tgl_action |
|
|||||||||
| 7 - 3 | 0 |
- |
reserved | |||||||||
| 2 - 0 | "000" |
wstrb_sel |
|
|||||||||
| sms_tbuf3_prod_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02ec Address@sms_tbuf_tx : 0x601b04ec |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf3_cons_offset_0 |
|
||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02f0 Address@sms_tbuf_tx : 0x601b04f0 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | ||||||
| 18 - 3 | 0x0 |
adr |
|
||||||
| 2 - 0 | 0 |
- |
reserved | ||||||
| sms_tbuf3_prod_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02f4 Address@sms_tbuf_tx : 0x601b04f4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf3_cons_offset_1 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02f8 Address@sms_tbuf_tx : 0x601b04f8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf3_prod_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b02fc Address@sms_tbuf_tx : 0x601b04fc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf3_cons_offset_2 |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0300 Address@sms_tbuf_tx : 0x601b0500 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 19 | 0 |
- |
reserved | |
| 18 - 3 | 0x0 |
adr |
|
|
| 2 - 0 | 0 |
- |
reserved | |
| sms_tbuf3_trigger |
|
|||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0304 Address@sms_tbuf_tx : 0x601b0504 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
tgl_cond_en |
|
|
| 16 | "0" |
tgl |
|
|
| 15 - 4 | 0 |
- |
reserved | |
| 3 | "0" |
unlock_cons |
|
|
| 2 | "0" |
unlock_prod |
|
|
| 1 | "0" |
fetch_lock_cons |
|
|
| 0 | "0" |
commit_lock_prod |
|
|
| sms_tbuf3_state |
|
|||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b0308 Address@sms_tbuf_tx : 0x601b0508 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
prod_seq_err_mask |
|
|||||||||
| 30 | "0" |
cons_seq_err_mask |
|
|||||||||
| 29 | "0" |
prod_err_mask |
|
|||||||||
| 28 | "0" |
cons_err_mask |
|
|||||||||
| 27 | "0" |
locked_mask |
|
|||||||||
| 26 | "0" |
bal_mask |
|
|||||||||
| 25 | "0" |
cons_idx_mask |
|
|||||||||
| 24 | "0" |
mid_idx_mask |
|
|||||||||
| 23 | "0" |
prod_idx_mask |
|
|||||||||
| 22 | "0" |
bal_latched_mask |
|
|||||||||
| 21 - 19 | "000" |
bal_prod |
|
|||||||||
| 18 - 16 | "000" |
bal_cons |
|
|||||||||
| 15 | "0" |
prod_seq_err |
|
|||||||||
| 14 | "0" |
cons_seq_err |
|
|||||||||
| 13 - 12 | "00" |
cons_idx |
|
|||||||||
| 11 - 10 | "00" |
mid_idx |
|
|||||||||
| 9 - 8 | "00" |
prod_idx |
|
|||||||||
| 7 | "0" |
prod_err |
|
|||||||||
| 6 | "0" |
cons_err |
|
|||||||||
| 5 - 4 | "00" |
locked |
|
|||||||||
| 3 - 1 | "000" |
bal |
|
|||||||||
| 0 | 0 |
- |
reserved | |||||||||
| sms_tbuf3_cfg |
|
||||||||||
| R/W |
0x00000000 |
Address@sms_tbuf_rx : 0x601b030c Address@sms_tbuf_tx : 0x601b050c |
Bits | Reset value | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 21 | 0 |
- |
reserved | ||||||||
| 20 | "0" |
cirq_fullover |
|
||||||||
| 19 | "0" |
cirq_unlocked |
|
||||||||
| 18 | "0" |
cirq_en |
|
||||||||
| 17 | "0" |
ceirq_seq_en |
|
||||||||
| 16 | "0" |
ceirq_en |
|
||||||||
| 15 - 13 | 0 |
- |
reserved | ||||||||
| 12 | "0" |
pirq_emptyunder |
|
||||||||
| 11 | "0" |
pirq_unlocked |
|
||||||||
| 10 | "0" |
pirq_en |
|
||||||||
| 9 | "0" |
peirq_seq_en |
|
||||||||
| 8 | "0" |
peirq_en |
|
||||||||
| 7 - 2 | 0 |
- |
reserved | ||||||||
| 1 - 0 | "00" |
buffer_mode |
|
||||||||
| sms_tbuf_all_state_0 |
|
|||
| R |
Address@sms_tbuf_rx : 0x601b0310 Address@sms_tbuf_tx : 0x601b0510 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 14 | buf3_bal |
|
||
| 13 - 12 | buf3_locked |
|
||
| 11 - 10 | buf2_bal |
|
||
| 9 - 8 | buf2_locked |
|
||
| 7 - 6 | buf1_bal |
|
||
| 5 - 4 | buf1_locked |
|
||
| 3 - 2 | buf0_bal |
|
||
| 1 - 0 | buf0_locked |
|
||
| sms_tbuf_all_state_error_0 |
|
|||
| R |
Address@sms_tbuf_rx : 0x601b0314 Address@sms_tbuf_tx : 0x601b0514 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 | buf3_prod_err |
|
||
| 14 | buf3_cons_err |
|
||
| 13 | buf3_prod_seq_err |
|
||
| 12 | buf3_cons_seq_err |
|
||
| 11 | buf2_prod_err |
|
||
| 10 | buf2_cons_err |
|
||
| 9 | buf2_prod_seq_err |
|
||
| 8 | buf2_cons_seq_err |
|
||
| 7 | buf1_prod_err |
|
||
| 6 | buf1_cons_err |
|
||
| 5 | buf1_prod_seq_err |
|
||
| 4 | buf1_cons_seq_err |
|
||
| 3 | buf0_prod_err |
|
||
| 2 | buf0_cons_err |
|
||
| 1 | buf0_prod_seq_err |
|
||
| 0 | buf0_cons_seq_err |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_tba_mst_0_status |
| 1 | 4 | - | reserved |
| 2 | 8 | R/W | sms_tba_mst_0_action |
| 3 | c | - | reserved |
| 4 | 10 | R/W | sms_tba_mst_0_ctrl |
| 5-3f | 14-fc | - | reserved |
| sms_tba_mst_0_status |
|
||||||||
| R/W |
0x00000024 |
Address : 0x601b0600 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | ||||||
| 15 | "0" |
master_is_consumer |
|
||||||
| 14 - 12 | "000" |
bal_pre_slave |
|
||||||
| 11 - 9 | "000" |
bal_pre_master |
|
||||||
| 8 - 6 | "000" |
bal |
|
||||||
| 5 - 4 | "10" |
slave_idx |
|
||||||
| 3 - 2 | "01" |
mid_idx |
|
||||||
| 1 - 0 | "00" |
master_idx |
|
||||||
| sms_tba_mst_0_action |
|
|||
| R/W |
0x00000000 |
Address : 0x601b0608 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
tgl_slave |
|
|
| 0 | "0" |
tgl_master |
|
|
| sms_tba_mst_0_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x601b0610 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
slv_irq_en |
|
|
| 0 | "0" |
mst_irq_en |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | sms_device_cfg_sync_src_sel |
| 1 | 4 | R/W | sms_device_cfg_host_capability |
| 2-3 | 8-c | - | reserved |
| sms_device_cfg_sync_src_sel |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x601b0700 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |||||||||
| 7 - 6 | "00" |
sel_3 |
|
|||||||||
| 5 - 4 | "00" |
sel_2 |
|
|||||||||
| 3 - 2 | "00" |
sel_1 |
|
|||||||||
| 1 - 0 | "00" |
sel_0 |
|
|||||||||
| sms_device_cfg_host_capability |
|
|||
| R/W |
0x00000000 |
Address : 0x601b0704 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
reset_excl_pcie |
|
|
| 0 | "0" |
reset |
|
|
| gen_ram_ctrl_netx22xx_0_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c100c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c101c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_mbist_power8 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c1020 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_0_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c180c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc4 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc5 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc6 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc7 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c181c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc8 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1820 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_0_ecc_status_corr0 |
|
|||
| R |
Address : 0x601c1a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr1 |
|
|||
| R |
Address : 0x601c1a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr2 |
|
|||
| R |
Address : 0x601c1a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr3 |
|
|||
| R |
Address : 0x601c1a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr4 |
|
|||
| R |
Address : 0x601c1a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr5 |
|
|||
| R |
Address : 0x601c1a14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr6 |
|
|||
| R |
Address : 0x601c1a18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr7 |
|
|||
| R |
Address : 0x601c1a1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_corr8 |
|
|||
| R |
Address : 0x601c1a20 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x601c1c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr1 |
|
|||
| R |
Address : 0x601c1c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr2 |
|
|||
| R |
Address : 0x601c1c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr3 |
|
|||
| R |
Address : 0x601c1c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr4 |
|
|||
| R |
Address : 0x601c1c10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr5 |
|
|||
| R |
Address : 0x601c1c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr6 |
|
|||
| R |
Address : 0x601c1c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr7 |
|
|||
| R |
Address : 0x601c1c1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_ecc_status_noncorr8 |
|
|||
| R |
Address : 0x601c1c20 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_0_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_8_err_ecc_correctable |
|
|
| 16 | "0" |
mem_7_err_ecc_correctable |
|
|
| 15 | "0" |
mem_6_err_ecc_correctable |
|
|
| 14 | "0" |
mem_5_err_ecc_correctable |
|
|
| 13 | "0" |
mem_4_err_ecc_correctable |
|
|
| 12 | "0" |
mem_3_err_ecc_correctable |
|
|
| 11 | "0" |
mem_2_err_ecc_correctable |
|
|
| 10 | "0" |
mem_1_err_ecc_correctable |
|
|
| 9 | "0" |
mem_0_err_ecc_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_0_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_8_err_ecc_correctable |
|
|
| 16 | "0" |
mem_7_err_ecc_correctable |
|
|
| 15 | "0" |
mem_6_err_ecc_correctable |
|
|
| 14 | "0" |
mem_5_err_ecc_correctable |
|
|
| 13 | "0" |
mem_4_err_ecc_correctable |
|
|
| 12 | "0" |
mem_3_err_ecc_correctable |
|
|
| 11 | "0" |
mem_2_err_ecc_correctable |
|
|
| 10 | "0" |
mem_1_err_ecc_correctable |
|
|
| 9 | "0" |
mem_0_err_ecc_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_0_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c1e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |
| 26 | "0" |
mem_8_mbist_or_init_finished |
|
|
| 25 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 24 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 23 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_8_err_ecc_correctable |
|
|
| 16 | "0" |
mem_7_err_ecc_correctable |
|
|
| 15 | "0" |
mem_6_err_ecc_correctable |
|
|
| 14 | "0" |
mem_5_err_ecc_correctable |
|
|
| 13 | "0" |
mem_4_err_ecc_correctable |
|
|
| 12 | "0" |
mem_3_err_ecc_correctable |
|
|
| 11 | "0" |
mem_2_err_ecc_correctable |
|
|
| 10 | "0" |
mem_1_err_ecc_correctable |
|
|
| 9 | "0" |
mem_0_err_ecc_correctable |
|
|
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_0_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601c1ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 27 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
mem_8_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_8_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_7_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_6_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_5_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_4_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_8_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_netx22xx_0_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x601c1efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| gen_ram_ctrl_netx22xx_1_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c200c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c2018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c201c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_1_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c280c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc4 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc5 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc6 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc7 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c281c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_1_ecc_status_corr0 |
|
|||
| R |
Address : 0x601c2a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr1 |
|
|||
| R |
Address : 0x601c2a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr2 |
|
|||
| R |
Address : 0x601c2a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr3 |
|
|||
| R |
Address : 0x601c2a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr4 |
|
|||
| R |
Address : 0x601c2a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr5 |
|
|||
| R |
Address : 0x601c2a14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr6 |
|
|||
| R |
Address : 0x601c2a18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_corr7 |
|
|||
| R |
Address : 0x601c2a1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x601c2c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr1 |
|
|||
| R |
Address : 0x601c2c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr2 |
|
|||
| R |
Address : 0x601c2c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr3 |
|
|||
| R |
Address : 0x601c2c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr4 |
|
|||
| R |
Address : 0x601c2c10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr5 |
|
|||
| R |
Address : 0x601c2c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr6 |
|
|||
| R |
Address : 0x601c2c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_ecc_status_noncorr7 |
|
|||
| R |
Address : 0x601c2c1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_1_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_1_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_1_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c2e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_1_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601c2ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_netx22xx_1_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x601c2efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| gen_ram_ctrl_netx22xx_2_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c300c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c3018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c301c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_2_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c380c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc4 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc5 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc6 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc7 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c381c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_2_ecc_status_corr0 |
|
|||
| R |
Address : 0x601c3a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr1 |
|
|||
| R |
Address : 0x601c3a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr2 |
|
|||
| R |
Address : 0x601c3a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr3 |
|
|||
| R |
Address : 0x601c3a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr4 |
|
|||
| R |
Address : 0x601c3a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr5 |
|
|||
| R |
Address : 0x601c3a14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr6 |
|
|||
| R |
Address : 0x601c3a18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_corr7 |
|
|||
| R |
Address : 0x601c3a1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x601c3c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr1 |
|
|||
| R |
Address : 0x601c3c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr2 |
|
|||
| R |
Address : 0x601c3c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr3 |
|
|||
| R |
Address : 0x601c3c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr4 |
|
|||
| R |
Address : 0x601c3c10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr5 |
|
|||
| R |
Address : 0x601c3c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr6 |
|
|||
| R |
Address : 0x601c3c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_ecc_status_noncorr7 |
|
|||
| R |
Address : 0x601c3c1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_2_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_2_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_2_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c3e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_2_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601c3ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_netx22xx_2_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x601c3efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| gen_ram_ctrl_netx22xx_3_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power1 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4004 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power2 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4008 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power3 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c400c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power4 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4010 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power5 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4014 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power6 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c4018 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_mbist_power7 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x601c401c |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_netx22xx_3_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc1 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4804 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc2 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4808 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc3 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c480c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc4 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4810 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc5 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4814 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc6 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4818 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc7 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c481c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_netx22xx_3_ecc_status_corr0 |
|
|||
| R |
Address : 0x601c4a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr1 |
|
|||
| R |
Address : 0x601c4a04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr2 |
|
|||
| R |
Address : 0x601c4a08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr3 |
|
|||
| R |
Address : 0x601c4a0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr4 |
|
|||
| R |
Address : 0x601c4a10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr5 |
|
|||
| R |
Address : 0x601c4a14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr6 |
|
|||
| R |
Address : 0x601c4a18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_corr7 |
|
|||
| R |
Address : 0x601c4a1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x601c4c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr1 |
|
|||
| R |
Address : 0x601c4c04 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr2 |
|
|||
| R |
Address : 0x601c4c08 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr3 |
|
|||
| R |
Address : 0x601c4c0c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr4 |
|
|||
| R |
Address : 0x601c4c10 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr5 |
|
|||
| R |
Address : 0x601c4c14 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr6 |
|
|||
| R |
Address : 0x601c4c18 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_ecc_status_noncorr7 |
|
|||
| R |
Address : 0x601c4c1c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_netx22xx_3_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_3_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_3_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x601c4e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_netx22xx_3_irq_mask_rst_reg0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address : 0x601c4ec0 |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 24 | 0 |
- |
reserved | |||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
mem_7_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
mem_6_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
mem_5_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
mem_4_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
mem_3_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
mem_2_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
mem_1_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
mem_7_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
mem_6_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
mem_5_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
mem_4_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
mem_3_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
mem_2_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
mem_1_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
mem_7_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
mem_6_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
mem_5_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
mem_4_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
mem_3_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
mem_2_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
mem_1_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||
| gen_ram_ctrl_netx22xx_3_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x601c4efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | pcie_msi2irq_msg |
| 1-3 | 4-c | - | reserved |
| pcie_msi2irq_msg |
|
|||
| R/W |
0x00000000 |
Address@msi2irq_0 : 0x68000000 Address@msi2irq_1 : 0x68000010 Address@msi2irq_2 : 0x68000020 Address@msi2irq_3 : 0x68000030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
msg |
|
|
| pcie_link0_sw_reset |
|
|||
| R/W |
0x00000000 |
Address : 0x68020000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
link0_pm_sw_reset_n |
|
|
| 7 | "0" |
link0_mgmt_sw_reset_n |
|
|
| 6 | "0" |
link0_mgmt_sticky_sw_reset_n |
|
|
| 5 | "0" |
link0_axi_sw_reset_n |
|
|
| 4 | "0" |
link0_sw_reset_n |
|
|
| 3 | "0" |
link0_pipe_sw_reset_n |
|
|
| 2 | "0" |
phy_pipe_sw_reset_n |
|
|
| 1 | "0" |
phy_apb_sw_reset_n |
|
|
| 0 | "0" |
link0_apb_sw_reset_n |
|
|
| pcie_link0_credit_availability_status |
|
|||
| R |
Address : 0x68020004 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 | link0_npd_credit_avail7 |
|
||
| 30 | link0_nph_credit_avail7 |
|
||
| 29 | link0_pd_credit_avail7 |
|
||
| 28 | link0_ph_credit_avail7 |
|
||
| 27 | link0_npd_credit_avail6 |
|
||
| 26 | link0_nph_credit_avail6 |
|
||
| 25 | link0_pd_credit_avail6 |
|
||
| 24 | link0_ph_credit_avail6 |
|
||
| 23 | link0_npd_credit_avail5 |
|
||
| 22 | link0_nph_credit_avail5 |
|
||
| 21 | link0_pd_credit_avail5 |
|
||
| 20 | link0_ph_credit_avail5 |
|
||
| 19 | link0_npd_credit_avail4 |
|
||
| 18 | link0_nph_credit_avail4 |
|
||
| 17 | link0_pd_credit_avail4 |
|
||
| 16 | link0_ph_credit_avail4 |
|
||
| 15 | link0_npd_credit_avail3 |
|
||
| 14 | link0_nph_credit_avail3 |
|
||
| 13 | link0_pd_credit_avail3 |
|
||
| 12 | link0_ph_credit_avail3 |
|
||
| 11 | link0_npd_credit_avail2 |
|
||
| 10 | link0_nph_credit_avail2 |
|
||
| 9 | link0_pd_credit_avail2 |
|
||
| 8 | link0_ph_credit_avail2 |
|
||
| 7 | link0_npd_credit_avail1 |
|
||
| 6 | link0_nph_credit_avail1 |
|
||
| 5 | link0_pd_credit_avail1 |
|
||
| 4 | link0_ph_credit_avail1 |
|
||
| 3 | link0_npd_credit_avail0 |
|
||
| 2 | link0_nph_credit_avail0 |
|
||
| 1 | link0_pd_credit_avail0 |
|
||
| 0 | link0_ph_credit_avail0 |
|
||
| pcie_link0_config |
|
||||||||
| R/W |
0x00000000 |
Address : 0x68020008 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||
| 12 | "0" |
force_power_state_change_ack |
|
||||||
| 11 - 9 | "000" |
vc_count |
|
||||||
| 8 | "0" |
core_clk_shutoff_detect_en |
|
||||||
| 7 - 3 | "00000" |
apb_core_clk_ratio |
|
||||||
| 2 | "0" |
sris_enable |
|
||||||
| 1 | "0" |
mode_select |
|
||||||
| 0 | "0" |
pcie_generation_sel |
|
||||||
| pcie_link0_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6802000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 | "0" |
clear_link_down_bit |
|
|
| 6 | "0" |
client_req_exit_l1_substate |
|
|
| 5 | "0" |
pcie_target_non_posted_rej |
|
|
| 4 | "0" |
client_req_exit_l1 |
|
|
| 3 | "0" |
req_pm_transition_l23_ready |
|
|
| 2 | "0" |
link_training_enable |
|
|
| 1 | "0" |
client_req_exit_l2 |
|
|
| 0 | "0" |
config_enable |
|
|
| pcie_link0_config_info |
|
||||||||||||
| R |
Address : 0x68020010 |
Bits | Name | Description | |||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 30 | - |
reserved | |||||||||||
| 29 | link0_ltr_mechanism_enable |
|
|||||||||||
| 28 - 26 | link0_tph_st_mode |
|
|||||||||||
| 25 | link0_tph_requester_enable |
|
|||||||||||
| 24 - 23 | link0_obff_enable |
|
|||||||||||
| 22 | link0_rcb_status |
|
|||||||||||
| 21 - 19 | link0_max_payload_size |
|
|||||||||||
| 18 - 16 | link0_max_read_req_size |
|
|||||||||||
| 15 - 13 | - |
reserved | |||||||||||
| 12 - 10 | link0_function_power_state |
|
|||||||||||
| 9 - 6 | link0_function_status |
|
|||||||||||
| 5 | link0_negotiated_speed |
|
|||||||||||
| 4 | - |
reserved | |||||||||||
| 3 - 2 | link0_link_status |
|
|||||||||||
| 1 | link0_core_clk_shutoff |
|
|||||||||||
| 0 | - |
reserved | |||||||||||
| pcie_link0_vendor_specific_capability |
|
|||
| R/W |
0x00000000 |
Address : 0x68020014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
link0_set_f0_vsec_control |
|
|
| pcie_link0_vendor_specific_capability_info |
|
|||
| R |
Address : 0x68020018 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 23 | - |
reserved | ||
| 22 - 0 | link0_get_f0_vsec_control |
|
||
| pcie_link0_debug |
|
||||||||||||||||||||
| R |
Address : 0x6802001c |
Bits | Name | Description | |||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 9 | - |
reserved | |||||||||||||||||||
| 8 - 6 | link0_l1_pm_substate_out |
|
|||||||||||||||||||
| 5 - 0 | link0_ltssm_state |
|
|||||||||||||||||||
| pcie_link0_debug_1 |
|
|||||||||||
| R |
Address : 0x68020020 |
Bits | Name | Description | ||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | link0_ltssm_transition_cause_data |
|
||||||||||
| pcie_link0_irq_state |
|
|||
| R |
Address : 0x68020024 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 10 | - |
reserved | ||
| 9 | link0_msg_sb_fifo_overflow |
|
||
| 8 | link0_msg_sb_fifo_not_empty |
|
||
| 7 | link0_reg_access_clk_shutoff |
|
||
| 6 | link0_power_state_change |
|
||
| 5 | link0_correctable_error |
|
||
| 4 | link0_non_fatal_error |
|
||
| 3 | link0_fatal_error |
|
||
| 2 | link0_link_down_reset |
|
||
| 1 | link0_hot_reset |
|
||
| 0 | link0_msi_enabled |
|
||
| pcie_link0_irq_clear |
|
|||
| W |
0x00000000 |
Address : 0x68020028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
link0_msg_sb_fifo_overflow_ack |
|
|
| 8 | 0 |
- |
reserved | |
| 7 | "0" |
link0_reg_access_clk_shutoff_ack |
|
|
| 6 | "0" |
link0_power_state_change_ack |
|
|
| 5 | "0" |
link0_correctable_error_ack |
|
|
| 4 | "0" |
link0_non_fatal_error_ack |
|
|
| 3 | "0" |
link0_fatal_error_ack |
|
|
| 2 | "0" |
link0_link_down_reset_ack |
|
|
| 1 | "0" |
link0_hot_reset_ack |
|
|
| 0 | "0" |
link0_msi_enabled_ack |
|
|
| pcie_link0_irq_set |
|
|||
| W |
0x00000000 |
Address : 0x6802002c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
link0_msg_sb_fifo_overflow_set |
|
|
| 8 | 0 |
- |
reserved | |
| 7 | "0" |
link0_reg_access_clk_shutoff_set |
|
|
| 6 | 0 |
- |
reserved | |
| 5 | "0" |
link0_correctable_error_set |
|
|
| 4 | "0" |
link0_non_fatal_error_set |
|
|
| 3 | "0" |
link0_fatal_error_set |
|
|
| 2 | "0" |
link0_link_down_reset_set |
|
|
| 1 | "0" |
link0_hot_reset_set |
|
|
| 0 | "0" |
link0_msi_enabled_set |
|
|
| pcie_link0_irq_mask |
|
|||
| R/W |
0x00000040 |
Address : 0x68020030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
link0_msg_sb_fifo_overflow_mask |
|
|
| 8 | "0" |
link0_msg_sb_fifo_not_empty_mask |
|
|
| 7 | "0" |
link0_reg_access_clk_shutoff_mask |
|
|
| 6 | "1" |
link0_power_state_change_mask |
|
|
| 5 | "0" |
link0_correctable_error_mask |
|
|
| 4 | "0" |
link0_non_fatal_error_mask |
|
|
| 3 | "0" |
link0_fatal_error_mask |
|
|
| 2 | "0" |
link0_link_down_reset_mask |
|
|
| 1 | "0" |
link0_hot_reset_mask |
|
|
| 0 | "0" |
link0_msi_enabled_mask |
|
|
| pcie_link0_issue_error |
|
|||
| W |
0x00000000 |
Address : 0x68020034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
link0_uncorrectable_error_in |
|
|
| 0 | "0" |
link0_correctable_error_in |
|
|
| pcie_link0_legacy_irq_mask |
|
|||
| R/W |
0x00000000 |
Address : 0x68020038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
link0_inta_in_mask |
|
|
| pcie_link0_msg_config |
|
|||
| R/W |
0x00000001 |
Address : 0x6802003c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 2 | "000000" |
link0_msg_vdh_max_data |
|
|
| 1 | 0 |
- |
reserved | |
| 0 | "1" |
link0_msg_fifo_enable |
|
|
| pcie_link0_msg_status |
|
|||
| R |
Address : 0x68020040 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 8 | link0_msg_data_fifo_level |
|
||
| 7 | - |
reserved | ||
| 6 - 0 | link0_msg_sb_fifo_level |
|
||
| pcie_link0_msg_fifo |
|
|||
| R |
Address : 0x68020044 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | link0_msg_data |
|
||
| pcie_link0_msg_sideband |
|
||||||||||||||||||
| R |
Address : 0x68020048 |
Bits | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | link0_msg_sb |
|
|||||||||||||||||
| pcie_pipe_pma0 |
|
|||||||||||
| R/W |
0x00000003 |
Address : 0x6802004c |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
pma_cmn_ext_refclk_detected_cfg |
|
|||||||||
| 1 - 0 | "11" |
pma_cmn_refclk_sel |
|
|||||||||
| pcie_pipe_pma0_info |
|
||||||||
| R |
Address : 0x68020050 |
Bits | Name | Description | |||||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 12 | - |
reserved | |||||||
| 11 | pma_cmn_ext_refclk_detected_valid |
|
|||||||
| 10 | pma_cmn_ext_refclk_detected |
|
|||||||
| 9 | pma_cmn_ready |
|
|||||||
| 8 | pma_cmn_macro_suspend_ack |
|
|||||||
| 7 - 2 | - |
reserved | |||||||
| 1 | link0_clock_stable |
|
|||||||
| 0 | pipe_rate0 |
|
|||||||
| pcie_link0_hot_reset |
|
|||
| R/W |
0x00000000 |
Address : 0x68020054 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 1 | 0 |
- |
reserved | |
| 0 | "0" |
link0_set_hot_reset |
|
|
| pcie_link0_perf_mask_0 |
|
|||
| R/W |
0x00000000 |
Address : 0x68020058 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 0 | 0x0 |
link0_perf_data_mask_0 |
|
|
| pcie_link0_perf_mask_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x6802005c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 0 | 0x0 |
link0_perf_data_mask_1 |
|
|
| pcie_link0_perf_mask_2 |
|
|||
| R/W |
0x00000000 |
Address : 0x68020060 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 0 | 0x0 |
link0_perf_data_mask_2 |
|
|
| pcie_link0_perf_mask_3 |
|
|||
| R/W |
0x00000000 |
Address : 0x68020064 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 18 | 0 |
- |
reserved | |
| 17 - 0 | 0x0 |
link0_perf_data_mask_3 |
|
|
| pcie_link0_perf_strobe |
|
|||
| W |
0x00000000 |
Address : 0x68020068 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 4 | 0 |
- |
reserved | |
| 3 - 0 | "0000" |
link0_perf_strobe |
|
|
| pcie_link_perf_cnt_0 |
|
|||
| R |
Address : 0x6802006c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | link0_perf_cnt_0 |
|
||
| pcie_link_perf_cnt_1 |
|
|||
| R |
Address : 0x68020070 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | link0_perf_cnt_1 |
|
||
| pcie_link_perf_cnt_2 |
|
|||
| R |
Address : 0x68020074 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | link0_perf_cnt_2 |
|
||
| pcie_link_perf_cnt_3 |
|
|||
| R |
Address : 0x68020078 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | link0_perf_cnt_3 |
|
||
| pcie_ram_sleep_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x68020100 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
dma_table_ram |
|
|
| 23 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
pcie_msg_sb_ram |
|
|
| 16 | "0" |
pcie_msg_data_ram |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
axi_dma_outbound_buffer_dpram |
|
|
| 8 | "0" |
axi_dma_inbound_buffer_dpram |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
axi_master_rfifo |
|
|
| 5 | "0" |
axi_slv_fifo |
|
|
| 4 | "0" |
sc_fifo |
|
|
| 3 | "0" |
pnp_fifo |
|
|
| 2 | "0" |
axi_slv_rd_reorder |
|
|
| 1 | "0" |
axi_interleaving_sram |
|
|
| 0 | "0" |
replay_buffer |
|
|
| pcie_ram_shutdown_ctrl |
|
|||
| R/W |
0x0103037f |
Address : 0x68020104 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "1" |
dma_table_ram |
|
|
| 23 - 18 | 0 |
- |
reserved | |
| 17 | "1" |
pcie_msg_sb_ram |
|
|
| 16 | "1" |
pcie_msg_data_ram |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "1" |
axi_dma_outbound_buffer_dpram |
|
|
| 8 | "1" |
axi_dma_inbound_buffer_dpram |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
axi_master_rfifo |
|
|
| 5 | "1" |
axi_slv_fifo |
|
|
| 4 | "1" |
sc_fifo |
|
|
| 3 | "1" |
pnp_fifo |
|
|
| 2 | "1" |
axi_slv_rd_reorder |
|
|
| 1 | "1" |
axi_interleaving_sram |
|
|
| 0 | "1" |
replay_buffer |
|
|
| pcie_ram_disable_ctrl |
|
|||
| R/W |
0x0103037f |
Address : 0x68020108 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "1" |
dma_table_ram |
|
|
| 23 - 18 | 0 |
- |
reserved | |
| 17 | "1" |
pcie_msg_sb_ram |
|
|
| 16 | "1" |
pcie_msg_data_ram |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "1" |
axi_dma_outbound_buffer_dpram |
|
|
| 8 | "1" |
axi_dma_inbound_buffer_dpram |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "1" |
axi_master_rfifo |
|
|
| 5 | "1" |
axi_slv_fifo |
|
|
| 4 | "1" |
sc_fifo |
|
|
| 3 | "1" |
pnp_fifo |
|
|
| 2 | "1" |
axi_slv_rd_reorder |
|
|
| 1 | "1" |
axi_interleaving_sram |
|
|
| 0 | "1" |
replay_buffer |
|
|
| pcie_ram_autosleep_ctrl_mask |
|
|||
| R/W |
0x00000000 |
Address : 0x6802010c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | "0" |
dma_table_ram |
|
|
| 23 - 18 | 0 |
- |
reserved | |
| 17 | "0" |
pcie_msg_sb_ram |
|
|
| 16 | "0" |
pcie_msg_data_ram |
|
|
| 15 - 10 | 0 |
- |
reserved | |
| 9 | "0" |
axi_dma_outbound_buffer_dpram |
|
|
| 8 | "0" |
axi_dma_inbound_buffer_dpram |
|
|
| 7 | 0 |
- |
reserved | |
| 6 | "0" |
axi_master_rfifo |
|
|
| 5 | "0" |
axi_slv_fifo |
|
|
| 4 | "0" |
sc_fifo |
|
|
| 3 | "0" |
pnp_fifo |
|
|
| 2 | "0" |
axi_slv_rd_reorder |
|
|
| 1 | "0" |
axi_interleaving_sram |
|
|
| 0 | "0" |
replay_buffer |
|
|
| pcie_ram_autosleep_ctrl |
|
||||||||
| R/W |
0x00000000 |
Address : 0x68020110 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
sleep_synced |
|
||||||
| 30 - 24 | 0 |
- |
reserved | ||||||
| 23 - 16 | "00000000" |
propagate_sleep_ticks |
|
||||||
| 15 - 11 | "00000" |
disable_ticks |
|
||||||
| 10 - 2 | 0 |
- |
reserved | ||||||
| 1 | "0" |
invert_polarity |
|
||||||
| 0 | "0" |
enable_autosleep |
|
||||||
| pcie_ram_ctrl_shutdown_timing |
|
|||
| R/W |
0x00000000 |
Address : 0x68020114 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
shutdown_synced |
|
|
| 30 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
propagate_shutdown_ticks |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | pcie_irq2msi_msi_addr |
| 1 | 4 | R/W | pcie_irq2msi_msi_data |
| 2 | 8 | R/W | pcie_irq2msi_cfg |
| 3 | c | R | pcie_irq2msi_axi_state |
| pcie_irq2msi_msi_addr |
|
|||
| R/W |
0x00000000 |
Address : 0x68030000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
addr |
|
|
| pcie_irq2msi_msi_data |
|
|||
| R/W |
0x00000000 |
Address : 0x68030004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
data |
|
|
| pcie_irq2msi_cfg |
|
|||
| R/W |
0x00000000 |
Address : 0x68030008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 9 | 0 |
- |
reserved | |
| 8 | "0" |
ack_resp |
|
|
| 7 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
auto_disable |
|
|
| 0 | "0" |
enable |
|
|
| pcie_irq2msi_axi_state |
|
|||
| R |
Address : 0x6803000c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 | resp_valid |
|
||
| 6 - 2 | resp_id |
|
||
| 1 - 0 | resp |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | pcie_msi2irq_cfg_irq_raw |
| 1 | 4 | R/W | pcie_msi2irq_cfg_irq_masked |
| 2 | 8 | R/W | pcie_msi2irq_cfg_irq_mask_set |
| 3 | c | R/W | pcie_msi2irq_cfg_irq_mask_rst |
| 4 | 10 | R/W | pcie_msi2irq_cfg_data_mask |
| 5 | 14 | R | pcie_msi2irq_cfg_last_msg |
| 6-7 | 18-1c | - | reserved |
| pcie_msi2irq_cfg_irq_raw |
|
|||
| R/W |
0x00000000 |
Address@msi2irq_0_cfg : 0x68030020 Address@msi2irq_1_cfg : 0x68030040 Address@msi2irq_2_cfg : 0x68030060 Address@msi2irq_3_cfg : 0x68030080 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
irq31 |
|
|
| 30 | "0" |
irq30 |
|
|
| 29 | "0" |
irq29 |
|
|
| 28 | "0" |
irq28 |
|
|
| 27 | "0" |
irq27 |
|
|
| 26 | "0" |
irq26 |
|
|
| 25 | "0" |
irq25 |
|
|
| 24 | "0" |
irq24 |
|
|
| 23 | "0" |
irq23 |
|
|
| 22 | "0" |
irq22 |
|
|
| 21 | "0" |
irq21 |
|
|
| 20 | "0" |
irq20 |
|
|
| 19 | "0" |
irq19 |
|
|
| 18 | "0" |
irq18 |
|
|
| 17 | "0" |
irq17 |
|
|
| 16 | "0" |
irq16 |
|
|
| 15 | "0" |
irq15 |
|
|
| 14 | "0" |
irq14 |
|
|
| 13 | "0" |
irq13 |
|
|
| 12 | "0" |
irq12 |
|
|
| 11 | "0" |
irq11 |
|
|
| 10 | "0" |
irq10 |
|
|
| 9 | "0" |
irq9 |
|
|
| 8 | "0" |
irq8 |
|
|
| 7 | "0" |
irq7 |
|
|
| 6 | "0" |
irq6 |
|
|
| 5 | "0" |
irq5 |
|
|
| 4 | "0" |
irq4 |
|
|
| 3 | "0" |
irq3 |
|
|
| 2 | "0" |
irq2 |
|
|
| 1 | "0" |
irq1 |
|
|
| 0 | "0" |
irq0 |
|
|
| pcie_msi2irq_cfg_irq_masked |
|
|||
| R/W |
0x00000000 |
Address@msi2irq_0_cfg : 0x68030024 Address@msi2irq_1_cfg : 0x68030044 Address@msi2irq_2_cfg : 0x68030064 Address@msi2irq_3_cfg : 0x68030084 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
irq31 |
|
|
| 30 | "0" |
irq30 |
|
|
| 29 | "0" |
irq29 |
|
|
| 28 | "0" |
irq28 |
|
|
| 27 | "0" |
irq27 |
|
|
| 26 | "0" |
irq26 |
|
|
| 25 | "0" |
irq25 |
|
|
| 24 | "0" |
irq24 |
|
|
| 23 | "0" |
irq23 |
|
|
| 22 | "0" |
irq22 |
|
|
| 21 | "0" |
irq21 |
|
|
| 20 | "0" |
irq20 |
|
|
| 19 | "0" |
irq19 |
|
|
| 18 | "0" |
irq18 |
|
|
| 17 | "0" |
irq17 |
|
|
| 16 | "0" |
irq16 |
|
|
| 15 | "0" |
irq15 |
|
|
| 14 | "0" |
irq14 |
|
|
| 13 | "0" |
irq13 |
|
|
| 12 | "0" |
irq12 |
|
|
| 11 | "0" |
irq11 |
|
|
| 10 | "0" |
irq10 |
|
|
| 9 | "0" |
irq9 |
|
|
| 8 | "0" |
irq8 |
|
|
| 7 | "0" |
irq7 |
|
|
| 6 | "0" |
irq6 |
|
|
| 5 | "0" |
irq5 |
|
|
| 4 | "0" |
irq4 |
|
|
| 3 | "0" |
irq3 |
|
|
| 2 | "0" |
irq2 |
|
|
| 1 | "0" |
irq1 |
|
|
| 0 | "0" |
irq0 |
|
|
| pcie_msi2irq_cfg_irq_mask_set |
|
|||
| R/W |
0x00000000 |
Address@msi2irq_0_cfg : 0x68030028 Address@msi2irq_1_cfg : 0x68030048 Address@msi2irq_2_cfg : 0x68030068 Address@msi2irq_3_cfg : 0x68030088 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
irq31 |
|
|
| 30 | "0" |
irq30 |
|
|
| 29 | "0" |
irq29 |
|
|
| 28 | "0" |
irq28 |
|
|
| 27 | "0" |
irq27 |
|
|
| 26 | "0" |
irq26 |
|
|
| 25 | "0" |
irq25 |
|
|
| 24 | "0" |
irq24 |
|
|
| 23 | "0" |
irq23 |
|
|
| 22 | "0" |
irq22 |
|
|
| 21 | "0" |
irq21 |
|
|
| 20 | "0" |
irq20 |
|
|
| 19 | "0" |
irq19 |
|
|
| 18 | "0" |
irq18 |
|
|
| 17 | "0" |
irq17 |
|
|
| 16 | "0" |
irq16 |
|
|
| 15 | "0" |
irq15 |
|
|
| 14 | "0" |
irq14 |
|
|
| 13 | "0" |
irq13 |
|
|
| 12 | "0" |
irq12 |
|
|
| 11 | "0" |
irq11 |
|
|
| 10 | "0" |
irq10 |
|
|
| 9 | "0" |
irq9 |
|
|
| 8 | "0" |
irq8 |
|
|
| 7 | "0" |
irq7 |
|
|
| 6 | "0" |
irq6 |
|
|
| 5 | "0" |
irq5 |
|
|
| 4 | "0" |
irq4 |
|
|
| 3 | "0" |
irq3 |
|
|
| 2 | "0" |
irq2 |
|
|
| 1 | "0" |
irq1 |
|
|
| 0 | "0" |
irq0 |
|
|
| pcie_msi2irq_cfg_irq_mask_rst |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| R/W |
0x00000000 |
Address@msi2irq_0_cfg : 0x6803002c Address@msi2irq_1_cfg : 0x6803004c Address@msi2irq_2_cfg : 0x6803006c Address@msi2irq_3_cfg : 0x6803008c |
Bits | Reset value | Name | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
irq31 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 30 | "0" |
irq30 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 29 | "0" |
irq29 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 28 | "0" |
irq28 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 27 | "0" |
irq27 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 26 | "0" |
irq26 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 25 | "0" |
irq25 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 24 | "0" |
irq24 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 23 | "0" |
irq23 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 22 | "0" |
irq22 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 21 | "0" |
irq21 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 20 | "0" |
irq20 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 19 | "0" |
irq19 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 18 | "0" |
irq18 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 17 | "0" |
irq17 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 16 | "0" |
irq16 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 15 | "0" |
irq15 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 14 | "0" |
irq14 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 13 | "0" |
irq13 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 12 | "0" |
irq12 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 11 | "0" |
irq11 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 10 | "0" |
irq10 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 9 | "0" |
irq9 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 8 | "0" |
irq8 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 7 | "0" |
irq7 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 6 | "0" |
irq6 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 5 | "0" |
irq5 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 4 | "0" |
irq4 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 3 | "0" |
irq3 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 2 | "0" |
irq2 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 1 | "0" |
irq1 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| 0 | "0" |
irq0 |
|
|||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
| pcie_msi2irq_cfg_data_mask |
|
|||
| R/W |
0x00000000 |
Address@msi2irq_0_cfg : 0x68030030 Address@msi2irq_1_cfg : 0x68030050 Address@msi2irq_2_cfg : 0x68030070 Address@msi2irq_3_cfg : 0x68030090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0x0 |
data |
|
|
| 15 - 0 | 0x0 |
msk |
|
|
| pcie_msi2irq_cfg_last_msg |
|
|||
| R |
Address@msi2irq_0_cfg : 0x68030034 Address@msi2irq_1_cfg : 0x68030054 Address@msi2irq_2_cfg : 0x68030074 Address@msi2irq_3_cfg : 0x68030094 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | msg |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | pcie_ep_cfg_id |
| 1 | 4 | R/W | pcie_ep_cfg_command_status |
| 2 | 8 | - | pcie_ep_cfg_revision_id_class_code |
| 3 | c | - | pcie_ep_cfg_bist_header_latency_cache_line |
| 4 | 10 | R/W | pcie_ep_cfg_base_addr_0 |
| 5 | 14 | R/W | pcie_ep_cfg_base_addr_1 |
| 6-23 | 18-8c | - | reserved |
| 24 | 90 | R/W | pcie_ep_cfg_msi_ctrl |
| 25 | 94 | R/W | pcie_ep_cfg_msi_addr_low |
| 26 | 98 | R/W | pcie_ep_cfg_msi_addr_high |
| 27 | 9c | R/W | pcie_ep_cfg_msi_msg_data |
| 28 | a0 | R/W | pcie_ep_cfg_msi_mask |
| 29-242 | a4-908 | - | reserved |
| 243 | 90c | R/W | pcie_ep_cfg_l1_pm_substates_ctrl_2 |
| 244-3ff | 910-ffc | - | reserved |
| pcie_ep_cfg_id |
|
|||
| R |
Address : 0x6f800000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | device_id |
|
||
| 15 - 0 | vendor_id |
|
||
| pcie_ep_cfg_command_status |
|
||||||||
| R/W |
0x00100000 |
Address : 0x6f800004 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
dpe |
|
||||||
| 30 | "0" |
sse |
|
||||||
| 29 | "0" |
rma |
|
||||||
| 28 | "0" |
rta |
|
||||||
| 27 | "0" |
sta |
|
||||||
| 26 - 25 | 0 |
- |
reserved | ||||||
| 24 | "0" |
mdpe |
|
||||||
| 23 - 21 | 0 |
- |
reserved | ||||||
| 20 | - |
cl_ro |
|
||||||
| 19 | - |
is_ro |
|
||||||
| 18 - 11 | 0 |
- |
reserved | ||||||
| 10 | "0" |
imd |
|
||||||
| 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
se |
|
||||||
| 7 | 0 |
- |
reserved | ||||||
| 6 | "0" |
pere |
|
||||||
| 5 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
be |
|
||||||
| 1 | "0" |
mse |
|
||||||
| 0 | "0" |
ise |
|
||||||
| pcie_ep_cfg_revision_id_class_code | |||
|
Address : 0x6f800008 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | pcie_ep_cfg_revision_id_class_code | ||
| pcie_ep_cfg_bist_header_latency_cache_line | |||
|
Address : 0x6f80000c |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | pcie_ep_cfg_bist_header_latency_cache_line | ||
| pcie_ep_cfg_base_addr_0 |
|
|||||||
| R/W |
0x00000004 |
Address : 0x6f800010 |
Bits | Reset value | Name | Description | ||
|---|---|---|---|---|---|---|---|---|
| 31 - 22 | 0x0 |
bamrw |
|
|||||
| 21 - 8 | - |
bamro_ro |
|
|||||
| 7 - 4 | 0 |
- |
reserved | |||||
| 3 | - |
po_ro |
|
|||||
| 2 | - |
so_ro |
|
|||||
| 1 | 0 |
- |
reserved | |||||
| 0 | - |
msio_ro |
|
|||||
| pcie_ep_cfg_base_addr_1 |
|
|||
| R/W |
0x00000000 |
Address : 0x6f800014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
bamrw |
|
|
| pcie_ep_cfg_msi_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6f800090 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | |
| 24 | - |
mc_ro |
|
|
| 23 | - |
bac64_ro |
|
|
| 22 - 20 | "000" |
mme |
|
|
| 19 - 17 | - |
mmc_ro |
|
|
| 16 | "0" |
me |
|
|
| 15 - 8 | - |
cp1_ro |
|
|
| 7 - 0 | - |
cid1_ro |
|
|
| pcie_ep_cfg_msi_addr_low |
|
|||
| R/W |
0x00000000 |
Address : 0x6f800094 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
mal |
|
|
| pcie_ep_cfg_msi_addr_high |
|
|||
| R/W |
0x00000000 |
Address : 0x6f800098 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
mah |
|
|
| pcie_ep_cfg_msi_msg_data |
|
|||
| R/W |
0x00000000 |
Address : 0x6f80009c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 - 0 | 0x0 |
md |
|
|
| pcie_ep_cfg_msi_mask |
|
|||
| R/W |
0x00000000 |
Address : 0x6f8000a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
mm |
|
|
| pcie_ep_cfg_l1_pm_substates_ctrl_2 |
|
|||
| R/W |
0x00000028 |
Address : 0x6f80090c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 3 | "00101" |
l1pwronval |
|
|
| 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
l1pwronsc |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R | pcie_rp_cfg_id |
| 1 | 4 | R/W | pcie_rp_cfg_command_status |
| 2 | 8 | - | pcie_rp_cfg_revision_id_class_code |
| 3 | c | - | pcie_rp_cfg_bist_header_latency_cache_line |
| 4-242 | 10-908 | - | reserved |
| 243 | 90c | R/W | pcie_rp_cfg_l1_pm_substates_ctrl_2 |
| 244-3ff | 910-ffc | - | reserved |
| pcie_rp_cfg_id |
|
|||
| R |
Address : 0x6f800000 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | device_id |
|
||
| 15 - 0 | vendor_id |
|
||
| pcie_rp_cfg_command_status |
|
||||||||
| R/W |
0x00100000 |
Address : 0x6f800004 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 | "0" |
dpe |
|
||||||
| 30 | "0" |
sse |
|
||||||
| 29 | "0" |
rma |
|
||||||
| 28 | "0" |
rta |
|
||||||
| 27 | "0" |
sta |
|
||||||
| 26 - 25 | 0 |
- |
reserved | ||||||
| 24 | "0" |
mdpe |
|
||||||
| 23 - 21 | 0 |
- |
reserved | ||||||
| 20 | - |
cl_ro |
|
||||||
| 19 | - |
is_ro |
|
||||||
| 18 - 11 | 0 |
- |
reserved | ||||||
| 10 | "0" |
imd |
|
||||||
| 9 | 0 |
- |
reserved | ||||||
| 8 | "0" |
se |
|
||||||
| 7 | 0 |
- |
reserved | ||||||
| 6 | "0" |
pere |
|
||||||
| 5 - 3 | 0 |
- |
reserved | ||||||
| 2 | "0" |
be |
|
||||||
| 1 | "0" |
mse |
|
||||||
| 0 | "0" |
ise |
|
||||||
| pcie_rp_cfg_revision_id_class_code | |||
|
Address : 0x6f800008 |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | pcie_rp_cfg_revision_id_class_code | ||
| pcie_rp_cfg_bist_header_latency_cache_line | |||
|
Address : 0x6f80000c |
Bits | Name | Description |
|---|---|---|---|
| 31 - 0 | pcie_rp_cfg_bist_header_latency_cache_line | ||
| pcie_rp_cfg_l1_pm_substates_ctrl_2 |
|
|||
| R/W |
0x00000028 |
Address : 0x6f80090c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 3 | "00101" |
l1pwronval |
|
|
| 2 | 0 |
- |
reserved | |
| 1 - 0 | "00" |
l1pwronsc |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | pcie_local_mgmt_i_pl_config_0_reg |
| 1-3ed | 4-fb4 | - | reserved |
| 3ee | fb8 | R/W | pcie_local_mgmt_i_ltssm_timer_control_reg3 |
| 3ef-3ff | fbc-ffc | - | reserved |
| pcie_local_mgmt_i_pl_config_0_reg |
|
|||
| R/W |
0x00000020 |
Address : 0x6f900000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 | "0" |
mle |
|
|
| 30 | - |
r0_ro |
|
|
| 29 - 24 | - |
ltssm_ro |
|
|
| 23 - 16 | - |
rlid_ro |
|
|
| 15 - 8 | - |
rfc_ro |
|
|
| 7 | "0" |
tss |
|
|
| 6 | "0" |
aper |
|
|
| 5 | - |
ltd_ro |
|
|
| 4 - 3 | - |
ns_ro |
|
|
| 2 - 1 | 0 |
- |
reserved | |
| 0 | - |
ls_ro |
|
|
| pcie_local_mgmt_i_ltssm_timer_control_reg3 |
|
|||
| R/W |
0xb71b7a12 |
Address : 0x6f900fb8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xb71b |
l48mstm |
|
|
| 15 - 0 | 0x7a12 |
l32mstm |
|
|
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | pcie_axi_cfg_outbound_at_reg0 |
| 1-21c | 4-870 | - | reserved |
| 21d | 874 | R/W | pcie_axi_cfg_function0_bar6_ep_inbound_at_reg1 |
| 21e | 878 | - | reserved |
| 21f | 87c | R/W | pcie_axi_cfg_reserved |
| 220-3ff | 880-ffc | - | reserved |
| pcie_axi_cfg_outbound_at_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x6fc00000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0x0 |
data |
|
|
| 7 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "000000" |
num_bits |
|
|
| pcie_axi_cfg_function0_bar6_ep_inbound_at_reg1 |
|
|||
| R/W |
0x00000000 |
Address : 0x6fc00874 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| pcie_axi_cfg_reserved |
|
|||
| R/W |
0x00000000 |
Address : 0x6fc0087c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
data |
|
|
| pcie_dma_channel0_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00000 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
ob_not_ib |
|
|
| 0 | "0" |
go |
|
|
| pcie_dma_channel0_sp_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00004 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel0_sp_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel0_attr_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe0000c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel0_attr_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel1_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
ob_not_ib |
|
|
| 0 | "0" |
go |
|
|
| pcie_dma_channel1_sp_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel1_sp_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe0001c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel1_attr_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00020 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel1_attr_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00024 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel2_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00028 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
ob_not_ib |
|
|
| 0 | "0" |
go |
|
|
| pcie_dma_channel2_sp_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe0002c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel2_sp_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00030 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel2_attr_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00034 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel2_attr_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00038 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel3_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe0003c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 2 | 0 |
- |
reserved | |
| 1 | "0" |
ob_not_ib |
|
|
| 0 | "0" |
go |
|
|
| pcie_dma_channel3_sp_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00040 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel3_sp_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00044 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
ptr |
|
|
| pcie_dma_channel3_attr_l |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe00048 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_channel3_attr_u |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe0004c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
attr |
|
|
| pcie_dma_common_udma_int |
|
|||
| R/W |
0x00000000 |
Address : 0x6fe000a0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "0" |
ch7_error_int |
|
|
| 14 | "0" |
ch6_error_int |
|
|
| 13 | "0" |
ch5_error_int |
|
|
| 12 | "0" |
ch4_error_int |
|
|
| 11 | "0" |
ch3_error_int |
|
|
| 10 | "0" |
ch2_error_int |
|
|
| 9 | "0" |
ch1_error_int |
|
|
| 8 | "0" |
ch0_error_int |
|
|
| 7 | "0" |
ch7_done_int |
|
|
| 6 | "0" |
ch6_done_int |
|
|
| 5 | "0" |
ch5_done_int |
|
|
| 4 | "0" |
ch4_done_int |
|
|
| 3 | "0" |
ch3_done_int |
|
|
| 2 | "0" |
ch2_done_int |
|
|
| 1 | "0" |
ch1_done_int |
|
|
| 0 | "0" |
ch0_done_int |
|
|
| pcie_dma_common_udma_int_ena |
|
|||
| R/W |
0x0000ffff |
Address : 0x6fe000a4 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "1" |
ch7_error_ena |
|
|
| 14 | "1" |
ch6_error_ena |
|
|
| 13 | "1" |
ch5_error_ena |
|
|
| 12 | "1" |
ch4_error_ena |
|
|
| 11 | "1" |
ch3_error_ena |
|
|
| 10 | "1" |
ch2_error_ena |
|
|
| 9 | "1" |
ch1_error_ena |
|
|
| 8 | "1" |
ch0_error_ena |
|
|
| 7 | "1" |
ch7_done_ena |
|
|
| 6 | "1" |
ch6_done_ena |
|
|
| 5 | "1" |
ch5_done_ena |
|
|
| 4 | "1" |
ch4_done_ena |
|
|
| 3 | "1" |
ch3_done_ena |
|
|
| 2 | "1" |
ch2_done_ena |
|
|
| 1 | "1" |
ch1_done_ena |
|
|
| 0 | "1" |
ch0_done_ena |
|
|
| pcie_dma_common_udma_int_dis |
|
|||
| R/W |
0x0000ffff |
Address : 0x6fe000a8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0 |
- |
reserved | |
| 15 | "1" |
ch7_error_dis |
|
|
| 14 | "1" |
ch6_error_dis |
|
|
| 13 | "1" |
ch5_error_dis |
|
|
| 12 | "1" |
ch4_error_dis |
|
|
| 11 | "1" |
ch3_error_dis |
|
|
| 10 | "1" |
ch2_error_dis |
|
|
| 9 | "1" |
ch1_error_dis |
|
|
| 8 | "1" |
ch0_error_dis |
|
|
| 7 | "1" |
ch7_done_dis |
|
|
| 6 | "1" |
ch6_done_dis |
|
|
| 5 | "1" |
ch5_done_dis |
|
|
| 4 | "1" |
ch4_done_dis |
|
|
| 3 | "1" |
ch3_done_dis |
|
|
| 2 | "1" |
ch2_done_dis |
|
|
| 1 | "1" |
ch1_done_dis |
|
|
| 0 | "1" |
ch0_done_dis |
|
|
| pcie_dma_common_udma_ib_ecc_uncorrectable_errors |
|
|||
| R |
Address : 0x6fe000ac |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | total |
|
||
| pcie_dma_common_udma_ib_ecc_correctable_errors |
|
|||
| R |
Address : 0x6fe000b0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | total |
|
||
| pcie_dma_common_udma_ob_ecc_uncorrectable_errors |
|
|||
| R |
Address : 0x6fe000b4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | total |
|
||
| pcie_dma_common_udma_ob_ecc_correctable_errors |
|
|||
| R |
Address : 0x6fe000b8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 0 | total |
|
||
| pcie_dma_common_udma_cap_ver |
|
|||
| R |
Address : 0x6fe000f8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 - 8 | maj_ver |
|
||
| 7 - 0 | min_ver |
|
||
| pcie_dma_common_udma_config |
|
|||
| R |
Address : 0x6fe000fc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 16 | - |
reserved | ||
| 15 | ext_tw_gt_32 |
|
||
| 14 | ext_aw_gt_32 |
|
||
| 13 | sys_tw_gt_32 |
|
||
| 12 | sys_aw_gt_32 |
|
||
| 11 - 8 | partition_size |
|
||
| 7 - 4 | num_partitions |
|
||
| 3 - 0 | num_channels |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0-1 | 0-4 | - | reserved |
| 2 | 8 | R/W | cm0_scs_actlr |
| 3 | c | - | reserved |
| 4 | 10 | R/W | cm0_scs_syst_csr |
| 5 | 14 | R/W | cm0_scs_syst_rvr |
| 6 | 18 | R/W | cm0_scs_syst_cvr |
| 7 | 1c | R | cm0_scs_syst_calib |
| 8-3f | 20-fc | - | reserved |
| 40 | 100 | R/W | cm0_scs_nvic_iser |
| 41-5f | 104-17c | - | reserved |
| 60 | 180 | R/W | cm0_scs_nvic_icer |
| 61-7f | 184-1fc | - | reserved |
| 80 | 200 | R/W | cm0_scs_nvic_ispr |
| 81-9f | 204-27c | - | reserved |
| a0 | 280 | R/W | cm0_scs_nvic_icpr |
| a1-ff | 284-3fc | - | reserved |
| 100 | 400 | R/W | cm0_scs_nvic_ipr0 |
| 101 | 404 | R/W | cm0_scs_nvic_ipr1 |
| 102 | 408 | R/W | cm0_scs_nvic_ipr2 |
| 103 | 40c | R/W | cm0_scs_nvic_ipr3 |
| 104 | 410 | R/W | cm0_scs_nvic_ipr4 |
| 105 | 414 | R/W | cm0_scs_nvic_ipr5 |
| 106 | 418 | R/W | cm0_scs_nvic_ipr6 |
| 107 | 41c | R/W | cm0_scs_nvic_ipr7 |
| 108-33f | 420-cfc | - | reserved |
| 340 | d00 | R | cm0_scs_cpuid |
| 341 | d04 | R/W | cm0_scs_icsr |
| 342 | d08 | R/W | cm0_scs_vtor |
| 343 | d0c | R/W | cm0_scs_aircr |
| 344 | d10 | R/W | cm0_scs_scr |
| 345 | d14 | R/W | cm0_scs_ccr |
| 346 | d18 | - | reserved |
| 347 | d1c | R/W | cm0_scs_shpr2 |
| 348 | d20 | R/W | cm0_scs_shpr3 |
| 349 | d24 | R/W | cm0_scs_shcsr |
| 34a-34b | d28-d2c | - | reserved |
| 34c | d30 | R/W | cm0_scs_dfsr |
| 34d-363 | d34-d8c | - | reserved |
| 364 | d90 | R | cm0_scs_mpu_type |
| 365 | d94 | R/W | cm0_scs_mpu_ctrl |
| 366 | d98 | R/W | cm0_scs_mpu_rnr |
| 367 | d9c | R/W | cm0_scs_mpu_rbar |
| 368 | da0 | R/W | cm0_scs_mpu_rasr |
| 369-37b | da4-dec | - | reserved |
| 37c | df0 | R/W | cm0_scs_dhcsr |
| 37d | df4 | W | cm0_scs_dcrsr |
| 37e | df8 | R/W | cm0_scs_dcrdr |
| 37f | dfc | R/W | cm0_scs_demcr |
| 380-3f3 | e00-fcc | - | reserved |
| 3f4 | fd0 | R | cm0_scs_pidr4 |
| 3f5-3f7 | fd4-fdc | - | reserved |
| 3f8 | fe0 | R | cm0_scs_pidr0 |
| 3f9 | fe4 | R | cm0_scs_pidr1 |
| 3fa | fe8 | R | cm0_scs_pidr2 |
| 3fb | fec | R | cm0_scs_pidr3 |
| 3fc | ff0 | R | cm0_scs_cidr0 |
| 3fd | ff4 | R | cm0_scs_cidr1 |
| 3fe | ff8 | R | cm0_scs_cidr2 |
| 3ff | ffc | R | cm0_scs_cidr3 |
| cm0_scs_actlr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e008 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_actlr | ||
| cm0_scs_syst_csr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e010 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_syst_csr | ||
| cm0_scs_syst_rvr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e014 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_syst_rvr | ||
| cm0_scs_syst_cvr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e018 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_syst_cvr | ||
| cm0_scs_syst_calib |
|
|||
| R |
Address : 0xe000e01c |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_syst_calib | |||
| cm0_scs_nvic_iser |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000e100 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
setena |
|
||||||
| cm0_scs_nvic_icer |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000e180 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
clrena |
|
||||||
| cm0_scs_nvic_ispr |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000e200 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
setpend |
|
||||||
| cm0_scs_nvic_icpr |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000e280 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 0 | 0x0 |
clrpend |
|
||||||
| cm0_scs_nvic_ipr0 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e400 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr1 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e404 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr2 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e408 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr3 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e40c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr4 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e410 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr5 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e414 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr6 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e418 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_nvic_ipr7 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000e41c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 24 | "00000000" |
pri_n3 |
|
|
| 23 - 16 | "00000000" |
pri_n2 |
|
|
| 15 - 8 | "00000000" |
pri_n1 |
|
|
| 7 - 0 | "00000000" |
pri_n0 |
|
|
| cm0_scs_cpuid |
|
|||
| R |
Address : 0xe000ed00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_cpuid | |||
| cm0_scs_icsr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed04 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_icsr | ||
| cm0_scs_vtor |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed08 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 7 | 0x0 |
tbloff |
|
|
| 6 - 0 | 0 |
- |
reserved | |
| cm0_scs_aircr |
|
|||
| R/W |
0xfa050000 |
Address : 0xe000ed0c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 16 | 0xfa05 |
vectkey |
|
|
| 15 | "0" |
endianness |
|
|
| 14 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
sysresetreq |
|
|
| 1 | "0" |
vectclractive |
|
|
| 0 | 0 |
- |
reserved | |
| cm0_scs_scr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed10 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_scr | ||
| cm0_scs_ccr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed14 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_ccr | ||
| cm0_scs_shpr2 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed1c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_shpr2 | ||
| cm0_scs_shpr3 |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed20 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_shpr3 | ||
| cm0_scs_shcsr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed24 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0 |
cm0_scs_shcsr | ||
| cm0_scs_dfsr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed30 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0 |
- |
reserved | |
| 4 | "0" |
external |
|
|
| 3 | "0" |
vcatch |
|
|
| 2 | "0" |
dwttrap |
|
|
| 1 | "0" |
bkpt |
|
|
| 0 | "0" |
halted |
|
|
| cm0_scs_mpu_type |
|
|||
| R |
Address : 0xe000ed90 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_mpu_type | |||
| cm0_scs_mpu_ctrl |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed94 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
privdefena |
||
| 1 | "0" |
hfnmiena |
||
| 0 | "0" |
enable |
||
| cm0_scs_mpu_rnr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed98 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 8 | 0 |
- |
reserved | |
| 7 - 0 | "00000000" |
region |
||
| cm0_scs_mpu_rbar |
|
|||
| R/W |
0x00000000 |
Address : 0xe000ed9c |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 5 | 0x0 |
addr |
||
| 4 | "0" |
valid |
||
| 3 - 0 | "0000" |
region |
||
| cm0_scs_mpu_rasr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000eda0 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 29 | 0 |
- |
reserved | |
| 28 | "0" |
xn |
||
| 27 | 0 |
- |
reserved | |
| 26 - 24 | "000" |
ap |
||
| 23 - 22 | 0 |
- |
reserved | |
| 21 - 19 | "000" |
tex |
||
| 18 | "0" |
s |
||
| 17 | "0" |
c |
||
| 16 | "0" |
b |
||
| 15 - 6 | 0 |
- |
reserved | |
| 5 - 1 | "00000" |
size |
||
| 0 | "0" |
enable |
||
| cm0_scs_dhcsr |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000edf0 |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 26 | 0 |
- |
reserved | ||||||
| 25 | "0" |
s_reset_st |
|
||||||
| 24 | "0" |
s_retire_st |
|
||||||
| 23 - 20 | 0 |
- |
reserved | ||||||
| 19 | "0" |
s_lockup |
|
||||||
| 18 | "0" |
s_sleep |
|
||||||
| 17 | "0" |
s_halt |
|
||||||
| 16 | "0" |
s_regrdy |
|
||||||
| 15 - 4 | 0 |
- |
reserved | ||||||
| 3 | "0" |
c_maskints |
|
||||||
| 2 | "0" |
c_step |
|
||||||
| 1 | "0" |
c_halt |
|
||||||
| 0 | "0" |
c_debugen |
|
||||||
| cm0_scs_dcrsr |
|
||||||||||||||||||||
| W |
0x00000000 |
Address : 0xe000edf4 |
Bits | Reset value | Name | Description | |||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 17 | 0 |
- |
reserved | ||||||||||||||||||
| 16 | "0" |
regwnr |
|
||||||||||||||||||
| 15 - 7 | 0 |
- |
reserved | ||||||||||||||||||
| 6 - 0 | "0000000" |
regsel |
|
||||||||||||||||||
| cm0_scs_dcrdr |
|
|||
| R/W |
0x00000000 |
Address : 0xe000edf8 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 0 | 0x0 |
dbgtmp |
|
|
| cm0_scs_demcr |
|
||||||||
| R/W |
0x00000000 |
Address : 0xe000edfc |
Bits | Reset value | Name | Description | |||
|---|---|---|---|---|---|---|---|---|---|
| 31 - 25 | 0 |
- |
reserved | ||||||
| 24 | "0" |
dwtena |
|
||||||
| 23 - 11 | 0 |
- |
reserved | ||||||
| 10 | "0" |
vc_harderr |
|
||||||
| 9 - 1 | 0 |
- |
reserved | ||||||
| 0 | "0" |
vc_corereset |
|
||||||
| cm0_scs_pidr4 |
|
|||
| R |
Address : 0xe000efd0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_pidr4 | |||
| cm0_scs_pidr0 |
|
|||
| R |
Address : 0xe000efe0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_pidr0 | |||
| cm0_scs_pidr1 |
|
|||
| R |
Address : 0xe000efe4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_pidr1 | |||
| cm0_scs_pidr2 |
|
|||
| R |
Address : 0xe000efe8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_pidr2 | |||
| cm0_scs_pidr3 |
|
|||
| R |
Address : 0xe000efec |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 0 | cm0_scs_pidr3 | |||
| cm0_scs_cidr0 |
|
|||
| R |
Address : 0xe000eff0 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_0 |
|
||
| cm0_scs_cidr1 |
|
|||
| R |
Address : 0xe000eff4 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 4 | class |
|
||
| 3 - 0 | prmbl_1 |
|
||
| cm0_scs_cidr2 |
|
|||
| R |
Address : 0xe000eff8 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_2 |
|
||
| cm0_scs_cidr3 |
|
|||
| R |
Address : 0xe000effc |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 8 | - |
reserved | ||
| 7 - 0 | prmbl_3 |
|
||
| Address mapping | |||
| DWord Offset (hex) | Byte Offset (hex) | Mode | Register |
|---|---|---|---|
| 0 | 0 | R/W | gen_ram_ctrl_mbist_power0 |
| 1-1ff | 4-7fc | - | reserved |
| 200 | 800 | R/W | gen_ram_ctrl_ecc0 |
| 201-27f | 804-9fc | - | reserved |
| 280 | a00 | R | gen_ram_ctrl_ecc_status_corr0 |
| 281-2ff | a04-bfc | - | reserved |
| 300 | c00 | R | gen_ram_ctrl_ecc_status_noncorr0 |
| 301-37f | c04-dfc | - | reserved |
| 380 | e00 | R/W | gen_ram_ctrl_irq_raw_reg0 |
| 381-38f | e04-e3c | - | reserved |
| 390 | e40 | R/W | gen_ram_ctrl_irq_masked_reg0 |
| 391-39f | e44-e7c | - | reserved |
| 3a0 | e80 | R/W | gen_ram_ctrl_irq_mask_set_reg0 |
| 3a1-3af | e84-ebc | - | reserved |
| 3b0 | ec0 | R/W | gen_ram_ctrl_irq_mask_rst_reg0 |
| 3b1-3be | ec4-ef8 | - | reserved |
| 3bf | efc | R/W | gen_ram_ctrl_power_sequencer_ctrl_reg |
| 3c0-3ff | f00-ffc | - | reserved |
| gen_ram_ctrl_mbist_power0 |
|
||||||||||||||||
| R/W |
0x000000a0 |
Address : 0x00000000 |
Bits | Reset value | Name | Description | |||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 13 | 0 |
- |
reserved | ||||||||||||||
| 12 | - |
ecc_support_ro |
|
||||||||||||||
| 11 | - |
sleep_support_ro |
|
||||||||||||||
| 10 | - |
mbist_init_support_ro |
|
||||||||||||||
| 9 | "0" |
enable_mode_abort |
|
||||||||||||||
| 8 | "0" |
enable_ecc_abort |
|
||||||||||||||
| 7 | "1" |
shutdown |
|
||||||||||||||
| 6 | "0" |
sleep |
|
||||||||||||||
| 5 | "1" |
disable_mem |
|
||||||||||||||
| 4 - 2 | - |
bist_status_ro |
|
||||||||||||||
| 1 - 0 | "00" |
bist_mode |
|
||||||||||||||
| gen_ram_ctrl_ecc0 |
|
|||
| R/W |
0x00000000 |
Address : 0x00000800 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | - |
ecc_corr_support_ro |
|
|
| 1 | "0" |
ecc_freeze_checkbits |
|
|
| 0 | "0" |
ecc_enable |
|
|
| gen_ram_ctrl_ecc_status_corr0 |
|
|||
| R |
Address : 0x00000a00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_ecc_status_noncorr0 |
|
|||
| R |
Address : 0x00000c00 |
Bits | Name | Description |
|---|---|---|---|---|
| 31 - 24 | ecc_err_counter |
|
||
| 23 - 0 | ecc_err_address |
|
||
| gen_ram_ctrl_irq_raw_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x00000e00 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_irq_masked_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x00000e40 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_irq_mask_set_reg0 |
|
|||
| R/W |
0x00000000 |
Address : 0x00000e80 |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|
| gen_ram_ctrl_irq_mask_rst_reg0 |
|
|||||||||||
| R/W |
0x00000000 |
Address : 0x00000ec0 |
Bits | Reset value | Name | Description | ||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 31 - 3 | 0 |
- |
reserved | |||||||||
| 2 | "0" |
mem_0_mbist_or_init_finished |
|
|||||||||
| 1 | "0" |
mem_0_err_ecc_correctable |
|
|||||||||
| 0 | "0" |
mem_0_err_ecc_non_correctable |
|
|||||||||
| gen_ram_ctrl_power_sequencer_ctrl_reg |
|
|||
| R/W |
0x0000000a |
Address : 0x00000efc |
Bits | Reset value | Name | Description |
|---|---|---|---|---|
| 31 - 6 | 0 |
- |
reserved | |
| 5 - 0 | "001010" |
power_sequencer_num_cycles |
|
|