Register Definition


Base Address Areas

Name Base Address 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
secenc_rom 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . .
bootreg 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_intram0_boot 0x00000000 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
iol_config_interconnect 0x00080000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . . . .
iol_ram_ctrl 0x00080000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 . . . . . . . . . . . .
iol_config 0x00081000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
iol_timer 0x00081100 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . .
iol_spi 0x00081100 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . . . .
iol_hsc 0x00081c00 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 1 . . . . . . . . . .
iol_wdg_sys 0x00082000 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . .
iol_arm_tim0 0x00082080 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . .
iol_arm_tim1 0x00082100 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . .
cada_config_interconnect 0x00100000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . . . . . . . . . .
ada_config_interconnect 0x00100000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . . . .
ada_ram_ctrl 0x00100000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
cada_ram_ctrl 0x00100000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
cada_config 0x00101000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
ada_config 0x00101000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
ada_timer 0x00101100 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . .
ada_hsc 0x00101c00 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 . . . . . . . . . .
ada_wdg_sys 0x00102000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . .
ada_arm_tim0 0x00102080 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . .
ada_arm_tim1 0x00102100 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . .
cada_ise_ctrl 0x00110000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
cada_internal_ise 0x00110000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
cada_internal_ise_dma 0x00110000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
cada_timer 0x00110800 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 . . . . . . . .
cada_hsc 0x00110c00 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 . . . . . . . . . .
cada_wdg_sys 0x00111000 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 . . . . .
cada_arm_tim0 0x00111080 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 . . . . . . .
cada_arm_tim1 0x00111100 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 . . . . . . .
cvm 0x02000000 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . .
cvm_intram0 0x02000000 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
cvm_cfg 0x03f00000 0 0 0 0 0 0 1 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . .
cvm_ram_ctrl 0x03f00000 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com 0x04000000 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . .
com_intram0 0x06000000 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
com_intram1 0x06100000 0 0 0 0 0 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . .
com_intram2 0x06200000 0 0 0 0 0 1 1 0 0 0 1 0 . . . . . . . . . . . . . . . . . . . .
com_a32_peri 0x06400000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . . . . . .
com_i2c0 0x06400000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
com_i2c1 0x06400040 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . .
com_spi0 0x06400080 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . .
com_spi1 0x064000c0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . .
com_uart0 0x06400100 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . .
com_uart1 0x06400140 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . .
com_gpio 0x06400180 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . .
com_pio 0x06400200 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . .
com_blink 0x06400300 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
com_blink_mixled 0x06400340 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 . . . . .
com_gxc_mixled0 0x06400360 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 . . . . .
com_gxc_mixled1 0x06400380 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 . . . . .
com_wdg 0x064003a0 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 . . . . .
com_hsgmii0 0x06400400 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . .
com_hsgmii1 0x06400500 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . .
com_xspi 0x06400600 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . .
com_sync_timer 0x06400800 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . .
com_sync_timer_global 0x06400c00 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . .
com_hsc 0x06401000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . .
com_can_fd 0x06420000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 0 . . . . . . . . . . . . . . . .
crypt 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 . . . . . . . . . . . . . .
com_crypt 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 . . . . . . . . . . . . . .
ise 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . .
com_ise 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . .
ise_dma 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
com_ise_dma 0x06430000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
mtgy 0x06432000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 . . . . . . . . . . . . .
com_mtgy 0x06432000 0 0 0 0 0 1 1 0 0 1 0 0 0 0 1 1 0 0 1 . . . . . . . . . . . . .
com_cda_rx 0x06600000 0 0 0 0 0 1 1 0 0 1 1 . . . . . . . . . . . . . . . . . . . . .
com_cda_rx_itcm_start 0x06600000 0 0 0 0 0 1 1 0 0 1 1 0 0 . . . . . . . . . . . . . . . . . . .
com_cda_rx_dtcm_start 0x06680000 0 0 0 0 0 1 1 0 0 1 1 0 1 . . . . . . . . . . . . . . . . . . .
com_cda_rx_config_interconnect 0x06700000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 . . . . . . . . . . . . . . . . .
com_cda_rx_ram_ctrl 0x06700000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_cda_rx_config 0x06701000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
com_cda_rx_ise_ctrl 0x06710000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
com_cda_rx_ise 0x06710000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
com_cda_rx_ise_dma 0x06710000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
com_cda_rx_timer 0x06710800 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 0 0 0 . . . . . . . .
com_cda_rx_hsc 0x06710c00 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 0 1 1 . . . . . . . . . .
com_cda_rx_wdg_sys 0x06711000 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 . . . . .
com_cda_rx_arm_tim0 0x06711080 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 0 0 1 . . . . . . .
com_cda_rx_arm_tim1 0x06711100 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 1 0 0 0 1 0 0 0 1 0 . . . . . . .
com_cda_tx 0x06800000 0 0 0 0 0 1 1 0 1 0 0 . . . . . . . . . . . . . . . . . . . . .
com_cda_tx_itcm_start 0x06800000 0 0 0 0 0 1 1 0 1 0 0 0 0 . . . . . . . . . . . . . . . . . . .
com_cda_tx_dtcm_start 0x06880000 0 0 0 0 0 1 1 0 1 0 0 0 1 . . . . . . . . . . . . . . . . . . .
com_cda_tx_config_interconnect 0x06900000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 . . . . . . . . . . . . . . . . .
com_cda_tx_ram_ctrl 0x06900000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_cda_tx_config 0x06901000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
com_cda_tx_ise_ctrl 0x06910000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
com_cda_tx_ise 0x06910000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . .
com_cda_tx_ise_dma 0x06910000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
com_cda_tx_timer 0x06910800 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 . . . . . . . .
com_cda_tx_hsc 0x06910c00 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 1 1 . . . . . . . . . .
com_cda_tx_wdg_sys 0x06911000 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 . . . . .
com_cda_tx_arm_tim0 0x06911080 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 0 1 . . . . . . .
com_cda_tx_arm_tim1 0x06911100 0 0 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 . . . . . . .
com_ada 0x06a00000 0 0 0 0 0 1 1 0 1 0 1 . . . . . . . . . . . . . . . . . . . . .
com_ada_itcm_start 0x06a00000 0 0 0 0 0 1 1 0 1 0 1 0 0 . . . . . . . . . . . . . . . . . . .
com_ada_dtcm_start 0x06a80000 0 0 0 0 0 1 1 0 1 0 1 0 1 . . . . . . . . . . . . . . . . . . .
com_ada_config_interconnect 0x06b00000 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 . . . . . . . . . . . . . .
com_ada_ram_ctrl 0x06b00000 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_ada_config 0x06b01000 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
com_ada_timer 0x06b01100 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . .
com_ada_hsc 0x06b01c00 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 0 1 1 1 . . . . . . . . . .
com_ada_wdg_sys 0x06b02000 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . .
com_ada_arm_tim0 0x06b02080 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . .
com_ada_arm_tim1 0x06b02100 0 0 0 0 0 1 1 0 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . .
com_iol 0x06c00000 0 0 0 0 0 1 1 0 1 1 0 0 . . . . . . . . . . . . . . . . . . . .
com_iol_itcm_start 0x06c00000 0 0 0 0 0 1 1 0 1 1 0 0 0 0 . . . . . . . . . . . . . . . . . .
com_iol_dtcm_start 0x06c40000 0 0 0 0 0 1 1 0 1 1 0 0 0 1 . . . . . . . . . . . . . . . . . .
com_iol_config_interconnect 0x06c80000 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 . . . . . . . . . . . . . .
com_iol_ram_ctrl 0x06c80000 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_iol_config 0x06c81000 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
com_iol_timer 0x06c81100 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . .
com_iol_spi 0x06c81100 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . . . .
com_iol_hsc 0x06c81c00 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 0 1 1 1 . . . . . . . . . .
com_iol_wdg_sys 0x06c82000 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . .
com_iol_arm_tim0 0x06c82080 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 0 1 . . . . . . .
com_iol_arm_tim1 0x06c82100 0 0 0 0 0 1 1 0 1 1 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 . . . . . . .
com_gic 0x07900000 0 0 0 0 0 1 1 1 1 0 0 1 0 . . . . . . . . . . . . . . . . . . .
com_periphbase 0x07980000 0 0 0 0 0 1 1 1 1 0 0 1 1 . . . . . . . . . . . . . . . . . . .
com_gxcs 0x07c00000 0 0 0 0 0 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . .
gxc_gpec_dram 0x07c00000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . .
gxc_grpu_ram 0x07c00000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . .
gxc_rate_limiter 0x07c00000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
gxc_token_bucket_instance0 0x07c00000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . .
gxc_token_bucket_instance1 0x07c00080 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . .
gxc_gtpu_ram 0x07c00800 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . .
gxc_gmac_regs 0x07c01000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . .
gxc_gpec_pram 0x07c02000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . .
gxc_gpec_regs 0x07c03000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . .
intram0_gxc 0x07c20000 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . .
intram1_gxc 0x07c40000 0 0 0 0 0 1 1 1 1 1 0 0 0 1 0 . . . . . . . . . . . . . . . . .
intram2_gxc 0x07c60000 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 0 . . . . . . . . . . . . . . . .
intram3_gxc 0x07c70000 0 0 0 0 0 1 1 1 1 1 0 0 0 1 1 1 . . . . . . . . . . . . . . . .
gxc_config0 0x07d00000 0 0 0 0 0 1 1 1 1 1 0 1 0 . . . . . . . . . . . . . . . . . . .
gxc_gpec00 0x07d00000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 . . . . . . . . . . . . . .
gxc_gpec00_dram 0x07d00000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 . . . . . . . . . . . . .
gxc_gpec00_pram 0x07d02000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 0 . . . . . . . . . . . .
gxc_gpec00_regs 0x07d03000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec01 0x07d04000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 . . . . . . . . . . . . . .
gxc_gpec01_dram 0x07d04000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 0 . . . . . . . . . . . . .
gxc_gpec01_pram 0x07d06000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 0 . . . . . . . . . . . .
gxc_gpec01_regs 0x07d07000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec02 0x07d08000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 . . . . . . . . . . . . . .
gxc_gpec02_dram 0x07d08000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 0 . . . . . . . . . . . . .
gxc_gpec02_pram 0x07d0a000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 0 . . . . . . . . . . . .
gxc_gpec02_regs 0x07d0b000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec03 0x07d0c000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 1 . . . . . . . . . . . . . .
gxc_gpec03_dram 0x07d0c000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 1 0 . . . . . . . . . . . . .
gxc_gpec03_pram 0x07d0e000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 0 . . . . . . . . . . . .
gxc_gpec03_regs 0x07d0f000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec04 0x07d10000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 . . . . . . . . . . . . . .
gxc_gpec04_dram 0x07d10000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 0 . . . . . . . . . . . . .
gxc_gpec04_pram 0x07d12000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 1 0 . . . . . . . . . . . .
gxc_gpec04_regs 0x07d13000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec05 0x07d14000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 . . . . . . . . . . . . . .
gxc_gpec05_dram 0x07d14000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 0 . . . . . . . . . . . . .
gxc_gpec05_pram 0x07d16000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 0 . . . . . . . . . . . .
gxc_gpec05_regs 0x07d17000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 0 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec06 0x07d18000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 . . . . . . . . . . . . . .
gxc_gpec06_dram 0x07d18000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 0 . . . . . . . . . . . . .
gxc_gpec06_pram 0x07d1a000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 0 . . . . . . . . . . . .
gxc_gpec06_regs 0x07d1b000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec07 0x07d1c000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 . . . . . . . . . . . . . .
gxc_gpec07_dram 0x07d1c000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 0 . . . . . . . . . . . . .
gxc_gpec07_pram 0x07d1e000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 0 . . . . . . . . . . . .
gxc_gpec07_regs 0x07d1f000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 0 1 1 1 1 1 0 0 0 0 . . . . . . . .
gxc_gmac0 0x07d20000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 . . . . . . . . . . . . .
gxc_grpu0_ram 0x07d20000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 0 . . . . . . . . . . .
gxc_gtpu0_ram 0x07d20800 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 0 1 . . . . . . . . . . .
gxc_gmac0_regs 0x07d21000 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 . . . . . . . . .
gxc_pfifo0 0x07d22200 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 0 . . . . . . . .
gxc_pfifo1 0x07d22300 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 0 1 1 . . . . . . . .
gxc_gpec0_irq 0x07d22400 0 0 0 0 0 1 1 1 1 1 0 1 0 0 1 0 0 0 1 0 0 1 0 0 0 0 0 . . . . .
gxc_gpec10 0x07d40000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 . . . . . . . . . . . . . .
gxc_gpec10_dram 0x07d40000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 0 . . . . . . . . . . . . .
gxc_gpec10_pram 0x07d42000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1 0 . . . . . . . . . . . .
gxc_gpec10_regs 0x07d43000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec11 0x07d44000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 . . . . . . . . . . . . . .
gxc_gpec11_dram 0x07d44000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 0 . . . . . . . . . . . . .
gxc_gpec11_pram 0x07d46000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 0 . . . . . . . . . . . .
gxc_gpec11_regs 0x07d47000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 0 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec12 0x07d48000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 . . . . . . . . . . . . . .
gxc_gpec12_dram 0x07d48000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 0 . . . . . . . . . . . . .
gxc_gpec12_pram 0x07d4a000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 0 . . . . . . . . . . . .
gxc_gpec12_regs 0x07d4b000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec13 0x07d4c000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 . . . . . . . . . . . . . .
gxc_gpec13_dram 0x07d4c000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 0 . . . . . . . . . . . . .
gxc_gpec13_pram 0x07d4e000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 0 . . . . . . . . . . . .
gxc_gpec13_regs 0x07d4f000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 0 1 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec14 0x07d50000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 . . . . . . . . . . . . . .
gxc_gpec14_dram 0x07d50000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 0 . . . . . . . . . . . . .
gxc_gpec14_pram 0x07d52000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 1 0 . . . . . . . . . . . .
gxc_gpec14_regs 0x07d53000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec15 0x07d54000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 . . . . . . . . . . . . . .
gxc_gpec15_dram 0x07d54000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 . . . . . . . . . . . . .
gxc_gpec15_pram 0x07d56000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 0 . . . . . . . . . . . .
gxc_gpec15_regs 0x07d57000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 1 1 0 0 0 0 . . . . . . . .
gxc_gpec16 0x07d58000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 . . . . . . . . . . . . . .
gxc_gpec16_dram 0x07d58000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 0 . . . . . . . . . . . . .
gxc_gpec16_pram 0x07d5a000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 0 . . . . . . . . . . . .
gxc_gpec16_regs 0x07d5b000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 0 1 1 0 0 0 0 . . . . . . . .
gxc_gpec17 0x07d5c000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 . . . . . . . . . . . . . .
gxc_gpec17_dram 0x07d5c000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 0 . . . . . . . . . . . . .
gxc_gpec17_pram 0x07d5e000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 0 . . . . . . . . . . . .
gxc_gpec17_regs 0x07d5f000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 0 1 1 1 1 1 0 0 0 0 . . . . . . . .
gxc_gmac1 0x07d60000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 . . . . . . . . . . . . .
gxc_grpu1_ram 0x07d60000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 0 . . . . . . . . . . .
gxc_gtpu1_ram 0x07d60800 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 0 1 . . . . . . . . . . .
gxc_gmac1_regs 0x07d61000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 0 1 0 0 0 . . . . . . . . .
gxc_pfifo2 0x07d62200 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 0 . . . . . . . .
gxc_pfifo3 0x07d62300 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 0 1 1 . . . . . . . .
gxc_gpec1_irq 0x07d62400 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 0 0 0 0 0 . . . . .
gxc_sr 0x07d62500 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 0 1 . . . . . . . .
gxc_timer 0x07d62600 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 0 0 . . . . . . .
gxc_start_stop 0x07d62780 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 0 . . . .
gxc_buf_man 0x07d62790 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 0 0 1 1 1 1 0 0 1 . . . .
gxc_sys_ram_ctrl 0x07d63000 0 0 0 0 0 1 1 1 1 1 0 1 0 1 1 0 0 0 1 1 . . . . . . . . . . . .
gxc_config1 0x07d80000 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 . . . . . . . . . . . . . . . . .
gxc_esc_unit_ram 0x07d80000 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 0 . . . . . . . . . . . . .
gxc_esc_unit 0x07d82000 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 0 . . . . . . . . . . .
gxc_pfifo0_config 0x07d82800 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . .
gxc_pfifo1_config 0x07d82880 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 1 . . . . . . .
gxc_pfifo2_config 0x07d82900 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 0 . . . . . . .
gxc_pfifo3_config 0x07d82980 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 1 1 . . . . . . .
gxc_phy_ctrl0 0x07d82a00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 0 . . . . . .
gxc_phy_ctrl1 0x07d82a40 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 1 0 0 1 . . . . . .
gxc_sys_ctrl 0x07d82b00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 0 1 1 . . . . . . . .
gxc_trigger_lt 0x07d82c00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 0 . . . . . . . .
gxc_trigger_lt_global 0x07d82d00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 0 1 . . . . . . . .
gxc_systime 0x07d82e00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 0 . . . . . . . .
gxc_systime_lt 0x07d82f00 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 0 0 . . . . .
gxc_distribute_sync 0x07d82f20 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 0 1 . . . . .
gxc_distribute_sync_global 0x07d82f40 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 0 1 0 1 1 1 1 0 1 0 . . . . .
gxc_global_buf_man 0x07d84000 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 0 1 0 0 . . . . . . . . . . . .
gxc_rate_limiter0 0x07d88000 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 0 . . . . . . . .
gxc_rate_limiter1 0x07d88100 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 0 1 . . . . . . . .
gxc_rate_limiter2 0x07d88200 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 0 . . . . . . . .
gxc_rate_limiter3 0x07d88300 0 0 0 0 0 1 1 1 1 1 0 1 1 0 0 0 1 0 0 0 0 0 1 1 . . . . . . . .
envm 0x08000000 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
sqirom 0x08000000 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . . . . .
host_debug 0x10000000 0 0 0 1 0 . . . . . . . . . . . . . . . . . . . . . . . . . . .
host_funnel 0x100a0000 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 . . . . . . . . . . . . . . . .
host_replicator 0x10110000 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . . . . . .
host_etr 0x10120000 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . . . . . . . . . .
host_catu 0x10130000 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . . . . . . . . . . . .
host_cti 0x10140000 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 . . . . . . . . . . . . . . . .
stm_apb 0x10170000 0 0 0 1 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . . . . . .
expansion 0x11000000 0 0 0 1 0 0 0 1 . . . . . . . . . . . . . . . . . . . . . . . .
host_cpu_debug 0x12000000 0 0 0 1 0 0 1 0 . . . . . . . . . . . . . . . . . . . . . . . .
host_cpu_debug_internal 0x13000000 0 0 0 1 0 0 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
corperi 0x1a000000 0 0 0 1 1 0 1 0 . . . . . . . . . . . . . . . . . . . . . . . .
system_id 0x1a000000 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
host_base_sys_ctrl 0x1a010000 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_firewall_ppu 0x1a020000 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
app_systop_ppu 0x1a030000 0 0 0 1 1 0 1 0 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
app_dbgtop_ppu 0x1a040000 0 0 0 1 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
refclk_cnt_ctrl 0x1a200000 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
refclk_cnt_read 0x1a210000 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
refclk_cnt_ctl 0x1a220000 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
refclk_cnt0 0x1a230000 0 0 0 1 1 0 1 0 0 0 1 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
refclk_cnt1 0x1a240000 0 0 0 1 1 0 1 0 0 0 1 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
refclk_cnt2 0x1a250000 0 0 0 1 1 0 1 0 0 0 1 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
refclk_cnt3 0x1a260000 0 0 0 1 1 0 1 0 0 0 1 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
app_ns_wdog_ctrl 0x1a300000 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_ns_wdog_refresh 0x1a310000 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_secure_wdog_ctrl 0x1a320000 0 0 0 1 1 0 1 0 0 0 1 1 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
app_secure_wdog_refresh 0x1a330000 0 0 0 1 1 0 1 0 0 0 1 1 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
s32k_cnt_ctrl 0x1a400000 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
s32k_cnt_read 0x1a410000 0 0 0 1 1 0 1 0 0 1 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
s32k_cnt_ctl 0x1a420000 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
s32k_cnt0 0x1a430000 0 0 0 1 1 0 1 0 0 1 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
s32k_cnt1 0x1a440000 0 0 0 1 1 0 1 0 0 1 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
interrupt_router 0x1a500000 0 0 0 1 1 0 1 0 0 1 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
cor_uart0 0x1a510000 0 0 0 1 1 0 1 0 0 1 0 1 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
cor_uart1 0x1a520000 0 0 0 1 1 0 1 0 0 1 0 1 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_base 0x1a800000 0 0 0 1 1 0 1 0 1 0 0 0 . . . . . . . . . . . . . . . . . . . .
host_sys_fw_ctrl 0x1a800000 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_sysperi 0x1a810000 0 0 0 1 1 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_dbgperi 0x1a820000 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_aonperi 0x1a830000 0 0 0 1 1 0 1 0 1 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_envm 0x1a840000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_cvm 0x1a850000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_hostcpu 0x1a860000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_com 0x1a870000 0 0 0 1 1 0 1 0 1 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_mot 0x1a880000 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_hperi_slv 0x1a890000 0 0 0 1 1 0 1 0 1 0 0 0 1 0 0 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_sms_slv 0x1a8a0000 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_hperi_mst 0x1a8b0000 0 0 0 1 1 0 1 0 1 0 0 0 1 0 1 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_sms_mst 0x1a8c0000 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 0 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_evm 0x1a8d0000 0 0 0 1 1 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 . . . . . . . . . . . .
host_sys_fw_comp_debug 0x1a8e0000 0 0 0 1 1 0 1 0 1 0 0 0 1 1 1 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
mot_mhu_base 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
host_to_extsys0_mhu0 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2com0 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_receiver_app2mot0 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
com_mhu_receiver_app2com0 0x1b000000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_sender_mot2app0 0x1b010000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
com_mhu_sender_com2app0 0x1b010000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_com2app0 0x1b010000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
extsys0_to_host_mhu0 0x1b010000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2com1 0x1b020000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_receiver_app2mot1 0x1b020000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
com_mhu_receiver_app2com1 0x1b020000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
host_to_extsys0_mhu1 0x1b020000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_sender_mot2app1 0x1b030000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
com_mhu_sender_com2app1 0x1b030000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_com2app1 0x1b030000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
extsys0_to_host_mhu1 0x1b030000 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2mot0 0x1b040000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_receiver_se2mot0 0x1b040000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
com_mhu_receiver_se2com0 0x1b040000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
host_to_extsys1_mhu0 0x1b040000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_sender_mot2se0 0x1b050000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
com_mhu_sender_com2se0 0x1b050000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_mot2app0 0x1b050000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
extsys1_to_host_mhu0 0x1b050000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2mot1 0x1b060000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_receiver_se2mot1 0x1b060000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
com_mhu_receiver_se2com1 0x1b060000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
host_to_extsys1_mhu1 0x1b060000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . .
mot_mhu_sender_mot2se1 0x1b070000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . . . . . .
com_mhu_sender_com2se1 0x1b070000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_mot2app1 0x1b070000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . . . . . .
extsys1_to_host_mhu1 0x1b070000 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2se0 0x1b800000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
host_to_secenc_mhu0 0x1b800000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_se2app0 0x1b810000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
secenc_to_host_mhu0 0x1b810000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_mhu_sender_app2se1 0x1b820000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
host_to_secenc_mhu1 0x1b820000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . .
app_mhu_receiver_se2app1 0x1b830000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
secenc_to_host_mhu1 0x1b830000 0 0 0 1 1 0 1 1 1 0 0 0 0 0 1 1 0 0 0 0 . . . . . . . . . . . .
int_apbcom 0x1b900000 0 0 0 1 1 0 1 1 1 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_clustop_ppu 0x1bc00000 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_core_ppu0 0x1bc10000 0 0 0 1 1 0 1 1 1 1 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_gic 0x1c000000 0 0 0 1 1 1 0 0 . . . . . . . . . . . . . . . . . . . . . . . .
app_gic_distributor 0x1c010000 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
app_gic_cpu_interface 0x1c02f000 0 0 0 1 1 1 0 0 0 0 0 0 0 0 1 0 1 1 1 1 . . . . . . . . . . . .
app_gic_virt_interface_ctrl 0x1c04f000 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 0 1 1 1 1 . . . . . . . . . . . .
app_gic_virt_interface_ctrl_alias 0x1c050000 0 0 0 1 1 1 0 0 0 0 0 0 0 1 0 1 0 0 0 0 . . . . . . . . . . . .
app_gic_virt_cpu_interface 0x1c06f000 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 1 1 1 1 . . . . . . . . . . . .
app_stm500_stim 0x1d000000 0 0 0 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
app_main_nic_gpv 0x1e000000 0 0 0 1 1 1 1 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
secenc_ca 0x2f000000 0 0 1 0 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . .
secenc_cryptocell 0x2f000000 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . .
secenc_cryptocell_otp_ctrl 0x2f004000 0 0 1 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 . . . . . . . .
secenc_ram 0x30000000 0 0 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
secenc_ram0 0x30000000 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
secenc_ram1 0x30060000 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
hperi 0x40000000 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . . . .
hperi_sys_cfg 0x40000000 0 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
global_status 0x40000000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . .
envm_cfg 0x40010000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . .
sqi 0x40010000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
evm_cfg 0x40020000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . .
xspi_evm 0x40020000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . .
global_setup 0x40030000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . .
global_asic_ctrl 0x40030000 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 . . . . . . . . . .
global_pad_ctrl 0x40030400 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 . . . . . . . . . .
global_ioextender_mux_ctrl 0x40030800 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 . . . . . . . . . .
global_ioextender 0x40030c00 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 0 . . . . . . . .
crg 0x40030d00 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 1 1 0 1 . . . . . . . .
com_setup 0x40040000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . . . . . .
com_asic_ctrl 0x40040000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
com_mmio_ctrl 0x40040100 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . .
app_setup 0x40050000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . .
app_asic_ctrl 0x40050000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 . . . . . . . .
app_mmio_ctrl 0x40050200 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 1 . . . . . . . . .
mot_setup 0x40060000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . . . . . . . . . .
mot_asic_ctrl 0x40060000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . .
mot_mmio_ctrl 0x40060200 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 1 . . . . . . . . .
secenc_setup 0x40070000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 . . . . . . . . . . . . . . . .
secenc_asic_ctrl 0x40070000 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 . . . . . . . .
app_peri 0x40080000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . . . .
app_peri_hostcpu 0x40080000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
app_biss0 0x40080000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
app_biss1 0x40080100 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . .
app_biss_ctrl0 0x40080200 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . .
app_biss_ctrl1 0x40080220 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . .
app_endat0 0x40080240 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . . .
app_endat1 0x40080280 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 0 . . . . . .
app_endat_ctrl0 0x400802c0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 . . . .
app_endat_ctrl1 0x400802d0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 . . . .
app_uart0 0x40080300 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
app_uart1 0x40080340 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . .
app_i2c0 0x40080380 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . .
app_i2c1 0x400803c0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 1 . . . . . .
app_spi0 0x40080400 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . .
app_spi1 0x40080440 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . .
app_sqi0 0x40080480 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . .
app_sqi1 0x400804c0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . .
app_gpio 0x40080500 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . .
app_pio 0x40080600 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . .
app_blink 0x40080700 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 0 . . . . . .
app_blink_mixled 0x40080740 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 0 . . . . .
app_trigger_irq 0x40080760 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 0 1 1 . . . . .
app_trigger_irq_global 0x40080780 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 . . . . .
app_sync_timer 0x40080800 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 . . . . . . . . . .
app_sync_timer_global 0x40080c00 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 . . . . . . . . . .
app_dmac0 0x40081000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . . . . . . . .
dmac_ch0 0x40081100 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 . . . . .
app_dmac0_dmac_ch0 0x40081100 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 0 . . . . .
app_dmac0_dmac_ch1 0x40081120 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 . . . . .
dmac_ch1 0x40081120 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 0 1 . . . . .
app_dmac0_dmac_ch2 0x40081140 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 . . . . .
dmac_ch2 0x40081140 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 0 . . . . .
app_dmac0_dmac_ch3 0x40081160 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 . . . . .
dmac_ch3 0x40081160 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 0 1 0 1 1 . . . . .
dmac_reg 0x40081800 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 . . . . . . . . . . .
app_dmac0_dmac_reg 0x40081800 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 1 . . . . . . . . . . .
app_dmac1 0x40082000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 . . . . . . . . . . . .
app_dmac1_dmac_ch0 0x40082100 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 0 . . . . .
app_dmac1_dmac_ch1 0x40082120 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 0 1 . . . . .
app_dmac1_dmac_ch2 0x40082140 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 0 . . . . .
app_dmac1_dmac_ch3 0x40082160 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 1 0 1 1 . . . . .
app_dmac1_dmac_reg 0x40082800 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 1 . . . . . . . . . . .
app_hsc 0x40083000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 1 0 0 . . . . . . . . . .
app_peri_misc 0x40090000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . . . . . . . . . . . . .
sdio 0x40090000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 . . . . . . . . . . . . .
app_hsgmii 0x40092000 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 0 0 0 . . . . . . . .
app_gem_gxl 0x400c0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . . . . . . . . . . . .
gem_gxl_conf 0x400c0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . . .
gem_gxl_ram_ctrl 0x400c8000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 0 0 0 . . . . . . . . . . . .
app_can_fd 0x400d0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . . . . . . . . . . . .
app_crypt 0x400e0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 . . . . . . . . . . . . . .
app_ise 0x400e0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 . . . . . . . . . . .
app_ise_dma 0x400e0000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
app_mtgy 0x400e2000 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 . . . . . . . . . . . . .
mot 0x48000000 0 1 0 0 1 0 0 . . . . . . . . . . . . . . . . . . . . . . . . .
mot_intram0 0x48000000 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . .
mot_intram1 0x48010000 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . .
mot_intram2 0x48020000 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . .
mot_intram3 0x48030000 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . .
mot_dbg 0x48040000 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . . . .
mot_ctrl_local 0x48044000 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . . . .
mot_ram_ctrl 0x48044000 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 . . . . . . . . . . . .
peri0 0x49000000 0 1 0 0 1 0 0 1 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
mot_peri0 0x49000000 0 1 0 0 1 0 0 1 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
mot_ctrl 0x49000000 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
singen 0x49000040 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . .
sdmf0 0x49000100 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . .
sdmf1 0x49000200 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . .
sdmf2 0x49000300 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . .
mpwm 0x49000400 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . .
menc 0x49000600 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . . .
madc 0x49000680 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 0 . . . . . .
madc_seq0 0x49000700 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 . . . . . . . .
madc_seq1 0x49000800 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . .
madc_seq2 0x49000900 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . . . . .
madc_seq3 0x49000a00 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 . . . . . . . .
mot_hsc 0x49000c00 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . .
mot_plic 0x49010000 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . .
mot_peri1 0x49100000 0 1 0 0 1 0 0 1 0 0 0 1 . . . . . . . . . . . . . . . . . . . .
mot_peri 0x49200000 0 1 0 0 1 0 0 1 0 0 1 0 . . . . . . . . . . . . . . . . . . . .
mot_hperi 0x49200000 0 1 0 0 1 0 0 1 0 0 1 0 . . . . . . . . . . . . . . . . . . . .
mot_peri_base 0x49200000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 . . . . . . . . . . . . . . . .
mot_biss0 0x49200000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . .
mot_biss1 0x49200100 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . .
mot_biss_ctrl0 0x49200200 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . .
mot_biss_ctrl1 0x49200220 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . .
mot_endat0 0x49200240 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 . . . . . .
mot_endat1 0x49200280 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 . . . . . .
mot_endat_ctrl0 0x492002c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 0 . . . .
mot_endat_ctrl1 0x492002d0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 . . . .
mot_uart0 0x49200300 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . .
mot_uart1 0x49200340 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . .
mot_i2c0 0x49200380 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . .
mot_i2c1 0x492003c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 . . . . . .
mot_spi0 0x49200400 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . .
mot_spi1 0x49200440 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . .
mot_sqi0 0x49200480 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . .
mot_sqi1 0x492004c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . .
mot_gpio 0x49200500 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . .
mot_pio 0x49200600 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . .
mot_blink 0x49200700 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 . . . . . .
mot_blink_mixled 0x49200740 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 . . . . .
mot_trigger_irq 0x49200760 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 1 . . . . .
mot_trigger_irq_global 0x49200780 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 . . . . .
mot_wdg0 0x492007a0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 1 . . . . .
mot_wdg1 0x492007c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 . . . . .
mot_timer0 0x49200800 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . .
mot_timer1 0x49200880 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . .
mot_sync_timer 0x49200c00 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . .
mot_sync_timer_global 0x49201000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . .
mot_irq_router_top_decoder 0x49210000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 . . . . . . . . . . . . . . . .
cpu0_decoder 0x49210000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
mot_irq_router_cpu0_decoder 0x49210000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
mot_irq_router_cpu0_motion_exp_0 0x49210000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . .
mot_irq_router_cpu0_sync_0 0x49210010 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 . . . .
mot_irq_router_cpu0_mpwm_0 0x49210020 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 . . . .
mot_irq_router_cpu0_adc_0 0x49210030 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 1 1 . . . .
mot_irq_router_cpu0_adc_1 0x49210040 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 . . . .
mot_irq_router_cpu0_enc_0 0x49210050 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 1 . . . .
mot_irq_router_cpu0_enc_1 0x49210060 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 0 . . . .
mot_irq_router_cpu0_com_0 0x49210070 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 1 1 . . . .
mot_irq_router_cpu0_com_1 0x49210080 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 . . . .
mot_irq_router_cpu0_com_2 0x49210090 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 1 . . . .
mot_irq_router_cpu0_com_3 0x492100a0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 1 0 . . . .
mot_irq_router_cpu0_peri_0 0x492100c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 0 . . . . .
mot_irq_router_cpu0_peri_1 0x492100e0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 1 1 1 . . . . .
mot_irq_router_cpu0_peri_2 0x49210100 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 0 . . . . .
mot_irq_router_cpu0_peri_3 0x49210120 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 0 1 . . . . .
mot_irq_router_cpu0_shdint_0 0x49210140 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 . . . .
cpu1_decoder 0x49211000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . .
mot_irq_router_cpu1_decoder 0x49211000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . .
mot_irq_router_cpu1_motion_exp_0 0x49211000 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 0 . . . .
mot_irq_router_cpu1_sync_0 0x49211010 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 0 1 . . . .
mot_irq_router_cpu1_mpwm_0 0x49211020 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 0 . . . .
mot_irq_router_cpu1_adc_0 0x49211030 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 0 1 1 . . . .
mot_irq_router_cpu1_adc_1 0x49211040 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 0 . . . .
mot_irq_router_cpu1_enc_0 0x49211050 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 0 1 . . . .
mot_irq_router_cpu1_enc_1 0x49211060 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 0 . . . .
mot_irq_router_cpu1_com_0 0x49211070 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 . . . .
mot_irq_router_cpu1_com_1 0x49211080 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 . . . .
mot_irq_router_cpu1_com_2 0x49211090 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 1 . . . .
mot_irq_router_cpu1_com_3 0x492110a0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 1 0 . . . .
mot_irq_router_cpu1_peri_0 0x492110c0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 0 . . . . .
mot_irq_router_cpu1_peri_1 0x492110e0 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 . . . . .
mot_irq_router_cpu1_peri_2 0x49211100 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 . . . . .
mot_irq_router_cpu1_peri_3 0x49211120 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 0 1 . . . . .
mot_irq_router_cpu1_shdint_0 0x49211140 0 1 0 0 1 0 0 1 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 1 0 1 0 0 . . . .
secenc_peri 0x50000000 0 1 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
secenc_timer0 0x50000000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
secenc_timer1 0x50001000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . .
secenc_mhu_sender_se2app0 0x50003000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . .
seh_mhu0 0x50003000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . .
secenc_mhu_receiver_app2se0 0x50004000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . .
hse_mhu0 0x50004000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . .
secenc_mhu_sender_se2app1 0x50005000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . .
seh_mhu1 0x50005000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . .
secenc_mhu_receiver_app2se1 0x50006000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . . . . . .
hse_mhu1 0x50006000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . . . . . .
secenc_mhu_sender_se2com0 0x50010000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
sees0_mhu0 0x50010000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
secenc_mhu_receiver_com2se0 0x50011000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . .
es0se_mhu0 0x50011000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 . . . . . . . . . . . .
secenc_mhu_sender_se2com1 0x50012000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . . . . . .
sees0_mhu1 0x50012000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 . . . . . . . . . . . .
secenc_mhu_receiver_com2se1 0x50013000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . . . . . . . .
es0se_mhu1 0x50013000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 . . . . . . . . . . . .
secenc_mhu_sender_se2mot0 0x50014000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 . . . . . . . . . . . .
sees1_mhu0 0x50014000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 0 . . . . . . . . . . . .
secenc_mhu_receiver_mot2se0 0x50015000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 . . . . . . . . . . . .
es1se_mhu0 0x50015000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 0 1 . . . . . . . . . . . .
secenc_mhu_sender_se2mot1 0x50016000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . .
sees1_mhu1 0x50016000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 0 . . . . . . . . . . . .
secenc_mhu_receiver_mot2se1 0x50017000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . .
es1se_mhu1 0x50017000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 1 1 1 . . . . . . . . . . . .
secenc_otp0 0x50018000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 . . . . . . . . . . . . .
secenc_otp1 0x5001a000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . . . . . . . . .
secenc_otp_ctrl0 0x5001c000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 . . . . . . . .
secenc_otp_ctrl1 0x5001d000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 1 0 0 0 0 . . . . . . . .
secenc_asic_ctrl_sse 0x5001e000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 . . . . . . . . . . . .
secenc_hash 0x5001f000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 . . . . . . . .
secenc_sys2jtag 0x50020000 0 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . . .
secenc_sys_ctrl 0x50080000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 . . . . . . . . . . . .
secenc_watchdog 0x50081000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 . . . . . . . . . . . .
secenc_secenctop_ppu 0x5008d000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 1 . . . . . . . . . . . .
secenc_base_sys_ctrl 0x5008e000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 0 . . . . . . . . . . . .
secenc_soc_watchdog 0x5008f000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1 1 . . . . . . . . . . . .
secenc_uart 0x50090000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 . . . . . . . . . . . .
secenc_secenc_ram_ctrl 0x50091000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 . . . . . . . . . . . .
secenc_ram_ctrl 0x50091000 0 1 0 1 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 1 . . . . . . . . . . . .
secenc_fw_ctrl 0x50200000 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
secenc_fw_comp_fc1 0x50210000 0 1 0 1 0 0 0 0 0 0 1 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
sms 0x60000000 0 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
sms_tbuf_rx_access 0x60000000 0 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . .
sms_rx_ram 0x60000000 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . .
secenc_host_access_rgn 0x60000000 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
sms_tbuf_tx_access 0x60040000 0 1 1 0 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . .
sms_tx_ram 0x60040000 0 1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 . . . . . . . . . . . . . . . .
sms_ac_ram 0x60080000 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
sms_ac_mem 0x60080000 0 1 1 0 0 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . . . . . . . . .
sms_cfg_sim_msg_combined 0x60100000 0 1 1 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . .
dpm_cfg 0x60138000 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 . . . . . . . . . . . . . . .
dpm_sys_cfg 0x60138000 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 . . . . . . . . . . . . . . .
dpm0 0x60138400 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 0 . . . . . . . .
dpm1 0x60138500 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 0 1 . . . . . . . .
hif_io_ctrl 0x60138600 0 1 1 0 0 0 0 0 0 0 0 1 0 0 1 1 1 0 0 0 0 1 1 0 0 0 . . . . . .
idpm_tb 0x60140000 0 1 1 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . . . .
idpm_sys_tb 0x60140000 0 1 1 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . . . .
sim_msg_tb_regs 0x60140000 0 1 1 0 0 0 0 0 0 0 0 1 0 1 . . . . . . . . . . . . . . . . . .
idpm_cfg 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . . . . .
idpm_sms_combined 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 . . . . . . . . . . . . . . . . . . .
sms_cfg 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . . . . . . . . . . . .
sms_ctrl 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 . . . . . . . . . . . . . . . . . .
sms_host_cfg_decoder 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 . . . . . . . . . . . . . . . .
sms_host_hsc 0x60180000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . .
sms_host_irq 0x60180400 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . .
sms_host_irq_logic 0x60180400 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . .
sms_host_tba 0x60181000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . .
sms_host_cfg_regs 0x60182000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 . . . .
sms_host_irq_router_top_decoder 0x6018f000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 . . . . . . . . . . . .
sms_host_irq_router_pcie_decoder 0x6018f000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 . . . . . . . . . . . .
sms_host_irq_router_pcie_int_a_0 0x6018f000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 . . . .
sms_device_cfg_decoder 0x601a0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 . . . . . . . . . . . . . . . . .
sms_device_irq_router_top_decoder 0x601a0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 . . . . . . . . . . . . . . . .
ada_decoder 0x601a0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 . . . . . . . . . . . .
sms_device_irq_router_ada_decoder 0x601a0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 . . . . . . . . . . . .
sms_device_irq_router_ada_plic_irq 0x601a0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . .
cda_rx_decoder 0x601a1000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 . . . . . . . . . . . .
sms_device_irq_router_cda_rx_decoder 0x601a1000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 . . . . . . . . . . . .
sms_device_irq_router_cda_rx_plic_irq 0x601a1000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 0 1 0 0 0 0 0 0 0 0 . . . .
cda_tx_decoder 0x601a2000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 . . . . . . . . . . . .
sms_device_irq_router_cda_tx_decoder 0x601a2000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 . . . . . . . . . . . .
sms_device_irq_router_cda_tx_plic_irq 0x601a2000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 0 0 0 0 0 0 0 0 0 . . . .
iol_decoder 0x601a3000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 . . . . . . . . . . . .
sms_device_irq_router_iol_decoder 0x601a3000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 . . . . . . . . . . . .
sms_device_irq_router_iol_plic_irq 0x601a3000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 0 0 0 . . . .
sms_device_irq_logic 0x601b0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
sms_device_irq 0x601b0000 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . .
sms_tbuf_rx 0x601b0200 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 0 1 . . . . . . . . .
sms_tbuf_tx 0x601b0400 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 0 . . . . . . . . .
sms_device_tba 0x601b0600 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 0 . . . . . . . .
sms_device_cfg_regs 0x601b0700 0 1 1 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 0 0 0 1 1 1 0 0 0 0 . . . .
dpm_ram_ctrl 0x601c1000 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 1 . . . . . . . . . . . .
intram0_ram_ctrl 0x601c2000 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 0 . . . . . . . . . . . .
intram1_ram_ctrl 0x601c3000 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 0 1 1 . . . . . . . . . . . .
intram2_ram_ctrl 0x601c4000 0 1 1 0 0 0 0 0 0 0 0 1 1 1 0 0 0 1 0 0 . . . . . . . . . . . .
sms_host_window 0x60200000 0 1 1 0 0 0 0 0 0 0 1 0 0 0 . . . . . . . . . . . . . . . . . .
sms_host_window_ac 0x60200000 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 . . . . . . . . . . . . . . . .
sms_host_window_rx 0x60210000 0 1 1 0 0 0 0 0 0 0 1 0 0 0 0 1 . . . . . . . . . . . . . . . .
sms_host_window_tx 0x60220000 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 0 . . . . . . . . . . . . . . . .
sms_host_window_hs 0x60230000 0 1 1 0 0 0 0 0 0 0 1 0 0 0 1 1 . . . . . . . . . . . . . . . .
sms_com_intram0 0x66000000 0 1 1 0 0 1 1 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
sms_com_intram1 0x66100000 0 1 1 0 0 1 1 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . .
sms_com_intram2 0x66200000 0 1 1 0 0 1 1 0 0 0 1 0 . . . . . . . . . . . . . . . . . . . .
msi2irq_decoder 0x68000000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . . . .
msi2irq_0 0x68000000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 . . . .
msi2irq_1 0x68000010 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 . . . .
msi2irq_2 0x68000020 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 . . . .
msi2irq_3 0x68000030 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 . . . .
pcie_dma_table_ram 0x68010000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 . . . . . . . . . . . .
pcie_regs_decoder 0x68020000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . .
pcie_regs 0x68020000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . .
pcie_sys_ctrl 0x68020000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . .
irq2msi_cfg 0x68030000 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 . . . .
msi2irq_0_cfg 0x68030020 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 1 . . . . .
msi2irq_1_cfg 0x68030040 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 0 . . . . .
msi2irq_2_cfg 0x68030060 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 1 1 . . . . .
msi2irq_3_cfg 0x68030080 0 1 1 0 1 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 1 0 0 . . . . .
pcie_phy_cfg 0x6f000000 0 1 1 0 1 1 1 1 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . .
pcie_management 0x6f800000 0 1 1 0 1 1 1 1 1 . . . . . . . . . . . . . . . . . . . . . . .
pcie_ep_cfg 0x6f800000 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_rp_cfg 0x6f800000 0 1 1 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_local_mgmt 0x6f900000 0 1 1 0 1 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_rp_cfg_rw 0x6fa00000 0 1 1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_axi_cfg 0x6fc00000 0 1 1 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_dma 0x6fe00000 0 1 1 0 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . .
pcie_rp 0x70000000 0 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . .
pcie_rp_mem 0x70100000 0 1 1 1 0 0 0 0 0 0 0 1 . . . . . . . . . . . . . . . . . . . .
evm 0x80000000 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ext_xspi 0x80000000 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
secenc_fw_base 0xa0400000 1 0 1 0 0 0 0 0 0 1 0 . . . . . . . . . . . . . . . . . . . . .
com_ext_xspi 0xe0000000 1 1 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
secenc_cm0_private_peripherals 0xe0000000 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . . .
secenc_cm0_scs 0xe000e000 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 0 . . . . . . . . . . . .
ada_internal_itcm_start 0xee000000 1 1 1 0 1 1 1 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
iol_internal_itcm_start 0xee000000 1 1 1 0 1 1 1 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
cada_internal_itcm_start 0xee000000 1 1 1 0 1 1 1 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
ada_internal_dtcm_start 0xf0000000 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
iol_internal_dtcm_start 0xf0000000 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .
cada_internal_dtcm_start 0xf0000000 1 1 1 1 0 0 0 0 0 0 0 0 0 . . . . . . . . . . . . . . . . . . .

Base Address Area: secenc_rom

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R secenc_rom_base
1-7ffe 4-1fff8 -  reserved
7fff 1fffc R secenc_rom_end

secenc_rom_base
SecEnc internal ROM start address
Area size: 128kB
R
Address : 0x00000000
Bits Name Description
31 - 0 secenc_rom_base


secenc_rom_end
SecEnc internal ROM end address
R
Address : 0x0001fffc
Bits Name Description
31 - 0 secenc_rom_end



Base Address Area: iol_ram_ctrl, com_iol_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_6_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_6_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_6_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_6_mbist_power3
4 10 R/W gen_ram_ctrl_netx22xx_6_mbist_power4
5 14 R/W gen_ram_ctrl_netx22xx_6_mbist_power5
6-1ff 18-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_6_ecc0
201-27f 804-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_6_ecc_status_corr0
281-2ff a04-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_6_ecc_status_noncorr0
301-37f c04-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_6_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_6_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_6_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_6_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_6_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_6_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x00080000
Address@com_iol_ram_ctrl : 0x06c80000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x00080004
Address@com_iol_ram_ctrl : 0x06c80004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.iccm.iccm.mem_bank[0].iccm.iccm_bank.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x00080008
Address@com_iol_ram_ctrl : 0x06c80008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.iccm.iccm.mem_bank[1].iccm.iccm_bank.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x0008000c
Address@com_iol_ram_ctrl : 0x06c8000c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_mbist_power4
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.iccm.iccm.mem_bank[2].iccm.iccm_bank.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x00080010
Address@com_iol_ram_ctrl : 0x06c80010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_mbist_power5
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.iol_i.el2_i.mem.iccm.iccm.mem_bank[3].iccm.iccm_bank.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@iol_ram_ctrl : 0x00080014
Address@com_iol_ram_ctrl : 0x06c80014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_6_ecc0
ECC control and status register
Dummy register, no ECC RAMs in the design.
R/W
0x00000000
Address@iol_ram_ctrl : 0x00080800
Address@com_iol_ram_ctrl : 0x06c80800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_6_ecc_status_corr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address@iol_ram_ctrl : 0x00080a00
Address@com_iol_ram_ctrl : 0x06c80a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_6_ecc_status_noncorr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address@iol_ram_ctrl : 0x00080c00
Address@com_iol_ram_ctrl : 0x06c80c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_6_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@iol_ram_ctrl : 0x00080e00
Address@com_iol_ram_ctrl : 0x06c80e00
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_6_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_6_irq_raw_reg0).
R/W
0x00000000
Address@iol_ram_ctrl : 0x00080e40
Address@com_iol_ram_ctrl : 0x06c80e40
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_6_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_6_irq_raw_reg0
R/W
0x00000000
Address@iol_ram_ctrl : 0x00080e80
Address@com_iol_ram_ctrl : 0x06c80e80
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_6_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 8 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_0_err_ecc_correctable
  2 : irq_reg0-mem_0_mbist_or_init_finished
  3 : irq_reg0-mem_1_mbist_or_init_finished
  4 : irq_reg0-mem_2_mbist_or_init_finished
  5 : irq_reg0-mem_3_mbist_or_init_finished
  6 : irq_reg0-mem_4_mbist_or_init_finished
  7 : irq_reg0-mem_5_mbist_or_init_finished
  8 : no active IRQ
R/W
0x00000000
Address@iol_ram_ctrl : 0x00080ec0
Address@com_iol_ram_ctrl : 0x06c80ec0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_6_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address@iol_ram_ctrl : 0x00080efc
Address@com_iol_ram_ctrl : 0x06c80efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: iol_config, com_iol_config

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W el2_power_mgmt
1 4 R el2_power_mgmt_info
2 8 R/W el2_rst_ctrl
3 c R/W el2_rst_vec
4 10 R/W el2_nmi_vec
5 14 W el2_set_softint
6 18 W el2_reset_softint
7 1c R el2_softint
8-3f 20-fc -  reserved

el2_power_mgmt
EL2 power management register
R/W
0x00000004
Address@iol_config : 0x00081000
Address@com_iol_config : 0x06c81000
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "1"
halt_req
Assert to halt CPU
halt_req: Request CPU to halt
1 0
-
 reserved
0 "0"
run_req
Assert to request CPU to run.
run_req : Request CPU to run


el2_power_mgmt_info
EL2 power management info register
R
Address@iol_config : 0x00081004
Address@com_iol_config : 0x06c81004
Bits Name Description
31 - 9 -
 reserved
8 wdg_active
High indicates that the IOL local watchdog is running
7 -
 reserved
6 debug_mode_status
High indicates thread is in debug mode and
shouldn't be halted.
debug_mode_status == 1 : Thread is in debug mode.
5 -
 reserved
4 halt_status
High indicates thread is halted.
halt_status == 1 : Thread is halted.
3 -
 reserved
2 halt_ack
High if EL2 thread acknowledges halt request
halt_ack == 1 : Thread acknowledges halt request
1 -
 reserved
0 run_ack
High if EL2 thread acknowledges run request
run_ack == 1 : Thread acknowledges run request


el2_rst_ctrl
EL2 reset control register
R/W
0x00000000
Address@iol_config : 0x00081008
Address@com_iol_config : 0x06c81008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
cpu_reset_n
CPU reset, active low. Reset and NMI vector must be
stable before release.


el2_rst_vec
EL2 reset vector register
R/W
0x00000000
Address@iol_config : 0x0008100c
Address@com_iol_config : 0x06c8100c
Bits Reset value Name Description
31 - 0 0x0
reset_vector
start address after power-on-reset
Must be stable several cycles before reset release!


el2_nmi_vec
EL2 non-maskable interrupt vector register
R/W
0x00000000
Address@iol_config : 0x00081010
Address@com_iol_config : 0x06c81010
Bits Reset value Name Description
31 - 0 0x0
nmi_vector
jump-address of non-maskable interrupt
Must be stable several cycles before reset release!


el2_set_softint
EL2 set software interrupt for thread 0
W
0x00000000
Address@iol_config : 0x00081014
Address@com_iol_config : 0x06c81014
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
thread_0
Set software interrupt for thread 0
this bit will be reset automatically by hardware


el2_reset_softint
EL2 reset software interrupt for thread 0
W
0x00000000
Address@iol_config : 0x00081018
Address@com_iol_config : 0x06c81018
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
thread_0
Reset software interrupt for thread 0
this bit will be reset automatically by hardware


el2_softint
EL2 read status of software interrupt for thread 0
R
Address@iol_config : 0x0008101c
Address@com_iol_config : 0x06c8101c
Bits Name Description
31 - 1 -
 reserved
0 thread_0
Status of software interrupt for thread 0



Base Address Area: iol_timer, ada_timer, cada_timer, com_cda_rx_timer, com_cda_tx_timer, com_ada_timer, com_iol_timer

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W rv_timer_ctrl
1 4 R/W rv_timer_cfg
2 8 R/W rv_timer_lower
3 c R/W rv_timer_upper
4 10 R/W rv_timer_intr_test
5-7 14-1c -  reserved
8 20 R/W rv_timer_compare_0_lower
9 24 R/W rv_timer_compare_0_upper
a 28 R/W rv_timer_intr_0_enable
b 2c R rv_timer_intr_0_state
c 30 R/W rv_timer_compare_1_lower
d 34 R/W rv_timer_compare_1_upper
e 38 R/W rv_timer_intr_1_enable
f 3c R rv_timer_intr_1_state
10 40 R/W rv_timer_compare_2_lower
11 44 R/W rv_timer_compare_2_upper
12 48 R/W rv_timer_intr_2_enable
13 4c R rv_timer_intr_2_state
14 50 R/W rv_timer_compare_3_lower
15 54 R/W rv_timer_compare_3_upper
16 58 R/W rv_timer_intr_3_enable
17 5c R rv_timer_intr_3_state
18 60 R/W rv_timer_compare_4_lower
19 64 R/W rv_timer_compare_4_upper
1a 68 R/W rv_timer_intr_4_enable
1b 6c R rv_timer_intr_4_state
1c 70 R/W rv_timer_compare_5_lower
1d 74 R/W rv_timer_compare_5_upper
1e 78 R/W rv_timer_intr_5_enable
1f 7c R rv_timer_intr_5_state
20 80 R/W rv_timer_compare_6_lower
21 84 R/W rv_timer_compare_6_upper
22 88 R/W rv_timer_intr_6_enable
23 8c R rv_timer_intr_6_state
24 90 R/W rv_timer_compare_7_lower
25 94 R/W rv_timer_compare_7_upper
26 98 R/W rv_timer_intr_7_enable
27 9c R rv_timer_intr_7_state
28-3f a0-fc -  reserved

rv_timer_ctrl
RV_TIMER Control Register
R/W
0x00000000
Address@iol_timer : 0x00081100
Address@ada_timer : 0x00101100
Address@cada_timer : 0x00110800
Address@com_cda_rx_timer : 0x06710800
Address@com_cda_tx_timer : 0x06910800
Address@com_ada_timer : 0x06b01100
Address@com_iol_timer : 0x06c81100
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
active
If 1, timer operates


rv_timer_cfg
RV_TIMER Configuration for timer
Change note: the prescale bitfield has no effect in the netx22xx_mpw variant (bug J210051-660)
R/W
0x00010000
Address@iol_timer : 0x00081104
Address@ada_timer : 0x00101104
Address@cada_timer : 0x00110804
Address@com_cda_rx_timer : 0x06710804
Address@com_cda_tx_timer : 0x06910804
Address@com_ada_timer : 0x06b01104
Address@com_iol_timer : 0x06c81104
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000001"
step
Incremental value for each tick
15 - 12 0
-
 reserved
11 - 0 0x0
prescale
Prescaler to generate tick


rv_timer_lower
RV_TIMER Timer value Lower
R/W
0x00000000
Address@iol_timer : 0x00081108
Address@ada_timer : 0x00101108
Address@cada_timer : 0x00110808
Address@com_cda_rx_timer : 0x06710808
Address@com_cda_tx_timer : 0x06910808
Address@com_ada_timer : 0x06b01108
Address@com_iol_timer : 0x06c81108
Bits Reset value Name Description
31 - 0 0x0
v
Timer value [31:0]
Writes for setting the timer value are only accepted if timer_ctrl.active==0
writable, but can also be changed by hardware


rv_timer_upper
RV_TIMER Timer value Upper
R/W
0x00000000
Address@iol_timer : 0x0008110c
Address@ada_timer : 0x0010110c
Address@cada_timer : 0x0011080c
Address@com_cda_rx_timer : 0x0671080c
Address@com_cda_tx_timer : 0x0691080c
Address@com_ada_timer : 0x06b0110c
Address@com_iol_timer : 0x06c8110c
Bits Reset value Name Description
31 - 0 0x0
v
Timer value [63:32]
Writes for setting the timer value are only accepted if timer_ctrl.active==0
writable, but can also be changed by hardware


rv_timer_intr_test
RV_TIMER Timer Interrupt test register
Change note: these software interrupts are not maskable by intr_*_enable in the netx22xx_mpw variant (bug J210051-662)
R/W
0x00000000
Address@iol_timer : 0x00081110
Address@ada_timer : 0x00101110
Address@cada_timer : 0x00110810
Address@com_cda_rx_timer : 0x06710810
Address@com_cda_tx_timer : 0x06910810
Address@com_ada_timer : 0x06b01110
Address@com_iol_timer : 0x06c81110
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
t
Write bit[N] to trigger interrupt N
Clear bit[N] to clear forced interrupt N


rv_timer_compare_0_lower
RV_TIMER Compare 0 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081120
Address@ada_timer : 0x00101120
Address@cada_timer : 0x00110820
Address@com_cda_rx_timer : 0x06710820
Address@com_cda_tx_timer : 0x06910820
Address@com_ada_timer : 0x06b01120
Address@com_iol_timer : 0x06c81120
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 0 [31:0]


rv_timer_compare_0_upper
RV_TIMER Compare 0 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081124
Address@ada_timer : 0x00101124
Address@cada_timer : 0x00110824
Address@com_cda_rx_timer : 0x06710824
Address@com_cda_tx_timer : 0x06910824
Address@com_ada_timer : 0x06b01124
Address@com_iol_timer : 0x06c81124
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 0 [63:32]


rv_timer_intr_0_enable
RV_TIMER Interrupt 0 Enable
R/W
0x00000000
Address@iol_timer : 0x00081128
Address@ada_timer : 0x00101128
Address@cada_timer : 0x00110828
Address@com_cda_rx_timer : 0x06710828
Address@com_cda_tx_timer : 0x06910828
Address@com_ada_timer : 0x06b01128
Address@com_iol_timer : 0x06c81128
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 0


rv_timer_intr_0_state
RV_TIMER Interrupt 0 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008112c
Address@ada_timer : 0x0010112c
Address@cada_timer : 0x0011082c
Address@com_cda_rx_timer : 0x0671082c
Address@com_cda_tx_timer : 0x0691082c
Address@com_ada_timer : 0x06b0112c
Address@com_iol_timer : 0x06c8112c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 0 status for timer


rv_timer_compare_1_lower
RV_TIMER Compare 1 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081130
Address@ada_timer : 0x00101130
Address@cada_timer : 0x00110830
Address@com_cda_rx_timer : 0x06710830
Address@com_cda_tx_timer : 0x06910830
Address@com_ada_timer : 0x06b01130
Address@com_iol_timer : 0x06c81130
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 1 [31:0]


rv_timer_compare_1_upper
RV_TIMER Compare 1 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081134
Address@ada_timer : 0x00101134
Address@cada_timer : 0x00110834
Address@com_cda_rx_timer : 0x06710834
Address@com_cda_tx_timer : 0x06910834
Address@com_ada_timer : 0x06b01134
Address@com_iol_timer : 0x06c81134
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 1 [63:32]


rv_timer_intr_1_enable
RV_TIMER Interrupt 1 Enable
R/W
0x00000000
Address@iol_timer : 0x00081138
Address@ada_timer : 0x00101138
Address@cada_timer : 0x00110838
Address@com_cda_rx_timer : 0x06710838
Address@com_cda_tx_timer : 0x06910838
Address@com_ada_timer : 0x06b01138
Address@com_iol_timer : 0x06c81138
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 1


rv_timer_intr_1_state
RV_TIMER Interrupt 1 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008113c
Address@ada_timer : 0x0010113c
Address@cada_timer : 0x0011083c
Address@com_cda_rx_timer : 0x0671083c
Address@com_cda_tx_timer : 0x0691083c
Address@com_ada_timer : 0x06b0113c
Address@com_iol_timer : 0x06c8113c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 1 status for timer


rv_timer_compare_2_lower
RV_TIMER Compare 2 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081140
Address@ada_timer : 0x00101140
Address@cada_timer : 0x00110840
Address@com_cda_rx_timer : 0x06710840
Address@com_cda_tx_timer : 0x06910840
Address@com_ada_timer : 0x06b01140
Address@com_iol_timer : 0x06c81140
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 2 [31:0]


rv_timer_compare_2_upper
RV_TIMER Compare 2 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081144
Address@ada_timer : 0x00101144
Address@cada_timer : 0x00110844
Address@com_cda_rx_timer : 0x06710844
Address@com_cda_tx_timer : 0x06910844
Address@com_ada_timer : 0x06b01144
Address@com_iol_timer : 0x06c81144
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 2 [63:32]


rv_timer_intr_2_enable
RV_TIMER Interrupt 2 Enable
R/W
0x00000000
Address@iol_timer : 0x00081148
Address@ada_timer : 0x00101148
Address@cada_timer : 0x00110848
Address@com_cda_rx_timer : 0x06710848
Address@com_cda_tx_timer : 0x06910848
Address@com_ada_timer : 0x06b01148
Address@com_iol_timer : 0x06c81148
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 2


rv_timer_intr_2_state
RV_TIMER Interrupt 2 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008114c
Address@ada_timer : 0x0010114c
Address@cada_timer : 0x0011084c
Address@com_cda_rx_timer : 0x0671084c
Address@com_cda_tx_timer : 0x0691084c
Address@com_ada_timer : 0x06b0114c
Address@com_iol_timer : 0x06c8114c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 2 status for timer


rv_timer_compare_3_lower
RV_TIMER Compare 3 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081150
Address@ada_timer : 0x00101150
Address@cada_timer : 0x00110850
Address@com_cda_rx_timer : 0x06710850
Address@com_cda_tx_timer : 0x06910850
Address@com_ada_timer : 0x06b01150
Address@com_iol_timer : 0x06c81150
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 3 [31:0]


rv_timer_compare_3_upper
RV_TIMER Compare 3 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081154
Address@ada_timer : 0x00101154
Address@cada_timer : 0x00110854
Address@com_cda_rx_timer : 0x06710854
Address@com_cda_tx_timer : 0x06910854
Address@com_ada_timer : 0x06b01154
Address@com_iol_timer : 0x06c81154
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 3 [63:32]


rv_timer_intr_3_enable
RV_TIMER Interrupt 3 Enable
R/W
0x00000000
Address@iol_timer : 0x00081158
Address@ada_timer : 0x00101158
Address@cada_timer : 0x00110858
Address@com_cda_rx_timer : 0x06710858
Address@com_cda_tx_timer : 0x06910858
Address@com_ada_timer : 0x06b01158
Address@com_iol_timer : 0x06c81158
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 3


rv_timer_intr_3_state
RV_TIMER Interrupt 3 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008115c
Address@ada_timer : 0x0010115c
Address@cada_timer : 0x0011085c
Address@com_cda_rx_timer : 0x0671085c
Address@com_cda_tx_timer : 0x0691085c
Address@com_ada_timer : 0x06b0115c
Address@com_iol_timer : 0x06c8115c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 3 status for timer


rv_timer_compare_4_lower
RV_TIMER Compare 4 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081160
Address@ada_timer : 0x00101160
Address@cada_timer : 0x00110860
Address@com_cda_rx_timer : 0x06710860
Address@com_cda_tx_timer : 0x06910860
Address@com_ada_timer : 0x06b01160
Address@com_iol_timer : 0x06c81160
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 4 [31:0]


rv_timer_compare_4_upper
RV_TIMER Compare 4 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081164
Address@ada_timer : 0x00101164
Address@cada_timer : 0x00110864
Address@com_cda_rx_timer : 0x06710864
Address@com_cda_tx_timer : 0x06910864
Address@com_ada_timer : 0x06b01164
Address@com_iol_timer : 0x06c81164
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 4 [63:32]


rv_timer_intr_4_enable
RV_TIMER Interrupt 4 Enable
R/W
0x00000000
Address@iol_timer : 0x00081168
Address@ada_timer : 0x00101168
Address@cada_timer : 0x00110868
Address@com_cda_rx_timer : 0x06710868
Address@com_cda_tx_timer : 0x06910868
Address@com_ada_timer : 0x06b01168
Address@com_iol_timer : 0x06c81168
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 4


rv_timer_intr_4_state
RV_TIMER Interrupt 4 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008116c
Address@ada_timer : 0x0010116c
Address@cada_timer : 0x0011086c
Address@com_cda_rx_timer : 0x0671086c
Address@com_cda_tx_timer : 0x0691086c
Address@com_ada_timer : 0x06b0116c
Address@com_iol_timer : 0x06c8116c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 4 status for timer


rv_timer_compare_5_lower
RV_TIMER Compare 5 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081170
Address@ada_timer : 0x00101170
Address@cada_timer : 0x00110870
Address@com_cda_rx_timer : 0x06710870
Address@com_cda_tx_timer : 0x06910870
Address@com_ada_timer : 0x06b01170
Address@com_iol_timer : 0x06c81170
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 5 [31:0]


rv_timer_compare_5_upper
RV_TIMER Compare 5 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081174
Address@ada_timer : 0x00101174
Address@cada_timer : 0x00110874
Address@com_cda_rx_timer : 0x06710874
Address@com_cda_tx_timer : 0x06910874
Address@com_ada_timer : 0x06b01174
Address@com_iol_timer : 0x06c81174
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 5 [63:32]


rv_timer_intr_5_enable
RV_TIMER Interrupt 5 Enable
R/W
0x00000000
Address@iol_timer : 0x00081178
Address@ada_timer : 0x00101178
Address@cada_timer : 0x00110878
Address@com_cda_rx_timer : 0x06710878
Address@com_cda_tx_timer : 0x06910878
Address@com_ada_timer : 0x06b01178
Address@com_iol_timer : 0x06c81178
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 5


rv_timer_intr_5_state
RV_TIMER Interrupt 5 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008117c
Address@ada_timer : 0x0010117c
Address@cada_timer : 0x0011087c
Address@com_cda_rx_timer : 0x0671087c
Address@com_cda_tx_timer : 0x0691087c
Address@com_ada_timer : 0x06b0117c
Address@com_iol_timer : 0x06c8117c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 5 status for timer


rv_timer_compare_6_lower
RV_TIMER Compare 6 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081180
Address@ada_timer : 0x00101180
Address@cada_timer : 0x00110880
Address@com_cda_rx_timer : 0x06710880
Address@com_cda_tx_timer : 0x06910880
Address@com_ada_timer : 0x06b01180
Address@com_iol_timer : 0x06c81180
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 6 [31:0]


rv_timer_compare_6_upper
RV_TIMER Compare 6 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081184
Address@ada_timer : 0x00101184
Address@cada_timer : 0x00110884
Address@com_cda_rx_timer : 0x06710884
Address@com_cda_tx_timer : 0x06910884
Address@com_ada_timer : 0x06b01184
Address@com_iol_timer : 0x06c81184
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 6 [63:32]


rv_timer_intr_6_enable
RV_TIMER Interrupt 6 Enable
R/W
0x00000000
Address@iol_timer : 0x00081188
Address@ada_timer : 0x00101188
Address@cada_timer : 0x00110888
Address@com_cda_rx_timer : 0x06710888
Address@com_cda_tx_timer : 0x06910888
Address@com_ada_timer : 0x06b01188
Address@com_iol_timer : 0x06c81188
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 6


rv_timer_intr_6_state
RV_TIMER Interrupt 6 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008118c
Address@ada_timer : 0x0010118c
Address@cada_timer : 0x0011088c
Address@com_cda_rx_timer : 0x0671088c
Address@com_cda_tx_timer : 0x0691088c
Address@com_ada_timer : 0x06b0118c
Address@com_iol_timer : 0x06c8118c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 6 status for timer


rv_timer_compare_7_lower
RV_TIMER Compare 7 value lower
R/W
0xffffffff
Address@iol_timer : 0x00081190
Address@ada_timer : 0x00101190
Address@cada_timer : 0x00110890
Address@com_cda_rx_timer : 0x06710890
Address@com_cda_tx_timer : 0x06910890
Address@com_ada_timer : 0x06b01190
Address@com_iol_timer : 0x06c81190
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 7 [31:0]


rv_timer_compare_7_upper
RV_TIMER Compare 7 value upper
R/W
0xffffffff
Address@iol_timer : 0x00081194
Address@ada_timer : 0x00101194
Address@cada_timer : 0x00110894
Address@com_cda_rx_timer : 0x06710894
Address@com_cda_tx_timer : 0x06910894
Address@com_ada_timer : 0x06b01194
Address@com_iol_timer : 0x06c81194
Bits Reset value Name Description
31 - 0 0xffffffff
v
Timer compare value 7 [63:32]


rv_timer_intr_7_enable
RV_TIMER Interrupt 7 Enable
R/W
0x00000000
Address@iol_timer : 0x00081198
Address@ada_timer : 0x00101198
Address@cada_timer : 0x00110898
Address@com_cda_rx_timer : 0x06710898
Address@com_cda_tx_timer : 0x06910898
Address@com_ada_timer : 0x06b01198
Address@com_iol_timer : 0x06c81198
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ie
Interrupt Enable for mtimecmp 7


rv_timer_intr_7_state
RV_TIMER Interrupt 7 State
Change note: the netx22xx_mpw variant shows the masked state instead of the correct raw state (bug J210051-661)
R
Address@iol_timer : 0x0008119c
Address@ada_timer : 0x0010119c
Address@cada_timer : 0x0011089c
Address@com_cda_rx_timer : 0x0671089c
Address@com_cda_tx_timer : 0x0691089c
Address@com_ada_timer : 0x06b0119c
Address@com_iol_timer : 0x06c8119c
Bits Name Description
31 - 1 -
 reserved
0 is
Interrupt 7 status for timer



Base Address Area: iol_spi, com_spi0, com_spi1, com_iol_spi, app_spi0, app_spi1, mot_spi0, mot_spi1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W spi_cr0
1 4 R/W spi_cr1
2 8 R/W spi_dr
3 c R spi_sr
4 10 -  reserved
5 14 R/W spi_imsc
6 18 R spi_ris
7 1c R spi_mis
8 20 R/W spi_icr
9 24 -  reserved
a 28 R/W spi_dmacr
b 2c R/W spi_pio_mode
c 30 R/W spi_data_register
d 34 R spi_status_register
e 38 R/W spi_control_register
f 3c R/W spi_interrupt_control_register

spi_cr0
SPI control register 0
Change note: in the 'netx22xx_mpw' the SPI module of the IOL subsystem is not available, due to a fault in the interconnect decoder.
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
R/W
0x80080007
Address@iol_spi : 0x00081100
Address@com_spi0 : 0x06400080
Address@com_spi1 : 0x064000c0
Address@com_iol_spi : 0x06c81100
Address@app_spi0 : 0x40080400
Address@app_spi1 : 0x40080440
Address@mot_spi0 : 0x49200400
Address@mot_spi1 : 0x49200440
Bits Reset value Name Description
31 "1"
netx100_comp
Use netx100/500-compatible SPI mode:
0: start transfer after writing data
1: start transfer after setting CR_write or CR_read
30 - 29 0
-
 reserved
28 "0"
slave_sig_early
Generate MISO in slave mode 1 SCK clock edge earlier than defined in the SPI specification.
This is to compensate pad or sampling delays on fast data rates. However, hold timing problems could
come up as MISO is generated very fast after the sampling SPI clock edge.
If filter_in is enabled, it takes at least 3 system clocks to generate MISO after SCK.
If filter_in is disabled, it takes at least 2 system clocks to generate MISO after SCK.
27 "0"
filter_in
Receive data is sampled every 10ns (100MHz system clock). If this bit is set, the
stored receive value will be the result of a majority decision of the three sampling points
around a SPI-clock edge (if two or more '1s! were sampled a '1' will be stored, else a '0' will
be stored. In slave mode chip-select and SCK edges will also be detected by oversampling if this bit is set:
An edge will be detected if the majority-result of 3 subsequent sampled values toggles.
Input filtering should be used for sck_muladd<=0x200 (i.e. below 12.5MHz). Stable signal phases are too
short with higher frequencies and input filtering cannot be used.
26 0
-
 reserved
25 - 24 "00"
format
Frame format:
00: Motorola SPI frame format
01..11: reserved
23 - 20 0
-
 reserved
19 - 8 0x800
sck_muladd
Serial clock rate multiply add value for master SCK generation.
The SPI clock frequency is: f_spi_sck = (sck_muladd * 100)/4096 [MHz].
Default value 0x800 equals 50MHz SPI clock rate.
All serial clock rates are derived from 100MHz netX system clock. Hence, all serial clock phases are multiples
of 10ns. This leads to non-constant serial clock phases when a clock rate is programmed which cannot be generated
by 100MHz/(2*n) without remainder. E.g. programming 0x4CC here will lead to a mean clock-rate of 30MHz. However,
single clock high and low phases of 10ns and clock periods of 30ns will occur. This must be considered for
serial device selection. E.g. using a 30MHz device which requires 33ns minimum clock period and a duty cycle
of 50% will fail.
Note: If sck_muladd is set to zero, SPI transfer will freeze.
The SPI clock must not exceed (system frequency/4) in slave mode, if correct data sampling should always be guaranteed.
Note: The value programmed here has no impact in slave mode.
7 "0"
SPH
Serial clock phase (netx500: CR_ncpha):
1: sample data at second clock edge, data is generated half a clock phase before sampling
0: sample data at first clock edge, data is generated half a clock phase before sampling
6 "0"
SPO
Serial clock polarity (netx500: CR_cpol):
0: idle: clock is low, first edge is rising
1: idle: clock is high, first edge is falling
5 - 4 0
-
 reserved
3 - 0 "0111"
datasize
DSS: data size select (transfer size = datasize + 1 bits):
0000...0010: reserved
0011: 4 bit
0100: 5 bit
...  
0111: 8 bit
...  
1111: 16 bit

Note: 16 bit TX-data-loss bug of netX50/netX5 is fixed since netX10.


spi_cr1
SPI control register 1
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
R/W
0x08080000
Address@iol_spi : 0x00081104
Address@com_spi0 : 0x06400084
Address@com_spi1 : 0x064000c4
Address@com_iol_spi : 0x06c81104
Address@app_spi0 : 0x40080404
Address@app_spi1 : 0x40080444
Address@mot_spi0 : 0x49200404
Address@mot_spi1 : 0x49200444
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 "0"
rx_fifo_clr
Writing "1" to this bit will clear the receive FIFOs.
27 - 24 "1000"
rx_fifo_wm
Receive FIFO watermark for IRQ generation
23 - 21 0
-
 reserved
20 "0"
tx_fifo_clr
Writing "1" to this bit will clear the transmit FIFOs.
Note: There must be at least 1 system clock idle after clear before writing new data to the
FIFO. This is guaranteed by the netX internal bus structure and needs not being considered by software.
19 - 16 "1000"
tx_fifo_wm
Transmit FIFO watermark for IRQ generation
15 - 12 0
-
 reserved
11 "0"
fss_static
SPI static chip-select:
0:
SPI chip-select signals are controlled by hardware during transfer depending on spi_cr0.SPH.
For spi_cr0.SPH==0 chip-select is toggled between each transferred word according to fss and datasize.
For spi_cr0.SPH==1 chip-select remains active between each transferred word and is deactivated after the last word.
1: SPI chip-select will be set statically according to the fss bits.
10 - 8 "000"
fss
Frame or slave select.
There are up to 3 external SPI chip-select signals.
In master mode, the fss bits define the states of the chip-select signals.
The inversion for low-active chip-selects (e.g. for Motorola SPI frame format) is done automatically
depending on the value programmed to the 'format' bits.
Example: To use the netX IO CS1 as chip-select, program '010' here, regardless whether the external
chip-select is low or high active.
In slave mode, the fss bits are a mask to select which netX input should be used as chip-select.
Example: To use the netX IO CS0 as chip-select, program '001' here.
7 - 5 0
-
 reserved
4 "0"
pio_mode
Only for test: If this bit is set the SPI function is not available. The IOs-states are
defined by the spi_pio_mode register instead.
3 "0"
SOD
Slave mode output disable (to connect multiple slaves to one master):
0: MISO can be driven in slave mode
1: MISO is not driven in slave mode
2 "0"
MS
Mode select:
0: Module is configured as master
1: Module is configured as slave
1 "0"
SSE
SPI enable:
0: Module disabled
1: Module enabled
0 "0"
LBM
Loop back mode:
0: Internal loop back disabled
1: Internal loop back enabled, spi_cr0.filter_in must be set for loopback function


spi_dr
SPI data register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
The SPI module has 2 FIFOs: One for transmit data and one for receive data.
Read access: Received data byte is delivered from receive FIFO.
Write access: Transmit data byte is written to send FIFO.
Both FIFOs (receive and transmit) have a depth of 16.
SPI master mode: MISO input data will be stored in the receive FIFO; transmit FIFO generates MOSI output data.
SPI slave mode: MOSI input data will be stored in the receive FIFO; transmit FIFO generates MISO output data.
R/W
0x00000000
Address@iol_spi : 0x00081108
Address@com_spi0 : 0x06400088
Address@com_spi1 : 0x064000c8
Address@com_iol_spi : 0x06c81108
Address@app_spi0 : 0x40080408
Address@app_spi1 : 0x40080448
Address@mot_spi0 : 0x49200408
Address@mot_spi1 : 0x49200448
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
data
Transmit data: Only lowest bits according to spi_cr0.datasize will be sent.
Receive data will be delivered on the lowest bits, unused bits (above spi_cr0.datasize) will be "0".
In slave mode transmit data is requested from the FIFO when the last bit of the currently
transferred word is set to the MISO signal.
If no next transmit data can be read from the FIFO until the current word's last bit was transferred, a
FIFO underrun will occur in case chip-select does not go inactive at the next detected SCK edge.


spi_sr
SPI status register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
Address@iol_spi : 0x0008110c
Address@com_spi0 : 0x0640008c
Address@com_spi1 : 0x064000cc
Address@com_iol_spi : 0x06c8110c
Address@app_spi0 : 0x4008040c
Address@app_spi1 : 0x4008044c
Address@mot_spi0 : 0x4920040c
Address@mot_spi1 : 0x4920044c
Bits Name Description
31 rx_fifo_err_undr
Receive FIFO underrun error occurred, data is lost
30 rx_fifo_err_ovfl
Receive FIFO overflow error occurred, data is lost
29 -
 reserved
28 - 24 rx_fifo_level
Receive FIFO level (number of received words to read out are left in FIFO)
23 tx_fifo_err_undr
Transmit FIFO underrun error occurred, data is lost
22 tx_fifo_err_ovfl
Transmit FIFO overflow error occurred, data is lost
21 -
 reserved
20 - 16 tx_fifo_level
Transmit FIFO level (number of words to transmit are left in FIFO)
15 - 5 -
 reserved
4 BSY
Device busy (1 if data is currently transmitted/received or the transmit FIFO is not empty)
3 RFF
Receive FIFO is full (1 if full)
2 RNE
Receive FIFO is not empty (0 if empty)
1 TNF
Transmit FIFO is not full (0 if full)
0 TFE
Transmit FIFO is empty (1 if empty)


spi_imsc
SPI Interrupt Mask Set and Clear register:
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
IRQ mask is an AND-mask: only raw interrupts with mask bit set can generate a module IRQ.
When writing this register, the corresponding interrupt is cleared similar to writing the register spi_icr.

Note: The functionality of this register is similar to the corresponding SQI register sqi_irq_mask.
      However, in contrast to this register, setting bits in sqi_irq_mask does not clear the corresponding interrupts.

Note: Both FIFOs (receive and transmit) have a depth of 16.
R/W
0x00000000
Address@iol_spi : 0x00081114
Address@com_spi0 : 0x06400094
Address@com_spi1 : 0x064000d4
Address@com_iol_spi : 0x06c81114
Address@app_spi0 : 0x40080414
Address@app_spi1 : 0x40080454
Address@mot_spi0 : 0x49200414
Address@mot_spi1 : 0x49200454
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
txeim
Transmit FIFO empty interrupt mask (for netx100/500 compliance)
5 "0"
rxfim
Receive FIFO full interrupt mask (for netx100/500 compliance)
4 "0"
rxneim
Receive FIFO not empty interrupt mask (for netx100/500 compliance)
3 "0"
TXIM
Transmit FIFO interrupt mask
2 "0"
RXIM
Receive FIFO interrupt mask
1 "0"
RTIM
Receive timeout interrupt mask
0 "0"
RORIM
Receive FIFO overrun interrupt mask


spi_ris
SPI interrupt state before masking register (raw interrupt)
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
Address@iol_spi : 0x00081118
Address@com_spi0 : 0x06400098
Address@com_spi1 : 0x064000d8
Address@com_iol_spi : 0x06c81118
Address@app_spi0 : 0x40080418
Address@app_spi1 : 0x40080458
Address@mot_spi0 : 0x49200418
Address@mot_spi1 : 0x49200458
Bits Name Description
31 - 7 -
 reserved
6 txeris
Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)
1: transmit FIFO is empty
0: transmit FIFO is not empty
5 rxfris
Unmasked receive FIFO full interrupt state (for netx100/500 compliance)
1: receive FIFO is full
0: receive FIFO is not full
4 rxneris
Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)
1: receive FIFO is not empty
0: receive FIFO is empty
3 TXRIS
Unmasked transmit FIFO interrupt state
1: transmit FIFO level is below spi_cr1.tx_fifo_wm
0: transmit FIFO equals or is higher than spi_cr1.tx_fifo_wm
2 RXRIS
Unmasked receive FIFO interrupt state
1: receive FIFO is higher than spi_cr1.rx_fifo_wm
0: receive FIFO is equals or is below spi_cr1.rx_fifo_wm
1 RTRIS
Unmasked receive timeout interrupt state
Timeout period are 32 SPI clock periods depending on adr_spi_cr0.sck_muladd
1: receive FIFO is not empty and not read out in the passed timeout period
0: receive FIFO is empty or read during the last timeout period
0 RORRIS
Unmasked receive FIFO overrun interrupt state
1: receive FIFO overrun error occurred
0: no receive FIFO overrun error occurred


spi_mis
SPI interrupt status register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R
Address@iol_spi : 0x0008111c
Address@com_spi0 : 0x0640009c
Address@com_spi1 : 0x064000dc
Address@com_iol_spi : 0x06c8111c
Address@app_spi0 : 0x4008041c
Address@app_spi1 : 0x4008045c
Address@mot_spi0 : 0x4920041c
Address@mot_spi1 : 0x4920045c
Bits Name Description
31 - 7 -
 reserved
6 txemis
Masked transmit FIFO empty interrupt state (for netx100/500 compliance)
5 rxfmis
Masked receive FIFO full interrupt state (for netx100/500 compliance)
4 rxnemis
Masked receive FIFO not empty interrupt state (for netx100/500 compliance)
3 TXMIS
Masked transmit FIFO interrupt state
2 RXMIS
Masked receive FIFO interrupt state
1 RTMIS
Masked receive timeout interrupt state
0 RORMIS
Masked receive FIFO overrun interrupt state


spi_icr
SPI interrupt clear register
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
An interrupt is cleared by writing "1" to the according bit.
Note: Both FIFOs (receive and transmit) have a depth of 16.
R/W
0x00000000
Address@iol_spi : 0x00081120
Address@com_spi0 : 0x064000a0
Address@com_spi1 : 0x064000e0
Address@com_iol_spi : 0x06c81120
Address@app_spi0 : 0x40080420
Address@app_spi1 : 0x40080460
Address@mot_spi0 : 0x49200420
Address@mot_spi1 : 0x49200460
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
txeic
Clear transmit FIFO empty interrupt (for netx100/500 compliance)
5 "0"
rxfic
Clear receive FIFO full interrupt (for netx100/500 compliance)
4 "0"
rxneic
Clear receive FIFO not empty interrupt (for netx100/500 compliance)
3 "0"
TXIC
PL022 extension: clear transmit FIFO interrupt
2 "0"
RXIC
PL022 extension: clear receive FIFO interrupt
1 "0"
RTIC
Clear receive FIFO overrun interrupt
0 "0"
RORIC
Clear receive FIFO overrun interrupt
Writing '1' here will clear the receive FIFO


spi_dmacr
SPI DMA control register
R/W
0x00000000
Address@iol_spi : 0x00081128
Address@com_spi0 : 0x064000a8
Address@com_spi1 : 0x064000e8
Address@com_iol_spi : 0x06c81128
Address@app_spi0 : 0x40080428
Address@app_spi1 : 0x40080468
Address@mot_spi0 : 0x49200428
Address@mot_spi1 : 0x49200468
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
TXDMAE
Enable DMA for SPI transmit data.
A single request will be generated if the transmit FIFO is not full and spi_cr1.SSE (module
enable) is set. Burst requests to the DMA controller will be generated if at least 4 words
are writable to the transmit FIFO (set DMA burst size to 4).
If this bit is reset or the module is disabled, the DMA request signals will also be reset.
Note: set dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA controller.
0 "0"
RXDMAE
Enable DMA for SPI receive data.
A single request will be generated if the receive FIFO is not empty and spi_cr1.SSE (module
enable) is set. Burst request to the DMA controller will be generated if the receive FIFO
contains at least 4 words (set DMA burst size to 4).
If this bit is reset or the module is disabled, the DMA request signals will also be reset.
Note: set dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA controller.


spi_pio_mode
SPI PIO mode register
The PIO mode is only for test purpose. It must be enabled by the pio_mode bit in the spi_cr1 register.
R/W
0x00000000
Address@iol_spi : 0x0008112c
Address@com_spi0 : 0x064000ac
Address@com_spi1 : 0x064000ec
Address@com_iol_spi : 0x06c8112c
Address@app_spi0 : 0x4008042c
Address@app_spi1 : 0x4008046c
Address@mot_spi0 : 0x4920042c
Address@mot_spi1 : 0x4920046c
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
miso_oe
Output drive enable of the MISO IO of the module.
20 "0"
mosi_oe
Output drive enable of the MOSI IO of the module.
19 "0"
sck_oe
Output drive enable of the SCK (serial clock) IO of the module.
18 "0"
fss2_oe
Output drive enable of the FSS[2] (CSn, chip-select 2) IO of the module.
17 "0"
fss1_oe
Output drive enable of the FSS[1] (CSn, chip-select 1) IO of the module.
16 "0"
fss0_oe
Output drive enable of the FSS[0] (CSn, chip-select 0) IO of the module.
15 - 14 0
-
 reserved
13 "0"
miso_out
Output state of the MISO IO of the module.
12 "0"
mosi_out
Output state of the MOSI IO of the module.
11 "0"
sck_out
Output state of the SCK (serial clock) IO of the module.
10 "0"
fss2_out
Output state of the FSS[2] (CSn, chip-select 2) IO of the module.
9 "0"
fss1_out
Output state of the FSS[1] (CSn, chip-select 1) IO of the module.
8 "0"
fss0_out
Output state of the FSS[0] (CSn, chip-select 0) IO of the module.
7 - 6 0
-
 reserved
5 -
miso_in_ro
Input state of the MISO IO of the module (read-only).
4 -
mosi_in_ro
Input state of the MOSI IO of the module (read-only).
3 -
sck_in_ro
Input state of the SCK (serial clock) IO of the module (read-only).
2 -
fss2_in_ro
Input state of the FSS[2] (CSn, chip-select 2) IO of the module (read-only).
1 -
fss1_in_ro
Input state of the FSS[1] (CSn, chip-select 1) IO of the module (read-only).
0 -
fss0_in_ro
Input state of the FSS[0] (CSn, chip-select 0) IO of the module (read-only).


spi_data_register
(NETX_SPI%_DATA)
netx100/500 compliant SPI data register (DR)
Registers 0x30..0x3C can be used instead of registers 0x00...0x24 to keep netx50 software compliant to netx100/500.
2 data bytes with valid bits.
During a write access data_byte_1 and dr_valid1 must not be used. dr_valid0 must be set.
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R/W
0x00000000
Address@iol_spi : 0x00081130
Address@com_spi0 : 0x064000b0
Address@com_spi1 : 0x064000f0
Address@com_iol_spi : 0x06c81130
Address@app_spi0 : 0x40080430
Address@app_spi1 : 0x40080470
Address@mot_spi0 : 0x49200430
Address@mot_spi1 : 0x49200470
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
dr_valid1
Obsolete, always 0
16 "0"
dr_valid0
Valid bit for data_byte_0
This bit shows if data_byte_0 is valid and must be set during a FIFO write access.
15 - 8 "00000000"
data_byte_1
Obsolete, don't use
7 - 0 "00000000"
data_byte_0
Data byte 0


spi_status_register
(NETX_SPI%_STAT)
netx100/500 compliant SPI status register (SR):
Shows the actual status of the SPI interface.
Bits 24..18 show occurred interrupts; writing ones into these bits clears the interrupts.
Writing into other bits has no effect.
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R
Address@iol_spi : 0x00081134
Address@com_spi0 : 0x064000b4
Address@com_spi1 : 0x064000f4
Address@com_iol_spi : 0x06c81134
Address@app_spi0 : 0x40080434
Address@app_spi1 : 0x40080474
Address@mot_spi0 : 0x49200434
Address@mot_spi1 : 0x49200474
Bits Name Description
31 - 26 -
 reserved
25 SR_selected
External master has access to SPI interface
24 SR_out_full
Output FIFO is full. This is only with netx100/500 an IRQ.
23 SR_out_empty
Output FIFO is empty in slave mode (equals spi_ris.txeris in netx50 and later versions)
22 SR_out_fw
netX is writing data too fast into output FIFO. Available as an IRQ only on netx100/500
(equals spi_sr.tx_fifo_err_ovfl in netx50 and later versions).
21 SR_out_fuel
Adjustable fill value of output FIFO reached (equals spi_ris.TXRIS in netx50 and later versions)
20 SR_in_full
Input FIFO is full (equals spi_ris.rxfris in netx50 and later versions)
19 SR_in_recdata
Valid data bytes in input FIFO (equals spi_ris.rxneris in netx50 and later versions)
18 SR_in_fuel
Adjustable fill value of input FIFO reached (equals spi_ris.RXRIS in netx50 and later versions)
17 - 9 SR_out_fuel_val
Output FIFO fill value (number of bytes)
8 - 0 SR_in_fuel_val
Input FIFO fill value (number of bytes)


spi_control_register
(NETX_SPI%_CTRL)
netx100/500 compliant SPI control register (CR)
R/W
0x500000c0
Address@iol_spi : 0x00081138
Address@com_spi0 : 0x064000b8
Address@com_spi1 : 0x064000f8
Address@com_iol_spi : 0x06c81138
Address@app_spi0 : 0x40080438
Address@app_spi1 : 0x40080478
Address@mot_spi0 : 0x49200438
Address@mot_spi1 : 0x49200478
Bits Reset value Name Description
31 "0"
CR_en
1: enable
0: disable SPI interface
30 "1"
CR_ms
1: master mode
0:slave mode
29 "0"
CR_cpol
1: falling edge of SCK is primary
0: rising edge of SCK is primary
28 "1"
CR_ncpha
SPI clock phase mode (Note: meaning of this bit is inverted to functionality of bit spi_cr0.SPH):
0: change data on secondary SCK edge
data is active on primary SCK edge
1: change data on primary SCK edge
data is active on secondary SCK edge
27 - 25 "000"
CR_burst
netx100/netx500 only, obsolete in later versions: burst length = 2^CR_burst
24 - 22 "000"
CR_burstdelay
netx100/netx500 only, obsolete in later versions: delay between transmission of 2 data bytes
(0 to 7 SCK cycles)
21 "0"
CR_clr_outfifo
Clear output FIFO
20 "0"
CR_clr_infifo
Clear input FIFO
19 - 12 0
-
 reserved
11 "0"
CS_mode
1: chip select is generated automatically by the internal state machine
0: chip select is directly controlled by software (see bits CR_ss).
10 - 8 "000"
CR_ss
External slave select
7 "1"
CR_write
netx100/netx500 only, in later versions always "1":  1: enable SPI interface write data
6 "1"
CR_read
netx100/netx500 only, in later versions always "1":  1: enable SPI interface read data
5 0
-
 reserved
4 - 1 "0000"
CR_speed
Clock divider for SPI clock (2 - 2^16)
If SPI clock rate is changed using spi_cr0.sck_muladd, this value will not be updated and may be incorrect
There are 16 different SPI clocks frequencies to choose:
0000: 0.025 MHz (Note: Not compatible to netx100/500. "0000" freezes SCK in netx100/500.)
0001: 0.05 MHz
0010: 0.1 MHz
0011: 0.2 MHz
0100: 0.5 MHz
0101: 1 MHz
0110: 1.25 MHz
0111: 2 MHz
1000: 2.5 MHz
1001: 3.3333 MHz
1010: 5 MHz
1011: 10 MHz
1100: 12.5 MHz
1101: 16.6666 MHz
1110: 25 MHz
1111: 50 MHz
0 "0"
CR_softreset
write only: no function in netx100/netx500; later versions: clears IRQs and FIFOs


spi_interrupt_control_register
(NETX_SPI%_INT_CTRL)
netx100/500 compliant SPI interrupt control register (IR)
In netx50 and later versions both FIFOs (receive and transmit) have a depth of 16, fill values are fixed to 4. To keep software
compatible, not more than 8 bytes should be in netx100/500 FIFOs.
R/W
0x00001008
Address@iol_spi : 0x0008113c
Address@com_spi0 : 0x064000bc
Address@com_spi1 : 0x064000fc
Address@com_iol_spi : 0x06c8113c
Address@app_spi0 : 0x4008043c
Address@app_spi1 : 0x4008047c
Address@mot_spi0 : 0x4920043c
Address@mot_spi1 : 0x4920047c
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
IR_out_full_en
IRQ enable for irq_spi(6), netx100/netx500 only, always "0" in later versions
23 "0"
IR_out_empty_en
IRQ enable for irq_spi(5)  (equals spi_imsc.rxeim in netx50 and later versions)
22 "0"
IR_out_fw_en
IRQ enable for irq_spi(4), netx100/netx500 only, always "0" in later versions
21 "0"
IR_out_fuel_en
IRQ enable for irq_spi(3)  (equals spi_imsc.TXIM in netx50 and later versions)
20 "0"
IR_in_full_en
IRQ enable for irq_spi(2)  (equals spi_imsc.txfim in netx50 and later versions)
19 "0"
IR_in_recdata_en
IRQ enable for irq_spi(1)  (equals spi_imsc.txneim in netx50 and later versions)
18 "0"
IR_in_fuel_en
IRQ enable for irq_spi(0)  (equals spi_imsc.RXIM in netx50 and later versions)
17 - 9 0x8
IR_out_fuel
Adjustable watermark level of output FIFO
8 - 0 0x8
IR_in_fuel
Adjustable watermark level of input FIFO



Base Address Area: iol_hsc, ada_hsc, cada_hsc, com_hsc, com_cda_rx_hsc, com_cda_tx_hsc, com_ada_hsc, com_iol_hsc, app_hsc, mot_hsc, sms_host_hsc

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_hsc_start
1-1f 4-7c -  reserved
20 80 R/W sms_hsc_set_start
21-3f 84-fc -  reserved
40 100 R/W sms_hsc_clr_start
41-7f 104-1fc -  reserved
80 200 R/W sms_hsc_irq_set
81 204 R/W sms_hsc_irq_clr
82 208 R sms_hsc_irq_state
83-ff 20c-3fc -  reserved

sms_hsc_start
SMS Handshake cell register
There are sms_hsc.NO of these registers placed with addr offset +4

instance_name - assigned CPU / number of HSCs / addresses
cda_rx / 4 HSCs / address @ com_cda_rx_hsc, cada_hsc (EH2 internal)
cda_tx / 4 HSCs / address @ com_cda_tx_hsc, cada_hsc (EH2 internal)
ada / 4 HSCs / address @ com_ada_hsc, ada_hsc (EH2 internal)
iol / 4 HSCs / address @ com_iol_hsc, iol_hsc (EL2 internal)
mot - mot_cpu0 & mot_cpu1 / 4 HSCs / address @ mot_hsc
com - ca32_com / 8 HSCs / address @ com_hsc
sms_host / 8 HSCs / address @ sms_host_hsc
app - ca32_app / 8 HSCs / address @ app_hsc
R/W
0x00000000
Address@iol_hsc : 0x00081c00
Address@ada_hsc : 0x00101c00
Address@cada_hsc : 0x00110c00
Address@com_hsc : 0x06401000
Address@com_cda_rx_hsc : 0x06710c00
Address@com_cda_tx_hsc : 0x06910c00
Address@com_ada_hsc : 0x06b01c00
Address@com_iol_hsc : 0x06c81c00
Address@app_hsc : 0x40083000
Address@mot_hsc : 0x49000c00
Address@sms_host_hsc : 0x60180000
Bits Reset value Name Description
31 - 0 0x0
data
Writing a different data value as the stored value, asserts irq sms_hsc.irq[n]
read: returns 'data' content


sms_hsc_set_start
SMS HSC SET register
There are sms_hsc.NO of these registers placed with addr offset +4
R/W
0x00000000
Address@iol_hsc : 0x00081c80
Address@ada_hsc : 0x00101c80
Address@cada_hsc : 0x00110c80
Address@com_hsc : 0x06401080
Address@com_cda_rx_hsc : 0x06710c80
Address@com_cda_tx_hsc : 0x06910c80
Address@com_ada_hsc : 0x06b01c80
Address@com_iol_hsc : 0x06c81c80
Address@app_hsc : 0x40083080
Address@mot_hsc : 0x49000c80
Address@sms_host_hsc : 0x60180080
Bits Reset value Name Description
31 - 0 0x0
data
Bits in the write payload will be set in the stored data.
read: returns 'data' content


sms_hsc_clr_start
SMS HSC SET register
There are sms_hsc.NO of these registers placed with addr offset +4
R/W
0x00000000
Address@iol_hsc : 0x00081d00
Address@ada_hsc : 0x00101d00
Address@cada_hsc : 0x00110d00
Address@com_hsc : 0x06401100
Address@com_cda_rx_hsc : 0x06710d00
Address@com_cda_tx_hsc : 0x06910d00
Address@com_ada_hsc : 0x06b01d00
Address@com_iol_hsc : 0x06c81d00
Address@app_hsc : 0x40083100
Address@mot_hsc : 0x49000d00
Address@sms_host_hsc : 0x60180100
Bits Reset value Name Description
31 - 0 0x0
data
Bits in the write payload will be cleared in the stored data.
read: returns 'data' content


sms_hsc_irq_set
SMS HSC IRQ SET register
R/W
0x00000000
Address@iol_hsc : 0x00081e00
Address@ada_hsc : 0x00101e00
Address@cada_hsc : 0x00110e00
Address@com_hsc : 0x06401200
Address@com_cda_rx_hsc : 0x06710e00
Address@com_cda_tx_hsc : 0x06910e00
Address@com_ada_hsc : 0x06b01e00
Address@com_iol_hsc : 0x06c81e00
Address@app_hsc : 0x40083200
Address@mot_hsc : 0x49000e00
Address@sms_host_hsc : 0x60180200
Bits Reset value Name Description
31 - 0 0x0
set_mask
For each bit: set_mask[n] set asserts irq[n]
read: returns '0


sms_hsc_irq_clr
SMS HSC IRQ CLR register
R/W
0x00000000
Address@iol_hsc : 0x00081e04
Address@ada_hsc : 0x00101e04
Address@cada_hsc : 0x00110e04
Address@com_hsc : 0x06401204
Address@com_cda_rx_hsc : 0x06710e04
Address@com_cda_tx_hsc : 0x06910e04
Address@com_ada_hsc : 0x06b01e04
Address@com_iol_hsc : 0x06c81e04
Address@app_hsc : 0x40083204
Address@mot_hsc : 0x49000e04
Address@sms_host_hsc : 0x60180204
Bits Reset value Name Description
31 - 0 0x0
clr_mask
For each bit: clr_mask[n] set deasserts irq[n]
read: returns '0


sms_hsc_irq_state
SMS HSC IRQ SET register
R
Address@iol_hsc : 0x00081e08
Address@ada_hsc : 0x00101e08
Address@cada_hsc : 0x00110e08
Address@com_hsc : 0x06401208
Address@com_cda_rx_hsc : 0x06710e08
Address@com_cda_tx_hsc : 0x06910e08
Address@com_ada_hsc : 0x06b01e08
Address@com_iol_hsc : 0x06c81e08
Address@app_hsc : 0x40083208
Address@mot_hsc : 0x49000e08
Address@sms_host_hsc : 0x60180208
Bits Name Description
31 - 0 irq
Each bit represents the individual IRQ of a handshake cell.



Base Address Area: iol_wdg_sys, ada_wdg_sys, cada_wdg_sys, com_wdg, com_cda_rx_wdg_sys, com_cda_tx_wdg_sys, com_ada_wdg_sys, com_iol_wdg_sys, mot_wdg0, mot_wdg1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W netx_sys_wdg_ctrl
1 4 R netx_sys_wdg
2 8 R/W netx_sys_wdg_irq_timeout
3 c R/W netx_sys_wdg_res_timeout
4 10 R/W netx_sys_wdg_irq_raw
5 14 R netx_sys_wdg_irq_masked
6 18 R/W netx_sys_wdg_irq_msk_set
7 1c R/W netx_sys_wdg_irq_msk_reset

netx_sys_wdg_ctrl
netX System Watchdog Trigger Register.
The watchdog access code is generated by a pseudo random generator. It must be written correctly
for a valid write access to this register (not only for triggering e.g. also for IRQ clearing).
Note:
   WDGACT signal is available as MMIO function..
R/W
0x00000000
Address@iol_wdg_sys : 0x00082000
Address@ada_wdg_sys : 0x00102000
Address@cada_wdg_sys : 0x00111000
Address@com_wdg : 0x064003a0
Address@com_cda_rx_wdg_sys : 0x06711000
Address@com_cda_tx_wdg_sys : 0x06911000
Address@com_ada_wdg_sys : 0x06b02000
Address@com_iol_wdg_sys : 0x06c82000
Address@mot_wdg0 : 0x492007a0
Address@mot_wdg1 : 0x492007c0
Bits Reset value Name Description
31 "0"
write_enable
Write enable bit for timeout register:
As long as this bit is not set all write accesses to the timeout register are ignored.
30 - 29 0
-
 reserved
28 "0"
wdg_counter_trigger_w
Watchdog trigger bit:
Bit must be set to trigger the watchdog counter.
When read, this bit is always '0'
27 - 25 0
-
 reserved
24 "0"
irq_req_watchdog
IRQ request of watchdog, writing 1 deletes IRQ
23 - 20 0
-
 reserved
19 - 0 0x0
wdg_access_code
Watchdog trigger and control register access code.
A read access gives the next 16 bit code for writing the 'netx_sys_wdg_ctrl' register.
A write access with correct access code will trigger the watchdog counter.


netx_sys_wdg
netX System Watchdog Register
The counter value is decremented each 10000 system clock cycles.
R
Address@iol_wdg_sys : 0x00082004
Address@ada_wdg_sys : 0x00102004
Address@cada_wdg_sys : 0x00111004
Address@com_wdg : 0x064003a4
Address@com_cda_rx_wdg_sys : 0x06711004
Address@com_cda_tx_wdg_sys : 0x06911004
Address@com_ada_wdg_sys : 0x06b02004
Address@com_iol_wdg_sys : 0x06c82004
Address@mot_wdg0 : 0x492007a4
Address@mot_wdg1 : 0x492007c4
Bits Name Description
31 - 17 -
 reserved
16 - 0 wdg_counter
Actual watchdog counter value


netx_sys_wdg_irq_timeout
netX System Wachtdog Interrupt Timout Register
R/W
0x00000000
Address@iol_wdg_sys : 0x00082008
Address@ada_wdg_sys : 0x00102008
Address@cada_wdg_sys : 0x00111008
Address@com_wdg : 0x064003a8
Address@com_cda_rx_wdg_sys : 0x06711008
Address@com_cda_tx_wdg_sys : 0x06911008
Address@com_ada_wdg_sys : 0x06b02008
Address@com_iol_wdg_sys : 0x06c82008
Address@mot_wdg0 : 0x492007a8
Address@mot_wdg1 : 0x492007c8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
wdg_irq_timeout
Watchdog interrupt timeout
The total netx_sys_irq timeout for a netX clock of 100MHz is: wdg_irq_timeout * 100µs
Note: The watchdog can be stopped by programming a 0.


netx_sys_wdg_res_timeout
netX System Watchdog Reset Timeout Register
R/W
0x00000000
Address@iol_wdg_sys : 0x0008200c
Address@ada_wdg_sys : 0x0010200c
Address@cada_wdg_sys : 0x0011100c
Address@com_wdg : 0x064003ac
Address@com_cda_rx_wdg_sys : 0x0671100c
Address@com_cda_tx_wdg_sys : 0x0691100c
Address@com_ada_wdg_sys : 0x06b0200c
Address@com_iol_wdg_sys : 0x06c8200c
Address@mot_wdg0 : 0x492007ac
Address@mot_wdg1 : 0x492007cc
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
wdg_res_timeout
Watchdog reset request timeout
The total reset timeout for a netX clock of 100MHz is: (wdg_irq_timeout + wdg_res_timeout) * 100µs
Note: The watchdog can be stopped by programming a 0.


netx_sys_wdg_irq_raw
netX System Wachtdog IRQ raw register:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@iol_wdg_sys : 0x00082010
Address@ada_wdg_sys : 0x00102010
Address@cada_wdg_sys : 0x00111010
Address@com_wdg : 0x064003b0
Address@com_cda_rx_wdg_sys : 0x06711010
Address@com_cda_tx_wdg_sys : 0x06911010
Address@com_ada_wdg_sys : 0x06b02010
Address@com_iol_wdg_sys : 0x06c82010
Address@mot_wdg0 : 0x492007b0
Address@mot_wdg1 : 0x492007d0
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_masked
netX System Wachtdog Masked IRQ register:
Read access shows status of masked IRQs.
R
Address@iol_wdg_sys : 0x00082014
Address@ada_wdg_sys : 0x00102014
Address@cada_wdg_sys : 0x00111014
Address@com_wdg : 0x064003b4
Address@com_cda_rx_wdg_sys : 0x06711014
Address@com_cda_tx_wdg_sys : 0x06911014
Address@com_ada_wdg_sys : 0x06b02014
Address@com_iol_wdg_sys : 0x06c82014
Address@mot_wdg0 : 0x492007b4
Address@mot_wdg1 : 0x492007d4
Bits Name Description
31 - 1 -
 reserved
0 wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_msk_set
netX System Wachtdog interrupt mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to irq_raw.
R/W
0x00000000
Address@iol_wdg_sys : 0x00082018
Address@ada_wdg_sys : 0x00102018
Address@cada_wdg_sys : 0x00111018
Address@com_wdg : 0x064003b8
Address@com_cda_rx_wdg_sys : 0x06711018
Address@com_cda_tx_wdg_sys : 0x06911018
Address@com_ada_wdg_sys : 0x06b02018
Address@com_iol_wdg_sys : 0x06c82018
Address@mot_wdg0 : 0x492007b8
Address@mot_wdg1 : 0x492007d8
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
wdg_res_irq
Watchdog reset request timeout interrupt


netx_sys_wdg_irq_msk_reset
netX System Wachtdog interrupt mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address@iol_wdg_sys : 0x0008201c
Address@ada_wdg_sys : 0x0010201c
Address@cada_wdg_sys : 0x0011101c
Address@com_wdg : 0x064003bc
Address@com_cda_rx_wdg_sys : 0x0671101c
Address@com_cda_tx_wdg_sys : 0x0691101c
Address@com_ada_wdg_sys : 0x06b0201c
Address@com_iol_wdg_sys : 0x06c8201c
Address@mot_wdg0 : 0x492007bc
Address@mot_wdg1 : 0x492007dc
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
wdg_res_irq
Watchdog reset request timeout interrupt



Base Address Area: iol_arm_tim0, iol_arm_tim1, ada_arm_tim0, ada_arm_tim1, cada_arm_tim0, cada_arm_tim1, com_cda_rx_arm_tim0, com_cda_rx_arm_tim1, com_cda_tx_arm_tim0, com_cda_tx_arm_tim1, com_ada_arm_tim0, com_ada_arm_tim1, com_iol_arm_tim0, com_iol_arm_tim1, gxc_timer, mot_timer0, mot_timer1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W timer_config_timer0
1 4 R/W timer_config_timer1
2 8 R/W timer_config_timer2
3 c R/W timer_preload_timer0
4 10 R/W timer_preload_timer1
5 14 R/W timer_preload_timer2
6 18 R/W timer_timer0
7 1c R/W timer_timer1
8 20 R/W timer_timer2
9 24 R timer_systime_s
a 28 R timer_systime_ns
b 2c R/W timer_compare_systime_s_value
c 30 R/W timer_irq_raw
d 34 R timer_irq_masked
e 38 R/W timer_irq_msk_set
f 3c R/W timer_irq_msk_reset
10 40 R/W timer_systime_config
11-1f 44-7c -  reserved

timer_config_timer0
ARM TIMER Config register0
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082080
Address@iol_arm_tim1 : 0x00082100
Address@ada_arm_tim0 : 0x00102080
Address@ada_arm_tim1 : 0x00102100
Address@cada_arm_tim0 : 0x00111080
Address@cada_arm_tim1 : 0x00111100
Address@com_cda_rx_arm_tim0 : 0x06711080
Address@com_cda_rx_arm_tim1 : 0x06711100
Address@com_cda_tx_arm_tim0 : 0x06911080
Address@com_cda_tx_arm_tim1 : 0x06911100
Address@com_ada_arm_tim0 : 0x06b02080
Address@com_ada_arm_tim1 : 0x06b02100
Address@com_iol_arm_tim0 : 0x06c82080
Address@com_iol_arm_tim1 : 0x06c82100
Address@gxc_timer : 0x07d62600
Address@mot_timer0 : 0x49200800
Address@mot_timer1 : 0x49200880
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 2 "00"
systime_config
systime  for timer (2'b10.. systime_counter, 2'b01.. systime_global, 2'b00.. systime)
1 - 0 "00"
mode
Timer0
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_config_timer1
ARM TIMER Config register1
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082084
Address@iol_arm_tim1 : 0x00082104
Address@ada_arm_tim0 : 0x00102084
Address@ada_arm_tim1 : 0x00102104
Address@cada_arm_tim0 : 0x00111084
Address@cada_arm_tim1 : 0x00111104
Address@com_cda_rx_arm_tim0 : 0x06711084
Address@com_cda_rx_arm_tim1 : 0x06711104
Address@com_cda_tx_arm_tim0 : 0x06911084
Address@com_cda_tx_arm_tim1 : 0x06911104
Address@com_ada_arm_tim0 : 0x06b02084
Address@com_ada_arm_tim1 : 0x06b02104
Address@com_iol_arm_tim0 : 0x06c82084
Address@com_iol_arm_tim1 : 0x06c82104
Address@gxc_timer : 0x07d62604
Address@mot_timer0 : 0x49200804
Address@mot_timer1 : 0x49200884
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 2 "00"
systime_config
systime  for timer (2'b10.. systime_counter, 2'b01.. systime_global, 2'b00.. systime)
1 - 0 "00"
mode
Timer1
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_config_timer2
ARM TIMER Config register2
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082088
Address@iol_arm_tim1 : 0x00082108
Address@ada_arm_tim0 : 0x00102088
Address@ada_arm_tim1 : 0x00102108
Address@cada_arm_tim0 : 0x00111088
Address@cada_arm_tim1 : 0x00111108
Address@com_cda_rx_arm_tim0 : 0x06711088
Address@com_cda_rx_arm_tim1 : 0x06711108
Address@com_cda_tx_arm_tim0 : 0x06911088
Address@com_cda_tx_arm_tim1 : 0x06911108
Address@com_ada_arm_tim0 : 0x06b02088
Address@com_ada_arm_tim1 : 0x06b02108
Address@com_iol_arm_tim0 : 0x06c82088
Address@com_iol_arm_tim1 : 0x06c82108
Address@gxc_timer : 0x07d62608
Address@mot_timer0 : 0x49200808
Address@mot_timer1 : 0x49200888
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 2 "00"
systime_config
systime  for timer (2'b10.. systime_counter, 2'b01.. systime_global, 2'b00.. systime)
1 - 0 "00"
mode
Timer2
      2'b00 : Timer stops at 0
      2'b01 : Timer is preload with value from preload register at 0
      2'b10 : Timer (value) compare with systime (once)
      2'b11 : reserved


timer_preload_timer0
ARM TIMER Timer 0
R/W
0x00000000
Address@iol_arm_tim0 : 0x0008208c
Address@iol_arm_tim1 : 0x0008210c
Address@ada_arm_tim0 : 0x0010208c
Address@ada_arm_tim1 : 0x0010210c
Address@cada_arm_tim0 : 0x0011108c
Address@cada_arm_tim1 : 0x0011110c
Address@com_cda_rx_arm_tim0 : 0x0671108c
Address@com_cda_rx_arm_tim1 : 0x0671110c
Address@com_cda_tx_arm_tim0 : 0x0691108c
Address@com_cda_tx_arm_tim1 : 0x0691110c
Address@com_ada_arm_tim0 : 0x06b0208c
Address@com_ada_arm_tim1 : 0x06b0210c
Address@com_iol_arm_tim0 : 0x06c8208c
Address@com_iol_arm_tim1 : 0x06c8210c
Address@gxc_timer : 0x07d6260c
Address@mot_timer0 : 0x4920080c
Address@mot_timer1 : 0x4920088c
Bits Reset value Name Description
31 - 0 0x0
val
preload value


timer_preload_timer1
ARM TIMER Timer 1
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082090
Address@iol_arm_tim1 : 0x00082110
Address@ada_arm_tim0 : 0x00102090
Address@ada_arm_tim1 : 0x00102110
Address@cada_arm_tim0 : 0x00111090
Address@cada_arm_tim1 : 0x00111110
Address@com_cda_rx_arm_tim0 : 0x06711090
Address@com_cda_rx_arm_tim1 : 0x06711110
Address@com_cda_tx_arm_tim0 : 0x06911090
Address@com_cda_tx_arm_tim1 : 0x06911110
Address@com_ada_arm_tim0 : 0x06b02090
Address@com_ada_arm_tim1 : 0x06b02110
Address@com_iol_arm_tim0 : 0x06c82090
Address@com_iol_arm_tim1 : 0x06c82110
Address@gxc_timer : 0x07d62610
Address@mot_timer0 : 0x49200810
Address@mot_timer1 : 0x49200890
Bits Reset value Name Description
31 - 0 0x0
val
preload value


timer_preload_timer2
ARM TIMER Timer 2
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082094
Address@iol_arm_tim1 : 0x00082114
Address@ada_arm_tim0 : 0x00102094
Address@ada_arm_tim1 : 0x00102114
Address@cada_arm_tim0 : 0x00111094
Address@cada_arm_tim1 : 0x00111114
Address@com_cda_rx_arm_tim0 : 0x06711094
Address@com_cda_rx_arm_tim1 : 0x06711114
Address@com_cda_tx_arm_tim0 : 0x06911094
Address@com_cda_tx_arm_tim1 : 0x06911114
Address@com_ada_arm_tim0 : 0x06b02094
Address@com_ada_arm_tim1 : 0x06b02114
Address@com_iol_arm_tim0 : 0x06c82094
Address@com_iol_arm_tim1 : 0x06c82114
Address@gxc_timer : 0x07d62614
Address@mot_timer0 : 0x49200814
Address@mot_timer1 : 0x49200894
Bits Reset value Name Description
31 - 0 0x0
val
preload value


timer_timer0
ARM TIMER Timer 0
R/W
0x00000000
Address@iol_arm_tim0 : 0x00082098
Address@iol_arm_tim1 : 0x00082118
Address@ada_arm_tim0 : 0x00102098
Address@ada_arm_tim1 : 0x00102118
Address@cada_arm_tim0 : 0x00111098
Address@cada_arm_tim1 : 0x00111118
Address@com_cda_rx_arm_tim0 : 0x06711098
Address@com_cda_rx_arm_tim1 : 0x06711118
Address@com_cda_tx_arm_tim0 : 0x06911098
Address@com_cda_tx_arm_tim1 : 0x06911118
Address@com_ada_arm_tim0 : 0x06b02098
Address@com_ada_arm_tim1 : 0x06b02118
Address@com_iol_arm_tim0 : 0x06c82098
Address@com_iol_arm_tim1 : 0x06c82118
Address@gxc_timer : 0x07d62618
Address@mot_timer0 : 0x49200818
Address@mot_timer1 : 0x49200898
Bits Reset value Name Description
31 - 0 0x0
val
actual value of timer / systime compare value


timer_timer1
ARM TIMER Timer 1
R/W
0x00000000
Address@iol_arm_tim0 : 0x0008209c
Address@iol_arm_tim1 : 0x0008211c
Address@ada_arm_tim0 : 0x0010209c
Address@ada_arm_tim1 : 0x0010211c
Address@cada_arm_tim0 : 0x0011109c
Address@cada_arm_tim1 : 0x0011111c
Address@com_cda_rx_arm_tim0 : 0x0671109c
Address@com_cda_rx_arm_tim1 : 0x0671111c
Address@com_cda_tx_arm_tim0 : 0x0691109c
Address@com_cda_tx_arm_tim1 : 0x0691111c
Address@com_ada_arm_tim0 : 0x06b0209c
Address@com_ada_arm_tim1 : 0x06b0211c
Address@com_iol_arm_tim0 : 0x06c8209c
Address@com_iol_arm_tim1 : 0x06c8211c
Address@gxc_timer : 0x07d6261c
Address@mot_timer0 : 0x4920081c
Address@mot_timer1 : 0x4920089c
Bits Reset value Name Description
31 - 0 0x0
val
actual value of timer / systime compare value


timer_timer2
ARM TIMER Timer 2
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820a0
Address@iol_arm_tim1 : 0x00082120
Address@ada_arm_tim0 : 0x001020a0
Address@ada_arm_tim1 : 0x00102120
Address@cada_arm_tim0 : 0x001110a0
Address@cada_arm_tim1 : 0x00111120
Address@com_cda_rx_arm_tim0 : 0x067110a0
Address@com_cda_rx_arm_tim1 : 0x06711120
Address@com_cda_tx_arm_tim0 : 0x069110a0
Address@com_cda_tx_arm_tim1 : 0x06911120
Address@com_ada_arm_tim0 : 0x06b020a0
Address@com_ada_arm_tim1 : 0x06b02120
Address@com_iol_arm_tim0 : 0x06c820a0
Address@com_iol_arm_tim1 : 0x06c82120
Address@gxc_timer : 0x07d62620
Address@mot_timer0 : 0x49200820
Address@mot_timer1 : 0x492008a0
Bits Reset value Name Description
31 - 0 0x0
val
actual value of timer / systime compare value


timer_systime_s
(NETX_SYS_TIME_S)
ARM_TIMER upper SYSTIME register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
This register should be dedicated to accesses via ARM.
xPIC software should access systime via xpic_timer_systime_s.
R
Address@iol_arm_tim0 : 0x000820a4
Address@iol_arm_tim1 : 0x00082124
Address@ada_arm_tim0 : 0x001020a4
Address@ada_arm_tim1 : 0x00102124
Address@cada_arm_tim0 : 0x001110a4
Address@cada_arm_tim1 : 0x00111124
Address@com_cda_rx_arm_tim0 : 0x067110a4
Address@com_cda_rx_arm_tim1 : 0x06711124
Address@com_cda_tx_arm_tim0 : 0x069110a4
Address@com_cda_tx_arm_tim1 : 0x06911124
Address@com_ada_arm_tim0 : 0x06b020a4
Address@com_ada_arm_tim1 : 0x06b02124
Address@com_iol_arm_tim0 : 0x06c820a4
Address@com_iol_arm_tim1 : 0x06c82124
Address@gxc_timer : 0x07d62624
Address@mot_timer0 : 0x49200824
Address@mot_timer1 : 0x492008a4
Bits Name Description
31 - 0 val
Systime high:
Sample systime_ns at read access to systime_s.
Value is incremented, if systime_ns reaches systime_border.


timer_systime_ns
(NETX_SYS_TIME_NS)
ARM_TIMER lower SYSTIME register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (e.g. at 2nd read access of systime_ns), the actual value of systime_ns is read.
This register should be dedicated to accesses via ARM.
xPIC software should access systime via xpic_timer_systime_ns.
R
Address@iol_arm_tim0 : 0x000820a8
Address@iol_arm_tim1 : 0x00082128
Address@ada_arm_tim0 : 0x001020a8
Address@ada_arm_tim1 : 0x00102128
Address@cada_arm_tim0 : 0x001110a8
Address@cada_arm_tim1 : 0x00111128
Address@com_cda_rx_arm_tim0 : 0x067110a8
Address@com_cda_rx_arm_tim1 : 0x06711128
Address@com_cda_tx_arm_tim0 : 0x069110a8
Address@com_cda_tx_arm_tim1 : 0x06911128
Address@com_ada_arm_tim0 : 0x06b020a8
Address@com_ada_arm_tim1 : 0x06b02128
Address@com_iol_arm_tim0 : 0x06c820a8
Address@com_iol_arm_tim1 : 0x06c82128
Address@gxc_timer : 0x07d62628
Address@mot_timer0 : 0x49200828
Address@mot_timer1 : 0x492008a8
Bits Name Description
31 - 0 val
Systime low:
Sample systime_ns at read access to systime_s.
Without sample read systime_s, read the actual value of systime_ns.


timer_compare_systime_s_value
SYSTIME sec compare value
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820ac
Address@iol_arm_tim1 : 0x0008212c
Address@ada_arm_tim0 : 0x001020ac
Address@ada_arm_tim1 : 0x0010212c
Address@cada_arm_tim0 : 0x001110ac
Address@cada_arm_tim1 : 0x0011112c
Address@com_cda_rx_arm_tim0 : 0x067110ac
Address@com_cda_rx_arm_tim1 : 0x0671112c
Address@com_cda_tx_arm_tim0 : 0x069110ac
Address@com_cda_tx_arm_tim1 : 0x0691112c
Address@com_ada_arm_tim0 : 0x06b020ac
Address@com_ada_arm_tim1 : 0x06b0212c
Address@com_iol_arm_tim0 : 0x06c820ac
Address@com_iol_arm_tim1 : 0x06c8212c
Address@gxc_timer : 0x07d6262c
Address@mot_timer0 : 0x4920082c
Address@mot_timer1 : 0x492008ac
Bits Reset value Name Description
31 - 0 0x0
val
Compare value with systime_s (seconds):
Systime_s_compare_irq is set, if systime_s matches.


timer_irq_raw
ARM_TIMER Raw IRQ register:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820b0
Address@iol_arm_tim1 : 0x00082130
Address@ada_arm_tim0 : 0x001020b0
Address@ada_arm_tim1 : 0x00102130
Address@cada_arm_tim0 : 0x001110b0
Address@cada_arm_tim1 : 0x00111130
Address@com_cda_rx_arm_tim0 : 0x067110b0
Address@com_cda_rx_arm_tim1 : 0x06711130
Address@com_cda_tx_arm_tim0 : 0x069110b0
Address@com_cda_tx_arm_tim1 : 0x06911130
Address@com_ada_arm_tim0 : 0x06b020b0
Address@com_ada_arm_tim1 : 0x06b02130
Address@com_iol_arm_tim0 : 0x06c820b0
Address@com_iol_arm_tim1 : 0x06c82130
Address@gxc_timer : 0x07d62630
Address@mot_timer0 : 0x49200830
Address@mot_timer1 : 0x492008b0
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
systime_s_irq
Systime sec Interrupt
2 "0"
timer2_irq
Timer 2 Interrupt
1 "0"
timer1_irq
Timer 1 Interrupt
0 "0"
timer0_irq
Timer 0 Interrupt


timer_irq_masked
ARM_TIMER Masked IRQ register:
Shows status of masked IRQs (as connected to ARM/xPIC)
R
Address@iol_arm_tim0 : 0x000820b4
Address@iol_arm_tim1 : 0x00082134
Address@ada_arm_tim0 : 0x001020b4
Address@ada_arm_tim1 : 0x00102134
Address@cada_arm_tim0 : 0x001110b4
Address@cada_arm_tim1 : 0x00111134
Address@com_cda_rx_arm_tim0 : 0x067110b4
Address@com_cda_rx_arm_tim1 : 0x06711134
Address@com_cda_tx_arm_tim0 : 0x069110b4
Address@com_cda_tx_arm_tim1 : 0x06911134
Address@com_ada_arm_tim0 : 0x06b020b4
Address@com_ada_arm_tim1 : 0x06b02134
Address@com_iol_arm_tim0 : 0x06c820b4
Address@com_iol_arm_tim1 : 0x06c82134
Address@gxc_timer : 0x07d62634
Address@mot_timer0 : 0x49200834
Address@mot_timer1 : 0x492008b4
Bits Name Description
31 - 4 -
 reserved
3 systime_s_irq
Systime sec Interrupt
2 timer2_irq
Timer 2 Interrupt
1 timer1_irq
Timer 1 Interrupt
0 timer0_irq
Timer 0 Interrupt


timer_irq_msk_set
ARM_TIMER interrupt mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to arm_timer_irq_raw.
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820b8
Address@iol_arm_tim1 : 0x00082138
Address@ada_arm_tim0 : 0x001020b8
Address@ada_arm_tim1 : 0x00102138
Address@cada_arm_tim0 : 0x001110b8
Address@cada_arm_tim1 : 0x00111138
Address@com_cda_rx_arm_tim0 : 0x067110b8
Address@com_cda_rx_arm_tim1 : 0x06711138
Address@com_cda_tx_arm_tim0 : 0x069110b8
Address@com_cda_tx_arm_tim1 : 0x06911138
Address@com_ada_arm_tim0 : 0x06b020b8
Address@com_ada_arm_tim1 : 0x06b02138
Address@com_iol_arm_tim0 : 0x06c820b8
Address@com_iol_arm_tim1 : 0x06c82138
Address@gxc_timer : 0x07d62638
Address@mot_timer0 : 0x49200838
Address@mot_timer1 : 0x492008b8
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
systime_s_irq
Systime sec Interrupt
2 "0"
timer2_irq
Timer 2 Interrupt
1 "0"
timer1_irq
Timer 1 Interrupt
0 "0"
timer0_irq
Timer 0 Interrupt


timer_irq_msk_reset
ARM_TIMER interrupt mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820bc
Address@iol_arm_tim1 : 0x0008213c
Address@ada_arm_tim0 : 0x001020bc
Address@ada_arm_tim1 : 0x0010213c
Address@cada_arm_tim0 : 0x001110bc
Address@cada_arm_tim1 : 0x0011113c
Address@com_cda_rx_arm_tim0 : 0x067110bc
Address@com_cda_rx_arm_tim1 : 0x0671113c
Address@com_cda_tx_arm_tim0 : 0x069110bc
Address@com_cda_tx_arm_tim1 : 0x0691113c
Address@com_ada_arm_tim0 : 0x06b020bc
Address@com_ada_arm_tim1 : 0x06b0213c
Address@com_iol_arm_tim0 : 0x06c820bc
Address@com_iol_arm_tim1 : 0x06c8213c
Address@gxc_timer : 0x07d6263c
Address@mot_timer0 : 0x4920083c
Address@mot_timer1 : 0x492008bc
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
systime_s_irq
Systime sec Interrupt
2 "0"
timer2_irq
Timer 2 Interrupt
1 "0"
timer1_irq
Timer 1 Interrupt
0 "0"
timer0_irq
Timer 0 Interrupt


timer_systime_config
Select systime  for arm_timer_systime_(ns)s functions
R/W
0x00000000
Address@iol_arm_tim0 : 0x000820c0
Address@iol_arm_tim1 : 0x00082140
Address@ada_arm_tim0 : 0x001020c0
Address@ada_arm_tim1 : 0x00102140
Address@cada_arm_tim0 : 0x001110c0
Address@cada_arm_tim1 : 0x00111140
Address@com_cda_rx_arm_tim0 : 0x067110c0
Address@com_cda_rx_arm_tim1 : 0x06711140
Address@com_cda_tx_arm_tim0 : 0x069110c0
Address@com_cda_tx_arm_tim1 : 0x06911140
Address@com_ada_arm_tim0 : 0x06b020c0
Address@com_ada_arm_tim1 : 0x06b02140
Address@com_iol_arm_tim0 : 0x06c820c0
Address@com_iol_arm_tim1 : 0x06c82140
Address@gxc_timer : 0x07d62640
Address@mot_timer0 : 0x49200840
Address@mot_timer1 : 0x492008c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
systime_config
systime  for timer (2'b10.. systime_counter, 2'b01.. systime_global, 2'b00.. systime)



Base Address Area: ada_ram_ctrl, com_ada_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_ada_0_mbist_power0
1 4 R/W gen_ram_ctrl_ada_0_mbist_power1
2 8 R/W gen_ram_ctrl_ada_0_mbist_power2
3 c R/W gen_ram_ctrl_ada_0_mbist_power3
4 10 R/W gen_ram_ctrl_ada_0_mbist_power4
5 14 R/W gen_ram_ctrl_ada_0_mbist_power5
6 18 R/W gen_ram_ctrl_ada_0_mbist_power6
7 1c R/W gen_ram_ctrl_ada_0_mbist_power7
8 20 R/W gen_ram_ctrl_ada_0_mbist_power8
9 24 R/W gen_ram_ctrl_ada_0_mbist_power9
a 28 R/W gen_ram_ctrl_ada_0_mbist_power10
b 2c R/W gen_ram_ctrl_ada_0_mbist_power11
c 30 R/W gen_ram_ctrl_ada_0_mbist_power12
d 34 R/W gen_ram_ctrl_ada_0_mbist_power13
e 38 R/W gen_ram_ctrl_ada_0_mbist_power14
f 3c R/W gen_ram_ctrl_ada_0_mbist_power15
10 40 R/W gen_ram_ctrl_ada_0_mbist_power16
11 44 R/W gen_ram_ctrl_ada_0_mbist_power17
12 48 R/W gen_ram_ctrl_ada_0_mbist_power18
13 4c R/W gen_ram_ctrl_ada_0_mbist_power19
14 50 R/W gen_ram_ctrl_ada_0_mbist_power20
15 54 R/W gen_ram_ctrl_ada_0_mbist_power21
16 58 R/W gen_ram_ctrl_ada_0_mbist_power22
17 5c R/W gen_ram_ctrl_ada_0_mbist_power23
18 60 R/W gen_ram_ctrl_ada_0_mbist_power24
19 64 R/W gen_ram_ctrl_ada_0_mbist_power25
1a 68 R/W gen_ram_ctrl_ada_0_mbist_power26
1b 6c R/W gen_ram_ctrl_ada_0_mbist_power27
1c 70 R/W gen_ram_ctrl_ada_0_mbist_power28
1d 74 R/W gen_ram_ctrl_ada_0_mbist_power29
1e 78 R/W gen_ram_ctrl_ada_0_mbist_power30
1f 7c R/W gen_ram_ctrl_ada_0_mbist_power31
20 80 R/W gen_ram_ctrl_ada_0_mbist_power32
21 84 R/W gen_ram_ctrl_ada_0_mbist_power33
22 88 R/W gen_ram_ctrl_ada_0_mbist_power34
23 8c R/W gen_ram_ctrl_ada_0_mbist_power35
24 90 R/W gen_ram_ctrl_ada_0_mbist_power36
25 94 R/W gen_ram_ctrl_ada_0_mbist_power37
26 98 R/W gen_ram_ctrl_ada_0_mbist_power38
27 9c R/W gen_ram_ctrl_ada_0_mbist_power39
28 a0 R/W gen_ram_ctrl_ada_0_mbist_power40
29 a4 R/W gen_ram_ctrl_ada_0_mbist_power41
2a-1ff a8-7fc -  reserved
200 800 R/W gen_ram_ctrl_ada_0_ecc0
201 804 R/W gen_ram_ctrl_ada_0_ecc1
202 808 R/W gen_ram_ctrl_ada_0_ecc2
203 80c R/W gen_ram_ctrl_ada_0_ecc3
204-27f 810-9fc -  reserved
280 a00 R gen_ram_ctrl_ada_0_ecc_status_corr0
281 a04 R gen_ram_ctrl_ada_0_ecc_status_corr1
282 a08 R gen_ram_ctrl_ada_0_ecc_status_corr2
283 a0c R gen_ram_ctrl_ada_0_ecc_status_corr3
284-2ff a10-bfc -  reserved
300 c00 R gen_ram_ctrl_ada_0_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_ada_0_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_ada_0_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_ada_0_ecc_status_noncorr3
304-37f c10-dfc -  reserved
380 e00 R/W gen_ram_ctrl_ada_0_irq_raw_reg0
381 e04 R/W gen_ram_ctrl_ada_0_irq_raw_reg1
382-38f e08-e3c -  reserved
390 e40 R/W gen_ram_ctrl_ada_0_irq_masked_reg0
391 e44 R/W gen_ram_ctrl_ada_0_irq_masked_reg1
392-39f e48-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_ada_0_irq_mask_set_reg0
3a1 e84 R/W gen_ram_ctrl_ada_0_irq_mask_set_reg1
3a2-3af e88-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_ada_0_irq_mask_rst_reg0
3b1 ec4 R/W gen_ram_ctrl_ada_0_irq_mask_rst_reg1
3b2-3be ec8-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_ada_0_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_ada_0_mbist_power0
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100000
Address@com_ada_ram_ctrl : 0x06b00000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power1
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100004
Address@com_ada_ram_ctrl : 0x06b00004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power2
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100008
Address@com_ada_ram_ctrl : 0x06b00008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power3
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010000c
Address@com_ada_ram_ctrl : 0x06b0000c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power4
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100010
Address@com_ada_ram_ctrl : 0x06b00010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power5
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100014
Address@com_ada_ram_ctrl : 0x06b00014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power6
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100018
Address@com_ada_ram_ctrl : 0x06b00018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power7
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010001c
Address@com_ada_ram_ctrl : 0x06b0001c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power8
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100020
Address@com_ada_ram_ctrl : 0x06b00020
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power9
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100024
Address@com_ada_ram_ctrl : 0x06b00024
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power10
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100028
Address@com_ada_ram_ctrl : 0x06b00028
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power11
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010002c
Address@com_ada_ram_ctrl : 0x06b0002c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power12
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100030
Address@com_ada_ram_ctrl : 0x06b00030
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power13
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100034
Address@com_ada_ram_ctrl : 0x06b00034
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power14
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100038
Address@com_ada_ram_ctrl : 0x06b00038
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power15
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010003c
Address@com_ada_ram_ctrl : 0x06b0003c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power16
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100040
Address@com_ada_ram_ctrl : 0x06b00040
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power17
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100044
Address@com_ada_ram_ctrl : 0x06b00044
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power18
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100048
Address@com_ada_ram_ctrl : 0x06b00048
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power19
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010004c
Address@com_ada_ram_ctrl : 0x06b0004c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power20
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[0].BANKS_WAY[0].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100050
Address@com_ada_ram_ctrl : 0x06b00050
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power21
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[0].BANKS_WAY[1].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100054
Address@com_ada_ram_ctrl : 0x06b00054
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power22
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[1].BANKS_WAY[0].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100058
Address@com_ada_ram_ctrl : 0x06b00058
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power23
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[1].BANKS_WAY[1].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010005c
Address@com_ada_ram_ctrl : 0x06b0005c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power24
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_tag_inst.PACKED_0.WAYS[0].ECC1.size_128.ic_way_tag.ram_inst (128x26 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100060
Address@com_ada_ram_ctrl : 0x06b00060
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power25
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_tag_inst.PACKED_0.WAYS[1].ECC1.size_128.ic_way_tag.ram_inst (128x26 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100064
Address@com_ada_ram_ctrl : 0x06b00064
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power26
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[0].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100068
Address@com_ada_ram_ctrl : 0x06b00068
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power27
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[0].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010006c
Address@com_ada_ram_ctrl : 0x06b0006c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power28
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[1].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100070
Address@com_ada_ram_ctrl : 0x06b00070
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power29
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[1].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100074
Address@com_ada_ram_ctrl : 0x06b00074
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power30
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[2].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100078
Address@com_ada_ram_ctrl : 0x06b00078
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power31
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[2].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010007c
Address@com_ada_ram_ctrl : 0x06b0007c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power32
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[3].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100080
Address@com_ada_ram_ctrl : 0x06b00080
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power33
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[3].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100084
Address@com_ada_ram_ctrl : 0x06b00084
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power34
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[4].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100088
Address@com_ada_ram_ctrl : 0x06b00088
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power35
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[4].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010008c
Address@com_ada_ram_ctrl : 0x06b0008c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power36
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[5].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100090
Address@com_ada_ram_ctrl : 0x06b00090
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power37
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[5].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100094
Address@com_ada_ram_ctrl : 0x06b00094
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power38
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[6].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x00100098
Address@com_ada_ram_ctrl : 0x06b00098
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power39
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[6].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x0010009c
Address@com_ada_ram_ctrl : 0x06b0009c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power40
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[7].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x001000a0
Address@com_ada_ram_ctrl : 0x06b000a0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_mbist_power41
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[7].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (1024x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@ada_ram_ctrl : 0x001000a4
Address@com_ada_ram_ctrl : 0x06b000a4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ada_0_ecc0
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100800
Address@com_ada_ram_ctrl : 0x06b00800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_ada_0_ecc1
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100804
Address@com_ada_ram_ctrl : 0x06b00804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_ada_0_ecc2
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100808
Address@com_ada_ram_ctrl : 0x06b00808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_ada_0_ecc3
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@ada_ram_ctrl : 0x0010080c
Address@com_ada_ram_ctrl : 0x06b0080c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_ada_0_ecc_status_corr0
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100a00
Address@com_ada_ram_ctrl : 0x06b00a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_corr1
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100a04
Address@com_ada_ram_ctrl : 0x06b00a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_corr2
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100a08
Address@com_ada_ram_ctrl : 0x06b00a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_corr3
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100a0c
Address@com_ada_ram_ctrl : 0x06b00a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_noncorr0
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100c00
Address@com_ada_ram_ctrl : 0x06b00c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_noncorr1
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100c04
Address@com_ada_ram_ctrl : 0x06b00c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_noncorr2
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100c08
Address@com_ada_ram_ctrl : 0x06b00c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_ecc_status_noncorr3
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@ada_ram_ctrl : 0x00100c0c
Address@com_ada_ram_ctrl : 0x06b00c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ada_0_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e00
Address@com_ada_ram_ctrl : 0x06b00e00
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_ada_0_irq_raw_reg1
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e04
Address@com_ada_ram_ctrl : 0x06b00e04
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_ada_0_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_ada_0_irq_raw_reg0).
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e40
Address@com_ada_ram_ctrl : 0x06b00e40
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_ada_0_irq_masked_reg1
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_ada_0_irq_raw_reg1).
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e44
Address@com_ada_ram_ctrl : 0x06b00e44
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_ada_0_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_ada_0_irq_raw_reg0
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e80
Address@com_ada_ram_ctrl : 0x06b00e80
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_ada_0_irq_mask_set_reg1
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_ada_0_irq_raw_reg1
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100e84
Address@com_ada_ram_ctrl : 0x06b00e84
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_ada_0_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 50 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_0_err_ecc_correctable
  5  : irq_reg0-mem_1_err_ecc_correctable
  6  : irq_reg0-mem_2_err_ecc_correctable
  7  : irq_reg0-mem_3_err_ecc_correctable
  8  : irq_reg0-mem_0_mbist_or_init_finished
  9  : irq_reg0-mem_1_mbist_or_init_finished
  10 : irq_reg0-mem_2_mbist_or_init_finished
  11 : irq_reg0-mem_3_mbist_or_init_finished
  12 : irq_reg0-mem_4_mbist_or_init_finished
  13 : irq_reg0-mem_5_mbist_or_init_finished
  14 : irq_reg0-mem_6_mbist_or_init_finished
  15 : irq_reg0-mem_7_mbist_or_init_finished
  16 : irq_reg0-mem_8_mbist_or_init_finished
  17 : irq_reg0-mem_9_mbist_or_init_finished
  18 : irq_reg0-mem_10_mbist_or_init_finished
  19 : irq_reg0-mem_11_mbist_or_init_finished
  20 : irq_reg0-mem_12_mbist_or_init_finished
  21 : irq_reg0-mem_13_mbist_or_init_finished
  22 : irq_reg0-mem_14_mbist_or_init_finished
  23 : irq_reg0-mem_15_mbist_or_init_finished
  24 : irq_reg0-mem_16_mbist_or_init_finished
  25 : irq_reg0-mem_17_mbist_or_init_finished
  26 : irq_reg0-mem_18_mbist_or_init_finished
  27 : irq_reg0-mem_19_mbist_or_init_finished
  28 : irq_reg0-mem_20_mbist_or_init_finished
  29 : irq_reg0-mem_21_mbist_or_init_finished
  30 : irq_reg0-mem_22_mbist_or_init_finished
  31 : irq_reg0-mem_23_mbist_or_init_finished
  32 : irq_reg1-mem_24_mbist_or_init_finished
  33 : irq_reg1-mem_25_mbist_or_init_finished
  34 : irq_reg1-mem_26_mbist_or_init_finished
  35 : irq_reg1-mem_27_mbist_or_init_finished
  36 : irq_reg1-mem_28_mbist_or_init_finished
  37 : irq_reg1-mem_29_mbist_or_init_finished
  38 : irq_reg1-mem_30_mbist_or_init_finished
  39 : irq_reg1-mem_31_mbist_or_init_finished
  40 : irq_reg1-mem_32_mbist_or_init_finished
  41 : irq_reg1-mem_33_mbist_or_init_finished
  42 : irq_reg1-mem_34_mbist_or_init_finished
  43 : irq_reg1-mem_35_mbist_or_init_finished
  44 : irq_reg1-mem_36_mbist_or_init_finished
  45 : irq_reg1-mem_37_mbist_or_init_finished
  46 : irq_reg1-mem_38_mbist_or_init_finished
  47 : irq_reg1-mem_39_mbist_or_init_finished
  48 : irq_reg1-mem_40_mbist_or_init_finished
  49 : irq_reg1-mem_41_mbist_or_init_finished
  50 : no active IRQ
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100ec0
Address@com_ada_ram_ctrl : 0x06b00ec0
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_ada_0_irq_mask_rst_reg1
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 50 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_0_err_ecc_correctable
  5  : irq_reg0-mem_1_err_ecc_correctable
  6  : irq_reg0-mem_2_err_ecc_correctable
  7  : irq_reg0-mem_3_err_ecc_correctable
  8  : irq_reg0-mem_0_mbist_or_init_finished
  9  : irq_reg0-mem_1_mbist_or_init_finished
  10 : irq_reg0-mem_2_mbist_or_init_finished
  11 : irq_reg0-mem_3_mbist_or_init_finished
  12 : irq_reg0-mem_4_mbist_or_init_finished
  13 : irq_reg0-mem_5_mbist_or_init_finished
  14 : irq_reg0-mem_6_mbist_or_init_finished
  15 : irq_reg0-mem_7_mbist_or_init_finished
  16 : irq_reg0-mem_8_mbist_or_init_finished
  17 : irq_reg0-mem_9_mbist_or_init_finished
  18 : irq_reg0-mem_10_mbist_or_init_finished
  19 : irq_reg0-mem_11_mbist_or_init_finished
  20 : irq_reg0-mem_12_mbist_or_init_finished
  21 : irq_reg0-mem_13_mbist_or_init_finished
  22 : irq_reg0-mem_14_mbist_or_init_finished
  23 : irq_reg0-mem_15_mbist_or_init_finished
  24 : irq_reg0-mem_16_mbist_or_init_finished
  25 : irq_reg0-mem_17_mbist_or_init_finished
  26 : irq_reg0-mem_18_mbist_or_init_finished
  27 : irq_reg0-mem_19_mbist_or_init_finished
  28 : irq_reg0-mem_20_mbist_or_init_finished
  29 : irq_reg0-mem_21_mbist_or_init_finished
  30 : irq_reg0-mem_22_mbist_or_init_finished
  31 : irq_reg0-mem_23_mbist_or_init_finished
  32 : irq_reg1-mem_24_mbist_or_init_finished
  33 : irq_reg1-mem_25_mbist_or_init_finished
  34 : irq_reg1-mem_26_mbist_or_init_finished
  35 : irq_reg1-mem_27_mbist_or_init_finished
  36 : irq_reg1-mem_28_mbist_or_init_finished
  37 : irq_reg1-mem_29_mbist_or_init_finished
  38 : irq_reg1-mem_30_mbist_or_init_finished
  39 : irq_reg1-mem_31_mbist_or_init_finished
  40 : irq_reg1-mem_32_mbist_or_init_finished
  41 : irq_reg1-mem_33_mbist_or_init_finished
  42 : irq_reg1-mem_34_mbist_or_init_finished
  43 : irq_reg1-mem_35_mbist_or_init_finished
  44 : irq_reg1-mem_36_mbist_or_init_finished
  45 : irq_reg1-mem_37_mbist_or_init_finished
  46 : irq_reg1-mem_38_mbist_or_init_finished
  47 : irq_reg1-mem_39_mbist_or_init_finished
  48 : irq_reg1-mem_40_mbist_or_init_finished
  49 : irq_reg1-mem_41_mbist_or_init_finished
  50 : no active IRQ
R/W
0x00000000
Address@ada_ram_ctrl : 0x00100ec4
Address@com_ada_ram_ctrl : 0x06b00ec4
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_ada_0_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address@ada_ram_ctrl : 0x00100efc
Address@com_ada_ram_ctrl : 0x06b00efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: cada_ram_ctrl, com_cda_rx_ram_ctrl, com_cda_tx_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_cada_0_mbist_power0
1 4 R/W gen_ram_ctrl_cada_0_mbist_power1
2 8 R/W gen_ram_ctrl_cada_0_mbist_power2
3 c R/W gen_ram_ctrl_cada_0_mbist_power3
4 10 R/W gen_ram_ctrl_cada_0_mbist_power4
5 14 R/W gen_ram_ctrl_cada_0_mbist_power5
6 18 R/W gen_ram_ctrl_cada_0_mbist_power6
7 1c R/W gen_ram_ctrl_cada_0_mbist_power7
8 20 R/W gen_ram_ctrl_cada_0_mbist_power8
9 24 R/W gen_ram_ctrl_cada_0_mbist_power9
a 28 R/W gen_ram_ctrl_cada_0_mbist_power10
b 2c R/W gen_ram_ctrl_cada_0_mbist_power11
c 30 R/W gen_ram_ctrl_cada_0_mbist_power12
d 34 R/W gen_ram_ctrl_cada_0_mbist_power13
e 38 R/W gen_ram_ctrl_cada_0_mbist_power14
f 3c R/W gen_ram_ctrl_cada_0_mbist_power15
10 40 R/W gen_ram_ctrl_cada_0_mbist_power16
11 44 R/W gen_ram_ctrl_cada_0_mbist_power17
12 48 R/W gen_ram_ctrl_cada_0_mbist_power18
13 4c R/W gen_ram_ctrl_cada_0_mbist_power19
14 50 R/W gen_ram_ctrl_cada_0_mbist_power20
15 54 R/W gen_ram_ctrl_cada_0_mbist_power21
16 58 R/W gen_ram_ctrl_cada_0_mbist_power22
17 5c R/W gen_ram_ctrl_cada_0_mbist_power23
18 60 R/W gen_ram_ctrl_cada_0_mbist_power24
19 64 R/W gen_ram_ctrl_cada_0_mbist_power25
1a 68 R/W gen_ram_ctrl_cada_0_mbist_power26
1b 6c R/W gen_ram_ctrl_cada_0_mbist_power27
1c 70 R/W gen_ram_ctrl_cada_0_mbist_power28
1d 74 R/W gen_ram_ctrl_cada_0_mbist_power29
1e 78 R/W gen_ram_ctrl_cada_0_mbist_power30
1f 7c R/W gen_ram_ctrl_cada_0_mbist_power31
20 80 R/W gen_ram_ctrl_cada_0_mbist_power32
21 84 R/W gen_ram_ctrl_cada_0_mbist_power33
22 88 R/W gen_ram_ctrl_cada_0_mbist_power34
23 8c R/W gen_ram_ctrl_cada_0_mbist_power35
24 90 R/W gen_ram_ctrl_cada_0_mbist_power36
25 94 R/W gen_ram_ctrl_cada_0_mbist_power37
26 98 R/W gen_ram_ctrl_cada_0_mbist_power38
27 9c R/W gen_ram_ctrl_cada_0_mbist_power39
28 a0 R/W gen_ram_ctrl_cada_0_mbist_power40
29 a4 R/W gen_ram_ctrl_cada_0_mbist_power41
2a a8 R/W gen_ram_ctrl_cada_0_mbist_power42
2b ac R/W gen_ram_ctrl_cada_0_mbist_power43
2c b0 R/W gen_ram_ctrl_cada_0_mbist_power44
2d b4 R/W gen_ram_ctrl_cada_0_mbist_power45
2e-1ff b8-7fc -  reserved
200 800 R/W gen_ram_ctrl_cada_0_ecc0
201 804 R/W gen_ram_ctrl_cada_0_ecc1
202 808 R/W gen_ram_ctrl_cada_0_ecc2
203 80c R/W gen_ram_ctrl_cada_0_ecc3
204-27f 810-9fc -  reserved
280 a00 R gen_ram_ctrl_cada_0_ecc_status_corr0
281 a04 R gen_ram_ctrl_cada_0_ecc_status_corr1
282 a08 R gen_ram_ctrl_cada_0_ecc_status_corr2
283 a0c R gen_ram_ctrl_cada_0_ecc_status_corr3
284-2ff a10-bfc -  reserved
300 c00 R gen_ram_ctrl_cada_0_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_cada_0_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_cada_0_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_cada_0_ecc_status_noncorr3
304-37f c10-dfc -  reserved
380 e00 R/W gen_ram_ctrl_cada_0_irq_raw_reg0
381 e04 R/W gen_ram_ctrl_cada_0_irq_raw_reg1
382-38f e08-e3c -  reserved
390 e40 R/W gen_ram_ctrl_cada_0_irq_masked_reg0
391 e44 R/W gen_ram_ctrl_cada_0_irq_masked_reg1
392-39f e48-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_cada_0_irq_mask_set_reg0
3a1 e84 R/W gen_ram_ctrl_cada_0_irq_mask_set_reg1
3a2-3af e88-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_cada_0_irq_mask_rst_reg0
3b1 ec4 R/W gen_ram_ctrl_cada_0_irq_mask_rst_reg1
3b2-3be ec8-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_cada_0_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_cada_0_mbist_power0
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100000
Address@com_cda_rx_ram_ctrl : 0x06700000
Address@com_cda_tx_ram_ctrl : 0x06900000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power1
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100004
Address@com_cda_rx_ram_ctrl : 0x06700004
Address@com_cda_tx_ram_ctrl : 0x06900004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power2
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100008
Address@com_cda_rx_ram_ctrl : 0x06700008
Address@com_cda_tx_ram_ctrl : 0x06900008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power3
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010000c
Address@com_cda_rx_ram_ctrl : 0x0670000c
Address@com_cda_tx_ram_ctrl : 0x0690000c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power4
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[0].dccm.dccm_bank.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100010
Address@com_cda_rx_ram_ctrl : 0x06700010
Address@com_cda_tx_ram_ctrl : 0x06900010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power5
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100014
Address@com_cda_rx_ram_ctrl : 0x06700014
Address@com_cda_tx_ram_ctrl : 0x06900014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power6
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100018
Address@com_cda_rx_ram_ctrl : 0x06700018
Address@com_cda_tx_ram_ctrl : 0x06900018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power7
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010001c
Address@com_cda_rx_ram_ctrl : 0x0670001c
Address@com_cda_tx_ram_ctrl : 0x0690001c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power8
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100020
Address@com_cda_rx_ram_ctrl : 0x06700020
Address@com_cda_tx_ram_ctrl : 0x06900020
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power9
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[1].dccm.dccm_bank.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100024
Address@com_cda_rx_ram_ctrl : 0x06700024
Address@com_cda_tx_ram_ctrl : 0x06900024
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power10
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100028
Address@com_cda_rx_ram_ctrl : 0x06700028
Address@com_cda_tx_ram_ctrl : 0x06900028
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power11
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010002c
Address@com_cda_rx_ram_ctrl : 0x0670002c
Address@com_cda_tx_ram_ctrl : 0x0690002c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power12
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100030
Address@com_cda_rx_ram_ctrl : 0x06700030
Address@com_cda_tx_ram_ctrl : 0x06900030
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power13
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100034
Address@com_cda_rx_ram_ctrl : 0x06700034
Address@com_cda_tx_ram_ctrl : 0x06900034
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power14
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[2].dccm.dccm_bank.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100038
Address@com_cda_rx_ram_ctrl : 0x06700038
Address@com_cda_tx_ram_ctrl : 0x06900038
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power15
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010003c
Address@com_cda_rx_ram_ctrl : 0x0670003c
Address@com_cda_tx_ram_ctrl : 0x0690003c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power16
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100040
Address@com_cda_rx_ram_ctrl : 0x06700040
Address@com_cda_tx_ram_ctrl : 0x06900040
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power17
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100044
Address@com_cda_rx_ram_ctrl : 0x06700044
Address@com_cda_tx_ram_ctrl : 0x06900044
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power18
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100048
Address@com_cda_rx_ram_ctrl : 0x06700048
Address@com_cda_tx_ram_ctrl : 0x06900048
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power19
MBIST/power control and status register
For memory eh2_i.mem.Gen_dccm_enable.dccm.mem_bank[3].dccm.dccm_bank.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (4096x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010004c
Address@com_cda_rx_ram_ctrl : 0x0670004c
Address@com_cda_tx_ram_ctrl : 0x0690004c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power20
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100050
Address@com_cda_rx_ram_ctrl : 0x06700050
Address@com_cda_tx_ram_ctrl : 0x06900050
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power21
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100054
Address@com_cda_rx_ram_ctrl : 0x06700054
Address@com_cda_tx_ram_ctrl : 0x06900054
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power22
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100058
Address@com_cda_rx_ram_ctrl : 0x06700058
Address@com_cda_tx_ram_ctrl : 0x06900058
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power23
MBIST/power control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010005c
Address@com_cda_rx_ram_ctrl : 0x0670005c
Address@com_cda_tx_ram_ctrl : 0x0690005c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power24
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[0].BANKS_WAY[0].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100060
Address@com_cda_rx_ram_ctrl : 0x06700060
Address@com_cda_tx_ram_ctrl : 0x06900060
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power25
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[0].BANKS_WAY[1].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100064
Address@com_cda_rx_ram_ctrl : 0x06700064
Address@com_cda_tx_ram_ctrl : 0x06900064
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power26
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[1].BANKS_WAY[0].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100068
Address@com_cda_rx_ram_ctrl : 0x06700068
Address@com_cda_tx_ram_ctrl : 0x06900068
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power27
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_data_inst.PACKED_0.WAYS[1].BANKS_WAY[1].ECC1.size_512.ic_bank_sb_way_data.ram_inst (512x71 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010006c
Address@com_cda_rx_ram_ctrl : 0x0670006c
Address@com_cda_tx_ram_ctrl : 0x0690006c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power28
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_tag_inst.PACKED_0.WAYS[0].ECC1.size_128.ic_way_tag.ram_inst (128x26 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100070
Address@com_cda_rx_ram_ctrl : 0x06700070
Address@com_cda_tx_ram_ctrl : 0x06900070
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power29
MBIST/power control and status register
For memory eh2_i.mem.icache.icm.ic_tag_inst.PACKED_0.WAYS[1].ECC1.size_128.ic_way_tag.ram_inst (128x26 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100074
Address@com_cda_rx_ram_ctrl : 0x06700074
Address@com_cda_tx_ram_ctrl : 0x06900074
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power30
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[0].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100078
Address@com_cda_rx_ram_ctrl : 0x06700078
Address@com_cda_tx_ram_ctrl : 0x06900078
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power31
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[0].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010007c
Address@com_cda_rx_ram_ctrl : 0x0670007c
Address@com_cda_tx_ram_ctrl : 0x0690007c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power32
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[1].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100080
Address@com_cda_rx_ram_ctrl : 0x06700080
Address@com_cda_tx_ram_ctrl : 0x06900080
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power33
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[1].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100084
Address@com_cda_rx_ram_ctrl : 0x06700084
Address@com_cda_tx_ram_ctrl : 0x06900084
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power34
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[2].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100088
Address@com_cda_rx_ram_ctrl : 0x06700088
Address@com_cda_tx_ram_ctrl : 0x06900088
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power35
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[2].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010008c
Address@com_cda_rx_ram_ctrl : 0x0670008c
Address@com_cda_tx_ram_ctrl : 0x0690008c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power36
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[3].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100090
Address@com_cda_rx_ram_ctrl : 0x06700090
Address@com_cda_tx_ram_ctrl : 0x06900090
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power37
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[3].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100094
Address@com_cda_rx_ram_ctrl : 0x06700094
Address@com_cda_tx_ram_ctrl : 0x06900094
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power38
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[4].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x00100098
Address@com_cda_rx_ram_ctrl : 0x06700098
Address@com_cda_tx_ram_ctrl : 0x06900098
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power39
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[4].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x0010009c
Address@com_cda_rx_ram_ctrl : 0x0670009c
Address@com_cda_tx_ram_ctrl : 0x0690009c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power40
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[5].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000a0
Address@com_cda_rx_ram_ctrl : 0x067000a0
Address@com_cda_tx_ram_ctrl : 0x069000a0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power41
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[5].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000a4
Address@com_cda_rx_ram_ctrl : 0x067000a4
Address@com_cda_tx_ram_ctrl : 0x069000a4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power42
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[6].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000a8
Address@com_cda_rx_ram_ctrl : 0x067000a8
Address@com_cda_tx_ram_ctrl : 0x069000a8
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power43
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[6].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000ac
Address@com_cda_rx_ram_ctrl : 0x067000ac
Address@com_cda_tx_ram_ctrl : 0x069000ac
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power44
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[7].iccm.iccm_bank.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000b0
Address@com_cda_rx_ram_ctrl : 0x067000b0
Address@com_cda_tx_ram_ctrl : 0x069000b0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_mbist_power45
MBIST/power control and status register
For memory eh2_i.mem.iccm.iccm.mem_bank[7].iccm.iccm_bank.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (2048x39 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address@cada_ram_ctrl : 0x001000b4
Address@com_cda_rx_ram_ctrl : 0x067000b4
Address@com_cda_tx_ram_ctrl : 0x069000b4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_cada_0_ecc0
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100800
Address@com_cda_rx_ram_ctrl : 0x06700800
Address@com_cda_tx_ram_ctrl : 0x06900800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_cada_0_ecc1
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100804
Address@com_cda_rx_ram_ctrl : 0x06700804
Address@com_cda_tx_ram_ctrl : 0x06900804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_cada_0_ecc2
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100808
Address@com_cda_rx_ram_ctrl : 0x06700808
Address@com_cda_tx_ram_ctrl : 0x06900808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_cada_0_ecc3
ECC control and status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
R/W
0x00000000
Address@cada_ram_ctrl : 0x0010080c
Address@com_cda_rx_ram_ctrl : 0x0670080c
Address@com_cda_tx_ram_ctrl : 0x0690080c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_cada_0_ecc_status_corr0
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100a00
Address@com_cda_rx_ram_ctrl : 0x06700a00
Address@com_cda_tx_ram_ctrl : 0x06900a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_corr1
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100a04
Address@com_cda_rx_ram_ctrl : 0x06700a04
Address@com_cda_tx_ram_ctrl : 0x06900a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_corr2
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100a08
Address@com_cda_rx_ram_ctrl : 0x06700a08
Address@com_cda_tx_ram_ctrl : 0x06900a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_corr3
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100a0c
Address@com_cda_rx_ram_ctrl : 0x06700a0c
Address@com_cda_tx_ram_ctrl : 0x06900a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_noncorr0
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100c00
Address@com_cda_rx_ram_ctrl : 0x06700c00
Address@com_cda_tx_ram_ctrl : 0x06900c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_noncorr1
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[0].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100c04
Address@com_cda_rx_ram_ctrl : 0x06700c04
Address@com_cda_tx_ram_ctrl : 0x06900c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_noncorr2
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[0].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100c08
Address@com_cda_rx_ram_ctrl : 0x06700c08
Address@com_cda_tx_ram_ctrl : 0x06900c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_ecc_status_noncorr3
ECC status register
For memory eh2_i.mem.btb.btb.BANKS[1].WAYS[1].btb_mem_512.btb_banki_j.ram_inst (64x60 bits excluding any parity bits)
The memory includes ECC/parity per 30 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@cada_ram_ctrl : 0x00100c0c
Address@com_cda_rx_ram_ctrl : 0x06700c0c
Address@com_cda_tx_ram_ctrl : 0x06900c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_cada_0_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e00
Address@com_cda_rx_ram_ctrl : 0x06700e00
Address@com_cda_tx_ram_ctrl : 0x06900e00
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_cada_0_irq_raw_reg1
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e04
Address@com_cda_rx_ram_ctrl : 0x06700e04
Address@com_cda_tx_ram_ctrl : 0x06900e04
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_cada_0_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_cada_0_irq_raw_reg0).
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e40
Address@com_cda_rx_ram_ctrl : 0x06700e40
Address@com_cda_tx_ram_ctrl : 0x06900e40
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_cada_0_irq_masked_reg1
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_cada_0_irq_raw_reg1).
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e44
Address@com_cda_rx_ram_ctrl : 0x06700e44
Address@com_cda_tx_ram_ctrl : 0x06900e44
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_cada_0_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_cada_0_irq_raw_reg0
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e80
Address@com_cda_rx_ram_ctrl : 0x06700e80
Address@com_cda_tx_ram_ctrl : 0x06900e80
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_cada_0_irq_mask_set_reg1
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_cada_0_irq_raw_reg1
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100e84
Address@com_cda_rx_ram_ctrl : 0x06700e84
Address@com_cda_tx_ram_ctrl : 0x06900e84
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_cada_0_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 54 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_0_err_ecc_correctable
  5  : irq_reg0-mem_1_err_ecc_correctable
  6  : irq_reg0-mem_2_err_ecc_correctable
  7  : irq_reg0-mem_3_err_ecc_correctable
  8  : irq_reg0-mem_0_mbist_or_init_finished
  9  : irq_reg0-mem_1_mbist_or_init_finished
  10 : irq_reg0-mem_2_mbist_or_init_finished
  11 : irq_reg0-mem_3_mbist_or_init_finished
  12 : irq_reg0-mem_4_mbist_or_init_finished
  13 : irq_reg0-mem_5_mbist_or_init_finished
  14 : irq_reg0-mem_6_mbist_or_init_finished
  15 : irq_reg0-mem_7_mbist_or_init_finished
  16 : irq_reg0-mem_8_mbist_or_init_finished
  17 : irq_reg0-mem_9_mbist_or_init_finished
  18 : irq_reg0-mem_10_mbist_or_init_finished
  19 : irq_reg0-mem_11_mbist_or_init_finished
  20 : irq_reg0-mem_12_mbist_or_init_finished
  21 : irq_reg0-mem_13_mbist_or_init_finished
  22 : irq_reg0-mem_14_mbist_or_init_finished
  23 : irq_reg0-mem_15_mbist_or_init_finished
  24 : irq_reg0-mem_16_mbist_or_init_finished
  25 : irq_reg0-mem_17_mbist_or_init_finished
  26 : irq_reg0-mem_18_mbist_or_init_finished
  27 : irq_reg0-mem_19_mbist_or_init_finished
  28 : irq_reg0-mem_20_mbist_or_init_finished
  29 : irq_reg0-mem_21_mbist_or_init_finished
  30 : irq_reg0-mem_22_mbist_or_init_finished
  31 : irq_reg0-mem_23_mbist_or_init_finished
  32 : irq_reg1-mem_24_mbist_or_init_finished
  33 : irq_reg1-mem_25_mbist_or_init_finished
  34 : irq_reg1-mem_26_mbist_or_init_finished
  35 : irq_reg1-mem_27_mbist_or_init_finished
  36 : irq_reg1-mem_28_mbist_or_init_finished
  37 : irq_reg1-mem_29_mbist_or_init_finished
  38 : irq_reg1-mem_30_mbist_or_init_finished
  39 : irq_reg1-mem_31_mbist_or_init_finished
  40 : irq_reg1-mem_32_mbist_or_init_finished
  41 : irq_reg1-mem_33_mbist_or_init_finished
  42 : irq_reg1-mem_34_mbist_or_init_finished
  43 : irq_reg1-mem_35_mbist_or_init_finished
  44 : irq_reg1-mem_36_mbist_or_init_finished
  45 : irq_reg1-mem_37_mbist_or_init_finished
  46 : irq_reg1-mem_38_mbist_or_init_finished
  47 : irq_reg1-mem_39_mbist_or_init_finished
  48 : irq_reg1-mem_40_mbist_or_init_finished
  49 : irq_reg1-mem_41_mbist_or_init_finished
  50 : irq_reg1-mem_42_mbist_or_init_finished
  51 : irq_reg1-mem_43_mbist_or_init_finished
  52 : irq_reg1-mem_44_mbist_or_init_finished
  53 : irq_reg1-mem_45_mbist_or_init_finished
  54 : no active IRQ
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100ec0
Address@com_cda_rx_ram_ctrl : 0x06700ec0
Address@com_cda_tx_ram_ctrl : 0x06900ec0
Bits Reset value Name Description
31 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_cada_0_irq_mask_rst_reg1
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 54 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_0_err_ecc_correctable
  5  : irq_reg0-mem_1_err_ecc_correctable
  6  : irq_reg0-mem_2_err_ecc_correctable
  7  : irq_reg0-mem_3_err_ecc_correctable
  8  : irq_reg0-mem_0_mbist_or_init_finished
  9  : irq_reg0-mem_1_mbist_or_init_finished
  10 : irq_reg0-mem_2_mbist_or_init_finished
  11 : irq_reg0-mem_3_mbist_or_init_finished
  12 : irq_reg0-mem_4_mbist_or_init_finished
  13 : irq_reg0-mem_5_mbist_or_init_finished
  14 : irq_reg0-mem_6_mbist_or_init_finished
  15 : irq_reg0-mem_7_mbist_or_init_finished
  16 : irq_reg0-mem_8_mbist_or_init_finished
  17 : irq_reg0-mem_9_mbist_or_init_finished
  18 : irq_reg0-mem_10_mbist_or_init_finished
  19 : irq_reg0-mem_11_mbist_or_init_finished
  20 : irq_reg0-mem_12_mbist_or_init_finished
  21 : irq_reg0-mem_13_mbist_or_init_finished
  22 : irq_reg0-mem_14_mbist_or_init_finished
  23 : irq_reg0-mem_15_mbist_or_init_finished
  24 : irq_reg0-mem_16_mbist_or_init_finished
  25 : irq_reg0-mem_17_mbist_or_init_finished
  26 : irq_reg0-mem_18_mbist_or_init_finished
  27 : irq_reg0-mem_19_mbist_or_init_finished
  28 : irq_reg0-mem_20_mbist_or_init_finished
  29 : irq_reg0-mem_21_mbist_or_init_finished
  30 : irq_reg0-mem_22_mbist_or_init_finished
  31 : irq_reg0-mem_23_mbist_or_init_finished
  32 : irq_reg1-mem_24_mbist_or_init_finished
  33 : irq_reg1-mem_25_mbist_or_init_finished
  34 : irq_reg1-mem_26_mbist_or_init_finished
  35 : irq_reg1-mem_27_mbist_or_init_finished
  36 : irq_reg1-mem_28_mbist_or_init_finished
  37 : irq_reg1-mem_29_mbist_or_init_finished
  38 : irq_reg1-mem_30_mbist_or_init_finished
  39 : irq_reg1-mem_31_mbist_or_init_finished
  40 : irq_reg1-mem_32_mbist_or_init_finished
  41 : irq_reg1-mem_33_mbist_or_init_finished
  42 : irq_reg1-mem_34_mbist_or_init_finished
  43 : irq_reg1-mem_35_mbist_or_init_finished
  44 : irq_reg1-mem_36_mbist_or_init_finished
  45 : irq_reg1-mem_37_mbist_or_init_finished
  46 : irq_reg1-mem_38_mbist_or_init_finished
  47 : irq_reg1-mem_39_mbist_or_init_finished
  48 : irq_reg1-mem_40_mbist_or_init_finished
  49 : irq_reg1-mem_41_mbist_or_init_finished
  50 : irq_reg1-mem_42_mbist_or_init_finished
  51 : irq_reg1-mem_43_mbist_or_init_finished
  52 : irq_reg1-mem_44_mbist_or_init_finished
  53 : irq_reg1-mem_45_mbist_or_init_finished
  54 : no active IRQ
R/W
0x00000000
Address@cada_ram_ctrl : 0x00100ec4
Address@com_cda_rx_ram_ctrl : 0x06700ec4
Address@com_cda_tx_ram_ctrl : 0x06900ec4
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_cada_0_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address@cada_ram_ctrl : 0x00100efc
Address@com_cda_rx_ram_ctrl : 0x06700efc
Address@com_cda_tx_ram_ctrl : 0x06900efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: cada_config, ada_config, com_cda_rx_config, com_cda_tx_config, com_ada_config

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W eh2_power_mgmt
1 4 R eh2_power_mgmt_info
2 8 R/W eh2_rst_ctrl
3 c R/W eh2_rst_vec
4 10 R/W eh2_nmi_vec
5 14 W eh2_set_softint
6 18 W eh2_reset_softint
7 1c R eh2_softint
8-3f 20-fc -  reserved

eh2_power_mgmt
EH2 power management register
R/W
0x0000000c
Address@cada_config : 0x00101000
Address@ada_config : 0x00101000
Address@com_cda_rx_config : 0x06701000
Address@com_cda_tx_config : 0x06901000
Address@com_ada_config : 0x06b01000
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 2 "11"
halt_req
Assert to halt thread $
halt_req[0] : Request thread 0 to halt
halt_req[1] : Request thread 1 to halt
1 - 0 "00"
run_req
Assert to request thread $ to run.
run_req[0] : Request thread 0 to run
run_req[1] : Request thread 1 to run


eh2_power_mgmt_info
EH2 power management info register
R
Address@cada_config : 0x00101004
Address@ada_config : 0x00101004
Address@com_cda_rx_config : 0x06701004
Address@com_cda_tx_config : 0x06901004
Address@com_ada_config : 0x06b01004
Bits Name Description
31 - 9 -
 reserved
8 wdg_active
High indicates that the EH2 local watchdog is running
7 - 6 debug_mode_status
High indicates thread is in debug mode and
shouldn't be halted.
debug_mode_status[0] == 1 : Thread 0 is in debug mode.
debug_mode_status[1] == 1 : Thread 1 is in debug mode.
5 - 4 halt_status
High indicates thread is halted.
halt_status[0] == 1 : Thread 0 is halted.
halt_status[1] == 1 : Thread 1 is halted.
3 - 2 halt_ack
High if EH2 thread acknowledges halt request
halt_ack[0]==1 : Thread 0 acknowledges halt request
halt_ack[1]==1 : Thread 1 acknowledges halt request
1 - 0 run_ack
High if EH2 thread acknowledges run request
run_ack[0]==1 : Thread 0 acknowledges run request
run_ack[1]==1 : Thread 1 acknowledges run request


eh2_rst_ctrl
EH2 reset control register
R/W
0x00000000
Address@cada_config : 0x00101008
Address@ada_config : 0x00101008
Address@com_cda_rx_config : 0x06701008
Address@com_cda_tx_config : 0x06901008
Address@com_ada_config : 0x06b01008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
cpu_reset_n
CPU reset, active low. Reset and NMI vector must be
stable before release.


eh2_rst_vec
EH2 reset vector register
R/W
0xee000000
Address@cada_config : 0x0010100c
Address@ada_config : 0x0010100c
Address@com_cda_rx_config : 0x0670100c
Address@com_cda_tx_config : 0x0690100c
Address@com_ada_config : 0x06b0100c
Bits Reset value Name Description
31 - 0 0xee000000
reset_vector
start address after power-on-reset
Must be stable several cycles before reset release!


eh2_nmi_vec
EH2 non-maskable interrupt vector register
R/W
0xee000000
Address@cada_config : 0x00101010
Address@ada_config : 0x00101010
Address@com_cda_rx_config : 0x06701010
Address@com_cda_tx_config : 0x06901010
Address@com_ada_config : 0x06b01010
Bits Reset value Name Description
31 - 0 0xee000000
nmi_vector
jump-address of non-maskable interrupt
Must be stable several cycles before reset release!


eh2_set_softint
EH2 set software interrupt for thread 0 or 1
W
0x00000000
Address@cada_config : 0x00101014
Address@ada_config : 0x00101014
Address@com_cda_rx_config : 0x06701014
Address@com_cda_tx_config : 0x06901014
Address@com_ada_config : 0x06b01014
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
thread_1
Set software interrupt for thread 1
this bit will be reset automatically by hardware
0 "0"
thread_0
Set software interrupt for thread 0
this bit will be reset automatically by hardware


eh2_reset_softint
EH2 reset software interrupt for thread 0 or 1
W
0x00000000
Address@cada_config : 0x00101018
Address@ada_config : 0x00101018
Address@com_cda_rx_config : 0x06701018
Address@com_cda_tx_config : 0x06901018
Address@com_ada_config : 0x06b01018
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
thread_1
Reset software interrupt for thread 1
this bit will be reset automatically by hardware
0 "0"
thread_0
Reset software interrupt for thread 0
this bit will be reset automatically by hardware


eh2_softint
EH2 read status of software interrupt for thread 0 and/or 1
R
Address@cada_config : 0x0010101c
Address@ada_config : 0x0010101c
Address@com_cda_rx_config : 0x0670101c
Address@com_cda_tx_config : 0x0690101c
Address@com_ada_config : 0x06b0101c
Bits Name Description
31 - 2 -
 reserved
1 thread_1
Status of software interrupt for thread 1
0 thread_0
Status of software interrupt for thread 0



Base Address Area: cada_internal_ise_dma, ise_dma, com_ise_dma, com_cda_rx_ise_dma, com_cda_tx_ise_dma, app_ise_dma

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ise_dma_cfg
1 4 R/W ise_dma_axi_cfg
2 8 R ise_dma_status
3 c R ise_dma_debug_axi_read_addr
4 10 R ise_dma_debug_axi_write_addr
5 14 R/W ise_dma_debug_cfg
6 18 R ise_dma_current_job
7 1c R ise_dma_last_job
8 20 W ise_dma_ctrl
9 24 W ise_dma_job_queue_push
a 28 R ise_dma_job_done_queue_read
b 2c -  reserved
c 30 R/W ise_dma_irq_raw
d 34 R/W ise_dma_irq_masked
e 38 R/W ise_dma_irq_mask_set
f 3c R/W ise_dma_irq_mask_rst

ise_dma_cfg
general configuration
R/W
0x00001008
Address@cada_internal_ise_dma : 0x00110000
Address@ise_dma : 0x06430000
Address@com_ise_dma : 0x06430000
Address@com_cda_rx_ise_dma : 0x06710000
Address@com_cda_tx_ise_dma : 0x06910000
Address@app_ise_dma : 0x400e0000
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
job_done_queue_lists
Enqueue only the first job of a job list into the job done queue, as soon as the last job in the list is finished or aborted either successfully or with error. If ctrl_job_list_abort is issued, the current job effectively becomes the last job in the list.
13 "0"
job_done_queue_enable
Use the job done queue. If the queue is full, jobs won't be processed further and the ISE stalls.
12 - 8 "10000"
job_done_queue_wm
job done queue watermark for irq
7 - 5 0
-
 reserved
4 - 0 "01000"
job_queue_wm
job queue watermark for irq


ise_dma_axi_cfg
configuration of AXI address channels
R/W
0x07070912
Address@cada_internal_ise_dma : 0x00110004
Address@ise_dma : 0x06430004
Address@com_ise_dma : 0x06430004
Address@com_cda_rx_ise_dma : 0x06710004
Address@com_cda_tx_ise_dma : 0x06910004
Address@app_ise_dma : 0x400e0004
Bits Reset value Name Description
31 - 24 "00000111"
max_burst_len_write
maximum burst length minus 1 on the write channel
23 - 16 "00000111"
max_burst_len_read
maximum burst length minus 1 on the write channel
15 - 14 0
-
 reserved
13 - 11 "001"
awprot
PROT signal of AXI-AW channel   (default: Normal Non-cacheable Bufferable)
10 - 7 "0010"
awcache
CACHE signal of AXI-AW channel  (default: Non-Privileged, Non-Secure, Data)
6 - 4 "001"
arprot
PROT signal of AXI-AR channel   (default: Normal Non-cacheable Bufferable)
3 - 0 "0010"
arcache
CACHE signal of AXI-AR channel  (default: Non-Privileged, Non-Secure, Data)


ise_dma_status
status register
R
Address@cada_internal_ise_dma : 0x00110008
Address@ise_dma : 0x06430008
Address@com_ise_dma : 0x06430008
Address@com_cda_rx_ise_dma : 0x06710008
Address@com_cda_tx_ise_dma : 0x06910008
Address@app_ise_dma : 0x400e0008
Bits Name Description
31 waiting_for_job_abort
after an erroneous job finished the ISE waits for job_abort to continue
30 read_err_job_desc
indicates if an axi error occured while reading the job descriptor, the ISE will stop processing the job immediatly, waiting_for_job_abort will be 1 as well
29 job_done_queue_empty
indicates if the job done queue is empty
28 job_done_queue_full
indicates if the job done queue is full
27 - 23 job_done_queue_fill
fill level of job queue
22 idle
combines job_queue_empty and not job_in_progress
21 job_queue_empty
indicates if the job queue is empty
20 job_queue_full
indicates if the job queue is full
19 - 15 job_queue_fill
fill level of job queue
14 job_output_done
all data was written for the current job
13 job_output_busy
data is being written for the current job
12 job_process_done
all data was process for the current job
11 job_process_busy
data is being processed (crypt, hash, copy) for the current job
10 job_input_done
all data was read for the current job
9 job_input_busy
data is being read for the current job
8 job_in_progress
a job is currently in progress
7 - 4 job_cfg_err
job config error code
Change note: Error codes changed after netx22xx_mpw.
4'b0000: no error
4'b0001: minimal descriptor error, i.e. extra.mini_copy_desc is set and one more of the conditions is not fulfilled
4'b0010: no-op, i.e. HASH_ALGO_NONE and CRYPT_ALGO_NONE
4'b0011: AES key len undefined
4'b0100: padding undefined
4'b0101: multiple MACs, i.e. hash enabled without H2C feedback and together with AES-GCM or Poly1305
4'b0110: ChaCha no-op, i.e. CHACHA_DISABLED and POLY_DISABLED
4'b0111: feedback undefined
4'b1000: HMAC key len greater 128 (decimal)
3 - 2 axi_write_err
error during AXI write transaction, 00: no error, 10: slave error, 11: decoding error
1 - 0 axi_read_err
error during AXI read  transaction, 00: no error, 10: slave error, 11: decoding error


ise_dma_debug_axi_read_addr
current AXI read address which can be used in error cases to determine the failed access
R
Address@cada_internal_ise_dma : 0x0011000c
Address@ise_dma : 0x0643000c
Address@com_ise_dma : 0x0643000c
Address@com_cda_rx_ise_dma : 0x0671000c
Address@com_cda_tx_ise_dma : 0x0691000c
Address@app_ise_dma : 0x400e000c
Bits Name Description
31 - 0 val
current AXI read address


ise_dma_debug_axi_write_addr
current AXI write address which can be used in error cases to determine the failed access
R
Address@cada_internal_ise_dma : 0x00110010
Address@ise_dma : 0x06430010
Address@com_ise_dma : 0x06430010
Address@com_cda_rx_ise_dma : 0x06710010
Address@com_cda_tx_ise_dma : 0x06910010
Address@app_ise_dma : 0x400e0010
Bits Name Description
31 - 0 val
current AXI write address


ise_dma_debug_cfg
general configuration
R/W
0x02000700
Address@cada_internal_ise_dma : 0x00110014
Address@ise_dma : 0x06430014
Address@com_ise_dma : 0x06430014
Address@com_cda_rx_ise_dma : 0x06710014
Address@com_cda_tx_ise_dma : 0x06910014
Address@app_ise_dma : 0x400e0014
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 16 0x200
inactivity_threshold
threshold for the inactivity counter, i.e. after how many cycles of inactivity should the inactivity interrupt trigger
15 - 11 0
-
 reserved
10 - 8 "111"
desc_req_words
number of 64-bit words of the job descriptor that shall be requested in the first request, 0 and 1 will be interpreted as 2
7 - 1 0
-
 reserved
0 "0"
override_clock_en_ctrl
0: Clock enables are controlled from ise_dma_crypt, 1: Clock enables are always active


ise_dma_current_job
current job in progress, 0x00000000 if no job in progress
R
Address@cada_internal_ise_dma : 0x00110018
Address@ise_dma : 0x06430018
Address@com_ise_dma : 0x06430018
Address@com_cda_rx_ise_dma : 0x06710018
Address@com_cda_tx_ise_dma : 0x06910018
Address@app_ise_dma : 0x400e0018
Bits Name Description
31 - 0 ptr
address of the job currently in progress


ise_dma_last_job
last job that was finished successfully or with error
R
Address@cada_internal_ise_dma : 0x0011001c
Address@ise_dma : 0x0643001c
Address@com_ise_dma : 0x0643001c
Address@com_cda_rx_ise_dma : 0x0671001c
Address@com_cda_tx_ise_dma : 0x0691001c
Address@app_ise_dma : 0x400e001c
Bits Name Description
31 - 0 ptr
address of the last job


ise_dma_ctrl
manual intervention control
W
0x00000000
Address@cada_internal_ise_dma : 0x00110020
Address@ise_dma : 0x06430020
Address@com_ise_dma : 0x06430020
Address@com_cda_rx_ise_dma : 0x06710020
Address@com_cda_tx_ise_dma : 0x06910020
Address@app_ise_dma : 0x400e0020
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
axi_write_cancel
cancel all transactions of the axi write channels (NOT AXI CONFORM!)
6 "0"
axi_read_cancel
cancel all transactions of the axi read channels (NOT AXI CONFORM!)
5 "0"
axi_write_flush
flush the axi write channels (job_abort should be issued at the same time)
4 "0"
axi_read_flush
flush the axi read channels  (job_abort should be issued at the same time)
3 "0"
job_list_abort
aborts the current job list (excluding the current job)
2 "0"
job_abort
aborts the currently processing job (axi should be flushed at the same time)
1 "0"
job_done_queue_clear
clears the queue with completed jobs
0 "0"
job_queue_clear
clears the job queue


ise_dma_job_queue_push
job queue push register
W
0x00000000
Address@cada_internal_ise_dma : 0x00110024
Address@ise_dma : 0x06430024
Address@com_ise_dma : 0x06430024
Address@com_cda_rx_ise_dma : 0x06710024
Address@com_cda_tx_ise_dma : 0x06910024
Address@app_ise_dma : 0x400e0024
Bits Reset value Name Description
31 - 0 0x0
ptr
job address


ise_dma_job_done_queue_read
job done queue read register
R
Address@cada_internal_ise_dma : 0x00110028
Address@ise_dma : 0x06430028
Address@com_ise_dma : 0x06430028
Address@com_cda_rx_ise_dma : 0x06710028
Address@com_cda_tx_ise_dma : 0x06910028
Address@app_ise_dma : 0x400e0028
Bits Name Description
31 - 0 ptr
job address


ise_dma_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@cada_internal_ise_dma : 0x00110030
Address@ise_dma : 0x06430030
Address@com_ise_dma : 0x06430030
Address@com_cda_rx_ise_dma : 0x06710030
Address@com_cda_tx_ise_dma : 0x06910030
Address@app_ise_dma : 0x400e0030
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
waiting_for_job_abort
Event: triggers if the status bit waiting_for_job_abort is high
11 "0"
inactivity
Event: triggers if the inactivity counter reached the configured threshold
10 "0"
job_done_queue_wm
Event: triggers if the fill level of the queue with finished jobs is above or equal the configured watermark value
9 "0"
job_done_queue_full
Event: triggers if the queue with finished jobs is full
8 "0"
job_list_finished
Event: triggers simulatneous with job_finished if the current job is the last in the list, i.e. its next_job field indicates EOL
7 "0"
job_finished_error
Event: triggers simultaneous with job_finished if the job was NOT successful, i.e. errors occured
6 "0"
job_finished_ok
Event: triggers simultaneous with job_finished if the job was successful, i.e. no error occured
5 "0"
job_finished
Event: triggers when the current job is finished and pushed into the done queue if configured so
4 "0"
job_error
Event: triggers immediatly if an error occurs
3 "0"
job_queue_wm
Event: triggers if the fill level of the job queue is below or equal the configured watermark value
2 "0"
job_queue_full
Event: triggers if the job queue is full
1 "0"
job_queue_empty
Event: triggers if the job queue is empty
0 "0"
job_queue_overflow
Event: triggers if the job queue overflows, i.e. a job is pushed when the queue is full


ise_dma_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_ise_dma_irq_raw).
R/W
0x00000000
Address@cada_internal_ise_dma : 0x00110034
Address@ise_dma : 0x06430034
Address@com_ise_dma : 0x06430034
Address@com_cda_rx_ise_dma : 0x06710034
Address@com_cda_tx_ise_dma : 0x06910034
Address@app_ise_dma : 0x400e0034
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
waiting_for_job_abort
Event: triggers if the status bit waiting_for_job_abort is high
11 "0"
inactivity
Event: triggers if the inactivity counter reached the configured threshold
10 "0"
job_done_queue_wm
Event: triggers if the fill level of the queue with finished jobs is above or equal the configured watermark value
9 "0"
job_done_queue_full
Event: triggers if the queue with finished jobs is full
8 "0"
job_list_finished
Event: triggers simulatneous with job_finished if the current job is the last in the list, i.e. its next_job field indicates EOL
7 "0"
job_finished_error
Event: triggers simultaneous with job_finished if the job was NOT successful, i.e. errors occured
6 "0"
job_finished_ok
Event: triggers simultaneous with job_finished if the job was successful, i.e. no error occured
5 "0"
job_finished
Event: triggers when the current job is finished and pushed into the done queue if configured so
4 "0"
job_error
Event: triggers immediatly if an error occurs
3 "0"
job_queue_wm
Event: triggers if the fill level of the job queue is below or equal the configured watermark value
2 "0"
job_queue_full
Event: triggers if the job queue is full
1 "0"
job_queue_empty
Event: triggers if the job queue is empty
0 "0"
job_queue_overflow
Event: triggers if the job queue overflows, i.e. a job is pushed when the queue is full


ise_dma_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_ise_dma_irq_raw
R/W
0x00000000
Address@cada_internal_ise_dma : 0x00110038
Address@ise_dma : 0x06430038
Address@com_ise_dma : 0x06430038
Address@com_cda_rx_ise_dma : 0x06710038
Address@com_cda_tx_ise_dma : 0x06910038
Address@app_ise_dma : 0x400e0038
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
waiting_for_job_abort
Event: triggers if the status bit waiting_for_job_abort is high
11 "0"
inactivity
Event: triggers if the inactivity counter reached the configured threshold
10 "0"
job_done_queue_wm
Event: triggers if the fill level of the queue with finished jobs is above or equal the configured watermark value
9 "0"
job_done_queue_full
Event: triggers if the queue with finished jobs is full
8 "0"
job_list_finished
Event: triggers simulatneous with job_finished if the current job is the last in the list, i.e. its next_job field indicates EOL
7 "0"
job_finished_error
Event: triggers simultaneous with job_finished if the job was NOT successful, i.e. errors occured
6 "0"
job_finished_ok
Event: triggers simultaneous with job_finished if the job was successful, i.e. no error occured
5 "0"
job_finished
Event: triggers when the current job is finished and pushed into the done queue if configured so
4 "0"
job_error
Event: triggers immediatly if an error occurs
3 "0"
job_queue_wm
Event: triggers if the fill level of the job queue is below or equal the configured watermark value
2 "0"
job_queue_full
Event: triggers if the job queue is full
1 "0"
job_queue_empty
Event: triggers if the job queue is empty
0 "0"
job_queue_overflow
Event: triggers if the job queue overflows, i.e. a job is pushed when the queue is full


ise_dma_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 13 when no IRQ is set:
  0  : irq-job_queue_overflow
  1  : irq-job_queue_empty
  2  : irq-job_queue_full
  3  : irq-job_queue_wm
  4  : irq-job_error
  5  : irq-job_finished
  6  : irq-job_finished_ok
  7  : irq-job_finished_error
  8  : irq-job_list_finished
  9  : irq-job_done_queue_full
  10 : irq-job_done_queue_wm
  11 : irq-inactivity
  12 : irq-waiting_for_job_abort
  13 : no active IRQ
R/W
0x00000000
Address@cada_internal_ise_dma : 0x0011003c
Address@ise_dma : 0x0643003c
Address@com_ise_dma : 0x0643003c
Address@com_cda_rx_ise_dma : 0x0671003c
Address@com_cda_tx_ise_dma : 0x0691003c
Address@app_ise_dma : 0x400e003c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
waiting_for_job_abort
Event: triggers if the status bit waiting_for_job_abort is high
11 "0"
inactivity
Event: triggers if the inactivity counter reached the configured threshold
10 "0"
job_done_queue_wm
Event: triggers if the fill level of the queue with finished jobs is above or equal the configured watermark value
9 "0"
job_done_queue_full
Event: triggers if the queue with finished jobs is full
8 "0"
job_list_finished
Event: triggers simulatneous with job_finished if the current job is the last in the list, i.e. its next_job field indicates EOL
7 "0"
job_finished_error
Event: triggers simultaneous with job_finished if the job was NOT successful, i.e. errors occured
6 "0"
job_finished_ok
Event: triggers simultaneous with job_finished if the job was successful, i.e. no error occured
5 "0"
job_finished
Event: triggers when the current job is finished and pushed into the done queue if configured so
4 "0"
job_error
Event: triggers immediatly if an error occurs
3 "0"
job_queue_wm
Event: triggers if the fill level of the job queue is below or equal the configured watermark value
2 "0"
job_queue_full
Event: triggers if the job queue is full
1 "0"
job_queue_empty
Event: triggers if the job queue is empty
0 "0"
job_queue_overflow
Event: triggers if the job queue overflows, i.e. a job is pushed when the queue is full



Base Address Area: cvm_intram0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram512_base
1-1fffe 4-7fff8 -  reserved
1ffff 7fffc R/W intram512_end

intram512_base
Area size: 512kB
R/W
0x00000000
Address : 0x02000000
Bits Reset value Name Description
31 - 0 0
intram512_base


intram512_end
R/W
0x00000000
Address : 0x0207fffc
Bits Reset value Name Description
31 - 0 0
intram512_end



Base Address Area: cvm_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_4_mbist_power0
1-1ff 4-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_4_ecc0
201-27f 804-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_4_ecc_status_corr0
281-2ff a04-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_4_ecc_status_noncorr0
301-37f c04-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_4_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_4_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_4_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_4_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_4_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_4_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.cvm_i.cvm_mem_i.cvm_intram_i0 (65536x64 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x03f00000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_4_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.cvm_i.cvm_mem_i.cvm_intram_i0 (65536x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x03f00800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_4_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.cvm_i.cvm_mem_i.cvm_intram_i0 (65536x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x03f00a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_4_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.cvm_i.cvm_mem_i.cvm_intram_i0 (65536x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x03f00c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_4_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x03f00e00
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_4_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_4_irq_raw_reg0).
R/W
0x00000000
Address : 0x03f00e40
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_4_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_4_irq_raw_reg0
R/W
0x00000000
Address : 0x03f00e80
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_4_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 3 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_0_err_ecc_correctable
  2 : irq_reg0-mem_0_mbist_or_init_finished
  3 : no active IRQ
R/W
0x00000000
Address : 0x03f00ec0
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_4_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x03f00efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: com_intram0, com_intram1, com_intram2, sms_com_intram0, sms_com_intram1, sms_com_intram2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram1024_base
1-3fffe 4-ffff8 -  reserved
3ffff ffffc R/W intram1024_end

intram1024_base
Area size: 1024kB
R/W
0x00000000
Address@com_intram0 : 0x06000000
Address@com_intram1 : 0x06100000
Address@com_intram2 : 0x06200000
Address@sms_com_intram0 : 0x66000000
Address@sms_com_intram1 : 0x66100000
Address@sms_com_intram2 : 0x66200000
Bits Reset value Name Description
31 - 0 0
intram1024_base


intram1024_end
R/W
0x00000000
Address@com_intram0 : 0x060ffffc
Address@com_intram1 : 0x061ffffc
Address@com_intram2 : 0x062ffffc
Address@sms_com_intram0 : 0x660ffffc
Address@sms_com_intram1 : 0x661ffffc
Address@sms_com_intram2 : 0x662ffffc
Bits Reset value Name Description
31 - 0 0
intram1024_end



Base Address Area: com_i2c0, com_i2c1, app_i2c0, app_i2c1, mot_i2c0, mot_i2c1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W i2c_mcr
1 4 R/W i2c_scr
2 8 R/W i2c_cmd
3 c R/W i2c_mdr
4 10 R/W i2c_sdr
5 14 R/W i2c_mfifo_cr
6 18 R/W i2c_sfifo_cr
7 1c R/W i2c_sr
8 20 R/W i2c_irqmsk
9 24 R/W i2c_irqsr
a 28 R i2c_irqmsked
b 2c R/W i2c_dmacr
c 30 R/W i2c_pio
d-f 34-3c -  reserved

i2c_mcr
I2C master control register:
R/W
0x00000000
Address@com_i2c0 : 0x06400000
Address@com_i2c1 : 0x06400040
Address@app_i2c0 : 0x40080380
Address@app_i2c1 : 0x400803c0
Address@mot_i2c0 : 0x49200380
Address@mot_i2c1 : 0x492003c0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
en_timeout
Enable I2C command timeout detection.
Enabling the timeout detection is recommended to prevent the module from stalling if
another device holds the I2C signals permanently low.
For details, see the description of bit i2s_sr.timeout.
17 "0"
rst_i2c
Reset the I2C bus-state-detection logic.
To avoid conflicts with other masters, some I2C bus states, which are important when there are multiple
masters on the I2C bus, are always monitored, even if the I2C module is disabled. For details, see bits i2c_sr.started and i2c.bus_master.
However, it may happen that bus states are detected which lock up the I2C module. E.g. hazards during power-up or IO configuration or sequences, which are not I2C compliant, can cause a lock-up.
This bit can be used to escape from such a situation.
Write a '1' here to reset the I2C bus-state-detection logic of register i2c_sr.
Note: This bit is new since netX56. It is always '0' when read.
16 "0"
pio_mode
If this bit is set, SCL and SDA can be controlled directly by register i2c_pio (e.g. to access devices being incompatible with I2C).
In PIO mode, the I2C controller state machine is disabled: FIFOs are not used, no IRQs will be set, and no DMA controlling is possible.
15 - 11 0
-
 reserved
10 - 4 "0000000"
sadr
7-bit slave address sent after (r)START:
For 10-bit addressing, the first byte (10-bit start '11110', address bits[9:8] must be programmed here. The second start
byte (lower slave address bits) must be on top of the master FIFO (i2c_mdr).
This register must be rewritten (even if the value does not change) to address another slave in the 10-bit mode (run 2-byte start sequence). The register must
not be rewritten before a repeated START on the same 10-bit addressed slave (run 1-byte start sequence e.g. write to read change).
3 - 1 "000"
mode
I2C-speed-mode:
If this device is used as a slave only, the mode should be set to the data rate generated by the fastest master on the I2C-bus
for appropriate input filtering and spike suppression. The programmed mode defines also the SDA hold time after a falling
edge of SCL.
Value Mode SDA hold time after SCL low
  000 Fast/Standard mode, 50 kbit/s      630ns
  001 Fast/Standard mode, 100 kbit/s      630ns
  010 Fast/Standard mode, 200 kbit/s      630ns
  011 Fast/Standard mode, 400 kbit/s      310ns
  100 High-speed mode, 800 kbit/s      150ns
  101 High-speed mode, 1.2 Mbit/s       70ns
  110 High-speed mode, 1.7 Mbit/s       70ns
  111 High-speed mode, 3.4 Mbit/s       30ns
0 "0"
en_i2c
Global I2C controller enable
1: Enable I2C controller
0: Disable I2C controller
Disabling the I2C module during a transfer will immediately disconnect the I2C module
from the bus without generating a STOP. The internal I2C state machine will be set back to initial/idle state.
The I2C bus-state-detection for the bits i2c_sr.bus_master and i2c_sr.started are performed even if the
module is disabled. For details, see these bits.


i2c_scr
I2C slave control register:
R/W
0x00000000
Address@com_i2c0 : 0x06400004
Address@com_i2c1 : 0x06400044
Address@app_i2c0 : 0x40080384
Address@app_i2c1 : 0x400803c4
Address@mot_i2c0 : 0x49200384
Address@mot_i2c1 : 0x492003c4
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
autoreset_ac_start
Auto reset ac_start (ac_start must be set again after any (r)START):
0: ac_start will not be reset automatically (netX 50-compatible, but not recommended)
1: Reset ac_start after this slave acknowledged a start sequence (recommended)
19 0
-
 reserved
18 "0"
ac_gcall
General call acknowledge:
0: Do not generate an acknowledge after a general call
1: Generate an acknowledge after a general call
17 "0"
ac_start
Enable start sequence acknowledge:
If the received address matches the sid-bits, the start-byte (2 bytes if sid10 is set) will be acknowledged.
If the master requests a read transfer, a slave FIFO read access will be carried out immediately after the
acknowledge, i.e. valid data must be present in the slave FIFO before enabling the acknowledge.
If autoreset_ac_start is enabled, the controller will automatically reset this bit. If it is not enabled,
the software should reset this bit after the start sequence has been acknowledged to avoid acknowledge and FIFO errors
after the next (r)START.
0: Do not generate an acknowledge after the start sequence
1: Generate an acknowledge after the start sequence
This bit is writable, but can also be changed by hardware.
16 "0"
ac_srx
Enable slave-receive-data acknowledge:
0: Do not acknowledge receive bytes
1: Acknowledge receive bytes
If the slave FIFO is full, receive data will not be acknowledged.
15 - 11 0
-
 reserved
10 "0"
sid10
10-bit slave device ID/address:
0: Wait for 7-bit slave address after (r)START
1: Wait for 10-bit slave address after (r)START
9 - 0 0x0
sid
Slave device ID/address:
External masters can address this device (this I2C module in slave mode) by the ID/address
programmed here. If sid10 is not set, bits 9 to 7 will be ignored.


i2c_cmd
I2C master command register:
R/W
0x0000000e
Address@com_i2c0 : 0x06400008
Address@com_i2c1 : 0x06400048
Address@app_i2c0 : 0x40080388
Address@app_i2c1 : 0x400803c8
Address@mot_i2c0 : 0x49200388
Address@mot_i2c1 : 0x492003c8
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 20 "00000000"
acpollmax
Number of tries (acpollmax+1, i.e. 1 to 256) for start sequence acknowledge polling:
For 7-bit addressing, acknowledge polling START and the first byte containing the slave address (i2c_mcr.sadr) will be repeated up
to acpollmax+1 times until a slave generates an acknowledge. If no acknowledge is received within acpollmax+1 tries, IRQ cmd_err will be generated.
For 10-bit-addressing, the 2-byte start sequence is performed. The second address byte (lower address bits) must be on top of the
master FIFO (i2c_mdr). For subsequent transfers, the value programmed in tsize has to ignore this byte.
The programmed value of acpollmax will count down during acknowledge polling after each start sequence.
This bit is writable, but can also be changed by hardware.
19 - 18 0
-
 reserved
17 - 8 0x0
tsize
Transfer tsize+1 bytes (1...1024):
If no acknowledge is generated by the slave (receiver), write transfers will be terminated and IRQ cmd_err will be generated.
For 10-bit-addressing, the second start-byte (lower address bits) must be on top of the master FIFO. For subsequent transfers,
the value programmed here has to ignore this byte.
This value will count down during transfers after each byte.
This bit is writable, but can also be changed by hardware.
7 - 4 0
-
 reserved
3 - 1 "111"
cmd
I2C sequence command:
All commands will generate IRQ cmd_ok or IRQ cmd_err. A successful command termination will always generate IRQ cmd_ok. In
case of an unsuccessful command termination, IRQ cmd_err will be set.
000 START Generate (r)START-condition
001 S_AC Acknowledge-polling: generate up to acpollmax+1 START-sequences (until acknowledged by slave)
010 S_AC_T Run S_AC, then transfer tsize+1 bytes from/to master FIFO. Not to be continued
011 S_AC_TC Run S_AC, then transfer tsize+1 bytes from/to master FIFO. To be continued
100 CT Continued transfer not to be continued
101 CTC Continued transfer to be continued
110 STOP Generate STOP-condition
111 IDLE Nothing to do, last command finished, break current command

Sequences including read transfers that are not to be continued (S_AC_T, CT with 'nwr' bit set) will not generate an acknowledge after
the last received byte (read transfer ends).
Read transfers that are to be continued (S_AC_TC, CTC) will generate an acknowledge after the last received byte and must be
followed by CT or CTC.
Before continued transfers (CT, CTC), a command including START (START, S_AC, S_AC_T, S_AC_TC) must be executed to generate
a valid I2C sequence.
STOP must always be executed by software to free the bus after transfer end. STOP is not included in any command sequence and
never executed automatically by this module.
Some commands are handled as sequences (i.e. after setting S_AC_T, first S_AC then CT will be seen when read).
You need not poll for IDLE here before setting up a new command, but you have to wait for cmd_ok or cmd_err status
flags of register i2c_irqsr to be set.
This bit is writable, but can also be changed by hardware.
0 "0"
nwr
Transfer direction (not-write/read):
0: cmd will be executed as write
1: cmd will be executed as read
Master FIFO-requests (IRQ and DMA) are generated depending on this direction flag.


i2c_mdr
I2C master data register (master FIFO):
There is only one FIFO for both receive and transmit master data with a depth of 16 bytes. For a master write access, data read from the FIFO is
is sent via I2C. For a master read access, data received from I2C is written into the FIFO.
In case of imminent data transfer failure (read transfer and FIFO is full or write transfer and FIFO is empty), the transfer will be paused.
To continue the transfer, the FIFO must be handled first (filled for transmit, read out for receive).
Note: The FIFO behavior has been changed: For netX 51/52/56 and older versions, the current command was aborted and the cmd_err was raised.
R/W
0x00000000
Address@com_i2c0 : 0x0640000c
Address@com_i2c1 : 0x0640004c
Address@app_i2c0 : 0x4008038c
Address@app_i2c1 : 0x400803cc
Address@mot_i2c0 : 0x4920038c
Address@mot_i2c1 : 0x492003cc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
mdata
I2C master transmit or receive data:
Transmit data will be removed from the FIFO after the receiving slave has generated the corresponding acknowledge. Transmit
data that has not been acknowledged will not be removed from the FIFO.


i2c_sdr
I2C slave data register (slave FIFO):
There is only one FIFO for both receive and transmit slave data with a depth of 16 bytes. For a read access of an external master, data sent by this
slave is read from the FIFO. For a write access of an external master, data received by this slave is written into the FIFO.
A transfer is initiated after the detection of I2C-start-sequence to the device address (i2c_scr.sid, sreq IRQ) which is acknowledged by this
device (i2c_scr.ac_start). For read transfers, sent data is read from the FIFO immediately after the detection of the acknowledge on
the I2C-bus. SDA will be driven with the next data MSB immediately after the acknowledge SCL high phase.
In case of a master read transfer and slave FIFO underrun, corrupted data will be sent to the master and the IRQ fifo_err will be set.
In case of a master write transfer and slave FIFO is full, no acknowledge will be generated for the last received byte. No FIFO overflow
will occur, but the last transferred byte (not acknowledged) will be lost and has to be sent again by the master.
R/W
0x00000000
Address@com_i2c0 : 0x06400010
Address@com_i2c1 : 0x06400050
Address@app_i2c0 : 0x40080390
Address@app_i2c1 : 0x400803d0
Address@mot_i2c0 : 0x49200390
Address@mot_i2c1 : 0x492003d0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
sdata
I2C slave transmit or receive data:
The software must handle i2c_scr.ac_start correctly to avoid FIFO errors after (r)START.


i2c_mfifo_cr
I2C master FIFO control register:
R/W
0x00000000
Address@com_i2c0 : 0x06400014
Address@com_i2c1 : 0x06400054
Address@app_i2c0 : 0x40080394
Address@app_i2c1 : 0x400803d4
Address@mot_i2c0 : 0x49200394
Address@mot_i2c1 : 0x492003d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
mfifo_clr
Clear master data FIFO, write only bit.
This bit is writable, but can also be changed by hardware.
7 - 4 0
-
 reserved
3 - 0 "0000"
mfifo_wm
Master FIFO watermark for the generation of IRQ mfifo_req:
If the master is the transmitter (enabled and i2c_cmd.nwr is 0), IRQ mfifo_req is generated if mfifo_level smaller than mfifo_wm.
If the master is the receiver (enabled and i2c_cmd.nwr is 1), IRQ mfifo_req is generated if mfifo_level greater than mfifo_wm.
Note: Set the watermark to 0 at transfer end to avoid further IRQ generation.


i2c_sfifo_cr
I2C slave FIFO control register:
R/W
0x00000000
Address@com_i2c0 : 0x06400018
Address@com_i2c1 : 0x06400058
Address@app_i2c0 : 0x40080398
Address@app_i2c1 : 0x400803d8
Address@mot_i2c0 : 0x49200398
Address@mot_i2c1 : 0x492003d8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
sfifo_clr
Clear slave data FIFO, write only bit.
This bit is writable, but can also be changed by hardware.
7 - 4 0
-
 reserved
3 - 0 "0000"
sfifo_wm
Slave FIFO watermark for the generation of IRQ sfifo_req:
If the slave is the transmitter (start sequence with set read bit was acknowledged by this slave), IRQ sfifo_req is generated if sfifo_level smaller than sfifo_wm.
If the slave is not the transmitter (is receiver or not selected), IRQ sfifo_req is generated if sfifo_level greater than sfifo_wm.


i2c_sr
I2C status register:
R/W
0xc0110040
Address@com_i2c0 : 0x0640001c
Address@com_i2c1 : 0x0640005c
Address@app_i2c0 : 0x4008039c
Address@app_i2c1 : 0x400803dc
Address@mot_i2c0 : 0x4920039c
Address@mot_i2c1 : 0x492003dc
Bits Reset value Name Description
31 -
sda_state
SDA signal state sampled and filtered from bus (e.g. to detect bus blockings)
This is a read-only status bit.
30 -
scl_state
SCL signal state sampled and filtered from bus (e.g. to detect bus blockings)
This is a read-only status bit.
29 0
-
 reserved
28 "0"
timeout
I2C command timeout detection (for I2C master).
I2C slaves can stretch low SCL phases by holding the SCL line low. The master must detect this and
wait until the SCL line is released before the current transfer can continue. In error cases,
the I2C bus can be blocked permanently by a low signal state of SCL. The reason for the blocking can
be e.g. a crashed I2C slave or a false I/O configuration. To escape from such a situation,
a timeout watchdog is implemented:
A timeout will be detected if the SCL line is held low for more than 256 SCL periods. In
this case, the recent command will be terminated and IRQ cmd_err will be set. The
timeout detection must be enabled by bit i2c_mcr.en_timeout. It is
disabled by default for backward compatibility. However, enabling is strongly recommended.
If timeout is detected, the status bit must be cleared before a new command can be applied.
This status bit can be cleared by writing a '1' to it or when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
27 -
sid10_aced
10-bit slave address acknowledge state.
0: There was no 10-bit slave address or it was not acknowledged.
1:

A 10-bit slave address was broadcasted and a slave acknowledged this broadcast.
I.e. for the master side: A 10-bit slave was addressed and the slave acknowledged.
I.e. for the slave side: A master broadcasted a start with the address programmed in register i2c_scr.sid
and the i2c module acknowledged this broadcast as bit i2c_scr.ac_start is set.

This read-only status bit is cleared automatically when the module detects a STOP or when register i2c_mcr
is written (e.g. to perform a module reset by bit i2c_mcr.rst_i2c or to address another
slave by changing the bits i2c_mcr.sadr).
Remember that during rSTART, the master will generate only the first START-byte.
26 -
gcall_aced
General call acknowledge state.
0: No general call start-byte, or general call start-byte was not acknowledged.
1: The slave side of the i2c module received and acknowledged a general call.
Bit i2c_scr.ac_gcall controls the acknowledging of a general call. This read-only status bit will be cleared automatically if the last start-byte is not a general
call or if it is a general call but bit i2c_scr.ac_gcall is not set. This bit is forced to '0' when the bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: The bit has no function for the master side of the i2c module
25 -
nwr_aced
Transfer direction (nwr-bit) of the last acknowledged start-byte (or 2-byte start sequence for 10-bit addressing).
0: The last acknowledged start-byte defined a write transfer.
1: The last acknowledged start-byte defined a read transfer.
Slave FIFO requests generating IRQ and DMA requests depend on this direction flag.
This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
24 -
last_ac
Last acknowledge detected on bus.
0: SDA was high at the last acknowledge, i.e. no acknowledge.
1: SDA was low at the last acknowledge, i.e. acknowledge.
This read-only status bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
23 -
slave_access
Slave access state.
0: No slave access to this device.
1: A master addressed this slave device.
This read-only status bit is set if a start-byte (2 bytes for 10-bit address) containing the
address programmed in register i2c_scr.sid has been received.
This bit is always reset to 0 during START or STOP. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: This bit does not depend on whether the start-byte has been acknowledged or not.
22 -
started
START condition detection:
0: The bus is idle (STOP was detected, not started).
1: (r)START was detected on the bus. The bus is occupied.
This detection will also take place while the module is disabled. This is important if there are multiple
I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the
I2C module must not start a transfer, before the other master has released the bus.
Use bit i2c_mcr.rst_i2c to force this read-only status bit to '0', e.g. in order to escape from an accidentally
detected START or a START that is not followed by a STOP.
21 -
nwr
Transfer direction detected after last (r)START.
0: The last start-byte defined a write transfer.
1: The last start-byte defined a read transfer.
This read-only status bit is always reset to 0 during (r)START. This bit is forced to '0' when bit i2c_mcr.rst_i2c performs a reset of the bus-state-detection logic.
Note: This bit does not depend on whether the start-byte has been acknowledged or not.
20 -
bus_master
Bus arbitration state.
0: Master lost I2C bus arbitration, bus is busy by another master.
1: Master gains I2C bus arbitration or bus is idle.
This read-only status bit is set when the monitored bus state does not match the bus
state expected by the I2C module. The bit is reset, when a STOP is detected. This detection will also take place while the module is disabled. This is important if there are multiple
I2C masters on the bus: If another master occupies the bus while the I2C module is disabled, the
I2C module must not start a transfer, before the other master has released the bus.
Use bit i2c_mcr.rst_i2c to force this bit to '0', e.g. in order to escape from an arbitration loss
not followed by a STOP.
19 -
sfifo_err_undr
Slave FIFO underrun error occurred.
Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
18 -
sfifo_err_ovfl
Slave FIFO overflow error occurred.
Data is lost and the slave FIFO must be cleared by bit i2c_sfifo_cr.sfifo_clr. Clearing the slave FIFO will also clear this read-only status bit.
17 -
sfifo_full
Slave FIFO is full (1 if full)
This is a read-only status bit.
16 -
sfifo_empty
Slave FIFO is empty (1 if empty)
This is a read-only status bit.
15 0
-
 reserved
14 - 10 -
sfifo_level
Slave FIFO level (0..16)
This is a read-only status bit field.
9 -
mfifo_err_undr
Master FIFO underrun error occurred.
Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
Note: This can only happen in case of a CPU read accesses to an empty FIFO. The I2C statemachine will pause external transfers before FIFO underrun occurs.
8 -
mfifo_err_ovfl
Master FIFO overflow error occurred.
Data is lost and the master FIFO must be cleared by bit i2c_mfifo_cr.mfifo_clr. Clearing the master FIFO will also clear this read-only status bit.
Note: This can only happen in case of a CPU write accesses to a full FIFO. The I2C statemachine will pause external transfers before FIFO overflow occurs.
7 -
mfifo_full
Master FIFO is full (1 if full)
This is a read-only status bit.
6 -
mfifo_empty
Master FIFO is empty (1 if empty)
This is a read-only status bit.
5 0
-
 reserved
4 - 0 -
mfifo_level
Master FIFO level (0..16)
This is a read-only status bit field.


i2c_irqmsk
I2C interrupt mask set or clear register:
These bits have AND-mask character. The corresponding IRQ will generate the module IRQ only if the mask bit
is set. Changing a mask bit from '0' to '1' will clear the corresponding raw IRQ state. For a detailed IRQ
description, see i2c_irqraw.
R/W
0x00000000
Address@com_i2c0 : 0x06400020
Address@com_i2c1 : 0x06400060
Address@app_i2c0 : 0x400803a0
Address@app_i2c1 : 0x400803e0
Address@mot_i2c0 : 0x492003a0
Address@mot_i2c1 : 0x492003e0
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
sreq
Slave request interrupt mask
5 "0"
sfifo_req
Slave FIFO action request interrupt mask
4 "0"
mfifo_req
Master FIFO action request interrupt mask
3 "0"
bus_busy
External I2C-bus is busy interrupt mask
2 "0"
fifo_err
FIFO error interrupt mask
1 "0"
cmd_err
Command error interrupt mask
0 "0"
cmd_ok
Command OK interrupt mask


i2c_irqsr
I2C interrupt state register (raw interrupt before masking):
Writing '1' will clear the corresponding IRQ.
R/W
0x00000000
Address@com_i2c0 : 0x06400024
Address@com_i2c1 : 0x06400064
Address@app_i2c0 : 0x400803a4
Address@app_i2c1 : 0x400803e4
Address@mot_i2c0 : 0x492003a4
Address@mot_i2c1 : 0x492003e4
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
sreq
Unmasked slave request interrupt state:
Purpose: Set up slave FIFO
1: External master was running START-sequence and requested this slave
0: Slave is not requested
5 "0"
sfifo_req
Unmasked slave FIFO action request interrupt state:
Purpose: Slave FIFO should be updated
1: Slave FIFO request: i2c_sr.sfifo_level is above or below i2c_sfifo_cr.sfifo_wm (see description i2c_sfifo_cr)
0: Slave FIFO state not critical
4 "0"
mfifo_req
Unmasked master FIFO action request interrupt state:
Purpose: Master FIFO should be updated
1: Master FIFO request: i2c_sr.mfifo_level is above or below i2c_mfifo_cr.mfifo_wm (see description i2c_mfifo_cr)
0: Master FIFO state not critical
3 "0"
bus_busy
Unmasked external I2C-bus is busy interrupt state:
Purpose: Detect I2C-bus arbitration loss
1: Master did not gain the requested bus access because another master accessed the bus
0: Bus is idle or no transfer is requested by this master
2 "0"
fifo_err
Unmasked FIFO error interrupt state:
Purpose: Detect FIFO errors/transfer failures
1: FIFO error occurred, check register i2c_sr
0: FIFOs ok
1 "0"
cmd_err
Unmasked command error interrupt state:
Purpose: Check last command termination
1: Last command finished erroneously
0: Command not finished, no command or command finished successfully
0 "0"
cmd_ok
Unmasked command OK interrupt state:
Purpose: Check last command termination
1: Last command finished successfully
0: Command not finished, no command or command finished erroneously


i2c_irqmsked
I2C masked interrupt state register:
If one of these bits is set, the I2C IRQ will be set to the interrupt controller.
For a detailed IRQ description, see i2c_irqraw.
R
Address@com_i2c0 : 0x06400028
Address@com_i2c1 : 0x06400068
Address@app_i2c0 : 0x400803a8
Address@app_i2c1 : 0x400803e8
Address@mot_i2c0 : 0x492003a8
Address@mot_i2c1 : 0x492003e8
Bits Name Description
31 - 7 -
 reserved
6 sreq
Masked slave request interrupt state
5 sfifo_req
Masked slave FIFO action request interrupt state
4 mfifo_req
Masked master FIFO action request interrupt state
3 bus_busy
Masked external I2C-bus is busy interrupt state
2 fifo_err
Masked FIFO error interrupt state
1 cmd_err
Masked command error interrupt state
0 cmd_ok
Masked command OK interrupt state


i2c_dmacr
I2C DMA control register:
Required settings for the DMA controller:
- DMA transfer size to/from I2C module: Byte
- DMA burst length to/from I2C module: 4
DMA burst requests will be generated if the corresponding FIFO contains more than 4 bytes (receive case) or if
more than 4 bytes are writable to the corresponding FIFO (transmit case).
DMA single transfer requests will be generated if the corresponding FIFO contains more than 1 byte (receive case) or if
more than 1 byte is writable to the corresponding FIFO (transmit case).
No further DMA requests will be generated if all transmit data is written to the master FIFO and the i2c module is
the DMA flow controller (for master data only). Once all data is written
to the master FIFO, the last burst/single request will be generated for the DMA controller.
If the DMA controller sets DMACTC (terminal count) to indicate the end of transfer, the corresponding bit will be cleared.
If one of the bits of this register is set to 0 by software and a DMA transfer has been requested before, the DMA controller
will perform one last transfer to reset DMA request signals.
R/W
0x00000000
Address@com_i2c0 : 0x0640002c
Address@com_i2c1 : 0x0640006c
Address@app_i2c0 : 0x400803ac
Address@app_i2c1 : 0x400803ec
Address@mot_i2c0 : 0x492003ac
Address@mot_i2c1 : 0x492003ec
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdmab_en
Enable DMA burst requests for I2C slave data.
The DMA controller must be the flow controller.
This bit is writable, but can also be changed by hardware.
2 "0"
sdmas_en
Enable DMA single requests for I2C slave data.
The DMA controller must be the flow controller.
This bit is writable, but can also be changed by hardware.
1 "0"
mdmab_en
Enable DMA burst requests for I2C master data.
The I2C module is the flow controller (i.e. peripheral-controlled flow control).
Both, single and burst requests must be enabled.
This bit is writable, but can also be changed by hardware.
0 "0"
mdmas_en
Enable DMA single requests for I2C master data.
The I2C module is the flow controller (i.e. peripheral-controlled flow control).
Both, single and burst requests must be enabled.
This bit is writable, but can also be changed by hardware.


i2c_pio
PIO mode register:
This register can directly control the I2C signals SCL and SDA if pio_mode is enabled in register i2c_mcr. In PIO mode, the
I2C controller state machine is disabled, thus, no FIFO action takes place, no IRQs will be set, and no DMA-controlling is possible.
Note: To avoid external driving conflicts, the I2C signals SCL and SDA are never driven active-high according to
the I2C bus specification. The high level of these signals is realized by a pull-up (of the pad or externally) and by setting the appropriate output enable to 0 (scl_oe, sda_oe) instead of driving the level
active-high. Driving the signals directly by enabling the outputs (programming
the bits sda_oe or scl_oe to '1') can lead to driving conflicts and could cause damage.
R/W
0x00000044
Address@com_i2c0 : 0x06400030
Address@com_i2c1 : 0x06400070
Address@app_i2c0 : 0x400803b0
Address@app_i2c1 : 0x400803f0
Address@mot_i2c0 : 0x492003b0
Address@mot_i2c1 : 0x492003f0
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 -
sda_in_ro
SDA input state (read-only)
5 "0"
sda_oe
SDA output enable
0: Do not drive SDA, switch pad to high-z.
1: Drive SDA, switch pad to programmed sda_out-state
4 "0"
sda_out
Driving level of SDA (1: high, 0: low) if output is enabled (sda_oe is set)
3 0
-
 reserved
2 -
scl_in_ro
SCL input state (read-only)
1 "0"
scl_oe
SCL output enable
0: Do not drive SCL, switch pad to high-z.
1: Drive SCL, switch pad to programmed scl_out-state
0 "0"
scl_out
Driving level of SCL (1: high, 0: low) if output is enabled (scl_oe is set)



Base Address Area: com_uart0, com_uart1, app_uart0, app_uart1, mot_uart0, mot_uart1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W uartdr
1 4 R/W uartrsr
2 8 R/W uartlcr_h
3 c R/W uartlcr_m
4 10 R/W uartlcr_l
5 14 R/W uartcr
6 18 R uartfr
7 1c R/W uartiir
8 20 R/W uartilpr
9 24 R/W uartrts
a 28 R/W uartforerun
b 2c R/W uarttrail
c 30 R/W uartdrvout
d 34 R/W uartcr_2
e 38 R/W uartrxiflsel
f 3c R/W uarttxiflsel

uartdr
(NETX_UART%_DATA)
data read or written from the interface
R/W
0x00000000
Address@com_uart0 : 0x06400100
Address@com_uart1 : 0x06400140
Address@app_uart0 : 0x40080300
Address@app_uart1 : 0x40080340
Address@mot_uart0 : 0x49200300
Address@mot_uart1 : 0x49200340
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
BE
Break Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
9 "0"
PE
Parity Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
8 "0"
FE
Framing Error, read only, mirrored from uartrsr, to handle in DMA-read-out data
7 - 0 "00000000"
DATA
data read or written from the interface


uartrsr
(NETX_UART%_STAT)
receive status register (read) / Error Clear Register (write)
R/W
0x00000000
Address@com_uart0 : 0x06400104
Address@com_uart1 : 0x06400144
Address@app_uart0 : 0x40080304
Address@app_uart1 : 0x40080344
Address@mot_uart0 : 0x49200304
Address@mot_uart1 : 0x49200344
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
OE
Overrun Error
2 "0"
BE
Break Error
1 "0"
PE
Parity Error
0 "0"
FE
Framing Error


uartlcr_h
(NETX_UART%_LINE_CTRL)
Line control Register, high byte
R/W
0x00000000
Address@com_uart0 : 0x06400108
Address@com_uart1 : 0x06400148
Address@app_uart0 : 0x40080308
Address@app_uart1 : 0x40080348
Address@mot_uart0 : 0x49200308
Address@mot_uart1 : 0x49200348
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 - 5 "00"
WLEN
 Word Length
"00" 5 bits
"01" 6 bits
"10" 7 bits
"11" 8 bits
4 "0"
FEN
FIFO Enable
3 "0"
STP2
2 Stop Bits Select
2 "0"
EPS
Even Parity Select
1 "0"
PEN
Parity Enalble
0 "0"
BRK
Send Break


uartlcr_m
(NETX_UART%_BAUD_DIV_MSB)
Line control Register, middle byte
R/W
0x00000000
Address@com_uart0 : 0x0640010c
Address@com_uart1 : 0x0640014c
Address@app_uart0 : 0x4008030c
Address@app_uart1 : 0x4008034c
Address@mot_uart0 : 0x4920030c
Address@mot_uart1 : 0x4920034c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
BAUDDIVMS
bauddiv : Baud Divisor Most Significant Byte
use higher byte of bauddiv = (system clk / (16 * baud rate)) - 1
if not alternative settings by register uartcr_2 are done


uartlcr_l
(NETX_UART%_BAUD_DIV_LSB)
Line control Register, low byte
R/W
0x00000000
Address@com_uart0 : 0x06400110
Address@com_uart1 : 0x06400150
Address@app_uart0 : 0x40080310
Address@app_uart1 : 0x40080350
Address@mot_uart0 : 0x49200310
Address@mot_uart1 : 0x49200350
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
BAUDDIVLS
Baud Divisor Least Significant Byte
use lower byte of bauddiv = (system clk / (16 * baud rate)) - 1
if not alternative settings by register uartcr_2 are done


uartcr
(NETX_UART%_CTRL)
uart control Register
R/W
0x00000000
Address@com_uart0 : 0x06400114
Address@com_uart1 : 0x06400154
Address@app_uart0 : 0x40080314
Address@app_uart1 : 0x40080354
Address@mot_uart0 : 0x49200314
Address@mot_uart1 : 0x49200354
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
TX_RX_LOOP
internal loop (TX -> RX) (test purpose only)
7 "0"
LBE
Loop Back Enable for IrDA mode
6 "0"
RTIE
Receive Timeout Interrupt Enable
5 "0"
TIE
Transmit Interrupt Enable
4 "0"
RIE
Receive Interrupt Enable
3 "0"
MSIE
Modem Status Interrupt Enable
2 "0"
SIRLP
IrDA SIR Low Power Mode
1 "0"
SIREN
SIR Enable
0 "0"
uartEN
uart Enable


uartfr
(NETX_UART%_FLAG)
uart Flag Register
R
Address@com_uart0 : 0x06400118
Address@com_uart1 : 0x06400158
Address@app_uart0 : 0x40080318
Address@app_uart1 : 0x40080358
Address@mot_uart0 : 0x49200318
Address@mot_uart1 : 0x49200358
Bits Name Description
31 - 8 -
 reserved
7 TXFE
Transmit FIFO Empty
6 RXFF
Receive FIFO Full
5 TXFF
Transmit FIFO Full
4 RXFE
Receive FIFO Empty
3 BUSY
uart BUSY
2 DCD
Data Carrier Detect
1 DSR
Data Set Ready
0 CTS
Clear To Send


uartiir
(NETX_UART%_INT_ID)
Interrupt Identification (read) / interrupt clear (write)
R/W
0x00000000
Address@com_uart0 : 0x0640011c
Address@com_uart1 : 0x0640015c
Address@app_uart0 : 0x4008031c
Address@app_uart1 : 0x4008035c
Address@mot_uart0 : 0x4920031c
Address@mot_uart1 : 0x4920035c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
RTIS
Receive Timeout Interrupt Status
2 "0"
TIS
Transmit Interrupt Status
1 "0"
RIS
Receive Interrupt Status
0 "0"
MIS
Modem Interrupt Status


uartilpr
(NETX_UART%_IRDA_LO_PWR_CNTR)
IrDA Low Power Counter Register
R/W
0x00000000
Address@com_uart0 : 0x06400120
Address@com_uart1 : 0x06400160
Address@app_uart0 : 0x40080320
Address@app_uart1 : 0x40080360
Address@mot_uart0 : 0x49200320
Address@mot_uart1 : 0x49200360
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
ILPDVSR
IrDA Low Power Divisor


uartrts
(NETX_UART%_RTS_CTRL)
RTS Control Register
R/W
0x00000000
Address@com_uart0 : 0x06400124
Address@com_uart1 : 0x06400164
Address@app_uart0 : 0x40080324
Address@app_uart1 : 0x40080364
Address@mot_uart0 : 0x49200324
Address@mot_uart1 : 0x49200364
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
STICK
stick parity
6 "0"
CTS_pol
nUARTCTS polarity: 1=active high
5 "0"
CTS_ctr
nUARTCTS control
4 "0"
RTS_pol
RTS polarity: 1=active high
3 "0"
MOD2
mode1/mode2
2 "0"
COUNT
count base: 1=system clocks, 0=time in bauds
1 "0"
RTS
if AUTO=0: controlled by this bit
0 "0"
AUTO
automatic or controlled by the next bit (RTS)


uartforerun
(NETX_UART%_RTS_LEAD_CYC)
RTS forerun cycles
R/W
0x00000000
Address@com_uart0 : 0x06400128
Address@com_uart1 : 0x06400168
Address@app_uart0 : 0x40080328
Address@app_uart1 : 0x40080368
Address@mot_uart0 : 0x49200328
Address@mot_uart1 : 0x49200368
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
FORERUN
number of forerun cycles in system clocks or bauds


uarttrail
(NETX_UART%_RTS_TRAIL_CYC)
RTS trail cycles
R/W
0x00000000
Address@com_uart0 : 0x0640012c
Address@com_uart1 : 0x0640016c
Address@app_uart0 : 0x4008032c
Address@app_uart1 : 0x4008036c
Address@mot_uart0 : 0x4920032c
Address@mot_uart1 : 0x4920036c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
TRAIL
number of trail cycles in system clocks or bauds


uartdrvout
(NETX_UART%_OUT_DRV_EN)
Drive Output
R/W
0x00000000
Address@com_uart0 : 0x06400130
Address@com_uart1 : 0x06400170
Address@app_uart0 : 0x40080330
Address@app_uart1 : 0x40080370
Address@mot_uart0 : 0x49200330
Address@mot_uart1 : 0x49200370
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 -
cts_in_ro
Input state of CTSn in PIO mode (does not depend on uartcr_2.pio_mode)
4 -
rx_in_ro
Input state of RX in PIO mode (does not depend on uartcr_2.pio_mode)
3 "0"
rts_out
Output state of RTSn in PIO mode (when uartcr_2.pio_mode and DRVRTS is set)
2 "0"
tx_out
Output state of TX in PIO mode (when uartcr_2.pio_mode and DRVTX is set)
1 "0"
DRVRTS
enable driver for RTS (does not depend on uartcr_2.pio_mode)
0 "0"
DRVTX
enable driver for TX (does not depend on uartcr_2.pio_mode)


uartcr_2
(NETX_UART%_BAUD_MODE_CTRL)
Control Register 2
R/W
0x00000000
Address@com_uart0 : 0x06400134
Address@com_uart1 : 0x06400174
Address@app_uart0 : 0x40080334
Address@app_uart1 : 0x40080374
Address@mot_uart0 : 0x49200334
Address@mot_uart1 : 0x49200374
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
pio_mode
PIO mode for test purpose.
When PIO mode is enabled (this bit is set) the IOs can be controlled directly by the uartdrvout register.
3 - 2 0
-
 reserved
1 "0"
oversampling_8x
Oversampling mode:
0: Use default 16x oversampling.
1: Use reduced accuracy 8x oversampling. This can be used to increase the max. baudrate. When selected, the configured baudrate will be doubled. Note that the bit reception is more error-prone in noisy environments.
0 "0"
Baud_Rate_Mode
If this bit is set the baud rate is generated more exactly by the following formula:
value = ( (Baud Rate * 16) / System Frequency ) * 2^16  .
You have to write this 16-bit value in register uartlcr_l and uartlcr_m.


uartrxiflsel
(NETX_UART%_RX_FIFO_IRQ_LVL)
RX FIFO trigger level and RX-DMA enable
R/W
0x00000008
Address@com_uart0 : 0x06400138
Address@com_uart1 : 0x06400178
Address@app_uart0 : 0x40080338
Address@app_uart1 : 0x40080378
Address@mot_uart0 : 0x49200338
Address@mot_uart1 : 0x49200378
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
RXDMA
  Enable DMA-requests for RX-fifo-data.
  A request will be generated if RX-FIFO is not empty and uartcr.uartEN (module enable) is set.
  Burst request to DMA-Ctrl will be done if the RX-FIFO contains at least 4 words (set DMA-burst-size to 4)
  If this bit is reset or the module is disabled, DMA-request will also be reset.
  single transfer request: RX-FIFO contains 1 byte or more, burst request: 4 bytes or more
  note: set adr_dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA module
4 - 0 "01000"
RXIFLSEL
  Choose a number between 1 and 16. It defines the IRQ trigger level of the receive fifo.
  The IRQ (UARTRXINTR) will be set if the number of received bytes in the receive fifo are greater than or equal RXIFLSEL.


uarttxiflsel
(NETX_UART%_TX_FIFO_IRQ_LVL)
TX FIFO trigger level and TX-DMA enable
R/W
0x00000008
Address@com_uart0 : 0x0640013c
Address@com_uart1 : 0x0640017c
Address@app_uart0 : 0x4008033c
Address@app_uart1 : 0x4008037c
Address@mot_uart0 : 0x4920033c
Address@mot_uart1 : 0x4920037c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
TXDMA
  Enable DMA-requests for TX-fifo-data.
  A request will be generated if TX-FIFO is not full and uartcr.uartEN (module enable) is set.
  Burst request to DMA-Ctrl will be done if at least 4 words are writable to the TX-FIFO (set DMA-burst-size to 4)
  If this bit is reset or the module is disabled, DMA-request will also be reset.
  note: set adr_dmac_chctrl.DBSize = 1 (i.e. burst size: 4) in the DMA module
4 - 0 "01000"
TXIFLSEL
  Choose a number between 1 and 16. It defines the IRQ trigger level of the transmit fifo.
  The IRQ (UARTTXINTR) will be set if the number of transmitted bytes in the transmit fifo are less than TXIFLSEL.



Base Address Area: com_gpio

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gpio_cfg0
1 4 R/W gpio_cfg1
2 8 R/W gpio_cfg2
3 c R/W gpio_cfg3
4 10 R/W gpio_tc0
5 14 R/W gpio_tc1
6 18 R/W gpio_tc2
7 1c R/W gpio_tc3
8 20 R/W gpio_counter0_ctrl
9 24 R/W gpio_counter1_ctrl
a 28 R/W gpio_counter2_ctrl
b 2c R/W gpio_counter3_ctrl
c 30 R/W gpio_counter0_max
d 34 R/W gpio_counter1_max
e 38 R/W gpio_counter2_max
f 3c R/W gpio_counter3_max
10 40 R/W gpio_counter0_cnt
11 44 R/W gpio_counter1_cnt
12 48 R/W gpio_counter2_cnt
13 4c R/W gpio_counter3_cnt
14 50 R/W gpio_line
15 54 R gpio_in
16 58 R/W gpio_irq_raw
17 5c R gpio_irq_masked
18 60 R/W gpio_irq_mask_set
19 64 R/W gpio_irq_mask_rst
1a 68 R/W gpio_cnt_irq_raw
1b 6c R gpio_cnt_irq_masked
1c 70 R/W gpio_cnt_irq_mask_set
1d 74 R/W gpio_cnt_irq_mask_rst
1e-1f 78-7c -  reserved

gpio_cfg0
GPIO pin 0 config register:
R/W
0x00000000
Address : 0x06400180
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
blink_once
Run blink sequence only once (blink mode only)
12 - 8 "00000"
blink_len
Length of blink sequence minus 1 (blink mode only)
 00000: use bit 0 of gpio_tc
 00001: use bits 0..1 of gpio_tc
 00010: use bits 0..2 of gpio_tc
...
 11111: use bits 0..31 of gpio_tc
7 - 5 "000"
count_ref
counter reference
 000: counter 0
 001: counter 1
 010: counter 2
 011: counter 3
 111: sys_time (global system time)
4 "0"
inv
1: invert input/output value
0: do not invert input/output
3 - 0 "0000"
mode
defines the gp input or output mode - depends on io_cfg
Input modes:
 0000: read mode
 0001: capture continued at rising edge (allows gpio_irq on each capture)
 0010: capture once at rising edge (reset gpio_irq to capture again)
 0011: capture once at high level (reset gpio_irq to capture again)
Output modes:
 0100: set to 0
 0101: set to 1
 0110: set to gpio_line[0]
 0111: pwm mode, direct threshold update (might cause hazards on output)
 1000: blink mode
Multi pin modes:
 1111: pwm2-mode with threshold update at counter=0 from gpio_tc[n+1] register (hazard-free)


gpio_cfg1
GPIO pin 1 config register:
R/W
0x00000000
Address : 0x06400184
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
blink_once
analog to gpio_cfg0
12 - 8 "00000"
blink_len
analog to gpio_cfg0
7 - 5 "000"
count_ref
analog to gpio_cfg0
4 "0"
inv
analog to gpio_cfg0
3 - 0 "0000"
mode
analog to gpio_cfg0


gpio_cfg2
GPIO pin 2 config register:
R/W
0x00000000
Address : 0x06400188
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
blink_once
analog to gpio_cfg0
12 - 8 "00000"
blink_len
analog to gpio_cfg0
7 - 5 "000"
count_ref
analog to gpio_cfg0
4 "0"
inv
analog to gpio_cfg0
3 - 0 "0000"
mode
analog to gpio_cfg0


gpio_cfg3
GPIO pin 3 config register:
R/W
0x00000000
Address : 0x0640018c
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
blink_once
analog to gpio_cfg0
12 - 8 "00000"
blink_len
analog to gpio_cfg0
7 - 5 "000"
count_ref
analog to gpio_cfg0
4 "0"
inv
analog to gpio_cfg0
3 - 0 "0000"
mode
analog to gpio_cfg0


gpio_tc0
GPIO pin 0 threshold or capture register:
R/W
0x00000000
Address : 0x06400190
Bits Reset value Name Description
31 - 0 0x0
val
 Threshold/Capture register:
 PWM mode (threshold):



The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0).
Therefore it is interpreted differently in symmetrical and asymmetrical counter mode:
Asymmetrical mode (sawtooth): pwm = (counter >= gpio_tc)
Symmetrical mode (triangle) : Counter is compared with gpio_tc[31:1], gpio_tc[0] extends the inactive phase
by 1 clock cycle only while counting up. This allows running a 10 ns resolution even in symmetrical mode.

 Capture mode (capture register)
  In the capture mode, this register holds the captured counter value.

 Blink mode (blink sequence)
  In the blink mode, this register holds the blinking sequence starting from bit 0.


gpio_tc1
GPIO pin 1 threshold or capture register:
R/W
0x00000000
Address : 0x06400194
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_tc0


gpio_tc2
GPIO pin 2 threshold or capture register:
R/W
0x00000000
Address : 0x06400198
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_tc0


gpio_tc3
GPIO pin 3 threshold or capture register:
R/W
0x00000000
Address : 0x0640019c
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_tc0


gpio_counter0_ctrl
GPIO counter0 control register:
R/W
0x00000000
Address : 0x064001a0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 - 7 "00"
gpio_ref
gpio reference (0 - 3)
6 - 5 "00"
event_act
Define action of selected external event (dependent on sel_event, gpio_ref)
00: count every clock cycle, ignore external events
01: count only external events (edge or level according to bit sel_event)
10: enable watchdog mode of counter (external event will be reset without IRQ, overflow generates IRQ).
11: enable automatic run mode (external event sets run bit, used for DC-DC PWM in combination with bit once=1)
4 "0"
once
1: count once (reset run bit after 1 period)
0: count continuously
3 "0"
sel_event
select external event
0: high level, invert gpio in register gpio_cfg to select low level
1: pos. edge, invert gpio in register gpio_cfg to select neg. edge
2 "0"
irq_en
1: enable interrupt request on sel_event
0: disable interrupt request
1 "0"
sym_nasym
1: symmetric mode (triangle)
0: asymmetric mode (sawtooth)
0 "0"
run
1: start counter, counter is running
0: stop counter


gpio_counter1_ctrl
GPIO counter1 control register:
R/W
0x00000000
Address : 0x064001a4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 - 7 "00"
gpio_ref
analog to gpio_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_counter0_ctrl
4 "0"
once
analog to gpio_counter0_ctrl
3 "0"
sel_event
analog to gpio_counter0_ctrl
2 "0"
irq_en
analog to gpio_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_counter0_ctrl
0 "0"
run
analog to gpio_counter0_ctrl


gpio_counter2_ctrl
GPIO counter2 control register:
R/W
0x00000000
Address : 0x064001a8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 - 7 "00"
gpio_ref
analog to gpio_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_counter0_ctrl
4 "0"
once
analog to gpio_counter0_ctrl
3 "0"
sel_event
analog to gpio_counter0_ctrl
2 "0"
irq_en
analog to gpio_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_counter0_ctrl
0 "0"
run
analog to gpio_counter0_ctrl


gpio_counter3_ctrl
GPIO counter3 control register:
R/W
0x00000000
Address : 0x064001ac
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 - 7 "00"
gpio_ref
analog to gpio_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_counter0_ctrl
4 "0"
once
analog to gpio_counter0_ctrl
3 "0"
sel_event
analog to gpio_counter0_ctrl
2 "0"
irq_en
analog to gpio_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_counter0_ctrl
0 "0"
run
analog to gpio_counter0_ctrl


gpio_counter0_max
GPIO counter0 max value:
R/W
0x00000000
Address : 0x064001b0
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_counter1_max
GPIO counter1 max value:
R/W
0x00000000
Address : 0x064001b4
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_counter2_max
GPIO counter2 max value:
R/W
0x00000000
Address : 0x064001b8
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_counter3_max
GPIO counter3 max value:
R/W
0x00000000
Address : 0x064001bc
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_counter0_cnt
GPIO counter0 current value:
R/W
0x00000000
Address : 0x064001c0
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_counter1_cnt
GPIO counter1 current value:
R/W
0x00000000
Address : 0x064001c4
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_counter2_cnt
GPIO counter2 current value:
R/W
0x00000000
Address : 0x064001c8
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_counter3_cnt
GPIO counter3 current value:
R/W
0x00000000
Address : 0x064001cc
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_line
GPIO line register
R/W
0x00000000
Address : 0x064001d0
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0000"
val
gpio output values


gpio_in
GPIO latched inputs register:
R
Address : 0x064001d4
Bits Name Description
31 - 4 -
 reserved
3 - 0 val
gpio input values


gpio_irq_raw
GPIO raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x064001d8
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
gpio3
Interrupt bit for GPIO3
2 "0"
gpio2
Interrupt bit for GPIO2
1 "0"
gpio1
Interrupt bit for GPIO1
0 "0"
gpio0
Interrupt bit for GPIO0


gpio_irq_masked
GPIO masked IRQ register:
R
Address : 0x064001dc
Bits Name Description
31 - 4 -
 reserved
3 gpio3
Interrupt bit for GPIO3
2 gpio2
Interrupt bit for GPIO2
1 gpio1
Interrupt bit for GPIO1
0 gpio0
Interrupt bit for GPIO0


gpio_irq_mask_set
GPIO interrupt mask set:
Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to gpio_irq_raw.
R/W
0x00000000
Address : 0x064001e0
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
gpio3
Interrupt bit for GPIO3
2 "0"
gpio2
Interrupt bit for GPIO2
1 "0"
gpio1
Interrupt bit for GPIO1
0 "0"
gpio0
Interrupt bit for GPIO0


gpio_irq_mask_rst
GPIO interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
0x00000000
Address : 0x064001e4
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
gpio3
Interrupt bit for GPIO3
2 "0"
gpio2
Interrupt bit for GPIO2
1 "0"
gpio1
Interrupt bit for GPIO1
0 "0"
gpio0
Interrupt bit for GPIO0


gpio_cnt_irq_raw
Counter raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x064001e8
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0


gpio_cnt_irq_masked
Counter masked IRQ register:
Read access shows the status of the masked IRQs (cnt_irq_raw AND cnt_irq_mask).
R
Address : 0x064001ec
Bits Name Description
31 - 4 -
 reserved
3 cnt3
Interrupt bit for counter3
2 cnt2
Interrupt bit for counter2
1 cnt1
Interrupt bit for counter1
0 cnt0
Interrupt bit for counter0


gpio_cnt_irq_mask_set
Counter interrupt mask set:
Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to cnt_irq_raw.
R/W
0x00000000
Address : 0x064001f0
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0


gpio_cnt_irq_mask_rst
Counter interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
0x00000000
Address : 0x064001f4
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0



Base Address Area: com_pio, app_pio, mot_pio

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R pio_in
1 4 R/W pio_out
2 8 R/W pio_oe
3 c R/W pio_in_inv
4 10 R/W pio_edge_event
5 14 R/W pio_irq_raw
6 18 R/W pio_irq_masked
7 1c R/W pio_irq_mask_set
8 20 R/W pio_irq_mask_rst
9-3f 24-fc -  reserved

pio_in
PIO input line status register.
Each PIO input status can also be read from dedicated PIOx input state register.
R
Address@com_pio : 0x06400200
Address@app_pio : 0x40080600
Address@mot_pio : 0x49200600
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
PIO input states (LSB: PIO0).


pio_out
PIO output drive level line register.
Each PIOs output drive level can also be programmed by dedicated PIOx output drive level register.
Note: For netx22xx sometimes the upper PIO's [15:7] are multiplexed on the input-only LVGS IOs. Hence they
      can only be used as inputs there. Howver, the Output function can be use on the IOEXTENDER.
      Take a close look to the pinning table: If the multiplex function you want to use is named 'pi'
      instead of 'pio' you are on an input-only pin and cannot use the PIO as output.
R/W
0x00000000
Address@com_pio : 0x06400204
Address@app_pio : 0x40080604
Address@mot_pio : 0x49200604
Bits Reset value Name Description
31 - 16 0x0
val_wm
Write mask of val.
15 - 0 0x0
val
PIO output drive levels (LSB: PIO0).


pio_oe
PIO output enable line register.
Each PIOs output enable can also be programmed by dedicated PIOx output enable register.
Note: For netx22xx sometimes the upper PIO's [15:7] are multiplexed on the input-only LVGS IOs. Hence they
      can only be used as inputs there. Howver, the Output function can be use on the IOEXTENDER.
      Take a close look to the pinning table: If the multiplex function you want to use is named 'pi'
      instead of 'pio' you are on an input-only pin and cannot use the PIO as output.
R/W
0x00000000
Address@com_pio : 0x06400208
Address@app_pio : 0x40080608
Address@mot_pio : 0x49200608
Bits Reset value Name Description
31 - 16 0x0
val_wm
Write mask of val.
15 - 0 0x0
val
PIO output enables (LSB: PIO0).


pio_in_inv
Invert input of PIO.
R/W
0x00000000
Address@com_pio : 0x0640020c
Address@app_pio : 0x4008060c
Address@mot_pio : 0x4920060c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
Invert PIO


pio_edge_event
generate IRQ at edge of PIO, otherwise level.
R/W
0x00000000
Address@com_pio : 0x06400210
Address@app_pio : 0x40080610
Address@mot_pio : 0x49200610
Bits Reset value Name Description
31 - 16 0x0
val_wm
Write mask of val.
15 - 0 0x0
val
Edge detect
0: generate IRQ if (inverted) PIO is high level
1: generate IRQ at rising edge of (inverted) PIO


pio_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@com_pio : 0x06400214
Address@app_pio : 0x40080614
Address@mot_pio : 0x49200614
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
pio15
event or active level at PIO15 input
14 "0"
pio14
event or active level at PIO14 input
13 "0"
pio13
event or active level at PIO13 input
12 "0"
pio12
event or active level at PIO12 input
11 "0"
pio11
event or active level at PIO11 input
10 "0"
pio10
event or active level at PIO10 input
9 "0"
pio9
event or active level at PIO9 input
8 "0"
pio8
event or active level at PIO8 input
7 "0"
pio7
event or active level at PIO7 input
6 "0"
pio6
event or active level at PIO6 input
5 "0"
pio5
event or active level at PIO5 input
4 "0"
pio4
event or active level at PIO4 input
3 "0"
pio3
event or active level at PIO3 input
2 "0"
pio2
event or active level at PIO2 input
1 "0"
pio1
event or active level at PIO1 input
0 "0"
pio0
event or active level at PIO0 input


pio_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_pio_irq_raw).
R/W
0x00000000
Address@com_pio : 0x06400218
Address@app_pio : 0x40080618
Address@mot_pio : 0x49200618
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
pio15
event or active level at PIO15 input
14 "0"
pio14
event or active level at PIO14 input
13 "0"
pio13
event or active level at PIO13 input
12 "0"
pio12
event or active level at PIO12 input
11 "0"
pio11
event or active level at PIO11 input
10 "0"
pio10
event or active level at PIO10 input
9 "0"
pio9
event or active level at PIO9 input
8 "0"
pio8
event or active level at PIO8 input
7 "0"
pio7
event or active level at PIO7 input
6 "0"
pio6
event or active level at PIO6 input
5 "0"
pio5
event or active level at PIO5 input
4 "0"
pio4
event or active level at PIO4 input
3 "0"
pio3
event or active level at PIO3 input
2 "0"
pio2
event or active level at PIO2 input
1 "0"
pio1
event or active level at PIO1 input
0 "0"
pio0
event or active level at PIO0 input


pio_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_pio_irq_raw
R/W
0x00000000
Address@com_pio : 0x0640021c
Address@app_pio : 0x4008061c
Address@mot_pio : 0x4920061c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
pio15
event or active level at PIO15 input
14 "0"
pio14
event or active level at PIO14 input
13 "0"
pio13
event or active level at PIO13 input
12 "0"
pio12
event or active level at PIO12 input
11 "0"
pio11
event or active level at PIO11 input
10 "0"
pio10
event or active level at PIO10 input
9 "0"
pio9
event or active level at PIO9 input
8 "0"
pio8
event or active level at PIO8 input
7 "0"
pio7
event or active level at PIO7 input
6 "0"
pio6
event or active level at PIO6 input
5 "0"
pio5
event or active level at PIO5 input
4 "0"
pio4
event or active level at PIO4 input
3 "0"
pio3
event or active level at PIO3 input
2 "0"
pio2
event or active level at PIO2 input
1 "0"
pio1
event or active level at PIO1 input
0 "0"
pio0
event or active level at PIO0 input


pio_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : irq-pio0
  1  : irq-pio1
  2  : irq-pio2
  3  : irq-pio3
  4  : irq-pio4
  5  : irq-pio5
  6  : irq-pio6
  7  : irq-pio7
  8  : irq-pio8
  9  : irq-pio9
  10 : irq-pio10
  11 : irq-pio11
  12 : irq-pio12
  13 : irq-pio13
  14 : irq-pio14
  15 : irq-pio15
  16 : no active IRQ
R/W
0x00000000
Address@com_pio : 0x06400220
Address@app_pio : 0x40080620
Address@mot_pio : 0x49200620
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
pio15
event or active level at PIO15 input
14 "0"
pio14
event or active level at PIO14 input
13 "0"
pio13
event or active level at PIO13 input
12 "0"
pio12
event or active level at PIO12 input
11 "0"
pio11
event or active level at PIO11 input
10 "0"
pio10
event or active level at PIO10 input
9 "0"
pio9
event or active level at PIO9 input
8 "0"
pio8
event or active level at PIO8 input
7 "0"
pio7
event or active level at PIO7 input
6 "0"
pio6
event or active level at PIO6 input
5 "0"
pio5
event or active level at PIO5 input
4 "0"
pio4
event or active level at PIO4 input
3 "0"
pio3
event or active level at PIO3 input
2 "0"
pio2
event or active level at PIO2 input
1 "0"
pio1
event or active level at PIO1 input
0 "0"
pio0
event or active level at PIO0 input



Base Address Area: com_blink, app_blink, mot_blink

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W blink_enable
1 4 R/W blink_config0
2 8 R/W blink_seq0
3 c R/W blink_config1
4 10 R/W blink_seq1
5 14 R/W blink_config2
6 18 R/W blink_seq2
7 1c R/W blink_config3
8 20 R/W blink_seq3
9 24 R/W blink_wdg_cfg
a 28 R/W blink_wdg_trigger
b-f 2c-3c -  reserved

blink_enable
Blinking output enable register:
This allows synchronous start of multiple blinking outputs.
Note: Blink unit works on a 10ms system tick, i.e. all blink sequences will start on this time base.
This register is a write mask register. Changes will only take effect, if the corresponding write mask bits (*_wm) are set.
R/W
0x00000000
Address@com_blink : 0x06400300
Address@app_blink : 0x40080700
Address@mot_blink : 0x49200700
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
en3_wm
Write mask of en3
18 "0"
en2_wm
Write mask of en2
17 "0"
en1_wm
Write mask of en1
16 "0"
en0_wm
Write mask of en0
15 - 4 0
-
 reserved
3 "0"
en3
Enable of blinking output 3
2 "0"
en2
Enable of blinking output 2
1 "0"
en1
Enable of blinking output 1
0 "0"
en0
Enable of blinking output 0
If disabled, counter is reset


blink_config0
Blinking output config register
R/W
0x00000163
Address@com_blink : 0x06400304
Address@app_blink : 0x40080704
Address@mot_blink : 0x49200704
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00001"
blink_len
Length of blink sequence
 00000: use bit 0 of blink_seq
 00001: use bits 0..1 of blink_seq
 00010: use bits 0..2 of blink_seq
...
 11111: use bits 0..31 of blink_seq
7 - 0 "01100011"
period
Blinking period in steps of 10ms
 00: 10ms
 ff: 2560ms


blink_seq0
Blinking output sequence register
R/W
0x00000001
Address@com_blink : 0x06400308
Address@app_blink : 0x40080708
Address@mot_blink : 0x49200708
Bits Reset value Name Description
31 - 0 0x1
val
Bits of blink sequence


blink_config1
Blinking output config register
R/W
0x00000163
Address@com_blink : 0x0640030c
Address@app_blink : 0x4008070c
Address@mot_blink : 0x4920070c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00001"
blink_len
Length of blink sequence
 00000: use bit 0 of blink_seq
 00001: use bits 0..1 of blink_seq
 00010: use bits 0..2 of blink_seq
...
 11111: use bits 0..31 of blink_seq
7 - 0 "01100011"
period
Blinking period in steps of 10ms
 00: 10ms
 ff: 2560ms


blink_seq1
Blinking output sequence register
R/W
0x00000001
Address@com_blink : 0x06400310
Address@app_blink : 0x40080710
Address@mot_blink : 0x49200710
Bits Reset value Name Description
31 - 0 0x1
val
Bits of blink sequence


blink_config2
Blinking output config register
R/W
0x00000163
Address@com_blink : 0x06400314
Address@app_blink : 0x40080714
Address@mot_blink : 0x49200714
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00001"
blink_len
Length of blink sequence
 00000: use bit 0 of blink_seq
 00001: use bits 0..1 of blink_seq
 00010: use bits 0..2 of blink_seq
...
 11111: use bits 0..31 of blink_seq
7 - 0 "01100011"
period
Blinking period in steps of 10ms
 00: 10ms
 ff: 2560ms


blink_seq2
Blinking output sequence register
R/W
0x00000001
Address@com_blink : 0x06400318
Address@app_blink : 0x40080718
Address@mot_blink : 0x49200718
Bits Reset value Name Description
31 - 0 0x1
val
Bits of blink sequence


blink_config3
Blinking output config register
R/W
0x00000163
Address@com_blink : 0x0640031c
Address@app_blink : 0x4008071c
Address@mot_blink : 0x4920071c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00001"
blink_len
Length of blink sequence
 00000: use bit 0 of blink_seq
 00001: use bits 0..1 of blink_seq
 00010: use bits 0..2 of blink_seq
...
 11111: use bits 0..31 of blink_seq
7 - 0 "01100011"
period
Blinking period in steps of 10ms
 00: 10ms
 ff: 2560ms


blink_seq3
Blinking output sequence register
R/W
0x00000001
Address@com_blink : 0x06400320
Address@app_blink : 0x40080720
Address@mot_blink : 0x49200720
Bits Reset value Name Description
31 - 0 0x1
val
Bits of blink sequence


blink_wdg_cfg
Blink watchdog config register
Writing this registers with a wdg_timeout that is not 0, starts the watchdog.
R/W
0x00000000
Address@com_blink : 0x06400324
Address@app_blink : 0x40080724
Address@mot_blink : 0x49200724
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 -
wdg_timeout_status_ro
timeout status
 0: watchdog not expired
 1: watchdog expired
27 - 25 0
-
 reserved
24 - 16 -
wdg_cnt_ro
current watchdog counter value in steps of 10ms
15 - 12 0
-
 reserved
11 "0"
fallback_led3
output value of LED3 in case of timeout
10 "0"
fallback_led2
output value of LED2 in case of timeout
9 "0"
fallback_led1
output value of LED1 in case of timeout
8 "0"
fallback_led0
output value of LED0 in case of timeout
7 - 6 0
-
 reserved
5 - 0 "000000"
wdg_timeout
Watchdog timeout value:
Time in steps of 80ms, within watchdog must be triggered before
timeout (all blink outputs turn to fallback value).
0: watchdog disabled
1: 70...80ms
2: 150...160ms
...
63: 5.03...5.04s
Note: The internal watchdog counter (wdg_cnt) works on a
      global 10ms tick. This leads to an unpredicted range
      of the real timeout time.


blink_wdg_trigger
Blink watchdog trigger register
R/W
0x00008c8c
Address@com_blink : 0x06400328
Address@app_blink : 0x40080728
Address@mot_blink : 0x49200728
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "10001100"
next_trigger
Value to write for next trigger access
7 - 0 "10001100"
trigger
Trigger value
Write here to trigger watchdog
Note: Writing to this register is also used
      to return watchdog from timeout state



Base Address Area: com_blink_mixled, com_gxc_mixled0, com_gxc_mixled1, app_blink_mixled, mot_blink_mixled

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mixled_cfg
1 4 R/W mixled_brightness_ch0_a
2 8 R/W mixled_brightness_ch0_b
3 c R/W mixled_brightness_ch0_a_b
4 10 R/W mixled_brightness_ch1_a
5 14 R/W mixled_brightness_ch1_b
6 18 R/W mixled_brightness_ch1_a_b
7 1c -  reserved

mixled_cfg
Global configuration register.
This register collects global configuration options of the MIXLED module.
Functional summary:
The MIXLED module does a PWM to mix pairs of external LEDs and control their brightness.
The PWM is fixed to 16 time slots, so the brightness is defined by a value between 0 an 16.
For use of multicolor LEDs, each pair of LED signals (here called channel) knows different
brightness values for the case that only one LED is active and the other case with both
LEDs mixed.
For use with common anode or bidirectional LEDs, the LEDs of a channel use an
inverse on-/off-pattern for the 16 timeslots. This ensures in a very simple way,
that only one LED is active at the same time, as long as the total brightness
of both LEDs is not bigger 16.
If LEDs are used, that allow turning on both at the same time, then there is no
restriction in the brightness_chX_a_b values.
The PWM frequency is not configurable inside this module. It is defined by the update frequency of
the IO-Extender module, driving exernal LEDs via external shift registers.
Note: The update frequency of IO-Extender is typically ~700Hz. This is due to the requirement, that
      pins to external shift register are also used to drive RDY/RUN LEDs, which must not glim when off.
      Considering this requirement, signals from blink unit or GXC to MIXLED should toggle
      much slower than 700Hz/16 (<<40Hz).
R/W
0x00000000
Address@com_blink_mixled : 0x06400340
Address@com_gxc_mixled0 : 0x06400360
Address@com_gxc_mixled1 : 0x06400380
Address@app_blink_mixled : 0x40080740
Address@mot_blink_mixled : 0x49200740
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
simple_pwm_pattern
The MIXLED module knows 2 different on-off patterns:
1: Simple pattern - Only turns LEDs on/off once per PWM period (=16 updates at IOE).
   It looks like this (turn time slot on, if brightness > value):
   LED A: 0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15
   LED B: 15,14,13,12,11,10,9,8,7,6,5,4,3,2,1,0
0: Reduce flickering mode - increase the switching rate to reduce visible flickering effects:
   It looks like this (turn time slot on, if brightness > value):
   LED A: 0,8,4,12,2,10,6,14,1,9,5,13,3,11,7,15
   LED B: 15,7,11,3,13,5,9,1,14,6,10,2,12,4,8,0
1 "0"
enable_1
Writing a '1' to this bit will enable brightness control for channel 1 (LEDs 2 and 3)
When disabled, inputs A1in and B1in from system will be directy.connected to A1out and B1out.
0 "0"
enable_0
Writing a '1' to this bit will enable brightness control for channel 0 (LEDs 0 and 1)
When disabled, inputs A0in and B0in from system will be directy.connected to A0out and B0out.


mixled_brightness_ch0_a
Control channel 0 brightness if only LED A is active.(Ain=1, Bin=0)
R/W
0x00000010
Address@com_blink_mixled : 0x06400344
Address@com_gxc_mixled0 : 0x06400364
Address@com_gxc_mixled1 : 0x06400384
Address@app_blink_mixled : 0x40080744
Address@mot_blink_mixled : 0x49200744
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "10000"
val
Number of time slots per period, LED A is active.
The value must be in [0:16].


mixled_brightness_ch0_b
Control channel 0 brightness if only LED B is active (Ain=0, Bin=1).
R/W
0x00000010
Address@com_blink_mixled : 0x06400348
Address@com_gxc_mixled0 : 0x06400368
Address@com_gxc_mixled1 : 0x06400388
Address@app_blink_mixled : 0x40080748
Address@mot_blink_mixled : 0x49200748
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "10000"
val
Number of time slots per period, LED B is active.
The value must be in [0:16].


mixled_brightness_ch0_a_b
Control channel 0 brightness and color if LED A and LED B are mixed (Ain=1, Bin=1).
For common anode or bidirectional LEDs the total number of time slots (led_a + led_b) must not exceed 16!
R/W
0x00000808
Address@com_blink_mixled : 0x0640034c
Address@com_gxc_mixled0 : 0x0640036c
Address@com_gxc_mixled1 : 0x0640038c
Address@app_blink_mixled : 0x4008074c
Address@mot_blink_mixled : 0x4920074c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "01000"
led_b
number of time slots, LED B is active.
The value should be in [0:(16-led_a)].
7 - 5 0
-
 reserved
4 - 0 "01000"
led_a
number of time slots, LED A is active.
The value must be in [0:16].


mixled_brightness_ch1_a
Control channel 0 brightness if only LED A is active.(Ain=1, Bin=0)
R/W
0x00000010
Address@com_blink_mixled : 0x06400350
Address@com_gxc_mixled0 : 0x06400370
Address@com_gxc_mixled1 : 0x06400390
Address@app_blink_mixled : 0x40080750
Address@mot_blink_mixled : 0x49200750
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "10000"
val
Number of time slots per period, LED A is active.
The value must be in [0:16].


mixled_brightness_ch1_b
Control channel 0 brightness if only LED B is active (Ain=0, Bin=1).
R/W
0x00000010
Address@com_blink_mixled : 0x06400354
Address@com_gxc_mixled0 : 0x06400374
Address@com_gxc_mixled1 : 0x06400394
Address@app_blink_mixled : 0x40080754
Address@mot_blink_mixled : 0x49200754
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "10000"
val
Number of time slots per period, LED B is active.
The value must be in [0:16].


mixled_brightness_ch1_a_b
Control channel 0 brightness and color if LED A and LED B are mixed (Ain=1, Bin=1).
For common anode or bidirectional LEDs the total number of time slots (led_a + led_b) must not exceed 16!
R/W
0x00000808
Address@com_blink_mixled : 0x06400358
Address@com_gxc_mixled0 : 0x06400378
Address@com_gxc_mixled1 : 0x06400398
Address@app_blink_mixled : 0x40080758
Address@mot_blink_mixled : 0x49200758
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "01000"
led_b
number of time slots, LED B is active.
The value should be in [0:(16-led_a)].
7 - 5 0
-
 reserved
4 - 0 "01000"
led_a
number of time slots, LED A is active.
The value must be in [0:16].



Base Address Area: com_hsgmii0, com_hsgmii1, app_hsgmii

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mr_control
1 4 R mr_status
2-3 8-c -  reserved
4 10 R/W mr_an_adv
5 14 R mr_an_lpa
6 18 R mr_an_exp
7-e 1c-38 -  reserved
f 3c R mr_ext_status
10 40 R/W h_cmd
11 44 R h_evt
12 48 R h_status
13 4c R/W h_an_config
14 50 R/W h_ibs_config
15 54 R/W h_adapt_config
16 58 R/W h_pcs_config
17 5c R/W h_pma_special
18 60 R/W h_bypass
19 64 R/W h_cdr_config
1a 68 R/W h_cdr_config2
1b 6c R h_cdr_status
1c 70 R/W h_clkgen_config
1d 74 R/W h_afe_cfg
1e 78 R/W h_cal
1f 7c R/W h_power
20 80 R/W h_sd100_cfg
21-3f 84-fc -  reserved

mr_control
PCS layer Control Register  (management register 0)
derived from ieee 802.3 section 2 table 22-7
R/W
0x00001800
Address@com_hsgmii0 : 0x06400400
Address@com_hsgmii1 : 0x06400500
Address@app_hsgmii : 0x40092000
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
reset
writing 1 causes reset of PCS FSMs. Config register contents keep unchanged.
Behaves linke strobing a 0 to h_power.pcs_enable
the hardware will automatically reset this bit
14 "0"
loopback
1: enable loopback
   The input of the deserializer is muxed to the output of the serializer
   Note: This does not disable the transmitter. The transmitter can be disabled separately by tx_on.
13 0
-
 reserved
12 "1"
autoneg_enable
1 enable auto-negotiation
11 "1"
power_down
0 : all powered down
in contrast to ieee specification, this is 1 at reset because this phy often needs to be configured before powered up
writable, but it can also be changed by hardware
writing 1 sets afe_cfg.d_comp_on and afe_cfg.d_tx_on to 0
writing 0 sets afe_cfg.d_comp_on and afe_cfg.d_tx_on to 1
reads afe_cfg.d_comp_on && afe_cfg.d_tx_on
See description of these signals for details.
10 0
-
 reserved
9 "0"
restart_autoneg
writing 1 causes restart of auto negotiation
the hardware will automatically reset this bit
8 - 0 0
-
 reserved


mr_status
PCS layer Status Register (management register 1)
derived from ieee 802.3 section 2 table 22-8
R
Address@com_hsgmii0 : 0x06400404
Address@com_hsgmii1 : 0x06400504
Address@app_hsgmii : 0x40092004
Bits Name Description
31 - 16 -
 reserved
15 base100_t4
always 0 : PHY is not able to perform 100BASE-T4
14 base100_x_fd
always 1 : PHY is able to perform 100BASE-X full duplex (if configured properly)
13 base100_x_hd
always 1 : PHY is able to perform 100BASE-X half duplex (if configured properly)
12 base10_fd
always 0 : PHY is not able to perform 10 mb/s full duplex
11 base10_hd
always 0 : PHY is not able to perform 10 mb/s half duplex
10 base100_t2_fd
always 0 : PHY is not able to perform 100BASE-T2 full duplex
9 base100_t2_hd
always 0 : PHY is not able to perform 100BASE-T2 half duplex
8 extended_status
always 1 : Extended status information in management register 15
7 unidirectional_ability
always 1 : PHY able to transmit from media independent interface
regardless of whether the PHY has determined that a valid
link has been established
6 mf_preamble_suppression
always 0 PHY will not accept management frames with preamble suppressed.
(first byte will always be replaced by 0x55, shrinkage might occur)
5 auto_neg_complete
1: Auto-Negotiation process completed
0: Auto-Negotiation process not completed
4 remote_fault
always 0: not supported
3 link_status
1: link has been continuously up since last read
0: link down occured since last read
2 -
 reserved
1 jabber_detect
always 0: not supported
0 extended_capability
always 1: extended registers exist


mr_an_adv
PCS layer Auto-Negotiation advertisement (management register 4)
R/W
0x00004001
Address@com_hsgmii0 : 0x06400410
Address@com_hsgmii1 : 0x06400510
Address@app_hsgmii : 0x40092010
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x4001
mr_adv_ability
rx_config_reg
Bit 14 is used for AutoNeg ACK and is always ignored; should be 1
Bits 15,13:10 are overwritten by in-band-status signals if selected by an_adv_use_ibs.
The meaning of this register is defined by how to use this phy. Defaults to MAC usage.
SGMII MAC:
[14] : 1,
[0]  : 1
       others should be 0
SGMII PHY mode:
[15]: link_status, 1: link up.
[14]: 1
[13]: reserved, 0
[12]: Duplex Mode,  1: full, 0: half
[11:10]: speed, 11: reserved, 10: 1000MBit, 01: 100MBit, 00: 10MBit.
[9:1]:resered, 0
[0]: 1
1000BASEX mode:
[15] NP (Next Page). Not supported, 0
[14] : 1
[13:12] RF (Remote Fault). Not supported, 0
[11:9] reserved, 0
[8:7] PS (Pause Capabilities). Not supported, 0
[6] : HD (Half Duplex supported). Not supported, 0
[5] : FD (Full Duplex supported). Link is always full duplex, 1
[4:1] reserved, 0


mr_an_lpa
PCS layer Auto-Negotiation link partner ability (management register 5)
R
Address@com_hsgmii0 : 0x06400414
Address@com_hsgmii1 : 0x06400514
Address@app_hsgmii : 0x40092014
Bits Name Description
31 - 16 -
 reserved
15 - 0 mr_lp_adv_ability
received from link partner's "tx_config_reg" via /C/ ordered sets


mr_an_exp
PCS layer Auto-Negotiation extended status register (management register 6)
R
Address@com_hsgmii0 : 0x06400418
Address@com_hsgmii1 : 0x06400518
Address@app_hsgmii : 0x40092018
Bits Name Description
31 - 3 -
 reserved
2 np
Next page capability. Not supported, returns always 0
1 page
Page received. Event. Is also set when new rx_config_reg was received. Clears when read.
0 -
 reserved


mr_ext_status
PCS layer Extended status register (management register 15)
R
Address@com_hsgmii0 : 0x0640043c
Address@com_hsgmii1 : 0x0640053c
Address@app_hsgmii : 0x4009203c
Bits Name Description
31 - 16 -
 reserved
15 base1000_x_fd
always 1 : PHY is able to perform 100BASE-X full duplex
14 base1000_x_hd
always 1 : PHY is able to perform 100BASE-X half duplex (in non-SGMII configuration)
13 base1000_t_fd
always 0 : PHY is not able to perform 100BASE-T full duplex
12 base1000_t_hd
always 0 : PHY is not able to perform 100BASE-T half duplex
11 - 0 -
 reserved


h_cmd
general HSGMII commands. Writing 1 sends the command, reads always 0
R/W
0x00000000
Address@com_hsgmii0 : 0x06400440
Address@com_hsgmii1 : 0x06400540
Address@app_hsgmii : 0x40092040
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
tx_idle_insert_k
insert one additional k28.5 code in next idle ordered set
This is done by executing IDLE_DISPARITY_* state in pcs transmit code-group twice for one time. causes shift of even-odd pattern by 1.
warning: This causes LOSS OF SYNC and re-syncronization at remote side!
might be useful to create a deterministic preamble shrinkage/carrier extension behavior, especially when working with 10/100 SGMII
0 "0"
tx_realign
re-align TX serializer sampling point


h_evt
general HSGMII event messages. When an event occurs, the corresponding bit is set to 1. All bits are reset by reading.
R
Address@com_hsgmii0 : 0x06400444
Address@com_hsgmii1 : 0x06400544
Address@app_hsgmii : 0x40092044
Bits Name Description
31 - 8 -
 reserved
7 tx_epd3
EPD3 state of PCS transmit ordered_set was entered (carrier extension due to even/odd idle alignment has occured)
6 tx_shrink
Preamble shrinkage occured at TX
5 rx_adapt_sp_shift
In 10/100 Mode: sampling point shift detected (was not aligned to change of PCS data). This normally occurs at preamble shrinkage.
4 tx_realign
TX serializer sampling point re-alignment occured
3 com_det
Comma detect event occured
2 lp_adv_ability_received
copy of mr_an_exp.page with own latch
1 sync_status_fail
sync_status=FAIL occured
0 link_status_down
0: link has been continuously up since last read
1: link down occured since last read
Note that this is exactly the inverted meaning of mr_status.link_status.
Is useful to save bus accesses. It is seperately latched there.


h_status
general HSGMII status
R
Address@com_hsgmii0 : 0x06400448
Address@com_hsgmii1 : 0x06400548
Address@app_hsgmii : 0x40092048
Bits Name Description
31 - 4 -
 reserved
3 - 0 tx_alignment
reads current alignment of TX serializer sampling point


h_an_config
advanced autoneg configuration
R/W
0x00000640
Address@com_hsgmii0 : 0x0640044c
Address@com_hsgmii1 : 0x0640054c
Address@app_hsgmii : 0x4009204c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x640
an_link_timer_duration
AutoNeg link_timer_duration in 1us steps. Must be set to 1.6ms for SGMII and 10ms for BASEX.
Can be set to low value for debug.


h_ibs_config
in-band status muxing configuration
should be configured depending on MAC, PHY or BASEX usage. Defaults are intended for MAC usage.
R/W
0x00000010
Address@com_hsgmii0 : 0x06400450
Address@com_hsgmii1 : 0x06400550
Address@app_hsgmii : 0x40092050
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
tx_crs_mode
Determines how hgmii.crs is generated
Note: when using SGMII PHY mode, hgmii.crs and hgmii.col must be ignored
0: hgmii.crs = pcs_rx_dv
Use this setting for SGMII MAC mode
1: hgmii.crs = pcs_crs
Use this setting for 1000BASE-X mode
9 "0"
tx_col_mode
Determines how hgmii.col is generated
Note: when using SGMII PHY mode, hgmii.crs and hgmii.col must be ignored
0: hgmii.col = pcs_tx_en & pcs_rx_dv
Use this setting for SGMII MAC mode
1: hgmii.col = pcs_col
Use this setting for 1000BASE-X mode
8 "0"
an_restart_ctrl
1: AutoNeg is restarted when hgmii.ibs_* changes
   Use this setting for SGMII PHY mode
7 "0"
an_adv_use_ibs
control some autoneg adverstment registers by ibs signals
0: rx_status_reg = mr_an_adv_ability
No ibs control. Use this setting when not in SGMII PHY mode
1:


rx_status_reg[15]    = hgmii.ibs_link_status
rx_status_reg[12]    = hgmii.ibs_duplex
rx_status_reg[11:10] = hgmii.ibs_speed
rx_status_reg[others] = mr_an_adv_ability[others]
Use this setting for SGMII PHY mode
6 - 5 "00"
mdef_ibs_speed
see ibs_src
4 "1"
mdef_ibs_duplex
see ibs_src
3 "0"
mdef_ibs_link_status
see ibs_src
2 0
-
 reserved
1 - 0 "00"
ibs_src
source of in-band-status signals. The in-band-status signals are wrapped to hgmii.ibs_* .
Note: hgmii.ibs_speed also controls the rate adapter.
0 : if mr_an_complete then
      hgmii.ibs_link_status = mr_lp_adv_ability[15]
      hgmii.ibs_duplex      = mr_lp_adv_ability[12]
      hgmii.ibs_speed       = mr_lp_adv_ability[11:10]
    else
      hgmii.ibs_* = mdef_ibs_*
    end
    Use this setting for SGMII MAC mode
1 : hgmii.ibs_* = ext_ibs_*
Use this setting for SGMII PHY mode
2 : 100/1000BASE-X mode
if pcs_sel100 == 1 then
       hgmii.ibs_link_status = detected link status (see h_sd100_cfg)
       hgmii.ibs_duplex      = mdef_duplex
       hgmii.ibs_speed       = 1
    else
       hgmii.ibs_link_status = mr_link_status
       hgmii.ibs_duplex      = mdef_duplex
       hgmii.ibs_speed       = 2
    end
3 : hgmii.ibs_* = mdef_ibs_*
    Useful for debug purposes


h_adapt_config
HSGMII rate adapter configuration
R/W
0x00003101
Address@com_hsgmii0 : 0x06400454
Address@com_hsgmii1 : 0x06400554
Address@app_hsgmii : 0x40092054
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "1"
tx_adapt_enable
0: adapter is by-passed and state of it is reset
12 "1"
rx_adapt_enable
0: adapter is by-passed and state of it is reset
11 "0"
tx_adapt_nibble_flip
determines in which order mii nibbles are mapped to PCS layer octets at tx side.
Setting 0 is recommended. Debug use only.
0 :
as specified by IEEE 802.3 Section 2 Figure 22-13
octet[7:4] <= second nibble
octet[3:0] <= first nibble
1 :
reverse order
octet[7:4] <= first nibble
octet[3:0] <= second nibble
10 "0"
rx_adapt_nibble_flip
determines in which order mii nibbles are mapped to PCS layer octets at rx side.
Setting 0 is recommended. Debug use only.
0 :
as specified by IEEE 802.3 Section 2 Figure 22-13
octet[7:4] <= second nibble
octet[3:0] <= first nibble
1 :
reverse order
octet[7:4] <= first nibble
octet[3:0] <= second nibble
9 "0"
tx_adapt_nibble_preamble_repair
1: in 10/100 mode: enlarge preamble by 1 nibble when preamble+SFD has odd number of nibbles. If this happens, the frame will be delayed by 1 nibble.
   note: the delay might be inconvenient for real time applications
0: odd nibbled preamble+SFD is not supported / changes frame data unless *_adapt_nibble_status workarounds are used
8 "1"
rx_cesup_odd_nibble
1: Suppress carrier extention additionally for odd nibble
   (when hgmii.ibs_speed < 2 && rx_adapt_nibble_status == 1)
   hgmii.rx_er = hgmii.ibs_duplex ? (pcs_rx_dv & pcs_rx_er) : pcs_rx_er
7 - 6 "00"
rx_cesup_mii
Determines how carrier extension is suppressed when hgmii.ibs_speed < 2 (10/100MBit mode)
0: No suppression (except at odd nibble if configured)
1: Apply SGMII PHY rules: Suppress in full duplex mode
hgmii.rx_er = hgmii.ibs_duplex ? (pcs_rx_dv & pcs_rx_er) : pcs_rx_er
2: Suppress always:
hgmii_rx_er = pcs_rx_dv & pcs_rx_er
Note: carrier extension suppression in MII mode is normally not needed due to shifted sampling in case of odd-aligned frame. May be always kept at 0.
5 - 4 "00"
rx_cesup_gmii
Determines how carrier extension is suppressed when hgmii.ibs_speed = 2 (1000MBit Mode)
0: No suppression
1: Apply SGMII PHY rules: Suppress in full duplex mode
hgmii.rx_er = hgmii.ibs_duplex ? (pcs_rx_dv & pcs_rx_er) : pcs_rx_er
2: Suppress always:
hgmii_rx_er = pcs_rx_dv & pcs_rx_er
3 "0"
rx_adapt_nibble_status
Determines how rx_dv and rx_er are sampled in MII (10/100) Modes
0: sample rx_dv and rx_er once per downsample period, aligned to start of frame, as done for rxd
1: update rx_dv and rx_er in the middle of downsample period
setting 1 is useful to support odd number of nibbles per frame
2 0
-
 reserved
1 - 0 "01"
tx_adapt_nibble_status
Determines how TX_EN and TX_ER of PCS is determined in MII (10/100) Modes
0: low  nibble status bits are used for complete replicaion of content
1: high nibble status bits are used for complete replicaion of content
2: low  nibble status bits are used for first half of replicaion of content
high nibble status bits are used for second half of replicaion of content
- setting is irrelevant as long as no odd number of nibbles are transferred.
- IEEE section2 22.2.3.5 allows implementation-specific behaviour when using odd nibbles
- setting 2 allows to transfer odd nibble status bits separately
- using odd nibbles is not defined in SGMII spec.
- tbd: special status codes (tx_en=0 & tx_er=1) might not be transfered correctly during odd nibble


h_pcs_config
advanced PCS and PMA configuration
R/W
0x00000041
Address@com_hsgmii0 : 0x06400458
Address@com_hsgmii1 : 0x06400558
Address@app_hsgmii : 0x40092058
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "1"
sd1000_val
value 'siglal detect' for 1000BASE-FX if sd100_src=0. Should be 1 for normal operation. Set to 0 for debug only.
5 "0"
sd1000_src
source of 'siglal detect' for 1000BASE-FX. Should be 0 for SGMII operation.
0 : fixed to sd1000_val
1 : ext_signal_detect
Note: Normally, Signal_detect can be set fixed to 1 because the synchronization FSM detect LOSS_OF_SYNC sufficiently by invalid or disaligned code groups.
An external signal_detect, usually driven by a fiber optics receiver, might be used additionally to force LOSS_OF_SYNC when signal_detect=0.
Note: ext_signal_detect is wired to com_sgmii?_link or app_mdio
4 "0"
pcs100_sample_mid
determines how data received from PMA is sampled in 100bt mode
0 : majority decision of 9 samples between the edges
1 : middle sample between the edges
3 "0"
tx_shadow_cfg_msb
0: tx_config_reg[15:8] is read when transferred in CONFIGURATION_C2D, as specified in IEEE
1: tx_config_reg[15:8] is transferred to a shadow register when tx_config_reg[7:0] is read in CONFIGURATION_C1D. In CONFIGURATION_C2D, the shadow register is transferred.
This avoids inconsistent transfer of tx_config_reg
Note: Normally, inconststent transfer is no problem since the config_reg is checkled 3 times when received.
Setting this bit to 1 might be useful for future protocol implementations.
2 "0"
rx_special_idle_sfd
1: RX FSM reacts to special idle SFD to prevent preamble shrinkage
   Breaks ieee standard but should have no effect if special idle sfd is not supported by TX
   /SI1/ = /K28.5/D5.1/
   /SI2/ = /K28.5/D16.1/
1 "0"
tx_special_idle_sfd
1: TX FSM generates special idle (SI) ordered set to signal a start of frame during idle ordered set
   Breaks ieee standard but should be ignored by standard ieee RX implementations
   Used to prevent preamble shrinkage if receiver also supports special idle sfd
   /SI1/ = /K28.5/D5.1/
   /SI2/ = /K28.5/D16.1/
0 "1"
en_cdet
enable comma detection at RX deserializer


h_pma_special
special PMA configuration. Should be kept default
This register is only writable when pll_on == 0 or (pma_rx_nres == 0 && pma_tx_nres == 0)
R/W
0x001fe0f8
Address@com_hsgmii0 : 0x0640045c
Address@com_hsgmii1 : 0x0640055c
Address@app_hsgmii : 0x4009205c
Bits Reset value Name Description
31 "0"
tx_inv
1: invert serialzed signal before transmission
30 "0"
tx_lsb_first
0: TBI msb first serialization
1: TBI lsb first serialization
29 "0"
rx_inv
1: invert received signal stream before deserialization
28 "0"
rx_lsb_first
0: TBI msb first deserialization
1: TBI lsb first deserialization
27 - 21 0
-
 reserved
20 "1"
rx_comma_rev
1: additional recognize inverse comma pattern
19 - 10 0x3f8
rx_comma_mask
comma recognition mask
9 - 0 0xf8
rx_comma
comma recognition pattern


h_bypass
PCS & adapt bypass (for debug or custom protocol implementation)
R/W
0x00000000
Address@com_hsgmii0 : 0x06400460
Address@com_hsgmii1 : 0x06400560
Address@app_hsgmii : 0x40092060
Bits Reset value Name Description
31 - 23 0x0
tx_enc_direct_kddn
see tx_enc_direct
22 - 16 0
-
 reserved
15 - 7 0x0
tx_enc_direct_kddp
see tx_enc_direct
6 0
-
 reserved
5 "0"
pcs100_tx_b5_direct
Bypass control for 1000BASE-X TX
0 : normal operation
1 : transmit B5 code = hgmii.txd[4:0]
note: device must be configured for 100BASE-X to use this bypass. B5 code is still synchronized to SFD.
4 "0"
pcs100_rx_b5_direct
Bypass control for 1000BASE-X RX
0 : normal operation
1 : hgmii.rxd[4:0] = received B5 code
note: device must be configured for 100BASE-X to use this bypass. B5 code is still synchronized to SFD. rx_en and rx_dv are still operating.
3 - 2 "00"
rx_bypass
0 : no RX bypass
1 : hgmii.rx* is controlled by decoder output:
   hgmii.rx_td = dec_td
   hgmii.rxd   = dec_data
   hgmii.rx_dv = ~dec_k
   hgmii.rx_er = dec_invalid
2 : hgmii.rx* is controlled by TBI output
   hgmii.rx_td = tbi_rx_td
   hgmii.rxd   = tbi_rx[7:0]
   hgmii.rx_dv = tbi_rx[8]
   hgmii.rx_er = tbi_rx[9]
note: pcs_sel100 must be 0 to use this bypass
1 "0"
tx_tbi_direct
0 : TX TBI interface is controlled by TX encoder
1 : TX TBI interface is directly controlled by hgmii.tx*:
   tbi_tx_td = hgmii.tx_td
   tbi_tx[7:0] = hgmii.txd
   tbi_tx[8]   = hgmii.tx_en
   tbi_tx[9]   = hgmii.tx_er
note: pcs_sel100 must be 0 to use this bypass
0 "0"
tx_enc_direct
0: TX encoder is controlled by PCS
1:




TX encoder is directly controlled by hgmii.tx* :
enc_td   = hgmii.tx_td
enc_data = hgmii.txd
enc_k    = ~hgmii.tx_en
hgmii.tx_er = 1 causes wrong disparity
hgmii.txd=0 && enc_k=1 generates disparity depending special data defined by tx_enc_direct_kdd*.
This is useful to get the running disparity to a known state:
     enc_data=tx_enc_direct_kddp[7:0], enc_k=tx_enc_direct_kddp[8] when running disparity is positive
     enc_data=tx_enc_direct_kddn[7:0], enc_k=tx_enc_direct_kddn[8] when running disparity is negative


h_cdr_config
This register is only writable when pll_on == 0 or pma_rx_nres == 0!
RX clock/data recovery configuration
phase regulation coefficients
For stable regulation, it is recommended that cdr_coeff_p is much higher than cdr_coeff_i
R/W
0x00400800
Address@com_hsgmii0 : 0x06400464
Address@com_hsgmii1 : 0x06400564
Address@app_hsgmii : 0x40092064
Bits Reset value Name Description
31 - 16 0x40
cdr_coeff_i
integral coefficient. Fixed point value with 20 fraction bits.
15 - 0 0x800
cdr_coeff_p
proportional coefficient. Fixed point value with 16 fraction bits.


h_cdr_config2
This register is only writable when pll_on == 0 or pma_rx_nres == 0!
RX clock/data recovery configuration
phase limit coefficients
R/W
0x0000000b
Address@com_hsgmii0 : 0x06400468
Address@com_hsgmii1 : 0x06400568
Address@app_hsgmii : 0x40092068
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
phdet_lr_en
1: enable low-rate phase detection for 125MBit/s channel
Note: This is needed for gigabit PCS and recommended also for 100base-X. If no phase detection is enabled, the CDR is turned off.
3 "1"
phdet_hr_en
1: enable high-rate phase detection using 180deg shifted sampling
Note: This is needed for 1.25GBit/s channel. If no phase detection is enabled, the CDR is turned off. phdet_hr_en superceeds phdet_lr_en.
2 - 0 "011"
cdr_integ_limit
limitation of internal CDR integrator
max_freq_drift = 2-5 - cdr_integ_limit
where max_freq_drift = |(fclk_remote/fclk_local) - 1|
if max_freq_drift is too low, larger frequency drifts can't be locked
if max_freq_Drift is too high, the CDR might theoretically be unable to lock if some wrong frequency catched it
The default value limits the relative frequency difference to +-0.39%


h_cdr_status
R
Address@com_hsgmii0 : 0x0640046c
Address@com_hsgmii1 : 0x0640056c
Address@app_hsgmii : 0x4009206c
Bits Name Description
31 - 16 phsel_inc_sum
rx_clk phase increments since last read, saturated to 0xffff
15 - 0 phsel_dec_sum
rx_clk phase decrements since last read, saturated to 0xffff


h_clkgen_config
This register is only writable when pll_on=0 !
PMA clock generator config
R/W
0x00000004
Address@com_hsgmii0 : 0x06400470
Address@com_hsgmii1 : 0x06400570
Address@app_hsgmii : 0x40092070
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0100"
pll_fd
PLL frequency divider (pll_fout/system_clock)
0: div by 1 .. 15: div by 16


h_afe_cfg
RX & TX analog frontend configuration
R/W
0x00000000
Address@com_hsgmii0 : 0x06400474
Address@com_hsgmii1 : 0x06400574
Address@app_hsgmii : 0x40092074
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
tx_term_enable
TX Enable termination
0: High Z (d_rx_term = 0)
1: as calibrated (d_tx_term = cal.termmination_rx)
6 - 3 "0000"
d_vcm
TX common mode voltage
vcm = (d_vcm * 0.0286 + 0.3) * VDDPST18
useful values:
 7: vcm=VDDPST/2 : most symmetric behaviour, best setting to use with AC coupling
13: best match to 1.2V LVDS standard if DC coupling is used
See doc/tools/settings_calculation.ods for details
2 "0"
rx_term_enable
RX Enable termination
0: High Z (d_rx_term = 0)
1: as calibrated (d_rx_term = cal.termmination_rx)
1 "0"
d_hyst_off
1: RX hysteresis disabled
0 "0"
d_cmr_on
1: RX common-mode pull resistors enable


h_cal
Calibration
R/W
0x00004000
Address@com_hsgmii0 : 0x06400478
Address@com_hsgmii1 : 0x06400578
Address@app_hsgmii : 0x40092078
Bits Reset value Name Description
31 - 23 0
-
 reserved
22 - 19 "0000"
d_iout
TX differential amplitude
Value 10 is recommended to get typical 350mV amplitude when both sides are terminated
Value 3 is recommended to get typical 350mV amplitude when one side is terminated
See doc/tools/settings_calculation.ods for details
18 - 17 "00"
d_slew
TX Slew Rate: number of steps per unit delay
0: 6 steps (slowest)
1: 3 steps
2: 2 steps
3: 1 step (no slew control, fastest)
16 - 14 "001"
clkgen_tx_dll_fd
TX Slew Rate: DLL reference clock divider (clk_tx / clk_tx_dll)
0: div by 1 .. 7: div by 8
Value 1 is recommended to match SGMII slew specification
13 - 11 "000"
d_dll_div
TX Slew Rate: DLL unit delays per reference clock period
7: 40
6: 37
5: 34
4: 31
3: 28
2: 26
1: 24
0: 22
Value 6 is recommended to match SGMII slew specification
10 - 6 "00000"
termination_rx
number of termination unit resistors for RX when termination is enabled
0 -> HighZ ..  18 (100Ohm typ) .. 31 (min.)
5 - 1 "00000"
termination_tx
number of termination unit resistors for TX when termination is enabled
0 -> HighZ ..  18 (100Ohm typ) .. 31 (min.)
0 "0"
clkgen_pll_vregh
VCO voltage regulator calibration
0: normal voltage
1: higher voltage


h_power
specific power down selection
R/W
0x00000000
Address@com_hsgmii0 : 0x0640047c
Address@com_hsgmii1 : 0x0640057c
Address@app_hsgmii : 0x4009207c
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
pcs_sel100
selects which type of PCS layer is enabled when pcs_enable=1 . The unused PCS layer is always disabled.
0 : use 1000BASE-X PCS Layer
1 : use 100BASE-X PCS Layer
Note: For SGMII, 1000BASE-X PCS Layer must be selected.
5 "0"
pcs_enable
0: disable 1000MBit PCS layer by assigning power_on=false to corresponding state machines
1: enable 1000MBit PCS layer by assigning power_on=true to corresponding state machines
This value is also changed by:
  - writing to mr_control.power_down
4 "0"
rx_pma_nres
RX PMA (in rx_clk clock domain) is in reset when rx_pma_nres == 0 || pll_on == 0
This value is also changed by:
 - writing to mr_control.power_down
3 "0"
tx_pma_nres
TX PMA (in tx_clk clock domain) is in reset when tx_pma_nres == 0 || pll_on == 0
This value is also changed by:
 - writing to mr_control.power_down
2 "0"
pll_on
0: PLL is powered down, PMA is in reset
1: PLL is active, PMA reset will be released after PLL converged
This value is also changed by:
 - writing to mr_control.power_down
1 "0"
d_comp_on
0: RX comparator is powered down
This value is also changed by:
  - writing to mr_control.power_down
0 "0"
d_tx_on
0: TX is powered down
This value is also changed by:
  - writing to mr_control.power_down


h_sd100_cfg
configuration of signal detect for 100BASE-X
R/W
0x80000400
Address@com_hsgmii0 : 0x06400480
Address@com_hsgmii1 : 0x06400580
Address@app_hsgmii : 0x40092080
Bits Reset value Name Description
31 - 17 0x4000
link_status_time
time that signal must be continuoisly 1 to set link_status = 1, in 31.25us steps (4*baud)
note: link_status is set to 0 immediately when signal_detect = 0
note: This equals link monitor "stabilize time"
note: This value might be set to low value or 0 for debugging. Setting sd_off_time = 0 and link_status_time = 0 allows unfiltered control of link_status.
16 - 2 0x100
sd_off_time
time that sd must be continuoisly 0 to set signal_detect = 0, in 31.25us steps (4*baud)
note: signal_detect is set to 1 immediately when sd = 1
note: when using sd_src=1, sd_off_time should be set to a higher value. Otherwise, it might be set to 0.
1 - 0 "00"
sd_src
sorce of signal detect
0: sd = rx ^ rx_last (i.e. when rx toggles). Note: d_hyst_off=0 is recommended when using in this mode # default 0
1: sd = ext_signal_detect
2: sd = 0
3: sd = 1



Base Address Area: com_xspi, xspi_evm

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W xspi_cr
1 4 R/W xspi_clk_cr0
2 8 R/W xspi_clk_cr1
3 c R/W xspi_dll_cr0
4 10 R/W xspi_dll_cr1
5 14 R/W xspi_dll_cr2
6 18 R/W xspi_csn_addr_map
7 1c R xspi_sr
8 20 R xspi_fsr
9 24 R/W xspi_fcr
a 28 R/W xspi_dvr0
b 2c R/W xspi_dvr1
c 30 R/W xspi_tcr0
d 34 R/W xspi_tcr1
e 38 R/W xspi_tcr2
f 3c R/W xspi_tlr
10 40 W xspi_ial0
11 44 W xspi_ial1
12 48 W xspi_ial2
13 4c W xspi_ial3
14 50 R/W xspi_mm_wcr0
15 54 R/W xspi_mm_wcr1
16 58 R/W xspi_mm_rcr0
17 5c R/W xspi_mm_rcr1
18 60 R/W xspi_mm_cr0
19 64 R/W xspi_mm_cr1
1a 68 R/W xspi_mm_cr2
1b 6c R/W xspi_mm_cr3
1c 70 R/W xspi_mhc0
1d 74 R/W xspi_mhc1
1e 78 R/W xspi_mlc0
1f 7c R/W xspi_mlc1
20 80 R/W xspi_irq_mask
21 84 R/W xspi_irq_raw
22 88 R xspi_irq_masked
23 8c R/W xspi_pio_out
24 90 R/W xspi_pio_oe
25 94 R xspi_pio_is
26 98 R xspi_rx_dr
27 9c -  reserved
28 a0 W xspi_csn0_ar_1s
29 a4 W xspi_csn0_ar_2s
2a a8 W xspi_csn0_ar_4s
2b ac W xspi_csn0_ar_8s
2c b0 W xspi_csn0_ar_1d
2d b4 W xspi_csn0_ar_2d
2e b8 W xspi_csn0_ar_4d
2f bc W xspi_csn0_ar_8d
30 c0 W xspi_csn1_ar_1s
31 c4 W xspi_csn1_ar_2s
32 c8 W xspi_csn1_ar_4s
33 cc W xspi_csn1_ar_8s
34 d0 W xspi_csn1_ar_1d
35 d4 W xspi_csn1_ar_2d
36 d8 W xspi_csn1_ar_4d
37 dc W xspi_csn1_ar_8d
38 e0 W xspi_tx_dr_1s
39 e4 W xspi_tx_dr_2s
3a e8 W xspi_tx_dr_4s
3b ec W xspi_tx_dr_8s
3c f0 W xspi_tx_dr_1d
3d f4 W xspi_tx_dr_2d
3e f8 W xspi_tx_dr_4d
3f fc W xspi_tx_dr_8d
40 100 W xspi_tx_dr_4s_ds_off
41 104 W xspi_tx_dr_8s_ds_off
42 108 W xspi_tx_dr_4d_ds_off
43 10c W xspi_tx_dr_8d_ds_off
44 110 R/W xspi_csn0_addr_byte0_cr0
45 114 R/W xspi_csn0_addr_byte0_cr1
46 118 R/W xspi_csn0_addr_byte1_cr0
47 11c R/W xspi_csn0_addr_byte1_cr1
48 120 R/W xspi_csn0_addr_byte2_cr0
49 124 R/W xspi_csn0_addr_byte2_cr1
4a 128 R/W xspi_csn0_addr_byte3_cr0
4b 12c R/W xspi_csn0_addr_byte3_cr1
4c 130 R/W xspi_csn0_addr_byte4_cr0
4d 134 R/W xspi_csn0_addr_byte4_cr1
4e 138 R/W xspi_csn0_addr_byte5_cr0
4f 13c R/W xspi_csn0_addr_byte5_cr1
50 140 R/W xspi_csn1_addr_byte0_cr0
51 144 R/W xspi_csn1_addr_byte0_cr1
52 148 R/W xspi_csn1_addr_byte1_cr0
53 14c R/W xspi_csn1_addr_byte1_cr1
54 150 R/W xspi_csn1_addr_byte2_cr0
55 154 R/W xspi_csn1_addr_byte2_cr1
56 158 R/W xspi_csn1_addr_byte3_cr0
57 15c R/W xspi_csn1_addr_byte3_cr1
58 160 R/W xspi_csn1_addr_byte4_cr0
59 164 R/W xspi_csn1_addr_byte4_cr1
5a 168 R/W xspi_csn1_addr_byte5_cr0
5b 16c R/W xspi_csn1_addr_byte5_cr1
5c-7f 170-1fc -  reserved

xspi_cr
xSPI Control Register (CR)
R/W
0x00000000
Address@com_xspi : 0x06400600
Address@xspi_evm : 0x40020000
Bits Reset value Name Description
31 "0"
reset
Reset to bring the XSPI controller back to a known state.
Will clear all FIFOs and drop pending AXI requests. It will reset AXI valid signals that are controlled
by the XSPI controller (r_valid, b_valid) to zero, which could lead to a violation of the AXI Specification:
If valid signals are high they must remain high until accepted by a ready signal from the counterpart.
While the reset is active, reading any register will return 0.
The hardware will automatically reset this bit.
30 - 6 0
-
 reserved
5 "0"
intn_polarity
External interrupt polarity
0 : active low
1 : active high
4 "0"
clk_monitor_enable
Enable the monitoring of the receive and transmit clock.
The clock monitor generates the clk_rx_too_slow, clk_rx_too_fast and clk_rx_tx_drifted interrupts.
Note: Counts and compares the clk_tx and clk_rx cycles for a transfer.
Note: Will throw an error if row boundary crossings lead to waiting cycles where DS (used as clk_rx)
is not toggling but the external clk is (APS51208N-OBR.pdf, Figure 6: Linear Burst Read with RBX).
3 - 2 "00"
xspi_mode
xSPI mode configuration, should only be changed if XSPI is idle or disabled.
00: Peripheral mode (default)
01: Memory mapped mode
10: Programmable IO mode
11: reserved
Note: Writable, but can also be changed by hardware if reset is activated or if xspi_mode is memory_mapped and TCR2.end_transfer is used.
Note: The Programmable IO mode can only be entered if clk_tx is off (CLK_CR0/1.clk_tx_en = 0).
1 0
-
 reserved
0 "0"
xspi_en
xSPI Enable
Note : The xSPI module should be disabled if it is not used for transfers. (E.g. it is only used to load an image from flash during startup).
Otherwise the internal slave DLLs will not toggle and might experience aging effects.
Note : The internal clocks (CLK_CR0/1) are also disabled if the module is disabled.
Note : The mode is switched to peripheral mode if the xSPI module is disabled.


xspi_clk_cr0
xSPI Clock Control Register 0 (CLK_CR0)
Clock divider control for chip select domain 0.
R/W
0x000000ff
Address@com_xspi : 0x06400604
Address@xspi_evm : 0x40020004
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
clk_tx_en
Enable Serial clock rate divider for chip select domain 0.
Writable, but can also be changed by hardware.
Note : The module must be enabled to enable the clk (CR.xspi_en).
Note : Turning off the module (CR.xspi_en) also turns off the clk.
Note : The module must not be in PIO mode to enable the clk (CR.xspi_mode).
7 - 0 "11111111"
clk_tx_div_val
Serial clock rate divider for chip select domain 0.
clk_fast (2GHz) will be divided by (clk_div_val+1) for clk_tx generation.
 9 : 200 MHz
11 : 166 MHz
14 : 133 MHz
19 : 100 MHz
24 : 80 MHz
29 : 66 MHz
39 : 50 MHz
Note : If changed the master DLL should probably be resynced (DLL_CR2.resync_dll) if it is not operating in bypass mode.


xspi_clk_cr1
xSPI Clock Control Register 1 (CLK_CR1)
Clock divider control for chip select domain 1.
R/W
0x000000ff
Address@com_xspi : 0x06400608
Address@xspi_evm : 0x40020008
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
clk_tx_en
Enable Serial clock rate divider for chip select domain 1.
Writable, but can also be changed by hardware.
Note : The module must be enabled to enable the clk (CR.xspi_en)
Note : Turning off the module (CR.xspi_en) also turns off the clk.
Note : The module must not be in PIO mode to enable the clk (CR.xspi_mode).
7 - 0 "11111111"
clk_tx_div_val
Serial clock rate divider for chip select domain 1.
clk_fast (2GHz) will be divided by (clk_div_val+1) for clk_tx generation.
 9 : 200 MHz
11 : 166 MHz
14 : 133 MHz
19 : 100 MHz
24 : 80 MHz
39 : 50 MHz
Note : If changed the master DLL should probably be resynced (DLL_CR2.resync_dll) if it is not operating in bypass mode.


xspi_dll_cr0
xSPI DLL Control Register 0 (DLL_CR0)
Controls the DLL for chip select domain 0.
After enabling clk_tx_csn0 (CLK_CR0.clk_tx_en), the master DLL periodically (DLL_CR2) starts the locking process with the configured CLK_CR0.clk_tx_div_val, phase_dly_value and starting_value parameters.
This register may be reconfigured while the xSPI is running.
R/W
0x00364040
Address@com_xspi : 0x0640060c
Address@xspi_evm : 0x4002000c
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
clk_rx_delay_by
CSN0 Receive Clock Delay Bypass
0: clk_rx_delay delays the internal clk_rx in relation to the external xspi_clk by steps of 1/256th of the period of xspi_clk (xspi_clk period == clk_tx period).
1: clk_rx_delay directly selects the number of delay elements used to delay the internal clk_rx in relation to the external xspi_clk.
Note: If the DLL locks in saturation (SR.csn0_dll_lock_mode = saturation), it is recommended to turn on clk_rx_delay_by and clk_tx_delay_by.
      The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
      bypass mode and the master being in saturation mode.
24 "0"
clk_tx_delay_by
CSN0 Transmit Clock Delay Bypass
0: clk_tx_delay delays the external xspi_clk in relation to the internal clk_tx by steps of 1/256th of the period of clk_tx (xspi_clk period == clk_tx period).
1: clk_tx_delay directly selects the number of delay elements used to delay the external xspi_clk in relation to the internal clk_tx.
Note: If the DLL locks in saturation (SR.csn0_dll_lock_mode = saturation), it is recommended to turn on clk_rx_delay_by and clk_tx_delay_by.
      The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
      bypass mode and the master being in saturation mode.
23 0
-
 reserved
22 - 20 "011"
phase_dly_value
phase_dly_value+1 delay elements inserted to build the window between two rising clock edges
that detect the locking of the DLL for chip select domain 0.
If the DLL does not lock, the phase_dly_value should be increased.
Note: should only be changed if DLL0 is locked SR.csn0_dll_locked or if clk_tx_csn0 is disabled CLK_CR0.clk_tx_en.
19 0
-
 reserved
18 - 16 "110"
starting_value
The DLL for chip select domain 0 will start its locking process with 2^starting_value delay elements.
Note: should only be changed if DLL0 is locked SR.csn0_dll_locked or if clk_tx_csn0 is disabled CLK_CR0.clk_tx_en.
15 - 8 "01000000"
clk_rx_delay
Controls the delay of the internal clk_rx in relation to the external xspi_clk for chip select domain 0.
If clk_rx_delay_by is not set the delay is controlled in steps of 1/256th of the xspi_clk period.
If clk_rx_delay_by is set clk_rx_delay is the number of delay elements inserted to delay the clk_rx.
Note: If !clk_rx_delay_by and (SR.csn0_dll_lock_mode == half clock) and SR.csn0_dll_locked, the DLL might overflow ((SR.csn0_dll_lock_value*2)*clk_rx_delay/256 >=256).
      In that case the behavior is dependent on TCR0.rx_ddr and TCR0.rx_sdr_edge. If none of the two are set, the delay is set to ((SR.csn0_dll_lock_value*2)*clk_rx_delay/256 - 256)
      and the RX sampling edge is set to be the negedge of clk_rx (as if TCR0.rx_sdr_edge was set).
      If TCR0.rx_ddr or TCR0.rx_sdr_edge are set, the DLL will be in saturation mode meaning all delay elements will be selected.
7 - 0 "01000000"
clk_tx_delay
Controls the delay of the external xspi_clk in relation to the internal clk_tx for chip select domain 0
If clk_tx_delay_by is not set the delay is controlled in steps of 1/256th of the clk_tx period.
If clk_tx_delay_by is set the clk_tx_delay is the number of delay elements inserted to delay the external xspi_clk (xspi_clk period == clk_tx period).
Note: If !clk_rx_delay_by and (SR.csn0_dll_lock_mode == half clock) and SR.csn0_dll_locked, the DLL might overflow ((SR.csn0_dll_lock_value*2)*clk_rx_delay/256 >=256).
      In that case, the DLL will be in saturation mode meaning all delay elements will be selected.


xspi_dll_cr1
xSPI DLL Control Register 1 (DLL_CR1)
Controls the DLL for chip select domain 1.
After enabling the clk_tx_csn1 (CLK_CR1.clk_tx_en), the master DLL periodically (DLL_CR2) starts the locking process with the configured CLK_CR1.clk_tx_div_val, phase_dly_value and starting_value parameters.
This register may be reconfigured while the xSPI is running.
R/W
0x00364040
Address@com_xspi : 0x06400610
Address@xspi_evm : 0x40020010
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
clk_rx_delay_by
CSN1 Receive Clock Delay Bypass
0: clk_rx_delay delays the internal clk_rx in relation to the external xspi_clk by steps of 1/256th of the period of xspi_clk (xspi_clk period == clk_tx period).
1: clk_rx_delay directly selects the number of delay elements used to delay the internal clk_rx in relation to the external xspi_clk.
Note: If the DLL locks in saturation (SR.csn1_dll_lock_mode = saturation), it is recommended to turn on clk_rx_delay_by and clk_tx_delay_by.
      The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
      bypass mode and the master being in saturation mode.
24 "0"
clk_tx_delay_by
CSN1 Transmit Clock Delay Bypass
0: clk_tx_delay delays the external xspi_clk in relation to the internal clk_tx by steps of 1/256th of the period of clk_tx (xspi_clk period == clk_tx period).
1: clk_tx_delay directly selects the number of delay elements used to delay the external xspi_clk in relation to the internal clk_tx.
Note: If the DLL locks in saturation (SR.csn1_dll_lock_mode = saturation), it is recommended to turn on clk_rx_delay_by and clk_tx_delay_by.
      The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
      bypass mode and the master being in saturation mode.
23 0
-
 reserved
22 - 20 "011"
phase_dly_value
phase_dly_value+1 delay elements inserted to build the window between two rising clock edges
that detect the locking of the DLL for chip select domain 0.
If the DLL does not lock, the phase_dly_value should be increased.
Note: should only be changed if DLL1 is locked SR.csn1_dll_locked or if clk_tx_csn1 is disabled CLK_CR1.clk_tx_en.
19 0
-
 reserved
18 - 16 "110"
starting_value
The DLL for chip select domain 1 will start its locking process with 2^starting_value delay elements.
Note: should only be changed if DLL1 is locked SR.csn1_dll_locked or if clk_tx_csn1 is disabled CLK_CR1.clk_tx_en.
15 - 8 "01000000"
clk_rx_delay
Controls the delay of the external xspi_clk in relation to the internal clk_tx for chip select domain 1
If clk_rx_delay_by is not set the delay is controlled in steps of 1/256th of the clk_tx period.
If clk_rx_delay_by is set clk_rx_delay is the number of delay elements inserted to delay the clk_rx.
Note: If !clk_rx_delay_by and (SR.csn1_dll_lock_mode == half clock) and SR.csn1_dll_locked, the DLL might overflow ((SR.csn1_dll_lock_value*2)*clk_rx_delay/256 >=256).
      In that case the behavior is dependent on TCR1.rx_ddr and TCR1.rx_sdr_edge. If none of the two are set, the delay is set to ((SR.csn1_dll_lock_value*2)*clk_rx_delay/256 - 256)
      and the RX sampling edge is set to be the negedge of clk_rx (as if TCR1.rx_sdr_edge was set).
      If TCR1.rx_ddr or TCR1.rx_sdr_edge are set, the DLL will be in saturation mode meaning all delay elements will be selected.
7 - 0 "01000000"
clk_tx_delay
Controls the delay of the external xspi_clk in relation to the internal clk_tx for chip select domain 0
If clk_tx_delay_by is not set the delay is controlled in steps of 1/256th of the clk_tx period.
If clk_tx_delay_by is set the clk_tx_delay is the number of delay elements inserted to delay the external xspi_clk (xspi_clk == clk_tx).
Note: If !clk_rx_delay_by and (SR.csn1_dll_lock_mode == half clock) and SR.csn1_dll_locked, the DLL might overflow ((SR.csn1_dll_lock_value*2)*clk_rx_delay/256 >=256).
      In that case, the DLL will be in saturation mode meaning all delay elements will be selected.


xspi_dll_cr2
xSPI DLL Control Register 2 (DLL_CR2)
Controls the general DLL configs.
This register may be reconfigured while the xSPI is running.
R/W
0x31052710
Address@com_xspi : 0x06400614
Address@xspi_evm : 0x40020014
Bits Reset value Name Description
31 "0"
resync_dll
Unlocks the DLL and starts a new locking process.
Writable, but can also be changed by hardware.
Note : Only updates if CLK_CR0.clk_tx_en and / or CLK_CR1.clk_tx_en
       Returns 0 when read.
30 "0"
disable_resync
Disables periodical resync of the master DLL.
Note : Can be safely turned off if everything operates in bypass mode anyway (DLL_CR0/1.clk_tx/rx_by).
29 - 28 "11"
toggle_en
Enables toggeling of the unused delay elements in the delay chains to mitigate asymmetrical aging.
x1 : Enable toggeling for the CSN1 master delay chain
1x : Enable toggeling for the CSN1 slave delay chains
Note : The xSPI module should be disabled if it is not used for transfers. (E.g. it is only used to load an image from flash during startup).
       Otherwise parts of the internal slave DLLs will not toggle and might experience asymmetrical aging effects.
27 - 24 "0001"
resync_delay
Number of resync_delay+2 clk_tx cycles that the next transfer will be delayed to reconfigure the slave DLLs if required.
If a reconfiguration is required, the output of the slave DLLs is supressed for resync_delay+1 clk_tx cycles.
23 - 16 "00000101"
delay_tolerance
Defines a tolerance in number of delay elements.
The slave DLLs are only updated if the number of delay elements change by a value bigger than delay_tolerance.
15 - 14 0
-
 reserved
13 - 0 0x2710
resync_period
Controls the period of the master DLL resync.
Note: Steps of 10ns (clk_cfg = 100MHz)
10000 = 100us


xspi_csn_addr_map
xSPI CSN Address Map Register (CSNAMR).
This register must not be changed if CR.xspi_mode == memory mapped mode.
Configures the address map for the CSN domains (pins CSN0, CSN1) in memory mapped mode.
If enabled, CSN0 is used for transfers to addresses smaller than the csn address boundary and CSN1
for transfers to addresses bigger or equal than the csn address boundary. If disabled, CSN0 is used for all transfers.
Please not that if only CSN1 is connected to a device and all transfers should be routed to CSN1,
the en bit must be set and due to the boundary implementation, all addresses need to have 1 MB offset if boundary = 0.
The granularity of boundary is 1 MB.
R/W
0x00000000
Address@com_xspi : 0x06400618
Address@xspi_evm : 0x40020018
Bits Reset value Name Description
31 "0"
en
Enable CSN addess boundary
30 - 28 0
-
 reserved
27 - 0 0x0
boundary
CSN address boundary
0 : Address >= 0x0010_0000 -> CSN1, 0x0010_0000 > Address -> CSN0
1 : Address >= 0x0020_0000 -> CSN1, 0x0020_0000 > Address ->  CSN0
...
Note: 1 MB granularity


xspi_sr
XSPI status register (SR)
R
Address@com_xspi : 0x0640061c
Address@xspi_evm : 0x4002001c
Bits Name Description
31 csn1_dll_resync
Master DLL resyncs the number of delay elements for CSN1.
30 - 23 csn1_dll_lock_value
csn1_dll_lock_value + 1 is the number of delay elements used in the master delay chain for CSN1.
Note : Only contains valid information if csn1_dll_locked.
22 - 21 csn1_dll_lock_mode
Contains the lock mode information of the master delay chain for CSN1.
Note : Only contains valid information if csn1_dll_locked.
00 : Full clock mode
01 : Half clock mode
10 : Saturation mode
11 : Bypass mode
Note :
If the DLL locks in saturation, it is recommended to turn on DLL_CR1.clk_rx_delay_by and DLL_CR1.clk_tx_delay_by.
The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
bypass mode and the master being in saturation mode.
Note : Only contains valid information if csn1_dll_locked.
20 csn1_dll_lc_skipped
The DLL lock condition was skipped during the locking attempt. This can happen if DLL_CR1.phase_dly_value is too low.
It means that during the locking process a condition where the number of delay elements needs to be increased was immediatly
followed by a condition where the number of delay elements needs to be decreased. Usually, the locking condition should occur in between.
Note : Only contains valid information if csn1_dll_locked.
19 csn1_dll_locked
The DLL for clk_tx_csn1 (determined by clk_tx_csn1_div_val) was locked once.
Note: After the DLL was locked once, periodical updates may occur (DLL_CR2). During those periodical updates the status is still locked, but the lock_value may change.
18 csn0_dll_resync
Master DLL resyncs the number of delay elements for CSN0.
17 - 10 csn0_dll_lock_value
csn0_dll_lock_value + 1 is the number of delay elements used in the master delay chain for CSN0.
Note : Only contains valid information if csn0_dll_locked.
9 - 8 csn0_dll_lock_mode
Contains the lock mode information of the master delay chain for CSN0.
00 : Full clock mode
01 : Half clock mode
10 : Saturation mode
11 : Bypass mode
Note :
If the DLL locks in saturation, it is recommended to turn on DLL_CR0.clk_rx_delay_by and DLL_CR0.clk_tx_delay_by.
The reason for this is the periodic resync that takes a lot of time to lock in saturation and that the slave DLLs behave the same for
bypass mode and the master being in saturation mode.
Note : Only contains valid information if csn0_dll_locked.
7 csn0_dll_lc_skipped
The DLL lock condition was skipped during the locking attempt. This can happen if DLL_CR0.phase_dly_value is too low.
It means that during the locking process a condition where the number of delay elements needs to be increased was immediatly
followed by a condition where the number of delay elements needs to be decreased. Usually, the locking condition should occur in between.
Note : Only contains valid information if csn0_dll_locked.
6 csn0_dll_locked
The DLL for clk_tx_csn0 (determined by clk_tx_csn0_div_val) was locked once.
Note: After the DLL was locked once, periodical updates may occur (DLL_CR2).  During those periodical updates the status is still locked, but the lock_value may change.
5 clk_rx_tx_drifted
The clock monitor detected that the clk_rx and clk_tx drifted. During an RX Transfers an unequal amount of clk_tx and clk_rx edges were detected.
Writing this bit will clear all flags generated by the clk_monitor (clk_rx_too_fast, clk_rx_too_slow, clk_rx_tx_drifted).
Note: Should not be cleared during an active transfer.
4 clk_rx_too_fast
The clock monitor detected that the clk_rx was faster than the clk_tx.
Writing this bit will clear all flags generated by the clk_monitor (clk_rx_too_fast, clk_rx_too_slow, clk_rx_tx_drifted).
Note: Should not be cleared during an active transfer.
3 clk_rx_too_slow
The clock monitor detected that the clk_rx was faster than the clk_tx.
Writing this bit will clear all flags generated by the clk_monitor (clk_rx_too_fast, clk_rx_too_slow, clk_rx_tx_drifted).
Note: Should not be cleared during an active transfer.
2 axi_core_busy
The AXI-core is busy (pending AXI write or read requests). The XSPI component can handle up to 4 pending reqeusts. It will answer them in order. There is a round-robin arbitration between read and write requests.
Pending AXI read request: A read burst was accepted (on the read address channel) and not all beats of this burst were transferred from the XSPI component to the AXI master.
Pending AXI write request: Not all beats of the burst were transferred from AXI master to the XSPI component (NOT the external device!).
AXI requests will be replied to with a SLV_ERROR response if the XSPI component is not enabled (CR.xspi_en) and operating in memory mapped mode (CR.xspi_mode).
Furthermore, AXI write requests to a chip select domain (0 or 1) will be answered with SLV_ERROR response if MMCR0.tx_enable, MMCR0.tx_enable are disabled.
For performance reasons, AXI write requests will be answered with OKAY after the last beat was transferred to the SYS TX FIFO.
If the XSPI component is turned off (CR.xspi_en), the mode is changed (CR.xspi_mode) or the transfer of the data
to the external device fails (damaged external device), then the request was erroneously answered with OKAY.
1 io_fifo_controller_busy
The IO FIFO controller is busy while transferring data from the SYS TX FIFO to the IO TX FIFO / filling the IO TX FIFO
or while data is transferred from the IO RX FIFO to the SYS RX FIFO.
Filling the IO TX FIFO is triggered explicitly in peripheral mode (TCR2.pm_start_transfer) or
implicitly in memory mapped mode as soon an accepted AXI request can be executed.
0 io_controller_busy
The IO controller in PIO mode or while processing a transaction to the external device.
Transaction to the external device are started as soon as the IO TX FIFO is not empty (also for RX transfers).
It stops being busy after the transfer finished automatically (TCR0/1.pm_auto_finish) or
was terminated explicitly (TCR2.end_transfer) or in case the IO TX FIFO runs empty and a stall is not possible (TCR0/1.pm_stall_possible) and the transfer should not continue (TCR0/1.pm_continue).


xspi_fsr
xSPI FIFO Status Register (FSR)
R
Address@com_xspi : 0x06400620
Address@xspi_evm : 0x40020020
Bits Name Description
31 - 22 -
 reserved
21 io_rx_fifo_empty
IO FIFO
20 io_rx_fifo_full
IO FIFO
19 io_rx_info_fifo_empty
IO FIFO
18 io_rx_info_fifo_full
IO FIFO
17 io_tx_fifo_empty
IO FIFO
16 io_tx_fifo_full
IO FIFO
15 mm_rx_info_fifo_full
AXI FIFO
14 mm_rx_info_fifo_empty
AXI FIFO
13 mm_ar_info_fifo_full
AXI FIFO
12 mm_ar_info_fifo_empty
AXI FIFO
11 mm_ax_fifo_full
AXI FIFO
10 mm_ax_fifo_empty
AXI FIFO
9 pm_rx_fifo_full
PM RX FIFO cleared together with the SYS RX FIFO
8 pm_rx_fifo_empty
PM RX FIFO cleared together with the SYS RX FIFO
7 sys_rx_fifo_overflow
SYS RX FIFO
6 sys_rx_fifo_underrun
SYS RX FIFO
5 sys_rx_fifo_full
SYS RX FIFO
4 sys_rx_fifo_empty
SYS RX FIFO
3 sys_tx_fifo_overflow
SYS TX FIFO
2 sys_tx_fifo_underrun
SYS TX FIFO
1 sys_tx_fifo_full
SYS TX FIFO
0 sys_tx_fifo_empty
SYS TX FIFO


xspi_fcr
xSPI FIFO Control Register (FCR)
R/W
0x00000000
Address@com_xspi : 0x06400624
Address@xspi_evm : 0x40020024
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
clear_axi_fifos
Clears the AXI FIFOs (MM_AX_FIFO, MM_AR_INFO_FIFO, MM_RX_INFO_FIFO).
Note: Clearing the AXI FIFOs should only be neccessary if an AXI master is no longer responsive.
Otherwise, the AXI FIFOs will run empty eventually. After clearing the AXI FIFOs,
pending AXI requests will not be responded to by the XSPI component which violates the AXI behavior.
If the XSPI component was operating in memory mapped mode, and the AXI masters are alive, it is recommended to first turn off the component (CRO.xspi_en)
while ensuring that no further AXI requests are issued to the XSPI component. Then pending AXI requests will be finished
with a SLV_ERR response and the AXI FIFOs will run empty.
clear_axi_fifos remains active while the XSPI component is busy clearing the AXI FIFOs and returns low after its done.
1 "0"
clear_sys_fifos
Clears the SYS FIFOs (SYS TX FIFO, SYS RX FIFO) and the PM RX FIFO.
Note: Clearing the SYS FIFOs while one of the components is busy leads to undefined behavior.
It is recommended to first turn off the component (CRO.xspi_en) before clearing the SYS FIFOs.
clear_sys_fifos remains active while the XSPI component is busy clearing the SYS FIFOs and returns low after its done.
0 "0"
clear_io_fifos
Clears the IO FIFOs (IO TX FIFO, IO RX INFO FIFO, IO RX FIFO) and ends the current transfer.
clear_io_fifos remains active while the XSPI component is busy clearing the IO FIFOs and returns low after its done.
Note: Setting this bit leads to the same behavior as writing the TCR2.end_transfer bit.
Note: If the IO CORE clock (clk_tx) is disabled (CLK_CR0.clk_tx_en == 0 && CLK_CR1.clk_tx_en == 0)
the fifo clear request will hang because its trying to synchronize into the clk_tx domain.


xspi_dvr0
xSPI Default Value Register 0 (DVR0)
This register must not be changed during a transfer (SR.io_controller_busy) or if CR.xspi_mode = memory mapped mode.
It defines the default drivers during dummy transfers and during different phases of a transfer (CA, IAL (ial_delay + ial), PAYLOAD) to chip select domain 0 (CSN0).
WARNING: Inproper usage might damage the external device.
R/W
0x06000000
Address@com_xspi : 0x06400628
Address@xspi_evm : 0x40020028
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
ca_en
Enable default values during the command and address phase.
ds_out, ds_oe, d_out, d_oe will be used on the bit lanes that are not used during the command and address phase.
If TCR0.ca_ds_en, ds_oe is on during command and address phase and ds_out will be set active according to TCR0.tx_ds_pol.
29 "0"
ial_delay_en
Enable default values during the IAL0/1.delay of the IAL phase.
ds_out, ds_oe, d_out, d_oe will be used on all bit lanes.
28 "0"
ial_en
Enable default values during the IAL0/1.ial of the IAL phase.
ds_out, ds_oe, d_out, d_oe will be used on all bit lanes.
27 "0"
payload_en
Enable default values during the payload phase.
ds_out, ds_oe, d_out, d_oe will be used on the bit lanes that are not used during the payload phase.
For TX transmissions: if TCR0.tx_ds_en, ds_oe is on during the payload phase and ds_out will be set according to TCR0.tx_ds_pol.
For RX transmissions: if TCR0.rx_ds_en, ds_oe is disabled during the payload phase.
26 - 25 "11"
csn_out
CSN1:CSN0 default output configuration
Only used when performing dummy transfers
0 : drive low
1 : drive high
Note: csn_oe is always enabled
24 "0"
ds_out
DS default output configuration
0 : drive low
1 : drive high
23 - 16 "00000000"
d_out
D7 (23) - D0 (16) default output configuration
0 : drive low
1 : drive high
15 - 9 0
-
 reserved
8 "0"
ds_oe
DS default output enable configuration
0 : output disabled
1 : output enabled
7 - 0 "00000000"
d_oe
D7 (7) - D0 (0) default output enable configuration
0 : output disabled
1 : output enabled


xspi_dvr1
xSPI Default Value Register 1 (DVR1)
This register must not be changed during a transfer (SR.io_controller_busy) or if CR.xspi_mode = memory mapped mode.
It defines the default drivers during dummy transfers and during different phases of a transfer (CA, IAL (ial_delay + ial), PAYLOAD) to chip select domain 0 (CSN0).
WARNING: Inproper usage might damage the external device.
R/W
0x06000000
Address@com_xspi : 0x0640062c
Address@xspi_evm : 0x4002002c
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
ca_en
Enable default values during the command and address phase.
ds_out, ds_oe, d_out, d_oe will be used on the bit lanes that are not used during the command and address phase.
If TCR1.ca_ds_en, ds_oe is on during command and address phase and ds_out will be set active according to TCR1.tx_ds_pol.
29 "0"
ial_delay_en
Enable default values during the IAL2/3.delay of the IAL phase.
ds_out, ds_oe, d_out, d_oe will be used on all bit lanes.
28 "0"
ial_en
Enable default values during the IAL2/3.ial of the IAL phase.
ds_out, ds_oe, d_out, d_oe will be used on all bit lanes.
27 "0"
payload_en
Enable default values during the payload phase.
ds_out, ds_oe, d_out, d_oe will be used on the bit lanes that are not used during the payload phase.
For TX transmissions: if TCR1.tx_ds_en, ds_oe is on during the payload phase and ds_out will be set according to TCR1.tx_ds_pol.
For RX transmissions: if TCR1.rx_ds_en, ds_oe is disabled during the payload phase.
26 - 25 "11"
csn_out
CSN1:CSN0 default output configuration
0 : drive low
1 : drive high
Note: csn_oe is always enabled, value only used for dummy transfers.
24 "0"
ds_out
DS default output configuration
0 : drive low
1 : drive high
23 - 16 "00000000"
d_out
D7 (23) - D0 (16) default output configuration
0 : drive low
1 : drive high
15 - 9 0
-
 reserved
8 "0"
ds_oe
DS default output enable configuration
0 : output disabled
1 : output enabled
7 - 0 "00000000"
d_oe
D7 (7) - D0 (0) default output enable configuration
0 : output disabled
1 : output enabled


xspi_tcr0
xSPI Transfer Control Register 0 (TCR0)
This register must not be changed during a transfer (SR.io_controller_busy) or if CR.xspi_mode = memory mapped mode.
It configures the transactions to chip select domain 0 (CSN0). TCR1 is a duplicate used for CSN1.
R/W
0x00002220
Address@com_xspi : 0x06400630
Address@xspi_evm : 0x40020030
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
rx_additional_edge
Some external memories send an additional posedge after on DS if rx_ds_en.
29 "0"
rx_sdr_edge
Determines if the incoming RX data is sampled on the posedge or negedge of clk_rx
0 : posedge
0 : negedge
28 "0"
ca_ds_en
If set the data strobe will be used during the command and address phase.
WARNING: Inproper usage might damage the external device.
         Command and address Bytes might be transmitted while the external device sends signals on DS (IALR0.dynamic).
27 - 26 "00"
switch_off_delay
Configures the number half clock cycles that CSN0 will remain low after the last falling xspi_clk edge
00 : CSN0 high directly after the last xspi_clk cycle
01 : CSN0 low half xspi_clk cycle longer
10 : CSN0 low one  xspi_clk cycle longer
11 : CSN0 low one and a half xspi_clk cycle longer
25 - 24 "00"
switch_on_delay
Configures the number half clock cycles that CSN0 will switch to low before the first rising xspi_clk edge
00 : CSN0 low directly with the first xspi_clk edge
01 : CSN0 low half xspi_clk cycle earlier
10 : CSN0 low one  xspi_clk cycle earlier
11 : CSN0 low one and a half xspi_clk cycle earlier
23 0
-
 reserved
22 - 20 "000"
address_bytes_used
Configures the number of address bytes used in peripheral mode
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
Note: The address for one CSN area must be completely transmitted before writing the address to the other CSN area.
Note: In peripheral mode it must be configured before the address register (csn1_ar_1s, csn1_ar_1d, ..) are written to transmit an address.
In memory mapped mode the address phase can be turned off resulting in no address bytes being transferred.
19 - 18 0
-
 reserved
17 "0"
pm_continue
If not set, a TX transfer is interrupted when the SYS TX FIFO underruns, an RX transfer when the SYS RX FIFO overflows and.
a Full Duplex Transfer in both cases.
Note: Only respected in Peripheral Mode.
      pm_continue can be used to initiate large areas of the external device with a default value.
      Therefore, TLR and command and address are configured as usual but no payload bytes are written into the SYS TX FIFO.
      pm_stall_possible is low and pm_continue is high. Then TLR bytes are sent and the DVR1 determines the data and data strobe.
16 "0"
pm_stall_possible
If not set, a transfer can not stop the clock while CSN1 is low.
If the SYS TX FIFO runs empty (TX transfer) or SYS RX FIFO gets full (RX transfer) or one of the two (FD transfer) and pm_stall_possible,
CSN1 is held low and the external xspi_clk is held low until the stalling condition is resolved.
If a stall is not possible a fifo underrun or overflow error will be provoked and depending on pm_continue, the transfer continues
In case of a TX or FD transfer with a SYS TX FIFO underrun, the output pins are driven with the values from the DVR1 register.
15 - 14 0
-
 reserved
13 "1"
tx_ds_pol
Sets the polarity of the data strobe signal.
0 : active high
1 : active low
NOTE: The tx_ds_pol mask is not applied to the DVR0.ds_out value.
12 "0"
tx_ds_en
Enable data strobe signal during data transmission, otherwise the DS output is disabled.
11 - 8 "0010"
rx_ds_off_delay
Delays the disabling of rx_ds_en in relation to the last clk_tx cycle.
The rx_ds_off_delay value determines how many clk_tx cycles after the last clk_tx cycle of the RX transfer,
DS is no longer used as internal clk_rx. Necessary to avoid collision with the dynamic ial repeat sensing which is done during the beginning of the IAL on the DS signal.
7 - 4 "0010"
rx_ds_on_delay
Delays the use of DS as internal clk_rx in relation to the end of the IAL phase.
The rx_ds_on_delay value determines how many cycles before finishing the IAL phase, the DS input
is used as internal clk_rx. Necessary to avoid collision with the dynamic ial repeat sensing which is done during the beginning of the IAL on the DS signal.
3 "0"
rx_ds_en
Configures if input of DS or the loopback clk is used to capture receive data as clk_rx
0 : loopback clock is used
1 : DS is used
2 "0"
rx_ddr
Configures the data rate used while receiving data from the external device in periphal mode
0 : Single data rate
1 : Double data rate
1 - 0 "00"
rx_bit_width
Configures the number of IOs used while receiving data from the external device in periphal mode
Number of IOs used = 2rx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8


xspi_tcr1
xSPI Transfer Control Register 1 (TCR1)
This register must not be changed during a transfer (bit 'busy' of register 'SR' is '1') or if CR.xspi_mode = memory mapped mode.
It configures the transactions to the chip select domain 1 (CSN1). TCR0 is a duplicate used for CSN0.
R/W
0x05002220
Address@com_xspi : 0x06400634
Address@xspi_evm : 0x40020034
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
rx_additional_edge
Some external memories send an additional posedge after on DS if rx_ds_en.
29 "0"
rx_sdr_edge
Determines if the incoming RX data is sampled on the posedge or negedge of clk_rx
0 : posedge
0 : negedge
28 "0"
ca_ds_en
If set the data strobe will be used during the command and address phase.
WARNING: Inproper usage might damage the external device.
         Command and address Bytes might be transmitted while the external device sends signals on DS (IALR1.dynamic).
27 - 26 "01"
switch_off_delay
Configures the number half clock cycles that CSN1 will remain low after the last falling xspi_clk edge
00 : CSN1 high directly after the last xspi_clk cycle
01 : CSN1 low half xspi_clk cycle longer
10 : CSN1 low one  xspi_clk cycle longer
11 : CSN1 low one and a half xspi_clk cycle longer
25 - 24 "01"
switch_on_delay
Configures the number half clock cycles that CSN1 will switch to low before the first rising xspi_clk edge
00 : CSN1 low directly with the first xspi_clk edge
01 : CSN1 low half xspi_clk cycle earlier
10 : CSN1 low one  xspi_clk cycle earlier
11 : CSN1 low one and a half xspi_clk cycle earlier
23 0
-
 reserved
22 - 20 "000"
address_bytes_used
Configures the number of address bytes used in peripheral mode.
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
Note: The address for one CSN area must be completely transmitted before writing the address to the other CSN area.
Note: In peripheral mode it must be configured before the address register (csn1_ar_1s, csn1_ar_1d, ..) are written to transmit an address.
In memory mapped mode the address phase can be turned off resulting in no address bytes being transferred.
19 - 18 0
-
 reserved
17 "0"
pm_continue
If not set, a TX transfer is interrupted when the SYS TX FIFO underruns, an RX transfer when the SYS RX FIFO overflows and.
a Full Duplex Transfer in both cases.
Note: Only respected in Peripheral Mode.
      pm_continue can be used to initiate large areas of the external device with a default value.
      Therefore, TLR and command and address are configured as usual but no payload bytes are written into the SYS TX FIFO.
      pm_stall_possible is low and pm_continue is high. Then TLR bytes are sent and the DVR1 determines the data and data strobe.
16 "0"
pm_stall_possible
If not set, a transfer can not stop the clock while CSN1 is low.
If the SYS TX FIFO runs empty (TX transfer) or SYS RX FIFO gets full (RX transfer) or one of the two (FD transfer) and pm_stall_possible,
CSN1 is held low and the external xspi_clk is held low until the stalling condition is resolved.
If a stall is not possible a fifo underrun or overflow error will be provoked and depending on pm_continue, the transfer continues
In case of a TX or FD transfer with a SYS TX FIFO underrun, the output pins are driven with the values from the DVR1 register.
15 - 14 0
-
 reserved
13 "1"
tx_ds_pol
Sets the polarity of the data strobe signal.
0 : active high
1 : active low
NOTE: The tx_ds_pol mask is not applied to the DVR0.ds_out value.
12 "0"
tx_ds_en
Enable data strobe signal during data transmission, otherwise the DS output is disabled.
11 - 8 "0010"
rx_ds_off_delay
Delays the disabling of rx_ds_en in relation to the last clk_tx cycle.
The rx_ds_off_delay value determines how many clk_tx cycles after the last clk_tx cycle of the RX transfer,
DS is no longer used as internal clk_rx. Necessary to avoid collision with the dynamic ial repeat sensing which is done during the beginning of the IAL on the DS signal.
7 - 4 "0010"
rx_ds_on_delay
Delays the use of DS as internal clk_rx in relation to the end of the IAL phase.
The rx_ds_on_delay value determines how many cycles before finishing the IAL phase, the DS input
is used as internal clk_rx. Necessary to avoid collision with the dynamic ial repeat sensing which is done during the beginning of the IAL on the DS signal.
3 "0"
rx_ds_en
Configures if input of DS or the loopback clk is used to capture receive data as clk_rx
0 : loopback clock is used
1 : DS is used
2 "0"
rx_ddr
Configures the data rate used while receiving data from the external device in periphal mode
0 : Single data rate
1 : Double data rate
1 - 0 "00"
rx_bit_width
Configures the number of IOs used while receiving data from the external device in periphal mode
Number of IOs used = 2rx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8


xspi_tcr2
xSPI Transfer Control Register 2 (TCR2)
R/W
0x00000030
Address@com_xspi : 0x06400638
Address@xspi_evm : 0x40020038
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
pm_rx_capture_all
If set, rx data is also sampled during command, address, and IAL phase.
Enable pm_continue and disable pm_stall_possible and rx_ds_en when using rx_capture all.
Note: May only be used for debug purposes in peripheral mode and only be changed if the XSPI is idle.
20 "0"
pm_csn_idx
Determines which CSN will be used for the transfer.
0 : CSN0
1 : CSN1
Note: For dummy transfers, the values of the DVRs determine the state of CSN0 and CSN1.
      In pio mode, the values of the pio register determine the state of CSN0 and CSN1.
19 - 17 0
-
 reserved
16 "0"
pm_skip_ial
Skip the initial access latency phase
If this bit is set the IAL phase is skipped
regardless of the IALR0/1.ial / IALR0/1.delay configuration.
15 - 13 0
-
 reserved
12 - 8 "00000"
pm_ca_length
Length of the command and address phase in bytes for transfers in peripheral mode
Configuration of 0 - 31 command/address bytes possible.
The transmission fifos must be filled accordingly.
Command Address Bytes must not be mixed with payload bytes.
Note: If the command address bytes are sent in 8d mode, an even number of bytes must be written to the FIFOs
7 - 6 0
-
 reserved
5 - 4 "11"
pm_transfer_type
Transfer type selection
Default is '11' for standard SPI compatibility.
00:

IOs are driven by DVR0/1 depending on pm_csn_idx.
xspi_clk frequency determined by CR1.clk_tx_csn0/1 config depending on pm_csn_idx.
If pm_auto_finish, transfer finishes automatically after TLR.transfer_length clock cycles.
If pm_auto_finish, transfer does not finish until explicitly stopped (end_transfer).
01: receive
Receives TLR.transfer_length bytes.
10: transmit
Transmits TLR.transfer_length bytes.
11:
full-duplex
Standard Motorola SPI mode only (1S-1S-1S).
The full-duplex standard Motorola SPI mode always transmits and receives data.
Note: If the transfer only consists command and address cycles (no payload) pm_transfer_type must be transmit.
3 "0"
end_transfer
Transfer end signal.
Writable, but can also be changed by hardware. Ends the current transfer and clears the IO FIFOs (IO TX FIFO, IO RX INFO FIFO, IO RX FIFO). The signal remains active while the XSPI component is busy clearing the IO_FIFOs and returns low after its done.
It also switches the XSPI into the peripheral mode (CR.xspi_mode).
Note: If the IO CORE clock (clk_tx) is disabled (CLK_CR0.clk_tx_en == 0 && CLK_CR1.clk_tx_en == 0)
the fifo clear request will hang because its trying to synchronize into the clk_tx domain.
2 0
-
 reserved
1 "0"
pm_auto_finish
Configures the terminating condition for transfers in peripheral mode.
0 : Transfer terminates after the end_transfer bit was written.
1 : Transfer terminates after TLR.transfer_length bytes.
Note: After starting the PIO mode (CR.xspi_mode) with pm_start_transfer it can only be stopped by end_transfer.
0 "0"
pm_start_transfer
Transfer start signal
Starts the transfer or the PIO mode.
The hardware will automatically reset this bit. This bit is always '0' when read. This bit is writable only after a transfer sequence is finished.


xspi_tlr
xSPI Transfer Length Register (TLR)
This register must not be changed during a transfer (SR.io_controller_busy).
R/W
0x00000000
Address@com_xspi : 0x0640063c
Address@xspi_evm : 0x4002003c
Bits Reset value Name Description
31 - 0 0x0
transfer_length
Number of payload bytes (excluding command / address bytes) to be send / received or number of dummy clock cycles.
0x0000_0000: No payload bytes are to be transferred.
0x0000_0001: 1 payload byte is to be transferred.
 ...
0xFFFF_FFFE: 4,294,967,294 (4G-2) payload bytes are to be transferred
0xFFFF_FFFF: 4,294,967,295 (4G-1) payload bytes are to be transferred


xspi_ial0
xSPI Initial Access Latency Register 0 (IALR0)
Configures the IAL for chip select domain 0.
In peripheral mode, the IAL can be reconfigured between transactions.
In memory mapped mode, this register configures the IAL for TX transactions to chip select domain 0.
(delay + ial)/2 clock cycles will be waited before the payload phase of the transaction begins.
During this waiting time, command and address bytes will be sent to the external device.
delay + ial must be even so that the payload phase begins with a rising clock edge, if it is odd the result will be rounded down.
Only ial will be repeated during dynamic IAL repeat.
W
0x06000000
Address@com_xspi : 0x06400640
Address@xspi_evm : 0x40020040
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 26 "01"
ds_sample_delay
Delays the window in which ds is sampled to check if the IAL needs to be repeated if dynamic is set.
In the default setting, DS is sampled on the 2nd negedge and evaluated on the third posedge of the internal clk_tx after starting the transfer.
25 "1"
ds_pol
Sets the polarity of the data strobe signal to be sesed for dynamic IAL repeat during the IAL phase.
0 : active high, repeat ial if DS is high in the ds sample window (configured by ds_sample_delay)
1 : active low, repeat ial if DS is low in the ds sample window (configured by ds_sample_delay)
24 "0"
dynamic
Dynamic repeat of IAL if ds sensed (DS ^ ds_pol) during the ds sample window
To be able to sense the DS signal and repeat the IAL, a minimum of 3 IAL cycles ial + delay >= 6 must be configured.
0 : Off
1 : On
23 - 16 "00000000"
delay
IAL delay in half-cycles measured from the start of the transmission.
15 - 0 0x0
ial
Initial Access Latency (IAL) in half-cycles


xspi_ial1
xSPI Initial Access Latency Register 1 (IALR1)
Configures the IAL for chip select domain 1.
In peripheral mode, the IAL can be reconfigured between transactions.
In memory mapped mode, this register configures the IAL for TX transactions to chip select domain 1.
(delay + ial)/2 clock cycles will be waited before the payload phase of the transaction begins.
During this waiting time, command and address bytes will be sent to the external device.
delay + ial must be even so that the payload phase begins with a rising clock edge, if it is odd the result will be rounded down.
Only ial will be repeated during dynamic IAL repeat.
W
0x06000000
Address@com_xspi : 0x06400644
Address@xspi_evm : 0x40020044
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 26 "01"
ds_sample_delay
Delays the window in which ds is sampled to check if the IAL needs to be repeated if dynamic is set.
In the default setting, DS is sampled on the 2nd negedge and evaluated on the third posedge of the internal clk_tx after starting the transfer.
25 "1"
ds_pol
Sets the polarity of the data strobe signal to be sesed for dynamic IAL repeat during the IAL phase.
0 : active high, repeat ial if DS is high in the ds sample window (configured by ds_sample_delay)
1 : active low, repeat ial if DS is low in the ds sample window (configured by ds_sample_delay)
24 "0"
dynamic
Dynamic repeat of IAL if ds sensed (DS ^ ds_pol) during the ds sample window
To be able to sense the DS signal and repeat the IAL, a minimum of 3 IAL cycles ial + delay >= 6 must be configured.
0 : Off
1 : On
23 - 16 "00000000"
delay
IAL delay in half-cycles measured from the start of the transmission.
15 - 0 0x0
ial
Initial Access Latency (IAL) in half-cycles


xspi_ial2
xSPI Initial Access Latency Register 2 (IALR2)
In memory mapped mode, this register configures the IAL for RX transactions to chip select domain 0.
(delay + ial)/2 clock cycles will be waited before the payload phase of the transaction begins.
During this waiting time, command and address bytes will be sent to the external device.
delay + ial must be even so that the payload phase begins with a rising clock edge, if it is odd the result will be rounded down.
Only ial will be repeated during dynamic IAL repeat.
W
0x00000000
Address@com_xspi : 0x06400648
Address@xspi_evm : 0x40020048
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000000"
delay
IAL delay in half-cycles measured from the start of the transmission.
15 - 0 0x0
ial
Initial Access Latency (IAL) in half-cycles


xspi_ial3
xSPI Initial Access Latency Register 3 (IALR3)
In memory mapped mode, this register configures the IAL for RX transactions to chip select domain 1.
In peripheral mode the IAL can be reconfigured between transactions.
(delay + ial)/2 clock cycles will be waited before the payload phase of the transaction begins.
During this waiting time, command and address bytes will be sent to the external device.
Only ial will be repeated during dynamic IAL repeat.
W
0x00000000
Address@com_xspi : 0x0640064c
Address@xspi_evm : 0x4002004c
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000000"
delay
IAL delay in half-cycles measured from the start of the transmission.
15 - 0 0x0
ial
Initial Access Latency (IAL) in half-cycles


xspi_mm_wcr0
xSPI Memory mapped Write Command Register 0 (MMWCR0).
This register must not be changed if CR.xspi_mode = memory mapped mode.
Holds the command that is being used during memory mapped write transactions to chip select domain 0.
The number of bytes used of this command is determined by write_command_length of the Memory mapped Config Register (MMCR1).
Note that for hyperbus or similar protocols, 6 address bytes should be configured MMCR1.tx_address_bytes_used
and the address scrambling feature (CSN0_ABx_CRy) should be used to toggle the bit for read and write transactions.
R/W
0x00000000
Address@com_xspi : 0x06400650
Address@xspi_evm : 0x40020050
Bits Reset value Name Description
31 - 0 0x0
write_command
write command


xspi_mm_wcr1
xSPI Memory mapped Write Command Register 1 (MMWCR1).
This register must not be changed if CR.xspi_mode = memory mapped mode.
Holds the command that is being used during memory mapped write transactions to chip select domain 1.
The number of bytes used of this command is determined by write_command_length of the Memory mapped Config Register (MMCR3).
Note that for hyperbus or similar protocols, 6 address bytes should be configured MMCR3.tx_address_bytes_used
and the address scrambling feature (CSN1_ABx_CRy) should be used to toggle the bit for read and write transactions.
R/W
0x00000000
Address@com_xspi : 0x06400654
Address@xspi_evm : 0x40020054
Bits Reset value Name Description
31 - 0 0x0
write_command
write command


xspi_mm_rcr0
xSPI Memory mapped Read Command Register 0 (MMRCR0).
This register must not be changed if CR.xspi_mode = memory mapped mode.
Holds the command that is being used during memory mapped read transactions to chip select domain 0.
The number of bytes used of this command is determined by mm_read_command_length of the Memory mapped Config Register (MMCR1).
Note that for hyperbus or similar protocols, 6 address bytes should be configured MMCR1.rx_address_bytes_used
and the address scrambling feature (CSN0_ABx_CRy) should be used to toggle the bit for read and write transactions.
R/W
0x00000000
Address@com_xspi : 0x06400658
Address@xspi_evm : 0x40020058
Bits Reset value Name Description
31 - 0 0x0
read_command
write command


xspi_mm_rcr1
xSPI Memory mapped Read Command Register 0 (MMRCR0).
This register must not be changed if CR.xspi_mode = memory mapped mode.
Holds the command that is being used during memory mapped read transactions to chip select domain 1.
The number of bytes used of this command is determined by mm_read_command_length of the Memory mapped Config Register (MMCR3).
Note that for hyperbus or similar protocols, 6 address bytes should be configured MMCR3.rx_address_bytes_used
and the address scrambling feature (CSN1_ABx_CRy) should be used to toggle the bit for read and write transactions.
R/W
0x00000000
Address@com_xspi : 0x0640065c
Address@xspi_evm : 0x4002005c
Bits Reset value Name Description
31 - 0 0x0
read_command
write command


xspi_mm_cr0
xSPI Memory mapped Configuration Register (MMCR0).
Configures the Memory mapped transfers to chip select domain 0.
This register must not be changed if CR.xspi_mode = memory mapped mode.
The IAL phase is configured by the IALR0 and IALR2.
Further configuration e.g. the bit width and data rate for RX in memory mapped mode are configured by TCR0.
The payload phase for memory mapped RX and TX transactions is not optional and comes after the optional command and address phase.
R/W
0x00000404
Address@com_xspi : 0x06400660
Address@xspi_evm : 0x40020060
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
tx_skip_ial
Skip the IAL for memory mapped TX transactions.
29 "0"
rx_skip_ial
Skip the ial for memory mapped RX transactions.
28 "0"
tx_enable
Enable memory mapped write transactions to chip select domain 0.
0 : Memory mapped writes on chip select domain 0 are disabled
1 : Memory mapped writes on chip select domain 0 are enabled
27 - 26 0
-
 reserved
25 - 24 "00"
memory_word_size
Memory word size of the external device.
Defines the address granularity for the memory mapped mode.
Incoming AXI transfers will be adjusted accordingly, which requires data strobe support from the external memory.
Only neccessary if AXI transfers with smaller granularity than the external memory can occur.
The connected AXI bus must be as least as wide as the addressed memory.
00: Byte
01: 2 Bytes
10: 4 Bytes
11: Reserved
23 - 19 0
-
 reserved
18 - 17 "00"
page_size
Page size of the external device connected to CSN0.
If the XSPI module is operating in memory mapped mode, AXI transfers that exceed the page size will be split.
00 : 256 Bytes
01 : 512 Bytes
10 : 1024 Bytes
11 : 2048 Bytes
Note : AXI4 transfers do not cross 4096 Byte boundaries, therefore no additional configuration required.
16 "0"
page_size_en
Enable the page size constraints in memory mapped mode for the external device connected to CSN0.
15 - 12 0
-
 reserved
11 "0"
rx_address_phase_off
Configures the address phase during memory mapped RX transactions.
0: On
1: Off
10 "1"
rx_address_phase_position
Configures the position of the address phase during memory mapped RX transactions.
0: First
1: Second
9 "0"
rx_command_phase_off
Configures the the command phase during memory mapped RX transactions.
0: On
1: Off
8 "0"
rx_command_phase_position
Configures the position of the command phase during memory mapped RX transactions.
0: First
1: Second
7 - 4 0
-
 reserved
3 "0"
tx_address_phase_off
Configures the address phase during memory mapped TX transactions.
0: On
1: Off
2 "1"
tx_address_phase_position
Configures the position of the address phase during memory mapped TX transactions.
00: First
01: Second
1 "0"
tx_command_phase_off
Configures the command phase during memory mapped TX transactions.
0: On
1: Off
0 "0"
tx_command_phase_position
Configures the position of the command phase during memory mapped TX transactions.
00: First
01: Second


xspi_mm_cr1
xSPI Memory mapped Configuration Register (MMCR1).
Configures the memory mapped transfers to chip select domain 0.
This register must not be changed if CR.xspi_mode = memory mapped mode.
The IAL phase is configured by the IALR0 and IALR2.
Further configuration e.g. the bit width and data rate for RX in memory mapped mode are configured by TCR0.
R/W
0x00000033
Address@com_xspi : 0x06400664
Address@xspi_evm : 0x40020064
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
data_tx_ddr
Configures the data rate used while sending the data to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
29 - 28 "00"
data_tx_bit_width
Configures the number of IOs used while sending the data to the external device in memory mapped mode
Number of IOs used = 2data_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
27 - 26 0
-
 reserved
25 - 24 "00"
rx_address_tx_bit_width
Configures the number of IOs used while sending the address to the external device for memory mapped RX transactions
Number of IOs used = 2rx_address_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
23 "0"
rx_address_tx_ddr
Configures the data rate used while sending the address to the external device for memory mapped RX transactions
0 : Single Data Rate
1 : Double Data Rate
22 - 20 "000"
rx_address_bytes_used
Configures the number of address bytes used for memory mapped RX transactions
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
19 - 18 0
-
 reserved
17 - 16 "00"
tx_address_tx_bit_width
Configures the number of IOs used while sending the address to the external device for memory mapped TX transactions
Number of IOs used = 2tx_address_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
15 "0"
tx_address_tx_ddr
Configures the data rate used while sending the address to the external device for memory mapped TX transactions
0 : Single Data Rate
1 : Double Data Rate
14 - 12 "000"
tx_address_bytes_used
Configures the number of address bytes used for memory mapped TX transactions
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
11 "0"
read_command_fd
Read command is a full-duplex command
Note : True full duplex where the external device writes the data while outputting the read data is not possible in memory mapped mode.
10 "0"
write_command_fd
Write command is a full-duplex command
Note : True full duplex where the external device writes the data while outputting the read data is not possible in memory mapped mode.
9 "0"
read_command_tx_ddr
Configures the data rate used while sending the read command to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
8 "0"
write_command_tx_ddr
Configures the data rate used while sending the write command to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
7 - 6 "00"
read_command_tx_bit_width
Configures the number of IOs used while sending the read command to the external device in memory mapped mode
Number of IOs used = 2read_command_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
5 - 4 "11"
read_command_length
Read command length in bytes
Indicates the number of valid bytes of the mm_read_command_register (MMRCR0).
Command length = value + 1
3 - 2 "00"
write_command_tx_bit_width
Configures the number of IOs used while sending the write command to the external device in memory mapped mode
Number of IOs used = 2write_command_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
1 - 0 "11"
write_command_length
Write command length in bytes
Indicates the number of valid bytes of the mm_write_command_register (MMWCR0).
Command length = value + 1


xspi_mm_cr2
xSPI Memory mapped Configuration Register (MMCR2).
Configures the memory mapped transfers to chip select domain 1.
This register must not be changed if CR.xspi_mode = memory mapped mode.
The IAL phase is configured by the IALR1 and IALR3.
Further configuration e.g. the bit width and data rate for RX in memory mapped mode are configured by TCR1.
The payload phase for memory mapped RX and TX transactions is not optional and comes after the optional command and address phase.
R/W
0x00000404
Address@com_xspi : 0x06400668
Address@xspi_evm : 0x40020068
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
tx_skip_ial
Skip the IAL for memory mapped TX transactions.
29 "0"
rx_skip_ial
Skip the ial for memory mapped RX transactions.
28 "0"
tx_enable
Enable memory mapped write transactions to chip select domain 1.
0 : Memory mapped writes on chip select domain 1 are disabled
1 : Memory mapped writes on chip select domain 1 are enabled
27 - 26 0
-
 reserved
25 - 24 "00"
memory_word_size
Memory word size of the external device
Defines the address granularity for the memory mapped mode.
Incoming AXI transfers will be adjusted accordingly, which requires data strobe support from the external memory.
Only neccessary if AXI transfers with smaller granularity than the external memory can occur.
The connected AXI bus must be as least as wide as the addressed memory.
00: Byte
01: 2 Bytes
10: 4 Bytes
11: Reserved
23 - 19 0
-
 reserved
18 - 17 "00"
page_size
Page size of the external device connected to CSN0.
If the XSPI module is operating in memory mapped mode, AXI transfers that exceed the page size will be split.
00 : 256 Bytes
01 : 512 Bytes
10 : 1024 Bytes
11 : 2048 Bytes
Note : AXI4 transfers do not cross 4096 Byte boundaries, therefore no additional configuration required.
16 "0"
page_size_en
Enable the page size constraints in memory mapped mode for the external device connected to CSN0.
15 - 12 0
-
 reserved
11 "0"
rx_address_phase_off
Configures the address phase during memory mapped RX transactions.
0: On
1: Off
10 "1"
rx_address_phase_position
Configures the position of the address phase during memory mapped RX transactions.
0: First
1: Second
9 "0"
rx_command_phase_off
Configures the the command phase during memory mapped RX transactions.
0: On
1: Off
8 "0"
rx_command_phase_position
Configures the position of the command phase during memory mapped RX transactions.
0: First
1: Second
7 - 4 0
-
 reserved
3 "0"
tx_address_phase_off
Configures the address phase during memory mapped TX transactions.
0: On
1: Off
2 "1"
tx_address_phase_position
Configures the position of the address phase during memory mapped TX transactions.
00: First
01: Second
1 "0"
tx_command_phase_off
Configures the command phase during memory mapped TX transactions.
0: On
1: Off
0 "0"
tx_command_phase_position
Configures the position of the command phase during memory mapped TX transactions.
00: First
01: Second


xspi_mm_cr3
xSPI Memory mapped Configuration Register (MMCR3).
Configures the memory mapped transfers to chip select domain 1.
This register must not be changed if CR.xspi_mode = memory mapped mode.
The IAL phase is configured by the IALR1 and IALR3.
Further configuration e.g. the bit width and data rate for RX in memory mapped mode are configured by TCR1.
R/W
0x00000033
Address@com_xspi : 0x0640066c
Address@xspi_evm : 0x4002006c
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
data_tx_ddr
Configures the data rate used while sending the data to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
29 - 28 "00"
data_tx_bit_width
Configures the number of IOs used while sending the data to the external device in memory mapped mode
Number of IOs used = 2data_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
27 - 26 0
-
 reserved
25 - 24 "00"
rx_address_tx_bit_width
Configures the number of IOs used while sending the address to the external device for memory mapped RX transactions
Number of IOs used = 2rx_address_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
23 "0"
rx_address_tx_ddr
Configures the data rate used while sending the address to the external device for memory mapped RX transactions
0 : Single Data Rate
1 : Double Data Rate
22 - 20 "000"
rx_address_bytes_used
Configures the number of address bytes used for memory mapped RX transactions
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
19 - 18 0
-
 reserved
17 - 16 "00"
tx_address_tx_bit_width
Configures the number of IOs used while sending the address to the external device for memory mapped TX transactions
Number of IOs used = 2tx_address_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
15 "0"
tx_address_tx_ddr
Configures the data rate used while sending the address to the external device for memory mapped TX transactions
0 : Single Data Rate
1 : Double Data Rate
14 - 12 "000"
tx_address_bytes_used
Configures the number of address bytes used for memory mapped TX transactions
Number of address bytes used = value + 1
000 : 1
...
101 : 6
110 : reserved
...
111 : reserved
11 "0"
read_command_fd
Read command is a full-duplex command
Note : True full duplex where the external device writes the data while outputting the read data is not possible in memory mapped mode.
10 "0"
write_command_fd
Write command is a full-duplex command
Note : True full duplex where the external device writes the data while outputting the read data is not possible in memory mapped mode.
9 "0"
read_command_tx_ddr
Configures the data rate used while sending the read command to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
8 "0"
write_command_tx_ddr
Configures the data rate used while sending the write command to the external device in memory mapped mode
0 : Single Data Rate
1 : Double Data Rate
7 - 6 "00"
read_command_tx_bit_width
Configures the number of IOs used while sending the read command to the external device in memory mapped mode
Number of IOs used = 2read_command_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
5 - 4 "11"
read_command_length
Read command length in bytes
Indicates the number of valid bytes of the mm_read_command_register (MMRCR1).
Command length = value + 1
3 - 2 "00"
write_command_tx_bit_width
Configures the number of IOs used while sending the write command to the external device in memory mapped mode
Number of IOs used = 2write_command_tx_bit_width
00 : 1
01 : 2
10 : 4
11 : 8
1 - 0 "11"
write_command_length
Write command length in bytes
Indicates the number of valid bytes of the mm_write_command_register (MMWCR1).
Command length = value + 1


xspi_mhc0
xSPI Minimum High Cyles 0 (MHC0)
Configures the minimum number of cycles to wait before starting the next transaction after a finished transfer to chip select domain 0.
Is only respected if the XSPI controller is operating in memory mapped mode (CR.xspi_mode).
If the next transfer targets the same chip select domain (0), CSN0 stays high for (n+1) x clk_tx_csn0 cycles,
with n = tx_intra_csn_min_high_cycles, if the previous transfer was a TX transfer or n = rx_intra_csn_min_high_cycles, if the previous transfer was a RX transfer.
If the next transfer targets the other chip select domain (1), CSN1 will become active (low) after (n+1) x clk_tx_csn0 cycles,
with n = tx_inter_csn_min_high_cycles, if the previous transfer was a TX transfer or n = rx_intra_csn_min_high_cycles, if the previous transfer was a RX transfer.
Follow up transfers that target the same chip select domain:
RX transfers may be started after the last clk cycle was looped back.
TX transfers may be started after the last clk cycle was send.
Follow up transfers that target a different chip select domain: DLL may be reconfigured
RX transfers may be started after the last clk cycle was looped back and passed its slave DLL.
TX transfers may be started after the last clk cycle was send and passed its slave DLL.
Transfers that change the chip select domain require to reconfigure the slave DLLs. Therefore, extra cycles are required.
R/W
0x00001031
Address@com_xspi : 0x06400670
Address@xspi_evm : 0x40020070
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 12 "0001"
tx_inter_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 1 after a TX transfer to chip select domain 0
CSMHT+1 is the minimum number of clk_tx_csn0 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after a TX transfer to
the external device at chip select domain 0 if the next transfer targets chip select domain 1. (clk_tx needs time to pass its DLL because the DLL value might change).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.
11 - 8 "0000"
tx_intra_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 0 after a TX transfer to chip select domain 0
CSMHT+1 is the minimum number of clk_tx_csn0 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after a TX transfer to
the external device at chip select domain 0 if the next transfer targets chip select domain 0.
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.
7 - 4 "0011"
rx_inter_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 1 after an RX transfer to chip select domain 0
CSMHT+1 is the minimum number of clk_tx_csn0 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after an RX transfer to
the external device at chip select domain 0 if the next transfer targets chip select domain 1. (clk_rx need time to loop back and pass its DLL because the DLL value might change).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay, if the last transfer was an RX transfer.
3 - 0 "0001"
rx_intra_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 0 after an RX transfer to chip select domain 0
CSMHT+1 is the minimum number of clk_tx_csn0 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after an RX transfer to
the external device at chip select domain 0 if the next transfer targets chip select domain 0. (clk_rx needs time to loop back).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.


xspi_mhc1
xSPI Minimum High Cyles 1 (MHC1)
Configures the minimum number of cycles to wait before starting the next transaction after a finished transfer to chip select domain 1.
Is only respected if the XSPI controller is operating in memory mapped mode (CR.xspi_mode).
If the next transfer targets the same chip select domain (1), CSN1 stays high for (n+1) x clk_tx_csn1 cycles,
with n = tx_intra_csn_min_high_cycles, if the previous transfer was a TX transfer or n = rx_intra_csn_min_high_cycles, if the previous transfer was a RX transfer.
If the next transfer targets the other chip select domain (0), CSN0 will become active (low) after (n+1) x clk_tx_csn1 cycles,
with n = tx_inter_csn_min_high_cycles, if the previous transfer was a TX transfer or n = rx_intra_csn_min_high_cycles, if the previous transfer was a RX transfer.
Follow up transfers that target the same chip select domain:
RX transfers may be started after the last clk cycle was looped back.
TX transfers may be started after the last clk cycle was send.
Follow up transfers that target a different chip select domain: DLL may be reconfigured
RX transfers may be started after the last clk cycle was looped back and passed its slave DLL.
TX transfers may be started after the last clk cycle was send and passed its slave DLL.
Transfers that change the chip select domain require to reconfigure the slave DLLs. Therefore, extra cycles are required.
R/W
0x00001031
Address@com_xspi : 0x06400674
Address@xspi_evm : 0x40020074
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 12 "0001"
tx_inter_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 0 after a TX transfer to chip select domain 1
CSMHT+1 is the minimum number of clk_tx_csn1 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after a TX transfer to
the external device at chip select domain 1 if the next transfer targets chip select domain 0. (clk_tx needs time to pass its DLL because the DLL value might change).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.
11 - 8 "0000"
tx_intra_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 1 after a TX transfer to chip select domain 1
CSMHT+1 is the minimum number of clk_tx_csn1 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after a TX transfer to
the external device at chip select domain 1 if the next transfer targets chip select domain 1.
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.
7 - 4 "0011"
rx_inter_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 0 after an RX transfer to chip select domain 1
CSMHT+1 is the minimum number of clk_tx_csn1 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after an RX transfer to
the external device at chip select domain 1 if the next transfer targets chip select domain 0. (clk_rx need time to loop back and pass its DLL because the DLL value might change).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay, if the last transfer was an RX transfer.
3 - 0 "0001"
rx_intra_csn_min_high_cycles
Chip Select Minimum High Time (CSMHT) for accesses to chip select domain 1 after an RX transfer to chip select domain 1
CSMHT+1 is the minimum number of clk_tx_csn1 cycles that the chip selects (CSN0 + CSN1) must remain inactive (high) after an RX transfer to
the external device at chip select domain 1 if the next transfer targets chip select domain 1. (clk_rx needs time to loop back).
NOTE: Does not consider TCR0.switch_on_delay or TCR0.switch_off_delay.


xspi_mlc0
xSPI Maximum Low Cyles 0 (MLC0)
Configures the maximum number of cycles that CSN0 may remain active (low) in clk_tx_csn0 cycles when the XSPI controller is operating in memory mapped mode (CR.xspi_mode).
In other modes this value is ignored and the programmer has to make sure that his transfers do not violate any constraints.
cs_max_low_time must be big enough so that payload data (at least 1x external memory word size) can actually be transferred without
violating chip select low time restrictions, otherwise the behavior is undefined.
cs0_switch_on_delay or cs0_switch_off_delay are not considered internally and must be taken into account when setting cs_max_low_cycles.
R/W
0x00000000
Address@com_xspi : 0x06400678
Address@xspi_evm : 0x40020078
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
csn_max_low_cycles
Chip Select Maximum Low Time
0 = off, no CSN maximum low time restrictions
cs_max_low_cycles = maximum number of cycles the chip select (CSN0) signal may remain active (low).
tCSL = (csn_max_low_cycles+1) * tPERIOD,clk_tx_csn0


xspi_mlc1
xSPI Maximum Low Cyles 1 (MLC1)
Configures the maximum number of cycles that CSN1 may remain active (low) in clk_tx_csn1 cycles when the XSPI controller is operating in memory mapped mode (CR.xspi_mode).
See xSPI Maximum Low Cyles 0 (MLC0) for more information
R/W
0x00000000
Address@com_xspi : 0x0640067c
Address@xspi_evm : 0x4002007c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
csn_max_low_cycles
Chip Select Maximum Low Time
0 = off
cs_max_low_cycles = maximum number of cycles the chip select (CSN1) signal may remain active (low).


xspi_irq_mask
xSPI interrupt mask register (IRQMR):
IRQ mask is an AND-mask: Only raw interrupts with mask bit set can generate a module IRQ to CPU.
For detailed IRQ behavior and function, see register 'xspi_irq_raw'.
R/W
0x00000000
Address@com_xspi : 0x06400680
Address@xspi_evm : 0x40020080
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
clk_rx_tx_drifted_im
Receive and transmit clock drift detected by the clock moniotor
9 "0"
clk_rx_too_fast_im
Receiving clock is faster than the sending clock
8 "0"
clk_rx_too_slow_im
Receiving clock is slower than the sending clock
7 "0"
external_im
External INTN pin interrupt mask
6 "0"
rx_fifo_overflow_im
Receive FIFO overflow interrupt mask
5 "0"
rx_fifo_underrun_im
Receive FIFO underrun interrupt mask
4 "0"
rx_fifo_nempty_im
Receive FIFO not empty interrupt mask
3 "0"
tx_fifo_overflow_im
Transmit FIFO overflow interrupt mask
2 "0"
tx_fifo_underrun_im
Transmit FIFO underrun interrupt mask
1 "0"
tx_fifo_empty_im
Transmit FIFO empty interrupt mask
0 "0"
transfer_end_im
Transfer end interrupt mask


xspi_irq_raw
xSPI interrupt state before masking register (raw interrupt).
Writing a "1" to a bit clears this interrupt.
Note that only the interrupts are cleared but not the status signals (e.g. SR.clk_rx_tx_drifted).
This means after clearing the clk_rx_tx_drifted interrupt, the interrupt can not occur again until the status was also cleared,
because the interrupt is only triggered upon a changing status.
R/W
0x00000000
Address@com_xspi : 0x06400684
Address@xspi_evm : 0x40020084
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
clk_rx_tx_drifted_is
Unmasked reiceive clock too fast interrupt state
1: Receive and transmit clock drift detected by the clock moniotor
0: No receive and transmit clock drift detected by the clock moniotor
9 "0"
clk_rx_too_fast_is
Unmasked reiceive clock too fast interrupt state
1: Receive clock too fast event occured in the clock moniotor
0: Receive clock too fast event did not occur in the clock moniotor
8 "0"
clk_rx_too_slow_is
Unmasked reiceive clock too slow interrupt state
1: Receive clock too slow event occured in the clock moniotor
0: Receive clock too slow event did not occur in the clock moniotor
7 "0"
external_is
Unmasked external interrupt state
1: INTN pin is equal to CR.intn_polarity.
0: INTN pin is not equal to CR.intn_polarity.
6 "0"
rx_fifo_overflow_is
Unmasked receive FIFO overflow interrupt state
1: Receive FIFO overflow error occurred
0: No receive FIFO overflow error occurred
5 "0"
rx_fifo_underrun_is
Unmasked receive FIFO underrun interrupt state
1: Receive FIFO underrun error occurred
0: No receive FIFO overflow error occurred
4 "0"
rx_fifo_nempty_is
Unmasked receive FIFO not empty interrupt state
1: Receive FIFO is not empty
0: Receive FIFO is empty
3 "0"
tx_fifo_overflow_is
Unmasked transmit FIFO overflow interrupt state
1: Transmit FIFO overflow error occurred
0: No transmit FIFO overflow error occurred
2 "0"
tx_fifo_underrun_is
Unmasked transmit FIFO underrun interrupt state
1: Transmit FIFO underrun error occurred
0: No transmit FIFO underrun error occurred
1 "0"
tx_fifo_empty_is
Unmasked transmit FIFO empty interrupt state
1: Transmit FIFO is full
0: Transmit FIFO is not empty
0 "0"
transfer_end_is
Unmasked transfer end interrupt state
1: Transfer finished. SR.io_controller_busy has become inactive.
0: Transfer not finished. SR.io_controller_busy is active.


xspi_irq_masked
xSPI masked interrupt status register
For detailed IRQ behavior and function, see register 'xspi_irq_raw'.
R
Address@com_xspi : 0x06400688
Address@xspi_evm : 0x40020088
Bits Name Description
31 - 11 -
 reserved
10 clk_rx_tx_drifted_mis
Masked reiceive clock too fast interrupt state
1: Receive and transmit clock drift detected by the clock moniotor
0: No receive and transmit clock drift detected by the clock moniotor
9 clk_rx_too_fast_mis
Masked reiceive clock too fast interrupt state
1: Receive clock too fast event occured in the clock moniotor
0: Receive clock too fast event did not occur in the clock moniotor
8 clk_rx_too_slow_mis
Masked reiceive clock too slow interrupt state
1: Receive clock too slow event occured in the clock moniotor
0: Receive clock too slow event did not occur in the clock moniotor
7 external_mis
Masked external interrupt state
1: INTN pin is equal to CR.intn_polarity.
0: INTN pin is not equal to CR.intn_polarity.
6 rx_fifo_overflow_mis
Masked receive FIFO overflow interrupt state
1: Receive FIFO overflow error occurred
0: No receive FIFO overflow error occurred
5 rx_fifo_underrun_mis
Masked receive FIFO underrun  interrupt state
1: Receive FIFO underrun  error occurred
0: No receive FIFO overflow error occurred
4 rx_fifo_nempty_mis
Masked receive FIFO not empty interrupt state
1: Receive FIFO is not empty
0: Receive FIFO is empty
3 tx_fifo_overflow_mis
Masked transmit FIFO overflow interrupt state
1: Transmit FIFO overflow error occurred
0: No transmit FIFO overflow error occurred
2 tx_fifo_underrun_mis
Masked transmit FIFO underrun  interrupt state
1: Transmit FIFO underrun  error occurred
0: No transmit FIFO underrun  error occurred
1 tx_fifo_empty_mis
Masked transmit FIFO empty interrupt state
1: Transmit FIFO is full
0: Transmit FIFO is not empty
0 transfer_end_mis
Masked transfer end interrupt state
1: Transfer finished. SR.io_controller_busy has become inactive.
0: Transfer not finished. SR.io_controller_busy is active.


xspi_pio_out
XSPI PIO output control register (POCR)
'xspi_mode' of register CR0 must be Programmable IO Mode.
Exception is intn_out and rstn_out because the INTN and RSTN output pins are dicrectly
controlled by the POCR and POECR register.
Bit 'xspi_en' of register CR0 has to be set to drive the XSPI IOs in the PIO mode.
R/W
0x00001e00
Address@com_xspi : 0x0640068c
Address@xspi_evm : 0x4002008c
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
clk_out
CLK          pin output state
12 "1"
rstn_out
RSTN         pin output state
11 "1"
intn_out
INTN         pin output state
10 - 9 "11"
csn_out
CSN1 - CSN0  pin output state
8 "0"
ds_out
DS           pin output state
7 - 0 "00000000"
d_out
D7 - D0      pin output state


xspi_pio_oe
XSPI PIO output enable register (POECR)
'xspi_mode' of register CR0 must be Programmable IO Mode.
Exception is intn_out and rstn_out because the INTN and RSTN output pins are dicrectly
controlled by the POCR and POECR register.
Bit 'xspi_en' of register CR0 has to be set to drive the XSPI IOs in the PIO mode.
R/W
0x00000000
Address@com_xspi : 0x06400690
Address@xspi_evm : 0x40020090
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
clk_oe
CLK          pin output enable
12 "0"
rstn_oe
RSTN         pin output enable
11 "0"
intn_oe
INTN         pin output enable
10 - 9 "00"
csn_oe
CSN1 - CSN0  pin output enable
8 "0"
ds_oe
DS           pin output enable
7 - 0 "00000000"
d_oe
D7 - D0      pin output enable


xspi_pio_is
xSPI PIO input status register (PIS)
Sampled output pin states.
R
Address@com_xspi : 0x06400694
Address@xspi_evm : 0x40020094
Bits Name Description
31 - 14 -
 reserved
13 clk_is
CLK          pin input state
12 rstn_is
RSTN         pin input state
11 intn_is
INTN         pin input state
10 - 9 csn_is
CSN1 - CSN0  pin input state
8 ds_is
DS           pin input state
7 - 0 d_is
D7 - D0      pin input state


xspi_rx_dr
xSPI receive data register
Received data word is delivered from receive FIFO.
Word, halfword and byte accesses are allowed.
Ordering of the bits is configured by the xspi_tcr.msbit_first and xspi_tcr.msbyte_first.
R
Address@com_xspi : 0x06400698
Address@xspi_evm : 0x40020098
Bits Name Description
31 - 0 data
RX Data


xspi_csn0_ar_1s
xSPI address register 1S (CSN0_AR_1S)
address to be sent in 1S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006a0
Address@xspi_evm : 0x400200a0
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_2s
xSPI address register 2S (CSN0_AR_2S)
address to be sent in 2S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006a4
Address@xspi_evm : 0x400200a4
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_4s
xSPI address register 4S (CSN0_AR_4S)
address to be sent in 4S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006a8
Address@xspi_evm : 0x400200a8
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_8s
xSPI address register 8S (CSN0_AR_8S)
address to be sent in 8S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006ac
Address@xspi_evm : 0x400200ac
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_1d
xSPI address register 1D (CSN0_AR_1D)
address to be sent in 1D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006b0
Address@xspi_evm : 0x400200b0
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_2d
xSPI address register 2D (CSN0_AR_2D)
address to be sent in 2D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006b4
Address@xspi_evm : 0x400200b4
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_4d
xSPI address register 4D (CSN0_AR_4D)
address to be sent in 4D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006b8
Address@xspi_evm : 0x400200b8
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn0_ar_8d
xSPI address register 8D (CSN0_AR_8D)
address to be sent in 8D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN0_ABx_CRy) and TCR0.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN0_ABx_CRy).
The complete number of address bytes (TCR0.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR0.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN0_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006bc
Address@xspi_evm : 0x400200bc
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_1s
xSPI address register 1S (CSN1_AR_1S)
address to be sent in 1S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006c0
Address@xspi_evm : 0x400200c0
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_2s
xSPI address register 2S (CSN1_AR_2S)
address to be sent in 2S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006c4
Address@xspi_evm : 0x400200c4
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_4s
xSPI address register 4S (CSN1_AR_4S)
address to be sent in 4S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006c8
Address@xspi_evm : 0x400200c8
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_8s
xSPI address register 8S (CSN1_AR_8S)
address to be sent in 8S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006cc
Address@xspi_evm : 0x400200cc
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_1d
xSPI address register 1D (CSN1_AR_1D)
address to be sent in 1D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006d0
Address@xspi_evm : 0x400200d0
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_2d
xSPI address register 2D (CSN1_AR_2D)
address to be sent in 2D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006d4
Address@xspi_evm : 0x400200d4
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_4d
xSPI address register 4D (CSN1_AR_4D)
address to be sent in 4D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006d8
Address@xspi_evm : 0x400200d8
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_csn1_ar_8d
xSPI address register 8D (CSN1_AR_8D)
address to be sent in 8D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Address Byte Control Register (CSN1_ABx_CRy) and TCR1.address_bytes_used must be configured before writing this register.
Ordering of the address bits is configured by the Address Byte Control Register (CSN1_ABx_CRy).
The complete number of address bytes (TCR1.address_bytes_used+1) must be written to the same xSPI address register
(mulitple accesses possible) before writing to a different address or data register.
If one access exceeds the number of address bytes, exceeding bytes are discareded.
E.g. TCR1.address_bytes_used = 1 => address bytes = 2, if a 4 byte access to the address register occurs, the two MSB are discarded.
To send the address from MSB to LSB with default CSN1_ABx_CRy config, address bytes must be written LSB to MSB to the address register.
W
0x00000000
Address@com_xspi : 0x064006dc
Address@xspi_evm : 0x400200dc
Bits Reset value Name Description
31 - 0 0x0
address
To be transmitted to the external device


xspi_tx_dr_1s
xSPI data register 1S (TX_DR_1S)
data to be sent in 1S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006e0
Address@xspi_evm : 0x400200e0
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_2s
xSPI data register 2S (TX_DR_2S)
data to be sent in 2S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006e4
Address@xspi_evm : 0x400200e4
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_4s
xSPI data register 4S (TX_DR_4S)
data to be sent in 4S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006e8
Address@xspi_evm : 0x400200e8
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_8s
xSPI data register 8S (TX_DR_8S)
data to be sent in 8S written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006ec
Address@xspi_evm : 0x400200ec
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_1d
xSPI data register 1D (TX_DR_1D)
data to be sent in 1D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006f0
Address@xspi_evm : 0x400200f0
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_2d
xSPI data register 2D (TX_DR_2D)
data to be sent in 2D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006f4
Address@xspi_evm : 0x400200f4
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_4d
xSPI data register 4D (TX_DR_4D)
data to be sent in 4D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006f8
Address@xspi_evm : 0x400200f8
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_8d
xSPI data register 8D (TX_DR_8D)
data to be sent in 8D written to SYS TX FIFO.
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed.
Send to the external device LSB to MSB.
W
0x00000000
Address@com_xspi : 0x064006fc
Address@xspi_evm : 0x400200fc
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device


xspi_tx_dr_4s_ds_off
xSPI data register (TX_DR_4S_DS_OFF)
Data to be sent in 4S with disabled data strobe meaning the DS output is driven to ~TCR0/1.tx_ds_pol.
Does not impact the enabling of the DS output during the transfer (TCR0/1.tx_ds_en).
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed
W
0x00000000
Address@com_xspi : 0x06400700
Address@xspi_evm : 0x40020100
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device with inactive DS


xspi_tx_dr_8s_ds_off
xSPI data register (TX_DR_8S_DS_OFF)
Data to be sent in 8S with disabled data strobe meaning the DS output is driven to ~TCR0/1.tx_ds_pol.
Does not impact the enabling of the DS output during the transfer (TCR0/1.tx_ds_en).
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed
W
0x00000000
Address@com_xspi : 0x06400704
Address@xspi_evm : 0x40020104
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device with inactive DS


xspi_tx_dr_4d_ds_off
xSPI data register (TX_DR_4D_DS_OFF)
Data to be sent in 4D with disabled data strobe meaning the DS output is driven to ~TCR0/1.tx_ds_pol.
Does not impact the enabling of the DS output during the transfer (TCR0/1.tx_ds_en).
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed
W
0x00000000
Address@com_xspi : 0x06400708
Address@xspi_evm : 0x40020108
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device with inactive DS


xspi_tx_dr_8d_ds_off
xSPI data register (TX_DR_8D_DS_OFF)
Data to be sent in 8D with disabled data strobe meaning the DS output is driven to ~TCR0/1.tx_ds_pol.
Does not impact the enabling of the DS output during the transfer (TCR0/1.tx_ds_en).
Only accessible if xSPI enabled in peripheral mode (CR).
Word, halfword and byte accesses are allowed
W
0x00000000
Address@com_xspi : 0x0640070c
Address@xspi_evm : 0x4002010c
Bits Reset value Name Description
31 - 0 0x0
data
To be transmitted to the external device with inactive DS


xspi_csn0_addr_byte0_cr0
xSPI CSN0 Address Byte 0 Control Register 0 (CSN0_AB0_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 3:0 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x03020100
Address@com_xspi : 0x06400710
Address@xspi_evm : 0x40020110
Bits Reset value Name Description
31 - 24 "00000011"
addr_bit3_cfg
address bit 3 configuration
00xx_xxxx : address bit 3 ==  xspi_ar[addr_bit3_cfg[5:0]]
01xx_xxxx : address bit 3 tied low  (address bit 3 unused)
10xx_xxxx : address bit 3 tied high (address bit 3 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00000010"
addr_bit2_cfg
address bit 2 configuration
00xx_xxxx : address bit 2 ==  xspi_ar[addr_bit2_cfg[5:0]]
01xx_xxxx : address bit 2 tied low  (address bit 2 unused)
10xx_xxxx : address bit 2 tied high (address bit 2 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00000001"
addr_bit1_cfg
address bit 1 configuration
00xx_xxxx : address bit 1 ==  xspi_ar[addr_bit1_cfg[5:0]]
01xx_xxxx : address bit 1 tied low  (address bit 1 unused)
10xx_xxxx : address bit 1 tied high (address bit 1 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00000000"
addr_bit0_cfg
address bit 0 configuration
00xx_xxxx : address bit 0 ==  xspi_ar[addr_bit0_cfg[5:0]]
01xx_xxxx : address bit 0 tied low  (address bit 0 unused)
10xx_xxxx : address bit 0 tied high (address bit 0 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte0_cr1
xSPI CSN0 Address Byte 0 Control Register 1 (CSN0_AB0_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 7:4 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x07060504
Address@com_xspi : 0x06400714
Address@xspi_evm : 0x40020114
Bits Reset value Name Description
31 - 24 "00000111"
addr_bit7_cfg
address bit 7 configuration
00xx_xxxx : address bit 7 ==  xspi_ar[addr_bit7_cfg[5:0]]
01xx_xxxx : address bit 7 tied low  (address bit 7 unused)
10xx_xxxx : address bit 7 tied high (address bit 7 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00000110"
addr_bit6_cfg
address bit 6 configuration
00xx_xxxx : address bit 6 ==  xspi_ar[addr_bit6_cfg[5:0]]
01xx_xxxx : address bit 6 tied low  (address bit 6 unused)
10xx_xxxx : address bit 6 tied high (address bit 6 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00000101"
addr_bit5_cfg
address bit 5 configuration
00xx_xxxx : address bit 5 ==  xspi_ar[addr_bit5_cfg[5:0]]
01xx_xxxx : address bit 5 tied low  (address bit 5 unused)
10xx_xxxx : address bit 5 tied high (address bit 5 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00000100"
addr_bit4_cfg
address bit 4 configuration
00xx_xxxx : address bit 4 ==  xspi_ar[addr_bit4_cfg[5:0]]
01xx_xxxx : address bit 4 tied low  (address bit 4 unused)
10xx_xxxx : address bit 4 tied high (address bit 4 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte1_cr0
xSPI CSN0 Address Byte 1 Control Register 0 (CSN0_AB1_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 11:8 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x0b0a0908
Address@com_xspi : 0x06400718
Address@xspi_evm : 0x40020118
Bits Reset value Name Description
31 - 24 "00001011"
addr_bit11_cfg
address bit 11 configuration
00xx_xxxx : address bit 11 ==  xspi_ar[addr_bit11_cfg[5:0]]
01xx_xxxx : address bit 11 tied low  (address bit 11 unused)
10xx_xxxx : address bit 11 tied high (address bit 11 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00001010"
addr_bit10_cfg
address bit 10 configuration
00xx_xxxx : address bit 10 ==  xspi_ar[addr_bit10_cfg[5:0]]
01xx_xxxx : address bit 10 tied low  (address bit 10 unused)
10xx_xxxx : address bit 10 tied high (address bit 10 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00001001"
addr_bit9_cfg
address bit 9 configuration
00xx_xxxx : address bit 9 ==  xspi_ar[addr_bit9_cfg[5:0]]
01xx_xxxx : address bit 9 tied low  (address bit 9 unused)
10xx_xxxx : address bit 9 tied high (address bit 9 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00001000"
addr_bit8_cfg
address bit 8 configuration
00xx_xxxx : address bit 8 ==  xspi_ar[addr_bit8_cfg[5:0]]
01xx_xxxx : address bit 8 tied low  (address bit 8 unused)
10xx_xxxx : address bit 8 tied high (address bit 8 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte1_cr1
xSPI CSN0 Address Byte 1 Control Register 1 (CSN0_AB1_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 15:12 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x0f0e0d0c
Address@com_xspi : 0x0640071c
Address@xspi_evm : 0x4002011c
Bits Reset value Name Description
31 - 24 "00001111"
addr_bit15_cfg
address bit 15 configuration
00xx_xxxx : address bit 15 ==  xspi_ar[addr_bit15_cfg[5:0]]
01xx_xxxx : address bit 15 tied low  (address bit 15 unused)
10xx_xxxx : address bit 15 tied high (address bit 15 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00001110"
addr_bit14_cfg
address bit 14 configuration
00xx_xxxx : address bit 14 ==  xspi_ar[addr_bit14_cfg[5:0]]
01xx_xxxx : address bit 14 tied low  (address bit 14 unused)
10xx_xxxx : address bit 14 tied high (address bit 14 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00001101"
addr_bit13_cfg
address bit 13 configuration
00xx_xxxx : address bit 13 ==  xspi_ar[addr_bit13_cfg[5:0]]
01xx_xxxx : address bit 13 tied low  (address bit 13 unused)
10xx_xxxx : address bit 13 tied high (address bit 13 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00001100"
addr_bit12_cfg
address bit 12 configuration
00xx_xxxx : address bit 12 ==  xspi_ar[addr_bit12_cfg[5:0]]
01xx_xxxx : address bit 12 tied low  (address bit 12 unused)
10xx_xxxx : address bit 12 tied high (address bit 12 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte2_cr0
xSPI CSN0 Address Byte 2 Control Register 0 (CSN0_AB2_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 19:16 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x13121110
Address@com_xspi : 0x06400720
Address@xspi_evm : 0x40020120
Bits Reset value Name Description
31 - 24 "00010011"
addr_bit19_cfg
address bit 19 configuration
00xx_xxxx : address bit 19 ==  xspi_ar[addr_bit19_cfg[5:0]]
01xx_xxxx : address bit 19 tied low  (address bit 19 unused)
10xx_xxxx : address bit 19 tied high (address bit 19 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00010010"
addr_bit18_cfg
address bit 18 configuration
00xx_xxxx : address bit 18 ==  xspi_ar[addr_bit18_cfg[5:0]]
01xx_xxxx : address bit 18 tied low  (address bit 18 unused)
10xx_xxxx : address bit 18 tied high (address bit 18 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00010001"
addr_bit17_cfg
address bit 17 configuration
00xx_xxxx : address bit 17 ==  xspi_ar[addr_bit17_cfg[5:0]]
01xx_xxxx : address bit 17 tied low  (address bit 17 unused)
10xx_xxxx : address bit 17 tied high (address bit 17 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00010000"
addr_bit16_cfg
address bit 16 configuration
00xx_xxxx : address bit 16 ==  xspi_ar[addr_bit16_cfg[5:0]]
01xx_xxxx : address bit 16 tied low  (address bit 16 unused)
10xx_xxxx : address bit 16 tied high (address bit 16 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte2_cr1
xSPI CSN0 Address Byte 2 Control Register 1 (CSN0_AB2_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 23:20 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x17161514
Address@com_xspi : 0x06400724
Address@xspi_evm : 0x40020124
Bits Reset value Name Description
31 - 24 "00010111"
addr_bit23_cfg
address bit 23 configuration
00xx_xxxx : address bit 23 ==  xspi_ar[addr_bit23_cfg[5:0]]
01xx_xxxx : address bit 23 tied low  (address bit 23 unused)
10xx_xxxx : address bit 23 tied high (address bit 23 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00010110"
addr_bit22_cfg
address bit 22 configuration
00xx_xxxx : address bit 22 ==  xspi_ar[addr_bit22_cfg[5:0]]
01xx_xxxx : address bit 22 tied low  (address bit 22 unused)
10xx_xxxx : address bit 22 tied high (address bit 22 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00010101"
addr_bit21_cfg
address bit 21 configuration
00xx_xxxx : address bit 21 ==  xspi_ar[addr_bit21_cfg[5:0]]
01xx_xxxx : address bit 21 tied low  (address bit 21 unused)
10xx_xxxx : address bit 21 tied high (address bit 21 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00010100"
addr_bit20_cfg
address bit 20 configuration
00xx_xxxx : address bit 20 ==  xspi_ar[addr_bit20_cfg[5:0]]
01xx_xxxx : address bit 20 tied low  (address bit 20 unused)
10xx_xxxx : address bit 20 tied high (address bit 20 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte3_cr0
xSPI CSN0 Address Byte 3 Control Register 0 (CSN0_AB3_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 27:24 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x1b1a1918
Address@com_xspi : 0x06400728
Address@xspi_evm : 0x40020128
Bits Reset value Name Description
31 - 24 "00011011"
addr_bit27_cfg
address bit 27 configuration
00xx_xxxx : address bit 27 ==  xspi_ar[addr_bit27_cfg[5:0]]
01xx_xxxx : address bit 27 tied low  (address bit 27 unused)
10xx_xxxx : address bit 27 tied high (address bit 27 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00011010"
addr_bit26_cfg
address bit 26 configuration
00xx_xxxx : address bit 26 ==  xspi_ar[addr_bit26_cfg[5:0]]
01xx_xxxx : address bit 26 tied low  (address bit 26 unused)
10xx_xxxx : address bit 26 tied high (address bit 26 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00011001"
addr_bit25_cfg
address bit 25 configuration
00xx_xxxx : address bit 25 ==  xspi_ar[addr_bit25_cfg[5:0]]
01xx_xxxx : address bit 25 tied low  (address bit 25 unused)
10xx_xxxx : address bit 25 tied high (address bit 25 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00011000"
addr_bit24_cfg
address bit 24 configuration
00xx_xxxx : address bit 24 ==  xspi_ar[addr_bit24_cfg[5:0]]
01xx_xxxx : address bit 24 tied low  (address bit 24 unused)
10xx_xxxx : address bit 24 tied high (address bit 24 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte3_cr1
xSPI CSN0 Address Byte 3 Control Register 1 (CSN0_AB3_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 31:28 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x1f1e1d1c
Address@com_xspi : 0x0640072c
Address@xspi_evm : 0x4002012c
Bits Reset value Name Description
31 - 24 "00011111"
addr_bit31_cfg
address bit 31 configuration
00xx_xxxx : address bit 31 ==  xspi_ar[addr_bit31_cfg[5:0]]
01xx_xxxx : address bit 31 tied low  (address bit 31 unused)
10xx_xxxx : address bit 31 tied high (address bit 31 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00011110"
addr_bit30_cfg
address bit 30 configuration
00xx_xxxx : address bit 30 ==  xspi_ar[addr_bit30_cfg[5:0]]
01xx_xxxx : address bit 30 tied low  (address bit 30 unused)
10xx_xxxx : address bit 30 tied high (address bit 30 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00011101"
addr_bit29_cfg
address bit 29 configuration
00xx_xxxx : address bit 29 ==  xspi_ar[addr_bit29_cfg[5:0]]
01xx_xxxx : address bit 29 tied low  (address bit 29 unused)
10xx_xxxx : address bit 29 tied high (address bit 29 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00011100"
addr_bit28_cfg
address bit 28 configuration
00xx_xxxx : address bit 28 ==  xspi_ar[addr_bit28_cfg[5:0]]
01xx_xxxx : address bit 28 tied low  (address bit 28 unused)
10xx_xxxx : address bit 28 tied high (address bit 28 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte4_cr0
xSPI CSN0 Address Byte 4 Control Register 0 (CSN0_AB4_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 35:32 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x23222120
Address@com_xspi : 0x06400730
Address@xspi_evm : 0x40020130
Bits Reset value Name Description
31 - 24 "00100011"
addr_bit35_cfg
address bit 35 configuration
00xx_xxxx : address bit 35 ==  xspi_ar[addr_bit35_cfg[5:0]]
01xx_xxxx : address bit 35 tied low  (address bit 35 unused)
10xx_xxxx : address bit 35 tied high (address bit 35 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00100010"
addr_bit34_cfg
address bit 34 configuration
00xx_xxxx : address bit 34 ==  xspi_ar[addr_bit34_cfg[5:0]]
01xx_xxxx : address bit 34 tied low  (address bit 34 unused)
10xx_xxxx : address bit 34 tied high (address bit 34 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00100001"
addr_bit33_cfg
address bit 33 configuration
00xx_xxxx : address bit 33 ==  xspi_ar[addr_bit33_cfg[5:0]]
01xx_xxxx : address bit 33 tied low  (address bit 33 unused)
10xx_xxxx : address bit 33 tied high (address bit 33 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00100000"
addr_bit32_cfg
address bit 32 configuration
00xx_xxxx : address bit 32 ==  xspi_ar[addr_bit32_cfg[5:0]]
01xx_xxxx : address bit 32 tied low  (address bit 32 unused)
10xx_xxxx : address bit 32 tied high (address bit 32 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte4_cr1
xSPI CSN0 Address Byte 4 Control Register 1 (CSN0_AB4_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 39:36 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x27262524
Address@com_xspi : 0x06400734
Address@xspi_evm : 0x40020134
Bits Reset value Name Description
31 - 24 "00100111"
addr_bit39_cfg
address bit 39 configuration
00xx_xxxx : address bit 39 ==  xspi_ar[addr_bit39_cfg[5:0]]
01xx_xxxx : address bit 39 tied low  (address bit 39 unused)
10xx_xxxx : address bit 39 tied high (address bit 39 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00100110"
addr_bit38_cfg
address bit 38 configuration
00xx_xxxx : address bit 38 ==  xspi_ar[addr_bit38_cfg[5:0]]
01xx_xxxx : address bit 38 tied low  (address bit 38 unused)
10xx_xxxx : address bit 38 tied high (address bit 38 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00100101"
addr_bit37_cfg
address bit 37 configuration
00xx_xxxx : address bit 37 ==  xspi_ar[addr_bit37_cfg[5:0]]
01xx_xxxx : address bit 37 tied low  (address bit 37 unused)
10xx_xxxx : address bit 37 tied high (address bit 37 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00100100"
addr_bit36_cfg
address bit 36 configuration
00xx_xxxx : address bit 36 ==  xspi_ar[addr_bit36_cfg[5:0]]
01xx_xxxx : address bit 36 tied low  (address bit 36 unused)
10xx_xxxx : address bit 36 tied high (address bit 36 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte5_cr0
xSPI CSN0 Address Byte 5 Control Register 0 (CSN0_AB5_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 43:40 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x2b2a2928
Address@com_xspi : 0x06400738
Address@xspi_evm : 0x40020138
Bits Reset value Name Description
31 - 24 "00101011"
addr_bit43_cfg
address bit 43 configuration
00xx_xxxx : address bit 43 ==  xspi_ar[addr_bit43_cfg[5:0]]
01xx_xxxx : address bit 43 tied low  (address bit 43 unused)
10xx_xxxx : address bit 43 tied high (address bit 43 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00101010"
addr_bit42_cfg
address bit 42 configuration
00xx_xxxx : address bit 42 ==  xspi_ar[addr_bit42_cfg[5:0]]
01xx_xxxx : address bit 42 tied low  (address bit 42 unused)
10xx_xxxx : address bit 42 tied high (address bit 42 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00101001"
addr_bit41_cfg
address bit 41 configuration
00xx_xxxx : address bit 41 ==  xspi_ar[addr_bit41_cfg[5:0]]
01xx_xxxx : address bit 41 tied low  (address bit 41 unused)
10xx_xxxx : address bit 41 tied high (address bit 41 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00101000"
addr_bit40_cfg
address bit 40 configuration
00xx_xxxx : address bit 40 ==  xspi_ar[addr_bit40_cfg[5:0]]
01xx_xxxx : address bit 40 tied low  (address bit 40 unused)
10xx_xxxx : address bit 40 tied high (address bit 40 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn0_addr_byte5_cr1
xSPI CSN0 Address Byte 5 Control Register 1 (CSN0_AB5_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 47:44 of the address send to the IOs for the external device connected to CSN0.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x2f2e2d2c
Address@com_xspi : 0x0640073c
Address@xspi_evm : 0x4002013c
Bits Reset value Name Description
31 - 24 "00101111"
addr_bit47_cfg
address bit 47 configuration
00xx_xxxx : address bit 47 ==  xspi_ar[addr_bit47_cfg[5:0]]
01xx_xxxx : address bit 47 tied low  (address bit 47 unused)
10xx_xxxx : address bit 47 tied high (address bit 47 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00101110"
addr_bit46_cfg
address bit 46 configuration
00xx_xxxx : address bit 46 ==  xspi_ar[addr_bit46_cfg[5:0]]
01xx_xxxx : address bit 46 tied low  (address bit 46 unused)
10xx_xxxx : address bit 46 tied high (address bit 46 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00101101"
addr_bit45_cfg
address bit 45 configuration
00xx_xxxx : address bit 45 ==  xspi_ar[addr_bit45_cfg[5:0]]
01xx_xxxx : address bit 45 tied low  (address bit 45 unused)
10xx_xxxx : address bit 45 tied high (address bit 45 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00101100"
addr_bit44_cfg
address bit 44 configuration
00xx_xxxx : address bit 44 ==  xspi_ar[addr_bit44_cfg[5:0]]
01xx_xxxx : address bit 44 tied low  (address bit 44 unused)
10xx_xxxx : address bit 44 tied high (address bit 44 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte0_cr0
xSPI CSN1 Address Byte 0 Control Register 0 (CSN1_AB0_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 3:0 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x03020100
Address@com_xspi : 0x06400740
Address@xspi_evm : 0x40020140
Bits Reset value Name Description
31 - 24 "00000011"
addr_bit3_cfg
address bit 3 configuration
00xx_xxxx : address bit 3 ==  xspi_ar[addr_bit3_cfg[5:0]]
01xx_xxxx : address bit 3 tied low  (address bit 3 unused)
10xx_xxxx : address bit 3 tied high (address bit 3 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00000010"
addr_bit2_cfg
address bit 2 configuration
00xx_xxxx : address bit 2 ==  xspi_ar[addr_bit2_cfg[5:0]]
01xx_xxxx : address bit 2 tied low  (address bit 2 unused)
10xx_xxxx : address bit 2 tied high (address bit 2 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00000001"
addr_bit1_cfg
address bit 1 configuration
00xx_xxxx : address bit 1 ==  xspi_ar[addr_bit1_cfg[5:0]]
01xx_xxxx : address bit 1 tied low  (address bit 1 unused)
10xx_xxxx : address bit 1 tied high (address bit 1 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00000000"
addr_bit0_cfg
address bit 0 configuration
00xx_xxxx : address bit 0 ==  xspi_ar[addr_bit0_cfg[5:0]]
01xx_xxxx : address bit 0 tied low  (address bit 0 unused)
10xx_xxxx : address bit 0 tied high (address bit 0 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte0_cr1
xSPI CSN1 Address Byte 0 Control Register 1 (CSN1_AB0_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 7:4 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x07060504
Address@com_xspi : 0x06400744
Address@xspi_evm : 0x40020144
Bits Reset value Name Description
31 - 24 "00000111"
addr_bit7_cfg
address bit 7 configuration
00xx_xxxx : address bit 7 ==  xspi_ar[addr_bit7_cfg[5:0]]
01xx_xxxx : address bit 7 tied low  (address bit 7 unused)
10xx_xxxx : address bit 7 tied high (address bit 7 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00000110"
addr_bit6_cfg
address bit 6 configuration
00xx_xxxx : address bit 6 ==  xspi_ar[addr_bit6_cfg[5:0]]
01xx_xxxx : address bit 6 tied low  (address bit 6 unused)
10xx_xxxx : address bit 6 tied high (address bit 6 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00000101"
addr_bit5_cfg
address bit 5 configuration
00xx_xxxx : address bit 5 ==  xspi_ar[addr_bit5_cfg[5:0]]
01xx_xxxx : address bit 5 tied low  (address bit 5 unused)
10xx_xxxx : address bit 5 tied high (address bit 5 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00000100"
addr_bit4_cfg
address bit 4 configuration
00xx_xxxx : address bit 4 ==  xspi_ar[addr_bit4_cfg[5:0]]
01xx_xxxx : address bit 4 tied low  (address bit 4 unused)
10xx_xxxx : address bit 4 tied high (address bit 4 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte1_cr0
xSPI CSN1 Address Byte 1 Control Register 0 (CSN1_AB1_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 11:8 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x0b0a0908
Address@com_xspi : 0x06400748
Address@xspi_evm : 0x40020148
Bits Reset value Name Description
31 - 24 "00001011"
addr_bit11_cfg
address bit 11 configuration
00xx_xxxx : address bit 11 ==  xspi_ar[addr_bit11_cfg[5:0]]
01xx_xxxx : address bit 11 tied low  (address bit 11 unused)
10xx_xxxx : address bit 11 tied high (address bit 11 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00001010"
addr_bit10_cfg
address bit 10 configuration
00xx_xxxx : address bit 10 ==  xspi_ar[addr_bit10_cfg[5:0]]
01xx_xxxx : address bit 10 tied low  (address bit 10 unused)
10xx_xxxx : address bit 10 tied high (address bit 10 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00001001"
addr_bit9_cfg
address bit 9 configuration
00xx_xxxx : address bit 9 ==  xspi_ar[addr_bit9_cfg[5:0]]
01xx_xxxx : address bit 9 tied low  (address bit 9 unused)
10xx_xxxx : address bit 9 tied high (address bit 9 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00001000"
addr_bit8_cfg
address bit 8 configuration
00xx_xxxx : address bit 8 ==  xspi_ar[addr_bit8_cfg[5:0]]
01xx_xxxx : address bit 8 tied low  (address bit 8 unused)
10xx_xxxx : address bit 8 tied high (address bit 8 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte1_cr1
xSPI CSN1 Address Byte 1 Control Register 1 (CSN1_AB1_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 15:12 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x0f0e0d0c
Address@com_xspi : 0x0640074c
Address@xspi_evm : 0x4002014c
Bits Reset value Name Description
31 - 24 "00001111"
addr_bit15_cfg
address bit 15 configuration
00xx_xxxx : address bit 15 ==  xspi_ar[addr_bit15_cfg[5:0]]
01xx_xxxx : address bit 15 tied low  (address bit 15 unused)
10xx_xxxx : address bit 15 tied high (address bit 15 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00001110"
addr_bit14_cfg
address bit 14 configuration
00xx_xxxx : address bit 14 ==  xspi_ar[addr_bit14_cfg[5:0]]
01xx_xxxx : address bit 14 tied low  (address bit 14 unused)
10xx_xxxx : address bit 14 tied high (address bit 14 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00001101"
addr_bit13_cfg
address bit 13 configuration
00xx_xxxx : address bit 13 ==  xspi_ar[addr_bit13_cfg[5:0]]
01xx_xxxx : address bit 13 tied low  (address bit 13 unused)
10xx_xxxx : address bit 13 tied high (address bit 13 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00001100"
addr_bit12_cfg
address bit 12 configuration
00xx_xxxx : address bit 12 ==  xspi_ar[addr_bit12_cfg[5:0]]
01xx_xxxx : address bit 12 tied low  (address bit 12 unused)
10xx_xxxx : address bit 12 tied high (address bit 12 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte2_cr0
xSPI CSN1 Address Byte 2 Control Register 0 (CSN1_AB2_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 19:16 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x13121110
Address@com_xspi : 0x06400750
Address@xspi_evm : 0x40020150
Bits Reset value Name Description
31 - 24 "00010011"
addr_bit19_cfg
address bit 19 configuration
00xx_xxxx : address bit 19 ==  xspi_ar[addr_bit19_cfg[5:0]]
01xx_xxxx : address bit 19 tied low  (address bit 19 unused)
10xx_xxxx : address bit 19 tied high (address bit 19 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00010010"
addr_bit18_cfg
address bit 18 configuration
00xx_xxxx : address bit 18 ==  xspi_ar[addr_bit18_cfg[5:0]]
01xx_xxxx : address bit 18 tied low  (address bit 18 unused)
10xx_xxxx : address bit 18 tied high (address bit 18 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00010001"
addr_bit17_cfg
address bit 17 configuration
00xx_xxxx : address bit 17 ==  xspi_ar[addr_bit17_cfg[5:0]]
01xx_xxxx : address bit 17 tied low  (address bit 17 unused)
10xx_xxxx : address bit 17 tied high (address bit 17 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00010000"
addr_bit16_cfg
address bit 16 configuration
00xx_xxxx : address bit 16 ==  xspi_ar[addr_bit16_cfg[5:0]]
01xx_xxxx : address bit 16 tied low  (address bit 16 unused)
10xx_xxxx : address bit 16 tied high (address bit 16 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte2_cr1
xSPI CSN1 Address Byte 2 Control Register 1 (CSN1_AB2_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 23:20 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x17161514
Address@com_xspi : 0x06400754
Address@xspi_evm : 0x40020154
Bits Reset value Name Description
31 - 24 "00010111"
addr_bit23_cfg
address bit 23 configuration
00xx_xxxx : address bit 23 ==  xspi_ar[addr_bit23_cfg[5:0]]
01xx_xxxx : address bit 23 tied low  (address bit 23 unused)
10xx_xxxx : address bit 23 tied high (address bit 23 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00010110"
addr_bit22_cfg
address bit 22 configuration
00xx_xxxx : address bit 22 ==  xspi_ar[addr_bit22_cfg[5:0]]
01xx_xxxx : address bit 22 tied low  (address bit 22 unused)
10xx_xxxx : address bit 22 tied high (address bit 22 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00010101"
addr_bit21_cfg
address bit 21 configuration
00xx_xxxx : address bit 21 ==  xspi_ar[addr_bit21_cfg[5:0]]
01xx_xxxx : address bit 21 tied low  (address bit 21 unused)
10xx_xxxx : address bit 21 tied high (address bit 21 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00010100"
addr_bit20_cfg
address bit 20 configuration
00xx_xxxx : address bit 20 ==  xspi_ar[addr_bit20_cfg[5:0]]
01xx_xxxx : address bit 20 tied low  (address bit 20 unused)
10xx_xxxx : address bit 20 tied high (address bit 20 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte3_cr0
xSPI CSN1 Address Byte 3 Control Register 0 (CSN1_AB3_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 27:24 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x1b1a1918
Address@com_xspi : 0x06400758
Address@xspi_evm : 0x40020158
Bits Reset value Name Description
31 - 24 "00011011"
addr_bit27_cfg
address bit 27 configuration
00xx_xxxx : address bit 27 ==  xspi_ar[addr_bit27_cfg[5:0]]
01xx_xxxx : address bit 27 tied low  (address bit 27 unused)
10xx_xxxx : address bit 27 tied high (address bit 27 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00011010"
addr_bit26_cfg
address bit 26 configuration
00xx_xxxx : address bit 26 ==  xspi_ar[addr_bit26_cfg[5:0]]
01xx_xxxx : address bit 26 tied low  (address bit 26 unused)
10xx_xxxx : address bit 26 tied high (address bit 26 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00011001"
addr_bit25_cfg
address bit 25 configuration
00xx_xxxx : address bit 25 ==  xspi_ar[addr_bit25_cfg[5:0]]
01xx_xxxx : address bit 25 tied low  (address bit 25 unused)
10xx_xxxx : address bit 25 tied high (address bit 25 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00011000"
addr_bit24_cfg
address bit 24 configuration
00xx_xxxx : address bit 24 ==  xspi_ar[addr_bit24_cfg[5:0]]
01xx_xxxx : address bit 24 tied low  (address bit 24 unused)
10xx_xxxx : address bit 24 tied high (address bit 24 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte3_cr1
xSPI CSN1 Address Byte 3 Control Register 1 (CSN1_AB3_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 31:28 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x1f1e1d1c
Address@com_xspi : 0x0640075c
Address@xspi_evm : 0x4002015c
Bits Reset value Name Description
31 - 24 "00011111"
addr_bit31_cfg
address bit 31 configuration
00xx_xxxx : address bit 31 ==  xspi_ar[addr_bit31_cfg[5:0]]
01xx_xxxx : address bit 31 tied low  (address bit 31 unused)
10xx_xxxx : address bit 31 tied high (address bit 31 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00011110"
addr_bit30_cfg
address bit 30 configuration
00xx_xxxx : address bit 30 ==  xspi_ar[addr_bit30_cfg[5:0]]
01xx_xxxx : address bit 30 tied low  (address bit 30 unused)
10xx_xxxx : address bit 30 tied high (address bit 30 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00011101"
addr_bit29_cfg
address bit 29 configuration
00xx_xxxx : address bit 29 ==  xspi_ar[addr_bit29_cfg[5:0]]
01xx_xxxx : address bit 29 tied low  (address bit 29 unused)
10xx_xxxx : address bit 29 tied high (address bit 29 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00011100"
addr_bit28_cfg
address bit 28 configuration
00xx_xxxx : address bit 28 ==  xspi_ar[addr_bit28_cfg[5:0]]
01xx_xxxx : address bit 28 tied low  (address bit 28 unused)
10xx_xxxx : address bit 28 tied high (address bit 28 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte4_cr0
xSPI CSN1 Address Byte 4 Control Register 0 (CSN1_AB4_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 35:32 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x23222120
Address@com_xspi : 0x06400760
Address@xspi_evm : 0x40020160
Bits Reset value Name Description
31 - 24 "00100011"
addr_bit35_cfg
address bit 35 configuration
00xx_xxxx : address bit 35 ==  xspi_ar[addr_bit35_cfg[5:0]]
01xx_xxxx : address bit 35 tied low  (address bit 35 unused)
10xx_xxxx : address bit 35 tied high (address bit 35 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00100010"
addr_bit34_cfg
address bit 34 configuration
00xx_xxxx : address bit 34 ==  xspi_ar[addr_bit34_cfg[5:0]]
01xx_xxxx : address bit 34 tied low  (address bit 34 unused)
10xx_xxxx : address bit 34 tied high (address bit 34 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00100001"
addr_bit33_cfg
address bit 33 configuration
00xx_xxxx : address bit 33 ==  xspi_ar[addr_bit33_cfg[5:0]]
01xx_xxxx : address bit 33 tied low  (address bit 33 unused)
10xx_xxxx : address bit 33 tied high (address bit 33 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00100000"
addr_bit32_cfg
address bit 32 configuration
00xx_xxxx : address bit 32 ==  xspi_ar[addr_bit32_cfg[5:0]]
01xx_xxxx : address bit 32 tied low  (address bit 32 unused)
10xx_xxxx : address bit 32 tied high (address bit 32 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte4_cr1
xSPI CSN1 Address Byte 4 Control Register 1 (CSN1_AB4_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 39:36 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x27262524
Address@com_xspi : 0x06400764
Address@xspi_evm : 0x40020164
Bits Reset value Name Description
31 - 24 "00100111"
addr_bit39_cfg
address bit 39 configuration
00xx_xxxx : address bit 39 ==  xspi_ar[addr_bit39_cfg[5:0]]
01xx_xxxx : address bit 39 tied low  (address bit 39 unused)
10xx_xxxx : address bit 39 tied high (address bit 39 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00100110"
addr_bit38_cfg
address bit 38 configuration
00xx_xxxx : address bit 38 ==  xspi_ar[addr_bit38_cfg[5:0]]
01xx_xxxx : address bit 38 tied low  (address bit 38 unused)
10xx_xxxx : address bit 38 tied high (address bit 38 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00100101"
addr_bit37_cfg
address bit 37 configuration
00xx_xxxx : address bit 37 ==  xspi_ar[addr_bit37_cfg[5:0]]
01xx_xxxx : address bit 37 tied low  (address bit 37 unused)
10xx_xxxx : address bit 37 tied high (address bit 37 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00100100"
addr_bit36_cfg
address bit 36 configuration
00xx_xxxx : address bit 36 ==  xspi_ar[addr_bit36_cfg[5:0]]
01xx_xxxx : address bit 36 tied low  (address bit 36 unused)
10xx_xxxx : address bit 36 tied high (address bit 36 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte5_cr0
xSPI CSN1 Address Byte 5 Control Register 0 (CSN1_AB5_CR0).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 43:40 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x2b2a2928
Address@com_xspi : 0x06400768
Address@xspi_evm : 0x40020168
Bits Reset value Name Description
31 - 24 "00101011"
addr_bit43_cfg
address bit 43 configuration
00xx_xxxx : address bit 43 ==  xspi_ar[addr_bit43_cfg[5:0]]
01xx_xxxx : address bit 43 tied low  (address bit 43 unused)
10xx_xxxx : address bit 43 tied high (address bit 43 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00101010"
addr_bit42_cfg
address bit 42 configuration
00xx_xxxx : address bit 42 ==  xspi_ar[addr_bit42_cfg[5:0]]
01xx_xxxx : address bit 42 tied low  (address bit 42 unused)
10xx_xxxx : address bit 42 tied high (address bit 42 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00101001"
addr_bit41_cfg
address bit 41 configuration
00xx_xxxx : address bit 41 ==  xspi_ar[addr_bit41_cfg[5:0]]
01xx_xxxx : address bit 41 tied low  (address bit 41 unused)
10xx_xxxx : address bit 41 tied high (address bit 41 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00101000"
addr_bit40_cfg
address bit 40 configuration
00xx_xxxx : address bit 40 ==  xspi_ar[addr_bit40_cfg[5:0]]
01xx_xxxx : address bit 40 tied low  (address bit 40 unused)
10xx_xxxx : address bit 40 tied high (address bit 40 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0


xspi_csn1_addr_byte5_cr1
xSPI CSN1 Address Byte 5 Control Register 1 (CSN1_AB5_CR1).
This register must not be changed if CR.xspi_mode = memory mapped mode or during transfers (SR.io_controller_busy).
This register configures the address bits 47:44 of the address send to the IOs for the external device connected to CSN1.
When and on what line the address bits will be transferred is dependent on the number of IOs in use when transferring the address.
R/W
0x2f2e2d2c
Address@com_xspi : 0x0640076c
Address@xspi_evm : 0x4002016c
Bits Reset value Name Description
31 - 24 "00101111"
addr_bit47_cfg
address bit 47 configuration
00xx_xxxx : address bit 47 ==  xspi_ar[addr_bit47_cfg[5:0]]
01xx_xxxx : address bit 47 tied low  (address bit 47 unused)
10xx_xxxx : address bit 47 tied high (address bit 47 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
23 - 16 "00101110"
addr_bit46_cfg
address bit 46 configuration
00xx_xxxx : address bit 46 ==  xspi_ar[addr_bit46_cfg[5:0]]
01xx_xxxx : address bit 46 tied low  (address bit 46 unused)
10xx_xxxx : address bit 46 tied high (address bit 46 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
15 - 8 "00101101"
addr_bit45_cfg
address bit 45 configuration
00xx_xxxx : address bit 45 ==  xspi_ar[addr_bit45_cfg[5:0]]
01xx_xxxx : address bit 45 tied low  (address bit 45 unused)
10xx_xxxx : address bit 45 tied high (address bit 45 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0
7 - 0 "00101100"
addr_bit44_cfg
address bit 44 configuration
00xx_xxxx : address bit 44 ==  xspi_ar[addr_bit44_cfg[5:0]]
01xx_xxxx : address bit 44 tied low  (address bit 44 unused)
10xx_xxxx : address bit 44 tied high (address bit 44 unused)
11xx_xxxx : R/W Toggle
11xx_xxx0 : Write = 1'b0, Read = 1'b1
11xx_xxx1 : Write = 1'b1, Read = 1'b0



Base Address Area: com_sync_timer, com_sync_timer_global, app_sync_timer, app_sync_timer_global, mot_sync_timer, mot_sync_timer_global

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sync_cfg
1 4 R/W sync_timebase_modulus
2 8 W sync_cmd_do_sync
3 c R/W sync_write_sync_ctrl
4 10 R/W sync_timebase_ws
5 14 R/W sync_timebase_inc_ws
6 18 R/W sync_base_phase_rld_ws
7 1c R/W sync_base_phase_ws
8 20 R/W sync_sub_phase_ws
9 24 R/W sync_timebase
a 28 R/W sync_timebase_inc
b 2c R/W sync_base_phase_rld
c 30 R/W sync_base_phase
d 34 R/W sync_read_sync_cfg
e 38 R sync_timebase_rs
f 3c R sync_base_phase_rs
10 40 R sync_sub_phase_sel0_rs
11 44 R sync_sub_phase_sel1_rs
12 48 R/W sync_irq_raw
13 4c R sync_irq_masked
14 50 R/W sync_irq_msk_set
15 54 R/W sync_irq_msk_reset
16 58 R sync_irq_no
17 5c R/W sync_reload_configuration
18 60 R/W sync_sub_phase_0_rld
19 64 R/W sync_sub_phase_0
1a 68 R/W sync_reload_sub_phase_offset_0
1b 6c R/W sync_sub_phase_1_rld
1c 70 R/W sync_sub_phase_1
1d 74 R/W sync_reload_sub_phase_offset_1
1e 78 R/W sync_sub_phase_2_rld
1f 7c R/W sync_sub_phase_2
20 80 R/W sync_reload_sub_phase_offset_2
21 84 R/W sync_sub_phase_3_rld
22 88 R/W sync_sub_phase_3
23 8c R/W sync_reload_sub_phase_offset_3
24 90 R/W sync_sub_phase_4_rld
25 94 R/W sync_sub_phase_4
26 98 R/W sync_reload_sub_phase_offset_4
27 9c R/W sync_sub_phase_5_rld
28 a0 R/W sync_sub_phase_5
29 a4 R/W sync_reload_sub_phase_offset_5
2a a8 R/W sync_sub_phase_6_rld
2b ac R/W sync_sub_phase_6
2c b0 R/W sync_reload_sub_phase_offset_6
2d b4 R/W sync_sub_phase_7_rld
2e b8 R/W sync_sub_phase_7
2f bc R/W sync_reload_sub_phase_offset_7
30 c0 R/W sync_sub_phase_8_rld
31 c4 R/W sync_sub_phase_8
32 c8 R/W sync_reload_sub_phase_offset_8
33 cc R/W sync_sub_phase_9_rld
34 d0 R/W sync_sub_phase_9
35 d4 R/W sync_reload_sub_phase_offset_9
36 d8 R/W sync_sub_phase_10_rld
37 dc R/W sync_sub_phase_10
38 e0 R/W sync_reload_sub_phase_offset_10
39 e4 R/W sync_sub_phase_11_rld
3a e8 R/W sync_sub_phase_11
3b ec R/W sync_reload_sub_phase_offset_11
3c f0 R/W sync_sub_phase_12_rld
3d f4 R/W sync_sub_phase_12
3e f8 R/W sync_reload_sub_phase_offset_12
3f fc R/W sync_sub_phase_13_rld
40 100 R/W sync_sub_phase_13
41 104 R/W sync_reload_sub_phase_offset_13
42 108 R/W sync_sub_phase_14_rld
43 10c R/W sync_sub_phase_14
44 110 R/W sync_reload_sub_phase_offset_14
45 114 R/W sync_sub_phase_15_rld
46 118 R/W sync_sub_phase_15
47 11c R/W sync_reload_sub_phase_offset_15
48 120 R/W sync_sync_gen_0_cfg
49 124 R/W sync_sync_gen_0_base_phase
4a 128 R/W sync_sync_gen_1_cfg
4b 12c R/W sync_sync_gen_1_base_phase
4c 130 R/W sync_sync_gen_2_cfg
4d 134 R/W sync_sync_gen_2_base_phase
4e 138 R/W sync_sync_gen_3_cfg
4f 13c R/W sync_sync_gen_3_base_phase
50 140 R/W sync_sync_gen_4_cfg
51 144 R/W sync_sync_gen_4_base_phase
52 148 R/W sync_sync_gen_5_cfg
53 14c R/W sync_sync_gen_5_base_phase
54 150 R/W sync_sync_gen_6_cfg
55 154 R/W sync_sync_gen_6_base_phase
56 158 R/W sync_sync_gen_7_cfg
57 15c R/W sync_sync_gen_7_base_phase
58 160 R/W sync_sync_gen_8_cfg
59 164 R/W sync_sync_gen_8_base_phase
5a 168 R/W sync_sync_gen_9_cfg
5b 16c R/W sync_sync_gen_9_base_phase
5c 170 R/W sync_sync_gen_10_cfg
5d 174 R/W sync_sync_gen_10_base_phase
5e 178 R/W sync_sync_gen_11_cfg
5f 17c R/W sync_sync_gen_11_base_phase
60 180 R/W sync_sync_gen_12_cfg
61 184 R/W sync_sync_gen_12_base_phase
62 188 R/W sync_sync_gen_13_cfg
63 18c R/W sync_sync_gen_13_base_phase
64 190 R/W sync_sync_gen_14_cfg
65 194 R/W sync_sync_gen_14_base_phase
66 198 R/W sync_sync_gen_15_cfg
67 19c R/W sync_sync_gen_15_base_phase
68 1a0 R/W sync_sync_gen_16_cfg
69 1a4 R/W sync_sync_gen_16_base_phase
6a 1a8 R/W sync_sync_gen_17_cfg
6b 1ac R/W sync_sync_gen_17_base_phase
6c 1b0 R/W sync_sync_gen_18_cfg
6d 1b4 R/W sync_sync_gen_18_base_phase
6e 1b8 R/W sync_sync_gen_19_cfg
6f 1bc R/W sync_sync_gen_19_base_phase
70 1c0 R/W sync_sync_gen_20_cfg
71 1c4 R/W sync_sync_gen_20_base_phase
72 1c8 R/W sync_sync_gen_21_cfg
73 1cc R/W sync_sync_gen_21_base_phase
74 1d0 R/W sync_sync_gen_22_cfg
75 1d4 R/W sync_sync_gen_22_base_phase
76 1d8 R/W sync_sync_gen_23_cfg
77 1dc R/W sync_sync_gen_23_base_phase
78 1e0 R/W sync_sync_gen_24_cfg
79 1e4 R/W sync_sync_gen_24_base_phase
7a 1e8 R/W sync_sync_gen_25_cfg
7b 1ec R/W sync_sync_gen_25_base_phase
7c 1f0 R/W sync_sync_gen_26_cfg
7d 1f4 R/W sync_sync_gen_26_base_phase
7e 1f8 R/W sync_sync_gen_27_cfg
7f 1fc R/W sync_sync_gen_27_base_phase
80 200 R/W sync_sync_gen_28_cfg
81 204 R/W sync_sync_gen_28_base_phase
82 208 R/W sync_sync_gen_29_cfg
83 20c R/W sync_sync_gen_29_base_phase
84 210 R/W sync_sync_out_0_cfg
85 214 R/W sync_sync_out_1_cfg
86 218 R/W sync_sync_out_2_cfg
87 21c R/W sync_sync_out_3_cfg
88 220 R/W sync_sync_out_4_cfg
89 224 R/W sync_sync_out_5_cfg
8a 228 R/W sync_sync_out_6_cfg
8b 22c R/W sync_sync_out_7_cfg
8c-ff 230-3fc -  reserved

sync_cfg
Configuration Registers

This module has following instances in netx22xx:
COM_SMS (two instances, 'default' and global)
- 24 sync outs ([3:0]=iol (configurable), [7:4]=cda_rx, [11:8]=cda_tx, [15:12]=ada, [19:16]=ca32_com, [23:20]=sms)
- 4 sync outputs with configurable pulse length ([3:0]=iol)
- summary IRQ wired to ca32_com
- no input syncs available

APP (two instances, 'default' and global) - CONFIGURATION TBD
- 8 sync outs (unassigned)
- 2 sync outputs with configurable pulse length (unassigned)
- summary IRQ wired to mot_irq_router (accessible by mot_cpu0 and mot_cpu1)
- no input syncs availble

MOT (two instances, 'default' and global) - CONFIGURATION TBD
- 8 sync outs (unassigned)
- 2 sync outputs with configurable pulse length (unassigned)
- summary IRQ wired to mot_irq_router (accessible by mot_cpu0 and mot_cpu1)
- no input syncs availble
R/W
0x00000000
Address@com_sync_timer : 0x06400800
Address@com_sync_timer_global : 0x06400c00
Address@app_sync_timer : 0x40080800
Address@app_sync_timer_global : 0x40080c00
Address@mot_sync_timer : 0x49200c00
Address@mot_sync_timer_global : 0x49201000
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
write_sync_src_sel
0: trigger on posedge of write_sync
1: trigger on each edge of sync_phase
1 "0"
incr_src_sel
0: increment TIMEBASE on posedge of clk
1: increment TIMEBASE on each edge of sync_clk
0 "0"
en
0: TIMEBASE is not incremented


sync_timebase_modulus
R/W
0x00000000
Address@com_sync_timer : 0x06400804
Address@com_sync_timer_global : 0x06400c04
Address@app_sync_timer : 0x40080804
Address@app_sync_timer_global : 0x40080c04
Address@mot_sync_timer : 0x49200c04
Address@mot_sync_timer_global : 0x49201004
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see TIMEBASE


sync_cmd_do_sync
Command Register
W
0x00000000
Address@com_sync_timer : 0x06400808
Address@com_sync_timer_global : 0x06400c08
Address@app_sync_timer : 0x40080808
Address@app_sync_timer_global : 0x40080c08
Address@mot_sync_timer : 0x49200c08
Address@mot_sync_timer_global : 0x49201008
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
sync29
1: triggers sync29
29 "0"
sync28
1: triggers sync28
28 "0"
sync27
1: triggers sync27
27 "0"
sync26
1: triggers sync26
26 "0"
sync25
1: triggers sync25
25 "0"
sync24
1: triggers sync24
24 "0"
sync23
1: triggers sync23
23 "0"
sync22
1: triggers sync22
22 "0"
sync21
1: triggers sync21
21 "0"
sync20
1: triggers sync20
20 "0"
sync19
1: triggers sync19
19 "0"
sync18
1: triggers sync18
18 "0"
sync17
1: triggers sync17
17 "0"
sync16
1: triggers sync16
16 "0"
sync15
1: triggers sync15
15 "0"
sync14
1: triggers sync14
14 "0"
sync13
1: triggers sync13
13 "0"
sync12
1: triggers sync12
12 "0"
sync11
1: triggers sync11
11 "0"
sync10
1: triggers sync10
10 "0"
sync9
1: triggers sync9
9 "0"
sync8
1: triggers sync8
8 "0"
sync7
1: triggers sync7
7 "0"
sync6
1: triggers sync6
6 "0"
sync5
1: triggers sync5
5 "0"
sync4
1: triggers sync4
4 "0"
sync3
1: triggers sync3
3 "0"
sync2
1: triggers sync2
2 "0"
sync1
1: triggers sync1 - also used internally by sync module to generates a pulse on sync_out
1 "0"
sync0
1: triggers sync0 - also used internally by sync module as write sync
0 "0"
read_sync
1: triggers a read sync


sync_write_sync_ctrl
Write Sync
When a write sync occurs all write sync (*_WS) registers which have their corresponding WRITE_SYNC_CTRL.*written flags set are transfered to their corresponding state registers.
The write sync is connected to sync generator sync[0].
R/W
0x00000000
Address@com_sync_timer : 0x0640080c
Address@com_sync_timer_global : 0x06400c0c
Address@app_sync_timer : 0x4008080c
Address@app_sync_timer_global : 0x40080c0c
Address@mot_sync_timer : 0x49200c0c
Address@mot_sync_timer_global : 0x4920100c
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
sub_phase_ws_written

3 "0"
base_phase_ws_written

2 "0"
base_phase_rld_ws_written

1 "0"
timebase_inc_ws_written

0 "0"
timebase_ws_written
1 : TIMEBASE_WS will be transfered to TIMEBASE during the next write_sync pulse.
Set automatically when the CPU writes to TIMEBASE_WS.
Cleared with every write_sync.


sync_timebase_ws
R/W
0x00000000
Address@com_sync_timer : 0x06400810
Address@com_sync_timer_global : 0x06400c10
Address@app_sync_timer : 0x40080810
Address@app_sync_timer_global : 0x40080c10
Address@mot_sync_timer : 0x49200c10
Address@mot_sync_timer_global : 0x49201010
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val



sync_timebase_inc_ws
R/W
0x00000000
Address@com_sync_timer : 0x06400814
Address@com_sync_timer_global : 0x06400c14
Address@app_sync_timer : 0x40080814
Address@app_sync_timer_global : 0x40080c14
Address@mot_sync_timer : 0x49200c14
Address@mot_sync_timer_global : 0x49201014
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val



sync_base_phase_rld_ws
R/W
0x00000000
Address@com_sync_timer : 0x06400818
Address@com_sync_timer_global : 0x06400c18
Address@app_sync_timer : 0x40080818
Address@app_sync_timer_global : 0x40080c18
Address@mot_sync_timer : 0x49200c18
Address@mot_sync_timer_global : 0x49201018
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val



sync_base_phase_ws
R/W
0x00000000
Address@com_sync_timer : 0x0640081c
Address@com_sync_timer_global : 0x06400c1c
Address@app_sync_timer : 0x4008081c
Address@app_sync_timer_global : 0x40080c1c
Address@mot_sync_timer : 0x49200c1c
Address@mot_sync_timer_global : 0x4920101c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val



sync_sub_phase_ws
R/W
0x00000000
Address@com_sync_timer : 0x06400820
Address@com_sync_timer_global : 0x06400c20
Address@app_sync_timer : 0x40080820
Address@app_sync_timer_global : 0x40080c20
Address@mot_sync_timer : 0x49200c20
Address@mot_sync_timer_global : 0x49201020
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 - 11 "0000"
sub_phase_sel
0..15: select SUB_PHASE_? to write on next write sync
10 - 0 0x0
val



sync_timebase
State
The registers TIMEBASE, TIMEBASE_INC, BASE_PHASE* and SUB_PHASE_* represent the dynamic state of the synchronization unit.
Directly writing to these registers is only recommended during startup (CFG.en=0). During operation they shall be set with at precisely defined time using the *_WS registers and a write sync.
R/W
0x00000000
Address@com_sync_timer : 0x06400824
Address@com_sync_timer_global : 0x06400c24
Address@app_sync_timer : 0x40080824
Address@app_sync_timer_global : 0x40080c24
Address@mot_sync_timer : 0x49200c24
Address@mot_sync_timer_global : 0x49201024
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
when CFG.en=1
TIMEBASE <= (TIMEBASE + TIMEBASE_INC) % TIMEBASE_MODULUS in every clock cycle


sync_timebase_inc
R/W
0x00000000
Address@com_sync_timer : 0x06400828
Address@com_sync_timer_global : 0x06400c28
Address@app_sync_timer : 0x40080828
Address@app_sync_timer_global : 0x40080c28
Address@mot_sync_timer : 0x49200c28
Address@mot_sync_timer_global : 0x49201028
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see TIMEBASE


sync_base_phase_rld
R/W
0x00000000
Address@com_sync_timer : 0x0640082c
Address@com_sync_timer_global : 0x06400c2c
Address@app_sync_timer : 0x4008082c
Address@app_sync_timer_global : 0x40080c2c
Address@mot_sync_timer : 0x49200c2c
Address@mot_sync_timer_global : 0x4920102c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see BASE_PHASE. Reload value for BASE_PHASE.


sync_base_phase
R/W
0x00000000
Address@com_sync_timer : 0x06400830
Address@com_sync_timer_global : 0x06400c30
Address@app_sync_timer : 0x40080830
Address@app_sync_timer_global : 0x40080c30
Address@mot_sync_timer : 0x49200c30
Address@mot_sync_timer_global : 0x49201030
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
Decremented by one simultaneously every time TIMEBASE wraps around TIMEBASE_MODULUS. Upon reaching zero BASE_PHASE wraps to BASE_PHASE_RLD and asserts base_phase_rld_evt.
when TIMEBASE overflows (simultaneously)
BASE_PHASE = (BASE_PHASE==0) ? BASE_PHASE_RLD : (BASE_PHASE - 1)


sync_read_sync_cfg
Read Sync
The read sync registers (*_RS) capture the state registers of the sync unit when an sync_in or sync_in_int sync pulse occurs.
R/W
0x00000000
Address@com_sync_timer : 0x06400834
Address@com_sync_timer_global : 0x06400c34
Address@app_sync_timer : 0x40080834
Address@app_sync_timer_global : 0x40080c34
Address@mot_sync_timer : 0x49200c34
Address@mot_sync_timer_global : 0x49201034
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 - 20 "00000"
sync_in_ifil_thres
integral filter threshold for the sync_in input.
19 - 15 "00000"
sub_phase_sel1
0..31: select SUB_PHASE_? for read sync
selected SUB_PHASE will be copied to SUB_PHASE_SEL1_RS at read sync
14 - 10 "00000"
sub_phase_sel0
0..31: select SUB_PHASE_? for read sync
selected SUB_PHASE will be copied to SUB_PHASE_SEL0_RS at read sync
9 - 8 "00"
sync_in_edge
0: rising edge of sync_in signal triggers a read sync
1: falling edge " "
2: both edges " "
7 - 5 "000"
sel_ext_rs
sync_in_ext[sel_ext_rs] will be used, if src is set to use_sync_ext
Not generated (if less then 8) inputs are tied to low.
4 - 2 "000"
sel_int_rs
sync_in_int[sel_int_rs] will be used, if src is set to use_sync_int
Not generated (if less then 8) inputs are tied to low.
1 - 0 "00"
src
0: no read_sync source selected
1: use_sync_int - will use (on-chip) sync_in signal selected via 'sel_int_rs'
2: use_sync_ext - will use (operipheral) sync_ext_in signal selected via 'sel_ext_rs'
3: use_sync_phase - read sync will trigger on each edge of the sync_phase signal


sync_timebase_rs
R
Address@com_sync_timer : 0x06400838
Address@com_sync_timer_global : 0x06400c38
Address@app_sync_timer : 0x40080838
Address@app_sync_timer_global : 0x40080c38
Address@mot_sync_timer : 0x49200c38
Address@mot_sync_timer_global : 0x49201038
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
Captures the corresponding register when a read sync occurs.


sync_base_phase_rs
R
Address@com_sync_timer : 0x0640083c
Address@com_sync_timer_global : 0x06400c3c
Address@app_sync_timer : 0x4008083c
Address@app_sync_timer_global : 0x40080c3c
Address@mot_sync_timer : 0x49200c3c
Address@mot_sync_timer_global : 0x4920103c
Bits Name Description
31 - 16 -
 reserved
15 - 0 val



sync_sub_phase_sel0_rs
R
Address@com_sync_timer : 0x06400840
Address@com_sync_timer_global : 0x06400c40
Address@app_sync_timer : 0x40080840
Address@app_sync_timer_global : 0x40080c40
Address@mot_sync_timer : 0x49200c40
Address@mot_sync_timer_global : 0x49201040
Bits Name Description
31 - 11 -
 reserved
10 - 0 val



sync_sub_phase_sel1_rs
R
Address@com_sync_timer : 0x06400844
Address@com_sync_timer_global : 0x06400c44
Address@app_sync_timer : 0x40080844
Address@app_sync_timer_global : 0x40080c44
Address@mot_sync_timer : 0x49200c44
Address@mot_sync_timer_global : 0x49201044
Bits Name Description
31 - 11 -
 reserved
10 - 0 val



sync_irq_raw
Writing a '1' to a bit position with an event type IRQ will clear the event flag.
Writing to bit positions with a 'status' type IRQ has no effect.
R/W
0x00000000
Address@com_sync_timer : 0x06400848
Address@com_sync_timer_global : 0x06400c48
Address@app_sync_timer : 0x40080848
Address@app_sync_timer_global : 0x40080c48
Address@mot_sync_timer : 0x49200c48
Address@mot_sync_timer_global : 0x49201048
Bits Reset value Name Description
31 "0"
sync29_evt
EVENT:
30 "0"
sync28_evt
EVENT:
29 "0"
sync27_evt
EVENT:
28 "0"
sync26_evt
EVENT:
27 "0"
sync25_evt
EVENT:
26 "0"
sync24_evt
EVENT:
25 "0"
sync23_evt
EVENT:
24 "0"
sync22_evt
EVENT:
23 "0"
sync21_evt
EVENT:
22 "0"
sync20_evt
EVENT:
21 "0"
sync19_evt
EVENT:
20 "0"
sync18_evt
EVENT:
19 "0"
sync17_evt
EVENT:
18 "0"
sync16_evt
EVENT:
17 "0"
sync15_evt
EVENT:
16 "0"
sync14_evt
EVENT:
15 "0"
sync13_evt
EVENT:
14 "0"
sync12_evt
EVENT:
13 "0"
sync11_evt
EVENT:
12 "0"
sync10_evt
EVENT:
11 "0"
sync9_evt
EVENT:
10 "0"
sync8_evt
EVENT:
9 "0"
sync7_evt
EVENT:
8 "0"
sync6_evt
EVENT:
7 "0"
sync5_evt
EVENT:
6 "0"
sync4_evt
EVENT:
5 "0"
sync3_evt
EVENT:
4 "0"
sync2_evt
EVENT:
3 "0"
sync1_evt
EVENT:
2 "0"
sync0_evt
EVENT: 1: sync0 occurred
1 "0"
read_sync_evt
EVENT: 1: read sync event occurred
0 "0"
base_phase_rld_evt
EVENT: 1: BASE_PHASE was reloaded with BASE_PHASE_RLD


sync_irq_masked
Shows status of masked IRQs (as connected to IRQ controller).
R
Address@com_sync_timer : 0x0640084c
Address@com_sync_timer_global : 0x06400c4c
Address@app_sync_timer : 0x4008084c
Address@app_sync_timer_global : 0x40080c4c
Address@mot_sync_timer : 0x49200c4c
Address@mot_sync_timer_global : 0x4920104c
Bits Name Description
31 sync29_evt
EVENT:
30 sync28_evt
EVENT:
29 sync27_evt
EVENT:
28 sync26_evt
EVENT:
27 sync25_evt
EVENT:
26 sync24_evt
EVENT:
25 sync23_evt
EVENT:
24 sync22_evt
EVENT:
23 sync21_evt
EVENT:
22 sync20_evt
EVENT:
21 sync19_evt
EVENT:
20 sync18_evt
EVENT:
19 sync17_evt
EVENT:
18 sync16_evt
EVENT:
17 sync15_evt
EVENT:
16 sync14_evt
EVENT:
15 sync13_evt
EVENT:
14 sync12_evt
EVENT:
13 sync11_evt
EVENT:
12 sync10_evt
EVENT:
11 sync9_evt
EVENT:
10 sync8_evt
EVENT:
9 sync7_evt
EVENT:
8 sync6_evt
EVENT:
7 sync5_evt
EVENT:
6 sync4_evt
EVENT:
5 sync3_evt
EVENT:
4 sync2_evt
EVENT:
3 sync1_evt
EVENT:
2 sync0_evt
EVENT:
1 read_sync_evt
EVENT:
0 base_phase_rld_evt
EVENT:


sync_irq_msk_set
R/W
0x00000000
Address@com_sync_timer : 0x06400850
Address@com_sync_timer_global : 0x06400c50
Address@app_sync_timer : 0x40080850
Address@app_sync_timer_global : 0x40080c50
Address@mot_sync_timer : 0x49200c50
Address@mot_sync_timer_global : 0x49201050
Bits Reset value Name Description
31 "0"
sync29_evt

30 "0"
sync28_evt

29 "0"
sync27_evt

28 "0"
sync26_evt

27 "0"
sync25_evt

26 "0"
sync24_evt

25 "0"
sync23_evt

24 "0"
sync22_evt

23 "0"
sync21_evt

22 "0"
sync20_evt

21 "0"
sync19_evt

20 "0"
sync18_evt

19 "0"
sync17_evt

18 "0"
sync16_evt

17 "0"
sync15_evt

16 "0"
sync14_evt

15 "0"
sync13_evt

14 "0"
sync12_evt

13 "0"
sync11_evt

12 "0"
sync10_evt

11 "0"
sync9_evt

10 "0"
sync8_evt

9 "0"
sync7_evt

8 "0"
sync6_evt

7 "0"
sync5_evt

6 "0"
sync4_evt

5 "0"
sync3_evt

4 "0"
sync2_evt

3 "0"
sync1_evt

2 "0"
sync0_evt

1 "0"
read_sync_evt

0 "0"
base_phase_rld_evt
Write: 1: set the corresponding bit in the IRQ mask
Read: returns IRQ mask


sync_irq_msk_reset
R/W
0x00000000
Address@com_sync_timer : 0x06400854
Address@com_sync_timer_global : 0x06400c54
Address@app_sync_timer : 0x40080854
Address@app_sync_timer_global : 0x40080c54
Address@mot_sync_timer : 0x49200c54
Address@mot_sync_timer_global : 0x49201054
Bits Reset value Name Description
31 "0"
sync29_evt

30 "0"
sync28_evt

29 "0"
sync27_evt

28 "0"
sync26_evt

27 "0"
sync25_evt

26 "0"
sync24_evt

25 "0"
sync23_evt

24 "0"
sync22_evt

23 "0"
sync21_evt

22 "0"
sync20_evt

21 "0"
sync19_evt

20 "0"
sync18_evt

19 "0"
sync17_evt

18 "0"
sync16_evt

17 "0"
sync15_evt

16 "0"
sync14_evt

15 "0"
sync13_evt

14 "0"
sync12_evt

13 "0"
sync11_evt

12 "0"
sync10_evt

11 "0"
sync9_evt

10 "0"
sync8_evt

9 "0"
sync7_evt

8 "0"
sync6_evt

7 "0"
sync5_evt

6 "0"
sync4_evt

5 "0"
sync3_evt

4 "0"
sync2_evt

3 "0"
sync1_evt

2 "0"
sync0_evt

1 "0"
read_sync_evt

0 "0"
base_phase_rld_evt
Write: 1: clear the corresponding bit in the IRQ mask
Read: returns IRQ mask


sync_irq_no
R
Address@com_sync_timer : 0x06400858
Address@com_sync_timer_global : 0x06400c58
Address@app_sync_timer : 0x40080858
Address@app_sync_timer_global : 0x40080c58
Address@mot_sync_timer : 0x49200c58
Address@mot_sync_timer_global : 0x49201058
Bits Name Description
31 - 6 -
 reserved
5 - 0 val
Number of the non-masked pending IRQ with the highest priority (=lowest bit position). When no non-masked IRQ is pending the number of the highest IRQ plus one is returned.


sync_reload_configuration
R/W
0x00000000
Address@com_sync_timer : 0x0640085c
Address@com_sync_timer_global : 0x06400c5c
Address@app_sync_timer : 0x4008085c
Address@app_sync_timer_global : 0x40080c5c
Address@mot_sync_timer : 0x49200c5c
Address@mot_sync_timer_global : 0x4920105c
Bits Reset value Name Description
31 - 16 0x0
autorld_sub_phases
Each bit determines if the corresponding sub_phase offset will be reloaded on a write_sync
The value reloaded must be configured beforehand in the 'reload_sub_phase_offset_X' registers.
X corresponds to the sub_phase number (max. of 16).
15 - 2 0
-
 reserved
1 "0"
autorld_base_phase
If set, 'base_phase' will be reloaded on each write_sync.
The value reloaded is determined by what was last written to the 'base_phase_ws' register.
0 "0"
autorld_timebase
If set, 'timebase' will be reloaded on each write_sync.
The value reloaded is determined by what was last written to the 'timebase_ws' register.


sync_sub_phase_0_rld
SUB_PHASE_0 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400860
Address@com_sync_timer_global : 0x06400c60
Address@app_sync_timer : 0x40080860
Address@app_sync_timer_global : 0x40080c60
Address@mot_sync_timer : 0x49200c60
Address@mot_sync_timer_global : 0x49201060
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 0


sync_sub_phase_0
R/W
0x00000000
Address@com_sync_timer : 0x06400864
Address@com_sync_timer_global : 0x06400c64
Address@app_sync_timer : 0x40080864
Address@app_sync_timer_global : 0x40080c64
Address@mot_sync_timer : 0x49200c64
Address@mot_sync_timer_global : 0x49201064
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_0 wraps to SUB_PHASE0_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_0= (SUB_PHASE_0==0) ? SUB_PHASE_0_RLD : (SUB_PHASE_0-1)


sync_reload_sub_phase_offset_0
Sub_phase 0 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400868
Address@com_sync_timer_global : 0x06400c68
Address@app_sync_timer : 0x40080868
Address@app_sync_timer_global : 0x40080c68
Address@mot_sync_timer : 0x49200c68
Address@mot_sync_timer_global : 0x49201068
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 0 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_1_rld
SUB_PHASE_1 reload register
R/W
0x00000000
Address@com_sync_timer : 0x0640086c
Address@com_sync_timer_global : 0x06400c6c
Address@app_sync_timer : 0x4008086c
Address@app_sync_timer_global : 0x40080c6c
Address@mot_sync_timer : 0x49200c6c
Address@mot_sync_timer_global : 0x4920106c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 1


sync_sub_phase_1
R/W
0x00000000
Address@com_sync_timer : 0x06400870
Address@com_sync_timer_global : 0x06400c70
Address@app_sync_timer : 0x40080870
Address@app_sync_timer_global : 0x40080c70
Address@mot_sync_timer : 0x49200c70
Address@mot_sync_timer_global : 0x49201070
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_1 wraps to SUB_PHASE1_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_1= (SUB_PHASE_1==0) ? SUB_PHASE_1_RLD : (SUB_PHASE_1-1)


sync_reload_sub_phase_offset_1
Sub_phase 1 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400874
Address@com_sync_timer_global : 0x06400c74
Address@app_sync_timer : 0x40080874
Address@app_sync_timer_global : 0x40080c74
Address@mot_sync_timer : 0x49200c74
Address@mot_sync_timer_global : 0x49201074
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 1 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_2_rld
SUB_PHASE_2 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400878
Address@com_sync_timer_global : 0x06400c78
Address@app_sync_timer : 0x40080878
Address@app_sync_timer_global : 0x40080c78
Address@mot_sync_timer : 0x49200c78
Address@mot_sync_timer_global : 0x49201078
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 2


sync_sub_phase_2
R/W
0x00000000
Address@com_sync_timer : 0x0640087c
Address@com_sync_timer_global : 0x06400c7c
Address@app_sync_timer : 0x4008087c
Address@app_sync_timer_global : 0x40080c7c
Address@mot_sync_timer : 0x49200c7c
Address@mot_sync_timer_global : 0x4920107c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_2 wraps to SUB_PHASE2_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_2= (SUB_PHASE_2==0) ? SUB_PHASE_2_RLD : (SUB_PHASE_2-1)


sync_reload_sub_phase_offset_2
Sub_phase 2 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400880
Address@com_sync_timer_global : 0x06400c80
Address@app_sync_timer : 0x40080880
Address@app_sync_timer_global : 0x40080c80
Address@mot_sync_timer : 0x49200c80
Address@mot_sync_timer_global : 0x49201080
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 2 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_3_rld
SUB_PHASE_3 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400884
Address@com_sync_timer_global : 0x06400c84
Address@app_sync_timer : 0x40080884
Address@app_sync_timer_global : 0x40080c84
Address@mot_sync_timer : 0x49200c84
Address@mot_sync_timer_global : 0x49201084
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 3


sync_sub_phase_3
R/W
0x00000000
Address@com_sync_timer : 0x06400888
Address@com_sync_timer_global : 0x06400c88
Address@app_sync_timer : 0x40080888
Address@app_sync_timer_global : 0x40080c88
Address@mot_sync_timer : 0x49200c88
Address@mot_sync_timer_global : 0x49201088
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_3 wraps to SUB_PHASE3_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_3= (SUB_PHASE_3==0) ? SUB_PHASE_3_RLD : (SUB_PHASE_3-1)


sync_reload_sub_phase_offset_3
Sub_phase 3 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x0640088c
Address@com_sync_timer_global : 0x06400c8c
Address@app_sync_timer : 0x4008088c
Address@app_sync_timer_global : 0x40080c8c
Address@mot_sync_timer : 0x49200c8c
Address@mot_sync_timer_global : 0x4920108c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 3 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_4_rld
SUB_PHASE_4 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400890
Address@com_sync_timer_global : 0x06400c90
Address@app_sync_timer : 0x40080890
Address@app_sync_timer_global : 0x40080c90
Address@mot_sync_timer : 0x49200c90
Address@mot_sync_timer_global : 0x49201090
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 4


sync_sub_phase_4
R/W
0x00000000
Address@com_sync_timer : 0x06400894
Address@com_sync_timer_global : 0x06400c94
Address@app_sync_timer : 0x40080894
Address@app_sync_timer_global : 0x40080c94
Address@mot_sync_timer : 0x49200c94
Address@mot_sync_timer_global : 0x49201094
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_4 wraps to SUB_PHASE4_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_4= (SUB_PHASE_4==0) ? SUB_PHASE_4_RLD : (SUB_PHASE_4-1)


sync_reload_sub_phase_offset_4
Sub_phase 4 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400898
Address@com_sync_timer_global : 0x06400c98
Address@app_sync_timer : 0x40080898
Address@app_sync_timer_global : 0x40080c98
Address@mot_sync_timer : 0x49200c98
Address@mot_sync_timer_global : 0x49201098
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 4 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_5_rld
SUB_PHASE_5 reload register
R/W
0x00000000
Address@com_sync_timer : 0x0640089c
Address@com_sync_timer_global : 0x06400c9c
Address@app_sync_timer : 0x4008089c
Address@app_sync_timer_global : 0x40080c9c
Address@mot_sync_timer : 0x49200c9c
Address@mot_sync_timer_global : 0x4920109c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 5


sync_sub_phase_5
R/W
0x00000000
Address@com_sync_timer : 0x064008a0
Address@com_sync_timer_global : 0x06400ca0
Address@app_sync_timer : 0x400808a0
Address@app_sync_timer_global : 0x40080ca0
Address@mot_sync_timer : 0x49200ca0
Address@mot_sync_timer_global : 0x492010a0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_5 wraps to SUB_PHASE5_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_5= (SUB_PHASE_5==0) ? SUB_PHASE_5_RLD : (SUB_PHASE_5-1)


sync_reload_sub_phase_offset_5
Sub_phase 5 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008a4
Address@com_sync_timer_global : 0x06400ca4
Address@app_sync_timer : 0x400808a4
Address@app_sync_timer_global : 0x40080ca4
Address@mot_sync_timer : 0x49200ca4
Address@mot_sync_timer_global : 0x492010a4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 5 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_6_rld
SUB_PHASE_6 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008a8
Address@com_sync_timer_global : 0x06400ca8
Address@app_sync_timer : 0x400808a8
Address@app_sync_timer_global : 0x40080ca8
Address@mot_sync_timer : 0x49200ca8
Address@mot_sync_timer_global : 0x492010a8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 6


sync_sub_phase_6
R/W
0x00000000
Address@com_sync_timer : 0x064008ac
Address@com_sync_timer_global : 0x06400cac
Address@app_sync_timer : 0x400808ac
Address@app_sync_timer_global : 0x40080cac
Address@mot_sync_timer : 0x49200cac
Address@mot_sync_timer_global : 0x492010ac
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_6 wraps to SUB_PHASE6_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_6= (SUB_PHASE_6==0) ? SUB_PHASE_6_RLD : (SUB_PHASE_6-1)


sync_reload_sub_phase_offset_6
Sub_phase 6 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008b0
Address@com_sync_timer_global : 0x06400cb0
Address@app_sync_timer : 0x400808b0
Address@app_sync_timer_global : 0x40080cb0
Address@mot_sync_timer : 0x49200cb0
Address@mot_sync_timer_global : 0x492010b0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 6 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_7_rld
SUB_PHASE_7 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008b4
Address@com_sync_timer_global : 0x06400cb4
Address@app_sync_timer : 0x400808b4
Address@app_sync_timer_global : 0x40080cb4
Address@mot_sync_timer : 0x49200cb4
Address@mot_sync_timer_global : 0x492010b4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 7


sync_sub_phase_7
R/W
0x00000000
Address@com_sync_timer : 0x064008b8
Address@com_sync_timer_global : 0x06400cb8
Address@app_sync_timer : 0x400808b8
Address@app_sync_timer_global : 0x40080cb8
Address@mot_sync_timer : 0x49200cb8
Address@mot_sync_timer_global : 0x492010b8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_7 wraps to SUB_PHASE7_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_7= (SUB_PHASE_7==0) ? SUB_PHASE_7_RLD : (SUB_PHASE_7-1)


sync_reload_sub_phase_offset_7
Sub_phase 7 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008bc
Address@com_sync_timer_global : 0x06400cbc
Address@app_sync_timer : 0x400808bc
Address@app_sync_timer_global : 0x40080cbc
Address@mot_sync_timer : 0x49200cbc
Address@mot_sync_timer_global : 0x492010bc
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 7 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_8_rld
SUB_PHASE_8 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008c0
Address@com_sync_timer_global : 0x06400cc0
Address@app_sync_timer : 0x400808c0
Address@app_sync_timer_global : 0x40080cc0
Address@mot_sync_timer : 0x49200cc0
Address@mot_sync_timer_global : 0x492010c0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 8


sync_sub_phase_8
R/W
0x00000000
Address@com_sync_timer : 0x064008c4
Address@com_sync_timer_global : 0x06400cc4
Address@app_sync_timer : 0x400808c4
Address@app_sync_timer_global : 0x40080cc4
Address@mot_sync_timer : 0x49200cc4
Address@mot_sync_timer_global : 0x492010c4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_8 wraps to SUB_PHASE8_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_8= (SUB_PHASE_8==0) ? SUB_PHASE_8_RLD : (SUB_PHASE_8-1)


sync_reload_sub_phase_offset_8
Sub_phase 8 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008c8
Address@com_sync_timer_global : 0x06400cc8
Address@app_sync_timer : 0x400808c8
Address@app_sync_timer_global : 0x40080cc8
Address@mot_sync_timer : 0x49200cc8
Address@mot_sync_timer_global : 0x492010c8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 8 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_9_rld
SUB_PHASE_9 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008cc
Address@com_sync_timer_global : 0x06400ccc
Address@app_sync_timer : 0x400808cc
Address@app_sync_timer_global : 0x40080ccc
Address@mot_sync_timer : 0x49200ccc
Address@mot_sync_timer_global : 0x492010cc
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 9


sync_sub_phase_9
R/W
0x00000000
Address@com_sync_timer : 0x064008d0
Address@com_sync_timer_global : 0x06400cd0
Address@app_sync_timer : 0x400808d0
Address@app_sync_timer_global : 0x40080cd0
Address@mot_sync_timer : 0x49200cd0
Address@mot_sync_timer_global : 0x492010d0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_9 wraps to SUB_PHASE9_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_9= (SUB_PHASE_9==0) ? SUB_PHASE_9_RLD : (SUB_PHASE_9-1)


sync_reload_sub_phase_offset_9
Sub_phase 9 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008d4
Address@com_sync_timer_global : 0x06400cd4
Address@app_sync_timer : 0x400808d4
Address@app_sync_timer_global : 0x40080cd4
Address@mot_sync_timer : 0x49200cd4
Address@mot_sync_timer_global : 0x492010d4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 9 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_10_rld
SUB_PHASE_10 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008d8
Address@com_sync_timer_global : 0x06400cd8
Address@app_sync_timer : 0x400808d8
Address@app_sync_timer_global : 0x40080cd8
Address@mot_sync_timer : 0x49200cd8
Address@mot_sync_timer_global : 0x492010d8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 10


sync_sub_phase_10
R/W
0x00000000
Address@com_sync_timer : 0x064008dc
Address@com_sync_timer_global : 0x06400cdc
Address@app_sync_timer : 0x400808dc
Address@app_sync_timer_global : 0x40080cdc
Address@mot_sync_timer : 0x49200cdc
Address@mot_sync_timer_global : 0x492010dc
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_10 wraps to SUB_PHASE10_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_10= (SUB_PHASE_10==0) ? SUB_PHASE_10_RLD : (SUB_PHASE_10-1)


sync_reload_sub_phase_offset_10
Sub_phase 10 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008e0
Address@com_sync_timer_global : 0x06400ce0
Address@app_sync_timer : 0x400808e0
Address@app_sync_timer_global : 0x40080ce0
Address@mot_sync_timer : 0x49200ce0
Address@mot_sync_timer_global : 0x492010e0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 10 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_11_rld
SUB_PHASE_11 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008e4
Address@com_sync_timer_global : 0x06400ce4
Address@app_sync_timer : 0x400808e4
Address@app_sync_timer_global : 0x40080ce4
Address@mot_sync_timer : 0x49200ce4
Address@mot_sync_timer_global : 0x492010e4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 11


sync_sub_phase_11
R/W
0x00000000
Address@com_sync_timer : 0x064008e8
Address@com_sync_timer_global : 0x06400ce8
Address@app_sync_timer : 0x400808e8
Address@app_sync_timer_global : 0x40080ce8
Address@mot_sync_timer : 0x49200ce8
Address@mot_sync_timer_global : 0x492010e8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_11 wraps to SUB_PHASE11_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_11= (SUB_PHASE_11==0) ? SUB_PHASE_11_RLD : (SUB_PHASE_11-1)


sync_reload_sub_phase_offset_11
Sub_phase 11 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008ec
Address@com_sync_timer_global : 0x06400cec
Address@app_sync_timer : 0x400808ec
Address@app_sync_timer_global : 0x40080cec
Address@mot_sync_timer : 0x49200cec
Address@mot_sync_timer_global : 0x492010ec
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 11 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_12_rld
SUB_PHASE_12 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008f0
Address@com_sync_timer_global : 0x06400cf0
Address@app_sync_timer : 0x400808f0
Address@app_sync_timer_global : 0x40080cf0
Address@mot_sync_timer : 0x49200cf0
Address@mot_sync_timer_global : 0x492010f0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 12


sync_sub_phase_12
R/W
0x00000000
Address@com_sync_timer : 0x064008f4
Address@com_sync_timer_global : 0x06400cf4
Address@app_sync_timer : 0x400808f4
Address@app_sync_timer_global : 0x40080cf4
Address@mot_sync_timer : 0x49200cf4
Address@mot_sync_timer_global : 0x492010f4
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_12 wraps to SUB_PHASE12_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_12= (SUB_PHASE_12==0) ? SUB_PHASE_12_RLD : (SUB_PHASE_12-1)


sync_reload_sub_phase_offset_12
Sub_phase 12 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x064008f8
Address@com_sync_timer_global : 0x06400cf8
Address@app_sync_timer : 0x400808f8
Address@app_sync_timer_global : 0x40080cf8
Address@mot_sync_timer : 0x49200cf8
Address@mot_sync_timer_global : 0x492010f8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 12 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_13_rld
SUB_PHASE_13 reload register
R/W
0x00000000
Address@com_sync_timer : 0x064008fc
Address@com_sync_timer_global : 0x06400cfc
Address@app_sync_timer : 0x400808fc
Address@app_sync_timer_global : 0x40080cfc
Address@mot_sync_timer : 0x49200cfc
Address@mot_sync_timer_global : 0x492010fc
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 13


sync_sub_phase_13
R/W
0x00000000
Address@com_sync_timer : 0x06400900
Address@com_sync_timer_global : 0x06400d00
Address@app_sync_timer : 0x40080900
Address@app_sync_timer_global : 0x40080d00
Address@mot_sync_timer : 0x49200d00
Address@mot_sync_timer_global : 0x49201100
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_13 wraps to SUB_PHASE13_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_13= (SUB_PHASE_13==0) ? SUB_PHASE_13_RLD : (SUB_PHASE_13-1)


sync_reload_sub_phase_offset_13
Sub_phase 13 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400904
Address@com_sync_timer_global : 0x06400d04
Address@app_sync_timer : 0x40080904
Address@app_sync_timer_global : 0x40080d04
Address@mot_sync_timer : 0x49200d04
Address@mot_sync_timer_global : 0x49201104
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 13 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_14_rld
SUB_PHASE_14 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400908
Address@com_sync_timer_global : 0x06400d08
Address@app_sync_timer : 0x40080908
Address@app_sync_timer_global : 0x40080d08
Address@mot_sync_timer : 0x49200d08
Address@mot_sync_timer_global : 0x49201108
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 14


sync_sub_phase_14
R/W
0x00000000
Address@com_sync_timer : 0x0640090c
Address@com_sync_timer_global : 0x06400d0c
Address@app_sync_timer : 0x4008090c
Address@app_sync_timer_global : 0x40080d0c
Address@mot_sync_timer : 0x49200d0c
Address@mot_sync_timer_global : 0x4920110c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_14 wraps to SUB_PHASE14_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_14= (SUB_PHASE_14==0) ? SUB_PHASE_14_RLD : (SUB_PHASE_14-1)


sync_reload_sub_phase_offset_14
Sub_phase 14 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x06400910
Address@com_sync_timer_global : 0x06400d10
Address@app_sync_timer : 0x40080910
Address@app_sync_timer_global : 0x40080d10
Address@mot_sync_timer : 0x49200d10
Address@mot_sync_timer_global : 0x49201110
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 14 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sub_phase_15_rld
SUB_PHASE_15 reload register
R/W
0x00000000
Address@com_sync_timer : 0x06400914
Address@com_sync_timer_global : 0x06400d14
Address@app_sync_timer : 0x40080914
Address@app_sync_timer_global : 0x40080d14
Address@mot_sync_timer : 0x49200d14
Address@mot_sync_timer_global : 0x49201114
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
see SUB_PHASE. Reload value for sub phase 15


sync_sub_phase_15
R/W
0x00000000
Address@com_sync_timer : 0x06400918
Address@com_sync_timer_global : 0x06400d18
Address@app_sync_timer : 0x40080918
Address@app_sync_timer_global : 0x40080d18
Address@mot_sync_timer : 0x49200d18
Address@mot_sync_timer_global : 0x49201118
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
val
Decremented by one simultaneously every time BASE_PHASE wraps to BASE_PHASE_RLD. Upon reaching zero SUB_PHASE_15 wraps to SUB_PHASE15_RLD.
when BASE_PHASE underflows (simultaneously)
SUB_PHASE_15= (SUB_PHASE_15==0) ? SUB_PHASE_15_RLD : (SUB_PHASE_15-1)


sync_reload_sub_phase_offset_15
Sub_phase 15 reload value register
R/W
0x00000000
Address@com_sync_timer : 0x0640091c
Address@com_sync_timer_global : 0x06400d1c
Address@app_sync_timer : 0x4008091c
Address@app_sync_timer_global : 0x40080d1c
Address@mot_sync_timer : 0x49200d1c
Address@mot_sync_timer_global : 0x4920111c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x0
reload_value
sub_phase 15 offset to load into sub_phase counter if the corresponding
autorld_sub_phases bit is set in the reload configuration register


sync_sync_gen_0_cfg
Sync signal generator 0 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400920
Address@com_sync_timer_global : 0x06400d20
Address@app_sync_timer : 0x40080920
Address@app_sync_timer_global : 0x40080d20
Address@mot_sync_timer : 0x49200d20
Address@mot_sync_timer_global : 0x49201120
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_0_base_phase
Sync signal generator 0 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400924
Address@com_sync_timer_global : 0x06400d24
Address@app_sync_timer : 0x40080924
Address@app_sync_timer_global : 0x40080d24
Address@mot_sync_timer : 0x49200d24
Address@mot_sync_timer_global : 0x49201124
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_1_cfg
Sync signal generator 1 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400928
Address@com_sync_timer_global : 0x06400d28
Address@app_sync_timer : 0x40080928
Address@app_sync_timer_global : 0x40080d28
Address@mot_sync_timer : 0x49200d28
Address@mot_sync_timer_global : 0x49201128
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_1_base_phase
Sync signal generator 1 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640092c
Address@com_sync_timer_global : 0x06400d2c
Address@app_sync_timer : 0x4008092c
Address@app_sync_timer_global : 0x40080d2c
Address@mot_sync_timer : 0x49200d2c
Address@mot_sync_timer_global : 0x4920112c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_2_cfg
Sync signal generator 2 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400930
Address@com_sync_timer_global : 0x06400d30
Address@app_sync_timer : 0x40080930
Address@app_sync_timer_global : 0x40080d30
Address@mot_sync_timer : 0x49200d30
Address@mot_sync_timer_global : 0x49201130
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_2_base_phase
Sync signal generator 2 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400934
Address@com_sync_timer_global : 0x06400d34
Address@app_sync_timer : 0x40080934
Address@app_sync_timer_global : 0x40080d34
Address@mot_sync_timer : 0x49200d34
Address@mot_sync_timer_global : 0x49201134
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_3_cfg
Sync signal generator 3 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400938
Address@com_sync_timer_global : 0x06400d38
Address@app_sync_timer : 0x40080938
Address@app_sync_timer_global : 0x40080d38
Address@mot_sync_timer : 0x49200d38
Address@mot_sync_timer_global : 0x49201138
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_3_base_phase
Sync signal generator 3 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640093c
Address@com_sync_timer_global : 0x06400d3c
Address@app_sync_timer : 0x4008093c
Address@app_sync_timer_global : 0x40080d3c
Address@mot_sync_timer : 0x49200d3c
Address@mot_sync_timer_global : 0x4920113c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_4_cfg
Sync signal generator 4 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400940
Address@com_sync_timer_global : 0x06400d40
Address@app_sync_timer : 0x40080940
Address@app_sync_timer_global : 0x40080d40
Address@mot_sync_timer : 0x49200d40
Address@mot_sync_timer_global : 0x49201140
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_4_base_phase
Sync signal generator 4 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400944
Address@com_sync_timer_global : 0x06400d44
Address@app_sync_timer : 0x40080944
Address@app_sync_timer_global : 0x40080d44
Address@mot_sync_timer : 0x49200d44
Address@mot_sync_timer_global : 0x49201144
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_5_cfg
Sync signal generator 5 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400948
Address@com_sync_timer_global : 0x06400d48
Address@app_sync_timer : 0x40080948
Address@app_sync_timer_global : 0x40080d48
Address@mot_sync_timer : 0x49200d48
Address@mot_sync_timer_global : 0x49201148
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_5_base_phase
Sync signal generator 5 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640094c
Address@com_sync_timer_global : 0x06400d4c
Address@app_sync_timer : 0x4008094c
Address@app_sync_timer_global : 0x40080d4c
Address@mot_sync_timer : 0x49200d4c
Address@mot_sync_timer_global : 0x4920114c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_6_cfg
Sync signal generator 6 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400950
Address@com_sync_timer_global : 0x06400d50
Address@app_sync_timer : 0x40080950
Address@app_sync_timer_global : 0x40080d50
Address@mot_sync_timer : 0x49200d50
Address@mot_sync_timer_global : 0x49201150
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_6_base_phase
Sync signal generator 6 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400954
Address@com_sync_timer_global : 0x06400d54
Address@app_sync_timer : 0x40080954
Address@app_sync_timer_global : 0x40080d54
Address@mot_sync_timer : 0x49200d54
Address@mot_sync_timer_global : 0x49201154
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_7_cfg
Sync signal generator 7 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400958
Address@com_sync_timer_global : 0x06400d58
Address@app_sync_timer : 0x40080958
Address@app_sync_timer_global : 0x40080d58
Address@mot_sync_timer : 0x49200d58
Address@mot_sync_timer_global : 0x49201158
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_7_base_phase
Sync signal generator 7 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640095c
Address@com_sync_timer_global : 0x06400d5c
Address@app_sync_timer : 0x4008095c
Address@app_sync_timer_global : 0x40080d5c
Address@mot_sync_timer : 0x49200d5c
Address@mot_sync_timer_global : 0x4920115c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_8_cfg
Sync signal generator 8 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400960
Address@com_sync_timer_global : 0x06400d60
Address@app_sync_timer : 0x40080960
Address@app_sync_timer_global : 0x40080d60
Address@mot_sync_timer : 0x49200d60
Address@mot_sync_timer_global : 0x49201160
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_8_base_phase
Sync signal generator 8 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400964
Address@com_sync_timer_global : 0x06400d64
Address@app_sync_timer : 0x40080964
Address@app_sync_timer_global : 0x40080d64
Address@mot_sync_timer : 0x49200d64
Address@mot_sync_timer_global : 0x49201164
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_9_cfg
Sync signal generator 9 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400968
Address@com_sync_timer_global : 0x06400d68
Address@app_sync_timer : 0x40080968
Address@app_sync_timer_global : 0x40080d68
Address@mot_sync_timer : 0x49200d68
Address@mot_sync_timer_global : 0x49201168
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_9_base_phase
Sync signal generator 9 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640096c
Address@com_sync_timer_global : 0x06400d6c
Address@app_sync_timer : 0x4008096c
Address@app_sync_timer_global : 0x40080d6c
Address@mot_sync_timer : 0x49200d6c
Address@mot_sync_timer_global : 0x4920116c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_10_cfg
Sync signal generator 10 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400970
Address@com_sync_timer_global : 0x06400d70
Address@app_sync_timer : 0x40080970
Address@app_sync_timer_global : 0x40080d70
Address@mot_sync_timer : 0x49200d70
Address@mot_sync_timer_global : 0x49201170
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_10_base_phase
Sync signal generator 10 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400974
Address@com_sync_timer_global : 0x06400d74
Address@app_sync_timer : 0x40080974
Address@app_sync_timer_global : 0x40080d74
Address@mot_sync_timer : 0x49200d74
Address@mot_sync_timer_global : 0x49201174
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_11_cfg
Sync signal generator 11 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400978
Address@com_sync_timer_global : 0x06400d78
Address@app_sync_timer : 0x40080978
Address@app_sync_timer_global : 0x40080d78
Address@mot_sync_timer : 0x49200d78
Address@mot_sync_timer_global : 0x49201178
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_11_base_phase
Sync signal generator 11 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640097c
Address@com_sync_timer_global : 0x06400d7c
Address@app_sync_timer : 0x4008097c
Address@app_sync_timer_global : 0x40080d7c
Address@mot_sync_timer : 0x49200d7c
Address@mot_sync_timer_global : 0x4920117c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_12_cfg
Sync signal generator 12 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400980
Address@com_sync_timer_global : 0x06400d80
Address@app_sync_timer : 0x40080980
Address@app_sync_timer_global : 0x40080d80
Address@mot_sync_timer : 0x49200d80
Address@mot_sync_timer_global : 0x49201180
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_12_base_phase
Sync signal generator 12 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400984
Address@com_sync_timer_global : 0x06400d84
Address@app_sync_timer : 0x40080984
Address@app_sync_timer_global : 0x40080d84
Address@mot_sync_timer : 0x49200d84
Address@mot_sync_timer_global : 0x49201184
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_13_cfg
Sync signal generator 13 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400988
Address@com_sync_timer_global : 0x06400d88
Address@app_sync_timer : 0x40080988
Address@app_sync_timer_global : 0x40080d88
Address@mot_sync_timer : 0x49200d88
Address@mot_sync_timer_global : 0x49201188
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_13_base_phase
Sync signal generator 13 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640098c
Address@com_sync_timer_global : 0x06400d8c
Address@app_sync_timer : 0x4008098c
Address@app_sync_timer_global : 0x40080d8c
Address@mot_sync_timer : 0x49200d8c
Address@mot_sync_timer_global : 0x4920118c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_14_cfg
Sync signal generator 14 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400990
Address@com_sync_timer_global : 0x06400d90
Address@app_sync_timer : 0x40080990
Address@app_sync_timer_global : 0x40080d90
Address@mot_sync_timer : 0x49200d90
Address@mot_sync_timer_global : 0x49201190
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_14_base_phase
Sync signal generator 14 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400994
Address@com_sync_timer_global : 0x06400d94
Address@app_sync_timer : 0x40080994
Address@app_sync_timer_global : 0x40080d94
Address@mot_sync_timer : 0x49200d94
Address@mot_sync_timer_global : 0x49201194
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_15_cfg
Sync signal generator 15 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400998
Address@com_sync_timer_global : 0x06400d98
Address@app_sync_timer : 0x40080998
Address@app_sync_timer_global : 0x40080d98
Address@mot_sync_timer : 0x49200d98
Address@mot_sync_timer_global : 0x49201198
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_15_base_phase
Sync signal generator 15 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x0640099c
Address@com_sync_timer_global : 0x06400d9c
Address@app_sync_timer : 0x4008099c
Address@app_sync_timer_global : 0x40080d9c
Address@mot_sync_timer : 0x49200d9c
Address@mot_sync_timer_global : 0x4920119c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_16_cfg
Sync signal generator 16 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009a0
Address@com_sync_timer_global : 0x06400da0
Address@app_sync_timer : 0x400809a0
Address@app_sync_timer_global : 0x40080da0
Address@mot_sync_timer : 0x49200da0
Address@mot_sync_timer_global : 0x492011a0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_16_base_phase
Sync signal generator 16 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009a4
Address@com_sync_timer_global : 0x06400da4
Address@app_sync_timer : 0x400809a4
Address@app_sync_timer_global : 0x40080da4
Address@mot_sync_timer : 0x49200da4
Address@mot_sync_timer_global : 0x492011a4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_17_cfg
Sync signal generator 17 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009a8
Address@com_sync_timer_global : 0x06400da8
Address@app_sync_timer : 0x400809a8
Address@app_sync_timer_global : 0x40080da8
Address@mot_sync_timer : 0x49200da8
Address@mot_sync_timer_global : 0x492011a8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_17_base_phase
Sync signal generator 17 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009ac
Address@com_sync_timer_global : 0x06400dac
Address@app_sync_timer : 0x400809ac
Address@app_sync_timer_global : 0x40080dac
Address@mot_sync_timer : 0x49200dac
Address@mot_sync_timer_global : 0x492011ac
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_18_cfg
Sync signal generator 18 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009b0
Address@com_sync_timer_global : 0x06400db0
Address@app_sync_timer : 0x400809b0
Address@app_sync_timer_global : 0x40080db0
Address@mot_sync_timer : 0x49200db0
Address@mot_sync_timer_global : 0x492011b0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_18_base_phase
Sync signal generator 18 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009b4
Address@com_sync_timer_global : 0x06400db4
Address@app_sync_timer : 0x400809b4
Address@app_sync_timer_global : 0x40080db4
Address@mot_sync_timer : 0x49200db4
Address@mot_sync_timer_global : 0x492011b4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_19_cfg
Sync signal generator 19 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009b8
Address@com_sync_timer_global : 0x06400db8
Address@app_sync_timer : 0x400809b8
Address@app_sync_timer_global : 0x40080db8
Address@mot_sync_timer : 0x49200db8
Address@mot_sync_timer_global : 0x492011b8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_19_base_phase
Sync signal generator 19 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009bc
Address@com_sync_timer_global : 0x06400dbc
Address@app_sync_timer : 0x400809bc
Address@app_sync_timer_global : 0x40080dbc
Address@mot_sync_timer : 0x49200dbc
Address@mot_sync_timer_global : 0x492011bc
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_20_cfg
Sync signal generator 20 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009c0
Address@com_sync_timer_global : 0x06400dc0
Address@app_sync_timer : 0x400809c0
Address@app_sync_timer_global : 0x40080dc0
Address@mot_sync_timer : 0x49200dc0
Address@mot_sync_timer_global : 0x492011c0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_20_base_phase
Sync signal generator 20 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009c4
Address@com_sync_timer_global : 0x06400dc4
Address@app_sync_timer : 0x400809c4
Address@app_sync_timer_global : 0x40080dc4
Address@mot_sync_timer : 0x49200dc4
Address@mot_sync_timer_global : 0x492011c4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_21_cfg
Sync signal generator 21 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009c8
Address@com_sync_timer_global : 0x06400dc8
Address@app_sync_timer : 0x400809c8
Address@app_sync_timer_global : 0x40080dc8
Address@mot_sync_timer : 0x49200dc8
Address@mot_sync_timer_global : 0x492011c8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_21_base_phase
Sync signal generator 21 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009cc
Address@com_sync_timer_global : 0x06400dcc
Address@app_sync_timer : 0x400809cc
Address@app_sync_timer_global : 0x40080dcc
Address@mot_sync_timer : 0x49200dcc
Address@mot_sync_timer_global : 0x492011cc
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_22_cfg
Sync signal generator 22 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009d0
Address@com_sync_timer_global : 0x06400dd0
Address@app_sync_timer : 0x400809d0
Address@app_sync_timer_global : 0x40080dd0
Address@mot_sync_timer : 0x49200dd0
Address@mot_sync_timer_global : 0x492011d0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_22_base_phase
Sync signal generator 22 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009d4
Address@com_sync_timer_global : 0x06400dd4
Address@app_sync_timer : 0x400809d4
Address@app_sync_timer_global : 0x40080dd4
Address@mot_sync_timer : 0x49200dd4
Address@mot_sync_timer_global : 0x492011d4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_23_cfg
Sync signal generator 23 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009d8
Address@com_sync_timer_global : 0x06400dd8
Address@app_sync_timer : 0x400809d8
Address@app_sync_timer_global : 0x40080dd8
Address@mot_sync_timer : 0x49200dd8
Address@mot_sync_timer_global : 0x492011d8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_23_base_phase
Sync signal generator 23 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009dc
Address@com_sync_timer_global : 0x06400ddc
Address@app_sync_timer : 0x400809dc
Address@app_sync_timer_global : 0x40080ddc
Address@mot_sync_timer : 0x49200ddc
Address@mot_sync_timer_global : 0x492011dc
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_24_cfg
Sync signal generator 24 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009e0
Address@com_sync_timer_global : 0x06400de0
Address@app_sync_timer : 0x400809e0
Address@app_sync_timer_global : 0x40080de0
Address@mot_sync_timer : 0x49200de0
Address@mot_sync_timer_global : 0x492011e0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_24_base_phase
Sync signal generator 24 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009e4
Address@com_sync_timer_global : 0x06400de4
Address@app_sync_timer : 0x400809e4
Address@app_sync_timer_global : 0x40080de4
Address@mot_sync_timer : 0x49200de4
Address@mot_sync_timer_global : 0x492011e4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_25_cfg
Sync signal generator 25 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009e8
Address@com_sync_timer_global : 0x06400de8
Address@app_sync_timer : 0x400809e8
Address@app_sync_timer_global : 0x40080de8
Address@mot_sync_timer : 0x49200de8
Address@mot_sync_timer_global : 0x492011e8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_25_base_phase
Sync signal generator 25 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009ec
Address@com_sync_timer_global : 0x06400dec
Address@app_sync_timer : 0x400809ec
Address@app_sync_timer_global : 0x40080dec
Address@mot_sync_timer : 0x49200dec
Address@mot_sync_timer_global : 0x492011ec
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_26_cfg
Sync signal generator 26 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009f0
Address@com_sync_timer_global : 0x06400df0
Address@app_sync_timer : 0x400809f0
Address@app_sync_timer_global : 0x40080df0
Address@mot_sync_timer : 0x49200df0
Address@mot_sync_timer_global : 0x492011f0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_26_base_phase
Sync signal generator 26 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009f4
Address@com_sync_timer_global : 0x06400df4
Address@app_sync_timer : 0x400809f4
Address@app_sync_timer_global : 0x40080df4
Address@mot_sync_timer : 0x49200df4
Address@mot_sync_timer_global : 0x492011f4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_27_cfg
Sync signal generator 27 config register
R/W
0x00000000
Address@com_sync_timer : 0x064009f8
Address@com_sync_timer_global : 0x06400df8
Address@app_sync_timer : 0x400809f8
Address@app_sync_timer_global : 0x40080df8
Address@mot_sync_timer : 0x49200df8
Address@mot_sync_timer_global : 0x492011f8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_27_base_phase
Sync signal generator 27 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x064009fc
Address@com_sync_timer_global : 0x06400dfc
Address@app_sync_timer : 0x400809fc
Address@app_sync_timer_global : 0x40080dfc
Address@mot_sync_timer : 0x49200dfc
Address@mot_sync_timer_global : 0x492011fc
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_28_cfg
Sync signal generator 28 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400a00
Address@com_sync_timer_global : 0x06400e00
Address@app_sync_timer : 0x40080a00
Address@app_sync_timer_global : 0x40080e00
Address@mot_sync_timer : 0x49200e00
Address@mot_sync_timer_global : 0x49201200
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_28_base_phase
Sync signal generator 28 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400a04
Address@com_sync_timer_global : 0x06400e04
Address@app_sync_timer : 0x40080a04
Address@app_sync_timer_global : 0x40080e04
Address@mot_sync_timer : 0x49200e04
Address@mot_sync_timer_global : 0x49201204
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_gen_29_cfg
Sync signal generator 29 config register
R/W
0x00000000
Address@com_sync_timer : 0x06400a08
Address@com_sync_timer_global : 0x06400e08
Address@app_sync_timer : 0x40080a08
Address@app_sync_timer_global : 0x40080e08
Address@mot_sync_timer : 0x49200e08
Address@mot_sync_timer_global : 0x49201208
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 5 0x0
sub_phase

4 - 0 "00000"
sub_phase_sel
0: no sync pulse generated by sync generator.
sync pulse generated when TIMEBASE advances AND
1: only SYNC_GEN?_BASE_PHASE matches BASE_PHASE
2: SYNC_GEN?_BASE_PHASE matches BASE_PHASE AND sub_phase matches SUB_PHASE0
3: " " SUB_PHASE1
...
9: " " SUB_PHASE7
...
17:" " SUB_PHASE15


sync_sync_gen_29_base_phase
Sync signal generator 29 base_phase register
R/W
0x00000000
Address@com_sync_timer : 0x06400a0c
Address@com_sync_timer_global : 0x06400e0c
Address@app_sync_timer : 0x40080a0c
Address@app_sync_timer_global : 0x40080e0c
Address@mot_sync_timer : 0x49200e0c
Address@mot_sync_timer_global : 0x4920120c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
see SYNC_GEN_0_CFG


sync_sync_out_0_cfg
Sync out generator config register
When sync[0] occurs, a pulse is generated on sync_out[0]
R/W
0x00000000
Address@com_sync_timer : 0x06400a10
Address@com_sync_timer_global : 0x06400e10
Address@app_sync_timer : 0x40080a10
Address@app_sync_timer_global : 0x40080e10
Address@mot_sync_timer : 0x49200e10
Address@mot_sync_timer_global : 0x49201210
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_1_cfg
Sync out generator config register
When sync[1] occurs, a pulse is generated on sync_out[1]
R/W
0x00000000
Address@com_sync_timer : 0x06400a14
Address@com_sync_timer_global : 0x06400e14
Address@app_sync_timer : 0x40080a14
Address@app_sync_timer_global : 0x40080e14
Address@mot_sync_timer : 0x49200e14
Address@mot_sync_timer_global : 0x49201214
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_2_cfg
Sync out generator config register
When sync[2] occurs, a pulse is generated on sync_out[2]
R/W
0x00000000
Address@com_sync_timer : 0x06400a18
Address@com_sync_timer_global : 0x06400e18
Address@app_sync_timer : 0x40080a18
Address@app_sync_timer_global : 0x40080e18
Address@mot_sync_timer : 0x49200e18
Address@mot_sync_timer_global : 0x49201218
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_3_cfg
Sync out generator config register
When sync[3] occurs, a pulse is generated on sync_out[3]
R/W
0x00000000
Address@com_sync_timer : 0x06400a1c
Address@com_sync_timer_global : 0x06400e1c
Address@app_sync_timer : 0x40080a1c
Address@app_sync_timer_global : 0x40080e1c
Address@mot_sync_timer : 0x49200e1c
Address@mot_sync_timer_global : 0x4920121c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_4_cfg
Sync out generator config register
When sync[4] occurs, a pulse is generated on sync_out[4]
R/W
0x00000000
Address@com_sync_timer : 0x06400a20
Address@com_sync_timer_global : 0x06400e20
Address@app_sync_timer : 0x40080a20
Address@app_sync_timer_global : 0x40080e20
Address@mot_sync_timer : 0x49200e20
Address@mot_sync_timer_global : 0x49201220
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_5_cfg
Sync out generator config register
When sync[5] occurs, a pulse is generated on sync_out[5]
R/W
0x00000000
Address@com_sync_timer : 0x06400a24
Address@com_sync_timer_global : 0x06400e24
Address@app_sync_timer : 0x40080a24
Address@app_sync_timer_global : 0x40080e24
Address@mot_sync_timer : 0x49200e24
Address@mot_sync_timer_global : 0x49201224
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_6_cfg
Sync out generator config register
When sync[6] occurs, a pulse is generated on sync_out[6]
R/W
0x00000000
Address@com_sync_timer : 0x06400a28
Address@com_sync_timer_global : 0x06400e28
Address@app_sync_timer : 0x40080a28
Address@app_sync_timer_global : 0x40080e28
Address@mot_sync_timer : 0x49200e28
Address@mot_sync_timer_global : 0x49201228
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles


sync_sync_out_7_cfg
Sync out generator config register
When sync[7] occurs, a pulse is generated on sync_out[7]
R/W
0x00000000
Address@com_sync_timer : 0x06400a2c
Address@com_sync_timer_global : 0x06400e2c
Address@app_sync_timer : 0x40080a2c
Address@app_sync_timer_global : 0x40080e2c
Address@mot_sync_timer : 0x49200e2c
Address@mot_sync_timer_global : 0x4920122c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 2 0x0
duration
pulse duration in clk cycles (only for polarity=0 and 1
1 - 0 "00"
polarity
sync_out behaviour
0: sync_out pulse is high active (idle level = 0)
1: sync_out pulse is low active (idle level = 1)
2: sync_out toggles



Base Address Area: com_can_fd, app_can_fd

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R can_fd_receive_buffer_random_access_region_start
1-3e 4-f8 -  reserved
3f fc R can_fd_receive_buffer_random_access_region_end
40 100 R can_fd_receive_buffer_fifo_region_start
41-7e 104-1f8 -  reserved
7f 1fc R can_fd_receive_buffer_fifo_region_end
80-ff 200-3fc -  reserved
100 400 W can_fd_receive_buffer_srb_cmd
101 404 R/W can_fd_receive_buffer_srb_ien
102 408 R can_fd_receive_buffer_srb_istat
103 40c R/W can_fd_receive_buffer_srb_irq
104 410 R can_fd_receive_buffer_srb_stat
105 414 R can_fd_receive_buffer_srb_rx_npackets
106 418 R/W can_fd_receive_buffer_srb_ctrl
107-1ff 41c-7fc -  reserved
200 800 R can_fd_can_time_stamp_time_ts_l
201 804 R can_fd_can_time_stamp_time_ts_h
202 808 R/W can_fd_can_time_stamp_time_mode
203 80c R/W can_fd_can_time_stamp_time_interval
204 810 W can_fd_can_time_stamp_time_cmd
205 814 R can_fd_can_time_stamp_time_capt_l
206 818 R can_fd_can_time_stamp_time_capt_h
207-2ff 81c-bfc -  reserved
300 c00 R can_fd_build_data_rev_info
301-37f c04-dfc -  reserved
380 e00 R can_fd_global_signals_global_interrupt
381-5ff e04-17fc -  reserved
600 1800 W can_fd_can_channel_0_random_access_region_start
601-63e 1804-18f8 -  reserved
63f 18fc W can_fd_can_channel_0_random_access_region_end
640 1900 W can_fd_can_channel_0_fifo_region_start
641-67e 1904-19f8 -  reserved
67f 19fc W can_fd_can_channel_0_fifo_region_end
680 1a00 W can_fd_can_channel_0_control_region_start
681-6fe 1a04-1bf8 -  reserved
6ff 1bfc W can_fd_can_channel_0_control_region_end
700 1c00 W can_fd_can_channel_0_kcan_cmd
701 1c04 -  reserved
702 1c08 R/W can_fd_can_channel_0_kcan_ien
703 1c0c R can_fd_can_channel_0_kcan_istat
704 1c10 R/W can_fd_can_channel_0_kcan_irq
705 1c14 R can_fd_can_channel_0_kcan_tx_npackets
706 1c18 R can_fd_can_channel_0_kcan_stat
707 1c1c R/W can_fd_can_channel_0_kcan_mode
708 1c20 R/W can_fd_can_channel_0_kcan_btrn
709 1c24 R/W can_fd_can_channel_0_kcan_blp
70a 1c28 R/W can_fd_can_channel_0_kcan_btrd
70b 1c2c R/W can_fd_can_channel_0_kcan_tx_rate_limit
70c 1c30 -  reserved
70d 1c34 R/W can_fd_can_channel_0_kcan_ssp_ctrl
70e-7ff 1c38-1ffc -  reserved
800 2000 R/W can_fd_can_channel_1_base_addr
801-3fff 2004-fffc -  reserved

can_fd_receive_buffer_random_access_region_start
Random Access Region start
The Random Access Region is used for reading received data in Random Access Mode. The format of the
data is defined by the RDATA packet.
R
Address@com_can_fd : 0x06420000
Address@app_can_fd : 0x400d0000
Bits Name Description
31 - 0 val
First dword of Random Access Region


can_fd_receive_buffer_random_access_region_end
Random Access Region end
R
Address@com_can_fd : 0x064200fc
Address@app_can_fd : 0x400d00fc
Bits Name Description
31 - 0 val
Last dword of Random Access Region


can_fd_receive_buffer_fifo_region_start
FIFO Region start
The FIFO Region is used for reading received data in FIFO Mode. The format of the data is defined by
the RDATA packet.
R
Address@com_can_fd : 0x06420100
Address@app_can_fd : 0x400d0100
Bits Name Description
31 - 0 val
First dword of FIFO Region


can_fd_receive_buffer_fifo_region_end
FIFO Region end
R
Address@com_can_fd : 0x064201fc
Address@app_can_fd : 0x400d01fc
Bits Name Description
31 - 0 val
Last dword of FIFO Region


can_fd_receive_buffer_srb_cmd
SRB_CMD: Command input register
W
0x00000000
Address@com_can_fd : 0x06420400
Address@app_can_fd : 0x400d0400
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
RDB
Release DMA Buffer. The appropriate bit must be written when the corresponding DMA
buffer has been handled to allow the DMA engine to reuse the buffer memory area.
For example, if DMA buffer 0 has just been serviced, bit 0 of RDB must be written.
3 - 1 0
-
 reserved
0 "0"
FOR
FIFO Offset Reset. Writing this bit will reset the internal FIFO offset pointer to
point at the first header word. This can be used to restart readout.


can_fd_receive_buffer_srb_ien
SRB_IEN: Interrupt Enable. Setting the bits in this register will allow the corresponding
interrupt sources to generate an interrupt. If the sources are not allowed to generate an interrupt,
they may still be read through the register SRB_ISTAT.
R/W
0x00000000
Address@com_can_fd : 0x06420404
Address@app_can_fd : 0x400d0404
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 - 12 "00"
DUF
Write to generate interrupt on DMA Underflow. One bit per DMA buffer. See SRB_IRQ
for details on this interrupt.
11 - 10 "00"
DOF
Write to generate interrupt on DMA Overflow. One bit per DMA buffer. See SRB_IRQ
for details on this interrupt.
9 - 8 "00"
DPD
Write to generate interrupt on DMA Packet Done. See SRB_IRQ for details on this
interrupt.
7 - 5 0
-
 reserved
4 "0"
RPA
Write to generate interrupt on RX Packet Available. See SRB_IRQ for details on this
interrupt.
3 "0"
RUF
Write to generate interrupt on RX Underflow. See SRB_IRQ for details on this
interrupt.
2 "0"
RMT
Write to generate interrupt on RX Missing Tag. See SRB_IRQ for details on this
interrupt.
1 "0"
RAL
Write to generate interrupt on RX Unaligned Read. See SRB_IRQ for details on this
interrupt.
0 "0"
IA
Write to generate interrupt on Illegal Access. See SRB_IRQ for details on this
interrupt.


can_fd_receive_buffer_srb_istat
SRB_ISTAT: Interrupt status. Contains the current status of all interrupt sources. These may
always be read, even if the sources are not configured to generate interrupts.
R
Address@com_can_fd : 0x06420408
Address@app_can_fd : 0x400d0408
Bits Name Description
31 - 14 -
 reserved
13 - 12 DUF
DMA Underflow detected. One bit per DMA buffer. See SRB_IRQ for details on this
interrupt.
11 - 10 DOF
DMA Overflow detected. One bit per DMA buffer. See SRB_IRQ for details on this
interrupt.
9 - 8 DPD
DMA Packet Done detected. See SRB_IRQ for details on this interrupt.
7 - 5 -
 reserved
4 RPA
RX Packet Available detected. See SRB_IRQ for details on this interrupt.
3 RUF
RX Underflow detected. See SRB_IRQ for details on this interrupt.
2 RMT
RX Missing Tag detected. See SRB_IRQ for details on this interrupt.
1 RAL
RX Unaligned Read detected. See SRB_IRQ for details on this interrupt.
0 IA
Illegal Access detected. See SRB_IRQ for details on this interrupt.


can_fd_receive_buffer_srb_irq
SRB_IRQ: Interrupt Request / Interrupt Clear. When read, this register signals which interrupt
source(s) that are currently creating an interrupt.

When written, each bit that is set high will clear its corresponding interrupt request. This must
be done when servicing the interrupt, as the bits of SRB_IRQ are otherwise sticky. Of course, the
original source of the interrupt must be removed to avoid the interrupt to re-trigger.
R/W
0x00000000
Address@com_can_fd : 0x0642040c
Address@app_can_fd : 0x400d040c
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 - 12 "00"
DUF
DMA Underflow detected. One bit per DMA buffer. See SRB_IRQ for details on this
interrupt.
11 - 10 "00"
DOF
DMA Overflow detected. One bit per DMA buffer. See SRB_IRQ for details on this
interrupt.
9 - 8 "00"
DPD
DMA Packet Done detected. See SRB_IRQ for details on this interrupt.
7 - 5 0
-
 reserved
4 "0"
RPA
RX Packet Available detected. See SRB_IRQ for details on this interrupt.
3 "0"
RUF
RX Underflow detected. See SRB_IRQ for details on this interrupt.
2 "0"
RMT
RX Missing Tag detected. See SRB_IRQ for details on this interrupt.
1 "0"
RAL
RX Unaligned Read detected. See SRB_IRQ for details on this interrupt.
0 "0"
IA
Illegal Access detected. See SRB_IRQ for details on this interrupt.


can_fd_receive_buffer_srb_stat
SRB_STAT: Status register. Some bits of this register return valid data only after the first
access to the receive buffer FIFO, see notes.
R
Address@com_can_fd : 0x06420410
Address@app_can_fd : 0x400d0410
Bits Name Description
31 - 25 -
 reserved
24 DMA
One if DMA is implemented, 0 if it is not.
23 - 21 -
 reserved
20 - 16 FOFS
FIFO Offset.
15 DI
DMA Idle.
14 EOP
Current word is end of packet word. This is true if FOFS is equal to LPOS.

NOTE: Only valid after first access to receive buffer FIFO was made, returns
uninitialized data otherwise!
13 DA
Data Available.
12 - 8 LPOS
Last Position written in FIFO.

NOTE: Only valid after first access to receive buffer FIFO was made, returns
uninitialized data otherwise!
7 - 3 -
 reserved
2 - 0 CHID
Channel ID of the unit that produced the current packet.


can_fd_receive_buffer_srb_rx_npackets
SRB_RX_NPACKETS: Number of words in receive buffer.
R
Address@com_can_fd : 0x06420414
Address@app_can_fd : 0x400d0414
Bits Name Description
31 - 24 -
 reserved
23 - 16 MAX_COUNT
The maximum number of packets that the receiver buffer can hold.
15 - 8 -
 reserved
7 - 0 COUNT
Number of packets currently in the receiver buffer.


can_fd_receive_buffer_srb_ctrl
SRB_CTRL: Control. This register contains the bit that enables or disables the DMA engine.
R/W
0x00000000
Address@com_can_fd : 0x06420418
Address@app_can_fd : 0x400d0418
Bits Reset value Name Description
31 - 8 0x0
DMA_BASE_ADDR
The top 24 bits of the base address used by the DMA engine.
7 - 1 0
-
 reserved
0 "0"
DEN
DMA enable. Set this bit to 1 to enable DMA and 0 to disable.


can_fd_can_time_stamp_time_ts_l
TIME_TS_L: Time stamp. Least significant 32 bits.
R
Address@com_can_fd : 0x06420800
Address@app_can_fd : 0x400d0800
Bits Name Description
31 - 0 TS_L
Holds the last captured least significant part of the time stamp. When reading
this register, the time stamp is also captured. The most sig-ificant bits can
then be read from the TIME_TS_H register.


can_fd_can_time_stamp_time_ts_h
TIME_TS_H: Time stamp. Most significant 32 bits.
R
Address@com_can_fd : 0x06420804
Address@app_can_fd : 0x400d0804
Bits Name Description
31 - 0 TS_H
Holds the last captured most significant part of the time stamp.


can_fd_can_time_stamp_time_mode
Time Mode: Mode Control.
R/W
0x00000000
Address@com_can_fd : 0x06420808
Address@app_can_fd : 0x400d0808
Bits Reset value Name Description
31 - 23 0
-
 reserved
22 - 16 "0000000"
PRESCALER
Prescaler for the time stamp counter. The system clock is divided with the
prescaler + 1 before being used to increment the time stamp counter.
15 - 3 0
-
 reserved
2 "0"
CAPTSRC
Capture source:
0: External event
1: Interval event
1 "0"
CAPTEN
Capture Enable. Set this bit to 1 to enable capture of external or internal
events.
0 "0"
INTEN
Interval Event Enable. Set this bit to 1 to enable interval-generated events.


can_fd_can_time_stamp_time_interval
Time Interval: Interval length compare value. Set to interval length - 1.
R/W
0x00000000
Address@com_can_fd : 0x0642080c
Address@app_can_fd : 0x400d080c
Bits Reset value Name Description
31 - 0 0x0
INTERVAL
Sets the interval length compare value. Should be set to the interval
length - 1, with the length given in system clock cycles.


can_fd_can_time_stamp_time_cmd
Time CMD: Command. Contains bits to restart the time stamp counter and to force capture of
the current value.
W
0x00000000
Address@com_can_fd : 0x06420810
Address@app_can_fd : 0x400d0810
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
RESTART
Forces the time stamp counter to restart from 0.
0 "0"
CAPT
Forces a capture of the current time stamp to CAPT_L/CAPT_H when set to 1.


can_fd_can_time_stamp_time_capt_l
TIME_CAPT_L: Captured Time. Least significant 32 bits.
R
Address@com_can_fd : 0x06420814
Address@app_can_fd : 0x400d0814
Bits Name Description
31 - 0 CAPT_L
Holds the last captured least significant part of the time stamp.


can_fd_can_time_stamp_time_capt_h
TIME_CAPT_H: Time stamp. Most significant 32 bits.
R
Address@com_can_fd : 0x06420818
Address@app_can_fd : 0x400d0818
Bits Name Description
31 - 0 CAPT_H
Holds the last captured most significant part of the time stamp. As a side
effect the ready signal is cleared when this register is read.


can_fd_build_data_rev_info
Rev Info: Contains revision number and modification status of the build.
R
Address@com_can_fd : 0x06420c00
Address@app_can_fd : 0x400d0c00
Bits Name Description
31 MOD
If set to 0, this bit signals that the IP was built from clean sources.
30 - 0 REV
Contains the revision number for source file traceability.


can_fd_global_signals_global_interrupt
Global Interrupt: This register collects the most important interrupts from the four first
channels and the receive subsystem
R
Address@com_can_fd : 0x06420e00
Address@app_can_fd : 0x400d0e00
Bits Name Description
31 OTH_N3
If set, this bit signals that there are other interrupts from channel N's KCAN_IRQ
30 - 29 -
 reserved
28 TE_N3
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
27 TFD_N3
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
26 ABD_N3
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
25 TNE_N3
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
24 OTH_N2
If set, this bit signals that there are other interrupts from channel N's KCAN_IRQ
23 - 22 -
 reserved
21 TE_N2
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
20 TFD_N2
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
19 ABD_N2
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
18 TNE_N2
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
17 OTH_N1
If set, this bit signals that there are other interrupts from channel N's KCAN_IRQ
16 - 15 -
 reserved
14 TE_N1
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
13 TFD_N1
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
12 ABD_N1
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
11 TNE_N1
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
10 OTH_N0
If set, this bit signals that there are other interrupts from channel N's KCAN_IRQ
9 - 8 -
 reserved
7 TE_N0
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
6 TFD_N0
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
5 ABD_N0
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
4 TNE_N0
Same interrupt bit as TE for channel N from the KCAN_IRQ register. See KCAN_IRQ
for details.
3 SRB_O
Indicates there are other interrupts from the SRB_IRQ register. See SRB_IRQ
for details.
2 - 1 -
 reserved
0 RPA
Same interrupt bit as RPA from the SRB_IRQ register. See SRB_IRQ for details.


can_fd_can_channel_0_random_access_region_start
Random Acess Region start: The Random Access Region is used for writing data to be transmitted,
in Random Access Mode. The procedure for transmitting data is detailed in chapter 4.
The format of the data is defined by the TDATA packet.
W
0x00000000
Address@com_can_fd : 0x06421800
Address@app_can_fd : 0x400d1800
Bits Reset value Name Description
31 - 0 0x0
val
First dword of Random Access Region


can_fd_can_channel_0_random_access_region_end
Random Access Region end
W
0x00000000
Address@com_can_fd : 0x064218fc
Address@app_can_fd : 0x400d18fc
Bits Reset value Name Description
31 - 0 0x0
val
Last dword of Random Access Region


can_fd_can_channel_0_fifo_region_start
FIFO Region start: The FIFO Region is used for writing data to be transmitted, in FIFO Mode. The
procedure for transmitting data is detailed in chapter 4. The format of the data is defined by
the TDATA packet.
W
0x00000000
Address@com_can_fd : 0x06421900
Address@app_can_fd : 0x400d1900
Bits Reset value Name Description
31 - 0 0x0
val
First dword of FIFO Region


can_fd_can_channel_0_fifo_region_end
FIFO Region end
W
0x00000000
Address@com_can_fd : 0x064219fc
Address@app_can_fd : 0x400d19fc
Bits Reset value Name Description
31 - 0 0x0
val
Last dword of FIFO Region


can_fd_can_channel_0_control_region_start
Control Region start: The Control Region is used for writing control packets to the CAN channel.
There is one type of control packet available: the EFLUSH packet. After a flush operation has
been issued to the CAN channel, all packets in the transmit buffer will be discarded until an
EFLUSH packet is written.
W
0x00000000
Address@com_can_fd : 0x06421a00
Address@app_can_fd : 0x400d1a00
Bits Reset value Name Description
31 - 0 0x0
val
First dword of Control Region


can_fd_can_channel_0_control_region_end
Control Region end
W
0x00000000
Address@com_can_fd : 0x06421bfc
Address@app_can_fd : 0x400d1bfc
Bits Reset value Name Description
31 - 0 0x0
val
Last dword of Control Region


can_fd_can_channel_0_kcan_cmd
KCAN_CMD: Command input register. All commands except for WTEC and WREC will wait until the
current receive or write operation is finished before execution. The result of multiple
requests being issued before previous requests are finished will be unpredictable. The RRQ
functionality is optional.
W
0x00000000
Address@com_can_fd : 0x06421c00
Address@app_can_fd : 0x400d1c00
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 - 16 0x0
EC
Error counter value set when used together with WTEC and WREC
15 - 6 0
-
 reserved
5 "0"
RRQ
Optional function - Restart request. Write this bit to restart the unit after
a bus off, triggered by the transmit error count reaching a value larger than
255. The restart request is only needed when the MRRQ bit in the register
KCAN_MODE is enabled. A restart request will make the unit start integrating to
the CAN communication and will go bus on when 128 occurrences of the idle
condition (11 recessive bit periods) is received.
4 "0"
WTEC
Set value of transmitter error counter to the value of EC.
3 "0"
WREC
Set value of receiver error counter to the value of EC.
2 "0"
FTX
Flushes the transmit FIFO. The FTX command is delayed until the transmitter is
idle. The current status can be read from the KCAN_STAT register.
1 "0"
AT
Abort, Flush and reset the CAN Channel. The AT command is delayed until the
transmitter is idle. Current reset mode and abort status can be read from the
KCAN_STAT register. The completion of the AT command will be acknowledged by a
status packet with the IDET bit set, if non-data packets are enabled.
0 "0"
SRQ
Request error status packet. A status packet will be written into the receiver
FIFO. The status packet will be tagged with the value of the last SEQNO written.
A status packet will not be generated until the current receive or transmit
operation is finished, so care must be taken that multiple status requests are
not done before the previous one is finished.


can_fd_can_channel_0_kcan_ien
KCAN_IEN: Interrupt Enable. Enables and disables the different interrupt sources. The interrupt
conditions may always be read from KCAN_ISTAT, even if the condition is not allowed to generate
an interrupt flag.
R/W
0x00000000
Address@com_can_fd : 0x06421c08
Address@app_can_fd : 0x400d1c08
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
TNE
Set to 1 to enable interrupt on the Transmit FIFO Near Empty condition. See
KCAN_IRQ for details.
17 "0"
TAL
Set to 1 to enable interrupt on the Transmitter Unaligned condition. See
KCAN_IRQ for details.
16 "0"
TE
Set to 1 to enable interrupt on the Transmit FIFO Empty condition. See KCAN_IRQ
for details.
15 "0"
TOF
Set to 1 to enable interrupt on the Transmit FIFO Full condition. See KCAN_IRQ
for details.
14 "0"
TFD
Set to 1 to enable interrupt on the Transmit Buffer Flush Done condition. See
KCAN_IRQ for details.
13 "0"
ABD
Set to 1 to enable interrupt on the Abort Done condition. See KCAN_IRQ for details.
12 - 6 0
-
 reserved
5 "0"
ROF
Set to 1 to enable interrupt on the RX FIFO Overflow condition. See KCAN_IRQ
for details.
4 "0"
IDLE
Set to 1 to enable interrupt on the TIdle State condition. See KCAN_IRQ for details.
3 "0"
FDIC
Set to 1 to enable interrupt on the FDF in Classic Mode condition. See KCAN_IRQ
for details.
2 "0"
BPP
Set to 1 to enable interrupt on the Bus Paramter Protection Error condition.
See KCAN_IRQ for details.
1 "0"
TAE
Set to 1 to enable interrupt on the TX FIFO Unaligned End condition. See
KCAN_IRQ for details.
0 "0"
TAR
Set to 1 to enable interrupt on the TX FIFO Unaligned Read condition. See
KCAN_IRQ for details.


can_fd_can_channel_0_kcan_istat
KCAN_ISTAT: Interrupt Status. Contains the current status of the CAN channel's interrupt sources.
These values are unaffected by the KCAN_IEN register, and can thus be read even if they are not
allowed to trigger an interrupt.
R
Address@com_can_fd : 0x06421c0c
Address@app_can_fd : 0x400d1c0c
Bits Name Description
31 - 19 -
 reserved
18 TNE
?Interrupt status Transmit FIFO Near Empty?
17 TAL
?Interrupt status Transmitter Unaligned?
16 TE
?Interrupt status Transmit FIFO Empty?
15 TOF
?Interrupt status Transmit FIFO Full?
14 TFD
?Interrupt status Transmit Buffer Flush Done?
13 ABD
?Interrupt status Abort Done?
12 - 6 -
 reserved
5 ROF
?Interrupt status RX FIFO Overflow?
4 IDLE
?Interrupt status Idle State?
3 FDIC
?Interrupt status FDF in Classic Mode?
2 BPP
?Interrupt status Bus Paramter Protection Error?
1 TAE
?Interrupt status TX FIFO Unaligned End?
0 TAR
?Interrupt status TX FIFO Unaligned Read?


can_fd_can_channel_0_kcan_irq
KCAN_IRQ: Interrupt Request / Interrupt Clear. When read, this register signals which interrupt
source(s) that are currently creating an interrupt.

When written, each bit that is set high will clear its corresponding interrupt request.
This must be done when servicing the interrupt, as the bits of KCAN_IRQ areotherwise sticky.
Of course, the original source of the interrupt must be removed toavoid the interrupt to re-trigger.
R/W
0x00000000
Address@com_can_fd : 0x06421c10
Address@app_can_fd : 0x400d1c10
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
TNE
Transmit FIFO Near empty. Goes high when the transmit FIFO is near empty,
i.e. when it holds one message or less.
17 "0"
TAL
Transmitter Unaligned. Illegal address was written in FIFO mode.
16 "0"
TE
Transmit FIFO empty. Goes high when the transmit FIFO is empty.
15 "0"
TOF
Transmit FIFO overflow. The transmit FIFO was written when already full.
14 "0"
TFD
Transmit Buffer Flush Done. TFD will pulse when the FTX command has been
handled. (This does NOT indicate that the end of flush ack packet has been generated.
13 "0"
ABD
Abort Done. Signals that an abort operation finished.
12 - 6 0
-
 reserved
5 "0"
ROF
RX FIFO Overflow. Packets have been lost.
4 "0"
IDLE
Idle State. Unit is in reset mode and no abort or flush is pending.
3 "0"
FDIC
FDF in Classic Mode. A CAN FD frame was sent with the unit set in classic mode.
2 "0"
BPP
Bus Parameter Protection Error. A write operation to the bus parameters failed
because the unit was not in reset mode.
1 "0"
TAE
TX FIFO Unaligned End. Transmitter signaled that message was done at an
unexpected time.
0 "0"
TAR
TX FIFO Unaligned Read. Transmitter requested data when it should not.


can_fd_can_channel_0_kcan_tx_npackets
KCAN_TX_NPACKETS: Number of packets in transmit buffer.
R
Address@com_can_fd : 0x06421c14
Address@app_can_fd : 0x400d1c14
Bits Name Description
31 - 24 -
 reserved
23 - 16 MAX_COUNT
Maximum number of packets in the transmit buffer. Two buffer positions are
always allocated. One position for the next data packet and one for the
next control packet:
free = BufferSize -max(N_datapackets, 1) - max(N_controlpackets, 1)
15 - 8 -
 reserved
7 - 0 COUNT
Number of packets in transmit buffer.


can_fd_can_channel_0_kcan_stat
KCAN_STAT: Status Register.
R
Address@com_can_fd : 0x06421c18
Address@app_can_fd : 0x400d1c18
Bits Name Description
31 - 24 CMD_SEQ_NO
Command Sequence Number for Flush, Abort or Status request.
23 - 20 -
 reserved
19 FD
CAN FD is implemented. This is a hardware capability bit.
18 - 16 -
 reserved
15 IRM
In Reset Mode. Set when the unit is in reset mode.
14 RMR
Reset Mode Requested. Set when reset mode is requested. This bit is
always the same as the RM bit in the KCAN_MODE register.
13 TXI
TX Idle. Set when no transmit operation is ongoing.
12 TXE
TX Enabled. Set when the transmitter is enabled.
11 BOFF
Bus Off. Set when unit has entered bus-off recovery mode.
10 IDLE
Idle State. Set when the unit is idle or in reset mode.
9 IRQ
Interrupt Request. Set when an interrupt is being signalled.
8 TXFR
Transmitter Flush Request. Set when a transmitter flush request is
pending, following a write to KCAN_CMD.
7 AR
Abort Request. Set when an abort request is pending, following a write
to KCAN_CMD.
6 SRP
Status Request Pending. Set when a status request is pending, following
a write to KCAN_CMD.
5 - 0 -
 reserved


can_fd_can_channel_0_kcan_mode
KCAN_MODE: The mode register is used for configuration and mode settings.
R/W
0x00008560
Address@com_can_fd : 0x06421c1c
Address@app_can_fd : 0x400d1c1c
Bits Reset value Name Description
31 "0"
CCM
Classic CAN Mode. If set high, the unit will behave as a classic CAN unit
when receiving packets and no CAN FD packets will be received.
30 - 22 0
-
 reserved
21 "0"
AAM
Auto ACK mode. If set high, the transmitting unit will send a dominant
bit at the ACK bit position. This mode can be used in a loopback mode to
avoid error frames when no other unit is responding.
20 "0"
APT
Acknowledgement packet type. If set high, data packets with type ACK_DATA
will be used instead of the normal ACK packets
19 0
-
 reserved
18 - 16 "000"
CHID
Channel ID used to tag packets written to receiver buffer.
15 "1"
NIFDEN
Non-ISO FD enable. Enable this bit to use the non-ISO CAN FD mode.
In this mode:
- The stuff bit counter will not be included in the frame format.
- CRC initial value for CRC17 and CRC21 will be zero.
14 - 13 0
-
 reserved
12 "0"
EPEN
Enable Error Packets. If set to 1, the CAN channel will generate error packets.
11 "0"
MRRQ
Manual restart request. When this bit is set the unit will not automatically
try to get bus on again after a bus off triggered by the transmit error counter
exceeds the value 255. The unit must then be restarted with an RRQ command
(KCAN_MODE)
10 "1"
DWH
Dual word header control bit. Only use when TIMESTAMP_SIZE is set to 64 bits.
The DWH control the number of header words expected when using FIFO mode to
access the transmit buffer. A DWH value set to 0 needs four header words and
when set to 1 a two word header is expected. A DWH value of 0 will make it
possible to use the same packet format for the transmitter as for the receiver.
9 "0"
LOM
Listen Only Mode. Setting this bit puts the CAN channel in listen only mode,
where it will be silent on the bus but still receive data. Because the channel
is to stay silent, no acknowledges are issued.
8 "1"
RM
Reset Mode. Set to go bus off. The action will not take effect until the
current ongoing transmit or receive of a packet is finished. The actual
status can be read back from the KCAN_STAT register. Note: This is not an
actual reset, but a state when the unit is off the bus and the protected
registers are writeable.
7 - 0 "01100000"
EWL
Error Warning Limit. The number of errors detected before a warning is issued.


can_fd_can_channel_0_kcan_btrn
KCAN_BTRN: Nominal Bit Timing. These are the timing parameters that are used for headers and
for data transfers in standard CAN mode.
This register is protected, and may only be updated when in reset mode.
The bit rate is calculated as:
Bit Rate = f_sys / ((1 + t_seg1 + t_seg2) * n_brp)
R/W
0x00000000
Address@com_can_fd : 0x06421c20
Address@app_can_fd : 0x400d1c20
Bits Reset value Name Description
31 0
-
 reserved
30 - 26 "00000"
TSEG2
Time Segment 2 setting. Valid range is 0 to 31. TSEG2 = t_seg2 - 1
25 - 17 0x0
TSEG1
Time Segment 1 setting. Valid range is 0 to 511. TSEG1 = t_seg1 - 1
16 - 13 "0000"
SJQ
Sync Jump Width setting. Valid range is 0 to 15, but must not be greater than
TSEG1 or TSEG2. SJW = t_sjw - 1
12 - 0 0x0
BRP
Bit Rate Prescaler setting. Valid range is 0 to 8191. BRP = nbrp - 1


can_fd_can_channel_0_kcan_blp
KCAN_BLP: Bus Load Prescaler. The bus load prescaler value gives the division factors for the
bus load counter.
Bus load calculations are done by the HW and the results are periodically produced and put in
the receiver FIFO if non-data packets are enabled (see EN_NONDATA_PACKETS). The bus load reading
will be interleaved with ordinary data packets and are delivered in order. The sampling rate and
period of results can be set by the BLP parameters. The prescaler should be set to match the CAN
bit rate, the interval is set to control the update period.
R/W
0x00000000
Address@com_can_fd : 0x06421c24
Address@app_can_fd : 0x400d1c24
Bits Reset value Name Description
31 - 24 "00000000"
PRESCALER
Set the number of clock cycles between sampling of the bus state.
Recommended setting is (t_seg1 + t_seg2 + 1) *n_brp =number of clock cycles
f or one bit. The bus load calculation will be disabled if this field is
set to 0.
23 - 20 0
-
 reserved
19 - 0 0x0
INTERVAL
Number of samples between results are being produced.


can_fd_can_channel_0_kcan_btrd
KCAN_BTRD: Data Phase Bit Timing. These are the timing parameters that are used for the CAN
FD data phase.
This register is protected, and may only be updated when in reset mode.
The bit rate is calculated as:
Bit Rate = f_sys / ((1 + t_seg1 + t_seg2) * n_brp)
R/W
0x00000000
Address@com_can_fd : 0x06421c28
Address@app_can_fd : 0x400d1c28
Bits Reset value Name Description
31 0
-
 reserved
30 - 26 "00000"
TSEG2
Time Segment 2 setting. Valid range is 0 to 31. TSEG2 = t_seg2 - 1
25 - 17 0x0
TSEG1
Time Segment 1 setting. Valid range is 0 to 511. TSEG1 = t_seg1 - 1
16 - 13 "0000"
SJW
Sync Jump Width setting. Valid range is 0 to 15, but must not be greater than
TSEG1 or TSEG2. SJW = t_sjw - 1
12 - 0 0x0
BRP
Bit Rate Prescaler setting. Valid range is 0 to 8191, except when transmitter
delay compensation, TRDCE, is enabled and only the range 0 to 1 is allowed.
BRP = n_brp - 1


can_fd_can_channel_0_kcan_tx_rate_limit
KCAN_TX_RATE_LIMIT: Transmit Rate Limit. May be used to set a minimum delay between two
consecutive transmitted packets.
This register is protected, and may only be updated when in reset mode.
R/W
0x00000000
Address@com_can_fd : 0x06421c2c
Address@app_can_fd : 0x400d1c2c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 0 0x0
DELAY
The minimum number of smicroseconds of inactivity that is forced upon the
transmitter between two consecutive transmitted packets. Maximum value gives
a delay of just above 1 second. The delay is measured from the sample point
of the last bit of end of frame of the transmitted packet.


can_fd_can_channel_0_kcan_ssp_ctrl
KCAN_SSP_CTRL: Register to control the secondary sample point.
This register is protected, and may only be updated when in reset mode.
R/W
0x00030000
Address@com_can_fd : 0x06421c34
Address@app_can_fd : 0x400d1c34
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
MTRD
Manual TRD. If cleared, automatic TRD measurement is used. The SSP offset
should be written into the OFFSET field. If set, the automatic measurement of
TRD will be disabled and the sum of manual TRD value + SSP offset should be
written into OFFSET field to get the correct SSP position.
17 "1"
RXRSP
RX relative SSP. If set, the position of the SSP is calculated relative to
the sample point. This will give a good sample point value for all reasonable
CAN FD bus parameter settings. If cleared, the position of the SSP is
calculated as described in ISO.
16 "1"
TRDCE
If set, transmitter delay compensation is enabled.
15 - 11 0
-
 reserved
10 - 0 0x0
OFFSET
Secondary Sample Offset (CAN FD). Secondary sample point timing adjustment in
number of clock cycles. Should be set to zero.


can_fd_can_channel_1_base_addr
Channel 1 base address. Has the same registers as channel 0 but is offset by 512 bytes. For more
information refer to can_fd_can_channel_0 register description.
R/W
0x00000000
Address@com_can_fd : 0x06422000
Address@app_can_fd : 0x400d2000
Bits Reset value Name Description
31 - 0 0x0
val
First dword of channel 1



Base Address Area: mtgy, com_mtgy, app_mtgy

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mtgy_cmd
1 4 R mtgy_stat
2 8 R/W mtgy_irq_raw
3 c R mtgy_irq_masked
4 10 R/W mtgy_irq_msk_set
5 14 R/W mtgy_irq_msk_reset
6-3ff 18-ffc -  reserved
400 1000 R/W mtgy_op_tc0
401 1004 R/W mtgy_op_tc1
402 1008 R/W mtgy_op_tc2
403 100c R/W mtgy_op_tc3
404 1010 R/W mtgy_op_tc4
405 1014 R/W mtgy_op_tc5
406 1018 R/W mtgy_op_tc6
407 101c R/W mtgy_op_tc7
408 1020 R/W mtgy_op_tc8
409 1024 R/W mtgy_op_tc9
40a 1028 R/W mtgy_op_tc10
40b 102c R/W mtgy_op_tc11
40c 1030 R/W mtgy_op_tc12
40d 1034 R/W mtgy_op_tc13
40e 1038 R/W mtgy_op_tc14
40f 103c R/W mtgy_op_tc15
410 1040 R/W mtgy_op_tc16
411 1044 R/W mtgy_op_tc17
412 1048 R/W mtgy_op_tc18
413 104c R/W mtgy_op_tc19
414 1050 R/W mtgy_op_tc20
415 1054 R/W mtgy_op_tc21
416 1058 R/W mtgy_op_tc22
417 105c R/W mtgy_op_tc23
418 1060 R/W mtgy_op_tc24
419 1064 R/W mtgy_op_tc25
41a 1068 R/W mtgy_op_tc26
41b 106c R/W mtgy_op_tc27
41c 1070 R/W mtgy_op_tc28
41d 1074 R/W mtgy_op_tc29
41e 1078 R/W mtgy_op_tc30
41f 107c R/W mtgy_op_tc31
420 1080 R/W mtgy_op_tc32
421 1084 R/W mtgy_op_tc33
422 1088 R/W mtgy_op_tc34
423 108c R/W mtgy_op_tc35
424 1090 R/W mtgy_op_tc36
425 1094 R/W mtgy_op_tc37
426 1098 R/W mtgy_op_tc38
427 109c R/W mtgy_op_tc39
428 10a0 R/W mtgy_op_tc40
429 10a4 R/W mtgy_op_tc41
42a 10a8 R/W mtgy_op_tc42
42b 10ac R/W mtgy_op_tc43
42c 10b0 R/W mtgy_op_tc44
42d 10b4 R/W mtgy_op_tc45
42e 10b8 R/W mtgy_op_tc46
42f 10bc R/W mtgy_op_tc47
430 10c0 R/W mtgy_op_tc48
431 10c4 R/W mtgy_op_tc49
432 10c8 R/W mtgy_op_tc50
433 10cc R/W mtgy_op_tc51
434 10d0 R/W mtgy_op_tc52
435 10d4 R/W mtgy_op_tc53
436 10d8 R/W mtgy_op_tc54
437 10dc R/W mtgy_op_tc55
438 10e0 R/W mtgy_op_tc56
439 10e4 R/W mtgy_op_tc57
43a 10e8 R/W mtgy_op_tc58
43b 10ec R/W mtgy_op_tc59
43c 10f0 R/W mtgy_op_tc60
43d 10f4 R/W mtgy_op_tc61
43e 10f8 R/W mtgy_op_tc62
43f 10fc R/W mtgy_op_tc63
440 1100 R/W mtgy_op_tc64
441 1104 R/W mtgy_op_tc65
442 1108 R/W mtgy_op_tc66
443 110c R/W mtgy_op_tc67
444 1110 R/W mtgy_op_tc68
445 1114 R/W mtgy_op_tc69
446 1118 R/W mtgy_op_tc70
447 111c R/W mtgy_op_tc71
448 1120 R/W mtgy_op_tc72
449 1124 R/W mtgy_op_tc73
44a 1128 R/W mtgy_op_tc74
44b 112c R/W mtgy_op_tc75
44c 1130 R/W mtgy_op_tc76
44d 1134 R/W mtgy_op_tc77
44e 1138 R/W mtgy_op_tc78
44f 113c R/W mtgy_op_tc79
450 1140 R/W mtgy_op_tc80
451 1144 R/W mtgy_op_tc81
452 1148 R/W mtgy_op_tc82
453 114c R/W mtgy_op_tc83
454 1150 R/W mtgy_op_tc84
455 1154 R/W mtgy_op_tc85
456 1158 R/W mtgy_op_tc86
457 115c R/W mtgy_op_tc87
458 1160 R/W mtgy_op_tc88
459 1164 R/W mtgy_op_tc89
45a 1168 R/W mtgy_op_tc90
45b 116c R/W mtgy_op_tc91
45c 1170 R/W mtgy_op_tc92
45d 1174 R/W mtgy_op_tc93
45e 1178 R/W mtgy_op_tc94
45f 117c R/W mtgy_op_tc95
460 1180 R/W mtgy_op_tc96
461 1184 R/W mtgy_op_tc97
462 1188 R/W mtgy_op_tc98
463 118c R/W mtgy_op_tc99
464 1190 R/W mtgy_op_tc100
465 1194 R/W mtgy_op_tc101
466 1198 R/W mtgy_op_tc102
467 119c R/W mtgy_op_tc103
468 11a0 R/W mtgy_op_tc104
469 11a4 R/W mtgy_op_tc105
46a 11a8 R/W mtgy_op_tc106
46b 11ac R/W mtgy_op_tc107
46c 11b0 R/W mtgy_op_tc108
46d 11b4 R/W mtgy_op_tc109
46e 11b8 R/W mtgy_op_tc110
46f 11bc R/W mtgy_op_tc111
470 11c0 R/W mtgy_op_tc112
471 11c4 R/W mtgy_op_tc113
472 11c8 R/W mtgy_op_tc114
473 11cc R/W mtgy_op_tc115
474 11d0 R/W mtgy_op_tc116
475 11d4 R/W mtgy_op_tc117
476 11d8 R/W mtgy_op_tc118
477 11dc R/W mtgy_op_tc119
478 11e0 R/W mtgy_op_tc120
479 11e4 R/W mtgy_op_tc121
47a 11e8 R/W mtgy_op_tc122
47b 11ec R/W mtgy_op_tc123
47c 11f0 R/W mtgy_op_tc124
47d 11f4 R/W mtgy_op_tc125
47e 11f8 R/W mtgy_op_tc126
47f 11fc R/W mtgy_op_tc127
480 1200 R/W mtgy_op_ts0
481 1204 R/W mtgy_op_ts1
482 1208 R/W mtgy_op_ts2
483 120c R/W mtgy_op_ts3
484 1210 R/W mtgy_op_ts4
485 1214 R/W mtgy_op_ts5
486 1218 R/W mtgy_op_ts6
487 121c R/W mtgy_op_ts7
488 1220 R/W mtgy_op_ts8
489 1224 R/W mtgy_op_ts9
48a 1228 R/W mtgy_op_ts10
48b 122c R/W mtgy_op_ts11
48c 1230 R/W mtgy_op_ts12
48d 1234 R/W mtgy_op_ts13
48e 1238 R/W mtgy_op_ts14
48f 123c R/W mtgy_op_ts15
490 1240 R/W mtgy_op_ts16
491 1244 R/W mtgy_op_ts17
492 1248 R/W mtgy_op_ts18
493 124c R/W mtgy_op_ts19
494 1250 R/W mtgy_op_ts20
495 1254 R/W mtgy_op_ts21
496 1258 R/W mtgy_op_ts22
497 125c R/W mtgy_op_ts23
498 1260 R/W mtgy_op_ts24
499 1264 R/W mtgy_op_ts25
49a 1268 R/W mtgy_op_ts26
49b 126c R/W mtgy_op_ts27
49c 1270 R/W mtgy_op_ts28
49d 1274 R/W mtgy_op_ts29
49e 1278 R/W mtgy_op_ts30
49f 127c R/W mtgy_op_ts31
4a0 1280 R/W mtgy_op_ts32
4a1 1284 R/W mtgy_op_ts33
4a2 1288 R/W mtgy_op_ts34
4a3 128c R/W mtgy_op_ts35
4a4 1290 R/W mtgy_op_ts36
4a5 1294 R/W mtgy_op_ts37
4a6 1298 R/W mtgy_op_ts38
4a7 129c R/W mtgy_op_ts39
4a8 12a0 R/W mtgy_op_ts40
4a9 12a4 R/W mtgy_op_ts41
4aa 12a8 R/W mtgy_op_ts42
4ab 12ac R/W mtgy_op_ts43
4ac 12b0 R/W mtgy_op_ts44
4ad 12b4 R/W mtgy_op_ts45
4ae 12b8 R/W mtgy_op_ts46
4af 12bc R/W mtgy_op_ts47
4b0 12c0 R/W mtgy_op_ts48
4b1 12c4 R/W mtgy_op_ts49
4b2 12c8 R/W mtgy_op_ts50
4b3 12cc R/W mtgy_op_ts51
4b4 12d0 R/W mtgy_op_ts52
4b5 12d4 R/W mtgy_op_ts53
4b6 12d8 R/W mtgy_op_ts54
4b7 12dc R/W mtgy_op_ts55
4b8 12e0 R/W mtgy_op_ts56
4b9 12e4 R/W mtgy_op_ts57
4ba 12e8 R/W mtgy_op_ts58
4bb 12ec R/W mtgy_op_ts59
4bc 12f0 R/W mtgy_op_ts60
4bd 12f4 R/W mtgy_op_ts61
4be 12f8 R/W mtgy_op_ts62
4bf 12fc R/W mtgy_op_ts63
4c0 1300 R/W mtgy_op_ts64
4c1 1304 R/W mtgy_op_ts65
4c2 1308 R/W mtgy_op_ts66
4c3 130c R/W mtgy_op_ts67
4c4 1310 R/W mtgy_op_ts68
4c5 1314 R/W mtgy_op_ts69
4c6 1318 R/W mtgy_op_ts70
4c7 131c R/W mtgy_op_ts71
4c8 1320 R/W mtgy_op_ts72
4c9 1324 R/W mtgy_op_ts73
4ca 1328 R/W mtgy_op_ts74
4cb 132c R/W mtgy_op_ts75
4cc 1330 R/W mtgy_op_ts76
4cd 1334 R/W mtgy_op_ts77
4ce 1338 R/W mtgy_op_ts78
4cf 133c R/W mtgy_op_ts79
4d0 1340 R/W mtgy_op_ts80
4d1 1344 R/W mtgy_op_ts81
4d2 1348 R/W mtgy_op_ts82
4d3 134c R/W mtgy_op_ts83
4d4 1350 R/W mtgy_op_ts84
4d5 1354 R/W mtgy_op_ts85
4d6 1358 R/W mtgy_op_ts86
4d7 135c R/W mtgy_op_ts87
4d8 1360 R/W mtgy_op_ts88
4d9 1364 R/W mtgy_op_ts89
4da 1368 R/W mtgy_op_ts90
4db 136c R/W mtgy_op_ts91
4dc 1370 R/W mtgy_op_ts92
4dd 1374 R/W mtgy_op_ts93
4de 1378 R/W mtgy_op_ts94
4df 137c R/W mtgy_op_ts95
4e0 1380 R/W mtgy_op_ts96
4e1 1384 R/W mtgy_op_ts97
4e2 1388 R/W mtgy_op_ts98
4e3 138c R/W mtgy_op_ts99
4e4 1390 R/W mtgy_op_ts100
4e5 1394 R/W mtgy_op_ts101
4e6 1398 R/W mtgy_op_ts102
4e7 139c R/W mtgy_op_ts103
4e8 13a0 R/W mtgy_op_ts104
4e9 13a4 R/W mtgy_op_ts105
4ea 13a8 R/W mtgy_op_ts106
4eb 13ac R/W mtgy_op_ts107
4ec 13b0 R/W mtgy_op_ts108
4ed 13b4 R/W mtgy_op_ts109
4ee 13b8 R/W mtgy_op_ts110
4ef 13bc R/W mtgy_op_ts111
4f0 13c0 R/W mtgy_op_ts112
4f1 13c4 R/W mtgy_op_ts113
4f2 13c8 R/W mtgy_op_ts114
4f3 13cc R/W mtgy_op_ts115
4f4 13d0 R/W mtgy_op_ts116
4f5 13d4 R/W mtgy_op_ts117
4f6 13d8 R/W mtgy_op_ts118
4f7 13dc R/W mtgy_op_ts119
4f8 13e0 R/W mtgy_op_ts120
4f9 13e4 R/W mtgy_op_ts121
4fa 13e8 R/W mtgy_op_ts122
4fb 13ec R/W mtgy_op_ts123
4fc 13f0 R/W mtgy_op_ts124
4fd 13f4 R/W mtgy_op_ts125
4fe 13f8 R/W mtgy_op_ts126
4ff 13fc R/W mtgy_op_ts127
500 1400 R/W mtgy_op_p0
501 1404 R/W mtgy_op_p1
502 1408 R/W mtgy_op_p2
503 140c R/W mtgy_op_p3
504 1410 R/W mtgy_op_p4
505 1414 R/W mtgy_op_p5
506 1418 R/W mtgy_op_p6
507 141c R/W mtgy_op_p7
508 1420 R/W mtgy_op_p8
509 1424 R/W mtgy_op_p9
50a 1428 R/W mtgy_op_p10
50b 142c R/W mtgy_op_p11
50c 1430 R/W mtgy_op_p12
50d 1434 R/W mtgy_op_p13
50e 1438 R/W mtgy_op_p14
50f 143c R/W mtgy_op_p15
510 1440 R/W mtgy_op_p16
511 1444 R/W mtgy_op_p17
512 1448 R/W mtgy_op_p18
513 144c R/W mtgy_op_p19
514 1450 R/W mtgy_op_p20
515 1454 R/W mtgy_op_p21
516 1458 R/W mtgy_op_p22
517 145c R/W mtgy_op_p23
518 1460 R/W mtgy_op_p24
519 1464 R/W mtgy_op_p25
51a 1468 R/W mtgy_op_p26
51b 146c R/W mtgy_op_p27
51c 1470 R/W mtgy_op_p28
51d 1474 R/W mtgy_op_p29
51e 1478 R/W mtgy_op_p30
51f 147c R/W mtgy_op_p31
520 1480 R/W mtgy_op_p32
521 1484 R/W mtgy_op_p33
522 1488 R/W mtgy_op_p34
523 148c R/W mtgy_op_p35
524 1490 R/W mtgy_op_p36
525 1494 R/W mtgy_op_p37
526 1498 R/W mtgy_op_p38
527 149c R/W mtgy_op_p39
528 14a0 R/W mtgy_op_p40
529 14a4 R/W mtgy_op_p41
52a 14a8 R/W mtgy_op_p42
52b 14ac R/W mtgy_op_p43
52c 14b0 R/W mtgy_op_p44
52d 14b4 R/W mtgy_op_p45
52e 14b8 R/W mtgy_op_p46
52f 14bc R/W mtgy_op_p47
530 14c0 R/W mtgy_op_p48
531 14c4 R/W mtgy_op_p49
532 14c8 R/W mtgy_op_p50
533 14cc R/W mtgy_op_p51
534 14d0 R/W mtgy_op_p52
535 14d4 R/W mtgy_op_p53
536 14d8 R/W mtgy_op_p54
537 14dc R/W mtgy_op_p55
538 14e0 R/W mtgy_op_p56
539 14e4 R/W mtgy_op_p57
53a 14e8 R/W mtgy_op_p58
53b 14ec R/W mtgy_op_p59
53c 14f0 R/W mtgy_op_p60
53d 14f4 R/W mtgy_op_p61
53e 14f8 R/W mtgy_op_p62
53f 14fc R/W mtgy_op_p63
540 1500 R/W mtgy_op_p64
541 1504 R/W mtgy_op_p65
542 1508 R/W mtgy_op_p66
543 150c R/W mtgy_op_p67
544 1510 R/W mtgy_op_p68
545 1514 R/W mtgy_op_p69
546 1518 R/W mtgy_op_p70
547 151c R/W mtgy_op_p71
548 1520 R/W mtgy_op_p72
549 1524 R/W mtgy_op_p73
54a 1528 R/W mtgy_op_p74
54b 152c R/W mtgy_op_p75
54c 1530 R/W mtgy_op_p76
54d 1534 R/W mtgy_op_p77
54e 1538 R/W mtgy_op_p78
54f 153c R/W mtgy_op_p79
550 1540 R/W mtgy_op_p80
551 1544 R/W mtgy_op_p81
552 1548 R/W mtgy_op_p82
553 154c R/W mtgy_op_p83
554 1550 R/W mtgy_op_p84
555 1554 R/W mtgy_op_p85
556 1558 R/W mtgy_op_p86
557 155c R/W mtgy_op_p87
558 1560 R/W mtgy_op_p88
559 1564 R/W mtgy_op_p89
55a 1568 R/W mtgy_op_p90
55b 156c R/W mtgy_op_p91
55c 1570 R/W mtgy_op_p92
55d 1574 R/W mtgy_op_p93
55e 1578 R/W mtgy_op_p94
55f 157c R/W mtgy_op_p95
560 1580 R/W mtgy_op_p96
561 1584 R/W mtgy_op_p97
562 1588 R/W mtgy_op_p98
563 158c R/W mtgy_op_p99
564 1590 R/W mtgy_op_p100
565 1594 R/W mtgy_op_p101
566 1598 R/W mtgy_op_p102
567 159c R/W mtgy_op_p103
568 15a0 R/W mtgy_op_p104
569 15a4 R/W mtgy_op_p105
56a 15a8 R/W mtgy_op_p106
56b 15ac R/W mtgy_op_p107
56c 15b0 R/W mtgy_op_p108
56d 15b4 R/W mtgy_op_p109
56e 15b8 R/W mtgy_op_p110
56f 15bc R/W mtgy_op_p111
570 15c0 R/W mtgy_op_p112
571 15c4 R/W mtgy_op_p113
572 15c8 R/W mtgy_op_p114
573 15cc R/W mtgy_op_p115
574 15d0 R/W mtgy_op_p116
575 15d4 R/W mtgy_op_p117
576 15d8 R/W mtgy_op_p118
577 15dc R/W mtgy_op_p119
578 15e0 R/W mtgy_op_p120
579 15e4 R/W mtgy_op_p121
57a 15e8 R/W mtgy_op_p122
57b 15ec R/W mtgy_op_p123
57c 15f0 R/W mtgy_op_p124
57d 15f4 R/W mtgy_op_p125
57e 15f8 R/W mtgy_op_p126
57f 15fc R/W mtgy_op_p127
580 1600 R/W mtgy_op_b0
581 1604 R/W mtgy_op_b1
582 1608 R/W mtgy_op_b2
583 160c R/W mtgy_op_b3
584 1610 R/W mtgy_op_b4
585 1614 R/W mtgy_op_b5
586 1618 R/W mtgy_op_b6
587 161c R/W mtgy_op_b7
588 1620 R/W mtgy_op_b8
589 1624 R/W mtgy_op_b9
58a 1628 R/W mtgy_op_b10
58b 162c R/W mtgy_op_b11
58c 1630 R/W mtgy_op_b12
58d 1634 R/W mtgy_op_b13
58e 1638 R/W mtgy_op_b14
58f 163c R/W mtgy_op_b15
590 1640 R/W mtgy_op_b16
591 1644 R/W mtgy_op_b17
592 1648 R/W mtgy_op_b18
593 164c R/W mtgy_op_b19
594 1650 R/W mtgy_op_b20
595 1654 R/W mtgy_op_b21
596 1658 R/W mtgy_op_b22
597 165c R/W mtgy_op_b23
598 1660 R/W mtgy_op_b24
599 1664 R/W mtgy_op_b25
59a 1668 R/W mtgy_op_b26
59b 166c R/W mtgy_op_b27
59c 1670 R/W mtgy_op_b28
59d 1674 R/W mtgy_op_b29
59e 1678 R/W mtgy_op_b30
59f 167c R/W mtgy_op_b31
5a0 1680 R/W mtgy_op_b32
5a1 1684 R/W mtgy_op_b33
5a2 1688 R/W mtgy_op_b34
5a3 168c R/W mtgy_op_b35
5a4 1690 R/W mtgy_op_b36
5a5 1694 R/W mtgy_op_b37
5a6 1698 R/W mtgy_op_b38
5a7 169c R/W mtgy_op_b39
5a8 16a0 R/W mtgy_op_b40
5a9 16a4 R/W mtgy_op_b41
5aa 16a8 R/W mtgy_op_b42
5ab 16ac R/W mtgy_op_b43
5ac 16b0 R/W mtgy_op_b44
5ad 16b4 R/W mtgy_op_b45
5ae 16b8 R/W mtgy_op_b46
5af 16bc R/W mtgy_op_b47
5b0 16c0 R/W mtgy_op_b48
5b1 16c4 R/W mtgy_op_b49
5b2 16c8 R/W mtgy_op_b50
5b3 16cc R/W mtgy_op_b51
5b4 16d0 R/W mtgy_op_b52
5b5 16d4 R/W mtgy_op_b53
5b6 16d8 R/W mtgy_op_b54
5b7 16dc R/W mtgy_op_b55
5b8 16e0 R/W mtgy_op_b56
5b9 16e4 R/W mtgy_op_b57
5ba 16e8 R/W mtgy_op_b58
5bb 16ec R/W mtgy_op_b59
5bc 16f0 R/W mtgy_op_b60
5bd 16f4 R/W mtgy_op_b61
5be 16f8 R/W mtgy_op_b62
5bf 16fc R/W mtgy_op_b63
5c0 1700 R/W mtgy_op_b64
5c1 1704 R/W mtgy_op_b65
5c2 1708 R/W mtgy_op_b66
5c3 170c R/W mtgy_op_b67
5c4 1710 R/W mtgy_op_b68
5c5 1714 R/W mtgy_op_b69
5c6 1718 R/W mtgy_op_b70
5c7 171c R/W mtgy_op_b71
5c8 1720 R/W mtgy_op_b72
5c9 1724 R/W mtgy_op_b73
5ca 1728 R/W mtgy_op_b74
5cb 172c R/W mtgy_op_b75
5cc 1730 R/W mtgy_op_b76
5cd 1734 R/W mtgy_op_b77
5ce 1738 R/W mtgy_op_b78
5cf 173c R/W mtgy_op_b79
5d0 1740 R/W mtgy_op_b80
5d1 1744 R/W mtgy_op_b81
5d2 1748 R/W mtgy_op_b82
5d3 174c R/W mtgy_op_b83
5d4 1750 R/W mtgy_op_b84
5d5 1754 R/W mtgy_op_b85
5d6 1758 R/W mtgy_op_b86
5d7 175c R/W mtgy_op_b87
5d8 1760 R/W mtgy_op_b88
5d9 1764 R/W mtgy_op_b89
5da 1768 R/W mtgy_op_b90
5db 176c R/W mtgy_op_b91
5dc 1770 R/W mtgy_op_b92
5dd 1774 R/W mtgy_op_b93
5de 1778 R/W mtgy_op_b94
5df 177c R/W mtgy_op_b95
5e0 1780 R/W mtgy_op_b96
5e1 1784 R/W mtgy_op_b97
5e2 1788 R/W mtgy_op_b98
5e3 178c R/W mtgy_op_b99
5e4 1790 R/W mtgy_op_b100
5e5 1794 R/W mtgy_op_b101
5e6 1798 R/W mtgy_op_b102
5e7 179c R/W mtgy_op_b103
5e8 17a0 R/W mtgy_op_b104
5e9 17a4 R/W mtgy_op_b105
5ea 17a8 R/W mtgy_op_b106
5eb 17ac R/W mtgy_op_b107
5ec 17b0 R/W mtgy_op_b108
5ed 17b4 R/W mtgy_op_b109
5ee 17b8 R/W mtgy_op_b110
5ef 17bc R/W mtgy_op_b111
5f0 17c0 R/W mtgy_op_b112
5f1 17c4 R/W mtgy_op_b113
5f2 17c8 R/W mtgy_op_b114
5f3 17cc R/W mtgy_op_b115
5f4 17d0 R/W mtgy_op_b116
5f5 17d4 R/W mtgy_op_b117
5f6 17d8 R/W mtgy_op_b118
5f7 17dc R/W mtgy_op_b119
5f8 17e0 R/W mtgy_op_b120
5f9 17e4 R/W mtgy_op_b121
5fa 17e8 R/W mtgy_op_b122
5fb 17ec R/W mtgy_op_b123
5fc 17f0 R/W mtgy_op_b124
5fd 17f4 R/W mtgy_op_b125
5fe 17f8 R/W mtgy_op_b126
5ff 17fc R/W mtgy_op_b127
600 1800 R/W mtgy_op_a0
601 1804 R/W mtgy_op_a1
602 1808 R/W mtgy_op_a2
603 180c R/W mtgy_op_a3
604 1810 R/W mtgy_op_a4
605 1814 R/W mtgy_op_a5
606 1818 R/W mtgy_op_a6
607 181c R/W mtgy_op_a7
608 1820 R/W mtgy_op_a8
609 1824 R/W mtgy_op_a9
60a 1828 R/W mtgy_op_a10
60b 182c R/W mtgy_op_a11
60c 1830 R/W mtgy_op_a12
60d 1834 R/W mtgy_op_a13
60e 1838 R/W mtgy_op_a14
60f 183c R/W mtgy_op_a15
610 1840 R/W mtgy_op_a16
611 1844 R/W mtgy_op_a17
612 1848 R/W mtgy_op_a18
613 184c R/W mtgy_op_a19
614 1850 R/W mtgy_op_a20
615 1854 R/W mtgy_op_a21
616 1858 R/W mtgy_op_a22
617 185c R/W mtgy_op_a23
618 1860 R/W mtgy_op_a24
619 1864 R/W mtgy_op_a25
61a 1868 R/W mtgy_op_a26
61b 186c R/W mtgy_op_a27
61c 1870 R/W mtgy_op_a28
61d 1874 R/W mtgy_op_a29
61e 1878 R/W mtgy_op_a30
61f 187c R/W mtgy_op_a31
620 1880 R/W mtgy_op_a32
621 1884 R/W mtgy_op_a33
622 1888 R/W mtgy_op_a34
623 188c R/W mtgy_op_a35
624 1890 R/W mtgy_op_a36
625 1894 R/W mtgy_op_a37
626 1898 R/W mtgy_op_a38
627 189c R/W mtgy_op_a39
628 18a0 R/W mtgy_op_a40
629 18a4 R/W mtgy_op_a41
62a 18a8 R/W mtgy_op_a42
62b 18ac R/W mtgy_op_a43
62c 18b0 R/W mtgy_op_a44
62d 18b4 R/W mtgy_op_a45
62e 18b8 R/W mtgy_op_a46
62f 18bc R/W mtgy_op_a47
630 18c0 R/W mtgy_op_a48
631 18c4 R/W mtgy_op_a49
632 18c8 R/W mtgy_op_a50
633 18cc R/W mtgy_op_a51
634 18d0 R/W mtgy_op_a52
635 18d4 R/W mtgy_op_a53
636 18d8 R/W mtgy_op_a54
637 18dc R/W mtgy_op_a55
638 18e0 R/W mtgy_op_a56
639 18e4 R/W mtgy_op_a57
63a 18e8 R/W mtgy_op_a58
63b 18ec R/W mtgy_op_a59
63c 18f0 R/W mtgy_op_a60
63d 18f4 R/W mtgy_op_a61
63e 18f8 R/W mtgy_op_a62
63f 18fc R/W mtgy_op_a63
640 1900 R/W mtgy_op_a64
641 1904 R/W mtgy_op_a65
642 1908 R/W mtgy_op_a66
643 190c R/W mtgy_op_a67
644 1910 R/W mtgy_op_a68
645 1914 R/W mtgy_op_a69
646 1918 R/W mtgy_op_a70
647 191c R/W mtgy_op_a71
648 1920 R/W mtgy_op_a72
649 1924 R/W mtgy_op_a73
64a 1928 R/W mtgy_op_a74
64b 192c R/W mtgy_op_a75
64c 1930 R/W mtgy_op_a76
64d 1934 R/W mtgy_op_a77
64e 1938 R/W mtgy_op_a78
64f 193c R/W mtgy_op_a79
650 1940 R/W mtgy_op_a80
651 1944 R/W mtgy_op_a81
652 1948 R/W mtgy_op_a82
653 194c R/W mtgy_op_a83
654 1950 R/W mtgy_op_a84
655 1954 R/W mtgy_op_a85
656 1958 R/W mtgy_op_a86
657 195c R/W mtgy_op_a87
658 1960 R/W mtgy_op_a88
659 1964 R/W mtgy_op_a89
65a 1968 R/W mtgy_op_a90
65b 196c R/W mtgy_op_a91
65c 1970 R/W mtgy_op_a92
65d 1974 R/W mtgy_op_a93
65e 1978 R/W mtgy_op_a94
65f 197c R/W mtgy_op_a95
660 1980 R/W mtgy_op_a96
661 1984 R/W mtgy_op_a97
662 1988 R/W mtgy_op_a98
663 198c R/W mtgy_op_a99
664 1990 R/W mtgy_op_a100
665 1994 R/W mtgy_op_a101
666 1998 R/W mtgy_op_a102
667 199c R/W mtgy_op_a103
668 19a0 R/W mtgy_op_a104
669 19a4 R/W mtgy_op_a105
66a 19a8 R/W mtgy_op_a106
66b 19ac R/W mtgy_op_a107
66c 19b0 R/W mtgy_op_a108
66d 19b4 R/W mtgy_op_a109
66e 19b8 R/W mtgy_op_a110
66f 19bc R/W mtgy_op_a111
670 19c0 R/W mtgy_op_a112
671 19c4 R/W mtgy_op_a113
672 19c8 R/W mtgy_op_a114
673 19cc R/W mtgy_op_a115
674 19d0 R/W mtgy_op_a116
675 19d4 R/W mtgy_op_a117
676 19d8 R/W mtgy_op_a118
677 19dc R/W mtgy_op_a119
678 19e0 R/W mtgy_op_a120
679 19e4 R/W mtgy_op_a121
67a 19e8 R/W mtgy_op_a122
67b 19ec R/W mtgy_op_a123
67c 19f0 R/W mtgy_op_a124
67d 19f4 R/W mtgy_op_a125
67e 19f8 R/W mtgy_op_a126
67f 19fc R/W mtgy_op_a127
680 1a00 R/W mtgy_op_e0
681 1a04 R/W mtgy_op_e1
682 1a08 R/W mtgy_op_e2
683 1a0c R/W mtgy_op_e3
684 1a10 R/W mtgy_op_e4
685 1a14 R/W mtgy_op_e5
686 1a18 R/W mtgy_op_e6
687 1a1c R/W mtgy_op_e7
688 1a20 R/W mtgy_op_e8
689 1a24 R/W mtgy_op_e9
68a 1a28 R/W mtgy_op_e10
68b 1a2c R/W mtgy_op_e11
68c 1a30 R/W mtgy_op_e12
68d 1a34 R/W mtgy_op_e13
68e 1a38 R/W mtgy_op_e14
68f 1a3c R/W mtgy_op_e15
690 1a40 R/W mtgy_op_e16
691 1a44 R/W mtgy_op_e17
692 1a48 R/W mtgy_op_e18
693 1a4c R/W mtgy_op_e19
694 1a50 R/W mtgy_op_e20
695 1a54 R/W mtgy_op_e21
696 1a58 R/W mtgy_op_e22
697 1a5c R/W mtgy_op_e23
698 1a60 R/W mtgy_op_e24
699 1a64 R/W mtgy_op_e25
69a 1a68 R/W mtgy_op_e26
69b 1a6c R/W mtgy_op_e27
69c 1a70 R/W mtgy_op_e28
69d 1a74 R/W mtgy_op_e29
69e 1a78 R/W mtgy_op_e30
69f 1a7c R/W mtgy_op_e31
6a0 1a80 R/W mtgy_op_e32
6a1 1a84 R/W mtgy_op_e33
6a2 1a88 R/W mtgy_op_e34
6a3 1a8c R/W mtgy_op_e35
6a4 1a90 R/W mtgy_op_e36
6a5 1a94 R/W mtgy_op_e37
6a6 1a98 R/W mtgy_op_e38
6a7 1a9c R/W mtgy_op_e39
6a8 1aa0 R/W mtgy_op_e40
6a9 1aa4 R/W mtgy_op_e41
6aa 1aa8 R/W mtgy_op_e42
6ab 1aac R/W mtgy_op_e43
6ac 1ab0 R/W mtgy_op_e44
6ad 1ab4 R/W mtgy_op_e45
6ae 1ab8 R/W mtgy_op_e46
6af 1abc R/W mtgy_op_e47
6b0 1ac0 R/W mtgy_op_e48
6b1 1ac4 R/W mtgy_op_e49
6b2 1ac8 R/W mtgy_op_e50
6b3 1acc R/W mtgy_op_e51
6b4 1ad0 R/W mtgy_op_e52
6b5 1ad4 R/W mtgy_op_e53
6b6 1ad8 R/W mtgy_op_e54
6b7 1adc R/W mtgy_op_e55
6b8 1ae0 R/W mtgy_op_e56
6b9 1ae4 R/W mtgy_op_e57
6ba 1ae8 R/W mtgy_op_e58
6bb 1aec R/W mtgy_op_e59
6bc 1af0 R/W mtgy_op_e60
6bd 1af4 R/W mtgy_op_e61
6be 1af8 R/W mtgy_op_e62
6bf 1afc R/W mtgy_op_e63
6c0 1b00 R/W mtgy_op_e64
6c1 1b04 R/W mtgy_op_e65
6c2 1b08 R/W mtgy_op_e66
6c3 1b0c R/W mtgy_op_e67
6c4 1b10 R/W mtgy_op_e68
6c5 1b14 R/W mtgy_op_e69
6c6 1b18 R/W mtgy_op_e70
6c7 1b1c R/W mtgy_op_e71
6c8 1b20 R/W mtgy_op_e72
6c9 1b24 R/W mtgy_op_e73
6ca 1b28 R/W mtgy_op_e74
6cb 1b2c R/W mtgy_op_e75
6cc 1b30 R/W mtgy_op_e76
6cd 1b34 R/W mtgy_op_e77
6ce 1b38 R/W mtgy_op_e78
6cf 1b3c R/W mtgy_op_e79
6d0 1b40 R/W mtgy_op_e80
6d1 1b44 R/W mtgy_op_e81
6d2 1b48 R/W mtgy_op_e82
6d3 1b4c R/W mtgy_op_e83
6d4 1b50 R/W mtgy_op_e84
6d5 1b54 R/W mtgy_op_e85
6d6 1b58 R/W mtgy_op_e86
6d7 1b5c R/W mtgy_op_e87
6d8 1b60 R/W mtgy_op_e88
6d9 1b64 R/W mtgy_op_e89
6da 1b68 R/W mtgy_op_e90
6db 1b6c R/W mtgy_op_e91
6dc 1b70 R/W mtgy_op_e92
6dd 1b74 R/W mtgy_op_e93
6de 1b78 R/W mtgy_op_e94
6df 1b7c R/W mtgy_op_e95
6e0 1b80 R/W mtgy_op_e96
6e1 1b84 R/W mtgy_op_e97
6e2 1b88 R/W mtgy_op_e98
6e3 1b8c R/W mtgy_op_e99
6e4 1b90 R/W mtgy_op_e100
6e5 1b94 R/W mtgy_op_e101
6e6 1b98 R/W mtgy_op_e102
6e7 1b9c R/W mtgy_op_e103
6e8 1ba0 R/W mtgy_op_e104
6e9 1ba4 R/W mtgy_op_e105
6ea 1ba8 R/W mtgy_op_e106
6eb 1bac R/W mtgy_op_e107
6ec 1bb0 R/W mtgy_op_e108
6ed 1bb4 R/W mtgy_op_e109
6ee 1bb8 R/W mtgy_op_e110
6ef 1bbc R/W mtgy_op_e111
6f0 1bc0 R/W mtgy_op_e112
6f1 1bc4 R/W mtgy_op_e113
6f2 1bc8 R/W mtgy_op_e114
6f3 1bcc R/W mtgy_op_e115
6f4 1bd0 R/W mtgy_op_e116
6f5 1bd4 R/W mtgy_op_e117
6f6 1bd8 R/W mtgy_op_e118
6f7 1bdc R/W mtgy_op_e119
6f8 1be0 R/W mtgy_op_e120
6f9 1be4 R/W mtgy_op_e121
6fa 1be8 R/W mtgy_op_e122
6fb 1bec R/W mtgy_op_e123
6fc 1bf0 R/W mtgy_op_e124
6fd 1bf4 R/W mtgy_op_e125
6fe 1bf8 R/W mtgy_op_e126
6ff 1bfc R/W mtgy_op_e127
700 1c00 R/W mtgy_op_x0
701 1c04 R/W mtgy_op_x1
702 1c08 R/W mtgy_op_x2
703 1c0c R/W mtgy_op_x3
704 1c10 R/W mtgy_op_x4
705 1c14 R/W mtgy_op_x5
706 1c18 R/W mtgy_op_x6
707 1c1c R/W mtgy_op_x7
708 1c20 R/W mtgy_op_x8
709 1c24 R/W mtgy_op_x9
70a 1c28 R/W mtgy_op_x10
70b 1c2c R/W mtgy_op_x11
70c 1c30 R/W mtgy_op_x12
70d 1c34 R/W mtgy_op_x13
70e 1c38 R/W mtgy_op_x14
70f 1c3c R/W mtgy_op_x15
710 1c40 R/W mtgy_op_x16
711 1c44 R/W mtgy_op_x17
712 1c48 R/W mtgy_op_x18
713 1c4c R/W mtgy_op_x19
714 1c50 R/W mtgy_op_x20
715 1c54 R/W mtgy_op_x21
716 1c58 R/W mtgy_op_x22
717 1c5c R/W mtgy_op_x23
718 1c60 R/W mtgy_op_x24
719 1c64 R/W mtgy_op_x25
71a 1c68 R/W mtgy_op_x26
71b 1c6c R/W mtgy_op_x27
71c 1c70 R/W mtgy_op_x28
71d 1c74 R/W mtgy_op_x29
71e 1c78 R/W mtgy_op_x30
71f 1c7c R/W mtgy_op_x31
720 1c80 R/W mtgy_op_x32
721 1c84 R/W mtgy_op_x33
722 1c88 R/W mtgy_op_x34
723 1c8c R/W mtgy_op_x35
724 1c90 R/W mtgy_op_x36
725 1c94 R/W mtgy_op_x37
726 1c98 R/W mtgy_op_x38
727 1c9c R/W mtgy_op_x39
728 1ca0 R/W mtgy_op_x40
729 1ca4 R/W mtgy_op_x41
72a 1ca8 R/W mtgy_op_x42
72b 1cac R/W mtgy_op_x43
72c 1cb0 R/W mtgy_op_x44
72d 1cb4 R/W mtgy_op_x45
72e 1cb8 R/W mtgy_op_x46
72f 1cbc R/W mtgy_op_x47
730 1cc0 R/W mtgy_op_x48
731 1cc4 R/W mtgy_op_x49
732 1cc8 R/W mtgy_op_x50
733 1ccc R/W mtgy_op_x51
734 1cd0 R/W mtgy_op_x52
735 1cd4 R/W mtgy_op_x53
736 1cd8 R/W mtgy_op_x54
737 1cdc R/W mtgy_op_x55
738 1ce0 R/W mtgy_op_x56
739 1ce4 R/W mtgy_op_x57
73a 1ce8 R/W mtgy_op_x58
73b 1cec R/W mtgy_op_x59
73c 1cf0 R/W mtgy_op_x60
73d 1cf4 R/W mtgy_op_x61
73e 1cf8 R/W mtgy_op_x62
73f 1cfc R/W mtgy_op_x63
740 1d00 R/W mtgy_op_x64
741 1d04 R/W mtgy_op_x65
742 1d08 R/W mtgy_op_x66
743 1d0c R/W mtgy_op_x67
744 1d10 R/W mtgy_op_x68
745 1d14 R/W mtgy_op_x69
746 1d18 R/W mtgy_op_x70
747 1d1c R/W mtgy_op_x71
748 1d20 R/W mtgy_op_x72
749 1d24 R/W mtgy_op_x73
74a 1d28 R/W mtgy_op_x74
74b 1d2c R/W mtgy_op_x75
74c 1d30 R/W mtgy_op_x76
74d 1d34 R/W mtgy_op_x77
74e 1d38 R/W mtgy_op_x78
74f 1d3c R/W mtgy_op_x79
750 1d40 R/W mtgy_op_x80
751 1d44 R/W mtgy_op_x81
752 1d48 R/W mtgy_op_x82
753 1d4c R/W mtgy_op_x83
754 1d50 R/W mtgy_op_x84
755 1d54 R/W mtgy_op_x85
756 1d58 R/W mtgy_op_x86
757 1d5c R/W mtgy_op_x87
758 1d60 R/W mtgy_op_x88
759 1d64 R/W mtgy_op_x89
75a 1d68 R/W mtgy_op_x90
75b 1d6c R/W mtgy_op_x91
75c 1d70 R/W mtgy_op_x92
75d 1d74 R/W mtgy_op_x93
75e 1d78 R/W mtgy_op_x94
75f 1d7c R/W mtgy_op_x95
760 1d80 R/W mtgy_op_x96
761 1d84 R/W mtgy_op_x97
762 1d88 R/W mtgy_op_x98
763 1d8c R/W mtgy_op_x99
764 1d90 R/W mtgy_op_x100
765 1d94 R/W mtgy_op_x101
766 1d98 R/W mtgy_op_x102
767 1d9c R/W mtgy_op_x103
768 1da0 R/W mtgy_op_x104
769 1da4 R/W mtgy_op_x105
76a 1da8 R/W mtgy_op_x106
76b 1dac R/W mtgy_op_x107
76c 1db0 R/W mtgy_op_x108
76d 1db4 R/W mtgy_op_x109
76e 1db8 R/W mtgy_op_x110
76f 1dbc R/W mtgy_op_x111
770 1dc0 R/W mtgy_op_x112
771 1dc4 R/W mtgy_op_x113
772 1dc8 R/W mtgy_op_x114
773 1dcc R/W mtgy_op_x115
774 1dd0 R/W mtgy_op_x116
775 1dd4 R/W mtgy_op_x117
776 1dd8 R/W mtgy_op_x118
777 1ddc R/W mtgy_op_x119
778 1de0 R/W mtgy_op_x120
779 1de4 R/W mtgy_op_x121
77a 1de8 R/W mtgy_op_x122
77b 1dec R/W mtgy_op_x123
77c 1df0 R/W mtgy_op_x124
77d 1df4 R/W mtgy_op_x125
77e 1df8 R/W mtgy_op_x126
77f 1dfc R/W mtgy_op_x127
780-7ff 1e00-1ffc -  reserved

mtgy_cmd
MWMM command register:
R/W
0x00000094
Address@mtgy : 0x06432000
Address@com_mtgy : 0x06432000
Address@app_mtgy : 0x400e2000
Bits Reset value Name Description
31 - 27 "00000"
src_addr_x
Source address X specification.
The source address X specification will be interpreted as vertical RAM location source address offset of auxiliary operand E.
26 - 22 "00000"
src_addr_e
Source Address E specification.
The source address E specification will be interpreted as vertical RAM location source address offset of exponent E.
21 - 17 "00000"
dest_addr
Destination Address / Source Address A specification.
Depending on the operation the destination address specification will be interpreted as horizontal or vertical RAM location offset or as vertical RAM location source address offset of operand A.
16 - 12 "00000"
src_addr
Source Address specification.
Depending on the operation the source address specification will be interpreted as horizontal or vertical RAM location offset.
11 - 8 "0000"
op
The operation code of the core.
Following operations codes are supported:
0: MontMult (Montgomery Multiplication Step)
1: MontR (Montgomery Parameter R)
2: MontR2 (Montgomery Parameter R2 )
3: MontExp (Montgomery Exponentiation Step)
4: ModAdd (Modular Addition)
5: ModSub (Modular Subtraction)
6: CopyH2V (Copy from horizontal to vertical RAM location)
7: CopyV2V (Copy from vertical to vertical RAM location)
8: CopyH2H (Copy from horizontal to horizontal RAM location)
9: CopyV2H (Copy from vertical to horizontal RAM location)
10: MontMult1 (Montgomery Multiplication Step with '1' as A Operand)
7 - 4 "1001"
precision
Precision of executed operations.
0: 192 bit
1: 224 bit
2: 256 bit
3: 320 bit
4: 384 bit
5: 512 bit
6: 768 bit
7: 1024 bit
8: 1536 bit
9: 2048 bit
10: 3072 bit
11: 4096 bit
15 - 12: reserved
3 0
-
 reserved
2 "1"
f_sel
Finite Field Selection signal.
Defines if the calculations will be performed in
1: GF(p) or
0: GF(2^m).
1 "0"
abort
Abort Signal of the MWMM Core.
A running calculation can be aborted by issuing this signal.
After writing '1', this bit will automatically be reset.
0 "0"
start
Start Signal of the MWMM Core.
Setting this signal will instruct the Core to start the operation given by 'op' with precision specified by 'precision'. Depending on the operation the core will use the RAM location specified by 'src_addr', 'dest_addr', 'src_addr_e' and 'src_addr_x'. Calculations will be performed in the underlying finite field specified by 'f_sel'.
After writing '1', this bit will automatically be reset.


mtgy_stat
MWMM status register:
R
Address@mtgy : 0x06432004
Address@com_mtgy : 0x06432004
Address@app_mtgy : 0x400e2004
Bits Name Description
31 - 1 -
 reserved
0 done
Done signal from the MWMM core.


mtgy_irq_raw
MWMM raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@mtgy : 0x06432008
Address@com_mtgy : 0x06432008
Address@app_mtgy : 0x400e2008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core. Only a posedge on this signal will set the interrupt.


mtgy_irq_masked
MWMM masked IRQ:
Shows status of masked IRQs.
R
Address@mtgy : 0x0643200c
Address@com_mtgy : 0x0643200c
Address@app_mtgy : 0x400e200c
Bits Name Description
31 - 1 -
 reserved
0 done
Done signal from the MWMM core.


mtgy_irq_msk_set
MWMM IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
R/W
0x00000000
Address@mtgy : 0x06432010
Address@com_mtgy : 0x06432010
Address@app_mtgy : 0x400e2010
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core.


mtgy_irq_msk_reset
MWMM IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address@mtgy : 0x06432014
Address@com_mtgy : 0x06432014
Address@app_mtgy : 0x400e2014
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
done
Done signal from the MWMM core.


mtgy_op_tc0
MWMM TC register 0
R/W
0x00000000
Address@mtgy : 0x06433000
Address@com_mtgy : 0x06433000
Address@app_mtgy : 0x400e3000
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_tc1
MWMM TC register 1
R/W
0x00000000
Address@mtgy : 0x06433004
Address@com_mtgy : 0x06433004
Address@app_mtgy : 0x400e3004
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_tc2
MWMM TC register 2
R/W
0x00000000
Address@mtgy : 0x06433008
Address@com_mtgy : 0x06433008
Address@app_mtgy : 0x400e3008
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_tc3
MWMM TC register 3
R/W
0x00000000
Address@mtgy : 0x0643300c
Address@com_mtgy : 0x0643300c
Address@app_mtgy : 0x400e300c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_tc4
MWMM TC register 4
R/W
0x00000000
Address@mtgy : 0x06433010
Address@com_mtgy : 0x06433010
Address@app_mtgy : 0x400e3010
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_tc5
MWMM TC register 5
R/W
0x00000000
Address@mtgy : 0x06433014
Address@com_mtgy : 0x06433014
Address@app_mtgy : 0x400e3014
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_tc6
MWMM TC register 6
R/W
0x00000000
Address@mtgy : 0x06433018
Address@com_mtgy : 0x06433018
Address@app_mtgy : 0x400e3018
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_tc7
MWMM TC register 7
R/W
0x00000000
Address@mtgy : 0x0643301c
Address@com_mtgy : 0x0643301c
Address@app_mtgy : 0x400e301c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_tc8
MWMM TC register 8
R/W
0x00000000
Address@mtgy : 0x06433020
Address@com_mtgy : 0x06433020
Address@app_mtgy : 0x400e3020
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_tc9
MWMM TC register 9
R/W
0x00000000
Address@mtgy : 0x06433024
Address@com_mtgy : 0x06433024
Address@app_mtgy : 0x400e3024
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_tc10
MWMM TC register 10
R/W
0x00000000
Address@mtgy : 0x06433028
Address@com_mtgy : 0x06433028
Address@app_mtgy : 0x400e3028
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_tc11
MWMM TC register 11
R/W
0x00000000
Address@mtgy : 0x0643302c
Address@com_mtgy : 0x0643302c
Address@app_mtgy : 0x400e302c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_tc12
MWMM TC register 12
R/W
0x00000000
Address@mtgy : 0x06433030
Address@com_mtgy : 0x06433030
Address@app_mtgy : 0x400e3030
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_tc13
MWMM TC register 13
R/W
0x00000000
Address@mtgy : 0x06433034
Address@com_mtgy : 0x06433034
Address@app_mtgy : 0x400e3034
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_tc14
MWMM TC register 14
R/W
0x00000000
Address@mtgy : 0x06433038
Address@com_mtgy : 0x06433038
Address@app_mtgy : 0x400e3038
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_tc15
MWMM TC register 15
R/W
0x00000000
Address@mtgy : 0x0643303c
Address@com_mtgy : 0x0643303c
Address@app_mtgy : 0x400e303c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_tc16
MWMM TC register 16
R/W
0x00000000
Address@mtgy : 0x06433040
Address@com_mtgy : 0x06433040
Address@app_mtgy : 0x400e3040
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_tc17
MWMM TC register 17
R/W
0x00000000
Address@mtgy : 0x06433044
Address@com_mtgy : 0x06433044
Address@app_mtgy : 0x400e3044
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_tc18
MWMM TC register 18
R/W
0x00000000
Address@mtgy : 0x06433048
Address@com_mtgy : 0x06433048
Address@app_mtgy : 0x400e3048
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_tc19
MWMM TC register 19
R/W
0x00000000
Address@mtgy : 0x0643304c
Address@com_mtgy : 0x0643304c
Address@app_mtgy : 0x400e304c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_tc20
MWMM TC register 20
R/W
0x00000000
Address@mtgy : 0x06433050
Address@com_mtgy : 0x06433050
Address@app_mtgy : 0x400e3050
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_tc21
MWMM TC register 21
R/W
0x00000000
Address@mtgy : 0x06433054
Address@com_mtgy : 0x06433054
Address@app_mtgy : 0x400e3054
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_tc22
MWMM TC register 22
R/W
0x00000000
Address@mtgy : 0x06433058
Address@com_mtgy : 0x06433058
Address@app_mtgy : 0x400e3058
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_tc23
MWMM TC register 23
R/W
0x00000000
Address@mtgy : 0x0643305c
Address@com_mtgy : 0x0643305c
Address@app_mtgy : 0x400e305c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_tc24
MWMM TC register 24
R/W
0x00000000
Address@mtgy : 0x06433060
Address@com_mtgy : 0x06433060
Address@app_mtgy : 0x400e3060
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_tc25
MWMM TC register 25
R/W
0x00000000
Address@mtgy : 0x06433064
Address@com_mtgy : 0x06433064
Address@app_mtgy : 0x400e3064
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_tc26
MWMM TC register 26
R/W
0x00000000
Address@mtgy : 0x06433068
Address@com_mtgy : 0x06433068
Address@app_mtgy : 0x400e3068
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_tc27
MWMM TC register 27
R/W
0x00000000
Address@mtgy : 0x0643306c
Address@com_mtgy : 0x0643306c
Address@app_mtgy : 0x400e306c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_tc28
MWMM TC register 28
R/W
0x00000000
Address@mtgy : 0x06433070
Address@com_mtgy : 0x06433070
Address@app_mtgy : 0x400e3070
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_tc29
MWMM TC register 29
R/W
0x00000000
Address@mtgy : 0x06433074
Address@com_mtgy : 0x06433074
Address@app_mtgy : 0x400e3074
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_tc30
MWMM TC register 30
R/W
0x00000000
Address@mtgy : 0x06433078
Address@com_mtgy : 0x06433078
Address@app_mtgy : 0x400e3078
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_tc31
MWMM TC register 31
R/W
0x00000000
Address@mtgy : 0x0643307c
Address@com_mtgy : 0x0643307c
Address@app_mtgy : 0x400e307c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_tc32
MWMM TC register 32
R/W
0x00000000
Address@mtgy : 0x06433080
Address@com_mtgy : 0x06433080
Address@app_mtgy : 0x400e3080
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_tc33
MWMM TC register 33
R/W
0x00000000
Address@mtgy : 0x06433084
Address@com_mtgy : 0x06433084
Address@app_mtgy : 0x400e3084
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_tc34
MWMM TC register 34
R/W
0x00000000
Address@mtgy : 0x06433088
Address@com_mtgy : 0x06433088
Address@app_mtgy : 0x400e3088
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_tc35
MWMM TC register 35
R/W
0x00000000
Address@mtgy : 0x0643308c
Address@com_mtgy : 0x0643308c
Address@app_mtgy : 0x400e308c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_tc36
MWMM TC register 36
R/W
0x00000000
Address@mtgy : 0x06433090
Address@com_mtgy : 0x06433090
Address@app_mtgy : 0x400e3090
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_tc37
MWMM TC register 37
R/W
0x00000000
Address@mtgy : 0x06433094
Address@com_mtgy : 0x06433094
Address@app_mtgy : 0x400e3094
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_tc38
MWMM TC register 38
R/W
0x00000000
Address@mtgy : 0x06433098
Address@com_mtgy : 0x06433098
Address@app_mtgy : 0x400e3098
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_tc39
MWMM TC register 39
R/W
0x00000000
Address@mtgy : 0x0643309c
Address@com_mtgy : 0x0643309c
Address@app_mtgy : 0x400e309c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_tc40
MWMM TC register 40
R/W
0x00000000
Address@mtgy : 0x064330a0
Address@com_mtgy : 0x064330a0
Address@app_mtgy : 0x400e30a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_tc41
MWMM TC register 41
R/W
0x00000000
Address@mtgy : 0x064330a4
Address@com_mtgy : 0x064330a4
Address@app_mtgy : 0x400e30a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_tc42
MWMM TC register 42
R/W
0x00000000
Address@mtgy : 0x064330a8
Address@com_mtgy : 0x064330a8
Address@app_mtgy : 0x400e30a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_tc43
MWMM TC register 43
R/W
0x00000000
Address@mtgy : 0x064330ac
Address@com_mtgy : 0x064330ac
Address@app_mtgy : 0x400e30ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_tc44
MWMM TC register 44
R/W
0x00000000
Address@mtgy : 0x064330b0
Address@com_mtgy : 0x064330b0
Address@app_mtgy : 0x400e30b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_tc45
MWMM TC register 45
R/W
0x00000000
Address@mtgy : 0x064330b4
Address@com_mtgy : 0x064330b4
Address@app_mtgy : 0x400e30b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_tc46
MWMM TC register 46
R/W
0x00000000
Address@mtgy : 0x064330b8
Address@com_mtgy : 0x064330b8
Address@app_mtgy : 0x400e30b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_tc47
MWMM TC register 47
R/W
0x00000000
Address@mtgy : 0x064330bc
Address@com_mtgy : 0x064330bc
Address@app_mtgy : 0x400e30bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_tc48
MWMM TC register 48
R/W
0x00000000
Address@mtgy : 0x064330c0
Address@com_mtgy : 0x064330c0
Address@app_mtgy : 0x400e30c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_tc49
MWMM TC register 49
R/W
0x00000000
Address@mtgy : 0x064330c4
Address@com_mtgy : 0x064330c4
Address@app_mtgy : 0x400e30c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_tc50
MWMM TC register 50
R/W
0x00000000
Address@mtgy : 0x064330c8
Address@com_mtgy : 0x064330c8
Address@app_mtgy : 0x400e30c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_tc51
MWMM TC register 51
R/W
0x00000000
Address@mtgy : 0x064330cc
Address@com_mtgy : 0x064330cc
Address@app_mtgy : 0x400e30cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_tc52
MWMM TC register 52
R/W
0x00000000
Address@mtgy : 0x064330d0
Address@com_mtgy : 0x064330d0
Address@app_mtgy : 0x400e30d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_tc53
MWMM TC register 53
R/W
0x00000000
Address@mtgy : 0x064330d4
Address@com_mtgy : 0x064330d4
Address@app_mtgy : 0x400e30d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_tc54
MWMM TC register 54
R/W
0x00000000
Address@mtgy : 0x064330d8
Address@com_mtgy : 0x064330d8
Address@app_mtgy : 0x400e30d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_tc55
MWMM TC register 55
R/W
0x00000000
Address@mtgy : 0x064330dc
Address@com_mtgy : 0x064330dc
Address@app_mtgy : 0x400e30dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_tc56
MWMM TC register 56
R/W
0x00000000
Address@mtgy : 0x064330e0
Address@com_mtgy : 0x064330e0
Address@app_mtgy : 0x400e30e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_tc57
MWMM TC register 57
R/W
0x00000000
Address@mtgy : 0x064330e4
Address@com_mtgy : 0x064330e4
Address@app_mtgy : 0x400e30e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_tc58
MWMM TC register 58
R/W
0x00000000
Address@mtgy : 0x064330e8
Address@com_mtgy : 0x064330e8
Address@app_mtgy : 0x400e30e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_tc59
MWMM TC register 59
R/W
0x00000000
Address@mtgy : 0x064330ec
Address@com_mtgy : 0x064330ec
Address@app_mtgy : 0x400e30ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_tc60
MWMM TC register 60
R/W
0x00000000
Address@mtgy : 0x064330f0
Address@com_mtgy : 0x064330f0
Address@app_mtgy : 0x400e30f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_tc61
MWMM TC register 61
R/W
0x00000000
Address@mtgy : 0x064330f4
Address@com_mtgy : 0x064330f4
Address@app_mtgy : 0x400e30f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_tc62
MWMM TC register 62
R/W
0x00000000
Address@mtgy : 0x064330f8
Address@com_mtgy : 0x064330f8
Address@app_mtgy : 0x400e30f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_tc63
MWMM TC register 63
R/W
0x00000000
Address@mtgy : 0x064330fc
Address@com_mtgy : 0x064330fc
Address@app_mtgy : 0x400e30fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_tc64
MWMM TC register 64
R/W
0x00000000
Address@mtgy : 0x06433100
Address@com_mtgy : 0x06433100
Address@app_mtgy : 0x400e3100
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_tc65
MWMM TC register 65
R/W
0x00000000
Address@mtgy : 0x06433104
Address@com_mtgy : 0x06433104
Address@app_mtgy : 0x400e3104
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_tc66
MWMM TC register 66
R/W
0x00000000
Address@mtgy : 0x06433108
Address@com_mtgy : 0x06433108
Address@app_mtgy : 0x400e3108
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_tc67
MWMM TC register 67
R/W
0x00000000
Address@mtgy : 0x0643310c
Address@com_mtgy : 0x0643310c
Address@app_mtgy : 0x400e310c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_tc68
MWMM TC register 68
R/W
0x00000000
Address@mtgy : 0x06433110
Address@com_mtgy : 0x06433110
Address@app_mtgy : 0x400e3110
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_tc69
MWMM TC register 69
R/W
0x00000000
Address@mtgy : 0x06433114
Address@com_mtgy : 0x06433114
Address@app_mtgy : 0x400e3114
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_tc70
MWMM TC register 70
R/W
0x00000000
Address@mtgy : 0x06433118
Address@com_mtgy : 0x06433118
Address@app_mtgy : 0x400e3118
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_tc71
MWMM TC register 71
R/W
0x00000000
Address@mtgy : 0x0643311c
Address@com_mtgy : 0x0643311c
Address@app_mtgy : 0x400e311c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_tc72
MWMM TC register 72
R/W
0x00000000
Address@mtgy : 0x06433120
Address@com_mtgy : 0x06433120
Address@app_mtgy : 0x400e3120
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_tc73
MWMM TC register 73
R/W
0x00000000
Address@mtgy : 0x06433124
Address@com_mtgy : 0x06433124
Address@app_mtgy : 0x400e3124
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_tc74
MWMM TC register 74
R/W
0x00000000
Address@mtgy : 0x06433128
Address@com_mtgy : 0x06433128
Address@app_mtgy : 0x400e3128
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_tc75
MWMM TC register 75
R/W
0x00000000
Address@mtgy : 0x0643312c
Address@com_mtgy : 0x0643312c
Address@app_mtgy : 0x400e312c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_tc76
MWMM TC register 76
R/W
0x00000000
Address@mtgy : 0x06433130
Address@com_mtgy : 0x06433130
Address@app_mtgy : 0x400e3130
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_tc77
MWMM TC register 77
R/W
0x00000000
Address@mtgy : 0x06433134
Address@com_mtgy : 0x06433134
Address@app_mtgy : 0x400e3134
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_tc78
MWMM TC register 78
R/W
0x00000000
Address@mtgy : 0x06433138
Address@com_mtgy : 0x06433138
Address@app_mtgy : 0x400e3138
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_tc79
MWMM TC register 79
R/W
0x00000000
Address@mtgy : 0x0643313c
Address@com_mtgy : 0x0643313c
Address@app_mtgy : 0x400e313c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_tc80
MWMM TC register 80
R/W
0x00000000
Address@mtgy : 0x06433140
Address@com_mtgy : 0x06433140
Address@app_mtgy : 0x400e3140
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_tc81
MWMM TC register 81
R/W
0x00000000
Address@mtgy : 0x06433144
Address@com_mtgy : 0x06433144
Address@app_mtgy : 0x400e3144
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_tc82
MWMM TC register 82
R/W
0x00000000
Address@mtgy : 0x06433148
Address@com_mtgy : 0x06433148
Address@app_mtgy : 0x400e3148
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_tc83
MWMM TC register 83
R/W
0x00000000
Address@mtgy : 0x0643314c
Address@com_mtgy : 0x0643314c
Address@app_mtgy : 0x400e314c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_tc84
MWMM TC register 84
R/W
0x00000000
Address@mtgy : 0x06433150
Address@com_mtgy : 0x06433150
Address@app_mtgy : 0x400e3150
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_tc85
MWMM TC register 85
R/W
0x00000000
Address@mtgy : 0x06433154
Address@com_mtgy : 0x06433154
Address@app_mtgy : 0x400e3154
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_tc86
MWMM TC register 86
R/W
0x00000000
Address@mtgy : 0x06433158
Address@com_mtgy : 0x06433158
Address@app_mtgy : 0x400e3158
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_tc87
MWMM TC register 87
R/W
0x00000000
Address@mtgy : 0x0643315c
Address@com_mtgy : 0x0643315c
Address@app_mtgy : 0x400e315c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_tc88
MWMM TC register 88
R/W
0x00000000
Address@mtgy : 0x06433160
Address@com_mtgy : 0x06433160
Address@app_mtgy : 0x400e3160
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_tc89
MWMM TC register 89
R/W
0x00000000
Address@mtgy : 0x06433164
Address@com_mtgy : 0x06433164
Address@app_mtgy : 0x400e3164
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_tc90
MWMM TC register 90
R/W
0x00000000
Address@mtgy : 0x06433168
Address@com_mtgy : 0x06433168
Address@app_mtgy : 0x400e3168
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_tc91
MWMM TC register 91
R/W
0x00000000
Address@mtgy : 0x0643316c
Address@com_mtgy : 0x0643316c
Address@app_mtgy : 0x400e316c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_tc92
MWMM TC register 92
R/W
0x00000000
Address@mtgy : 0x06433170
Address@com_mtgy : 0x06433170
Address@app_mtgy : 0x400e3170
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_tc93
MWMM TC register 93
R/W
0x00000000
Address@mtgy : 0x06433174
Address@com_mtgy : 0x06433174
Address@app_mtgy : 0x400e3174
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_tc94
MWMM TC register 94
R/W
0x00000000
Address@mtgy : 0x06433178
Address@com_mtgy : 0x06433178
Address@app_mtgy : 0x400e3178
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_tc95
MWMM TC register 95
R/W
0x00000000
Address@mtgy : 0x0643317c
Address@com_mtgy : 0x0643317c
Address@app_mtgy : 0x400e317c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_tc96
MWMM TC register 96
R/W
0x00000000
Address@mtgy : 0x06433180
Address@com_mtgy : 0x06433180
Address@app_mtgy : 0x400e3180
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_tc97
MWMM TC register 97
R/W
0x00000000
Address@mtgy : 0x06433184
Address@com_mtgy : 0x06433184
Address@app_mtgy : 0x400e3184
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_tc98
MWMM TC register 98
R/W
0x00000000
Address@mtgy : 0x06433188
Address@com_mtgy : 0x06433188
Address@app_mtgy : 0x400e3188
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_tc99
MWMM TC register 99
R/W
0x00000000
Address@mtgy : 0x0643318c
Address@com_mtgy : 0x0643318c
Address@app_mtgy : 0x400e318c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_tc100
MWMM TC register 100
R/W
0x00000000
Address@mtgy : 0x06433190
Address@com_mtgy : 0x06433190
Address@app_mtgy : 0x400e3190
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_tc101
MWMM TC register 101
R/W
0x00000000
Address@mtgy : 0x06433194
Address@com_mtgy : 0x06433194
Address@app_mtgy : 0x400e3194
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_tc102
MWMM TC register 102
R/W
0x00000000
Address@mtgy : 0x06433198
Address@com_mtgy : 0x06433198
Address@app_mtgy : 0x400e3198
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_tc103
MWMM TC register 103
R/W
0x00000000
Address@mtgy : 0x0643319c
Address@com_mtgy : 0x0643319c
Address@app_mtgy : 0x400e319c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_tc104
MWMM TC register 104
R/W
0x00000000
Address@mtgy : 0x064331a0
Address@com_mtgy : 0x064331a0
Address@app_mtgy : 0x400e31a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_tc105
MWMM TC register 105
R/W
0x00000000
Address@mtgy : 0x064331a4
Address@com_mtgy : 0x064331a4
Address@app_mtgy : 0x400e31a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_tc106
MWMM TC register 106
R/W
0x00000000
Address@mtgy : 0x064331a8
Address@com_mtgy : 0x064331a8
Address@app_mtgy : 0x400e31a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_tc107
MWMM TC register 107
R/W
0x00000000
Address@mtgy : 0x064331ac
Address@com_mtgy : 0x064331ac
Address@app_mtgy : 0x400e31ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_tc108
MWMM TC register 108
R/W
0x00000000
Address@mtgy : 0x064331b0
Address@com_mtgy : 0x064331b0
Address@app_mtgy : 0x400e31b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_tc109
MWMM TC register 109
R/W
0x00000000
Address@mtgy : 0x064331b4
Address@com_mtgy : 0x064331b4
Address@app_mtgy : 0x400e31b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_tc110
MWMM TC register 110
R/W
0x00000000
Address@mtgy : 0x064331b8
Address@com_mtgy : 0x064331b8
Address@app_mtgy : 0x400e31b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_tc111
MWMM TC register 111
R/W
0x00000000
Address@mtgy : 0x064331bc
Address@com_mtgy : 0x064331bc
Address@app_mtgy : 0x400e31bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_tc112
MWMM TC register 112
R/W
0x00000000
Address@mtgy : 0x064331c0
Address@com_mtgy : 0x064331c0
Address@app_mtgy : 0x400e31c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_tc113
MWMM TC register 113
R/W
0x00000000
Address@mtgy : 0x064331c4
Address@com_mtgy : 0x064331c4
Address@app_mtgy : 0x400e31c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_tc114
MWMM TC register 114
R/W
0x00000000
Address@mtgy : 0x064331c8
Address@com_mtgy : 0x064331c8
Address@app_mtgy : 0x400e31c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_tc115
MWMM TC register 115
R/W
0x00000000
Address@mtgy : 0x064331cc
Address@com_mtgy : 0x064331cc
Address@app_mtgy : 0x400e31cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_tc116
MWMM TC register 116
R/W
0x00000000
Address@mtgy : 0x064331d0
Address@com_mtgy : 0x064331d0
Address@app_mtgy : 0x400e31d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_tc117
MWMM TC register 117
R/W
0x00000000
Address@mtgy : 0x064331d4
Address@com_mtgy : 0x064331d4
Address@app_mtgy : 0x400e31d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_tc118
MWMM TC register 118
R/W
0x00000000
Address@mtgy : 0x064331d8
Address@com_mtgy : 0x064331d8
Address@app_mtgy : 0x400e31d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_tc119
MWMM TC register 119
R/W
0x00000000
Address@mtgy : 0x064331dc
Address@com_mtgy : 0x064331dc
Address@app_mtgy : 0x400e31dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_tc120
MWMM TC register 120
R/W
0x00000000
Address@mtgy : 0x064331e0
Address@com_mtgy : 0x064331e0
Address@app_mtgy : 0x400e31e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_tc121
MWMM TC register 121
R/W
0x00000000
Address@mtgy : 0x064331e4
Address@com_mtgy : 0x064331e4
Address@app_mtgy : 0x400e31e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_tc122
MWMM TC register 122
R/W
0x00000000
Address@mtgy : 0x064331e8
Address@com_mtgy : 0x064331e8
Address@app_mtgy : 0x400e31e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_tc123
MWMM TC register 123
R/W
0x00000000
Address@mtgy : 0x064331ec
Address@com_mtgy : 0x064331ec
Address@app_mtgy : 0x400e31ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_tc124
MWMM TC register 124
R/W
0x00000000
Address@mtgy : 0x064331f0
Address@com_mtgy : 0x064331f0
Address@app_mtgy : 0x400e31f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_tc125
MWMM TC register 125
R/W
0x00000000
Address@mtgy : 0x064331f4
Address@com_mtgy : 0x064331f4
Address@app_mtgy : 0x400e31f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_tc126
MWMM TC register 126
R/W
0x00000000
Address@mtgy : 0x064331f8
Address@com_mtgy : 0x064331f8
Address@app_mtgy : 0x400e31f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_tc127
MWMM TC register 127
R/W
0x00000000
Address@mtgy : 0x064331fc
Address@com_mtgy : 0x064331fc
Address@app_mtgy : 0x400e31fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_ts0
MWMM TS register 0
R/W
0x00000000
Address@mtgy : 0x06433200
Address@com_mtgy : 0x06433200
Address@app_mtgy : 0x400e3200
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_ts1
MWMM TS register 1
R/W
0x00000000
Address@mtgy : 0x06433204
Address@com_mtgy : 0x06433204
Address@app_mtgy : 0x400e3204
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_ts2
MWMM TS register 2
R/W
0x00000000
Address@mtgy : 0x06433208
Address@com_mtgy : 0x06433208
Address@app_mtgy : 0x400e3208
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_ts3
MWMM TS register 3
R/W
0x00000000
Address@mtgy : 0x0643320c
Address@com_mtgy : 0x0643320c
Address@app_mtgy : 0x400e320c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_ts4
MWMM TS register 4
R/W
0x00000000
Address@mtgy : 0x06433210
Address@com_mtgy : 0x06433210
Address@app_mtgy : 0x400e3210
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_ts5
MWMM TS register 5
R/W
0x00000000
Address@mtgy : 0x06433214
Address@com_mtgy : 0x06433214
Address@app_mtgy : 0x400e3214
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_ts6
MWMM TS register 6
R/W
0x00000000
Address@mtgy : 0x06433218
Address@com_mtgy : 0x06433218
Address@app_mtgy : 0x400e3218
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_ts7
MWMM TS register 7
R/W
0x00000000
Address@mtgy : 0x0643321c
Address@com_mtgy : 0x0643321c
Address@app_mtgy : 0x400e321c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_ts8
MWMM TS register 8
R/W
0x00000000
Address@mtgy : 0x06433220
Address@com_mtgy : 0x06433220
Address@app_mtgy : 0x400e3220
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_ts9
MWMM TS register 9
R/W
0x00000000
Address@mtgy : 0x06433224
Address@com_mtgy : 0x06433224
Address@app_mtgy : 0x400e3224
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_ts10
MWMM TS register 10
R/W
0x00000000
Address@mtgy : 0x06433228
Address@com_mtgy : 0x06433228
Address@app_mtgy : 0x400e3228
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_ts11
MWMM TS register 11
R/W
0x00000000
Address@mtgy : 0x0643322c
Address@com_mtgy : 0x0643322c
Address@app_mtgy : 0x400e322c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_ts12
MWMM TS register 12
R/W
0x00000000
Address@mtgy : 0x06433230
Address@com_mtgy : 0x06433230
Address@app_mtgy : 0x400e3230
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_ts13
MWMM TS register 13
R/W
0x00000000
Address@mtgy : 0x06433234
Address@com_mtgy : 0x06433234
Address@app_mtgy : 0x400e3234
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_ts14
MWMM TS register 14
R/W
0x00000000
Address@mtgy : 0x06433238
Address@com_mtgy : 0x06433238
Address@app_mtgy : 0x400e3238
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_ts15
MWMM TS register 15
R/W
0x00000000
Address@mtgy : 0x0643323c
Address@com_mtgy : 0x0643323c
Address@app_mtgy : 0x400e323c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_ts16
MWMM TS register 16
R/W
0x00000000
Address@mtgy : 0x06433240
Address@com_mtgy : 0x06433240
Address@app_mtgy : 0x400e3240
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_ts17
MWMM TS register 17
R/W
0x00000000
Address@mtgy : 0x06433244
Address@com_mtgy : 0x06433244
Address@app_mtgy : 0x400e3244
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_ts18
MWMM TS register 18
R/W
0x00000000
Address@mtgy : 0x06433248
Address@com_mtgy : 0x06433248
Address@app_mtgy : 0x400e3248
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_ts19
MWMM TS register 19
R/W
0x00000000
Address@mtgy : 0x0643324c
Address@com_mtgy : 0x0643324c
Address@app_mtgy : 0x400e324c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_ts20
MWMM TS register 20
R/W
0x00000000
Address@mtgy : 0x06433250
Address@com_mtgy : 0x06433250
Address@app_mtgy : 0x400e3250
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_ts21
MWMM TS register 21
R/W
0x00000000
Address@mtgy : 0x06433254
Address@com_mtgy : 0x06433254
Address@app_mtgy : 0x400e3254
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_ts22
MWMM TS register 22
R/W
0x00000000
Address@mtgy : 0x06433258
Address@com_mtgy : 0x06433258
Address@app_mtgy : 0x400e3258
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_ts23
MWMM TS register 23
R/W
0x00000000
Address@mtgy : 0x0643325c
Address@com_mtgy : 0x0643325c
Address@app_mtgy : 0x400e325c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_ts24
MWMM TS register 24
R/W
0x00000000
Address@mtgy : 0x06433260
Address@com_mtgy : 0x06433260
Address@app_mtgy : 0x400e3260
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_ts25
MWMM TS register 25
R/W
0x00000000
Address@mtgy : 0x06433264
Address@com_mtgy : 0x06433264
Address@app_mtgy : 0x400e3264
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_ts26
MWMM TS register 26
R/W
0x00000000
Address@mtgy : 0x06433268
Address@com_mtgy : 0x06433268
Address@app_mtgy : 0x400e3268
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_ts27
MWMM TS register 27
R/W
0x00000000
Address@mtgy : 0x0643326c
Address@com_mtgy : 0x0643326c
Address@app_mtgy : 0x400e326c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_ts28
MWMM TS register 28
R/W
0x00000000
Address@mtgy : 0x06433270
Address@com_mtgy : 0x06433270
Address@app_mtgy : 0x400e3270
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_ts29
MWMM TS register 29
R/W
0x00000000
Address@mtgy : 0x06433274
Address@com_mtgy : 0x06433274
Address@app_mtgy : 0x400e3274
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_ts30
MWMM TS register 30
R/W
0x00000000
Address@mtgy : 0x06433278
Address@com_mtgy : 0x06433278
Address@app_mtgy : 0x400e3278
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_ts31
MWMM TS register 31
R/W
0x00000000
Address@mtgy : 0x0643327c
Address@com_mtgy : 0x0643327c
Address@app_mtgy : 0x400e327c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_ts32
MWMM TS register 32
R/W
0x00000000
Address@mtgy : 0x06433280
Address@com_mtgy : 0x06433280
Address@app_mtgy : 0x400e3280
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_ts33
MWMM TS register 33
R/W
0x00000000
Address@mtgy : 0x06433284
Address@com_mtgy : 0x06433284
Address@app_mtgy : 0x400e3284
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_ts34
MWMM TS register 34
R/W
0x00000000
Address@mtgy : 0x06433288
Address@com_mtgy : 0x06433288
Address@app_mtgy : 0x400e3288
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_ts35
MWMM TS register 35
R/W
0x00000000
Address@mtgy : 0x0643328c
Address@com_mtgy : 0x0643328c
Address@app_mtgy : 0x400e328c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_ts36
MWMM TS register 36
R/W
0x00000000
Address@mtgy : 0x06433290
Address@com_mtgy : 0x06433290
Address@app_mtgy : 0x400e3290
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_ts37
MWMM TS register 37
R/W
0x00000000
Address@mtgy : 0x06433294
Address@com_mtgy : 0x06433294
Address@app_mtgy : 0x400e3294
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_ts38
MWMM TS register 38
R/W
0x00000000
Address@mtgy : 0x06433298
Address@com_mtgy : 0x06433298
Address@app_mtgy : 0x400e3298
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_ts39
MWMM TS register 39
R/W
0x00000000
Address@mtgy : 0x0643329c
Address@com_mtgy : 0x0643329c
Address@app_mtgy : 0x400e329c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_ts40
MWMM TS register 40
R/W
0x00000000
Address@mtgy : 0x064332a0
Address@com_mtgy : 0x064332a0
Address@app_mtgy : 0x400e32a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_ts41
MWMM TS register 41
R/W
0x00000000
Address@mtgy : 0x064332a4
Address@com_mtgy : 0x064332a4
Address@app_mtgy : 0x400e32a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_ts42
MWMM TS register 42
R/W
0x00000000
Address@mtgy : 0x064332a8
Address@com_mtgy : 0x064332a8
Address@app_mtgy : 0x400e32a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_ts43
MWMM TS register 43
R/W
0x00000000
Address@mtgy : 0x064332ac
Address@com_mtgy : 0x064332ac
Address@app_mtgy : 0x400e32ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_ts44
MWMM TS register 44
R/W
0x00000000
Address@mtgy : 0x064332b0
Address@com_mtgy : 0x064332b0
Address@app_mtgy : 0x400e32b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_ts45
MWMM TS register 45
R/W
0x00000000
Address@mtgy : 0x064332b4
Address@com_mtgy : 0x064332b4
Address@app_mtgy : 0x400e32b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_ts46
MWMM TS register 46
R/W
0x00000000
Address@mtgy : 0x064332b8
Address@com_mtgy : 0x064332b8
Address@app_mtgy : 0x400e32b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_ts47
MWMM TS register 47
R/W
0x00000000
Address@mtgy : 0x064332bc
Address@com_mtgy : 0x064332bc
Address@app_mtgy : 0x400e32bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_ts48
MWMM TS register 48
R/W
0x00000000
Address@mtgy : 0x064332c0
Address@com_mtgy : 0x064332c0
Address@app_mtgy : 0x400e32c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_ts49
MWMM TS register 49
R/W
0x00000000
Address@mtgy : 0x064332c4
Address@com_mtgy : 0x064332c4
Address@app_mtgy : 0x400e32c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_ts50
MWMM TS register 50
R/W
0x00000000
Address@mtgy : 0x064332c8
Address@com_mtgy : 0x064332c8
Address@app_mtgy : 0x400e32c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_ts51
MWMM TS register 51
R/W
0x00000000
Address@mtgy : 0x064332cc
Address@com_mtgy : 0x064332cc
Address@app_mtgy : 0x400e32cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_ts52
MWMM TS register 52
R/W
0x00000000
Address@mtgy : 0x064332d0
Address@com_mtgy : 0x064332d0
Address@app_mtgy : 0x400e32d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_ts53
MWMM TS register 53
R/W
0x00000000
Address@mtgy : 0x064332d4
Address@com_mtgy : 0x064332d4
Address@app_mtgy : 0x400e32d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_ts54
MWMM TS register 54
R/W
0x00000000
Address@mtgy : 0x064332d8
Address@com_mtgy : 0x064332d8
Address@app_mtgy : 0x400e32d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_ts55
MWMM TS register 55
R/W
0x00000000
Address@mtgy : 0x064332dc
Address@com_mtgy : 0x064332dc
Address@app_mtgy : 0x400e32dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_ts56
MWMM TS register 56
R/W
0x00000000
Address@mtgy : 0x064332e0
Address@com_mtgy : 0x064332e0
Address@app_mtgy : 0x400e32e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_ts57
MWMM TS register 57
R/W
0x00000000
Address@mtgy : 0x064332e4
Address@com_mtgy : 0x064332e4
Address@app_mtgy : 0x400e32e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_ts58
MWMM TS register 58
R/W
0x00000000
Address@mtgy : 0x064332e8
Address@com_mtgy : 0x064332e8
Address@app_mtgy : 0x400e32e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_ts59
MWMM TS register 59
R/W
0x00000000
Address@mtgy : 0x064332ec
Address@com_mtgy : 0x064332ec
Address@app_mtgy : 0x400e32ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_ts60
MWMM TS register 60
R/W
0x00000000
Address@mtgy : 0x064332f0
Address@com_mtgy : 0x064332f0
Address@app_mtgy : 0x400e32f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_ts61
MWMM TS register 61
R/W
0x00000000
Address@mtgy : 0x064332f4
Address@com_mtgy : 0x064332f4
Address@app_mtgy : 0x400e32f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_ts62
MWMM TS register 62
R/W
0x00000000
Address@mtgy : 0x064332f8
Address@com_mtgy : 0x064332f8
Address@app_mtgy : 0x400e32f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_ts63
MWMM TS register 63
R/W
0x00000000
Address@mtgy : 0x064332fc
Address@com_mtgy : 0x064332fc
Address@app_mtgy : 0x400e32fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_ts64
MWMM TS register 64
R/W
0x00000000
Address@mtgy : 0x06433300
Address@com_mtgy : 0x06433300
Address@app_mtgy : 0x400e3300
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_ts65
MWMM TS register 65
R/W
0x00000000
Address@mtgy : 0x06433304
Address@com_mtgy : 0x06433304
Address@app_mtgy : 0x400e3304
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_ts66
MWMM TS register 66
R/W
0x00000000
Address@mtgy : 0x06433308
Address@com_mtgy : 0x06433308
Address@app_mtgy : 0x400e3308
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_ts67
MWMM TS register 67
R/W
0x00000000
Address@mtgy : 0x0643330c
Address@com_mtgy : 0x0643330c
Address@app_mtgy : 0x400e330c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_ts68
MWMM TS register 68
R/W
0x00000000
Address@mtgy : 0x06433310
Address@com_mtgy : 0x06433310
Address@app_mtgy : 0x400e3310
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_ts69
MWMM TS register 69
R/W
0x00000000
Address@mtgy : 0x06433314
Address@com_mtgy : 0x06433314
Address@app_mtgy : 0x400e3314
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_ts70
MWMM TS register 70
R/W
0x00000000
Address@mtgy : 0x06433318
Address@com_mtgy : 0x06433318
Address@app_mtgy : 0x400e3318
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_ts71
MWMM TS register 71
R/W
0x00000000
Address@mtgy : 0x0643331c
Address@com_mtgy : 0x0643331c
Address@app_mtgy : 0x400e331c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_ts72
MWMM TS register 72
R/W
0x00000000
Address@mtgy : 0x06433320
Address@com_mtgy : 0x06433320
Address@app_mtgy : 0x400e3320
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_ts73
MWMM TS register 73
R/W
0x00000000
Address@mtgy : 0x06433324
Address@com_mtgy : 0x06433324
Address@app_mtgy : 0x400e3324
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_ts74
MWMM TS register 74
R/W
0x00000000
Address@mtgy : 0x06433328
Address@com_mtgy : 0x06433328
Address@app_mtgy : 0x400e3328
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_ts75
MWMM TS register 75
R/W
0x00000000
Address@mtgy : 0x0643332c
Address@com_mtgy : 0x0643332c
Address@app_mtgy : 0x400e332c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_ts76
MWMM TS register 76
R/W
0x00000000
Address@mtgy : 0x06433330
Address@com_mtgy : 0x06433330
Address@app_mtgy : 0x400e3330
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_ts77
MWMM TS register 77
R/W
0x00000000
Address@mtgy : 0x06433334
Address@com_mtgy : 0x06433334
Address@app_mtgy : 0x400e3334
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_ts78
MWMM TS register 78
R/W
0x00000000
Address@mtgy : 0x06433338
Address@com_mtgy : 0x06433338
Address@app_mtgy : 0x400e3338
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_ts79
MWMM TS register 79
R/W
0x00000000
Address@mtgy : 0x0643333c
Address@com_mtgy : 0x0643333c
Address@app_mtgy : 0x400e333c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_ts80
MWMM TS register 80
R/W
0x00000000
Address@mtgy : 0x06433340
Address@com_mtgy : 0x06433340
Address@app_mtgy : 0x400e3340
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_ts81
MWMM TS register 81
R/W
0x00000000
Address@mtgy : 0x06433344
Address@com_mtgy : 0x06433344
Address@app_mtgy : 0x400e3344
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_ts82
MWMM TS register 82
R/W
0x00000000
Address@mtgy : 0x06433348
Address@com_mtgy : 0x06433348
Address@app_mtgy : 0x400e3348
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_ts83
MWMM TS register 83
R/W
0x00000000
Address@mtgy : 0x0643334c
Address@com_mtgy : 0x0643334c
Address@app_mtgy : 0x400e334c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_ts84
MWMM TS register 84
R/W
0x00000000
Address@mtgy : 0x06433350
Address@com_mtgy : 0x06433350
Address@app_mtgy : 0x400e3350
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_ts85
MWMM TS register 85
R/W
0x00000000
Address@mtgy : 0x06433354
Address@com_mtgy : 0x06433354
Address@app_mtgy : 0x400e3354
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_ts86
MWMM TS register 86
R/W
0x00000000
Address@mtgy : 0x06433358
Address@com_mtgy : 0x06433358
Address@app_mtgy : 0x400e3358
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_ts87
MWMM TS register 87
R/W
0x00000000
Address@mtgy : 0x0643335c
Address@com_mtgy : 0x0643335c
Address@app_mtgy : 0x400e335c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_ts88
MWMM TS register 88
R/W
0x00000000
Address@mtgy : 0x06433360
Address@com_mtgy : 0x06433360
Address@app_mtgy : 0x400e3360
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_ts89
MWMM TS register 89
R/W
0x00000000
Address@mtgy : 0x06433364
Address@com_mtgy : 0x06433364
Address@app_mtgy : 0x400e3364
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_ts90
MWMM TS register 90
R/W
0x00000000
Address@mtgy : 0x06433368
Address@com_mtgy : 0x06433368
Address@app_mtgy : 0x400e3368
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_ts91
MWMM TS register 91
R/W
0x00000000
Address@mtgy : 0x0643336c
Address@com_mtgy : 0x0643336c
Address@app_mtgy : 0x400e336c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_ts92
MWMM TS register 92
R/W
0x00000000
Address@mtgy : 0x06433370
Address@com_mtgy : 0x06433370
Address@app_mtgy : 0x400e3370
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_ts93
MWMM TS register 93
R/W
0x00000000
Address@mtgy : 0x06433374
Address@com_mtgy : 0x06433374
Address@app_mtgy : 0x400e3374
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_ts94
MWMM TS register 94
R/W
0x00000000
Address@mtgy : 0x06433378
Address@com_mtgy : 0x06433378
Address@app_mtgy : 0x400e3378
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_ts95
MWMM TS register 95
R/W
0x00000000
Address@mtgy : 0x0643337c
Address@com_mtgy : 0x0643337c
Address@app_mtgy : 0x400e337c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_ts96
MWMM TS register 96
R/W
0x00000000
Address@mtgy : 0x06433380
Address@com_mtgy : 0x06433380
Address@app_mtgy : 0x400e3380
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_ts97
MWMM TS register 97
R/W
0x00000000
Address@mtgy : 0x06433384
Address@com_mtgy : 0x06433384
Address@app_mtgy : 0x400e3384
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_ts98
MWMM TS register 98
R/W
0x00000000
Address@mtgy : 0x06433388
Address@com_mtgy : 0x06433388
Address@app_mtgy : 0x400e3388
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_ts99
MWMM TS register 99
R/W
0x00000000
Address@mtgy : 0x0643338c
Address@com_mtgy : 0x0643338c
Address@app_mtgy : 0x400e338c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_ts100
MWMM TS register 100
R/W
0x00000000
Address@mtgy : 0x06433390
Address@com_mtgy : 0x06433390
Address@app_mtgy : 0x400e3390
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_ts101
MWMM TS register 101
R/W
0x00000000
Address@mtgy : 0x06433394
Address@com_mtgy : 0x06433394
Address@app_mtgy : 0x400e3394
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_ts102
MWMM TS register 102
R/W
0x00000000
Address@mtgy : 0x06433398
Address@com_mtgy : 0x06433398
Address@app_mtgy : 0x400e3398
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_ts103
MWMM TS register 103
R/W
0x00000000
Address@mtgy : 0x0643339c
Address@com_mtgy : 0x0643339c
Address@app_mtgy : 0x400e339c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_ts104
MWMM TS register 104
R/W
0x00000000
Address@mtgy : 0x064333a0
Address@com_mtgy : 0x064333a0
Address@app_mtgy : 0x400e33a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_ts105
MWMM TS register 105
R/W
0x00000000
Address@mtgy : 0x064333a4
Address@com_mtgy : 0x064333a4
Address@app_mtgy : 0x400e33a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_ts106
MWMM TS register 106
R/W
0x00000000
Address@mtgy : 0x064333a8
Address@com_mtgy : 0x064333a8
Address@app_mtgy : 0x400e33a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_ts107
MWMM TS register 107
R/W
0x00000000
Address@mtgy : 0x064333ac
Address@com_mtgy : 0x064333ac
Address@app_mtgy : 0x400e33ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_ts108
MWMM TS register 108
R/W
0x00000000
Address@mtgy : 0x064333b0
Address@com_mtgy : 0x064333b0
Address@app_mtgy : 0x400e33b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_ts109
MWMM TS register 109
R/W
0x00000000
Address@mtgy : 0x064333b4
Address@com_mtgy : 0x064333b4
Address@app_mtgy : 0x400e33b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_ts110
MWMM TS register 110
R/W
0x00000000
Address@mtgy : 0x064333b8
Address@com_mtgy : 0x064333b8
Address@app_mtgy : 0x400e33b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_ts111
MWMM TS register 111
R/W
0x00000000
Address@mtgy : 0x064333bc
Address@com_mtgy : 0x064333bc
Address@app_mtgy : 0x400e33bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_ts112
MWMM TS register 112
R/W
0x00000000
Address@mtgy : 0x064333c0
Address@com_mtgy : 0x064333c0
Address@app_mtgy : 0x400e33c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_ts113
MWMM TS register 113
R/W
0x00000000
Address@mtgy : 0x064333c4
Address@com_mtgy : 0x064333c4
Address@app_mtgy : 0x400e33c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_ts114
MWMM TS register 114
R/W
0x00000000
Address@mtgy : 0x064333c8
Address@com_mtgy : 0x064333c8
Address@app_mtgy : 0x400e33c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_ts115
MWMM TS register 115
R/W
0x00000000
Address@mtgy : 0x064333cc
Address@com_mtgy : 0x064333cc
Address@app_mtgy : 0x400e33cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_ts116
MWMM TS register 116
R/W
0x00000000
Address@mtgy : 0x064333d0
Address@com_mtgy : 0x064333d0
Address@app_mtgy : 0x400e33d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_ts117
MWMM TS register 117
R/W
0x00000000
Address@mtgy : 0x064333d4
Address@com_mtgy : 0x064333d4
Address@app_mtgy : 0x400e33d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_ts118
MWMM TS register 118
R/W
0x00000000
Address@mtgy : 0x064333d8
Address@com_mtgy : 0x064333d8
Address@app_mtgy : 0x400e33d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_ts119
MWMM TS register 119
R/W
0x00000000
Address@mtgy : 0x064333dc
Address@com_mtgy : 0x064333dc
Address@app_mtgy : 0x400e33dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_ts120
MWMM TS register 120
R/W
0x00000000
Address@mtgy : 0x064333e0
Address@com_mtgy : 0x064333e0
Address@app_mtgy : 0x400e33e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_ts121
MWMM TS register 121
R/W
0x00000000
Address@mtgy : 0x064333e4
Address@com_mtgy : 0x064333e4
Address@app_mtgy : 0x400e33e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_ts122
MWMM TS register 122
R/W
0x00000000
Address@mtgy : 0x064333e8
Address@com_mtgy : 0x064333e8
Address@app_mtgy : 0x400e33e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_ts123
MWMM TS register 123
R/W
0x00000000
Address@mtgy : 0x064333ec
Address@com_mtgy : 0x064333ec
Address@app_mtgy : 0x400e33ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_ts124
MWMM TS register 124
R/W
0x00000000
Address@mtgy : 0x064333f0
Address@com_mtgy : 0x064333f0
Address@app_mtgy : 0x400e33f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_ts125
MWMM TS register 125
R/W
0x00000000
Address@mtgy : 0x064333f4
Address@com_mtgy : 0x064333f4
Address@app_mtgy : 0x400e33f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_ts126
MWMM TS register 126
R/W
0x00000000
Address@mtgy : 0x064333f8
Address@com_mtgy : 0x064333f8
Address@app_mtgy : 0x400e33f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_ts127
MWMM TS register 127
R/W
0x00000000
Address@mtgy : 0x064333fc
Address@com_mtgy : 0x064333fc
Address@app_mtgy : 0x400e33fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_p0
MWMM operand P register 0
R/W
0x00000000
Address@mtgy : 0x06433400
Address@com_mtgy : 0x06433400
Address@app_mtgy : 0x400e3400
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_p1
MWMM operand P register 1
R/W
0x00000000
Address@mtgy : 0x06433404
Address@com_mtgy : 0x06433404
Address@app_mtgy : 0x400e3404
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_p2
MWMM operand P register 2
R/W
0x00000000
Address@mtgy : 0x06433408
Address@com_mtgy : 0x06433408
Address@app_mtgy : 0x400e3408
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_p3
MWMM operand P register 3
R/W
0x00000000
Address@mtgy : 0x0643340c
Address@com_mtgy : 0x0643340c
Address@app_mtgy : 0x400e340c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_p4
MWMM operand P register 4
R/W
0x00000000
Address@mtgy : 0x06433410
Address@com_mtgy : 0x06433410
Address@app_mtgy : 0x400e3410
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_p5
MWMM operand P register 5
R/W
0x00000000
Address@mtgy : 0x06433414
Address@com_mtgy : 0x06433414
Address@app_mtgy : 0x400e3414
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_p6
MWMM operand P register 6
R/W
0x00000000
Address@mtgy : 0x06433418
Address@com_mtgy : 0x06433418
Address@app_mtgy : 0x400e3418
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_p7
MWMM operand P register 7
R/W
0x00000000
Address@mtgy : 0x0643341c
Address@com_mtgy : 0x0643341c
Address@app_mtgy : 0x400e341c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_p8
MWMM operand P register 8
R/W
0x00000000
Address@mtgy : 0x06433420
Address@com_mtgy : 0x06433420
Address@app_mtgy : 0x400e3420
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_p9
MWMM operand P register 9
R/W
0x00000000
Address@mtgy : 0x06433424
Address@com_mtgy : 0x06433424
Address@app_mtgy : 0x400e3424
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_p10
MWMM operand P register 10
R/W
0x00000000
Address@mtgy : 0x06433428
Address@com_mtgy : 0x06433428
Address@app_mtgy : 0x400e3428
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_p11
MWMM operand P register 11
R/W
0x00000000
Address@mtgy : 0x0643342c
Address@com_mtgy : 0x0643342c
Address@app_mtgy : 0x400e342c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_p12
MWMM operand P register 12
R/W
0x00000000
Address@mtgy : 0x06433430
Address@com_mtgy : 0x06433430
Address@app_mtgy : 0x400e3430
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_p13
MWMM operand P register 13
R/W
0x00000000
Address@mtgy : 0x06433434
Address@com_mtgy : 0x06433434
Address@app_mtgy : 0x400e3434
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_p14
MWMM operand P register 14
R/W
0x00000000
Address@mtgy : 0x06433438
Address@com_mtgy : 0x06433438
Address@app_mtgy : 0x400e3438
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_p15
MWMM operand P register 15
R/W
0x00000000
Address@mtgy : 0x0643343c
Address@com_mtgy : 0x0643343c
Address@app_mtgy : 0x400e343c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_p16
MWMM operand P register 16
R/W
0x00000000
Address@mtgy : 0x06433440
Address@com_mtgy : 0x06433440
Address@app_mtgy : 0x400e3440
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_p17
MWMM operand P register 17
R/W
0x00000000
Address@mtgy : 0x06433444
Address@com_mtgy : 0x06433444
Address@app_mtgy : 0x400e3444
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_p18
MWMM operand P register 18
R/W
0x00000000
Address@mtgy : 0x06433448
Address@com_mtgy : 0x06433448
Address@app_mtgy : 0x400e3448
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_p19
MWMM operand P register 19
R/W
0x00000000
Address@mtgy : 0x0643344c
Address@com_mtgy : 0x0643344c
Address@app_mtgy : 0x400e344c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_p20
MWMM operand P register 20
R/W
0x00000000
Address@mtgy : 0x06433450
Address@com_mtgy : 0x06433450
Address@app_mtgy : 0x400e3450
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_p21
MWMM operand P register 21
R/W
0x00000000
Address@mtgy : 0x06433454
Address@com_mtgy : 0x06433454
Address@app_mtgy : 0x400e3454
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_p22
MWMM operand P register 22
R/W
0x00000000
Address@mtgy : 0x06433458
Address@com_mtgy : 0x06433458
Address@app_mtgy : 0x400e3458
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_p23
MWMM operand P register 23
R/W
0x00000000
Address@mtgy : 0x0643345c
Address@com_mtgy : 0x0643345c
Address@app_mtgy : 0x400e345c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_p24
MWMM operand P register 24
R/W
0x00000000
Address@mtgy : 0x06433460
Address@com_mtgy : 0x06433460
Address@app_mtgy : 0x400e3460
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_p25
MWMM operand P register 25
R/W
0x00000000
Address@mtgy : 0x06433464
Address@com_mtgy : 0x06433464
Address@app_mtgy : 0x400e3464
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_p26
MWMM operand P register 26
R/W
0x00000000
Address@mtgy : 0x06433468
Address@com_mtgy : 0x06433468
Address@app_mtgy : 0x400e3468
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_p27
MWMM operand P register 27
R/W
0x00000000
Address@mtgy : 0x0643346c
Address@com_mtgy : 0x0643346c
Address@app_mtgy : 0x400e346c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_p28
MWMM operand P register 28
R/W
0x00000000
Address@mtgy : 0x06433470
Address@com_mtgy : 0x06433470
Address@app_mtgy : 0x400e3470
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_p29
MWMM operand P register 29
R/W
0x00000000
Address@mtgy : 0x06433474
Address@com_mtgy : 0x06433474
Address@app_mtgy : 0x400e3474
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_p30
MWMM operand P register 30
R/W
0x00000000
Address@mtgy : 0x06433478
Address@com_mtgy : 0x06433478
Address@app_mtgy : 0x400e3478
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_p31
MWMM operand P register 31
R/W
0x00000000
Address@mtgy : 0x0643347c
Address@com_mtgy : 0x0643347c
Address@app_mtgy : 0x400e347c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_p32
MWMM operand P register 32
R/W
0x00000000
Address@mtgy : 0x06433480
Address@com_mtgy : 0x06433480
Address@app_mtgy : 0x400e3480
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_p33
MWMM operand P register 33
R/W
0x00000000
Address@mtgy : 0x06433484
Address@com_mtgy : 0x06433484
Address@app_mtgy : 0x400e3484
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_p34
MWMM operand P register 34
R/W
0x00000000
Address@mtgy : 0x06433488
Address@com_mtgy : 0x06433488
Address@app_mtgy : 0x400e3488
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_p35
MWMM operand P register 35
R/W
0x00000000
Address@mtgy : 0x0643348c
Address@com_mtgy : 0x0643348c
Address@app_mtgy : 0x400e348c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_p36
MWMM operand P register 36
R/W
0x00000000
Address@mtgy : 0x06433490
Address@com_mtgy : 0x06433490
Address@app_mtgy : 0x400e3490
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_p37
MWMM operand P register 37
R/W
0x00000000
Address@mtgy : 0x06433494
Address@com_mtgy : 0x06433494
Address@app_mtgy : 0x400e3494
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_p38
MWMM operand P register 38
R/W
0x00000000
Address@mtgy : 0x06433498
Address@com_mtgy : 0x06433498
Address@app_mtgy : 0x400e3498
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_p39
MWMM operand P register 39
R/W
0x00000000
Address@mtgy : 0x0643349c
Address@com_mtgy : 0x0643349c
Address@app_mtgy : 0x400e349c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_p40
MWMM operand P register 40
R/W
0x00000000
Address@mtgy : 0x064334a0
Address@com_mtgy : 0x064334a0
Address@app_mtgy : 0x400e34a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_p41
MWMM operand P register 41
R/W
0x00000000
Address@mtgy : 0x064334a4
Address@com_mtgy : 0x064334a4
Address@app_mtgy : 0x400e34a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_p42
MWMM operand P register 42
R/W
0x00000000
Address@mtgy : 0x064334a8
Address@com_mtgy : 0x064334a8
Address@app_mtgy : 0x400e34a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_p43
MWMM operand P register 43
R/W
0x00000000
Address@mtgy : 0x064334ac
Address@com_mtgy : 0x064334ac
Address@app_mtgy : 0x400e34ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_p44
MWMM operand P register 44
R/W
0x00000000
Address@mtgy : 0x064334b0
Address@com_mtgy : 0x064334b0
Address@app_mtgy : 0x400e34b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_p45
MWMM operand P register 45
R/W
0x00000000
Address@mtgy : 0x064334b4
Address@com_mtgy : 0x064334b4
Address@app_mtgy : 0x400e34b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_p46
MWMM operand P register 46
R/W
0x00000000
Address@mtgy : 0x064334b8
Address@com_mtgy : 0x064334b8
Address@app_mtgy : 0x400e34b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_p47
MWMM operand P register 47
R/W
0x00000000
Address@mtgy : 0x064334bc
Address@com_mtgy : 0x064334bc
Address@app_mtgy : 0x400e34bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_p48
MWMM operand P register 48
R/W
0x00000000
Address@mtgy : 0x064334c0
Address@com_mtgy : 0x064334c0
Address@app_mtgy : 0x400e34c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_p49
MWMM operand P register 49
R/W
0x00000000
Address@mtgy : 0x064334c4
Address@com_mtgy : 0x064334c4
Address@app_mtgy : 0x400e34c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_p50
MWMM operand P register 50
R/W
0x00000000
Address@mtgy : 0x064334c8
Address@com_mtgy : 0x064334c8
Address@app_mtgy : 0x400e34c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_p51
MWMM operand P register 51
R/W
0x00000000
Address@mtgy : 0x064334cc
Address@com_mtgy : 0x064334cc
Address@app_mtgy : 0x400e34cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_p52
MWMM operand P register 52
R/W
0x00000000
Address@mtgy : 0x064334d0
Address@com_mtgy : 0x064334d0
Address@app_mtgy : 0x400e34d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_p53
MWMM operand P register 53
R/W
0x00000000
Address@mtgy : 0x064334d4
Address@com_mtgy : 0x064334d4
Address@app_mtgy : 0x400e34d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_p54
MWMM operand P register 54
R/W
0x00000000
Address@mtgy : 0x064334d8
Address@com_mtgy : 0x064334d8
Address@app_mtgy : 0x400e34d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_p55
MWMM operand P register 55
R/W
0x00000000
Address@mtgy : 0x064334dc
Address@com_mtgy : 0x064334dc
Address@app_mtgy : 0x400e34dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_p56
MWMM operand P register 56
R/W
0x00000000
Address@mtgy : 0x064334e0
Address@com_mtgy : 0x064334e0
Address@app_mtgy : 0x400e34e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_p57
MWMM operand P register 57
R/W
0x00000000
Address@mtgy : 0x064334e4
Address@com_mtgy : 0x064334e4
Address@app_mtgy : 0x400e34e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_p58
MWMM operand P register 58
R/W
0x00000000
Address@mtgy : 0x064334e8
Address@com_mtgy : 0x064334e8
Address@app_mtgy : 0x400e34e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_p59
MWMM operand P register 59
R/W
0x00000000
Address@mtgy : 0x064334ec
Address@com_mtgy : 0x064334ec
Address@app_mtgy : 0x400e34ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_p60
MWMM operand P register 60
R/W
0x00000000
Address@mtgy : 0x064334f0
Address@com_mtgy : 0x064334f0
Address@app_mtgy : 0x400e34f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_p61
MWMM operand P register 61
R/W
0x00000000
Address@mtgy : 0x064334f4
Address@com_mtgy : 0x064334f4
Address@app_mtgy : 0x400e34f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_p62
MWMM operand P register 62
R/W
0x00000000
Address@mtgy : 0x064334f8
Address@com_mtgy : 0x064334f8
Address@app_mtgy : 0x400e34f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_p63
MWMM operand P register 63
R/W
0x00000000
Address@mtgy : 0x064334fc
Address@com_mtgy : 0x064334fc
Address@app_mtgy : 0x400e34fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_p64
MWMM operand P register 64
R/W
0x00000000
Address@mtgy : 0x06433500
Address@com_mtgy : 0x06433500
Address@app_mtgy : 0x400e3500
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_p65
MWMM operand P register 65
R/W
0x00000000
Address@mtgy : 0x06433504
Address@com_mtgy : 0x06433504
Address@app_mtgy : 0x400e3504
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_p66
MWMM operand P register 66
R/W
0x00000000
Address@mtgy : 0x06433508
Address@com_mtgy : 0x06433508
Address@app_mtgy : 0x400e3508
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_p67
MWMM operand P register 67
R/W
0x00000000
Address@mtgy : 0x0643350c
Address@com_mtgy : 0x0643350c
Address@app_mtgy : 0x400e350c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_p68
MWMM operand P register 68
R/W
0x00000000
Address@mtgy : 0x06433510
Address@com_mtgy : 0x06433510
Address@app_mtgy : 0x400e3510
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_p69
MWMM operand P register 69
R/W
0x00000000
Address@mtgy : 0x06433514
Address@com_mtgy : 0x06433514
Address@app_mtgy : 0x400e3514
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_p70
MWMM operand P register 70
R/W
0x00000000
Address@mtgy : 0x06433518
Address@com_mtgy : 0x06433518
Address@app_mtgy : 0x400e3518
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_p71
MWMM operand P register 71
R/W
0x00000000
Address@mtgy : 0x0643351c
Address@com_mtgy : 0x0643351c
Address@app_mtgy : 0x400e351c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_p72
MWMM operand P register 72
R/W
0x00000000
Address@mtgy : 0x06433520
Address@com_mtgy : 0x06433520
Address@app_mtgy : 0x400e3520
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_p73
MWMM operand P register 73
R/W
0x00000000
Address@mtgy : 0x06433524
Address@com_mtgy : 0x06433524
Address@app_mtgy : 0x400e3524
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_p74
MWMM operand P register 74
R/W
0x00000000
Address@mtgy : 0x06433528
Address@com_mtgy : 0x06433528
Address@app_mtgy : 0x400e3528
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_p75
MWMM operand P register 75
R/W
0x00000000
Address@mtgy : 0x0643352c
Address@com_mtgy : 0x0643352c
Address@app_mtgy : 0x400e352c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_p76
MWMM operand P register 76
R/W
0x00000000
Address@mtgy : 0x06433530
Address@com_mtgy : 0x06433530
Address@app_mtgy : 0x400e3530
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_p77
MWMM operand P register 77
R/W
0x00000000
Address@mtgy : 0x06433534
Address@com_mtgy : 0x06433534
Address@app_mtgy : 0x400e3534
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_p78
MWMM operand P register 78
R/W
0x00000000
Address@mtgy : 0x06433538
Address@com_mtgy : 0x06433538
Address@app_mtgy : 0x400e3538
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_p79
MWMM operand P register 79
R/W
0x00000000
Address@mtgy : 0x0643353c
Address@com_mtgy : 0x0643353c
Address@app_mtgy : 0x400e353c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_p80
MWMM operand P register 80
R/W
0x00000000
Address@mtgy : 0x06433540
Address@com_mtgy : 0x06433540
Address@app_mtgy : 0x400e3540
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_p81
MWMM operand P register 81
R/W
0x00000000
Address@mtgy : 0x06433544
Address@com_mtgy : 0x06433544
Address@app_mtgy : 0x400e3544
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_p82
MWMM operand P register 82
R/W
0x00000000
Address@mtgy : 0x06433548
Address@com_mtgy : 0x06433548
Address@app_mtgy : 0x400e3548
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_p83
MWMM operand P register 83
R/W
0x00000000
Address@mtgy : 0x0643354c
Address@com_mtgy : 0x0643354c
Address@app_mtgy : 0x400e354c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_p84
MWMM operand P register 84
R/W
0x00000000
Address@mtgy : 0x06433550
Address@com_mtgy : 0x06433550
Address@app_mtgy : 0x400e3550
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_p85
MWMM operand P register 85
R/W
0x00000000
Address@mtgy : 0x06433554
Address@com_mtgy : 0x06433554
Address@app_mtgy : 0x400e3554
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_p86
MWMM operand P register 86
R/W
0x00000000
Address@mtgy : 0x06433558
Address@com_mtgy : 0x06433558
Address@app_mtgy : 0x400e3558
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_p87
MWMM operand P register 87
R/W
0x00000000
Address@mtgy : 0x0643355c
Address@com_mtgy : 0x0643355c
Address@app_mtgy : 0x400e355c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_p88
MWMM operand P register 88
R/W
0x00000000
Address@mtgy : 0x06433560
Address@com_mtgy : 0x06433560
Address@app_mtgy : 0x400e3560
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_p89
MWMM operand P register 89
R/W
0x00000000
Address@mtgy : 0x06433564
Address@com_mtgy : 0x06433564
Address@app_mtgy : 0x400e3564
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_p90
MWMM operand P register 90
R/W
0x00000000
Address@mtgy : 0x06433568
Address@com_mtgy : 0x06433568
Address@app_mtgy : 0x400e3568
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_p91
MWMM operand P register 91
R/W
0x00000000
Address@mtgy : 0x0643356c
Address@com_mtgy : 0x0643356c
Address@app_mtgy : 0x400e356c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_p92
MWMM operand P register 92
R/W
0x00000000
Address@mtgy : 0x06433570
Address@com_mtgy : 0x06433570
Address@app_mtgy : 0x400e3570
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_p93
MWMM operand P register 93
R/W
0x00000000
Address@mtgy : 0x06433574
Address@com_mtgy : 0x06433574
Address@app_mtgy : 0x400e3574
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_p94
MWMM operand P register 94
R/W
0x00000000
Address@mtgy : 0x06433578
Address@com_mtgy : 0x06433578
Address@app_mtgy : 0x400e3578
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_p95
MWMM operand P register 95
R/W
0x00000000
Address@mtgy : 0x0643357c
Address@com_mtgy : 0x0643357c
Address@app_mtgy : 0x400e357c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_p96
MWMM operand P register 96
R/W
0x00000000
Address@mtgy : 0x06433580
Address@com_mtgy : 0x06433580
Address@app_mtgy : 0x400e3580
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_p97
MWMM operand P register 97
R/W
0x00000000
Address@mtgy : 0x06433584
Address@com_mtgy : 0x06433584
Address@app_mtgy : 0x400e3584
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_p98
MWMM operand P register 98
R/W
0x00000000
Address@mtgy : 0x06433588
Address@com_mtgy : 0x06433588
Address@app_mtgy : 0x400e3588
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_p99
MWMM operand P register 99
R/W
0x00000000
Address@mtgy : 0x0643358c
Address@com_mtgy : 0x0643358c
Address@app_mtgy : 0x400e358c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_p100
MWMM operand P register 100
R/W
0x00000000
Address@mtgy : 0x06433590
Address@com_mtgy : 0x06433590
Address@app_mtgy : 0x400e3590
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_p101
MWMM operand P register 101
R/W
0x00000000
Address@mtgy : 0x06433594
Address@com_mtgy : 0x06433594
Address@app_mtgy : 0x400e3594
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_p102
MWMM operand P register 102
R/W
0x00000000
Address@mtgy : 0x06433598
Address@com_mtgy : 0x06433598
Address@app_mtgy : 0x400e3598
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_p103
MWMM operand P register 103
R/W
0x00000000
Address@mtgy : 0x0643359c
Address@com_mtgy : 0x0643359c
Address@app_mtgy : 0x400e359c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_p104
MWMM operand P register 104
R/W
0x00000000
Address@mtgy : 0x064335a0
Address@com_mtgy : 0x064335a0
Address@app_mtgy : 0x400e35a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_p105
MWMM operand P register 105
R/W
0x00000000
Address@mtgy : 0x064335a4
Address@com_mtgy : 0x064335a4
Address@app_mtgy : 0x400e35a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_p106
MWMM operand P register 106
R/W
0x00000000
Address@mtgy : 0x064335a8
Address@com_mtgy : 0x064335a8
Address@app_mtgy : 0x400e35a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_p107
MWMM operand P register 107
R/W
0x00000000
Address@mtgy : 0x064335ac
Address@com_mtgy : 0x064335ac
Address@app_mtgy : 0x400e35ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_p108
MWMM operand P register 108
R/W
0x00000000
Address@mtgy : 0x064335b0
Address@com_mtgy : 0x064335b0
Address@app_mtgy : 0x400e35b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_p109
MWMM operand P register 109
R/W
0x00000000
Address@mtgy : 0x064335b4
Address@com_mtgy : 0x064335b4
Address@app_mtgy : 0x400e35b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_p110
MWMM operand P register 110
R/W
0x00000000
Address@mtgy : 0x064335b8
Address@com_mtgy : 0x064335b8
Address@app_mtgy : 0x400e35b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_p111
MWMM operand P register 111
R/W
0x00000000
Address@mtgy : 0x064335bc
Address@com_mtgy : 0x064335bc
Address@app_mtgy : 0x400e35bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_p112
MWMM operand P register 112
R/W
0x00000000
Address@mtgy : 0x064335c0
Address@com_mtgy : 0x064335c0
Address@app_mtgy : 0x400e35c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_p113
MWMM operand P register 113
R/W
0x00000000
Address@mtgy : 0x064335c4
Address@com_mtgy : 0x064335c4
Address@app_mtgy : 0x400e35c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_p114
MWMM operand P register 114
R/W
0x00000000
Address@mtgy : 0x064335c8
Address@com_mtgy : 0x064335c8
Address@app_mtgy : 0x400e35c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_p115
MWMM operand P register 115
R/W
0x00000000
Address@mtgy : 0x064335cc
Address@com_mtgy : 0x064335cc
Address@app_mtgy : 0x400e35cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_p116
MWMM operand P register 116
R/W
0x00000000
Address@mtgy : 0x064335d0
Address@com_mtgy : 0x064335d0
Address@app_mtgy : 0x400e35d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_p117
MWMM operand P register 117
R/W
0x00000000
Address@mtgy : 0x064335d4
Address@com_mtgy : 0x064335d4
Address@app_mtgy : 0x400e35d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_p118
MWMM operand P register 118
R/W
0x00000000
Address@mtgy : 0x064335d8
Address@com_mtgy : 0x064335d8
Address@app_mtgy : 0x400e35d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_p119
MWMM operand P register 119
R/W
0x00000000
Address@mtgy : 0x064335dc
Address@com_mtgy : 0x064335dc
Address@app_mtgy : 0x400e35dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_p120
MWMM operand P register 120
R/W
0x00000000
Address@mtgy : 0x064335e0
Address@com_mtgy : 0x064335e0
Address@app_mtgy : 0x400e35e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_p121
MWMM operand P register 121
R/W
0x00000000
Address@mtgy : 0x064335e4
Address@com_mtgy : 0x064335e4
Address@app_mtgy : 0x400e35e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_p122
MWMM operand P register 122
R/W
0x00000000
Address@mtgy : 0x064335e8
Address@com_mtgy : 0x064335e8
Address@app_mtgy : 0x400e35e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_p123
MWMM operand P register 123
R/W
0x00000000
Address@mtgy : 0x064335ec
Address@com_mtgy : 0x064335ec
Address@app_mtgy : 0x400e35ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_p124
MWMM operand P register 124
R/W
0x00000000
Address@mtgy : 0x064335f0
Address@com_mtgy : 0x064335f0
Address@app_mtgy : 0x400e35f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_p125
MWMM operand P register 125
R/W
0x00000000
Address@mtgy : 0x064335f4
Address@com_mtgy : 0x064335f4
Address@app_mtgy : 0x400e35f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_p126
MWMM operand P register 126
R/W
0x00000000
Address@mtgy : 0x064335f8
Address@com_mtgy : 0x064335f8
Address@app_mtgy : 0x400e35f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_p127
MWMM operand P register 127
R/W
0x00000000
Address@mtgy : 0x064335fc
Address@com_mtgy : 0x064335fc
Address@app_mtgy : 0x400e35fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_b0
MWMM operand B register 0
R/W
0x00000000
Address@mtgy : 0x06433600
Address@com_mtgy : 0x06433600
Address@app_mtgy : 0x400e3600
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_b1
MWMM operand B register 1
R/W
0x00000000
Address@mtgy : 0x06433604
Address@com_mtgy : 0x06433604
Address@app_mtgy : 0x400e3604
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_b2
MWMM operand B register 2
R/W
0x00000000
Address@mtgy : 0x06433608
Address@com_mtgy : 0x06433608
Address@app_mtgy : 0x400e3608
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_b3
MWMM operand B register 3
R/W
0x00000000
Address@mtgy : 0x0643360c
Address@com_mtgy : 0x0643360c
Address@app_mtgy : 0x400e360c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_b4
MWMM operand B register 4
R/W
0x00000000
Address@mtgy : 0x06433610
Address@com_mtgy : 0x06433610
Address@app_mtgy : 0x400e3610
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_b5
MWMM operand B register 5
R/W
0x00000000
Address@mtgy : 0x06433614
Address@com_mtgy : 0x06433614
Address@app_mtgy : 0x400e3614
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_b6
MWMM operand B register 6
R/W
0x00000000
Address@mtgy : 0x06433618
Address@com_mtgy : 0x06433618
Address@app_mtgy : 0x400e3618
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_b7
MWMM operand B register 7
R/W
0x00000000
Address@mtgy : 0x0643361c
Address@com_mtgy : 0x0643361c
Address@app_mtgy : 0x400e361c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_b8
MWMM operand B register 8
R/W
0x00000000
Address@mtgy : 0x06433620
Address@com_mtgy : 0x06433620
Address@app_mtgy : 0x400e3620
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_b9
MWMM operand B register 9
R/W
0x00000000
Address@mtgy : 0x06433624
Address@com_mtgy : 0x06433624
Address@app_mtgy : 0x400e3624
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_b10
MWMM operand B register 10
R/W
0x00000000
Address@mtgy : 0x06433628
Address@com_mtgy : 0x06433628
Address@app_mtgy : 0x400e3628
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_b11
MWMM operand B register 11
R/W
0x00000000
Address@mtgy : 0x0643362c
Address@com_mtgy : 0x0643362c
Address@app_mtgy : 0x400e362c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_b12
MWMM operand B register 12
R/W
0x00000000
Address@mtgy : 0x06433630
Address@com_mtgy : 0x06433630
Address@app_mtgy : 0x400e3630
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_b13
MWMM operand B register 13
R/W
0x00000000
Address@mtgy : 0x06433634
Address@com_mtgy : 0x06433634
Address@app_mtgy : 0x400e3634
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_b14
MWMM operand B register 14
R/W
0x00000000
Address@mtgy : 0x06433638
Address@com_mtgy : 0x06433638
Address@app_mtgy : 0x400e3638
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_b15
MWMM operand B register 15
R/W
0x00000000
Address@mtgy : 0x0643363c
Address@com_mtgy : 0x0643363c
Address@app_mtgy : 0x400e363c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_b16
MWMM operand B register 16
R/W
0x00000000
Address@mtgy : 0x06433640
Address@com_mtgy : 0x06433640
Address@app_mtgy : 0x400e3640
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_b17
MWMM operand B register 17
R/W
0x00000000
Address@mtgy : 0x06433644
Address@com_mtgy : 0x06433644
Address@app_mtgy : 0x400e3644
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_b18
MWMM operand B register 18
R/W
0x00000000
Address@mtgy : 0x06433648
Address@com_mtgy : 0x06433648
Address@app_mtgy : 0x400e3648
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_b19
MWMM operand B register 19
R/W
0x00000000
Address@mtgy : 0x0643364c
Address@com_mtgy : 0x0643364c
Address@app_mtgy : 0x400e364c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_b20
MWMM operand B register 20
R/W
0x00000000
Address@mtgy : 0x06433650
Address@com_mtgy : 0x06433650
Address@app_mtgy : 0x400e3650
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_b21
MWMM operand B register 21
R/W
0x00000000
Address@mtgy : 0x06433654
Address@com_mtgy : 0x06433654
Address@app_mtgy : 0x400e3654
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_b22
MWMM operand B register 22
R/W
0x00000000
Address@mtgy : 0x06433658
Address@com_mtgy : 0x06433658
Address@app_mtgy : 0x400e3658
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_b23
MWMM operand B register 23
R/W
0x00000000
Address@mtgy : 0x0643365c
Address@com_mtgy : 0x0643365c
Address@app_mtgy : 0x400e365c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_b24
MWMM operand B register 24
R/W
0x00000000
Address@mtgy : 0x06433660
Address@com_mtgy : 0x06433660
Address@app_mtgy : 0x400e3660
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_b25
MWMM operand B register 25
R/W
0x00000000
Address@mtgy : 0x06433664
Address@com_mtgy : 0x06433664
Address@app_mtgy : 0x400e3664
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_b26
MWMM operand B register 26
R/W
0x00000000
Address@mtgy : 0x06433668
Address@com_mtgy : 0x06433668
Address@app_mtgy : 0x400e3668
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_b27
MWMM operand B register 27
R/W
0x00000000
Address@mtgy : 0x0643366c
Address@com_mtgy : 0x0643366c
Address@app_mtgy : 0x400e366c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_b28
MWMM operand B register 28
R/W
0x00000000
Address@mtgy : 0x06433670
Address@com_mtgy : 0x06433670
Address@app_mtgy : 0x400e3670
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_b29
MWMM operand B register 29
R/W
0x00000000
Address@mtgy : 0x06433674
Address@com_mtgy : 0x06433674
Address@app_mtgy : 0x400e3674
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_b30
MWMM operand B register 30
R/W
0x00000000
Address@mtgy : 0x06433678
Address@com_mtgy : 0x06433678
Address@app_mtgy : 0x400e3678
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_b31
MWMM operand B register 31
R/W
0x00000000
Address@mtgy : 0x0643367c
Address@com_mtgy : 0x0643367c
Address@app_mtgy : 0x400e367c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_b32
MWMM operand B register 32
R/W
0x00000000
Address@mtgy : 0x06433680
Address@com_mtgy : 0x06433680
Address@app_mtgy : 0x400e3680
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_b33
MWMM operand B register 33
R/W
0x00000000
Address@mtgy : 0x06433684
Address@com_mtgy : 0x06433684
Address@app_mtgy : 0x400e3684
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_b34
MWMM operand B register 34
R/W
0x00000000
Address@mtgy : 0x06433688
Address@com_mtgy : 0x06433688
Address@app_mtgy : 0x400e3688
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_b35
MWMM operand B register 35
R/W
0x00000000
Address@mtgy : 0x0643368c
Address@com_mtgy : 0x0643368c
Address@app_mtgy : 0x400e368c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_b36
MWMM operand B register 36
R/W
0x00000000
Address@mtgy : 0x06433690
Address@com_mtgy : 0x06433690
Address@app_mtgy : 0x400e3690
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_b37
MWMM operand B register 37
R/W
0x00000000
Address@mtgy : 0x06433694
Address@com_mtgy : 0x06433694
Address@app_mtgy : 0x400e3694
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_b38
MWMM operand B register 38
R/W
0x00000000
Address@mtgy : 0x06433698
Address@com_mtgy : 0x06433698
Address@app_mtgy : 0x400e3698
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_b39
MWMM operand B register 39
R/W
0x00000000
Address@mtgy : 0x0643369c
Address@com_mtgy : 0x0643369c
Address@app_mtgy : 0x400e369c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_b40
MWMM operand B register 40
R/W
0x00000000
Address@mtgy : 0x064336a0
Address@com_mtgy : 0x064336a0
Address@app_mtgy : 0x400e36a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_b41
MWMM operand B register 41
R/W
0x00000000
Address@mtgy : 0x064336a4
Address@com_mtgy : 0x064336a4
Address@app_mtgy : 0x400e36a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_b42
MWMM operand B register 42
R/W
0x00000000
Address@mtgy : 0x064336a8
Address@com_mtgy : 0x064336a8
Address@app_mtgy : 0x400e36a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_b43
MWMM operand B register 43
R/W
0x00000000
Address@mtgy : 0x064336ac
Address@com_mtgy : 0x064336ac
Address@app_mtgy : 0x400e36ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_b44
MWMM operand B register 44
R/W
0x00000000
Address@mtgy : 0x064336b0
Address@com_mtgy : 0x064336b0
Address@app_mtgy : 0x400e36b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_b45
MWMM operand B register 45
R/W
0x00000000
Address@mtgy : 0x064336b4
Address@com_mtgy : 0x064336b4
Address@app_mtgy : 0x400e36b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_b46
MWMM operand B register 46
R/W
0x00000000
Address@mtgy : 0x064336b8
Address@com_mtgy : 0x064336b8
Address@app_mtgy : 0x400e36b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_b47
MWMM operand B register 47
R/W
0x00000000
Address@mtgy : 0x064336bc
Address@com_mtgy : 0x064336bc
Address@app_mtgy : 0x400e36bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_b48
MWMM operand B register 48
R/W
0x00000000
Address@mtgy : 0x064336c0
Address@com_mtgy : 0x064336c0
Address@app_mtgy : 0x400e36c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_b49
MWMM operand B register 49
R/W
0x00000000
Address@mtgy : 0x064336c4
Address@com_mtgy : 0x064336c4
Address@app_mtgy : 0x400e36c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_b50
MWMM operand B register 50
R/W
0x00000000
Address@mtgy : 0x064336c8
Address@com_mtgy : 0x064336c8
Address@app_mtgy : 0x400e36c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_b51
MWMM operand B register 51
R/W
0x00000000
Address@mtgy : 0x064336cc
Address@com_mtgy : 0x064336cc
Address@app_mtgy : 0x400e36cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_b52
MWMM operand B register 52
R/W
0x00000000
Address@mtgy : 0x064336d0
Address@com_mtgy : 0x064336d0
Address@app_mtgy : 0x400e36d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_b53
MWMM operand B register 53
R/W
0x00000000
Address@mtgy : 0x064336d4
Address@com_mtgy : 0x064336d4
Address@app_mtgy : 0x400e36d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_b54
MWMM operand B register 54
R/W
0x00000000
Address@mtgy : 0x064336d8
Address@com_mtgy : 0x064336d8
Address@app_mtgy : 0x400e36d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_b55
MWMM operand B register 55
R/W
0x00000000
Address@mtgy : 0x064336dc
Address@com_mtgy : 0x064336dc
Address@app_mtgy : 0x400e36dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_b56
MWMM operand B register 56
R/W
0x00000000
Address@mtgy : 0x064336e0
Address@com_mtgy : 0x064336e0
Address@app_mtgy : 0x400e36e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_b57
MWMM operand B register 57
R/W
0x00000000
Address@mtgy : 0x064336e4
Address@com_mtgy : 0x064336e4
Address@app_mtgy : 0x400e36e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_b58
MWMM operand B register 58
R/W
0x00000000
Address@mtgy : 0x064336e8
Address@com_mtgy : 0x064336e8
Address@app_mtgy : 0x400e36e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_b59
MWMM operand B register 59
R/W
0x00000000
Address@mtgy : 0x064336ec
Address@com_mtgy : 0x064336ec
Address@app_mtgy : 0x400e36ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_b60
MWMM operand B register 60
R/W
0x00000000
Address@mtgy : 0x064336f0
Address@com_mtgy : 0x064336f0
Address@app_mtgy : 0x400e36f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_b61
MWMM operand B register 61
R/W
0x00000000
Address@mtgy : 0x064336f4
Address@com_mtgy : 0x064336f4
Address@app_mtgy : 0x400e36f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_b62
MWMM operand B register 62
R/W
0x00000000
Address@mtgy : 0x064336f8
Address@com_mtgy : 0x064336f8
Address@app_mtgy : 0x400e36f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_b63
MWMM operand B register 63
R/W
0x00000000
Address@mtgy : 0x064336fc
Address@com_mtgy : 0x064336fc
Address@app_mtgy : 0x400e36fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_b64
MWMM operand B register 64
R/W
0x00000000
Address@mtgy : 0x06433700
Address@com_mtgy : 0x06433700
Address@app_mtgy : 0x400e3700
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_b65
MWMM operand B register 65
R/W
0x00000000
Address@mtgy : 0x06433704
Address@com_mtgy : 0x06433704
Address@app_mtgy : 0x400e3704
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_b66
MWMM operand B register 66
R/W
0x00000000
Address@mtgy : 0x06433708
Address@com_mtgy : 0x06433708
Address@app_mtgy : 0x400e3708
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_b67
MWMM operand B register 67
R/W
0x00000000
Address@mtgy : 0x0643370c
Address@com_mtgy : 0x0643370c
Address@app_mtgy : 0x400e370c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_b68
MWMM operand B register 68
R/W
0x00000000
Address@mtgy : 0x06433710
Address@com_mtgy : 0x06433710
Address@app_mtgy : 0x400e3710
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_b69
MWMM operand B register 69
R/W
0x00000000
Address@mtgy : 0x06433714
Address@com_mtgy : 0x06433714
Address@app_mtgy : 0x400e3714
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_b70
MWMM operand B register 70
R/W
0x00000000
Address@mtgy : 0x06433718
Address@com_mtgy : 0x06433718
Address@app_mtgy : 0x400e3718
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_b71
MWMM operand B register 71
R/W
0x00000000
Address@mtgy : 0x0643371c
Address@com_mtgy : 0x0643371c
Address@app_mtgy : 0x400e371c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_b72
MWMM operand B register 72
R/W
0x00000000
Address@mtgy : 0x06433720
Address@com_mtgy : 0x06433720
Address@app_mtgy : 0x400e3720
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_b73
MWMM operand B register 73
R/W
0x00000000
Address@mtgy : 0x06433724
Address@com_mtgy : 0x06433724
Address@app_mtgy : 0x400e3724
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_b74
MWMM operand B register 74
R/W
0x00000000
Address@mtgy : 0x06433728
Address@com_mtgy : 0x06433728
Address@app_mtgy : 0x400e3728
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_b75
MWMM operand B register 75
R/W
0x00000000
Address@mtgy : 0x0643372c
Address@com_mtgy : 0x0643372c
Address@app_mtgy : 0x400e372c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_b76
MWMM operand B register 76
R/W
0x00000000
Address@mtgy : 0x06433730
Address@com_mtgy : 0x06433730
Address@app_mtgy : 0x400e3730
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_b77
MWMM operand B register 77
R/W
0x00000000
Address@mtgy : 0x06433734
Address@com_mtgy : 0x06433734
Address@app_mtgy : 0x400e3734
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_b78
MWMM operand B register 78
R/W
0x00000000
Address@mtgy : 0x06433738
Address@com_mtgy : 0x06433738
Address@app_mtgy : 0x400e3738
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_b79
MWMM operand B register 79
R/W
0x00000000
Address@mtgy : 0x0643373c
Address@com_mtgy : 0x0643373c
Address@app_mtgy : 0x400e373c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_b80
MWMM operand B register 80
R/W
0x00000000
Address@mtgy : 0x06433740
Address@com_mtgy : 0x06433740
Address@app_mtgy : 0x400e3740
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_b81
MWMM operand B register 81
R/W
0x00000000
Address@mtgy : 0x06433744
Address@com_mtgy : 0x06433744
Address@app_mtgy : 0x400e3744
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_b82
MWMM operand B register 82
R/W
0x00000000
Address@mtgy : 0x06433748
Address@com_mtgy : 0x06433748
Address@app_mtgy : 0x400e3748
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_b83
MWMM operand B register 83
R/W
0x00000000
Address@mtgy : 0x0643374c
Address@com_mtgy : 0x0643374c
Address@app_mtgy : 0x400e374c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_b84
MWMM operand B register 84
R/W
0x00000000
Address@mtgy : 0x06433750
Address@com_mtgy : 0x06433750
Address@app_mtgy : 0x400e3750
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_b85
MWMM operand B register 85
R/W
0x00000000
Address@mtgy : 0x06433754
Address@com_mtgy : 0x06433754
Address@app_mtgy : 0x400e3754
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_b86
MWMM operand B register 86
R/W
0x00000000
Address@mtgy : 0x06433758
Address@com_mtgy : 0x06433758
Address@app_mtgy : 0x400e3758
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_b87
MWMM operand B register 87
R/W
0x00000000
Address@mtgy : 0x0643375c
Address@com_mtgy : 0x0643375c
Address@app_mtgy : 0x400e375c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_b88
MWMM operand B register 88
R/W
0x00000000
Address@mtgy : 0x06433760
Address@com_mtgy : 0x06433760
Address@app_mtgy : 0x400e3760
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_b89
MWMM operand B register 89
R/W
0x00000000
Address@mtgy : 0x06433764
Address@com_mtgy : 0x06433764
Address@app_mtgy : 0x400e3764
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_b90
MWMM operand B register 90
R/W
0x00000000
Address@mtgy : 0x06433768
Address@com_mtgy : 0x06433768
Address@app_mtgy : 0x400e3768
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_b91
MWMM operand B register 91
R/W
0x00000000
Address@mtgy : 0x0643376c
Address@com_mtgy : 0x0643376c
Address@app_mtgy : 0x400e376c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_b92
MWMM operand B register 92
R/W
0x00000000
Address@mtgy : 0x06433770
Address@com_mtgy : 0x06433770
Address@app_mtgy : 0x400e3770
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_b93
MWMM operand B register 93
R/W
0x00000000
Address@mtgy : 0x06433774
Address@com_mtgy : 0x06433774
Address@app_mtgy : 0x400e3774
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_b94
MWMM operand B register 94
R/W
0x00000000
Address@mtgy : 0x06433778
Address@com_mtgy : 0x06433778
Address@app_mtgy : 0x400e3778
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_b95
MWMM operand B register 95
R/W
0x00000000
Address@mtgy : 0x0643377c
Address@com_mtgy : 0x0643377c
Address@app_mtgy : 0x400e377c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_b96
MWMM operand B register 96
R/W
0x00000000
Address@mtgy : 0x06433780
Address@com_mtgy : 0x06433780
Address@app_mtgy : 0x400e3780
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_b97
MWMM operand B register 97
R/W
0x00000000
Address@mtgy : 0x06433784
Address@com_mtgy : 0x06433784
Address@app_mtgy : 0x400e3784
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_b98
MWMM operand B register 98
R/W
0x00000000
Address@mtgy : 0x06433788
Address@com_mtgy : 0x06433788
Address@app_mtgy : 0x400e3788
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_b99
MWMM operand B register 99
R/W
0x00000000
Address@mtgy : 0x0643378c
Address@com_mtgy : 0x0643378c
Address@app_mtgy : 0x400e378c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_b100
MWMM operand B register 100
R/W
0x00000000
Address@mtgy : 0x06433790
Address@com_mtgy : 0x06433790
Address@app_mtgy : 0x400e3790
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_b101
MWMM operand B register 101
R/W
0x00000000
Address@mtgy : 0x06433794
Address@com_mtgy : 0x06433794
Address@app_mtgy : 0x400e3794
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_b102
MWMM operand B register 102
R/W
0x00000000
Address@mtgy : 0x06433798
Address@com_mtgy : 0x06433798
Address@app_mtgy : 0x400e3798
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_b103
MWMM operand B register 103
R/W
0x00000000
Address@mtgy : 0x0643379c
Address@com_mtgy : 0x0643379c
Address@app_mtgy : 0x400e379c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_b104
MWMM operand B register 104
R/W
0x00000000
Address@mtgy : 0x064337a0
Address@com_mtgy : 0x064337a0
Address@app_mtgy : 0x400e37a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_b105
MWMM operand B register 105
R/W
0x00000000
Address@mtgy : 0x064337a4
Address@com_mtgy : 0x064337a4
Address@app_mtgy : 0x400e37a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_b106
MWMM operand B register 106
R/W
0x00000000
Address@mtgy : 0x064337a8
Address@com_mtgy : 0x064337a8
Address@app_mtgy : 0x400e37a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_b107
MWMM operand B register 107
R/W
0x00000000
Address@mtgy : 0x064337ac
Address@com_mtgy : 0x064337ac
Address@app_mtgy : 0x400e37ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_b108
MWMM operand B register 108
R/W
0x00000000
Address@mtgy : 0x064337b0
Address@com_mtgy : 0x064337b0
Address@app_mtgy : 0x400e37b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_b109
MWMM operand B register 109
R/W
0x00000000
Address@mtgy : 0x064337b4
Address@com_mtgy : 0x064337b4
Address@app_mtgy : 0x400e37b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_b110
MWMM operand B register 110
R/W
0x00000000
Address@mtgy : 0x064337b8
Address@com_mtgy : 0x064337b8
Address@app_mtgy : 0x400e37b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_b111
MWMM operand B register 111
R/W
0x00000000
Address@mtgy : 0x064337bc
Address@com_mtgy : 0x064337bc
Address@app_mtgy : 0x400e37bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_b112
MWMM operand B register 112
R/W
0x00000000
Address@mtgy : 0x064337c0
Address@com_mtgy : 0x064337c0
Address@app_mtgy : 0x400e37c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_b113
MWMM operand B register 113
R/W
0x00000000
Address@mtgy : 0x064337c4
Address@com_mtgy : 0x064337c4
Address@app_mtgy : 0x400e37c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_b114
MWMM operand B register 114
R/W
0x00000000
Address@mtgy : 0x064337c8
Address@com_mtgy : 0x064337c8
Address@app_mtgy : 0x400e37c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_b115
MWMM operand B register 115
R/W
0x00000000
Address@mtgy : 0x064337cc
Address@com_mtgy : 0x064337cc
Address@app_mtgy : 0x400e37cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_b116
MWMM operand B register 116
R/W
0x00000000
Address@mtgy : 0x064337d0
Address@com_mtgy : 0x064337d0
Address@app_mtgy : 0x400e37d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_b117
MWMM operand B register 117
R/W
0x00000000
Address@mtgy : 0x064337d4
Address@com_mtgy : 0x064337d4
Address@app_mtgy : 0x400e37d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_b118
MWMM operand B register 118
R/W
0x00000000
Address@mtgy : 0x064337d8
Address@com_mtgy : 0x064337d8
Address@app_mtgy : 0x400e37d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_b119
MWMM operand B register 119
R/W
0x00000000
Address@mtgy : 0x064337dc
Address@com_mtgy : 0x064337dc
Address@app_mtgy : 0x400e37dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_b120
MWMM operand B register 120
R/W
0x00000000
Address@mtgy : 0x064337e0
Address@com_mtgy : 0x064337e0
Address@app_mtgy : 0x400e37e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_b121
MWMM operand B register 121
R/W
0x00000000
Address@mtgy : 0x064337e4
Address@com_mtgy : 0x064337e4
Address@app_mtgy : 0x400e37e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_b122
MWMM operand B register 122
R/W
0x00000000
Address@mtgy : 0x064337e8
Address@com_mtgy : 0x064337e8
Address@app_mtgy : 0x400e37e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_b123
MWMM operand B register 123
R/W
0x00000000
Address@mtgy : 0x064337ec
Address@com_mtgy : 0x064337ec
Address@app_mtgy : 0x400e37ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_b124
MWMM operand B register 124
R/W
0x00000000
Address@mtgy : 0x064337f0
Address@com_mtgy : 0x064337f0
Address@app_mtgy : 0x400e37f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_b125
MWMM operand B register 125
R/W
0x00000000
Address@mtgy : 0x064337f4
Address@com_mtgy : 0x064337f4
Address@app_mtgy : 0x400e37f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_b126
MWMM operand B register 126
R/W
0x00000000
Address@mtgy : 0x064337f8
Address@com_mtgy : 0x064337f8
Address@app_mtgy : 0x400e37f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_b127
MWMM operand B register 127
R/W
0x00000000
Address@mtgy : 0x064337fc
Address@com_mtgy : 0x064337fc
Address@app_mtgy : 0x400e37fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_a0
MWMM operand A register 0
R/W
0x00000000
Address@mtgy : 0x06433800
Address@com_mtgy : 0x06433800
Address@app_mtgy : 0x400e3800
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_a1
MWMM operand A register 1
R/W
0x00000000
Address@mtgy : 0x06433804
Address@com_mtgy : 0x06433804
Address@app_mtgy : 0x400e3804
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_a2
MWMM operand A register 2
R/W
0x00000000
Address@mtgy : 0x06433808
Address@com_mtgy : 0x06433808
Address@app_mtgy : 0x400e3808
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_a3
MWMM operand A register 3
R/W
0x00000000
Address@mtgy : 0x0643380c
Address@com_mtgy : 0x0643380c
Address@app_mtgy : 0x400e380c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_a4
MWMM operand A register 4
R/W
0x00000000
Address@mtgy : 0x06433810
Address@com_mtgy : 0x06433810
Address@app_mtgy : 0x400e3810
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_a5
MWMM operand A register 5
R/W
0x00000000
Address@mtgy : 0x06433814
Address@com_mtgy : 0x06433814
Address@app_mtgy : 0x400e3814
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_a6
MWMM operand A register 6
R/W
0x00000000
Address@mtgy : 0x06433818
Address@com_mtgy : 0x06433818
Address@app_mtgy : 0x400e3818
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_a7
MWMM operand A register 7
R/W
0x00000000
Address@mtgy : 0x0643381c
Address@com_mtgy : 0x0643381c
Address@app_mtgy : 0x400e381c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_a8
MWMM operand A register 8
R/W
0x00000000
Address@mtgy : 0x06433820
Address@com_mtgy : 0x06433820
Address@app_mtgy : 0x400e3820
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_a9
MWMM operand A register 9
R/W
0x00000000
Address@mtgy : 0x06433824
Address@com_mtgy : 0x06433824
Address@app_mtgy : 0x400e3824
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_a10
MWMM operand A register 10
R/W
0x00000000
Address@mtgy : 0x06433828
Address@com_mtgy : 0x06433828
Address@app_mtgy : 0x400e3828
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_a11
MWMM operand A register 11
R/W
0x00000000
Address@mtgy : 0x0643382c
Address@com_mtgy : 0x0643382c
Address@app_mtgy : 0x400e382c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_a12
MWMM operand A register 12
R/W
0x00000000
Address@mtgy : 0x06433830
Address@com_mtgy : 0x06433830
Address@app_mtgy : 0x400e3830
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_a13
MWMM operand A register 13
R/W
0x00000000
Address@mtgy : 0x06433834
Address@com_mtgy : 0x06433834
Address@app_mtgy : 0x400e3834
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_a14
MWMM operand A register 14
R/W
0x00000000
Address@mtgy : 0x06433838
Address@com_mtgy : 0x06433838
Address@app_mtgy : 0x400e3838
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_a15
MWMM operand A register 15
R/W
0x00000000
Address@mtgy : 0x0643383c
Address@com_mtgy : 0x0643383c
Address@app_mtgy : 0x400e383c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_a16
MWMM operand A register 16
R/W
0x00000000
Address@mtgy : 0x06433840
Address@com_mtgy : 0x06433840
Address@app_mtgy : 0x400e3840
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_a17
MWMM operand A register 17
R/W
0x00000000
Address@mtgy : 0x06433844
Address@com_mtgy : 0x06433844
Address@app_mtgy : 0x400e3844
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_a18
MWMM operand A register 18
R/W
0x00000000
Address@mtgy : 0x06433848
Address@com_mtgy : 0x06433848
Address@app_mtgy : 0x400e3848
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_a19
MWMM operand A register 19
R/W
0x00000000
Address@mtgy : 0x0643384c
Address@com_mtgy : 0x0643384c
Address@app_mtgy : 0x400e384c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_a20
MWMM operand A register 20
R/W
0x00000000
Address@mtgy : 0x06433850
Address@com_mtgy : 0x06433850
Address@app_mtgy : 0x400e3850
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_a21
MWMM operand A register 21
R/W
0x00000000
Address@mtgy : 0x06433854
Address@com_mtgy : 0x06433854
Address@app_mtgy : 0x400e3854
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_a22
MWMM operand A register 22
R/W
0x00000000
Address@mtgy : 0x06433858
Address@com_mtgy : 0x06433858
Address@app_mtgy : 0x400e3858
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_a23
MWMM operand A register 23
R/W
0x00000000
Address@mtgy : 0x0643385c
Address@com_mtgy : 0x0643385c
Address@app_mtgy : 0x400e385c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_a24
MWMM operand A register 24
R/W
0x00000000
Address@mtgy : 0x06433860
Address@com_mtgy : 0x06433860
Address@app_mtgy : 0x400e3860
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_a25
MWMM operand A register 25
R/W
0x00000000
Address@mtgy : 0x06433864
Address@com_mtgy : 0x06433864
Address@app_mtgy : 0x400e3864
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_a26
MWMM operand A register 26
R/W
0x00000000
Address@mtgy : 0x06433868
Address@com_mtgy : 0x06433868
Address@app_mtgy : 0x400e3868
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_a27
MWMM operand A register 27
R/W
0x00000000
Address@mtgy : 0x0643386c
Address@com_mtgy : 0x0643386c
Address@app_mtgy : 0x400e386c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_a28
MWMM operand A register 28
R/W
0x00000000
Address@mtgy : 0x06433870
Address@com_mtgy : 0x06433870
Address@app_mtgy : 0x400e3870
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_a29
MWMM operand A register 29
R/W
0x00000000
Address@mtgy : 0x06433874
Address@com_mtgy : 0x06433874
Address@app_mtgy : 0x400e3874
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_a30
MWMM operand A register 30
R/W
0x00000000
Address@mtgy : 0x06433878
Address@com_mtgy : 0x06433878
Address@app_mtgy : 0x400e3878
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_a31
MWMM operand A register 31
R/W
0x00000000
Address@mtgy : 0x0643387c
Address@com_mtgy : 0x0643387c
Address@app_mtgy : 0x400e387c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_a32
MWMM operand A register 32
R/W
0x00000000
Address@mtgy : 0x06433880
Address@com_mtgy : 0x06433880
Address@app_mtgy : 0x400e3880
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_a33
MWMM operand A register 33
R/W
0x00000000
Address@mtgy : 0x06433884
Address@com_mtgy : 0x06433884
Address@app_mtgy : 0x400e3884
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_a34
MWMM operand A register 34
R/W
0x00000000
Address@mtgy : 0x06433888
Address@com_mtgy : 0x06433888
Address@app_mtgy : 0x400e3888
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_a35
MWMM operand A register 35
R/W
0x00000000
Address@mtgy : 0x0643388c
Address@com_mtgy : 0x0643388c
Address@app_mtgy : 0x400e388c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_a36
MWMM operand A register 36
R/W
0x00000000
Address@mtgy : 0x06433890
Address@com_mtgy : 0x06433890
Address@app_mtgy : 0x400e3890
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_a37
MWMM operand A register 37
R/W
0x00000000
Address@mtgy : 0x06433894
Address@com_mtgy : 0x06433894
Address@app_mtgy : 0x400e3894
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_a38
MWMM operand A register 38
R/W
0x00000000
Address@mtgy : 0x06433898
Address@com_mtgy : 0x06433898
Address@app_mtgy : 0x400e3898
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_a39
MWMM operand A register 39
R/W
0x00000000
Address@mtgy : 0x0643389c
Address@com_mtgy : 0x0643389c
Address@app_mtgy : 0x400e389c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_a40
MWMM operand A register 40
R/W
0x00000000
Address@mtgy : 0x064338a0
Address@com_mtgy : 0x064338a0
Address@app_mtgy : 0x400e38a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_a41
MWMM operand A register 41
R/W
0x00000000
Address@mtgy : 0x064338a4
Address@com_mtgy : 0x064338a4
Address@app_mtgy : 0x400e38a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_a42
MWMM operand A register 42
R/W
0x00000000
Address@mtgy : 0x064338a8
Address@com_mtgy : 0x064338a8
Address@app_mtgy : 0x400e38a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_a43
MWMM operand A register 43
R/W
0x00000000
Address@mtgy : 0x064338ac
Address@com_mtgy : 0x064338ac
Address@app_mtgy : 0x400e38ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_a44
MWMM operand A register 44
R/W
0x00000000
Address@mtgy : 0x064338b0
Address@com_mtgy : 0x064338b0
Address@app_mtgy : 0x400e38b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_a45
MWMM operand A register 45
R/W
0x00000000
Address@mtgy : 0x064338b4
Address@com_mtgy : 0x064338b4
Address@app_mtgy : 0x400e38b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_a46
MWMM operand A register 46
R/W
0x00000000
Address@mtgy : 0x064338b8
Address@com_mtgy : 0x064338b8
Address@app_mtgy : 0x400e38b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_a47
MWMM operand A register 47
R/W
0x00000000
Address@mtgy : 0x064338bc
Address@com_mtgy : 0x064338bc
Address@app_mtgy : 0x400e38bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_a48
MWMM operand A register 48
R/W
0x00000000
Address@mtgy : 0x064338c0
Address@com_mtgy : 0x064338c0
Address@app_mtgy : 0x400e38c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_a49
MWMM operand A register 49
R/W
0x00000000
Address@mtgy : 0x064338c4
Address@com_mtgy : 0x064338c4
Address@app_mtgy : 0x400e38c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_a50
MWMM operand A register 50
R/W
0x00000000
Address@mtgy : 0x064338c8
Address@com_mtgy : 0x064338c8
Address@app_mtgy : 0x400e38c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_a51
MWMM operand A register 51
R/W
0x00000000
Address@mtgy : 0x064338cc
Address@com_mtgy : 0x064338cc
Address@app_mtgy : 0x400e38cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_a52
MWMM operand A register 52
R/W
0x00000000
Address@mtgy : 0x064338d0
Address@com_mtgy : 0x064338d0
Address@app_mtgy : 0x400e38d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_a53
MWMM operand A register 53
R/W
0x00000000
Address@mtgy : 0x064338d4
Address@com_mtgy : 0x064338d4
Address@app_mtgy : 0x400e38d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_a54
MWMM operand A register 54
R/W
0x00000000
Address@mtgy : 0x064338d8
Address@com_mtgy : 0x064338d8
Address@app_mtgy : 0x400e38d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_a55
MWMM operand A register 55
R/W
0x00000000
Address@mtgy : 0x064338dc
Address@com_mtgy : 0x064338dc
Address@app_mtgy : 0x400e38dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_a56
MWMM operand A register 56
R/W
0x00000000
Address@mtgy : 0x064338e0
Address@com_mtgy : 0x064338e0
Address@app_mtgy : 0x400e38e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_a57
MWMM operand A register 57
R/W
0x00000000
Address@mtgy : 0x064338e4
Address@com_mtgy : 0x064338e4
Address@app_mtgy : 0x400e38e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_a58
MWMM operand A register 58
R/W
0x00000000
Address@mtgy : 0x064338e8
Address@com_mtgy : 0x064338e8
Address@app_mtgy : 0x400e38e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_a59
MWMM operand A register 59
R/W
0x00000000
Address@mtgy : 0x064338ec
Address@com_mtgy : 0x064338ec
Address@app_mtgy : 0x400e38ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_a60
MWMM operand A register 60
R/W
0x00000000
Address@mtgy : 0x064338f0
Address@com_mtgy : 0x064338f0
Address@app_mtgy : 0x400e38f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_a61
MWMM operand A register 61
R/W
0x00000000
Address@mtgy : 0x064338f4
Address@com_mtgy : 0x064338f4
Address@app_mtgy : 0x400e38f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_a62
MWMM operand A register 62
R/W
0x00000000
Address@mtgy : 0x064338f8
Address@com_mtgy : 0x064338f8
Address@app_mtgy : 0x400e38f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_a63
MWMM operand A register 63
R/W
0x00000000
Address@mtgy : 0x064338fc
Address@com_mtgy : 0x064338fc
Address@app_mtgy : 0x400e38fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_a64
MWMM operand A register 64
R/W
0x00000000
Address@mtgy : 0x06433900
Address@com_mtgy : 0x06433900
Address@app_mtgy : 0x400e3900
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_a65
MWMM operand A register 65
R/W
0x00000000
Address@mtgy : 0x06433904
Address@com_mtgy : 0x06433904
Address@app_mtgy : 0x400e3904
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_a66
MWMM operand A register 66
R/W
0x00000000
Address@mtgy : 0x06433908
Address@com_mtgy : 0x06433908
Address@app_mtgy : 0x400e3908
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_a67
MWMM operand A register 67
R/W
0x00000000
Address@mtgy : 0x0643390c
Address@com_mtgy : 0x0643390c
Address@app_mtgy : 0x400e390c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_a68
MWMM operand A register 68
R/W
0x00000000
Address@mtgy : 0x06433910
Address@com_mtgy : 0x06433910
Address@app_mtgy : 0x400e3910
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_a69
MWMM operand A register 69
R/W
0x00000000
Address@mtgy : 0x06433914
Address@com_mtgy : 0x06433914
Address@app_mtgy : 0x400e3914
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_a70
MWMM operand A register 70
R/W
0x00000000
Address@mtgy : 0x06433918
Address@com_mtgy : 0x06433918
Address@app_mtgy : 0x400e3918
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_a71
MWMM operand A register 71
R/W
0x00000000
Address@mtgy : 0x0643391c
Address@com_mtgy : 0x0643391c
Address@app_mtgy : 0x400e391c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_a72
MWMM operand A register 72
R/W
0x00000000
Address@mtgy : 0x06433920
Address@com_mtgy : 0x06433920
Address@app_mtgy : 0x400e3920
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_a73
MWMM operand A register 73
R/W
0x00000000
Address@mtgy : 0x06433924
Address@com_mtgy : 0x06433924
Address@app_mtgy : 0x400e3924
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_a74
MWMM operand A register 74
R/W
0x00000000
Address@mtgy : 0x06433928
Address@com_mtgy : 0x06433928
Address@app_mtgy : 0x400e3928
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_a75
MWMM operand A register 75
R/W
0x00000000
Address@mtgy : 0x0643392c
Address@com_mtgy : 0x0643392c
Address@app_mtgy : 0x400e392c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_a76
MWMM operand A register 76
R/W
0x00000000
Address@mtgy : 0x06433930
Address@com_mtgy : 0x06433930
Address@app_mtgy : 0x400e3930
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_a77
MWMM operand A register 77
R/W
0x00000000
Address@mtgy : 0x06433934
Address@com_mtgy : 0x06433934
Address@app_mtgy : 0x400e3934
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_a78
MWMM operand A register 78
R/W
0x00000000
Address@mtgy : 0x06433938
Address@com_mtgy : 0x06433938
Address@app_mtgy : 0x400e3938
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_a79
MWMM operand A register 79
R/W
0x00000000
Address@mtgy : 0x0643393c
Address@com_mtgy : 0x0643393c
Address@app_mtgy : 0x400e393c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_a80
MWMM operand A register 80
R/W
0x00000000
Address@mtgy : 0x06433940
Address@com_mtgy : 0x06433940
Address@app_mtgy : 0x400e3940
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_a81
MWMM operand A register 81
R/W
0x00000000
Address@mtgy : 0x06433944
Address@com_mtgy : 0x06433944
Address@app_mtgy : 0x400e3944
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_a82
MWMM operand A register 82
R/W
0x00000000
Address@mtgy : 0x06433948
Address@com_mtgy : 0x06433948
Address@app_mtgy : 0x400e3948
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_a83
MWMM operand A register 83
R/W
0x00000000
Address@mtgy : 0x0643394c
Address@com_mtgy : 0x0643394c
Address@app_mtgy : 0x400e394c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_a84
MWMM operand A register 84
R/W
0x00000000
Address@mtgy : 0x06433950
Address@com_mtgy : 0x06433950
Address@app_mtgy : 0x400e3950
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_a85
MWMM operand A register 85
R/W
0x00000000
Address@mtgy : 0x06433954
Address@com_mtgy : 0x06433954
Address@app_mtgy : 0x400e3954
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_a86
MWMM operand A register 86
R/W
0x00000000
Address@mtgy : 0x06433958
Address@com_mtgy : 0x06433958
Address@app_mtgy : 0x400e3958
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_a87
MWMM operand A register 87
R/W
0x00000000
Address@mtgy : 0x0643395c
Address@com_mtgy : 0x0643395c
Address@app_mtgy : 0x400e395c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_a88
MWMM operand A register 88
R/W
0x00000000
Address@mtgy : 0x06433960
Address@com_mtgy : 0x06433960
Address@app_mtgy : 0x400e3960
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_a89
MWMM operand A register 89
R/W
0x00000000
Address@mtgy : 0x06433964
Address@com_mtgy : 0x06433964
Address@app_mtgy : 0x400e3964
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_a90
MWMM operand A register 90
R/W
0x00000000
Address@mtgy : 0x06433968
Address@com_mtgy : 0x06433968
Address@app_mtgy : 0x400e3968
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_a91
MWMM operand A register 91
R/W
0x00000000
Address@mtgy : 0x0643396c
Address@com_mtgy : 0x0643396c
Address@app_mtgy : 0x400e396c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_a92
MWMM operand A register 92
R/W
0x00000000
Address@mtgy : 0x06433970
Address@com_mtgy : 0x06433970
Address@app_mtgy : 0x400e3970
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_a93
MWMM operand A register 93
R/W
0x00000000
Address@mtgy : 0x06433974
Address@com_mtgy : 0x06433974
Address@app_mtgy : 0x400e3974
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_a94
MWMM operand A register 94
R/W
0x00000000
Address@mtgy : 0x06433978
Address@com_mtgy : 0x06433978
Address@app_mtgy : 0x400e3978
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_a95
MWMM operand A register 95
R/W
0x00000000
Address@mtgy : 0x0643397c
Address@com_mtgy : 0x0643397c
Address@app_mtgy : 0x400e397c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_a96
MWMM operand A register 96
R/W
0x00000000
Address@mtgy : 0x06433980
Address@com_mtgy : 0x06433980
Address@app_mtgy : 0x400e3980
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_a97
MWMM operand A register 97
R/W
0x00000000
Address@mtgy : 0x06433984
Address@com_mtgy : 0x06433984
Address@app_mtgy : 0x400e3984
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_a98
MWMM operand A register 98
R/W
0x00000000
Address@mtgy : 0x06433988
Address@com_mtgy : 0x06433988
Address@app_mtgy : 0x400e3988
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_a99
MWMM operand A register 99
R/W
0x00000000
Address@mtgy : 0x0643398c
Address@com_mtgy : 0x0643398c
Address@app_mtgy : 0x400e398c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_a100
MWMM operand A register 100
R/W
0x00000000
Address@mtgy : 0x06433990
Address@com_mtgy : 0x06433990
Address@app_mtgy : 0x400e3990
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_a101
MWMM operand A register 101
R/W
0x00000000
Address@mtgy : 0x06433994
Address@com_mtgy : 0x06433994
Address@app_mtgy : 0x400e3994
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_a102
MWMM operand A register 102
R/W
0x00000000
Address@mtgy : 0x06433998
Address@com_mtgy : 0x06433998
Address@app_mtgy : 0x400e3998
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_a103
MWMM operand A register 103
R/W
0x00000000
Address@mtgy : 0x0643399c
Address@com_mtgy : 0x0643399c
Address@app_mtgy : 0x400e399c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_a104
MWMM operand A register 104
R/W
0x00000000
Address@mtgy : 0x064339a0
Address@com_mtgy : 0x064339a0
Address@app_mtgy : 0x400e39a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_a105
MWMM operand A register 105
R/W
0x00000000
Address@mtgy : 0x064339a4
Address@com_mtgy : 0x064339a4
Address@app_mtgy : 0x400e39a4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_a106
MWMM operand A register 106
R/W
0x00000000
Address@mtgy : 0x064339a8
Address@com_mtgy : 0x064339a8
Address@app_mtgy : 0x400e39a8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_a107
MWMM operand A register 107
R/W
0x00000000
Address@mtgy : 0x064339ac
Address@com_mtgy : 0x064339ac
Address@app_mtgy : 0x400e39ac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_a108
MWMM operand A register 108
R/W
0x00000000
Address@mtgy : 0x064339b0
Address@com_mtgy : 0x064339b0
Address@app_mtgy : 0x400e39b0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_a109
MWMM operand A register 109
R/W
0x00000000
Address@mtgy : 0x064339b4
Address@com_mtgy : 0x064339b4
Address@app_mtgy : 0x400e39b4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_a110
MWMM operand A register 110
R/W
0x00000000
Address@mtgy : 0x064339b8
Address@com_mtgy : 0x064339b8
Address@app_mtgy : 0x400e39b8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_a111
MWMM operand A register 111
R/W
0x00000000
Address@mtgy : 0x064339bc
Address@com_mtgy : 0x064339bc
Address@app_mtgy : 0x400e39bc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_a112
MWMM operand A register 112
R/W
0x00000000
Address@mtgy : 0x064339c0
Address@com_mtgy : 0x064339c0
Address@app_mtgy : 0x400e39c0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_a113
MWMM operand A register 113
R/W
0x00000000
Address@mtgy : 0x064339c4
Address@com_mtgy : 0x064339c4
Address@app_mtgy : 0x400e39c4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_a114
MWMM operand A register 114
R/W
0x00000000
Address@mtgy : 0x064339c8
Address@com_mtgy : 0x064339c8
Address@app_mtgy : 0x400e39c8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_a115
MWMM operand A register 115
R/W
0x00000000
Address@mtgy : 0x064339cc
Address@com_mtgy : 0x064339cc
Address@app_mtgy : 0x400e39cc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_a116
MWMM operand A register 116
R/W
0x00000000
Address@mtgy : 0x064339d0
Address@com_mtgy : 0x064339d0
Address@app_mtgy : 0x400e39d0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_a117
MWMM operand A register 117
R/W
0x00000000
Address@mtgy : 0x064339d4
Address@com_mtgy : 0x064339d4
Address@app_mtgy : 0x400e39d4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_a118
MWMM operand A register 118
R/W
0x00000000
Address@mtgy : 0x064339d8
Address@com_mtgy : 0x064339d8
Address@app_mtgy : 0x400e39d8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_a119
MWMM operand A register 119
R/W
0x00000000
Address@mtgy : 0x064339dc
Address@com_mtgy : 0x064339dc
Address@app_mtgy : 0x400e39dc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_a120
MWMM operand A register 120
R/W
0x00000000
Address@mtgy : 0x064339e0
Address@com_mtgy : 0x064339e0
Address@app_mtgy : 0x400e39e0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_a121
MWMM operand A register 121
R/W
0x00000000
Address@mtgy : 0x064339e4
Address@com_mtgy : 0x064339e4
Address@app_mtgy : 0x400e39e4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_a122
MWMM operand A register 122
R/W
0x00000000
Address@mtgy : 0x064339e8
Address@com_mtgy : 0x064339e8
Address@app_mtgy : 0x400e39e8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_a123
MWMM operand A register 123
R/W
0x00000000
Address@mtgy : 0x064339ec
Address@com_mtgy : 0x064339ec
Address@app_mtgy : 0x400e39ec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_a124
MWMM operand A register 124
R/W
0x00000000
Address@mtgy : 0x064339f0
Address@com_mtgy : 0x064339f0
Address@app_mtgy : 0x400e39f0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_a125
MWMM operand A register 125
R/W
0x00000000
Address@mtgy : 0x064339f4
Address@com_mtgy : 0x064339f4
Address@app_mtgy : 0x400e39f4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_a126
MWMM operand A register 126
R/W
0x00000000
Address@mtgy : 0x064339f8
Address@com_mtgy : 0x064339f8
Address@app_mtgy : 0x400e39f8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_a127
MWMM operand A register 127
R/W
0x00000000
Address@mtgy : 0x064339fc
Address@com_mtgy : 0x064339fc
Address@app_mtgy : 0x400e39fc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_e0
MWMM operand E register 0
R/W
0x00000000
Address@mtgy : 0x06433a00
Address@com_mtgy : 0x06433a00
Address@app_mtgy : 0x400e3a00
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_e1
MWMM operand E register 1
R/W
0x00000000
Address@mtgy : 0x06433a04
Address@com_mtgy : 0x06433a04
Address@app_mtgy : 0x400e3a04
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_e2
MWMM operand E register 2
R/W
0x00000000
Address@mtgy : 0x06433a08
Address@com_mtgy : 0x06433a08
Address@app_mtgy : 0x400e3a08
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_e3
MWMM operand E register 3
R/W
0x00000000
Address@mtgy : 0x06433a0c
Address@com_mtgy : 0x06433a0c
Address@app_mtgy : 0x400e3a0c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_e4
MWMM operand E register 4
R/W
0x00000000
Address@mtgy : 0x06433a10
Address@com_mtgy : 0x06433a10
Address@app_mtgy : 0x400e3a10
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_e5
MWMM operand E register 5
R/W
0x00000000
Address@mtgy : 0x06433a14
Address@com_mtgy : 0x06433a14
Address@app_mtgy : 0x400e3a14
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_e6
MWMM operand E register 6
R/W
0x00000000
Address@mtgy : 0x06433a18
Address@com_mtgy : 0x06433a18
Address@app_mtgy : 0x400e3a18
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_e7
MWMM operand E register 7
R/W
0x00000000
Address@mtgy : 0x06433a1c
Address@com_mtgy : 0x06433a1c
Address@app_mtgy : 0x400e3a1c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_e8
MWMM operand E register 8
R/W
0x00000000
Address@mtgy : 0x06433a20
Address@com_mtgy : 0x06433a20
Address@app_mtgy : 0x400e3a20
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_e9
MWMM operand E register 9
R/W
0x00000000
Address@mtgy : 0x06433a24
Address@com_mtgy : 0x06433a24
Address@app_mtgy : 0x400e3a24
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_e10
MWMM operand E register 10
R/W
0x00000000
Address@mtgy : 0x06433a28
Address@com_mtgy : 0x06433a28
Address@app_mtgy : 0x400e3a28
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_e11
MWMM operand E register 11
R/W
0x00000000
Address@mtgy : 0x06433a2c
Address@com_mtgy : 0x06433a2c
Address@app_mtgy : 0x400e3a2c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_e12
MWMM operand E register 12
R/W
0x00000000
Address@mtgy : 0x06433a30
Address@com_mtgy : 0x06433a30
Address@app_mtgy : 0x400e3a30
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_e13
MWMM operand E register 13
R/W
0x00000000
Address@mtgy : 0x06433a34
Address@com_mtgy : 0x06433a34
Address@app_mtgy : 0x400e3a34
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_e14
MWMM operand E register 14
R/W
0x00000000
Address@mtgy : 0x06433a38
Address@com_mtgy : 0x06433a38
Address@app_mtgy : 0x400e3a38
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_e15
MWMM operand E register 15
R/W
0x00000000
Address@mtgy : 0x06433a3c
Address@com_mtgy : 0x06433a3c
Address@app_mtgy : 0x400e3a3c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_e16
MWMM operand E register 16
R/W
0x00000000
Address@mtgy : 0x06433a40
Address@com_mtgy : 0x06433a40
Address@app_mtgy : 0x400e3a40
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_e17
MWMM operand E register 17
R/W
0x00000000
Address@mtgy : 0x06433a44
Address@com_mtgy : 0x06433a44
Address@app_mtgy : 0x400e3a44
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_e18
MWMM operand E register 18
R/W
0x00000000
Address@mtgy : 0x06433a48
Address@com_mtgy : 0x06433a48
Address@app_mtgy : 0x400e3a48
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_e19
MWMM operand E register 19
R/W
0x00000000
Address@mtgy : 0x06433a4c
Address@com_mtgy : 0x06433a4c
Address@app_mtgy : 0x400e3a4c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_e20
MWMM operand E register 20
R/W
0x00000000
Address@mtgy : 0x06433a50
Address@com_mtgy : 0x06433a50
Address@app_mtgy : 0x400e3a50
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_e21
MWMM operand E register 21
R/W
0x00000000
Address@mtgy : 0x06433a54
Address@com_mtgy : 0x06433a54
Address@app_mtgy : 0x400e3a54
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_e22
MWMM operand E register 22
R/W
0x00000000
Address@mtgy : 0x06433a58
Address@com_mtgy : 0x06433a58
Address@app_mtgy : 0x400e3a58
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_e23
MWMM operand E register 23
R/W
0x00000000
Address@mtgy : 0x06433a5c
Address@com_mtgy : 0x06433a5c
Address@app_mtgy : 0x400e3a5c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_e24
MWMM operand E register 24
R/W
0x00000000
Address@mtgy : 0x06433a60
Address@com_mtgy : 0x06433a60
Address@app_mtgy : 0x400e3a60
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_e25
MWMM operand E register 25
R/W
0x00000000
Address@mtgy : 0x06433a64
Address@com_mtgy : 0x06433a64
Address@app_mtgy : 0x400e3a64
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_e26
MWMM operand E register 26
R/W
0x00000000
Address@mtgy : 0x06433a68
Address@com_mtgy : 0x06433a68
Address@app_mtgy : 0x400e3a68
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_e27
MWMM operand E register 27
R/W
0x00000000
Address@mtgy : 0x06433a6c
Address@com_mtgy : 0x06433a6c
Address@app_mtgy : 0x400e3a6c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_e28
MWMM operand E register 28
R/W
0x00000000
Address@mtgy : 0x06433a70
Address@com_mtgy : 0x06433a70
Address@app_mtgy : 0x400e3a70
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_e29
MWMM operand E register 29
R/W
0x00000000
Address@mtgy : 0x06433a74
Address@com_mtgy : 0x06433a74
Address@app_mtgy : 0x400e3a74
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_e30
MWMM operand E register 30
R/W
0x00000000
Address@mtgy : 0x06433a78
Address@com_mtgy : 0x06433a78
Address@app_mtgy : 0x400e3a78
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_e31
MWMM operand E register 31
R/W
0x00000000
Address@mtgy : 0x06433a7c
Address@com_mtgy : 0x06433a7c
Address@app_mtgy : 0x400e3a7c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_e32
MWMM operand E register 32
R/W
0x00000000
Address@mtgy : 0x06433a80
Address@com_mtgy : 0x06433a80
Address@app_mtgy : 0x400e3a80
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_e33
MWMM operand E register 33
R/W
0x00000000
Address@mtgy : 0x06433a84
Address@com_mtgy : 0x06433a84
Address@app_mtgy : 0x400e3a84
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_e34
MWMM operand E register 34
R/W
0x00000000
Address@mtgy : 0x06433a88
Address@com_mtgy : 0x06433a88
Address@app_mtgy : 0x400e3a88
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_e35
MWMM operand E register 35
R/W
0x00000000
Address@mtgy : 0x06433a8c
Address@com_mtgy : 0x06433a8c
Address@app_mtgy : 0x400e3a8c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_e36
MWMM operand E register 36
R/W
0x00000000
Address@mtgy : 0x06433a90
Address@com_mtgy : 0x06433a90
Address@app_mtgy : 0x400e3a90
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_e37
MWMM operand E register 37
R/W
0x00000000
Address@mtgy : 0x06433a94
Address@com_mtgy : 0x06433a94
Address@app_mtgy : 0x400e3a94
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_e38
MWMM operand E register 38
R/W
0x00000000
Address@mtgy : 0x06433a98
Address@com_mtgy : 0x06433a98
Address@app_mtgy : 0x400e3a98
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_e39
MWMM operand E register 39
R/W
0x00000000
Address@mtgy : 0x06433a9c
Address@com_mtgy : 0x06433a9c
Address@app_mtgy : 0x400e3a9c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_e40
MWMM operand E register 40
R/W
0x00000000
Address@mtgy : 0x06433aa0
Address@com_mtgy : 0x06433aa0
Address@app_mtgy : 0x400e3aa0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_e41
MWMM operand E register 41
R/W
0x00000000
Address@mtgy : 0x06433aa4
Address@com_mtgy : 0x06433aa4
Address@app_mtgy : 0x400e3aa4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_e42
MWMM operand E register 42
R/W
0x00000000
Address@mtgy : 0x06433aa8
Address@com_mtgy : 0x06433aa8
Address@app_mtgy : 0x400e3aa8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_e43
MWMM operand E register 43
R/W
0x00000000
Address@mtgy : 0x06433aac
Address@com_mtgy : 0x06433aac
Address@app_mtgy : 0x400e3aac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_e44
MWMM operand E register 44
R/W
0x00000000
Address@mtgy : 0x06433ab0
Address@com_mtgy : 0x06433ab0
Address@app_mtgy : 0x400e3ab0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_e45
MWMM operand E register 45
R/W
0x00000000
Address@mtgy : 0x06433ab4
Address@com_mtgy : 0x06433ab4
Address@app_mtgy : 0x400e3ab4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_e46
MWMM operand E register 46
R/W
0x00000000
Address@mtgy : 0x06433ab8
Address@com_mtgy : 0x06433ab8
Address@app_mtgy : 0x400e3ab8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_e47
MWMM operand E register 47
R/W
0x00000000
Address@mtgy : 0x06433abc
Address@com_mtgy : 0x06433abc
Address@app_mtgy : 0x400e3abc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_e48
MWMM operand E register 48
R/W
0x00000000
Address@mtgy : 0x06433ac0
Address@com_mtgy : 0x06433ac0
Address@app_mtgy : 0x400e3ac0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_e49
MWMM operand E register 49
R/W
0x00000000
Address@mtgy : 0x06433ac4
Address@com_mtgy : 0x06433ac4
Address@app_mtgy : 0x400e3ac4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_e50
MWMM operand E register 50
R/W
0x00000000
Address@mtgy : 0x06433ac8
Address@com_mtgy : 0x06433ac8
Address@app_mtgy : 0x400e3ac8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_e51
MWMM operand E register 51
R/W
0x00000000
Address@mtgy : 0x06433acc
Address@com_mtgy : 0x06433acc
Address@app_mtgy : 0x400e3acc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_e52
MWMM operand E register 52
R/W
0x00000000
Address@mtgy : 0x06433ad0
Address@com_mtgy : 0x06433ad0
Address@app_mtgy : 0x400e3ad0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_e53
MWMM operand E register 53
R/W
0x00000000
Address@mtgy : 0x06433ad4
Address@com_mtgy : 0x06433ad4
Address@app_mtgy : 0x400e3ad4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_e54
MWMM operand E register 54
R/W
0x00000000
Address@mtgy : 0x06433ad8
Address@com_mtgy : 0x06433ad8
Address@app_mtgy : 0x400e3ad8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_e55
MWMM operand E register 55
R/W
0x00000000
Address@mtgy : 0x06433adc
Address@com_mtgy : 0x06433adc
Address@app_mtgy : 0x400e3adc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_e56
MWMM operand E register 56
R/W
0x00000000
Address@mtgy : 0x06433ae0
Address@com_mtgy : 0x06433ae0
Address@app_mtgy : 0x400e3ae0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_e57
MWMM operand E register 57
R/W
0x00000000
Address@mtgy : 0x06433ae4
Address@com_mtgy : 0x06433ae4
Address@app_mtgy : 0x400e3ae4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_e58
MWMM operand E register 58
R/W
0x00000000
Address@mtgy : 0x06433ae8
Address@com_mtgy : 0x06433ae8
Address@app_mtgy : 0x400e3ae8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_e59
MWMM operand E register 59
R/W
0x00000000
Address@mtgy : 0x06433aec
Address@com_mtgy : 0x06433aec
Address@app_mtgy : 0x400e3aec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_e60
MWMM operand E register 60
R/W
0x00000000
Address@mtgy : 0x06433af0
Address@com_mtgy : 0x06433af0
Address@app_mtgy : 0x400e3af0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_e61
MWMM operand E register 61
R/W
0x00000000
Address@mtgy : 0x06433af4
Address@com_mtgy : 0x06433af4
Address@app_mtgy : 0x400e3af4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_e62
MWMM operand E register 62
R/W
0x00000000
Address@mtgy : 0x06433af8
Address@com_mtgy : 0x06433af8
Address@app_mtgy : 0x400e3af8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_e63
MWMM operand E register 63
R/W
0x00000000
Address@mtgy : 0x06433afc
Address@com_mtgy : 0x06433afc
Address@app_mtgy : 0x400e3afc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_e64
MWMM operand E register 64
R/W
0x00000000
Address@mtgy : 0x06433b00
Address@com_mtgy : 0x06433b00
Address@app_mtgy : 0x400e3b00
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_e65
MWMM operand E register 65
R/W
0x00000000
Address@mtgy : 0x06433b04
Address@com_mtgy : 0x06433b04
Address@app_mtgy : 0x400e3b04
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_e66
MWMM operand E register 66
R/W
0x00000000
Address@mtgy : 0x06433b08
Address@com_mtgy : 0x06433b08
Address@app_mtgy : 0x400e3b08
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_e67
MWMM operand E register 67
R/W
0x00000000
Address@mtgy : 0x06433b0c
Address@com_mtgy : 0x06433b0c
Address@app_mtgy : 0x400e3b0c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_e68
MWMM operand E register 68
R/W
0x00000000
Address@mtgy : 0x06433b10
Address@com_mtgy : 0x06433b10
Address@app_mtgy : 0x400e3b10
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_e69
MWMM operand E register 69
R/W
0x00000000
Address@mtgy : 0x06433b14
Address@com_mtgy : 0x06433b14
Address@app_mtgy : 0x400e3b14
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_e70
MWMM operand E register 70
R/W
0x00000000
Address@mtgy : 0x06433b18
Address@com_mtgy : 0x06433b18
Address@app_mtgy : 0x400e3b18
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_e71
MWMM operand E register 71
R/W
0x00000000
Address@mtgy : 0x06433b1c
Address@com_mtgy : 0x06433b1c
Address@app_mtgy : 0x400e3b1c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_e72
MWMM operand E register 72
R/W
0x00000000
Address@mtgy : 0x06433b20
Address@com_mtgy : 0x06433b20
Address@app_mtgy : 0x400e3b20
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_e73
MWMM operand E register 73
R/W
0x00000000
Address@mtgy : 0x06433b24
Address@com_mtgy : 0x06433b24
Address@app_mtgy : 0x400e3b24
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_e74
MWMM operand E register 74
R/W
0x00000000
Address@mtgy : 0x06433b28
Address@com_mtgy : 0x06433b28
Address@app_mtgy : 0x400e3b28
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_e75
MWMM operand E register 75
R/W
0x00000000
Address@mtgy : 0x06433b2c
Address@com_mtgy : 0x06433b2c
Address@app_mtgy : 0x400e3b2c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_e76
MWMM operand E register 76
R/W
0x00000000
Address@mtgy : 0x06433b30
Address@com_mtgy : 0x06433b30
Address@app_mtgy : 0x400e3b30
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_e77
MWMM operand E register 77
R/W
0x00000000
Address@mtgy : 0x06433b34
Address@com_mtgy : 0x06433b34
Address@app_mtgy : 0x400e3b34
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_e78
MWMM operand E register 78
R/W
0x00000000
Address@mtgy : 0x06433b38
Address@com_mtgy : 0x06433b38
Address@app_mtgy : 0x400e3b38
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_e79
MWMM operand E register 79
R/W
0x00000000
Address@mtgy : 0x06433b3c
Address@com_mtgy : 0x06433b3c
Address@app_mtgy : 0x400e3b3c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_e80
MWMM operand E register 80
R/W
0x00000000
Address@mtgy : 0x06433b40
Address@com_mtgy : 0x06433b40
Address@app_mtgy : 0x400e3b40
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_e81
MWMM operand E register 81
R/W
0x00000000
Address@mtgy : 0x06433b44
Address@com_mtgy : 0x06433b44
Address@app_mtgy : 0x400e3b44
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_e82
MWMM operand E register 82
R/W
0x00000000
Address@mtgy : 0x06433b48
Address@com_mtgy : 0x06433b48
Address@app_mtgy : 0x400e3b48
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_e83
MWMM operand E register 83
R/W
0x00000000
Address@mtgy : 0x06433b4c
Address@com_mtgy : 0x06433b4c
Address@app_mtgy : 0x400e3b4c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_e84
MWMM operand E register 84
R/W
0x00000000
Address@mtgy : 0x06433b50
Address@com_mtgy : 0x06433b50
Address@app_mtgy : 0x400e3b50
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_e85
MWMM operand E register 85
R/W
0x00000000
Address@mtgy : 0x06433b54
Address@com_mtgy : 0x06433b54
Address@app_mtgy : 0x400e3b54
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_e86
MWMM operand E register 86
R/W
0x00000000
Address@mtgy : 0x06433b58
Address@com_mtgy : 0x06433b58
Address@app_mtgy : 0x400e3b58
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_e87
MWMM operand E register 87
R/W
0x00000000
Address@mtgy : 0x06433b5c
Address@com_mtgy : 0x06433b5c
Address@app_mtgy : 0x400e3b5c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_e88
MWMM operand E register 88
R/W
0x00000000
Address@mtgy : 0x06433b60
Address@com_mtgy : 0x06433b60
Address@app_mtgy : 0x400e3b60
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_e89
MWMM operand E register 89
R/W
0x00000000
Address@mtgy : 0x06433b64
Address@com_mtgy : 0x06433b64
Address@app_mtgy : 0x400e3b64
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_e90
MWMM operand E register 90
R/W
0x00000000
Address@mtgy : 0x06433b68
Address@com_mtgy : 0x06433b68
Address@app_mtgy : 0x400e3b68
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_e91
MWMM operand E register 91
R/W
0x00000000
Address@mtgy : 0x06433b6c
Address@com_mtgy : 0x06433b6c
Address@app_mtgy : 0x400e3b6c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_e92
MWMM operand E register 92
R/W
0x00000000
Address@mtgy : 0x06433b70
Address@com_mtgy : 0x06433b70
Address@app_mtgy : 0x400e3b70
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_e93
MWMM operand E register 93
R/W
0x00000000
Address@mtgy : 0x06433b74
Address@com_mtgy : 0x06433b74
Address@app_mtgy : 0x400e3b74
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_e94
MWMM operand E register 94
R/W
0x00000000
Address@mtgy : 0x06433b78
Address@com_mtgy : 0x06433b78
Address@app_mtgy : 0x400e3b78
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_e95
MWMM operand E register 95
R/W
0x00000000
Address@mtgy : 0x06433b7c
Address@com_mtgy : 0x06433b7c
Address@app_mtgy : 0x400e3b7c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_e96
MWMM operand E register 96
R/W
0x00000000
Address@mtgy : 0x06433b80
Address@com_mtgy : 0x06433b80
Address@app_mtgy : 0x400e3b80
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_e97
MWMM operand E register 97
R/W
0x00000000
Address@mtgy : 0x06433b84
Address@com_mtgy : 0x06433b84
Address@app_mtgy : 0x400e3b84
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_e98
MWMM operand E register 98
R/W
0x00000000
Address@mtgy : 0x06433b88
Address@com_mtgy : 0x06433b88
Address@app_mtgy : 0x400e3b88
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_e99
MWMM operand E register 99
R/W
0x00000000
Address@mtgy : 0x06433b8c
Address@com_mtgy : 0x06433b8c
Address@app_mtgy : 0x400e3b8c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_e100
MWMM operand E register 100
R/W
0x00000000
Address@mtgy : 0x06433b90
Address@com_mtgy : 0x06433b90
Address@app_mtgy : 0x400e3b90
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_e101
MWMM operand E register 101
R/W
0x00000000
Address@mtgy : 0x06433b94
Address@com_mtgy : 0x06433b94
Address@app_mtgy : 0x400e3b94
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_e102
MWMM operand E register 102
R/W
0x00000000
Address@mtgy : 0x06433b98
Address@com_mtgy : 0x06433b98
Address@app_mtgy : 0x400e3b98
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_e103
MWMM operand E register 103
R/W
0x00000000
Address@mtgy : 0x06433b9c
Address@com_mtgy : 0x06433b9c
Address@app_mtgy : 0x400e3b9c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_e104
MWMM operand E register 104
R/W
0x00000000
Address@mtgy : 0x06433ba0
Address@com_mtgy : 0x06433ba0
Address@app_mtgy : 0x400e3ba0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_e105
MWMM operand E register 105
R/W
0x00000000
Address@mtgy : 0x06433ba4
Address@com_mtgy : 0x06433ba4
Address@app_mtgy : 0x400e3ba4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_e106
MWMM operand E register 106
R/W
0x00000000
Address@mtgy : 0x06433ba8
Address@com_mtgy : 0x06433ba8
Address@app_mtgy : 0x400e3ba8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_e107
MWMM operand E register 107
R/W
0x00000000
Address@mtgy : 0x06433bac
Address@com_mtgy : 0x06433bac
Address@app_mtgy : 0x400e3bac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_e108
MWMM operand E register 108
R/W
0x00000000
Address@mtgy : 0x06433bb0
Address@com_mtgy : 0x06433bb0
Address@app_mtgy : 0x400e3bb0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_e109
MWMM operand E register 109
R/W
0x00000000
Address@mtgy : 0x06433bb4
Address@com_mtgy : 0x06433bb4
Address@app_mtgy : 0x400e3bb4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_e110
MWMM operand E register 110
R/W
0x00000000
Address@mtgy : 0x06433bb8
Address@com_mtgy : 0x06433bb8
Address@app_mtgy : 0x400e3bb8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_e111
MWMM operand E register 111
R/W
0x00000000
Address@mtgy : 0x06433bbc
Address@com_mtgy : 0x06433bbc
Address@app_mtgy : 0x400e3bbc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_e112
MWMM operand E register 112
R/W
0x00000000
Address@mtgy : 0x06433bc0
Address@com_mtgy : 0x06433bc0
Address@app_mtgy : 0x400e3bc0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_e113
MWMM operand E register 113
R/W
0x00000000
Address@mtgy : 0x06433bc4
Address@com_mtgy : 0x06433bc4
Address@app_mtgy : 0x400e3bc4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_e114
MWMM operand E register 114
R/W
0x00000000
Address@mtgy : 0x06433bc8
Address@com_mtgy : 0x06433bc8
Address@app_mtgy : 0x400e3bc8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_e115
MWMM operand E register 115
R/W
0x00000000
Address@mtgy : 0x06433bcc
Address@com_mtgy : 0x06433bcc
Address@app_mtgy : 0x400e3bcc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_e116
MWMM operand E register 116
R/W
0x00000000
Address@mtgy : 0x06433bd0
Address@com_mtgy : 0x06433bd0
Address@app_mtgy : 0x400e3bd0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_e117
MWMM operand E register 117
R/W
0x00000000
Address@mtgy : 0x06433bd4
Address@com_mtgy : 0x06433bd4
Address@app_mtgy : 0x400e3bd4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_e118
MWMM operand E register 118
R/W
0x00000000
Address@mtgy : 0x06433bd8
Address@com_mtgy : 0x06433bd8
Address@app_mtgy : 0x400e3bd8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_e119
MWMM operand E register 119
R/W
0x00000000
Address@mtgy : 0x06433bdc
Address@com_mtgy : 0x06433bdc
Address@app_mtgy : 0x400e3bdc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_e120
MWMM operand E register 120
R/W
0x00000000
Address@mtgy : 0x06433be0
Address@com_mtgy : 0x06433be0
Address@app_mtgy : 0x400e3be0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_e121
MWMM operand E register 121
R/W
0x00000000
Address@mtgy : 0x06433be4
Address@com_mtgy : 0x06433be4
Address@app_mtgy : 0x400e3be4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_e122
MWMM operand E register 122
R/W
0x00000000
Address@mtgy : 0x06433be8
Address@com_mtgy : 0x06433be8
Address@app_mtgy : 0x400e3be8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_e123
MWMM operand E register 123
R/W
0x00000000
Address@mtgy : 0x06433bec
Address@com_mtgy : 0x06433bec
Address@app_mtgy : 0x400e3bec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_e124
MWMM operand E register 124
R/W
0x00000000
Address@mtgy : 0x06433bf0
Address@com_mtgy : 0x06433bf0
Address@app_mtgy : 0x400e3bf0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_e125
MWMM operand E register 125
R/W
0x00000000
Address@mtgy : 0x06433bf4
Address@com_mtgy : 0x06433bf4
Address@app_mtgy : 0x400e3bf4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_e126
MWMM operand E register 126
R/W
0x00000000
Address@mtgy : 0x06433bf8
Address@com_mtgy : 0x06433bf8
Address@app_mtgy : 0x400e3bf8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_e127
MWMM operand E register 127
R/W
0x00000000
Address@mtgy : 0x06433bfc
Address@com_mtgy : 0x06433bfc
Address@app_mtgy : 0x400e3bfc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064


mtgy_op_x0
MWMM operand X register 0
R/W
0x00000000
Address@mtgy : 0x06433c00
Address@com_mtgy : 0x06433c00
Address@app_mtgy : 0x400e3c00
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


mtgy_op_x1
MWMM operand X register 1
R/W
0x00000000
Address@mtgy : 0x06433c04
Address@com_mtgy : 0x06433c04
Address@app_mtgy : 0x400e3c04
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


mtgy_op_x2
MWMM operand X register 2
R/W
0x00000000
Address@mtgy : 0x06433c08
Address@com_mtgy : 0x06433c08
Address@app_mtgy : 0x400e3c08
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


mtgy_op_x3
MWMM operand X register 3
R/W
0x00000000
Address@mtgy : 0x06433c0c
Address@com_mtgy : 0x06433c0c
Address@app_mtgy : 0x400e3c0c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


mtgy_op_x4
MWMM operand X register 4
R/W
0x00000000
Address@mtgy : 0x06433c10
Address@com_mtgy : 0x06433c10
Address@app_mtgy : 0x400e3c10
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


mtgy_op_x5
MWMM operand X register 5
R/W
0x00000000
Address@mtgy : 0x06433c14
Address@com_mtgy : 0x06433c14
Address@app_mtgy : 0x400e3c14
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


mtgy_op_x6
MWMM operand X register 6
R/W
0x00000000
Address@mtgy : 0x06433c18
Address@com_mtgy : 0x06433c18
Address@app_mtgy : 0x400e3c18
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


mtgy_op_x7
MWMM operand X register 7
R/W
0x00000000
Address@mtgy : 0x06433c1c
Address@com_mtgy : 0x06433c1c
Address@app_mtgy : 0x400e3c1c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


mtgy_op_x8
MWMM operand X register 8
R/W
0x00000000
Address@mtgy : 0x06433c20
Address@com_mtgy : 0x06433c20
Address@app_mtgy : 0x400e3c20
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


mtgy_op_x9
MWMM operand X register 9
R/W
0x00000000
Address@mtgy : 0x06433c24
Address@com_mtgy : 0x06433c24
Address@app_mtgy : 0x400e3c24
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


mtgy_op_x10
MWMM operand X register 10
R/W
0x00000000
Address@mtgy : 0x06433c28
Address@com_mtgy : 0x06433c28
Address@app_mtgy : 0x400e3c28
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


mtgy_op_x11
MWMM operand X register 11
R/W
0x00000000
Address@mtgy : 0x06433c2c
Address@com_mtgy : 0x06433c2c
Address@app_mtgy : 0x400e3c2c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


mtgy_op_x12
MWMM operand X register 12
R/W
0x00000000
Address@mtgy : 0x06433c30
Address@com_mtgy : 0x06433c30
Address@app_mtgy : 0x400e3c30
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


mtgy_op_x13
MWMM operand X register 13
R/W
0x00000000
Address@mtgy : 0x06433c34
Address@com_mtgy : 0x06433c34
Address@app_mtgy : 0x400e3c34
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


mtgy_op_x14
MWMM operand X register 14
R/W
0x00000000
Address@mtgy : 0x06433c38
Address@com_mtgy : 0x06433c38
Address@app_mtgy : 0x400e3c38
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


mtgy_op_x15
MWMM operand X register 15
R/W
0x00000000
Address@mtgy : 0x06433c3c
Address@com_mtgy : 0x06433c3c
Address@app_mtgy : 0x400e3c3c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480


mtgy_op_x16
MWMM operand X register 16
R/W
0x00000000
Address@mtgy : 0x06433c40
Address@com_mtgy : 0x06433c40
Address@app_mtgy : 0x400e3c40
Bits Reset value Name Description
31 - 0 0x0
val
data bits 543..512


mtgy_op_x17
MWMM operand X register 17
R/W
0x00000000
Address@mtgy : 0x06433c44
Address@com_mtgy : 0x06433c44
Address@app_mtgy : 0x400e3c44
Bits Reset value Name Description
31 - 0 0x0
val
data bits 575..544


mtgy_op_x18
MWMM operand X register 18
R/W
0x00000000
Address@mtgy : 0x06433c48
Address@com_mtgy : 0x06433c48
Address@app_mtgy : 0x400e3c48
Bits Reset value Name Description
31 - 0 0x0
val
data bits 607..576


mtgy_op_x19
MWMM operand X register 19
R/W
0x00000000
Address@mtgy : 0x06433c4c
Address@com_mtgy : 0x06433c4c
Address@app_mtgy : 0x400e3c4c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 639..608


mtgy_op_x20
MWMM operand X register 20
R/W
0x00000000
Address@mtgy : 0x06433c50
Address@com_mtgy : 0x06433c50
Address@app_mtgy : 0x400e3c50
Bits Reset value Name Description
31 - 0 0x0
val
data bits 671..640


mtgy_op_x21
MWMM operand X register 21
R/W
0x00000000
Address@mtgy : 0x06433c54
Address@com_mtgy : 0x06433c54
Address@app_mtgy : 0x400e3c54
Bits Reset value Name Description
31 - 0 0x0
val
data bits 703..672


mtgy_op_x22
MWMM operand X register 22
R/W
0x00000000
Address@mtgy : 0x06433c58
Address@com_mtgy : 0x06433c58
Address@app_mtgy : 0x400e3c58
Bits Reset value Name Description
31 - 0 0x0
val
data bits 735..704


mtgy_op_x23
MWMM operand X register 23
R/W
0x00000000
Address@mtgy : 0x06433c5c
Address@com_mtgy : 0x06433c5c
Address@app_mtgy : 0x400e3c5c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 767..736


mtgy_op_x24
MWMM operand X register 24
R/W
0x00000000
Address@mtgy : 0x06433c60
Address@com_mtgy : 0x06433c60
Address@app_mtgy : 0x400e3c60
Bits Reset value Name Description
31 - 0 0x0
val
data bits 799..768


mtgy_op_x25
MWMM operand X register 25
R/W
0x00000000
Address@mtgy : 0x06433c64
Address@com_mtgy : 0x06433c64
Address@app_mtgy : 0x400e3c64
Bits Reset value Name Description
31 - 0 0x0
val
data bits 831..800


mtgy_op_x26
MWMM operand X register 26
R/W
0x00000000
Address@mtgy : 0x06433c68
Address@com_mtgy : 0x06433c68
Address@app_mtgy : 0x400e3c68
Bits Reset value Name Description
31 - 0 0x0
val
data bits 863..832


mtgy_op_x27
MWMM operand X register 27
R/W
0x00000000
Address@mtgy : 0x06433c6c
Address@com_mtgy : 0x06433c6c
Address@app_mtgy : 0x400e3c6c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 895..864


mtgy_op_x28
MWMM operand X register 28
R/W
0x00000000
Address@mtgy : 0x06433c70
Address@com_mtgy : 0x06433c70
Address@app_mtgy : 0x400e3c70
Bits Reset value Name Description
31 - 0 0x0
val
data bits 927..896


mtgy_op_x29
MWMM operand X register 29
R/W
0x00000000
Address@mtgy : 0x06433c74
Address@com_mtgy : 0x06433c74
Address@app_mtgy : 0x400e3c74
Bits Reset value Name Description
31 - 0 0x0
val
data bits 959..928


mtgy_op_x30
MWMM operand X register 30
R/W
0x00000000
Address@mtgy : 0x06433c78
Address@com_mtgy : 0x06433c78
Address@app_mtgy : 0x400e3c78
Bits Reset value Name Description
31 - 0 0x0
val
data bits 991..960


mtgy_op_x31
MWMM operand X register 31
R/W
0x00000000
Address@mtgy : 0x06433c7c
Address@com_mtgy : 0x06433c7c
Address@app_mtgy : 0x400e3c7c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1023..992


mtgy_op_x32
MWMM operand X register 32
R/W
0x00000000
Address@mtgy : 0x06433c80
Address@com_mtgy : 0x06433c80
Address@app_mtgy : 0x400e3c80
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1055..1024


mtgy_op_x33
MWMM operand X register 33
R/W
0x00000000
Address@mtgy : 0x06433c84
Address@com_mtgy : 0x06433c84
Address@app_mtgy : 0x400e3c84
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1087..1056


mtgy_op_x34
MWMM operand X register 34
R/W
0x00000000
Address@mtgy : 0x06433c88
Address@com_mtgy : 0x06433c88
Address@app_mtgy : 0x400e3c88
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1119..1088


mtgy_op_x35
MWMM operand X register 35
R/W
0x00000000
Address@mtgy : 0x06433c8c
Address@com_mtgy : 0x06433c8c
Address@app_mtgy : 0x400e3c8c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1151..1120


mtgy_op_x36
MWMM operand X register 36
R/W
0x00000000
Address@mtgy : 0x06433c90
Address@com_mtgy : 0x06433c90
Address@app_mtgy : 0x400e3c90
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1183..1152


mtgy_op_x37
MWMM operand X register 37
R/W
0x00000000
Address@mtgy : 0x06433c94
Address@com_mtgy : 0x06433c94
Address@app_mtgy : 0x400e3c94
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1215..1184


mtgy_op_x38
MWMM operand X register 38
R/W
0x00000000
Address@mtgy : 0x06433c98
Address@com_mtgy : 0x06433c98
Address@app_mtgy : 0x400e3c98
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1247..1216


mtgy_op_x39
MWMM operand X register 39
R/W
0x00000000
Address@mtgy : 0x06433c9c
Address@com_mtgy : 0x06433c9c
Address@app_mtgy : 0x400e3c9c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1279..1248


mtgy_op_x40
MWMM operand X register 40
R/W
0x00000000
Address@mtgy : 0x06433ca0
Address@com_mtgy : 0x06433ca0
Address@app_mtgy : 0x400e3ca0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1311..1280


mtgy_op_x41
MWMM operand X register 41
R/W
0x00000000
Address@mtgy : 0x06433ca4
Address@com_mtgy : 0x06433ca4
Address@app_mtgy : 0x400e3ca4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1343..1312


mtgy_op_x42
MWMM operand X register 42
R/W
0x00000000
Address@mtgy : 0x06433ca8
Address@com_mtgy : 0x06433ca8
Address@app_mtgy : 0x400e3ca8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1375..1344


mtgy_op_x43
MWMM operand X register 43
R/W
0x00000000
Address@mtgy : 0x06433cac
Address@com_mtgy : 0x06433cac
Address@app_mtgy : 0x400e3cac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1407..1376


mtgy_op_x44
MWMM operand X register 44
R/W
0x00000000
Address@mtgy : 0x06433cb0
Address@com_mtgy : 0x06433cb0
Address@app_mtgy : 0x400e3cb0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1439..1408


mtgy_op_x45
MWMM operand X register 45
R/W
0x00000000
Address@mtgy : 0x06433cb4
Address@com_mtgy : 0x06433cb4
Address@app_mtgy : 0x400e3cb4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1471..1440


mtgy_op_x46
MWMM operand X register 46
R/W
0x00000000
Address@mtgy : 0x06433cb8
Address@com_mtgy : 0x06433cb8
Address@app_mtgy : 0x400e3cb8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1503..1472


mtgy_op_x47
MWMM operand X register 47
R/W
0x00000000
Address@mtgy : 0x06433cbc
Address@com_mtgy : 0x06433cbc
Address@app_mtgy : 0x400e3cbc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1535..1504


mtgy_op_x48
MWMM operand X register 48
R/W
0x00000000
Address@mtgy : 0x06433cc0
Address@com_mtgy : 0x06433cc0
Address@app_mtgy : 0x400e3cc0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1567..1536


mtgy_op_x49
MWMM operand X register 49
R/W
0x00000000
Address@mtgy : 0x06433cc4
Address@com_mtgy : 0x06433cc4
Address@app_mtgy : 0x400e3cc4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1599..1568


mtgy_op_x50
MWMM operand X register 50
R/W
0x00000000
Address@mtgy : 0x06433cc8
Address@com_mtgy : 0x06433cc8
Address@app_mtgy : 0x400e3cc8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1631..1600


mtgy_op_x51
MWMM operand X register 51
R/W
0x00000000
Address@mtgy : 0x06433ccc
Address@com_mtgy : 0x06433ccc
Address@app_mtgy : 0x400e3ccc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1663..1632


mtgy_op_x52
MWMM operand X register 52
R/W
0x00000000
Address@mtgy : 0x06433cd0
Address@com_mtgy : 0x06433cd0
Address@app_mtgy : 0x400e3cd0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1695..1664


mtgy_op_x53
MWMM operand X register 53
R/W
0x00000000
Address@mtgy : 0x06433cd4
Address@com_mtgy : 0x06433cd4
Address@app_mtgy : 0x400e3cd4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1727..1696


mtgy_op_x54
MWMM operand X register 54
R/W
0x00000000
Address@mtgy : 0x06433cd8
Address@com_mtgy : 0x06433cd8
Address@app_mtgy : 0x400e3cd8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1759..1728


mtgy_op_x55
MWMM operand X register 55
R/W
0x00000000
Address@mtgy : 0x06433cdc
Address@com_mtgy : 0x06433cdc
Address@app_mtgy : 0x400e3cdc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1791..1760


mtgy_op_x56
MWMM operand X register 56
R/W
0x00000000
Address@mtgy : 0x06433ce0
Address@com_mtgy : 0x06433ce0
Address@app_mtgy : 0x400e3ce0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1823..1792


mtgy_op_x57
MWMM operand X register 57
R/W
0x00000000
Address@mtgy : 0x06433ce4
Address@com_mtgy : 0x06433ce4
Address@app_mtgy : 0x400e3ce4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1855..1824


mtgy_op_x58
MWMM operand X register 58
R/W
0x00000000
Address@mtgy : 0x06433ce8
Address@com_mtgy : 0x06433ce8
Address@app_mtgy : 0x400e3ce8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1887..1856


mtgy_op_x59
MWMM operand X register 59
R/W
0x00000000
Address@mtgy : 0x06433cec
Address@com_mtgy : 0x06433cec
Address@app_mtgy : 0x400e3cec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1919..1888


mtgy_op_x60
MWMM operand X register 60
R/W
0x00000000
Address@mtgy : 0x06433cf0
Address@com_mtgy : 0x06433cf0
Address@app_mtgy : 0x400e3cf0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1951..1920


mtgy_op_x61
MWMM operand X register 61
R/W
0x00000000
Address@mtgy : 0x06433cf4
Address@com_mtgy : 0x06433cf4
Address@app_mtgy : 0x400e3cf4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 1983..1952


mtgy_op_x62
MWMM operand X register 62
R/W
0x00000000
Address@mtgy : 0x06433cf8
Address@com_mtgy : 0x06433cf8
Address@app_mtgy : 0x400e3cf8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2015..1984


mtgy_op_x63
MWMM operand X register 63
R/W
0x00000000
Address@mtgy : 0x06433cfc
Address@com_mtgy : 0x06433cfc
Address@app_mtgy : 0x400e3cfc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2047..2016


mtgy_op_x64
MWMM operand X register 64
R/W
0x00000000
Address@mtgy : 0x06433d00
Address@com_mtgy : 0x06433d00
Address@app_mtgy : 0x400e3d00
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2079..2048


mtgy_op_x65
MWMM operand X register 65
R/W
0x00000000
Address@mtgy : 0x06433d04
Address@com_mtgy : 0x06433d04
Address@app_mtgy : 0x400e3d04
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2111..2080


mtgy_op_x66
MWMM operand X register 66
R/W
0x00000000
Address@mtgy : 0x06433d08
Address@com_mtgy : 0x06433d08
Address@app_mtgy : 0x400e3d08
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2143..2112


mtgy_op_x67
MWMM operand X register 67
R/W
0x00000000
Address@mtgy : 0x06433d0c
Address@com_mtgy : 0x06433d0c
Address@app_mtgy : 0x400e3d0c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2175..2144


mtgy_op_x68
MWMM operand X register 68
R/W
0x00000000
Address@mtgy : 0x06433d10
Address@com_mtgy : 0x06433d10
Address@app_mtgy : 0x400e3d10
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2207..2176


mtgy_op_x69
MWMM operand X register 69
R/W
0x00000000
Address@mtgy : 0x06433d14
Address@com_mtgy : 0x06433d14
Address@app_mtgy : 0x400e3d14
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2239..2208


mtgy_op_x70
MWMM operand X register 70
R/W
0x00000000
Address@mtgy : 0x06433d18
Address@com_mtgy : 0x06433d18
Address@app_mtgy : 0x400e3d18
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2271..2240


mtgy_op_x71
MWMM operand X register 71
R/W
0x00000000
Address@mtgy : 0x06433d1c
Address@com_mtgy : 0x06433d1c
Address@app_mtgy : 0x400e3d1c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2303..2272


mtgy_op_x72
MWMM operand X register 72
R/W
0x00000000
Address@mtgy : 0x06433d20
Address@com_mtgy : 0x06433d20
Address@app_mtgy : 0x400e3d20
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2335..2304


mtgy_op_x73
MWMM operand X register 73
R/W
0x00000000
Address@mtgy : 0x06433d24
Address@com_mtgy : 0x06433d24
Address@app_mtgy : 0x400e3d24
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2367..2336


mtgy_op_x74
MWMM operand X register 74
R/W
0x00000000
Address@mtgy : 0x06433d28
Address@com_mtgy : 0x06433d28
Address@app_mtgy : 0x400e3d28
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2399..2368


mtgy_op_x75
MWMM operand X register 75
R/W
0x00000000
Address@mtgy : 0x06433d2c
Address@com_mtgy : 0x06433d2c
Address@app_mtgy : 0x400e3d2c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2431..2400


mtgy_op_x76
MWMM operand X register 76
R/W
0x00000000
Address@mtgy : 0x06433d30
Address@com_mtgy : 0x06433d30
Address@app_mtgy : 0x400e3d30
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2463..2432


mtgy_op_x77
MWMM operand X register 77
R/W
0x00000000
Address@mtgy : 0x06433d34
Address@com_mtgy : 0x06433d34
Address@app_mtgy : 0x400e3d34
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2495..2464


mtgy_op_x78
MWMM operand X register 78
R/W
0x00000000
Address@mtgy : 0x06433d38
Address@com_mtgy : 0x06433d38
Address@app_mtgy : 0x400e3d38
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2527..2496


mtgy_op_x79
MWMM operand X register 79
R/W
0x00000000
Address@mtgy : 0x06433d3c
Address@com_mtgy : 0x06433d3c
Address@app_mtgy : 0x400e3d3c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2559..2528


mtgy_op_x80
MWMM operand X register 80
R/W
0x00000000
Address@mtgy : 0x06433d40
Address@com_mtgy : 0x06433d40
Address@app_mtgy : 0x400e3d40
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2591..2560


mtgy_op_x81
MWMM operand X register 81
R/W
0x00000000
Address@mtgy : 0x06433d44
Address@com_mtgy : 0x06433d44
Address@app_mtgy : 0x400e3d44
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2623..2592


mtgy_op_x82
MWMM operand X register 82
R/W
0x00000000
Address@mtgy : 0x06433d48
Address@com_mtgy : 0x06433d48
Address@app_mtgy : 0x400e3d48
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2655..2624


mtgy_op_x83
MWMM operand X register 83
R/W
0x00000000
Address@mtgy : 0x06433d4c
Address@com_mtgy : 0x06433d4c
Address@app_mtgy : 0x400e3d4c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2687..2656


mtgy_op_x84
MWMM operand X register 84
R/W
0x00000000
Address@mtgy : 0x06433d50
Address@com_mtgy : 0x06433d50
Address@app_mtgy : 0x400e3d50
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2719..2688


mtgy_op_x85
MWMM operand X register 85
R/W
0x00000000
Address@mtgy : 0x06433d54
Address@com_mtgy : 0x06433d54
Address@app_mtgy : 0x400e3d54
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2751..2720


mtgy_op_x86
MWMM operand X register 86
R/W
0x00000000
Address@mtgy : 0x06433d58
Address@com_mtgy : 0x06433d58
Address@app_mtgy : 0x400e3d58
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2783..2752


mtgy_op_x87
MWMM operand X register 87
R/W
0x00000000
Address@mtgy : 0x06433d5c
Address@com_mtgy : 0x06433d5c
Address@app_mtgy : 0x400e3d5c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2815..2784


mtgy_op_x88
MWMM operand X register 88
R/W
0x00000000
Address@mtgy : 0x06433d60
Address@com_mtgy : 0x06433d60
Address@app_mtgy : 0x400e3d60
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2847..2816


mtgy_op_x89
MWMM operand X register 89
R/W
0x00000000
Address@mtgy : 0x06433d64
Address@com_mtgy : 0x06433d64
Address@app_mtgy : 0x400e3d64
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2879..2848


mtgy_op_x90
MWMM operand X register 90
R/W
0x00000000
Address@mtgy : 0x06433d68
Address@com_mtgy : 0x06433d68
Address@app_mtgy : 0x400e3d68
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2911..2880


mtgy_op_x91
MWMM operand X register 91
R/W
0x00000000
Address@mtgy : 0x06433d6c
Address@com_mtgy : 0x06433d6c
Address@app_mtgy : 0x400e3d6c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2943..2912


mtgy_op_x92
MWMM operand X register 92
R/W
0x00000000
Address@mtgy : 0x06433d70
Address@com_mtgy : 0x06433d70
Address@app_mtgy : 0x400e3d70
Bits Reset value Name Description
31 - 0 0x0
val
data bits 2975..2944


mtgy_op_x93
MWMM operand X register 93
R/W
0x00000000
Address@mtgy : 0x06433d74
Address@com_mtgy : 0x06433d74
Address@app_mtgy : 0x400e3d74
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3007..2976


mtgy_op_x94
MWMM operand X register 94
R/W
0x00000000
Address@mtgy : 0x06433d78
Address@com_mtgy : 0x06433d78
Address@app_mtgy : 0x400e3d78
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3039..3008


mtgy_op_x95
MWMM operand X register 95
R/W
0x00000000
Address@mtgy : 0x06433d7c
Address@com_mtgy : 0x06433d7c
Address@app_mtgy : 0x400e3d7c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3071..3040


mtgy_op_x96
MWMM operand X register 96
R/W
0x00000000
Address@mtgy : 0x06433d80
Address@com_mtgy : 0x06433d80
Address@app_mtgy : 0x400e3d80
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3103..3072


mtgy_op_x97
MWMM operand X register 97
R/W
0x00000000
Address@mtgy : 0x06433d84
Address@com_mtgy : 0x06433d84
Address@app_mtgy : 0x400e3d84
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3135..3104


mtgy_op_x98
MWMM operand X register 98
R/W
0x00000000
Address@mtgy : 0x06433d88
Address@com_mtgy : 0x06433d88
Address@app_mtgy : 0x400e3d88
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3167..3136


mtgy_op_x99
MWMM operand X register 99
R/W
0x00000000
Address@mtgy : 0x06433d8c
Address@com_mtgy : 0x06433d8c
Address@app_mtgy : 0x400e3d8c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3199..3168


mtgy_op_x100
MWMM operand X register 100
R/W
0x00000000
Address@mtgy : 0x06433d90
Address@com_mtgy : 0x06433d90
Address@app_mtgy : 0x400e3d90
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3231..3200


mtgy_op_x101
MWMM operand X register 101
R/W
0x00000000
Address@mtgy : 0x06433d94
Address@com_mtgy : 0x06433d94
Address@app_mtgy : 0x400e3d94
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3263..3232


mtgy_op_x102
MWMM operand X register 102
R/W
0x00000000
Address@mtgy : 0x06433d98
Address@com_mtgy : 0x06433d98
Address@app_mtgy : 0x400e3d98
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3295..3264


mtgy_op_x103
MWMM operand X register 103
R/W
0x00000000
Address@mtgy : 0x06433d9c
Address@com_mtgy : 0x06433d9c
Address@app_mtgy : 0x400e3d9c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3327..3296


mtgy_op_x104
MWMM operand X register 104
R/W
0x00000000
Address@mtgy : 0x06433da0
Address@com_mtgy : 0x06433da0
Address@app_mtgy : 0x400e3da0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3359..3328


mtgy_op_x105
MWMM operand X register 105
R/W
0x00000000
Address@mtgy : 0x06433da4
Address@com_mtgy : 0x06433da4
Address@app_mtgy : 0x400e3da4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3391..3360


mtgy_op_x106
MWMM operand X register 106
R/W
0x00000000
Address@mtgy : 0x06433da8
Address@com_mtgy : 0x06433da8
Address@app_mtgy : 0x400e3da8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3423..3392


mtgy_op_x107
MWMM operand X register 107
R/W
0x00000000
Address@mtgy : 0x06433dac
Address@com_mtgy : 0x06433dac
Address@app_mtgy : 0x400e3dac
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3455..3424


mtgy_op_x108
MWMM operand X register 108
R/W
0x00000000
Address@mtgy : 0x06433db0
Address@com_mtgy : 0x06433db0
Address@app_mtgy : 0x400e3db0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3487..3456


mtgy_op_x109
MWMM operand X register 109
R/W
0x00000000
Address@mtgy : 0x06433db4
Address@com_mtgy : 0x06433db4
Address@app_mtgy : 0x400e3db4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3519..3488


mtgy_op_x110
MWMM operand X register 110
R/W
0x00000000
Address@mtgy : 0x06433db8
Address@com_mtgy : 0x06433db8
Address@app_mtgy : 0x400e3db8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3551..3520


mtgy_op_x111
MWMM operand X register 111
R/W
0x00000000
Address@mtgy : 0x06433dbc
Address@com_mtgy : 0x06433dbc
Address@app_mtgy : 0x400e3dbc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3583..3552


mtgy_op_x112
MWMM operand X register 112
R/W
0x00000000
Address@mtgy : 0x06433dc0
Address@com_mtgy : 0x06433dc0
Address@app_mtgy : 0x400e3dc0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3615..3584


mtgy_op_x113
MWMM operand X register 113
R/W
0x00000000
Address@mtgy : 0x06433dc4
Address@com_mtgy : 0x06433dc4
Address@app_mtgy : 0x400e3dc4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3647..3616


mtgy_op_x114
MWMM operand X register 114
R/W
0x00000000
Address@mtgy : 0x06433dc8
Address@com_mtgy : 0x06433dc8
Address@app_mtgy : 0x400e3dc8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3679..3648


mtgy_op_x115
MWMM operand X register 115
R/W
0x00000000
Address@mtgy : 0x06433dcc
Address@com_mtgy : 0x06433dcc
Address@app_mtgy : 0x400e3dcc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3711..3680


mtgy_op_x116
MWMM operand X register 116
R/W
0x00000000
Address@mtgy : 0x06433dd0
Address@com_mtgy : 0x06433dd0
Address@app_mtgy : 0x400e3dd0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3743..3712


mtgy_op_x117
MWMM operand X register 117
R/W
0x00000000
Address@mtgy : 0x06433dd4
Address@com_mtgy : 0x06433dd4
Address@app_mtgy : 0x400e3dd4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3775..3744


mtgy_op_x118
MWMM operand X register 118
R/W
0x00000000
Address@mtgy : 0x06433dd8
Address@com_mtgy : 0x06433dd8
Address@app_mtgy : 0x400e3dd8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3807..3776


mtgy_op_x119
MWMM operand X register 119
R/W
0x00000000
Address@mtgy : 0x06433ddc
Address@com_mtgy : 0x06433ddc
Address@app_mtgy : 0x400e3ddc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3839..3808


mtgy_op_x120
MWMM operand X register 120
R/W
0x00000000
Address@mtgy : 0x06433de0
Address@com_mtgy : 0x06433de0
Address@app_mtgy : 0x400e3de0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3871..3840


mtgy_op_x121
MWMM operand X register 121
R/W
0x00000000
Address@mtgy : 0x06433de4
Address@com_mtgy : 0x06433de4
Address@app_mtgy : 0x400e3de4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3903..3872


mtgy_op_x122
MWMM operand X register 122
R/W
0x00000000
Address@mtgy : 0x06433de8
Address@com_mtgy : 0x06433de8
Address@app_mtgy : 0x400e3de8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3935..3904


mtgy_op_x123
MWMM operand X register 123
R/W
0x00000000
Address@mtgy : 0x06433dec
Address@com_mtgy : 0x06433dec
Address@app_mtgy : 0x400e3dec
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3967..3936


mtgy_op_x124
MWMM operand X register 124
R/W
0x00000000
Address@mtgy : 0x06433df0
Address@com_mtgy : 0x06433df0
Address@app_mtgy : 0x400e3df0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 3999..3968


mtgy_op_x125
MWMM operand X register 125
R/W
0x00000000
Address@mtgy : 0x06433df4
Address@com_mtgy : 0x06433df4
Address@app_mtgy : 0x400e3df4
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4031..4000


mtgy_op_x126
MWMM operand X register 126
R/W
0x00000000
Address@mtgy : 0x06433df8
Address@com_mtgy : 0x06433df8
Address@app_mtgy : 0x400e3df8
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4063..4032


mtgy_op_x127
MWMM operand X register 127
R/W
0x00000000
Address@mtgy : 0x06433dfc
Address@com_mtgy : 0x06433dfc
Address@app_mtgy : 0x400e3dfc
Bits Reset value Name Description
31 - 0 0x0
val
data bits 4095..4064



Base Address Area: gxc_gpec_dram, gxc_gpec00_dram, gxc_gpec01_dram, gxc_gpec02_dram, gxc_gpec03_dram, gxc_gpec04_dram, gxc_gpec05_dram, gxc_gpec06_dram, gxc_gpec07_dram, gxc_gpec10_dram, gxc_gpec11_dram, gxc_gpec12_dram, gxc_gpec13_dram, gxc_gpec14_dram, gxc_gpec15_dram, gxc_gpec16_dram, gxc_gpec17_dram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 - gpec_dram_start
1-7fe 4-1ff8 -  reserved
7ff 1ffc - gpec_dram_end

gpec_dram_start

Address@gxc_gpec_dram : 0x07c00000
Address@gxc_gpec00_dram : 0x07d00000
Address@gxc_gpec01_dram : 0x07d04000
Address@gxc_gpec02_dram : 0x07d08000
Address@gxc_gpec03_dram : 0x07d0c000
Address@gxc_gpec04_dram : 0x07d10000
Address@gxc_gpec05_dram : 0x07d14000
Address@gxc_gpec06_dram : 0x07d18000
Address@gxc_gpec07_dram : 0x07d1c000
Address@gxc_gpec10_dram : 0x07d40000
Address@gxc_gpec11_dram : 0x07d44000
Address@gxc_gpec12_dram : 0x07d48000
Address@gxc_gpec13_dram : 0x07d4c000
Address@gxc_gpec14_dram : 0x07d50000
Address@gxc_gpec15_dram : 0x07d54000
Address@gxc_gpec16_dram : 0x07d58000
Address@gxc_gpec17_dram : 0x07d5c000
Bits Name Description
31 - 0 gpec_dram_start


gpec_dram_end

Address@gxc_gpec_dram : 0x07c01ffc
Address@gxc_gpec00_dram : 0x07d01ffc
Address@gxc_gpec01_dram : 0x07d05ffc
Address@gxc_gpec02_dram : 0x07d09ffc
Address@gxc_gpec03_dram : 0x07d0dffc
Address@gxc_gpec04_dram : 0x07d11ffc
Address@gxc_gpec05_dram : 0x07d15ffc
Address@gxc_gpec06_dram : 0x07d19ffc
Address@gxc_gpec07_dram : 0x07d1dffc
Address@gxc_gpec10_dram : 0x07d41ffc
Address@gxc_gpec11_dram : 0x07d45ffc
Address@gxc_gpec12_dram : 0x07d49ffc
Address@gxc_gpec13_dram : 0x07d4dffc
Address@gxc_gpec14_dram : 0x07d51ffc
Address@gxc_gpec15_dram : 0x07d55ffc
Address@gxc_gpec16_dram : 0x07d59ffc
Address@gxc_gpec17_dram : 0x07d5dffc
Bits Name Description
31 - 0 gpec_dram_end



Base Address Area: gxc_grpu_ram, gxc_gtpu_ram, gxc_grpu0_ram, gxc_gtpu0_ram, gxc_grpu1_ram, gxc_gtpu1_ram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 - gmac_ram_start
1-17e 4-5f8 -  reserved
17f 5fc - gmac_ram_end
180-1ff 600-7fc -  reserved

gmac_ram_start
gMAC RPU program-RAM start address.
The Program-RAM is not addressable for gMAC RPU and TPU !

Address@gxc_grpu_ram : 0x07c00000
Address@gxc_gtpu_ram : 0x07c00800
Address@gxc_grpu0_ram : 0x07d20000
Address@gxc_gtpu0_ram : 0x07d20800
Address@gxc_grpu1_ram : 0x07d60000
Address@gxc_gtpu1_ram : 0x07d60800
Bits Name Description
31 - 0 gmac_ram_start


gmac_ram_end
gMAC RPU program-RAM end address.
This value is not used by design flow, only for documentation

Address@gxc_grpu_ram : 0x07c005fc
Address@gxc_gtpu_ram : 0x07c00dfc
Address@gxc_grpu0_ram : 0x07d205fc
Address@gxc_gtpu0_ram : 0x07d20dfc
Address@gxc_grpu1_ram : 0x07d605fc
Address@gxc_gtpu1_ram : 0x07d60dfc
Bits Name Description
31 - 0 gmac_ram_end



Base Address Area: gxc_token_bucket_instance0, gxc_token_bucket_instance1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W tbi_cr0
1 4 R/W tbi_bucket0_cfg
2 8 R/W tbi_bucket0_lvl
3 c R/W tbi_bucket1_cfg
4 10 R/W tbi_bucket1_lvl
5 14 R/W tbi_bucket2_cfg
6 18 R/W tbi_bucket2_lvl
7 1c R/W tbi_bucket3_cfg
8 20 R/W tbi_bucket3_lvl
9 24 R/W tbi_bucket4_cfg
a 28 R/W tbi_bucket4_lvl
b 2c R/W tbi_bucket5_cfg
c 30 R/W tbi_bucket5_lvl
d 34 R/W tbi_bucket6_cfg
e 38 R/W tbi_bucket6_lvl
f 3c R/W tbi_bucket7_cfg
10 40 R/W tbi_bucket7_lvl
11-1f 44-7c -  reserved

tbi_cr0
TBI control register 0 (CR0)

Writing to tbi_reset will reset the Token Bucket instance's internal state
machine and sets bucket_nempty ('1), shared ('0), s_environment('0) to their
reset values. Other fields of the control register are not changed. Token
levels of all buckets in the instance also stay unchanged.

When enabled, the instance updates each of its buckets from highest to lowest
bucket successively during each update cycle. Furthermore, it generates a
'tbi_cycle_event' to its corresponding gPEC at the start of every update cycle,
including one for the first cycle immediately after it was enabled.

Disabling the Token Bucket instance (!tbi_en) or changing the update rate
will reset the instance's internal state machine and set shared ('0) to its
reset value. Disabling the instance will also reset the bucket_nempty ('1) signals and
the environment signals (busy, decrement_request, decrement).
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00000
Address@gxc_token_bucket_instance1 : 0x07c00080
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
tbi_update_rate
Update rate of the Token Bucket instance
00 : 6400 ns
01 : 640  ns
10 : 64   ns
11 : Reserved
3 - 1 0
-
 reserved
0 "0"
tbi_en
Enables the Token Bucket instance


tbi_bucket0_cfg
TBI Bucket 0 Config Register (B0_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00004
Address@gxc_token_bucket_instance1 : 0x07c00084
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket0_lvl
TBI Bucket 0 Level Register (B0_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00008
Address@gxc_token_bucket_instance1 : 0x07c00088
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket1_cfg
TBI Bucket 1 Config Register (B1_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c0000c
Address@gxc_token_bucket_instance1 : 0x07c0008c
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket1_lvl
TBI Bucket 1 Level Register (B1_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00010
Address@gxc_token_bucket_instance1 : 0x07c00090
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket2_cfg
TBI Bucket 2 Config Register (B2_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00014
Address@gxc_token_bucket_instance1 : 0x07c00094
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket2_lvl
TBI Bucket 2 Level Register (B2_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00018
Address@gxc_token_bucket_instance1 : 0x07c00098
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket3_cfg
TBI Bucket 3 Config Register (B3_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c0001c
Address@gxc_token_bucket_instance1 : 0x07c0009c
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket3_lvl
TBI Bucket 3 Level Register (B3_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00020
Address@gxc_token_bucket_instance1 : 0x07c000a0
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket4_cfg
TBI Bucket 4 Config Register (B4_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00024
Address@gxc_token_bucket_instance1 : 0x07c000a4
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket4_lvl
TBI Bucket 4 Level Register (B4_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00028
Address@gxc_token_bucket_instance1 : 0x07c000a8
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket5_cfg
TBI Bucket 5 Config Register (B5_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c0002c
Address@gxc_token_bucket_instance1 : 0x07c000ac
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket5_lvl
TBI Bucket 5 Level Register (B5_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00030
Address@gxc_token_bucket_instance1 : 0x07c000b0
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket6_cfg
TBI Bucket 6 Config Register (B6_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00034
Address@gxc_token_bucket_instance1 : 0x07c000b4
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket6_lvl
TBI Bucket 6 Level Register (B6_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00038
Address@gxc_token_bucket_instance1 : 0x07c000b8
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.


tbi_bucket7_cfg
TBI Bucket 7 Config Register (B7_CFG).

This register is only updated after writing both the config and level register
of this bucket successively.

Reset values of all fields of this register are undefined ('X'), except for
the 'en' bit.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c0003c
Address@gxc_token_bucket_instance1 : 0x07c000bc
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 16 0x0
size
Upper bits of the bucket size (size[25:12], size [11:0] = 0)

Reset value is 'X'.
15 - 14 0
-
 reserved
13 - 4 0x0
inc
Number of tokens that will be added to the bucket
on every update cycle (see 'tbi_cr0.tbi_update_rate')

Reset value is 'X'.
3 0
-
 reserved
2 "0"
share
Enable sharing of excess tokens with other buckets

Excess tokens are shared with bucket number (n-1) % 8, where n is the
index of this bucket.

Tokens shared to buckets beneath this bucket will be added in the same
update cycle. Tokens shared from bucket 0 to bucket 7 will will be
delayed by 1 update cycle.

In normal usage, the 'share' bit of the lowest enabled bucket shall be
zero to avoid sharing of tokens back to the highest bucket (see MEF 10.3).

Reset value is 'X'.
1 "0"
cbs_en
Enable credit-based shaper (CBS) functionality

When enabled, the CBS logic controls when the bucket level may increment
and when it is reset depending on the corresponding bits in bucket_nempty,
pfifo_mask, pfifo_nempty and ENV.busy[n]:

CBS_LOGIC: always
  IF(bucket_nempty && pfifo_mask && ~pfifo_nempty && !ENV.busy[n])
    reset <= 1
  ELSE
    reset <= 0
    inc_en <= pfifo_mask

ENV.busy[n] is set using gpec_pfifo_cfg register from the bucket instance's
corresponding gPEC.

Reset value is 'X'.
0 "0"
en
Enable this bucket

When the bucket is enabled, the Token Bucket instance's state machine adds up
tokens from 'inc' + incoming tokens that were shared with this bucket. Excess
tokens may be shared with the next bucket depending on the 'sharing' flag.

A disabled bucket won't be added any tokens but it will always share
excess tokens recieved from other buckets with the next bucket, regardless
off the 'sharing' flag.


tbi_bucket7_lvl
TBI Bucket 7 Level Register (B7_LVL).

Writing this register will transfer the level together with
the last written bucket config to the bucket memory.
Other than indicated in the "Reset value" column the reset is 'X'.
R/W
0x00000000
Address@gxc_token_bucket_instance0 : 0x07c00040
Address@gxc_token_bucket_instance1 : 0x07c000c0
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 0 0x0
level
Current fill level of the bucket

Reset value is 'X'.



Base Address Area: gxc_gmac_regs, gxc_gmac0_regs, gxc_gmac1_regs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gmac_sr0
1 4 R/W gmac_sr1
2 8 R/W gmac_sr2
3 c R/W gmac_sr3
4 10 R/W gmac_sr4
5 14 R/W gmac_sr5
6 18 R/W gmac_sr6
7 1c R/W gmac_sr7
8 20 R/W gmac_sr8
9 24 R/W gmac_sr9
a 28 R/W gmac_sr10
b 2c R/W gmac_sr11
c 30 R/W gmac_sr12
d 34 R/W gmac_sr13
e 38 R/W gmac_sr14
f 3c R/W gmac_sr15
10 40 R/W gmac_wr0
11 44 R/W gmac_wr1
12 48 R/W gmac_wr2
13 4c R/W gmac_wr3
14 50 R/W gmac_wr4
15 54 R/W gmac_wr5
16 58 R/W gmac_wr6
17 5c R/W gmac_wr7
18 60 R/W gmac_wr8
19 64 R/W gmac_wr9
1a 68 R/W gmac_statcfg0
1b 6c R/W gmac_statcfg1
1c 70 R/W gmac_stat_bits
1d 74 R gmac_cmp0_status
1e 78 R gmac_cmp1_status
1f 7c R gmac_cmp2_status
20 80 R gmac_cmp_rx_status
21 84 R gmac_status_int
22 88 R/W gmac_status_mii
23 8c R/W gmac_status_miif
24 90 R/W gmac_config_mii
25 94 R/W gmac_debug_mii
26 98 R/W gmac_debug_sgmii
27 9c R/W gmac_lut_bits
28 a0 R/W gmac_rpu_wr0
29 a4 R/W gmac_rpu_wr1
2a a8 R/W gmac_rx_config
2b ac R/W gmac_rx_config_clock_handling
2c b0 R gmac_rx
2d b4 R gmac_rx2
2e b8 R gmac_rx_last4
2f bc R/W gmac_rx_count
30 c0 R/W gmac_rpu_count1
31 c4 R/W gmac_rpu_count2
32 c8 R gmac_cmp_rpucnt_status
33 cc R gmac_cmp_rxcrc_status
34 d0 R/W gmac_tpu_wr0
35 d4 R/W gmac_tpu_wr1
36 d8 R/W gmac_tx_config
37 dc R/W gmac_tx_config_clock_handling
38 e0 R/W gmac_tx
39 e4 R gmac_tx2
3a e8 W gmac_tx_toggle_en
3b ec R/W gmac_tx_count
3c f0 R/W gmac_tpu_count1
3d f4 R/W gmac_tpu_count2
3e f8 R gmac_cmp_tpucnt_status
3f fc -  reserved
40 100 R/W gmac_systime_msk
41 104 R/W gmac_systime_cmp
42 108 R gmac_systime
43 10c R gmac_counter
44 110 R gmac_systime_phy
45 114 R gmac_counter_phy
46 118 R/W gmac_rpu_pc
47 11c R/W gmac_tpu_pc
48 120 R/W gmac_urtx
49 124 W gmac_urx32
4a 128 R/W gmac_urtxe
4b 12c W gmac_urxe32
4c 130 R/W gmac_pm_mask0
4d 134 R/W gmac_pm_val0
4e 138 R/W gmac_pm_mask1
4f 13c R/W gmac_pm_val1
50 140 R/W gmac_pm_mask2
51 144 R/W gmac_pm_val2
52 148 R/W gmac_pm_mask3
53 14c R/W gmac_pm_val3
54-5f 150-17c -  reserved
60 180 R gmac_rpu_jmp_latch
61 184 R/W gmac_rx_crc_cfg
62 188 R/W gmac_rx_crc_polynomial
63 18c R/W gmac_rx_crc
64 190 R/W gmac_rx_crc32_cfg
65 194 R/W gmac_rx_crc32
66 198 R gmac_rpu_count1_2lsb_shift_val
67 19c R gmac_rpu_count2_2lsb_shift_val
68 1a0 W gmac_rx_frame_err_cnt
69 1a4 R gmac_rx_rpm_hit_num
6a 1a8 R gmac_rx_smd_hit_num
6b-6f 1ac-1bc -  reserved
70 1c0 R gmac_tpu_jmp_latch
71 1c4 R/W gmac_tx_crc_cfg
72 1c8 R/W gmac_tx_crc_polynomial
73 1cc R/W gmac_tx_crc
74 1d0 R/W gmac_tx_crc32_cfg
75 1d4 R/W gmac_tx_crc32
76-7f 1d8-1fc -  reserved

gmac_sr0
Shared Work Register 0 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01000
Address@gxc_gmac0_regs : 0x07d21000
Address@gxc_gmac1_regs : 0x07d61000
Bits Reset value Name Description
31 - 0 0x0
sr0
Shared Register


gmac_sr1
Shared Work Register 1 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01004
Address@gxc_gmac0_regs : 0x07d21004
Address@gxc_gmac1_regs : 0x07d61004
Bits Reset value Name Description
31 - 0 0x0
sr1
Shared Register


gmac_sr2
Shared Work Register 2 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01008
Address@gxc_gmac0_regs : 0x07d21008
Address@gxc_gmac1_regs : 0x07d61008
Bits Reset value Name Description
31 - 0 0x0
sr2
Shared Register


gmac_sr3
Shared Work Register 3 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0100c
Address@gxc_gmac0_regs : 0x07d2100c
Address@gxc_gmac1_regs : 0x07d6100c
Bits Reset value Name Description
31 - 0 0x0
sr3
Shared Register


gmac_sr4
Shared Work Register 4 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01010
Address@gxc_gmac0_regs : 0x07d21010
Address@gxc_gmac1_regs : 0x07d61010
Bits Reset value Name Description
31 - 0 0x0
sr4
Shared Register


gmac_sr5
Shared Work Register 5 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01014
Address@gxc_gmac0_regs : 0x07d21014
Address@gxc_gmac1_regs : 0x07d61014
Bits Reset value Name Description
31 - 0 0x0
sr5
Shared Register


gmac_sr6
Shared Work Register 6 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01018
Address@gxc_gmac0_regs : 0x07d21018
Address@gxc_gmac1_regs : 0x07d61018
Bits Reset value Name Description
31 - 0 0x0
sr6
Shared Register


gmac_sr7
Shared Work Register 7 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0101c
Address@gxc_gmac0_regs : 0x07d2101c
Address@gxc_gmac1_regs : 0x07d6101c
Bits Reset value Name Description
31 - 0 0x0
sr7
Shared Register


gmac_sr8
Shared Work Register 8 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01020
Address@gxc_gmac0_regs : 0x07d21020
Address@gxc_gmac1_regs : 0x07d61020
Bits Reset value Name Description
31 - 0 0x0
sr8
Shared Register


gmac_sr9
Shared Work Register 9 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01024
Address@gxc_gmac0_regs : 0x07d21024
Address@gxc_gmac1_regs : 0x07d61024
Bits Reset value Name Description
31 - 0 0x0
sr9
Shared Register


gmac_sr10
Shared Work Register 10 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01028
Address@gxc_gmac0_regs : 0x07d21028
Address@gxc_gmac1_regs : 0x07d61028
Bits Reset value Name Description
31 - 0 0x0
sr10
Shared Register


gmac_sr11
Shared Work Register 11 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0102c
Address@gxc_gmac0_regs : 0x07d2102c
Address@gxc_gmac1_regs : 0x07d6102c
Bits Reset value Name Description
31 - 0 0x0
sr11
Shared Register


gmac_sr12
Shared Work Register 12 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01030
Address@gxc_gmac0_regs : 0x07d21030
Address@gxc_gmac1_regs : 0x07d61030
Bits Reset value Name Description
31 - 0 0x0
sr12
Shared Register


gmac_sr13
Shared Work Register 13 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01034
Address@gxc_gmac0_regs : 0x07d21034
Address@gxc_gmac1_regs : 0x07d61034
Bits Reset value Name Description
31 - 0 0x0
sr13
Shared Register


gmac_sr14
Shared Work Register 14 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01038
Address@gxc_gmac0_regs : 0x07d21038
Address@gxc_gmac1_regs : 0x07d61038
Bits Reset value Name Description
31 - 0 0x0
sr14
Shared Register


gmac_sr15
Shared Work Register 15 accessible by all gMACs and gPECs
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0103c
Address@gxc_gmac0_regs : 0x07d2103c
Address@gxc_gmac1_regs : 0x07d6103c
Bits Reset value Name Description
31 - 0 0x0
sr15
Shared Register


gmac_wr0
gMAC internal Work Register 0
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01040
Address@gxc_gmac0_regs : 0x07d21040
Address@gxc_gmac1_regs : 0x07d61040
Bits Reset value Name Description
31 - 0 0x0
wr0
Work Register


gmac_wr1
gMAC internal Work Register 1
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01044
Address@gxc_gmac0_regs : 0x07d21044
Address@gxc_gmac1_regs : 0x07d61044
Bits Reset value Name Description
31 - 0 0x0
wr1
Work Register


gmac_wr2
gMAC internal Work Register 2
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01048
Address@gxc_gmac0_regs : 0x07d21048
Address@gxc_gmac1_regs : 0x07d61048
Bits Reset value Name Description
31 - 0 0x0
wr2
Work Register


gmac_wr3
gMAC internal Work Register 3
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0104c
Address@gxc_gmac0_regs : 0x07d2104c
Address@gxc_gmac1_regs : 0x07d6104c
Bits Reset value Name Description
31 - 0 0x0
wr3
Work Register


gmac_wr4
gMAC internal Work Register 4
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01050
Address@gxc_gmac0_regs : 0x07d21050
Address@gxc_gmac1_regs : 0x07d61050
Bits Reset value Name Description
31 - 0 0x0
wr4
Work Register


gmac_wr5
gMAC internal Work Register 5
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01054
Address@gxc_gmac0_regs : 0x07d21054
Address@gxc_gmac1_regs : 0x07d61054
Bits Reset value Name Description
31 - 0 0x0
wr5
Work Register


gmac_wr6
gMAC internal Work Register 6
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01058
Address@gxc_gmac0_regs : 0x07d21058
Address@gxc_gmac1_regs : 0x07d61058
Bits Reset value Name Description
31 - 0 0x0
wr6
Work Register


gmac_wr7
gMAC internal Work Register 7
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0105c
Address@gxc_gmac0_regs : 0x07d2105c
Address@gxc_gmac1_regs : 0x07d6105c
Bits Reset value Name Description
31 - 0 0x0
wr7
Work Register


gmac_wr8
gMAC internal Work Register 8
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01060
Address@gxc_gmac0_regs : 0x07d21060
Address@gxc_gmac1_regs : 0x07d61060
Bits Reset value Name Description
31 - 0 0x0
wr8
Work Register


gmac_wr9
gMAC internal Work Register 9
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01064
Address@gxc_gmac0_regs : 0x07d21064
Address@gxc_gmac1_regs : 0x07d61064
Bits Reset value Name Description
31 - 0 0x0
wr9
Work Register


gmac_statcfg0
Shared Config and Status Register of GMAC0:
This register is shared between all GMACs, all GPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 8..12 do not require write masks), but upper 16 bits can have completey independent read functionality.
If gxc_sys_ctrl-piomode is active, this will overwrite values of gpio* bits.
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01068
Address@gxc_gmac0_regs : 0x07d21068
Address@gxc_gmac1_regs : 0x07d61068
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
lmo_link_and_n_eld_bad_link
!eld_bad_link & link_mode_out_link
29 "0"
dr_err_or_crx_err_or_fcr_err
dr_err or crx_err or fcr_err are active
28 "0"
hdx1000
read only 1 GBit half duplex mode
hdx1000 = (link_mode_out_duplex==0) and (link_mode_out_speed==2)
27 "0"
link_mode_out_duplex
read only duplex status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_duplex
1: full duplex
0: half duplex
26 "0"
link_mode_out_link
read only link status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_link
1: link up
0: link down
25 - 24 "00"
link_mode_out_speed
read only speed status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_speed
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
11: undefined
23 "0"
utxe_empty
utxe_empty (UTXE_FIFO empty)
22 "0"
utxe_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
21 "0"
urxe_bit32
bit 32 at output of URXE FIFO
20 "0"
urxe_rdy
Received bytes are valid at output of URX_FIFO
19 "0"
utx_empty
utx_empty (UTX_FIFO empty)
18 "0"
utx_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
17 "0"
urx_bit32
bit 32 at output of URX FIFO
16 "0"
urx_rdy
Received bytes are valid at output of URX_FIFO
15 0
-
 reserved
14 "0"
eld_bad_link
link_status from enhanced link detection unit.
Reset by writing 1 to this bit, requires no write mask
13 "0"
utxe_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTXE_FIFO, requires no write mask
12 "0"
urxe_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URXE_FIFO, requires no write mask
11 "0"
utx_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTX_FIFO, requires no write mask
10 "0"
urx_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URX_FIFO, requires no write mask
9 - 8 0
-
 reserved
7 "0"
gpio3_oe
GPIO3 pin output enable
6 "0"
gpio2_oe
GPIO2 pin output enable
5 "0"
gpio1_oe
GPIO1 pin output enable
4 "0"
gpio0_oe
GPIO0 pin output enable
3 "0"
gpio3
write: GPIO3 pin output: not used
read: GPIO3 pin input
2 "0"
gpio2
write: GPIO2 pin output
read: GPIO2 pin input:  connected to link (controls phy_led),
1 "0"
gpio1
write: GPIO1 pin output
read: GPIO1 pin input:  connected to rxsdf (samples systime),
0 "0"
gpio0
write: GPIO0 pin output
read: GPIO0 pin input:  connected to txsdf (samples systime)


gmac_statcfg1
Shared Config and Status Register of GMAC1:
This register is shared between all GMACs, all GPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 8..12 do not require write masks), but upper 16 bits can have completey independent read functionality.
If gxc_sys_ctrl-piomode is active, this will overwrite values of gpio* bits.
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0106c
Address@gxc_gmac0_regs : 0x07d2106c
Address@gxc_gmac1_regs : 0x07d6106c
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
lmo_link_and_n_eld_bad_link
!eld_bad_link & link_mode_out_link
29 "0"
dr_err_or_crx_err_or_fcr_err
dr_err or crx_err or fcr_err are active
28 "0"
hdx1000
read only 1 GBit half duplex mode
hdx1000 = (link_mode_out_duplex==0) and (link_mode_out_speed==2)
27 "0"
link_mode_out_duplex
read only duplex status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_duplex
1: full duplex
0: half duplex
26 "0"
link_mode_out_link
read only link status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_link
1: link up
0: link down
25 - 24 "00"
link_mode_out_speed
read only speed status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_speed
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
11: undefined
23 "0"
utxe_empty
utxe_empty (UTXE_FIFO empty)
22 "0"
utxe_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
21 "0"
urxe_bit32
bit 32 at output of URXE FIFO
20 "0"
urxe_rdy
Received bytes are valid at output of URX_FIFO
19 "0"
utx_empty
utx_empty (UTX_FIFO empty)
18 "0"
utx_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
17 "0"
urx_bit32
bit 32 at output of URX FIFO
16 "0"
urx_rdy
Received bytes are valid at output of URX_FIFO
15 0
-
 reserved
14 "0"
eld_bad_link
link_status from enhanced link detection unit.
Reset by writing 1 to this bit, requires no write mask
13 "0"
utxe_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTXE_FIFO, requires no write mask
12 "0"
urxe_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URXE_FIFO, requires no write mask
11 "0"
utx_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTX_FIFO, requires no write mask
10 "0"
urx_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URX_FIFO, requires no write mask
9 - 8 0
-
 reserved
7 "0"
gpio3_oe
GPIO3 pin output enable
6 "0"
gpio2_oe
GPIO2 pin output enable
5 "0"
gpio1_oe
GPIO1 pin output enable
4 "0"
gpio0_oe
GPIO0 pin output enable
3 "0"
gpio3
write: GPIO3 pin output: not used
read: GPIO3 pin input:  might be used as spis-mosi or spim-miso
2 "0"
gpio2
write: GPIO2 pin output: might be used as spim_clk
read: GPIO2 pin input:  connected to link (controls phy_led),
                         might be used as pb-din or spis-clk
1 "0"
gpio1
write: GPIO1 pin output: might be used as pb-dv spim-cs
read: GPIO1 pin input:  connected to rxsdf (samples systime),
                         might be used as spis-cs
0 "0"
gpio0
write: GPIO0 pin output: might be used as pb-dout or spis-miso or spim-mosi
read: GPIO0 pin input:  connected to txsdf (samples systime)


gmac_stat_bits
stat_bits:
These bits can be accessed by all gMACs and gPECs in parallel, all accesses with write bit mask.
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01070
Address@gxc_gmac0_regs : 0x07d21070
Address@gxc_gmac1_regs : 0x07d61070
Bits Reset value Name Description
31 - 16 0x0
write_mask
write mask of bits 15..0
15 - 0 0x0
val
Global stat_bits[15:0]


gmac_cmp0_status
gMAC Compare0 Status Register
R
Address@gxc_gmac_regs : 0x07c01074
Address@gxc_gmac0_regs : 0x07d21074
Address@gxc_gmac1_regs : 0x07d61074
Bits Name Description
31 cnt2_tpu_z
tpu_count2 = 0
30 cnt1_tpu_z
tpu_count1 = 0
29 cnt2_rpu_z
rpu_count2 = 0
28 cnt1_rpu_z
rpu_count1 = 0
27 cnt_tx_z
count_tx = 0
26 cnt_rx_z
count_rx = 0
25 wr9_z
1: work register 9 equals 0
24 wr8_z
1: work register 8 equals 0
23 wr7_z
1: work register 7 equals 0
22 wr6_z
1: work register 6 equals 0
21 wr5_z
1: work register 5 equals 0
20 wr4_z
1: work register 4 equals 0
19 wr3_z
1: work register 3 equals 0
18 wr2_z
1: work register 2 equals 0
17 wr1_z
1: work register 1 equals 0
16 wr0_z
1: work register 0 equals 0
15 sr15_z
sr15 = 0
14 sr14_z
sr14 = 0
13 sr13_z
sr13 = 0
12 sr12_z
sr12 = 0
11 sr11_z
sr11 = 0
10 sr10_z
sr10 = 0
9 sr9_z
sr9 = 0
8 sr8_z
sr8 = 0
7 sr7_z
sr7 = 0
6 sr6_z
sr6 = 0
5 sr5_z
sr5 = 0
4 sr4_z
sr4 = 0
3 sr3_z
sr3 = 0
2 sr2_z
sr2 = 0
1 sr1_z
sr1 = 0
0 sr0_z
sr0 = 0


gmac_cmp1_status
gMAC Compare1 Status Register
R
Address@gxc_gmac_regs : 0x07c01078
Address@gxc_gmac0_regs : 0x07d21078
Address@gxc_gmac1_regs : 0x07d61078
Bits Name Description
31 - 28 -
 reserved
27 counter32
compare of 32-bit counter with systime_cmp(value) and systime_msk:
(1: compare this bit position, 0: ignore this bit position)
26 systime32
compare of 32-bit systime with systime_cmp(value) and systime_msk:
(1: compare this bit position, 0: ignore this bit position)
25 counter64
compare of 64-bit counter with wr6,wr2(value) and wr7,wr3(mask):
{wr7,wr3} define, which bits of systime and {wr6,wr2} are to be compared
(1: compare this bit position, 0: ignore this bit position)
24 systime64
compare of 64-bit systime with wr6,wr2(value) and wr7,wr3(mask):
{wr7,wr3} define, which bits of systime and {wr6,wr2} are to be compared
(1: compare this bit position, 0: ignore this bit position)
23 txcnt_wr5_b3
1: tx_count equals {24'd0,wr5[31:24]}, no ALU-Flag, calculated every cycle
22 txcnt_wr5_b2
1: tx_count equals {24'd0,wr5[23:16]}, no ALU-Flag, calculated every cycle
21 txcnt_wr5_b1
1: tx_count equals {24'd0,wr5[15:8]},  no ALU-Flag, calculated every cycle
20 txcnt_wr5_b0
1: tx_count equals {24'd0,wr5[7:0]},   no ALU-Flag, calculated every cycle
19 txcnt_wr4_b3
1: tx_count equals {24'd0,wr4[31:24]}, no ALU-Flag, calculated every cycle
18 txcnt_wr4_b2
1: tx_count equals {24'd0,wr4[23:16]}, no ALU-Flag, calculated every cycle
17 txcnt_wr4_b1
1: tx_count equals {24'd0,wr4[15:8]},  no ALU-Flag, calculated every cycle
16 txcnt_wr4_b0
1: tx_count equals {24'd0,wr4[7:0]},   no ALU-Flag, calculated every cycle
15 rxcnt_wr1_b3
1: rx_count equals {24'd0,wr1[31:24]}, no ALU-Flag, calculated every cycle
14 rxcnt_wr1_b2
1: rx_count equals {24'd0,wr1[23:16]}, no ALU-Flag, calculated every cycle
13 rxcnt_wr1_b1
1: rx_count equals {24'd0,wr1[15:8]},  no ALU-Flag, calculated every cycle
12 rxcnt_wr1_b0
1: rx_count equals {24'd0,wr1[7:0]},   no ALU-Flag, calculated every cycle
11 rxcnt_wr0_b3
1: rx_count equals {24'd0,wr0[31:24]}, no ALU-Flag, calculated every cycle
10 rxcnt_wr0_b2
1: rx_count equals {24'd0,wr0[23:16]}, no ALU-Flag, calculated every cycle
9 rxcnt_wr0_b1
1: rx_count equals {24'd0,wr0[15:8]},  no ALU-Flag, calculated every cycle
8 rxcnt_wr0_b0
1: rx_count equals {24'd0,wr0[7:0]},   no ALU-Flag, calculated every cycle
7 txcnt_wr7
1: tx_count equals wr7, no ALU-Flag, calculated every cycle
6 txcnt_wr6
1: tx_count equals wr6, no ALU-Flag, calculated every cycle
5 txcnt_wr5
1: tx_count equals wr5, no ALU-Flag, calculated every cycle
4 txcnt_wr4
1: tx_count equals wr4, no ALU-Flag, calculated every cycle
3 rxcnt_wr3
1: rx_count equals wr3, no ALU-Flag, calculated every cycle
2 rxcnt_wr2
1: rx_count equals wr2, no ALU-Flag, calculated every cycle
1 rxcnt_wr1
1: rx_count equals wr1, no ALU-Flag, calculated every cycle
0 rxcnt_wr0
1: rx_count equals wr0, no ALU-Flag, calculated every cycle


gmac_cmp2_status
gMAC Compare2 Status Register
Change note: After netx22xx_mpw tpm_hit*_sr*_nz status bits are added
R
Address@gxc_gmac_regs : 0x07c0107c
Address@gxc_gmac0_regs : 0x07d2107c
Address@gxc_gmac1_regs : 0x07d6107c
Bits Name Description
31 - 22 -
 reserved
21 wr6_se_wr7
1: wr6 <= wr7
20 wr4_se_wr5
1: wr4 <= wr5
19 wr2_se_wr3
1: wr2 <= wr3
18 wr0_se_wr1
1: wr0 <= wr1
17 rpm2_hit2or3
pattern/mask 2 or pattern 3 matches receive data2
16 rpm2_hit0or1
pattern/mask 0 or pattern 1 matches receive data2
15 rpm2_hit3
pattern/mask3 match receive data2
14 rpm2_hit2
pattern/mask2 match receive data2
13 rpm2_hit1
pattern/mask1 match receive data2
12 rpm2_hit0
pattern/mask0 match receive data2
11 tpm_hit2or3
pattern/mask 2 or pattern 3 matches transmit data
10 tpm_hit0or1
pattern/mask 0 or pattern 1 matches transmit data
9 rpm_hit2or3
pattern/mask 2 or pattern 3 matches receive data
8 rpm_hit0or1
pattern/mask 0 or pattern 1 matches receive data
7 tpm_hit3
pattern/mask3 match transmit data
6 tpm_hit2
pattern/mask2 match transmit data
5 tpm_hit1
pattern/mask1 match transmit data
4 tpm_hit0
pattern/mask0 match transmit data
3 rpm_hit3
pattern/mask3 match receive data
2 rpm_hit2
pattern/mask2 match receive data
1 rpm_hit1
pattern/mask1 match receive data
0 rpm_hit0
pattern/mask0 match receive data


gmac_cmp_rx_status
gMAC Compare RX Status Register
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c01080
Address@gxc_gmac0_regs : 0x07d21080
Address@gxc_gmac1_regs : 0x07d61080
Bits Name Description
31 -
 reserved
30 rx2_b3_eq_01_02_03_07_08_09_0d
rx2[31:24] == 8'h01 or rx2[31:24] == 8'h02 or rx2[31:24] == 8'h03 or rx2[31:24] == 8'h07 or rx2[31:24] == 8'h08 or rx2[31:24] == 8'h09 or rx2[31:24] == 8'h0d (match Ecat.HiAddr++)
29 rx2_eq_450008
rx2[23:0] == 24'h450008
28 rx2_w1_eq_feb6
rx2[31:16] == 16'hfeb6
27 rx2_w1_eq_a488
rx2[31:16] == 16'ha488
26 rx2_w1_eq_0081
rx2[31:16] == 16'h0081
25 rx_b3_eq_01_02_03_07_08_09_0d
rx[31:24] == 8'h01 or rx[31:24] == 8'h02 or rx[31:24] == 8'h03 or rx[31:24] == 8'h07 or rx[31:24] == 8'h08 or rx[31:24] == 8'h09 or rx[31:24] == 8'h0d (match Ecat.HiAddr++)
24 rx_eq_450008
rx[23:0] == 24'h450008
23 rx_w1_eq_feb6
rx[31:16] == 16'hfeb6
22 rx_w1_eq_a488
rx[31:16] == 16'ha488
21 rx_w1_eq_0081
rx[31:16] == 16'h0081
20 rx_b3_is_smd
rx[31:24] is any of d5, 07, 19, e6, 4c, 7f, b3, 61, 52, 9e, 2a
19 rx_b3_eq_0e
rx[31:24] == 8'h0e (False Carrier)
18 rx_b3_eq_1f
rx[31:24] == 8'h1f (Carrier Extend Error)
17 rx_b3_eq_0f
rx[31:24] == 8'h0f (Carrier Extend)
16 rx_b3_eq_ff
rx[31:24] == 8'hff (Carrier Sense)
15 rx_b3_eq_61_52_9e_2a
rx[31:24] == 8'h61 or rx[31:24] == 8'h52 or rx[31:24] == 8'h9e or rx[31:24] == 8'h2a (SMD-Cx)
14 rx_b3_eq_e6_4c_7f_b3
rx[31:24] == 8'he6 or rx[31:24] == 8'h4c or rx[31:24] == 8'h7f or rx[31:24] == 8'hb3 (SMD-Sx)
13 rx_b3_eq_d5_07_19
rx[31:24] == 8'hd5 or rx[31:24] == 8'h07 or rx[31:24] == 8'h19 (SMD-E or SMD-V or SMD-R)
12 rx_b3_eq_07_19
rx[31:24] == 8'h07 or rx[31:24] == 8'h19 (SMD-V or SMD-R)
11 rx_b3_eq_2a
rx[31:24] == 8'h2a (SMD-C3)
10 rx_b3_eq_9e
rx[31:24] == 8'h9e (SMD-C2)
9 rx_b3_eq_52
rx[31:24] == 8'h52 (SMD-C1)
8 rx_b3_eq_61
rx[31:24] == 8'h61 (SMD-C0)
7 rx_b3_eq_b3
rx[31:24] == 8'hb3 (SMD-S3 or FRAG_CNT3)
6 rx_b3_eq_7f
rx[31:24] == 8'h7f (SMD-S2 or FRAG_CNT2)
5 rx_b3_eq_4c
rx[31:24] == 8'h4c (SMD-S1 or FRAG_CNT1)
4 rx_b3_eq_e6
rx[31:24] == 8'he6 (SMD-S0 or FRAG_CNT0)
3 rx_b3_eq_19
rx[31:24] == 8'h19 (SMD-R)
2 rx_b3_eq_07
rx[31:24] == 8'h07 (SMD-V)
1 rx_b3_eq_d5
rx[31:24] == 8'hd5 (SMD-E)
0 rx_b3_eq_55
rx[31:24] == 8'h55 (Preamble)


gmac_status_int
gMAC Status Internal Register
R
Address@gxc_gmac_regs : 0x07c01084
Address@gxc_gmac0_regs : 0x07d21084
Address@gxc_gmac1_regs : 0x07d61084
Bits Name Description
31 utxe32_nxt
bit 33 of utxe fifo (nxt)
30 utx32_nxt
bit 33 of utx fifo (nxt)
29 utxe32_last
bit 33 of utxe fifo (last)
28 utx32_last
bit 33 of utx fifo (last)
27 utxe32or31_nxt
bit 33 or bit 32 of utxe fifo set (nxt)
26 utx32or31_nxt
bit 33 or bit 32 of utx fifo set (nxt)
25 -
 reserved
24 tx_crc_ok_wr9
compare of tx_crc with wr9
23 - 12 -
 reserved
11 zero
always 0, used by gmacass
10 -
 reserved
9 btran
byte/nibble transmitted (active for 1 cc)
8 brec
byte/nibble received (active for 1 cc)
7 tpu_ovf
TPU ovf flag
6 tpu_neg
TPU neg flag
5 tpu_zero
TPU zero flag
4 tpu_carry
TPU carry flag
3 rpu_ovf
RPU ovf flag
2 rpu_neg
RPU neg flag
1 rpu_zero
RPU zero flag
0 rpu_carry
RPU carry flag


gmac_status_mii
gMAC MII receive status register before MII-FIFO and before nibble2byte conversion.
All bits are read only, writing 1 to *_was_here resets these bits.
Note: This register has a write pipeline delay of 1 clock cycle.
Change note: After netx22xx_mpw there is only one tx_swap signal (tx_swap = tx_swap0 or tx_swap1)
Change note: After netx22xx_mpw some swap bugs are cleaned up. External SDF and SGMII signal are now swapped. (Issue J210051-593/593/596)
Change note: After netx22xx_mpw col,crs,crs_and_txen signals are generated in gmac_io_mux symmetrical for all ext_modes (before swapping)
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01088
Address@gxc_gmac0_regs : 0x07d21088
Address@gxc_gmac1_regs : 0x07d61088
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 -
tx_swap
Swap TX signals between gMACs:
If enabled, output signals from other GMAC (RGMII_TXCLK, TXD, TXEN, TXER) are output at this GMAC's IOs.
Also MII_TXCLK and COL/CRS input signals of other GMAC are driven by this GMAC's IOs.
This signal is a read only version of gxc_sys_ctrl.swap.tx_swap0/1.
28 -
rx_swap
Swap RX signals between gMACs:
If enabled, input signals from other GMAC's IOs (RXCLK, RXD, RXDV, RXER) are used in this GMAC.
This signal is a read only version of gxc_sys_ctrl.swap.rx_swap0/1.
27 0
-
 reserved
26 "0"
dr_err_or_crx_err_or_fcr_err_was_here
dr_err_was_here or crx_err_was_here or fcr_err was here are active
25 "0"
crx_err_or_fcr_err_was_here
crx_err_was_here or fcr_err was here are active
24 "0"
dr_err_or_crx_err_was_here
dr_err_was_here or crx_err was here are active
23 0
-
 reserved
22 "0"
dr_err_or_crx_err_or_fcr_err
dr_err or crx_err or fcr_err are active
21 "0"
crx_err_or_fcr_err
crx_err or fcr_err are active
20 "0"
dr_err_or_crx_err
dr_err or crx_err are active
19 "0"
invalid_cg
invalid code goup (debug only signal)
Hard error if signals are found that cannot be generated by the PHY.
rmii mode: always 0 (s. debug_mii-rmii_protocol_error)
mii mode: !rx_dv & rxerr & (rxd <> 4'he)
rgmii_10_100 mode: !rx_dv & rxerr & (rxd <> 4'h[e,f])
rgmii_1G mode: !rx_dv & rxerr & (rxd <> 8'h[ff,0e,0f,1f])
sgmii_10_100 mode: !rx_dv & rxerr & (rxd <> 4'h[e,f])
sgmii_1G mode: !rx_dv & rxerr & (rxd <> 8'h[ff,0e,0f,1f])
Note: In byte-wise mode this signal is generated per nibble. There is no nibble2byte collection. Better use invalid_cg_was_here.
18 "0"
crs_and_txen
crs & txen
rmii mode: !duplex & crs & tx_en
mii mode: !duplex & crs & tx_en
rgmii_10_100 mode: !duplex & crs & tx_en
rgmii_1G mode: !duplex & crs & (tx_en | (tx_err & (tx_d in 8'h[0f,1f])))
sgmii_10_100 mode: !duplex & crs & tx_en
sgmii_1G mode: !duplex & crs & (tx_en | (tx_err & (tx_d in 8'h[0f,1f])))
Note: In byte-wise mode this signal is generated per nibble. There is no nibble2byte collection.
17 "0"
col
Collision
rmii mode: !duplex & crs & tx_en
mii mode: from pin
rgmii_10_100 mode: !duplex & crs & tx_en
rgmii_1G mode: !duplex & crs & (tx_en | (tx_err & (tx_d in 8'h[0f,1f])))
sgmii mode: from SGMII-PHY
Note: In byte-wise mode this signal is generated per nibble. There is no nibble2byte collection.
16 "0"
crs
Carrier Sense
rmii mode: from pin (crsdv)
mii mode: from pin
rgmii_10_100 mode: rx_dv | (rx_err & (rx_d in 4'h[f,e]))
rgmii_1G mode: rx_dv | (rx_err & (rx_d in 8'h[ff,0e,0f,1f]))
sgmii mode: from SGMII-PHY
Note: In byte-wise mode this signal is generated per nibble. There is no nibble2byte collection.
15 "0"
invalid_cg_was_here
invalid code group was here:
Set with invalid_cg.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
14 "0"
crs_and_txen_was_here
crs_and_txen was here:
Set with crs_and_txen.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
13 "0"
col_was_here
col was here:
Useful, if col needs to be checked at end of frame.
Set with col.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
12 "0"
crs_was_here
crs was here:
Useful, if crs needs to be checked at end of frame.
Set with crs.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
11 "0"
fcr_err_was_here
false carrier indication was here:
Set with fcr_err.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
10 "0"
crx_err_was_here
carrier extend error was here:
Useful, if crx_err needs to be checked at end of carrier extension.
Set with crx_err.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
9 "0"
dr_err_was_here
data reception error was here:
Useful, if dr_err needs to be checked at end of frame.
Set with dr_err.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
8 "0"
rx_err_was_here
rx_err was here:
Useful, if rx_err needs to be checked at end of frame.
Set with rx_err.
Reset by writing 1 to this bit or at start of next frame if rx_config.autoclear_status is active.
7 "0"
crx_err
carrier extend error
rmii mode: 0 (n/a)
mii mode: 0 (n/a)
rgmii_10_100 mode: 0 (n/a)
rgmii_1G mode: !rx_dv & rx_err & rxd=8'h1f
sgmii_10_100 mode: 0 (n/a)
sgmii_1G mode: !rx_dv & rx_err & rxd=8'h1f
6 "0"
crx
carrier extend
rmii mode: 0 (n/a)
mii mode: 0 (n/a)
rgmii_10_100 mode: 0 (n/a)
rgmii_1G mode: !rx_dv & rx_err & rxd=8'h0f
sgmii_10_100 mode: 0 (n/a)
sgmii_1G mode: !rx_dv & rx_err & rxd=8'h0f
5 "0"
fcr_err
false carrier indication
rmii mode: false carrier frame detected, data set to rxd=e,rx_dv=0.rx_err=1
mii_nibble mode: !rx_dv & rx_err & rxd=4'he
mii_byte mode: (!rx_dv[lower_nibble] & rx_err[lower_nibble] & rxd[lower_nibble]=4'he) | (!rx_dv[upper_nibble] & rx_err[upper_nibble] & rxd[upper_nibble]=4'he)
rgmii_10_100_nibble mode: !rx_dv & rx_err & rxd=4'he (nibble wise)
rgmii_10_100_byte mode: (!rx_dv[lower_nibble] & rx_err[lower_nibble] & rxd[lower_nibble]=4'he) | (!rx_dv[upper_nibble] & rx_err[upper_nibble] & rxd[upper_nibble]=4'he)
rgmii_1G mode: !rx_dv & rx_err & rxd=8'h0e
sgmii_10_100_nibble mode: !rx_dv & rx_err & rxd=4'he (nibble wise)
sgmii_10_100_byte mode: (!rx_dv[lower_nibble] & rx_err[lower_nibble] & rxd[lower_nibble]=4'he) | (!rx_dv[upper_nibble] & rx_err[upper_nibble] & rxd[upper_nibble]=4'he)
sgmii_1G mode: !rx_dv & rx_err & rxd=8'h0e
4 "0"
dr_err
data reception error
rmii_10_100_nibble mode: rx_dv & rx_err (nibble wise)
rmii_10_100_byte mode: (rx_dv[lower_nibble] & rx_err[lower_nibble]) | (rx_dv[upper_nibble] & rx_err[upper_nibble])
mii_10_100_nibble mode: rx_dv & rx_err (nibble wise)
mii_10_100_byte mode: (rx_dv[lower_nibble] & rx_err[lower_nibble]) | (rx_dv[upper_nibble] & rx_err[upper_nibble])
rgmii_10_100_nibble mode: rx_dv & rx_err (nibble wise)
rgmii_10_100_byte mode: (rx_dv[lower_nibble] & rx_err[lower_nibble]) | (rx_dv[upper_nibble] & rx_err[upper_nibble])
rgmii_1G mode: rx_dv & rx_err (byte wise)
sgmii_10_100_nibble mode: rx_dv & rx_err (nibble wise)
sgmii_10_100_byte mode: (rx_dv[lower_nibble] & rx_err[lower_nibble]) | (rx_dv[upper_nibble] & rx_err[upper_nibble])
sgmii_1G mode: rx_dv & rx_err (byte wise)
3 "0"
v_ne
rx_dv & !rx_err
2 "0"
nv_ne
!rx_dv & !rx_err
1 "0"
rx_err
rmii mode: from pin
mii mode: from pin
rgmii_10_100_nibble mode: rx_err (nibble wise)
rgmii_10_100_byte mode: rx_err[lower_nibble] | rx_err[upper_nibble] (1 in case of single nibble errors)
rgmii_1G mode: rx_err (byte wise)
sgmii_10_100_nibble mode: rx_err (nibble wise)
sgmii_10_100_byte mode: rx_err[lower_nibble] | rx_err[upper_nibble] (1 in case of single nibble errors)
sgmii_1G mode: rx_err (byte wise)
0 "0"
rx_dv
rmii mode: from pin (crsdv)
mii mode: from pin
rgmii_10_100_nibble mode: rx_dv (nibble wise)
rgmii_10_100_byte mode: rx_dv[lower_nibble] & rx_dv[upper_nibble] (0 in case of additional nibble)
rgmii_1G mode: rx_dv (byte wise)
sgmii_10_100_nibble mode: rx_dv (nibble wise)
sgmii_10_100_byte mode: rx_dv[lower_nibble] & rx_dv[upper_nibble] (0 in case of additional nibble)
sgmii_1G mode: rx_dv (byte wise)


gmac_status_miif
gMAC MII receive status register after MII-FIFO
All bits are read only, writing 1 to miif_error or miif_short_ifg has reset funtionality.
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0108c
Address@gxc_gmac0_regs : 0x07d2108c
Address@gxc_gmac1_regs : 0x07d6108c
Bits Reset value Name Description
31 "0"
miif_error
Any error at MII-FIFO occured.
Any error can be miif_short_dv, miif_unfl or miif_ovfl.(not miif_short_ifg)
Reset by setting gmac_rx_config-rx_fifo_depth=0 or writing to status_miif-miif_error (will also reset MII-FIFO).
30 "0"
miif_unfl
MII-FIFO underflow.
This bit is read only.
Reset by setting gmac_rx_config-rx_fifo_depth=0 or writing to status_miif-miif_error (will also reset MII-FIFO).
29 "0"
miif_ovfl
MII-FIFO overflow.
This bit is read only.
Reset by setting gmac_rx_config-rx_fifo_depth=0 or writing to status_miif-miif_error (will also reset MII-FIFO).
28 "0"
miif_short_dv
MII-FIFO error:
rx_dv gets inactive before FIFO reached fill_level.
This leads to directly output data from FIFO and finish frame.
This bit is read only.
Reset by setting gmac_rx_config-rx_fifo_depth=0 or writing to status_miif-miif_error (will also reset MII-FIFO).
27 - 25 0
-
 reserved
24 "0"
miif_short_ifg
MII-FIFO debug status:
rx_dv gets active before FIFO is empty from previous frame.
This leads to ignoring data until FIFO is empty and the next frame is finished (next frame will be skipped).
This error bit is not part of miif_error, as actual frame might be okay.
This bit is read only.
Reset by writing to this bit or at FIFO reset (setting gmac_rx_config-rx_fifo_depth=0 or writing to status_miif-miif_error).
23 - 21 0
-
 reserved
20 "0"
miif_dr_err_or_crx_err
miif_dr_err or miif_crx_err are active
19 "0"
miif_wr_state_in_frame
MII-FIFO debug status: Write state machine is in state 'in_frame'.
18 "0"
miif_rd_state_wait_for_fifo_empty
MII-FIFO debug status: Read state machine is in state 'wait_for_fifo_empty'.
17 "0"
miif_rd_state_frame_data
MII-FIFO debug status: Read state machine is in state 'frame_data'.
16 "0"
miif_rd_state_fifo_ramp_up
MII-FIFO debug status: Read state machine is in state 'fifo_ramp_up'.
15 "0"
miif_rd_state_wait_for_frame
MII-FIFO debug status: Read state machine is in state 'wait_for_frame'.
14 - 9 0
-
 reserved
8 "0"
miif_not_empty
MII-FIFO is not empty:
FIFO is automatically filled, if miif_rx_dv=1.
FIFO is no longer filled, if miif_rx_dv=miif_rx_er=0.
This bit gets active, if FIFO contains any data (fill_level != 0).
7 "0"
miif_crx_err
carrier extend error (only exists in GMII modes)
rgmii_1G mode: !miif_rx_dv & miif_rx_err & miif_rxd=8'h1f
rgmii_10_100 mode: 0 (n/a)
mii mode: 0 (n/a)
gmii_1G mode: !miif_rx_dv & miif_rx_err & miif_rxd=8'h1f
gmii_10_100 mode: 0 (n/a)
6 "0"
miif_crx
carrier extend (only exists in GMII modes)
rgmii_1G mode: !miif_rx_dv & miif_rx_err & miif_rxd=8'h0f
rgmii_10_100 mode: 0 (n/a)
mii mode: 0 (n/a)
gmii_1G mode: !miif_rx_dv & miif_rx_err & miif_rxd=8'h0f
gmii_10_100 mode: 0 (n/a)
5 0
-
 reserved
4 "0"
miif_dr_err
data reception error
miif_rx_dv=1 & miif_rx_err=1
3 "0"
miif_v_ne
miif_rx_dv & !miif_rx_err
2 "0"
miif_nv_ne
!miif_rx_dv & !miif_rx_err
1 "0"
miif_rx_err
rx_err signal at output of MII-FIFO
0 "0"
miif_rx_dv
data valid signal at output of MII-FIFO


gmac_config_mii
gMAC MII transmit config register
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01090
Address@gxc_gmac0_regs : 0x07d21090
Address@gxc_gmac1_regs : 0x07d61090
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 "0"
hgmii_tx_idle_insert_k_cmd
pulse to insert one additional k28.5 code in next idle ordered set (causes re-sync on remote side!)
Might be used some time after insertion of a tx_dribble_nibble to align the idle pattern.
5 "0"
hgmii_tx_realign_cmd
pulse to re-align TX serializer sampling point to center of symbol (should be done after tx_td rate was changed)
tx_td must get active all 4 (20 in 100MBit) cycles. If not, automatic resync will happen in HSGMII
4 "0"
hgmii_mr_main_reset_cmd
pulse to start main reset
reset according to FX-standard
3 "0"
hgmii_mr_restart_an_cmd
pulse to restart auto negotiation
2 "0"
tx_dribble_nibble
Send dribble nibble
Only used in 8Bit 10/100Mbit xMII modes, synchronized to mii_tx_clk.
If set, second nibble has tx_en=0.
Note: This bit is only useful, if tx_en=1 (otherwise second nibble is already 0).
1 "0"
tx_err
tx error
Switches TXERR pad, synchronized to tx_clk.
0 "0"
tx_en
tx enable:
Switches TXEN pad, synchronized to tx_clk.


gmac_debug_mii
gMAC xMII debug register:
This register collects status bits of xMII (MII, RMII, RGMII, SGMII) related functionalities.
All bits are read only, writing 1 to a position resets this bit.
If rx_config.autoclear_error is set, most of these status bits are reset at start of next frame (see comment at bit description).
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01094
Address@gxc_gmac0_regs : 0x07d21094
Address@gxc_gmac1_regs : 0x07d61094
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
rgmii_warning_rx_data_not_repeated
data bits change at falling edge of rxclk (only in RGMII-10/100 mode)
16 "0"
rmii_warning_direct_rxdv
warning if frame starts without rxd=2'b00 (or 2'b11).
Note: This bit is not reset at start of frame, reset manually by writing to this bit.
15 "0"
rmii_warning_10M_resync
warning if 10Mbit RMII frame start resyncs 10x counter
Note: This bit is not reset at start of frame, reset manually by writing to this bit.
14 "0"
rmii_warning_misaligned_sof
warning if frame starts at odd halfnibble, 1 halfnibble will be dropped for sync
Note: This bit is not reset at start of frame, reset manually by writing to this bit.
13 "0"
rmii_warning_misaligned_fc
warning if false carrier starts at odd halfnibble, 1 halfnibble will be dropped for sync
12 "0"
rmii_error_10M_not_repeated
error if in 10Mbit RMII data and err are not 10x repeated
11 "0"
rmii_error_protocol
Error from RMII PHY detected, active if in:
- FRAME_STATE_CRS(crsdv=1 & rxdv=0): rxd=2'b11
- FRAME_STATE_FALSE_CARRIER: rxd<>2'b10
10 "0"
rmii_error_short_crsdv
error if crsdv goes low before sfd found
9 "0"
rmii_error_unaligned_eof
error if data frame finishes at odd halfnibble
8 "0"
rmii_error_unaligned_eo_fc
error if false carrier frame finishes at odd halfnibble
7 - 6 0
-
 reserved
5 "0"
misaligned_sof
data_valid gets active in misaligned nibble relative to previous frame
4 "0"
misaligned_smd
SMD is not aligned to start of frame
3 "0"
invalid_smd
SMD is not one of: d5, 07, 19, e6, 4c, 7f, b3, 61, 52, 9e, 2a
2 "0"
short_preamble
rxdv goes low or rxer goes high, before SMD was found
1 "0"
dribble_nibble
frame ends at non-byte border
0 "0"
smd_found
Start Mpacket Delimiter (SMD) found
one of d5, 07, 19, e6, 4c, 7f, b3, 61, 52, 9e, 2a


gmac_debug_sgmii
gMAC SGMII debug register:
This register collects bits of SGMII related functionalities.
Note: These inputs from internal SGMII PHY are swapped according to status_mii-rx_swap.
All bits are read only, writing 1 to a position resets this bit in case of "pulse" bits.
Note: This register has a write pipeline delay of 1 clock cycle.
Change note: After netx22xx these signals are also swapped
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01098
Address@gxc_gmac0_regs : 0x07d21098
Address@gxc_gmac1_regs : 0x07d61098
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
sgmii_lp_adv_ability_received
pulse: mr_an_exp.page received. Is also set when new an_adv_ability was received (s.hsgmii.rx_config_reg)
12 "0"
sgmii_mr_link
link status of SGMII connection (PCS layer xmit == DATA) (speed and duplex of SGMII should always be 1G/full)
11 0
-
 reserved
10 "0"
sgmii_rx_sync_status_fail
pulse: sync_status != OK occured (RX of SGMII: incoming sequence OK, if active for longer time this leads to mr_link = 0)
9 "0"
sgmii_rx_com_det_evt
pulse: comma detect event (info only at rx)
8 "0"
sgmii_rx_adapt_sp_shift_evt
pulse: sampling point shift detected in 10/100 mode (was not aligned to change of PCS data). This normally occurs at preamble shrinkage.
7 - 4 "0000"
sgmii_tx_alignment
current alignment of TX serializer sampling point (tx serializer vs. pma strobe sample phase) -> influences delay
3 "0"
sgmii_tx_realign_evt
pulse: TX serializer sampling point re-alignment occured (error, if tx-data from GMAC is at wrong rate)
2 "0"
sgmii_tx_shrink_evt
pulse: preamble shrinkage occured at TX (started in wrong even/odd raster)
1 "0"
sgmii_tx_epd3_evt
pulse: unwanted carrier extension due to even/odd idle alignment occured at transmitter (EPD3 state of PCS transmit ordered_set was entered)
0 "0"
sgmii_tx_even
tx ordered set alignment. Might be used to synchronize tx_en to idle ordered set to avoid preamble shrinkage (changes all 4 cc)


gmac_lut_bits
lut bits register
Note: This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0109c
Address@gxc_gmac0_regs : 0x07d2109c
Address@gxc_gmac1_regs : 0x07d6109c
Bits Reset value Name Description
31 - 16 0x0
lut_out
read lut_out write write_mask for lut in
15 - 0 0x0
lut_in



gmac_rpu_wr0
gMAC RPU internal Work Register 0
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010a0
Address@gxc_gmac0_regs : 0x07d210a0
Address@gxc_gmac1_regs : 0x07d610a0
Bits Reset value Name Description
31 - 0 0x0
val
RPU Work Register


gmac_rpu_wr1
gMAC RPU internal Work Register 1
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010a4
Address@gxc_gmac0_regs : 0x07d210a4
Address@gxc_gmac1_regs : 0x07d610a4
Bits Reset value Name Description
31 - 0 0x0
val
RPU Work Register


gmac_rx_config
gMAC RX config register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not readable by TPU.
R/W
0x30200100
Address@gxc_gmac_regs : 0x07c010a8
Address@gxc_gmac0_regs : 0x07d210a8
Address@gxc_gmac1_regs : 0x07d610a8
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
shift_rx_only_when_rxdv
Shift new receive data to RX register only, if rxdv is active.
This mode also influences rx_last4, rpu_count1_2lsb_shift_val and rpu_count2_2lsb_shift_val
29 - 23 "1100000"
rx_ifg_cnt_val
RX IFG counter:
This register is used to check the Interframe Gap time between two received frames.
At the end of a frame (EOF) it will be set to a programmable rx_ifg_cnt_preload value (=negative length of IFG),
then count up all received bits, saturating at zero.
The IFG counter will never exceed 0 even if its at -4 and 8 is added (speed 1000Mbit).
The rxdv signal used for this function is taken directly from sampling stage (SW might consider delay of nibble2byte conversion and MIIF).
If the minimum IFG is reached, cmp_rpucnt_status.rx_ifg_cnt_zero gets active.
Read access shows the current counter value rx_ifg_cnt_val.
Write access sets the preload value rx_ifg_cnt_preload (=negative length of IFG).
22 "0"
urx_fifo_fill_level_wrap
0: new behaviour: underflow: read@fifoempty drops read access, fill_level stays zero, output is undefined.
                  overflow: write@fifofull drops write access, fill_level stays max, FIFO RAM stays unchanged.
1: legacy mode:   underflow: read@fifoempty leads to fill_level=max (generates wrong utx_empty=0), FIFO needs to be reset.
                  overflow: write@fifofull leads to fill_level=0 (generates wrong urx_rdy=0), FIFO RAM is corrupted.
21 "1"
autoclear_error
Automatically clears all bits of debug_mii at start of next frame.
20 "0"
autoclear_status
Automatically clears *_was_here bits in status_mii at start of next frame.
19 "0"
smd_detection_mode
If active, accept only very clean preamble (only 5 followed by SMD)
This bit influences automatic nibble to byte conversion (rx_nibble2byte_man=0),
0: all data preceeding SMD will be ignored
1: expect_clean_preamble (only 5 preceeding SMD):
Any data nibble <> 5 preceeding SMD will lead to not detecting the SMD and thus not correcting a misaligned_smd to a byte border.
18 "0"
rx_nibble2byte_man
Select 10/100Mbit input handling
0: auto, 10/100Mbit works byte-wise, start of frame and SMD is detected and misaligned nibbles are corrected automatically
1: manual, GMAC decides if 10/100MBit is handled nibble- or byte-wise (s. gmac.rx_config_clock_handling)
17 - 16 "00"
rx_crc32_src
Source of CRC32 unit
00: src1 value is input CRC32 unit
01: reserved
10: rx[31:24] is input CRC32 unit
11: rx2[31:24] is input CRC32 unit
15 - 14 "00"
rx_crc_src
Source of CRC unit
00: src1 value is input CRC unit
01: reserved
10: rx[31:24] is input CRC unit
11: rx2[31:24] is input CRC unit
13 "0"
urxe_write_odd
This bit toggles with every write access to URXE-FIFO.
This bit has a delay of 1cc, i.e. gets active in the next but one cycle after writing URX-FIFO.
12 "0"
urx_write_odd
This bit toggles with every write access to URX-FIFO.
This bit has a delay of 1cc, i.e. gets active in the next but one cycle after writing URX-FIFO.
11 "0"
rx_count_stops_at_ovfl
1: rx_count stops counting after overflow
0: rx_count continues counting at overflow
10 "0"
rx_shift_lr
1: SBU writes incoming bits to position 7:0 of register rx and shifts rx left,
0: SBU writes incoming bits to position 31:24 of register rx and shifts rx right
9 - 8 "01"
rpu_sync_delay
Delay between rx_write_phase and RPU-sync pulse:
By this value the RPU-sync pulse is delayed by 0, 1, 2 or 3 clockcycles (x2ns).
If rpu_sync_delay=0, sync pulse at RPU is active 1 cycle before data (rx, status_mii, status_miif) -> don't use these registers in first cycle.
If rpu_sync_delay=1, sync pulse at RPU is active with data (rx, status_mii, status_miif) -> this is the default.
rpu_sync_delay=2,3 are for reserved future use cases -> never use.
7 - 5 0
-
 reserved
4 - 3 "00"
rx_fifo_depth_add
Fill level additional wait cycles, before reading from FIFO to rx register starts.
Allows to increase the guaranteed delay of the FIFO in steps of 2ns.
The delay of the FIFO after SOF is calculated in 1GBit modes as: TotalDelay = (4*rx_fifo_depth - 3 + rx_fifo_depth_add) * 2ns, e.g.:
  rx_fifo_depth rx_fifo_depth_add TotalDelay
  ------------- ----------------- ----------
     0 dont care  0 ns
     1    0  2 ns
     1    1  4 ns
     1    2  6 ns
     1    3  8 ns
     2    0 10 ns
     2    1 12 ns
     ...    ...  
     7    3 28 ns
2 - 0 "000"
rx_fifo_depth
Fill level (= number of nibbles/bytes) up to which MII-FIFO is filled, before reading from FIFO to rx register starts.
0 means, MII-FIFO is turned off, data is sampled directly to rx register (with jitter), FIFO is reset.
MII-FIFO can be used in all modes defined by ext_mode, speed, rx_nibble2byte_man, rx_nibble2byte_man_mode,
but values must not be changed within a frame (especially rx_nibble2byte_man_mode cannot be used).


gmac_rx_config_clock_handling
gMAC RX Config register for clock handling:
Note: This register is not accessible by TPU and not writable by CPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010ac
Address@gxc_gmac0_regs : 0x07d210ac
Address@gxc_gmac1_regs : 0x07d610ac
Bits Reset value Name Description
31 - 16 0x0
hgmii_mr_lp_adv_ability
read only "rx_config_reg" received from remote partner, contains status bits of remote link
Note: These inputs from internal SGMII PHY are swapped according to status_mii-rx_swap.
15 - 1 0
-
 reserved
0 "0"
rx_nibble2byte_man_mode
manual 10/100 input handling
This bit is only used, if activated by rx_config-rx_nibble2byte_man and (speed=10 or 100 Mbit)
Note: nibble-wise is used to detect SMD, may be switched to byte-wise afterwards.
0: nibble-wise, rx-register is shifted left and new input data is put to rx[31:28] (rx_shift_lr=0)
1: byte-wise, rx-register is shifted left and new input data is put to rx[31:24] (rx_shift_lr=0)


gmac_rx
gMAC RX Register
Sampled bits from SBU are collected in this register, i.e. if a new bit arrives from SBU (sync), other bits are shifted (direction programmable).
Same behaviour in MII-Modes (4/8 bits arrive in parallel and the other bits are shifted by 4/8).
R
Address@gxc_gmac_regs : 0x07c010b0
Address@gxc_gmac0_regs : 0x07d210b0
Address@gxc_gmac1_regs : 0x07d610b0
Bits Name Description
31 - 0 rx
previously received bits


gmac_rx2
gMAC RX2 Register
Bits shifted out of rx register are collected in this register.
Note: This register is not readable by TPU.
Change note: in netX22xx_mpw bit0 might be wrong if gpio2rx_smplsum command is used
R
Address@gxc_gmac_regs : 0x07c010b4
Address@gxc_gmac0_regs : 0x07d210b4
Address@gxc_gmac1_regs : 0x07d610b4
Bits Name Description
31 - 0 val
bits shifted out of rx register


gmac_rx_last4
gMAC RX_LAST4 Register
This address shows the last 4 bytes of a frame for crc check.
shift_rx_only_when_rxdv=0: rx_last4 = {rx[23:0],rx2[31:24]}
shift_rx_only_when_rxdv=1: rx_last4 = {rx[31:0]}
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c010b8
Address@gxc_gmac0_regs : 0x07d210b8
Address@gxc_gmac1_regs : 0x07d610b8
Bits Name Description
31 - 0 val
rx bits for compare


gmac_rx_count
gMAC RX Counter
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010bc
Address@gxc_gmac0_regs : 0x07d210bc
Address@gxc_gmac1_regs : 0x07d610bc
Bits Reset value Name Description
31 - 0 0x0
rx_count
Counter running on eclk


gmac_rpu_count1
gMAC RPU Counter 1
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010c0
Address@gxc_gmac0_regs : 0x07d210c0
Address@gxc_gmac1_regs : 0x07d610c0
Bits Reset value Name Description
31 - 0 0x0
rpu_count1
Counter incremented by rpu-hw_support bit cnt1


gmac_rpu_count2
gMAC RPU Counter 2
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010c4
Address@gxc_gmac0_regs : 0x07d210c4
Address@gxc_gmac1_regs : 0x07d610c4
Bits Reset value Name Description
31 - 0 0x0
rpu_count2
Counter incremented by rpu-hw_support bit cnt2


gmac_cmp_rpucnt_status
gMAC Compare RPUcnt Status Register
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c010c8
Address@gxc_gmac0_regs : 0x07d210c8
Address@gxc_gmac1_regs : 0x07d610c8
Bits Name Description
31 - 29 -
 reserved
28 rx_ifg_cnt_zero
1: rx_ifg_cnt is zero (min. IFG reached)
27 rpucnt2_wr3
1: rpu_count2 equals wr3
26 rpucnt2_wr2
1: rpu_count2 equals wr2
25 rpucnt2_wr1
1: rpu_count2 equals wr1
24 rpucnt2_wr0
1: rpu_count2 equals wr0
23 rpucnt2_mod8_zero
1: rpu_count2[2:0] == 0
22 rpucnt2_mod4_zero
1: rpu_count2[1:0] == 0
21 rpucnt1_mod8_zero
1: rpu_count1[2:0] == 0
20 rpucnt1_mod4_zero
1: rpu_count1[1:0] == 0
19 rpucnt2_gr_wr2_w1
1: rpu_count2 > {16'd0,wr2[31:16]}
18 rpucnt2_sm_wr2_w0
1: rpu_count2 < {16'd0,wr2[15:0]}
17 rpucnt1_gr_wr2_w1
1: rpu_count1 > {16'd0,wr2[31:16]}
16 rpucnt1_sm_wr2_w0
1: rpu_count1 < {16'd0,wr2[15:0]}
15 rpucnt1_sr7
1: rpu_count1 equals sr7
14 rpucnt1_sr6
1: rpu_count1 equals sr6
13 rpucnt1_sr5
1: rpu_count1 equals sr5
12 rpucnt1_sr4
1: rpu_count1 equals sr4
11 rpucnt1_sr3
1: rpu_count1 equals sr3
10 rpucnt1_sr2
1: rpu_count1 equals sr2
9 rpucnt1_sr1
1: rpu_count1 equals sr1
8 rpucnt1_sr0
1: rpu_count1 equals sr0
7 rpucnt1_wr7
1: rpu_count1 equals wr7
6 rpucnt1_wr6
1: rpu_count1 equals wr6
5 rpucnt1_wr5
1: rpu_count1 equals wr5
4 rpucnt1_wr4
1: rpu_count1 equals wr4
3 rpucnt1_wr3
1: rpu_count1 equals wr3
2 rpucnt1_wr2
1: rpu_count1 equals wr2
1 rpucnt1_wr1
1: rpu_count1 equals wr1
0 rpucnt1_wr0
1: rpu_count1 equals wr0


gmac_cmp_rxcrc_status
gMAC Compare RXCRC Status Register
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c010cc
Address@gxc_gmac0_regs : 0x07d210cc
Address@gxc_gmac1_regs : 0x07d610cc
Bits Name Description
31 - 22 -
 reserved
21 rx_crc32_ok_rx_last4_inv_hi_not_drewh
status_int-rx_crc32_ok_rx_last4_inv_hi and not status_mii-dr_err_was_here
20 rx_crc32_ok_rx_last4_inv_not_drewh
status_int-rx_crc32_ok_rx_last4_inv and not status_mii-dr_err_was_here
19 rx_crc32_ok_wr9_not_drewh
status_int-rx_crc32_ok_wr9 and not status_mii-dr_err_was_here
18 rx_crc32_ok_not_drewh
status_int-rx_crc32_ok and not status_mii-dr_err_was_here
17 rx_last4_b3_eq_crc32_b3_not_drewh
status_int-rx_last4_b3_eq_crc32_b3 and not status_mii-dr_err_was_here
16 rx_crc_ok_rx_last4_inv_hi_not_drewh
status_int-rx_crc_ok_rx_last4_inv_hi and not status_mii-dr_err_was_here
15 rx_crc_ok_rx_last4_inv_not_drewh
status_int-rx_crc_ok_rx_last4_inv and not status_mii-dr_err_was_here
14 rx_crc_ok_wr8_not_drewh
status_int-rx_crc_ok_wr8 and not status_mii-dr_err_was_here
13 rx_crc_ok_not_drewh
status_int-rx_crc_ok and not status_mii-dr_err_was_here
12 rx_last4_b3_eq_crc_b3_not_drewh
status_int-rx_last4_b3_eq_crc_b3 and not status_mii-dr_err_was_here
11 rx_last4_b3_eq_crc32_b3
compare of rx_crc32[31:24] with rx_last4[31:24]
10 rx_crc32_ok_rx_last4_inv_hi
compare of rx_crc32 with (rx_last4 xor 0xffff0000)
9 rx_crc32_ok_rx_last4_inv_wr9
compare of rx_crc32 with (rx_last4 xor wr9)
8 rx_crc32_ok_rx_last4_inv
compare of rx_crc32 with (rx_last4 xor 0xffffffff)
7 rx_crc32_ok_wr9
compare of rx_crc32 with wr9
6 rx_crc32_ok
compare of rx_crc32 with 0xc704dd7b
5 rx_last4_b3_eq_crc_b3
compare of rx_crc[31:24] with rx_last4[31:24]
4 rx_crc_ok_rx_last4_inv_hi
compare of rx_crc with (rx_last4 xor 0xffff0000)
3 rx_crc_ok_rx_last4_inv_wr8
compare of rx_crc with (rx_last4 xor wr8)
2 rx_crc_ok_rx_last4_inv
compare of rx_crc with (rx_last4 xor 0xffffffff)
1 rx_crc_ok_wr8
compare of rx_crc with wr8
0 rx_crc_ok
compare of rx_crc with 0xc704dd7b


gmac_tpu_wr0
gMAC TPU internal Work Register 0
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010d0
Address@gxc_gmac0_regs : 0x07d210d0
Address@gxc_gmac1_regs : 0x07d610d0
Bits Reset value Name Description
31 - 0 0x0
val
TPU Work Register


gmac_tpu_wr1
gMAC TPU internal Work Register 1
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010d4
Address@gxc_gmac0_regs : 0x07d210d4
Address@gxc_gmac1_regs : 0x07d610d4
Bits Reset value Name Description
31 - 0 0x0
val
TPU Work Register


gmac_tx_config
gMAC TX config register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x301ffc00
Address@gxc_gmac_regs : 0x07c010d8
Address@gxc_gmac0_regs : 0x07d210d8
Address@gxc_gmac1_regs : 0x07d610d8
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 23 "1100000"
tx_ifg_cnt_val
TX IFG counter:
This register is used to check the Interframe Gap time between two transmitted frames.
At the end of a frame (EOF) it will be set to a programmable tx_ifg_cnt_preload value (=negative length of IFG),
then count up all transmitted bits, saturating at zero.
The IFG counter will never exceed 0 even if its at -4 and 8 is added (speed 1000Mbit).
If the minimum IFG is reached, cmp_tpucnt_status.tx_ifg_cnt_zero gets active.
Read access shows the current counter value tx_ifg_cnt_val.
Write access sets the preload value tx_ifg_cnt_preload (=negative length of IFG).
22 "0"
utx_fifo_fill_level_wrap
0: new behaviour: underflow: read@fifoempty drops read access, fill_level stays zero, output is undefined.
                  overflow: write@fifofull drops write access, fill_level stays max, FIFO RAM stays unchanged.
1: legacy mode:   underflow: read@fifoempty leads to fill_level=max (generates wrong utx_empty=0), FIFO needs to be reset.
                  overflow: write@fifofull leads to fill_level=0 (generates wrong urx_rdy=0), FIFO RAM is corrupted.
21 - 20 "01"
mii_output_phase
MII-mode: Phase of mii_txclk, where nxt_tx_d, tx_en, tx_err signals are changed to be sampled by mii_txclk.
RMII-mode: Phase of rmii_refclk, where nxt_tx_d, tx_en outputs are changed to be sampled by rmii_refclk.
RGMII,SGMII-mode: unused.
0: change output 15cc after tpu_sync (2ns before next posedge@speed100)
1: change output 14cc after tpu_sync (4ns before next posedge@speed100)
2: change output 13cc after tpu_sync (6ns before next posedge@speed100)
3: change output 12cc after tpu_sync (8ns before next posedge@speed100)
19 - 15 "11111"
utxe_watermark
Watermark for gPEC event utxe_nxt2.
utxe_nxt2 is active, when there is at least 2 free entries to fill level (utxe_watermark+1).
Due to internal pipeline structure utxe_nxt2 need not be inactive, if there is watermark or more entries in the FIFO.
Allowed range is [2..31].
Value can only be changed, if FIFO is empty.
Example1: utxe_watermark=2:  utxe_nxt2 is active if utxe_fill_level < 2.
Example2: utxe_watermark=31: utxe_nxt2 is active if utxe_fill_level < 31.
                             utxe_nxt2 need not be inactive if utxe_fill_level >= 31.
14 - 10 "11111"
utx_watermark
Watermark for gPEC event utx_nxt2.
utx_nxt2 is active, when there is at least 2 free entries to fill level (utx_watermark+1).
Due to internal pipeline structure utx_nxt2 need not be inactive, if there is watermark or more entries in the FIFO.
Allowed range is [2..31].
Value can only be changed, if FIFO is empty.
Example1: utx_watermark=2:  utx_nxt2 is active if utx_fill_level < 2.
Example2: utx_watermark=31: utx_nxt2 is active if utx_fill_level < 31.
                            utx_nxt2 need not be inactive if utx_fill_level >= 31.
9 - 8 "00"
tx_crc32_src
Source of CRC32 unit
00: src1 value is input CRC32 unit
01: reserved
10: tx[7:0] is input CRC32 unit
11: tx2[7:0] is input CRC32 unit
7 - 6 "00"
tx_crc_src
Source of CRC unit
00: src1 value is input CRC unit
01: reserved
10: tx[7:0] is input CRC unit
11: tx2[7:0] is input CRC unit
5 "0"
tx_count_stops_at_ovfl
1: tx_count stops counting after overflow
0: tx_count continues counting at overflow
4 "0"
tx_shift_lr
1: OBU reads outgoing bits from position 15 of register tx and shifts tx left,
0: OBU reads outgoing bits from position 0 of register tx and shifts tx right
3 - 2 "00"
tpu_sync_delay
Delay between read of TX-register and TPU-sync pulse:
00: TPU-sync pulse is delayed by 1 clockcycle (2ns)
01: TPU-sync pulse is delayed by 1 clockcycle (2ns)
10: TPU-sync pulse is delayed by 2 clockcycle (4ns)
11: TPU-sync pulse is delayed by 3 clockcycle (6ns)
Note: Zero delay (former value 00) is no longer supported, as it leads to very long timing pathes in GMAC logic
1 - 0 "00"
tx_read_phase
TX register read phase:
This value defines the phase of external clock and thus when the next byte is read from tx register.


gmac_tx_config_clock_handling
gMAC TX Config register for clock handling
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010dc
Address@gxc_gmac0_regs : 0x07d210dc
Address@gxc_gmac1_regs : 0x07d610dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
tx_stay_on_byteborder
MII,RMII,RGMII-100/10 output handling:
0: In tx_byte_mode OBU will try to start a new frame asap.
   If TPU-SW sets txen to 1(start of new frame), OBU will synchronize on the next nibble-border.
   TPU-sync signals might jitter for 1 cycle.
   Intention is to spare effort for starting frames in nibble-mode, then switching to byte mode.
   Note: TPU-sync signal still occurs only bytewise and also the TX counter only counts full bytes.
1: In tx_byte_mode OBU will always stay on byte borders.
   txen and tx-registers must be set within 9 cycles after sync.
0 "0"
tx_nibble2byte_mode
MII output handling
0: nibble-wise (transmit 4 bit per sync)
1: byte-wise (transmit 8 bit per sync)
Note: This bit is ignored at 1GBit/s transfer rates, where bits are always transmitted byte-wise.
Note: nibble-wise is used to start transmission at 4-bit-sync in slow (R)(S)(G)MII modes, then switch manually to byte-wise at SMD.


gmac_tx
gMAC TX Register
Transmitted bits read automatically by OBU from this register, i.e. if a bit is send (sync), other bits are rotated accordingly (direction programmable).
Same behaviour in MII-modes (4/8 bits arrive in parallel and the other bits are rotated by 4/8).
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010e0
Address@gxc_gmac0_regs : 0x07d210e0
Address@gxc_gmac1_regs : 0x07d610e0
Bits Reset value Name Description
31 - 0 0x0
tx
to be transmitted bits
bit 0  is transmitted next in case of tx_shift_lr = 0
bit 31 is transmitted next in case of tx_shift_lr = 1


gmac_tx2
gMAC TX2 Register
Transmitted bits read by OBU from TX register are shifted into this TX2 register, i.e. if a bit is send, other bits are rotated accordingly (direction programmable).
Same behaviour in MII-modes (4/8 bits are send in parallel and the other bits are rotated by 4/8).
Note: This register is not accessible by RPU (except as src1 data).
R
Address@gxc_gmac_regs : 0x07c010e4
Address@gxc_gmac0_regs : 0x07d210e4
Address@gxc_gmac1_regs : 0x07d610e4
Bits Name Description
31 - 0 tx
already transmitted bits
bit 0  was transmitted first in case of tx_shift_lr = 0
bit 31 was transmitted first in case of tx_shift_lr = 1


gmac_tx_toggle_en
gMAC TX Register, that also changes config_mii.tx_en, config_mii.tx_err, tx_count
Write to this register also writes tx and tx_count registers.
Note: This register is not writable by RPU.
W
0x00000000
Address@gxc_gmac_regs : 0x07c010e8
Address@gxc_gmac0_regs : 0x07d210e8
Address@gxc_gmac1_regs : 0x07d610e8
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 - 12 "00000"
txcnt_val
value to be negated, shifted and load to tx_count register
-> tx_count = -txcnt_val * 4
11 "0"
load_txcnt
load tx_count with negative value of txcnt_val
10 "0"
mirror
mirror tx0 byte to tx[31:8]
0: tx[31:8] = 24'd0
1: tx[31:8] = {tx0,tx0,tx0}
9 "0"
txer
set config_mii.txer to this value
8 "0"
txen
set config_mii.txen to this value
7 - 0 "00000000"
tx0
to be transmitted bits
these bits are written to tx[7:0]


gmac_tx_count
gMAC TX Counter
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010ec
Address@gxc_gmac0_regs : 0x07d210ec
Address@gxc_gmac1_regs : 0x07d610ec
Bits Reset value Name Description
31 - 0 0x0
tx_count
Counter running on eclk


gmac_tpu_count1
gMAC TPU Counter 1
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010f0
Address@gxc_gmac0_regs : 0x07d210f0
Address@gxc_gmac1_regs : 0x07d610f0
Bits Reset value Name Description
31 - 0 0x0
tpu_count1
Counter incremented by tpu-hw_support bit cnt1


gmac_tpu_count2
gMAC TPU Counter 2
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c010f4
Address@gxc_gmac0_regs : 0x07d210f4
Address@gxc_gmac1_regs : 0x07d610f4
Bits Reset value Name Description
31 - 0 0x0
tpu_count2
Counter incremented by tpu-hw_support bit cnt2


gmac_cmp_tpucnt_status
gMAC Compare TPUcnt Status Register
Note: This register is not accessible by RPU (except as src1 data).
R
Address@gxc_gmac_regs : 0x07c010f8
Address@gxc_gmac0_regs : 0x07d210f8
Address@gxc_gmac1_regs : 0x07d610f8
Bits Name Description
31 - 29 -
 reserved
28 tx_ifg_cnt_zero
1: tx_ifg_cnt is zero (min. IFG reached)
27 tpucnt2_wr7
1: tpu_count2 equals wr7
26 tpucnt2_wr6
1: tpu_count2 equals wr6
25 tpucnt2_wr5
1: tpu_count2 equals wr5
24 tpucnt2_wr4
1: tpu_count2 equals wr4
23 tpucnt2_mod8_zero
1: tpu_count2[2:0] == 0
22 tpucnt2_mod4_zero
1: tpu_count2[1:0] == 0
21 tpucnt1_mod8_zero
1: tpu_count1[2:0] == 0
20 tpucnt1_mod4_zero
1: tpu_count1[1:0] == 0
19 tpucnt2_gr_wr6_w1
1: tpu_count2 > {16'd0,wr6[31:16]}
18 tpucnt2_sm_wr6_w0
1: tpu_count2 < {16'd0,wr6[15:0]}
17 tpucnt1_gr_wr6_w1
1: tpu_count1 > {16'd0,wr6[31:16]}
16 tpucnt1_sm_wr6_w0
1: tpu_count1 < {16'd0,wr6[15:0]}
15 tpucnt1_sr7
1: tpu_count1 equals sr7
14 tpucnt1_sr6
1: tpu_count1 equals sr6
13 tpucnt1_sr5
1: tpu_count1 equals sr5
12 tpucnt1_sr4
1: tpu_count1 equals sr4
11 tpucnt1_sr3
1: tpu_count1 equals sr3
10 tpucnt1_sr2
1: tpu_count1 equals sr2
9 tpucnt1_sr1
1: tpu_count1 equals sr1
8 tpucnt1_sr0
1: tpu_count1 equals sr0
7 tpucnt1_wr7
1: tpu_count1 equals wr7
6 tpucnt1_wr6
1: tpu_count1 equals wr6
5 tpucnt1_wr5
1: tpu_count1 equals wr5
4 tpucnt1_wr4
1: tpu_count1 equals wr4
3 tpucnt1_wr3
1: tpu_count1 equals wr3
2 tpucnt1_wr2
1: tpu_count1 equals wr2
1 tpucnt1_wr1
1: tpu_count1 equals wr1
0 tpucnt1_wr0
1: tpu_count1 equals wr0


gmac_systime_msk
gMAC Systime Compare Mask register:
Work register, used for compare with systime[31:0]
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01100
Address@gxc_gmac0_regs : 0x07d21100
Address@gxc_gmac1_regs : 0x07d61100
Bits Reset value Name Description
31 - 0 0x0
val
Systime Compare Mask Register


gmac_systime_cmp
gMAC Systime Compare Value register:
Work register, used for compare with systime[31:0]
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01104
Address@gxc_gmac0_regs : 0x07d21104
Address@gxc_gmac1_regs : 0x07d61104
Bits Reset value Name Description
31 - 0 0x0
val
Systime Compare Value Register


gmac_systime
gMAC System Time
Note: This register is not usable as condition.
R
Address@gxc_gmac_regs : 0x07c01108
Address@gxc_gmac0_regs : 0x07d21108
Address@gxc_gmac1_regs : 0x07d61108
Bits Name Description
31 - 0 val
32 lower bits of 64 bit systime.
Read access to this register will latch counter to different registers for RPU and TPU access.


gmac_counter
gMAC System Time Counter
Latched by read access to gmac_systime to different registers for RPU and TPU access:
- RPU read access to gmac_systime latches to register for RPU access
- TPU read access to gmac_systime latches to register for TPU access
Note: This register is not usable as condition.
R
Address@gxc_gmac_regs : 0x07c0110c
Address@gxc_gmac0_regs : 0x07d2110c
Address@gxc_gmac1_regs : 0x07d6110c
Bits Name Description
31 - 0 val
32 lower bits of 64 bit systime counter


gmac_systime_phy
gMAC System Time sampled at phy
Latched by phy sfd-signals to different registers for RPU and TPU access:
- rxsfd latches to register for RPU access
- txsfd latches to register for TPU access
Note: This register is not usable as condition.
R
Address@gxc_gmac_regs : 0x07c01110
Address@gxc_gmac0_regs : 0x07d21110
Address@gxc_gmac1_regs : 0x07d61110
Bits Name Description
31 - 0 val
32 lower bits of 64 bit systime,


gmac_counter_phy
gMAC (System Time) Counter sampled at phy
Latched by phy sfd-signals to different registers for RPU and TPU access:
- rxsfd latches to register for RPU access
- txsfd latches to register for TPU access
Note: This register is not usable as condition.
R
Address@gxc_gmac_regs : 0x07c01114
Address@gxc_gmac0_regs : 0x07d21114
Address@gxc_gmac1_regs : 0x07d61114
Bits Name Description
31 - 0 val
32 lower bits of 64 bit systime counter


gmac_rpu_pc
RPU Progamm counter
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
Change note: After netx22xx_mpw the command add_sat16u was changed to add16u
Change note: After netx22xx_mpw the gpio2rx_smplsum command is also connected to TPU
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01118
Address@gxc_gmac0_regs : 0x07d21118
Address@gxc_gmac1_regs : 0x07d61118
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 - 0 "0000000"
rpu_pc
Program Counter of RPU


gmac_tpu_pc
TPU Progamm counter
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0111c
Address@gxc_gmac0_regs : 0x07d2111c
Address@gxc_gmac1_regs : 0x07d6111c
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 - 0 "0000000"
tpu_pc
Program Counter of TPU


gmac_urtx
gMAC UTX FIFO and URX FIFO with bit32=0
write: URX FIFO with bit32=0
URX FIFO is part of gMAC. It can be read (output) by all gPECs, but only written (input) by the gMAC it belongs to.
read:
UTX FIFO
UTX FIFO is part of gMAC. It can be written (input) by all gPECs, but only read (output) by the gMAC it belongs to.
Read as src2 allows multiple reads, only read as src1 will change FIFO state.
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01120
Address@gxc_gmac0_regs : 0x07d21120
Address@gxc_gmac1_regs : 0x07d61120
Bits Reset value Name Description
31 - 0 0x0
val
input of URX_FIFO or output of UTX_FIFO


gmac_urx32
gMAC URX FIFO input with bit32=1
URX FIFO is part of gMAC. It can be read (output) by all gPECs, but only written (input) by the gMAC it belongs to.
Note: This register has a write pipeline delay of 1 clock cycle.
W
0x00000000
Address@gxc_gmac_regs : 0x07c01124
Address@gxc_gmac0_regs : 0x07d21124
Address@gxc_gmac1_regs : 0x07d61124
Bits Reset value Name Description
31 - 0 0x0
val
Lastly received bits to be transmitted to gPEC (input of URX_FIFO)


gmac_urtxe
gMAC UTXE FIFO and URXE FIFO with bit32=0
write: URXE FIFO with bit32=0
URXE FIFO is part of gMAC. It can be read (output) by all gPECs, but only written (input) by the gMAC it belongs to.
read:
UTXE FIFO
UTXE FIFO is part of gMAC. It can be written (input) by all gPECs, but only read (output) by the gMAC it belongs to.
Read as src2 allows multiple reads, only read as src1 will change FIFO state.
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01128
Address@gxc_gmac0_regs : 0x07d21128
Address@gxc_gmac1_regs : 0x07d61128
Bits Reset value Name Description
31 - 0 0x0
val
input of URXE_FIFO or output of UTXE_FIFO


gmac_urxe32
gMAC Express URX FIFO input with bit32=1
URX FIFO is part of gMAC. It can be read (output) by all gPECs, but only written (input) by the gMAC it belongs to.
Note: This register has a write pipeline delay of 1 clock cycle.
W
0x00000000
Address@gxc_gmac_regs : 0x07c0112c
Address@gxc_gmac0_regs : 0x07d2112c
Address@gxc_gmac1_regs : 0x07d6112c
Bits Reset value Name Description
31 - 0 0x0
val
Lastly received bits to be transmitted to gPEC (input of URX_FIFO)


gmac_pm_mask0
gMAC Pattern Match Mask 0 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as mask register in combination with gmac_pm_val0.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01130
Address@gxc_gmac0_regs : 0x07d21130
Address@gxc_gmac1_regs : 0x07d61130
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Mask:
1: compare this position of gmac_rpm_val0
0: ignore  this position of gmac_rpm_val0


gmac_pm_val0
gMAC Pattern Match Value 0 Register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as value of bits to be compared
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01134
Address@gxc_gmac0_regs : 0x07d21134
Address@gxc_gmac1_regs : 0x07d61134
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Value


gmac_pm_mask1
gMAC Pattern Match Mask 1 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as mask register in combination with gmac_pm_val1.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01138
Address@gxc_gmac0_regs : 0x07d21138
Address@gxc_gmac1_regs : 0x07d61138
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Mask:
1: compare this position of gmac_rpm_val1
0: ignore  this position of gmac_rpm_val1


gmac_pm_val1
gMAC Pattern Match Value 1 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as value of bits to be compared
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0113c
Address@gxc_gmac0_regs : 0x07d2113c
Address@gxc_gmac1_regs : 0x07d6113c
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Value


gmac_pm_mask2
gMAC Pattern Match Mask 2 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as mask register in combination with gmac_pm_val2.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01140
Address@gxc_gmac0_regs : 0x07d21140
Address@gxc_gmac1_regs : 0x07d61140
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Mask:
1: compare this position of gmac_rpm_val2
0: ignore  this position of gmac_rpm_val2


gmac_pm_val2
gMAC Pattern Match Value 2 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as value of bits to be compared
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01144
Address@gxc_gmac0_regs : 0x07d21144
Address@gxc_gmac1_regs : 0x07d61144
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Value


gmac_pm_mask3
gMAC Pattern Match Mask 3 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as mask register in combination with gmac_pm_val3.
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01148
Address@gxc_gmac0_regs : 0x07d21148
Address@gxc_gmac1_regs : 0x07d61148
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Mask:
1: compare this position of gmac_rpm_val3
0: ignore  this position of gmac_rpm_val3


gmac_pm_val3
gMAC Pattern Match Value 3 register:
Work register, used for different compare functions as defined in gmac_cmp* registers.
Usually used as value of bits to be compared
Note: This register is not usable as condition.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0114c
Address@gxc_gmac0_regs : 0x07d2114c
Address@gxc_gmac1_regs : 0x07d6114c
Bits Reset value Name Description
31 - 0 0x0
val
Pattern Match Value


gmac_rpu_jmp_latch
RPU Jump Latch:
Stores old PC at jump (via write to pc or via jump to address different from pc+1).
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c01180
Address@gxc_gmac0_regs : 0x07d21180
Address@gxc_gmac1_regs : 0x07d61180
Bits Name Description
31 - 7 -
 reserved
6 - 0 old_pc
Program Counter of RPU before last jump


gmac_rx_crc_cfg
gMAC RX CRC Config Register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01184
Address@gxc_gmac0_regs : 0x07d21184
Address@gxc_gmac1_regs : 0x07d61184
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
swap_output
Swap output of crc at PU access
11 "0"
endian
Swap incoming bits in case of nof_bits = 2,4,8
10 "0"
direct_div
calculate direct polynomial division without n zeros after frame
9 - 8 "00"
nof_bits
1(0),2(1),4(2),8(3) Bits from rx register to be executed in parallel
7 - 3 "00000"
len
Length of RX_CRC minus 1 (0-31)
2 "0"
invert
Invert input of RX CRC
1 "0"
zero
Set input of RX CRC to zero (before invert)
0 "0"
shift_right
Shift RX CRC from left to right
(usually used with crc_swap_output but inverted in case of crc_endian)


gmac_rx_crc_polynomial
gMAC RX CRC Polynomial
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R/W
0x04c11db7
Address@gxc_gmac_regs : 0x07c01188
Address@gxc_gmac0_regs : 0x07d21188
Address@gxc_gmac1_regs : 0x07d61188
Bits Reset value Name Description
31 - 0 0x4c11db7
val
RX-CRC Polynomial


gmac_rx_crc
gMAC RX CRC
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c0118c
Address@gxc_gmac0_regs : 0x07d2118c
Address@gxc_gmac1_regs : 0x07d6118c
Bits Reset value Name Description
31 - 0 0x0
val
RX-CRC


gmac_rx_crc32_cfg
gMAC RX CRC32 Config Register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01190
Address@gxc_gmac0_regs : 0x07d21190
Address@gxc_gmac1_regs : 0x07d61190
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
swap_output
Swap output of crc at PU access
11 "0"
endian
Swap incoming bits in case of nof_bits = 2,4,8
10 "0"
direct_div
calculate direct polynomial division without n zeros after frame
9 - 8 "00"
nof_bits
1(0),2(1),4(2),8(3) Bits from rx register to be executed in parallel
7 - 3 0
-
 reserved
2 "0"
invert
Invert input of RX CRC32
1 "0"
zero
Set input of RX CRC32 to zero (before invert)
0 "0"
shift_right
Shift RX CRC32 from left to right
(usually used with crc_swap_output but inverted in case of crc_endian)


gmac_rx_crc32
gMAC RX CRC32
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c01194
Address@gxc_gmac0_regs : 0x07d21194
Address@gxc_gmac1_regs : 0x07d61194
Bits Reset value Name Description
31 - 0 0x0
val
RX-CRC32


gmac_rpu_count1_2lsb_shift_val
gMAC Lower bits of rpu_count1 processed for dword alignment
This is dependent on shift_rx_only_when_rxdv
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c01198
Address@gxc_gmac0_regs : 0x07d21198
Address@gxc_gmac1_regs : 0x07d61198
Bits Name Description
31 - 5 msk
shift_rx_only_when_rxdv=0: Mask value 0x00ffffff >> srt
shift_rx_only_when_rxdv=1: Mask value 0xffffffff >> srt
4 - 0 srt
shift_rx_only_when_rxdv=0: Shift value (3 - rpu_count1[1:0]) << 3
shift_rx_only_when_rxdv=1: Shift value (4 - rpu_count1[1:0]) << 3


gmac_rpu_count2_2lsb_shift_val
gMAC Lower bits of rpu_count2 processed for dword alignment
This is dependent on shift_rx_only_when_rxdv
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c0119c
Address@gxc_gmac0_regs : 0x07d2119c
Address@gxc_gmac1_regs : 0x07d6119c
Bits Name Description
31 - 5 msk
shift_rx_only_when_rxdv=0: Mask value 0x00ffffff >> srt
shift_rx_only_when_rxdv=1: Mask value 0xffffffff >> srt
4 - 0 srt
shift_rx_only_when_rxdv=0: Shift value (3 - rpu_count1[1:0]) << 3
shift_rx_only_when_rxdv=1: Shift value (4 - rpu_count1[1:0]) << 3


gmac_rx_frame_err_cnt
RX CRC counter pulses
In this register GMAC sends pulses to counters inside gxc_sys_ctrl.
Note: This register has a write pipeline delay of 1 clock cycle.
W
0x00000000
Address@gxc_gmac_regs : 0x07c011a0
Address@gxc_gmac0_regs : 0x07d211a0
Address@gxc_gmac1_regs : 0x07d611a0
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
cnt1
write 1 to send count pulse to gxc_sys_ctrl_gmac_rpuX_counter_1
3 "0"
cnt0
write 1 to send count pulse to gxc_sys_ctrl_gmac_rpuX_counter_0
2 "0"
proc_err
write 1 to send count pulse to gxc_sys_ctrl proc_err counter
1 "0"
frwd_err
write 1 to send count pulse to gxc_sys_ctrl forwarded_err counter
0 "0"
frame_err
write 1 to send count pulse to gxc_sys_ctrl invalid_frame counter


gmac_rx_rpm_hit_num
gMAC rpm_hit_num Register
Used for jump table.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c011a4
Address@gxc_gmac0_regs : 0x07d211a4
Address@gxc_gmac1_regs : 0x07d611a4
Bits Name Description
31 - 3 -
 reserved
2 - 0 rpm_hit_num
Number of receive pattern match
000: rpm_hit0 = 1
001: rpm_hit1 = 1 (and rpm_hit0 = 0)
010: rpm_hit2 = 1 (and rpm_hit0,1 = 0)
011: rpm_hit3 = 1 (and rpm_hit0,1,2 = 0)
100: no rpm match


gmac_rx_smd_hit_num
gMAC smd_hit_num Register
Used for jump table.
Note: Matches also if nibbles have no active rx_dv. Use shift_rx_only_when_rxdv mode to match only valid SMD bytes.
Note: This register is not usable as condition.
Note: This register is not readable by TPU.
R
Address@gxc_gmac_regs : 0x07c011a8
Address@gxc_gmac0_regs : 0x07d211a8
Address@gxc_gmac1_regs : 0x07d611a8
Bits Name Description
31 - 4 -
 reserved
3 - 0 smd_hit_num
Number of receive pattern match
0000: rx_b3_eq_55 = 1
0001: rx_b3_eq_d5 = 1 (and none of the above)
0010: rx_b3_eq_07 = 1 (and none of the above)
0011: rx_b3_eq_19 = 1 (and none of the above)
0100: rx_b3_eq_e6 = 1 (and none of the above)
0101: rx_b3_eq_4c = 1 (and none of the above)
0110: rx_b3_eq_7f = 1 (and none of the above)
0111: rx_b3_eq_b3 = 1 (and none of the above)
1000: none of the above matches


gmac_tpu_jmp_latch
TPU Jump Latch:
Stores old PC at jump (via write to pc or via jump to address different from pc+1).
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R
Address@gxc_gmac_regs : 0x07c011c0
Address@gxc_gmac0_regs : 0x07d211c0
Address@gxc_gmac1_regs : 0x07d611c0
Bits Name Description
31 - 7 -
 reserved
6 - 0 old_pc
Program Counter of TPU before last jump


gmac_tx_crc_cfg
gMAC TX CRC Config Register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c011c4
Address@gxc_gmac0_regs : 0x07d211c4
Address@gxc_gmac1_regs : 0x07d611c4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
swap_output
Swap output of crc at PU access
11 "0"
endian
Swap incoming bits in case of nof_bits = 2,4,8
10 "0"
direct_div
calculate direct polynomial division without n zeros after frame
9 - 8 "00"
nof_bits
1(0),2(1),4(2),8(3) Bits from tx_register to be executed in parallel
7 - 3 "00000"
len
Length of TX_CRC minus 1 (0-31)
2 "0"
invert
Invert input of TX CRC
1 "0"
zero
Set input of TX CRC to zero (before invert)
0 "0"
shift_right
Shift TX CRC from left to right
(usually used with crc_swap_output but inverted in case of crc_endian)


gmac_tx_crc_polynomial
gMAC TX CRC Polynomial
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x04c11db7
Address@gxc_gmac_regs : 0x07c011c8
Address@gxc_gmac0_regs : 0x07d211c8
Address@gxc_gmac1_regs : 0x07d611c8
Bits Reset value Name Description
31 - 0 0x4c11db7
val
TX-CRC Polynomial


gmac_tx_crc
gMAC TX CRC
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c011cc
Address@gxc_gmac0_regs : 0x07d211cc
Address@gxc_gmac1_regs : 0x07d611cc
Bits Reset value Name Description
31 - 0 0x0
val
TX-CRC


gmac_tx_crc32_cfg
gMAC TX CRC32 Config Register
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c011d0
Address@gxc_gmac0_regs : 0x07d211d0
Address@gxc_gmac1_regs : 0x07d611d0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
swap_output
Swap output of crc at PU access
11 "0"
endian
Swap incoming bits in case of nof_bits = 2,4,8
10 "0"
direct_div
calculate direct polynomial division without n zeros after frame
9 - 8 "00"
nof_bits
1(0),2(1),4(2),8(3) Bits from tx_register to be executed in parallel
7 - 3 0
-
 reserved
2 "0"
invert
Invert input of TX CRC32
1 "0"
zero
Set input of TX CRC32 to zero (before invert)
0 "0"
shift_right
Shift TX CRC32 from left to right
(usually used with crc_swap_output but inverted in case of crc_endian)


gmac_tx_crc32
gMAC TX CRC32
Note: This register has a write pipeline delay of 1 clock cycle.
Note: This register is not usable as condition.
Note: This register is not accessible by RPU (except as src1 data).
R/W
0x00000000
Address@gxc_gmac_regs : 0x07c011d4
Address@gxc_gmac0_regs : 0x07d211d4
Address@gxc_gmac1_regs : 0x07d611d4
Bits Reset value Name Description
31 - 0 0x0
val
TX-CRC32



Base Address Area: gxc_gpec_pram, gxc_gpec00_pram, gxc_gpec01_pram, gxc_gpec02_pram, gxc_gpec03_pram, gxc_gpec04_pram, gxc_gpec05_pram, gxc_gpec06_pram, gxc_gpec07_pram, gxc_gpec10_pram, gxc_gpec11_pram, gxc_gpec12_pram, gxc_gpec13_pram, gxc_gpec14_pram, gxc_gpec15_pram, gxc_gpec16_pram, gxc_gpec17_pram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 - gpec_pram_start
1-3fe 4-ff8 -  reserved
3ff ffc - gpec_pram_end

gpec_pram_start

Address@gxc_gpec_pram : 0x07c02000
Address@gxc_gpec00_pram : 0x07d02000
Address@gxc_gpec01_pram : 0x07d06000
Address@gxc_gpec02_pram : 0x07d0a000
Address@gxc_gpec03_pram : 0x07d0e000
Address@gxc_gpec04_pram : 0x07d12000
Address@gxc_gpec05_pram : 0x07d16000
Address@gxc_gpec06_pram : 0x07d1a000
Address@gxc_gpec07_pram : 0x07d1e000
Address@gxc_gpec10_pram : 0x07d42000
Address@gxc_gpec11_pram : 0x07d46000
Address@gxc_gpec12_pram : 0x07d4a000
Address@gxc_gpec13_pram : 0x07d4e000
Address@gxc_gpec14_pram : 0x07d52000
Address@gxc_gpec15_pram : 0x07d56000
Address@gxc_gpec16_pram : 0x07d5a000
Address@gxc_gpec17_pram : 0x07d5e000
Bits Name Description
31 - 0 gpec_pram_start


gpec_pram_end

Address@gxc_gpec_pram : 0x07c02ffc
Address@gxc_gpec00_pram : 0x07d02ffc
Address@gxc_gpec01_pram : 0x07d06ffc
Address@gxc_gpec02_pram : 0x07d0affc
Address@gxc_gpec03_pram : 0x07d0effc
Address@gxc_gpec04_pram : 0x07d12ffc
Address@gxc_gpec05_pram : 0x07d16ffc
Address@gxc_gpec06_pram : 0x07d1affc
Address@gxc_gpec07_pram : 0x07d1effc
Address@gxc_gpec10_pram : 0x07d42ffc
Address@gxc_gpec11_pram : 0x07d46ffc
Address@gxc_gpec12_pram : 0x07d4affc
Address@gxc_gpec13_pram : 0x07d4effc
Address@gxc_gpec14_pram : 0x07d52ffc
Address@gxc_gpec15_pram : 0x07d56ffc
Address@gxc_gpec16_pram : 0x07d5affc
Address@gxc_gpec17_pram : 0x07d5effc
Bits Name Description
31 - 0 gpec_pram_end



Base Address Area: gxc_gpec_regs, gxc_gpec00_regs, gxc_gpec01_regs, gxc_gpec02_regs, gxc_gpec03_regs, gxc_gpec04_regs, gxc_gpec05_regs, gxc_gpec06_regs, gxc_gpec07_regs, gxc_gpec10_regs, gxc_gpec11_regs, gxc_gpec12_regs, gxc_gpec13_regs, gxc_gpec14_regs, gxc_gpec15_regs, gxc_gpec16_regs, gxc_gpec17_regs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gpec_r0
1 4 R/W gpec_r1
2 8 R/W gpec_r2
3 c R/W gpec_r3
4 10 R/W gpec_r4
5 14 R/W gpec_r5
6 18 R/W gpec_r6
7 1c R/W gpec_r7
8 20 R/W gpec_stat_bits
9 24 R/W gpec_range_urx_count
a 28 R/W gpec_usr0
b 2c R/W gpec_range67
c 30 R/W gpec_timer0
d 34 R/W gpec_timer1
e 38 R/W gpec_timer2
f 3c R/W gpec_timer3
10 40 R/W gpec_timer4
11 44 R/W gpec_timer5
12 48 R/W gpec_urx_count
13 4c R/W gpec_axi_data
14 50 R/W gpec_pc
15 54 R/W gpec_zero
16 58 R/W gpec_config
17 5c R/W gpec_ec_mask0
18 60 R/W gpec_ec_mask1
19 64 R/W gpec_ec_mask2
1a 68 R/W gpec_ec_mask3
1b 6c R/W gpec_ec_mask4
1c 70 R/W gpec_ec_mask5
1d 74 R/W gpec_ec_mask6
1e 78 R/W gpec_ec_mask7
1f 7c R/W gpec_pfifo_mask
20 80 R/W gpec_pfifo_cfg
21 84 R/W gpec_lut_bits
22 88 R/W gpec_crc_data
23 8c W gpec_irq
24 90 R gpec_systime
25 94 R gpec_counter
26 98 R/W gpec_fifo_data
27 9c R/W gpec_host_req
28 a0 R/W gpec_sr0
29 a4 R/W gpec_sr1
2a a8 R/W gpec_sr2
2b ac R/W gpec_sr3
2c b0 R/W gpec_sr4
2d b4 R/W gpec_sr5
2e b8 R/W gpec_sr6
2f bc R/W gpec_sr7
30 c0 R/W gpec_sr8
31 c4 R/W gpec_sr9
32 c8 R/W gpec_sr10
33 cc R/W gpec_sr11
34 d0 R/W gpec_sr12
35 d4 R/W gpec_sr13
36 d8 R/W gpec_sr14
37 dc R/W gpec_sr15
38 e0 R/W gpec_statcfg0
39 e4 R/W gpec_statcfg1
3a e8 R/W gpec_axi_wr_cfg
3b ec R/W gpec_axi_rd_cfg
3c f0 R/W gpec_urtx0
3d f4 R/W gpec_urtx1
3e f8 R/W gpec_urtxe0
3f fc R/W gpec_urtxe1

gpec_r0
Work Register 0
This register can be used as address register and as a target of multiplication.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03000
Address@gxc_gpec00_regs : 0x07d03000
Address@gxc_gpec01_regs : 0x07d07000
Address@gxc_gpec02_regs : 0x07d0b000
Address@gxc_gpec03_regs : 0x07d0f000
Address@gxc_gpec04_regs : 0x07d13000
Address@gxc_gpec05_regs : 0x07d17000
Address@gxc_gpec06_regs : 0x07d1b000
Address@gxc_gpec07_regs : 0x07d1f000
Address@gxc_gpec10_regs : 0x07d43000
Address@gxc_gpec11_regs : 0x07d47000
Address@gxc_gpec12_regs : 0x07d4b000
Address@gxc_gpec13_regs : 0x07d4f000
Address@gxc_gpec14_regs : 0x07d53000
Address@gxc_gpec15_regs : 0x07d57000
Address@gxc_gpec16_regs : 0x07d5b000
Address@gxc_gpec17_regs : 0x07d5f000
Bits Reset value Name Description
31 - 0 0x0
r0
software defined value


gpec_r1
Work Register 1
This register can be used as address register and as a target of multiplication.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03004
Address@gxc_gpec00_regs : 0x07d03004
Address@gxc_gpec01_regs : 0x07d07004
Address@gxc_gpec02_regs : 0x07d0b004
Address@gxc_gpec03_regs : 0x07d0f004
Address@gxc_gpec04_regs : 0x07d13004
Address@gxc_gpec05_regs : 0x07d17004
Address@gxc_gpec06_regs : 0x07d1b004
Address@gxc_gpec07_regs : 0x07d1f004
Address@gxc_gpec10_regs : 0x07d43004
Address@gxc_gpec11_regs : 0x07d47004
Address@gxc_gpec12_regs : 0x07d4b004
Address@gxc_gpec13_regs : 0x07d4f004
Address@gxc_gpec14_regs : 0x07d53004
Address@gxc_gpec15_regs : 0x07d57004
Address@gxc_gpec16_regs : 0x07d5b004
Address@gxc_gpec17_regs : 0x07d5f004
Bits Reset value Name Description
31 - 0 0x0
r1
software defined value


gpec_r2
Work Register 2
This register can be used as address register and as a target of multiplication.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03008
Address@gxc_gpec00_regs : 0x07d03008
Address@gxc_gpec01_regs : 0x07d07008
Address@gxc_gpec02_regs : 0x07d0b008
Address@gxc_gpec03_regs : 0x07d0f008
Address@gxc_gpec04_regs : 0x07d13008
Address@gxc_gpec05_regs : 0x07d17008
Address@gxc_gpec06_regs : 0x07d1b008
Address@gxc_gpec07_regs : 0x07d1f008
Address@gxc_gpec10_regs : 0x07d43008
Address@gxc_gpec11_regs : 0x07d47008
Address@gxc_gpec12_regs : 0x07d4b008
Address@gxc_gpec13_regs : 0x07d4f008
Address@gxc_gpec14_regs : 0x07d53008
Address@gxc_gpec15_regs : 0x07d57008
Address@gxc_gpec16_regs : 0x07d5b008
Address@gxc_gpec17_regs : 0x07d5f008
Bits Reset value Name Description
31 - 0 0x0
r2
software defined value


gpec_r3
Work Register 3
This register can be used as address register and as a target of multiplication.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0300c
Address@gxc_gpec00_regs : 0x07d0300c
Address@gxc_gpec01_regs : 0x07d0700c
Address@gxc_gpec02_regs : 0x07d0b00c
Address@gxc_gpec03_regs : 0x07d0f00c
Address@gxc_gpec04_regs : 0x07d1300c
Address@gxc_gpec05_regs : 0x07d1700c
Address@gxc_gpec06_regs : 0x07d1b00c
Address@gxc_gpec07_regs : 0x07d1f00c
Address@gxc_gpec10_regs : 0x07d4300c
Address@gxc_gpec11_regs : 0x07d4700c
Address@gxc_gpec12_regs : 0x07d4b00c
Address@gxc_gpec13_regs : 0x07d4f00c
Address@gxc_gpec14_regs : 0x07d5300c
Address@gxc_gpec15_regs : 0x07d5700c
Address@gxc_gpec16_regs : 0x07d5b00c
Address@gxc_gpec17_regs : 0x07d5f00c
Bits Reset value Name Description
31 - 0 0x0
r3
software defined value


gpec_r4
Work Register 4
This register can be used as address register and as a target of multiplication.
r4[31:16] are considered as range4.
Generates range events.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03010
Address@gxc_gpec00_regs : 0x07d03010
Address@gxc_gpec01_regs : 0x07d07010
Address@gxc_gpec02_regs : 0x07d0b010
Address@gxc_gpec03_regs : 0x07d0f010
Address@gxc_gpec04_regs : 0x07d13010
Address@gxc_gpec05_regs : 0x07d17010
Address@gxc_gpec06_regs : 0x07d1b010
Address@gxc_gpec07_regs : 0x07d1f010
Address@gxc_gpec10_regs : 0x07d43010
Address@gxc_gpec11_regs : 0x07d47010
Address@gxc_gpec12_regs : 0x07d4b010
Address@gxc_gpec13_regs : 0x07d4f010
Address@gxc_gpec14_regs : 0x07d53010
Address@gxc_gpec15_regs : 0x07d57010
Address@gxc_gpec16_regs : 0x07d5b010
Address@gxc_gpec17_regs : 0x07d5f010
Bits Reset value Name Description
31 - 0 0x0
r4
software defined value


gpec_r5
Work Register 5
This register can be used as address register and as a target of multiplication.
r5[31:16] are considered as range5.
Generates range events.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03014
Address@gxc_gpec00_regs : 0x07d03014
Address@gxc_gpec01_regs : 0x07d07014
Address@gxc_gpec02_regs : 0x07d0b014
Address@gxc_gpec03_regs : 0x07d0f014
Address@gxc_gpec04_regs : 0x07d13014
Address@gxc_gpec05_regs : 0x07d17014
Address@gxc_gpec06_regs : 0x07d1b014
Address@gxc_gpec07_regs : 0x07d1f014
Address@gxc_gpec10_regs : 0x07d43014
Address@gxc_gpec11_regs : 0x07d47014
Address@gxc_gpec12_regs : 0x07d4b014
Address@gxc_gpec13_regs : 0x07d4f014
Address@gxc_gpec14_regs : 0x07d53014
Address@gxc_gpec15_regs : 0x07d57014
Address@gxc_gpec16_regs : 0x07d5b014
Address@gxc_gpec17_regs : 0x07d5f014
Bits Reset value Name Description
31 - 0 0x0
r5
software defined value


gpec_r6
Work Register 6
This register can be used as address register and as a target of multiplication.

Shared in gpec regmode_bank1 with fmmusm_read_addr_in (w mode).
Register only accessible via gpec00.

Shared in gpec regmode_bank1 with sm_read_addr_out (r mode).
Register only accessible via gpec00.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03018
Address@gxc_gpec00_regs : 0x07d03018
Address@gxc_gpec01_regs : 0x07d07018
Address@gxc_gpec02_regs : 0x07d0b018
Address@gxc_gpec03_regs : 0x07d0f018
Address@gxc_gpec04_regs : 0x07d13018
Address@gxc_gpec05_regs : 0x07d17018
Address@gxc_gpec06_regs : 0x07d1b018
Address@gxc_gpec07_regs : 0x07d1f018
Address@gxc_gpec10_regs : 0x07d43018
Address@gxc_gpec11_regs : 0x07d47018
Address@gxc_gpec12_regs : 0x07d4b018
Address@gxc_gpec13_regs : 0x07d4f018
Address@gxc_gpec14_regs : 0x07d53018
Address@gxc_gpec15_regs : 0x07d57018
Address@gxc_gpec16_regs : 0x07d5b018
Address@gxc_gpec17_regs : 0x07d5f018
Bits Reset value Name Description
31 - 0 0x0
r6
software defined value


gpec_r7
Work Register 7
This register can be used as address register and as a target of multiplication.

Shared in gpec regmode_bank1 with fmmusm_write_addr_in (w mode).
Register only accessible via gpec00.
This register has an additional write pipeline delay of 1 clock cycle.

Shared in gpec regmode_bank1 with sm_write_addr_out (r mode).
Register only accessible via gpec00.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0301c
Address@gxc_gpec00_regs : 0x07d0301c
Address@gxc_gpec01_regs : 0x07d0701c
Address@gxc_gpec02_regs : 0x07d0b01c
Address@gxc_gpec03_regs : 0x07d0f01c
Address@gxc_gpec04_regs : 0x07d1301c
Address@gxc_gpec05_regs : 0x07d1701c
Address@gxc_gpec06_regs : 0x07d1b01c
Address@gxc_gpec07_regs : 0x07d1f01c
Address@gxc_gpec10_regs : 0x07d4301c
Address@gxc_gpec11_regs : 0x07d4701c
Address@gxc_gpec12_regs : 0x07d4b01c
Address@gxc_gpec13_regs : 0x07d4f01c
Address@gxc_gpec14_regs : 0x07d5301c
Address@gxc_gpec15_regs : 0x07d5701c
Address@gxc_gpec16_regs : 0x07d5b01c
Address@gxc_gpec17_regs : 0x07d5f01c
Bits Reset value Name Description
31 - 0 0x0
r7
software defined value


gpec_stat_bits
Status Bits Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Interface register to gxc_sr module of the corresponding gxc instance.
Read access returns gxc_sr.stat_bits[15:0]
Write access writes gxc_sr.stat_bits[15:0] if corresponding bits in set_mask are set.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03020
Address@gxc_gpec00_regs : 0x07d03020
Address@gxc_gpec01_regs : 0x07d07020
Address@gxc_gpec02_regs : 0x07d0b020
Address@gxc_gpec03_regs : 0x07d0f020
Address@gxc_gpec04_regs : 0x07d13020
Address@gxc_gpec05_regs : 0x07d17020
Address@gxc_gpec06_regs : 0x07d1b020
Address@gxc_gpec07_regs : 0x07d1f020
Address@gxc_gpec10_regs : 0x07d43020
Address@gxc_gpec11_regs : 0x07d47020
Address@gxc_gpec12_regs : 0x07d4b020
Address@gxc_gpec13_regs : 0x07d4f020
Address@gxc_gpec14_regs : 0x07d53020
Address@gxc_gpec15_regs : 0x07d57020
Address@gxc_gpec16_regs : 0x07d5b020
Address@gxc_gpec17_regs : 0x07d5f020
Bits Reset value Name Description
31 - 16 0x0
set_mask
set mask for flags
15 - 0 0x0
flags
shared bit vector


gpec_range_urx_count
Range URX Counter Register
Over- / underflow thresholds to limit accesses to URX(E).
Generates range events

Shared in gpec regmode_bank1 with range_utx_count (r/w mode).
Over- / underflow thresholds to limit accesses to UTX(E).
Generates range events

Shared in gpec regmode_bank2 with wait_mask (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
use nop before wait
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03024
Address@gxc_gpec00_regs : 0x07d03024
Address@gxc_gpec01_regs : 0x07d07024
Address@gxc_gpec02_regs : 0x07d0b024
Address@gxc_gpec03_regs : 0x07d0f024
Address@gxc_gpec04_regs : 0x07d13024
Address@gxc_gpec05_regs : 0x07d17024
Address@gxc_gpec06_regs : 0x07d1b024
Address@gxc_gpec07_regs : 0x07d1f024
Address@gxc_gpec10_regs : 0x07d43024
Address@gxc_gpec11_regs : 0x07d47024
Address@gxc_gpec12_regs : 0x07d4b024
Address@gxc_gpec13_regs : 0x07d4f024
Address@gxc_gpec14_regs : 0x07d53024
Address@gxc_gpec15_regs : 0x07d57024
Address@gxc_gpec16_regs : 0x07d5b024
Address@gxc_gpec17_regs : 0x07d5f024
Bits Reset value Name Description
31 - 16 0x0
range_urxe_count
in regmode bank 1 range_utxe_count
border for urxe_count/ utxe_count
15 - 0 0x0
range_urx_count
in regmode bank 1 range_utx_count
border for urx_count/ utxe_count


gpec_usr0
User Register
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03028
Address@gxc_gpec00_regs : 0x07d03028
Address@gxc_gpec01_regs : 0x07d07028
Address@gxc_gpec02_regs : 0x07d0b028
Address@gxc_gpec03_regs : 0x07d0f028
Address@gxc_gpec04_regs : 0x07d13028
Address@gxc_gpec05_regs : 0x07d17028
Address@gxc_gpec06_regs : 0x07d1b028
Address@gxc_gpec07_regs : 0x07d1f028
Address@gxc_gpec10_regs : 0x07d43028
Address@gxc_gpec11_regs : 0x07d47028
Address@gxc_gpec12_regs : 0x07d4b028
Address@gxc_gpec13_regs : 0x07d4f028
Address@gxc_gpec14_regs : 0x07d53028
Address@gxc_gpec15_regs : 0x07d57028
Address@gxc_gpec16_regs : 0x07d5b028
Address@gxc_gpec17_regs : 0x07d5f028
Bits Reset value Name Description
31 - 0 0x0
val
software defined value


gpec_range67
Range r6/r7 Register
Over- / underflow thresholds to limit buffer addresses.
Generates range events.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0302c
Address@gxc_gpec00_regs : 0x07d0302c
Address@gxc_gpec01_regs : 0x07d0702c
Address@gxc_gpec02_regs : 0x07d0b02c
Address@gxc_gpec03_regs : 0x07d0f02c
Address@gxc_gpec04_regs : 0x07d1302c
Address@gxc_gpec05_regs : 0x07d1702c
Address@gxc_gpec06_regs : 0x07d1b02c
Address@gxc_gpec07_regs : 0x07d1f02c
Address@gxc_gpec10_regs : 0x07d4302c
Address@gxc_gpec11_regs : 0x07d4702c
Address@gxc_gpec12_regs : 0x07d4b02c
Address@gxc_gpec13_regs : 0x07d4f02c
Address@gxc_gpec14_regs : 0x07d5302c
Address@gxc_gpec15_regs : 0x07d5702c
Address@gxc_gpec16_regs : 0x07d5b02c
Address@gxc_gpec17_regs : 0x07d5f02c
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 16 0x0
range7
border for gpec_r7
15 - 13 0
-
 reserved
12 - 0 0x0
range6
border for gpec_r6


gpec_timer0
Timer 0 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank2 with gpec_config2 (r/w mode).
     5    : pfifo_rdy_timer2small  # debug status, set to one if pfifo_rdy event goes up after pfifo_rdy timer expired; write one to reset flag
 4 - 0    : pfifo_rdy_timer      #  0: pfifo_rdy signal generated after access finished
           :                      #  1..31: pfifo_rdy generated x cc after access started (set to worst case value; used to get determistic PEC program flow, worst case value is number of pfifo accessing parties minus one)
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03030
Address@gxc_gpec00_regs : 0x07d03030
Address@gxc_gpec01_regs : 0x07d07030
Address@gxc_gpec02_regs : 0x07d0b030
Address@gxc_gpec03_regs : 0x07d0f030
Address@gxc_gpec04_regs : 0x07d13030
Address@gxc_gpec05_regs : 0x07d17030
Address@gxc_gpec06_regs : 0x07d1b030
Address@gxc_gpec07_regs : 0x07d1f030
Address@gxc_gpec10_regs : 0x07d43030
Address@gxc_gpec11_regs : 0x07d47030
Address@gxc_gpec12_regs : 0x07d4b030
Address@gxc_gpec13_regs : 0x07d4f030
Address@gxc_gpec14_regs : 0x07d53030
Address@gxc_gpec15_regs : 0x07d57030
Address@gxc_gpec16_regs : 0x07d5b030
Address@gxc_gpec17_regs : 0x07d5f030
Bits Reset value Name Description
31 - 0 0x0
timer_preload0
read: actual value of timer, write: timer and preload value


gpec_timer1
Timer 1 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank2 with axi_wr_msk (r/w mode).
  27 -  0  : val        # address mask: bits set to one are not changed by auto increment
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03034
Address@gxc_gpec00_regs : 0x07d03034
Address@gxc_gpec01_regs : 0x07d07034
Address@gxc_gpec02_regs : 0x07d0b034
Address@gxc_gpec03_regs : 0x07d0f034
Address@gxc_gpec04_regs : 0x07d13034
Address@gxc_gpec05_regs : 0x07d17034
Address@gxc_gpec06_regs : 0x07d1b034
Address@gxc_gpec07_regs : 0x07d1f034
Address@gxc_gpec10_regs : 0x07d43034
Address@gxc_gpec11_regs : 0x07d47034
Address@gxc_gpec12_regs : 0x07d4b034
Address@gxc_gpec13_regs : 0x07d4f034
Address@gxc_gpec14_regs : 0x07d53034
Address@gxc_gpec15_regs : 0x07d57034
Address@gxc_gpec16_regs : 0x07d5b034
Address@gxc_gpec17_regs : 0x07d5f034
Bits Reset value Name Description
31 - 0 0x0
timer_preload1
read: actual value of timer, write: timer and preload value


gpec_timer2
Timer 2 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank2 with crc_polynom (r/w mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03038
Address@gxc_gpec00_regs : 0x07d03038
Address@gxc_gpec01_regs : 0x07d07038
Address@gxc_gpec02_regs : 0x07d0b038
Address@gxc_gpec03_regs : 0x07d0f038
Address@gxc_gpec04_regs : 0x07d13038
Address@gxc_gpec05_regs : 0x07d17038
Address@gxc_gpec06_regs : 0x07d1b038
Address@gxc_gpec07_regs : 0x07d1f038
Address@gxc_gpec10_regs : 0x07d43038
Address@gxc_gpec11_regs : 0x07d47038
Address@gxc_gpec12_regs : 0x07d4b038
Address@gxc_gpec13_regs : 0x07d4f038
Address@gxc_gpec14_regs : 0x07d53038
Address@gxc_gpec15_regs : 0x07d57038
Address@gxc_gpec16_regs : 0x07d5b038
Address@gxc_gpec17_regs : 0x07d5f038
Bits Reset value Name Description
31 - 0 0x0
timer_preload2
read: actual value of timer, write: timer and preload value


gpec_timer3
Timer 3 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank2 with crc_cfg (r/w mode).
crc_cfg[10]    = crc_invert
crc_cfg[9]     = crc_zero
crc_cfg[8]     = reserved
crc_cfg[7]     = crc_shift_right
crc_cfg[6]     = crc_swap_output
crc_cfg[5]     = crc_direct_div
crc_cfg[4:0]   = crc_length
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0303c
Address@gxc_gpec00_regs : 0x07d0303c
Address@gxc_gpec01_regs : 0x07d0703c
Address@gxc_gpec02_regs : 0x07d0b03c
Address@gxc_gpec03_regs : 0x07d0f03c
Address@gxc_gpec04_regs : 0x07d1303c
Address@gxc_gpec05_regs : 0x07d1703c
Address@gxc_gpec06_regs : 0x07d1b03c
Address@gxc_gpec07_regs : 0x07d1f03c
Address@gxc_gpec10_regs : 0x07d4303c
Address@gxc_gpec11_regs : 0x07d4703c
Address@gxc_gpec12_regs : 0x07d4b03c
Address@gxc_gpec13_regs : 0x07d4f03c
Address@gxc_gpec14_regs : 0x07d5303c
Address@gxc_gpec15_regs : 0x07d5703c
Address@gxc_gpec16_regs : 0x07d5b03c
Address@gxc_gpec17_regs : 0x07d5f03c
Bits Reset value Name Description
31 - 0 0x0
timer_preload3
read: actual value of timer, write: timer and preload value


gpec_timer4
Timer 4 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank2 with queue_nempty_man (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
 15 - 0    : val      #  one select bit per FIFO
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03040
Address@gxc_gpec00_regs : 0x07d03040
Address@gxc_gpec01_regs : 0x07d07040
Address@gxc_gpec02_regs : 0x07d0b040
Address@gxc_gpec03_regs : 0x07d0f040
Address@gxc_gpec04_regs : 0x07d13040
Address@gxc_gpec05_regs : 0x07d17040
Address@gxc_gpec06_regs : 0x07d1b040
Address@gxc_gpec07_regs : 0x07d1f040
Address@gxc_gpec10_regs : 0x07d43040
Address@gxc_gpec11_regs : 0x07d47040
Address@gxc_gpec12_regs : 0x07d4b040
Address@gxc_gpec13_regs : 0x07d4f040
Address@gxc_gpec14_regs : 0x07d53040
Address@gxc_gpec15_regs : 0x07d57040
Address@gxc_gpec16_regs : 0x07d5b040
Address@gxc_gpec17_regs : 0x07d5f040
Bits Reset value Name Description
31 - 0 0x0
timer_preload4
read: actual value of timer, write: timer and preload value


gpec_timer5
Timer 5 Register
Timer mode is programmed in gpec_config.

Shared in gpec regmode_bank1 with urx_last (r mode).
Latches last read and taken out value from any URX(E) FIFO. Sniffing a URX(E) doesn't update urx_last.

Shared in gpec regmode_bank2 with axi_base_config (r/w mode).
     31    : axi_reset                   # reset AXI channel state machine and FIFOs, write 1 and release reset with write 0. AXI has to be rdy (at least 1 cc) to recognize reset. # default 0
     27    : axi_wr_rdy_timer2small      # read only debug status, set to one if axi_wr_rdy event goes up after axi_wr_rdy timer expired; write one to reset flag. # default 0
     26    : axi_wr_mode                 # default 1
           : #       1'b0 : normal access
           : #       1'b1 : auto post-inc (for offset_addr)
25 - 20    : axi_wr_rdy_timer            #  0: axi_write_rdy signal generated after access finished
           :                             #  1..63: axi_write_rdy generated x cc after access started (set to worst case value; used to get determistic PEC program flow)
19 - 16    : axi_wr_base_addr            # upper 5 bits of axi write Address # default 0
     12    : axi_rd_auto_reset_data_fifo # auto reset axi read fifo on adr_gpec_axi_rd_cfg write # default 0
     11    : axi_rd_rdy_timer2small      # read only debug status, set to one if axi_rd_rdy event goes up after axi_rd_rdy timer expired; write one to reset flag. # default 0
     10    : axi_rd_mode                 # default 1
           : #       1'b0 : normal access
           : #       1'b1 : auto post-inc (for offset_addr)
 9 - 4     : axi_rd_rdy_timer            #  0: axi_read_rdy signal generated after access finished
           :                             #  1..63: axi_read_rdy generated x cc after access started (set to worst case value; used to get determistic PEC program flow)
  3 - 0    : axi_rd_base_addr            # upper 5 bits of axi read Address # default 0
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03044
Address@gxc_gpec00_regs : 0x07d03044
Address@gxc_gpec01_regs : 0x07d07044
Address@gxc_gpec02_regs : 0x07d0b044
Address@gxc_gpec03_regs : 0x07d0f044
Address@gxc_gpec04_regs : 0x07d13044
Address@gxc_gpec05_regs : 0x07d17044
Address@gxc_gpec06_regs : 0x07d1b044
Address@gxc_gpec07_regs : 0x07d1f044
Address@gxc_gpec10_regs : 0x07d43044
Address@gxc_gpec11_regs : 0x07d47044
Address@gxc_gpec12_regs : 0x07d4b044
Address@gxc_gpec13_regs : 0x07d4f044
Address@gxc_gpec14_regs : 0x07d53044
Address@gxc_gpec15_regs : 0x07d57044
Address@gxc_gpec16_regs : 0x07d5b044
Address@gxc_gpec17_regs : 0x07d5f044
Bits Reset value Name Description
31 - 0 0x0
timer_preload5
read: actual value of timer, write: timer and preload value


gpec_urx_count
URX(E) and UTX(E) Counter Register

Shared in gpec regmode_bank1 with utx_count (r/w mode).

Shared in gpec regmode_bank2 with axi_rd_msk (r/w mode).
  27 -  0  : val        # address mask: bits set to one are not changed by auto increment
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03048
Address@gxc_gpec00_regs : 0x07d03048
Address@gxc_gpec01_regs : 0x07d07048
Address@gxc_gpec02_regs : 0x07d0b048
Address@gxc_gpec03_regs : 0x07d0f048
Address@gxc_gpec04_regs : 0x07d13048
Address@gxc_gpec05_regs : 0x07d17048
Address@gxc_gpec06_regs : 0x07d1b048
Address@gxc_gpec07_regs : 0x07d1f048
Address@gxc_gpec10_regs : 0x07d43048
Address@gxc_gpec11_regs : 0x07d47048
Address@gxc_gpec12_regs : 0x07d4b048
Address@gxc_gpec13_regs : 0x07d4f048
Address@gxc_gpec14_regs : 0x07d53048
Address@gxc_gpec15_regs : 0x07d57048
Address@gxc_gpec16_regs : 0x07d5b048
Address@gxc_gpec17_regs : 0x07d5f048
Bits Reset value Name Description
31 - 16 0x0
urxe_count
in regmode bank 1 utxe_count
counts up accesses of gpec to any URXE/UTXE FIFO
15 - 0 0x0
urx_count
in regmode bank 1 utx_count
counts up accesses of gpec to any URX/UTX FIFO


gpec_axi_data
AXI Data Register
The gpec read-after-write register bypass is deactivated for this register.
Write:
  gpec04/14:  16 * 32 Bit FIFO
  other gpecs: 8 * 32 Bit FIFO
Read:
  gpec06/16:  16 * 32 Bit FIFO
  other gpecs: 8 * 32 Bit FIFO
Sniffer mode is supported for gpec read accesses. In sniffer mode the read data is not withdrawn from the FIFO.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0304c
Address@gxc_gpec00_regs : 0x07d0304c
Address@gxc_gpec01_regs : 0x07d0704c
Address@gxc_gpec02_regs : 0x07d0b04c
Address@gxc_gpec03_regs : 0x07d0f04c
Address@gxc_gpec04_regs : 0x07d1304c
Address@gxc_gpec05_regs : 0x07d1704c
Address@gxc_gpec06_regs : 0x07d1b04c
Address@gxc_gpec07_regs : 0x07d1f04c
Address@gxc_gpec10_regs : 0x07d4304c
Address@gxc_gpec11_regs : 0x07d4704c
Address@gxc_gpec12_regs : 0x07d4b04c
Address@gxc_gpec13_regs : 0x07d4f04c
Address@gxc_gpec14_regs : 0x07d5304c
Address@gxc_gpec15_regs : 0x07d5704c
Address@gxc_gpec16_regs : 0x07d5b04c
Address@gxc_gpec17_regs : 0x07d5f04c
Bits Reset value Name Description
31 - 0 0x0
val
read: pop element from AXI read FIFO, write: push element to AXI write FIFO


gpec_pc
Program Counter Register
R/W
0x000007ff
Address@gxc_gpec_regs : 0x07c03050
Address@gxc_gpec00_regs : 0x07d03050
Address@gxc_gpec01_regs : 0x07d07050
Address@gxc_gpec02_regs : 0x07d0b050
Address@gxc_gpec03_regs : 0x07d0f050
Address@gxc_gpec04_regs : 0x07d13050
Address@gxc_gpec05_regs : 0x07d17050
Address@gxc_gpec06_regs : 0x07d1b050
Address@gxc_gpec07_regs : 0x07d1f050
Address@gxc_gpec10_regs : 0x07d43050
Address@gxc_gpec11_regs : 0x07d47050
Address@gxc_gpec12_regs : 0x07d4b050
Address@gxc_gpec13_regs : 0x07d4f050
Address@gxc_gpec14_regs : 0x07d53050
Address@gxc_gpec15_regs : 0x07d57050
Address@gxc_gpec16_regs : 0x07d5b050
Address@gxc_gpec17_regs : 0x07d5f050
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 0 0x7ff
pc
gpec Program Counter (dword address inside DPRAM)


gpec_zero
Zero Register
The gpec read-after-write register bypass is deactivated for this register.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03054
Address@gxc_gpec00_regs : 0x07d03054
Address@gxc_gpec01_regs : 0x07d07054
Address@gxc_gpec02_regs : 0x07d0b054
Address@gxc_gpec03_regs : 0x07d0f054
Address@gxc_gpec04_regs : 0x07d13054
Address@gxc_gpec05_regs : 0x07d17054
Address@gxc_gpec06_regs : 0x07d1b054
Address@gxc_gpec07_regs : 0x07d1f054
Address@gxc_gpec10_regs : 0x07d43054
Address@gxc_gpec11_regs : 0x07d47054
Address@gxc_gpec12_regs : 0x07d4b054
Address@gxc_gpec13_regs : 0x07d4f054
Address@gxc_gpec14_regs : 0x07d53054
Address@gxc_gpec15_regs : 0x07d57054
Address@gxc_gpec16_regs : 0x07d5b054
Address@gxc_gpec17_regs : 0x07d5f054
Bits Reset value Name Description
31 - 0 0x0
zero
Always Zero


gpec_config
Configuration Register
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03058
Address@gxc_gpec00_regs : 0x07d03058
Address@gxc_gpec01_regs : 0x07d07058
Address@gxc_gpec02_regs : 0x07d0b058
Address@gxc_gpec03_regs : 0x07d0f058
Address@gxc_gpec04_regs : 0x07d13058
Address@gxc_gpec05_regs : 0x07d17058
Address@gxc_gpec06_regs : 0x07d1b058
Address@gxc_gpec07_regs : 0x07d1f058
Address@gxc_gpec10_regs : 0x07d43058
Address@gxc_gpec11_regs : 0x07d47058
Address@gxc_gpec12_regs : 0x07d4b058
Address@gxc_gpec13_regs : 0x07d4f058
Address@gxc_gpec14_regs : 0x07d53058
Address@gxc_gpec15_regs : 0x07d57058
Address@gxc_gpec16_regs : 0x07d5b058
Address@gxc_gpec17_regs : 0x07d5f058
Bits Reset value Name Description
31 - 30 "00"
register_mode
Register Mode
after changing register mode use nop for read instruction, not necessary for write instruction
      2'b00 : regmode_bank0 / normal
      2'b01 : regmode_bank1
      2'b10 : regmode_bank2
      2'b11 : reserved
29 - 27 "000"
frame_cmp_status
readonly: nr of lowest matching compare channel (see frame_cmp_config64)
     0..5 : matching channel
        7 : no match
     Attention: The dp_regs are undefined after reset. All dp_regs must be initialized for the comparison logic to work.
                After writing the input value, a "nop" command is required before the gpec_config becomes valid.
26 - 23 "0000"
usr
software defined value
22 "0"
frame_cmp_config64
1'b0 32 bit compare, 1'b1 64 bit compare
     32 bit mode compares input (dp_regs[12]) with 6 channels:
       channel 0: (input & dp_regs[10]) == dp_regs[11]
       channel 1: (input & dp_regs[ 8]) == dp_regs[ 9]
       channel 2: (input & dp_regs[ 6]) == dp_regs[ 7]
       channel 3: (input & dp_regs[ 4]) == dp_regs[ 5]
       channel 4: (input & dp_regs[ 2]) == dp_regs[ 3]
       channel 5: (input & dp_regs[ 0]) == dp_regs[ 1]
     64 bit mode compares input (dp_regs[13,12]) with 3 channels:
       channel 0: (input & dp_regs[10, 8]) == dp_regs[11, 9]
       channel 1: (input & dp_regs[ 6, 4]) == dp_regs[ 7, 5]
       channel 2: (input & dp_regs[ 2, 0]) == dp_regs[ 3, 1]
     Note: Use lower channels if not using all channels to avoid faulty matches
21 - 18 "0000"
event
event
17 - 15 "000"
timer5
timer 5 mode, see timer0
14 - 12 "000"
timer4
timer 4 mode, see timer0
11 - 9 "000"
timer3
timer 3 mode, see timer0
8 - 6 "000"
timer2
timer 2 mode, see timer0
5 - 3 "000"
timer1
timer 1 mode, see timer0
2 - 0 "000"
timer0
timer 0 mode
      2'b000 : Timer stops at 0
      2'b001 : Timer is preload with value from preload register at 0
      2'b010 : Timer (value) compare with systime
      2'b110 : Timer (value) compare with counter
      2'b111 : Timer is workregister


gpec_ec_mask0
Event Controller Mask Register 0
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c0305c
Address@gxc_gpec00_regs : 0x07d0305c
Address@gxc_gpec01_regs : 0x07d0705c
Address@gxc_gpec02_regs : 0x07d0b05c
Address@gxc_gpec03_regs : 0x07d0f05c
Address@gxc_gpec04_regs : 0x07d1305c
Address@gxc_gpec05_regs : 0x07d1705c
Address@gxc_gpec06_regs : 0x07d1b05c
Address@gxc_gpec07_regs : 0x07d1f05c
Address@gxc_gpec10_regs : 0x07d4305c
Address@gxc_gpec11_regs : 0x07d4705c
Address@gxc_gpec12_regs : 0x07d4b05c
Address@gxc_gpec13_regs : 0x07d4f05c
Address@gxc_gpec14_regs : 0x07d5305c
Address@gxc_gpec15_regs : 0x07d5705c
Address@gxc_gpec16_regs : 0x07d5b05c
Address@gxc_gpec17_regs : 0x07d5f05c
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask1
Event Controller Mask Register 1
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03060
Address@gxc_gpec00_regs : 0x07d03060
Address@gxc_gpec01_regs : 0x07d07060
Address@gxc_gpec02_regs : 0x07d0b060
Address@gxc_gpec03_regs : 0x07d0f060
Address@gxc_gpec04_regs : 0x07d13060
Address@gxc_gpec05_regs : 0x07d17060
Address@gxc_gpec06_regs : 0x07d1b060
Address@gxc_gpec07_regs : 0x07d1f060
Address@gxc_gpec10_regs : 0x07d43060
Address@gxc_gpec11_regs : 0x07d47060
Address@gxc_gpec12_regs : 0x07d4b060
Address@gxc_gpec13_regs : 0x07d4f060
Address@gxc_gpec14_regs : 0x07d53060
Address@gxc_gpec15_regs : 0x07d57060
Address@gxc_gpec16_regs : 0x07d5b060
Address@gxc_gpec17_regs : 0x07d5f060
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask2
Event Controller Mask Register 2
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03064
Address@gxc_gpec00_regs : 0x07d03064
Address@gxc_gpec01_regs : 0x07d07064
Address@gxc_gpec02_regs : 0x07d0b064
Address@gxc_gpec03_regs : 0x07d0f064
Address@gxc_gpec04_regs : 0x07d13064
Address@gxc_gpec05_regs : 0x07d17064
Address@gxc_gpec06_regs : 0x07d1b064
Address@gxc_gpec07_regs : 0x07d1f064
Address@gxc_gpec10_regs : 0x07d43064
Address@gxc_gpec11_regs : 0x07d47064
Address@gxc_gpec12_regs : 0x07d4b064
Address@gxc_gpec13_regs : 0x07d4f064
Address@gxc_gpec14_regs : 0x07d53064
Address@gxc_gpec15_regs : 0x07d57064
Address@gxc_gpec16_regs : 0x07d5b064
Address@gxc_gpec17_regs : 0x07d5f064
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask3
Event Controller Mask Register 3
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03068
Address@gxc_gpec00_regs : 0x07d03068
Address@gxc_gpec01_regs : 0x07d07068
Address@gxc_gpec02_regs : 0x07d0b068
Address@gxc_gpec03_regs : 0x07d0f068
Address@gxc_gpec04_regs : 0x07d13068
Address@gxc_gpec05_regs : 0x07d17068
Address@gxc_gpec06_regs : 0x07d1b068
Address@gxc_gpec07_regs : 0x07d1f068
Address@gxc_gpec10_regs : 0x07d43068
Address@gxc_gpec11_regs : 0x07d47068
Address@gxc_gpec12_regs : 0x07d4b068
Address@gxc_gpec13_regs : 0x07d4f068
Address@gxc_gpec14_regs : 0x07d53068
Address@gxc_gpec15_regs : 0x07d57068
Address@gxc_gpec16_regs : 0x07d5b068
Address@gxc_gpec17_regs : 0x07d5f068
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask4
Event Controller Mask Register 4
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c0306c
Address@gxc_gpec00_regs : 0x07d0306c
Address@gxc_gpec01_regs : 0x07d0706c
Address@gxc_gpec02_regs : 0x07d0b06c
Address@gxc_gpec03_regs : 0x07d0f06c
Address@gxc_gpec04_regs : 0x07d1306c
Address@gxc_gpec05_regs : 0x07d1706c
Address@gxc_gpec06_regs : 0x07d1b06c
Address@gxc_gpec07_regs : 0x07d1f06c
Address@gxc_gpec10_regs : 0x07d4306c
Address@gxc_gpec11_regs : 0x07d4706c
Address@gxc_gpec12_regs : 0x07d4b06c
Address@gxc_gpec13_regs : 0x07d4f06c
Address@gxc_gpec14_regs : 0x07d5306c
Address@gxc_gpec15_regs : 0x07d5706c
Address@gxc_gpec16_regs : 0x07d5b06c
Address@gxc_gpec17_regs : 0x07d5f06c
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask5
Event Controller Mask Register 5
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03070
Address@gxc_gpec00_regs : 0x07d03070
Address@gxc_gpec01_regs : 0x07d07070
Address@gxc_gpec02_regs : 0x07d0b070
Address@gxc_gpec03_regs : 0x07d0f070
Address@gxc_gpec04_regs : 0x07d13070
Address@gxc_gpec05_regs : 0x07d17070
Address@gxc_gpec06_regs : 0x07d1b070
Address@gxc_gpec07_regs : 0x07d1f070
Address@gxc_gpec10_regs : 0x07d43070
Address@gxc_gpec11_regs : 0x07d47070
Address@gxc_gpec12_regs : 0x07d4b070
Address@gxc_gpec13_regs : 0x07d4f070
Address@gxc_gpec14_regs : 0x07d53070
Address@gxc_gpec15_regs : 0x07d57070
Address@gxc_gpec16_regs : 0x07d5b070
Address@gxc_gpec17_regs : 0x07d5f070
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask6
Event Controller Mask Register 6

Shared in gpec regmode_bank1 with ecat_event_req_masked (r mode).
Read access returns ethercat_reg79[15:0] & ethercat_reg44[15:0].
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03074
Address@gxc_gpec00_regs : 0x07d03074
Address@gxc_gpec01_regs : 0x07d07074
Address@gxc_gpec02_regs : 0x07d0b074
Address@gxc_gpec03_regs : 0x07d0f074
Address@gxc_gpec04_regs : 0x07d13074
Address@gxc_gpec05_regs : 0x07d17074
Address@gxc_gpec06_regs : 0x07d1b074
Address@gxc_gpec07_regs : 0x07d1f074
Address@gxc_gpec10_regs : 0x07d43074
Address@gxc_gpec11_regs : 0x07d47074
Address@gxc_gpec12_regs : 0x07d4b074
Address@gxc_gpec13_regs : 0x07d4f074
Address@gxc_gpec14_regs : 0x07d53074
Address@gxc_gpec15_regs : 0x07d57074
Address@gxc_gpec16_regs : 0x07d5b074
Address@gxc_gpec17_regs : 0x07d5f074
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_ec_mask7
Event Controller Mask Register 7

Shared in gpec regmode_bank1 with sm_write_read_buf_full (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
read: sm_write_read_buf_full = {sm_last_byte_addressed[7:0],sm_last_byte_addressed[7:0],sm_last_byte_addressed[7:0],sm_last_byte_addressed[7:0]}
write: sm_write_read_buf_full:
       31:24 : clear sm_buf_full
       23:16 : set sm_buf_full
        15:8 : set sm_read_event
         7:0 : set sm_write_event
R/W
0x0000ffff
Address@gxc_gpec_regs : 0x07c03078
Address@gxc_gpec00_regs : 0x07d03078
Address@gxc_gpec01_regs : 0x07d07078
Address@gxc_gpec02_regs : 0x07d0b078
Address@gxc_gpec03_regs : 0x07d0f078
Address@gxc_gpec04_regs : 0x07d13078
Address@gxc_gpec05_regs : 0x07d17078
Address@gxc_gpec06_regs : 0x07d1b078
Address@gxc_gpec07_regs : 0x07d1f078
Address@gxc_gpec10_regs : 0x07d43078
Address@gxc_gpec11_regs : 0x07d47078
Address@gxc_gpec12_regs : 0x07d4b078
Address@gxc_gpec13_regs : 0x07d4f078
Address@gxc_gpec14_regs : 0x07d53078
Address@gxc_gpec15_regs : 0x07d57078
Address@gxc_gpec16_regs : 0x07d5b078
Address@gxc_gpec17_regs : 0x07d5f078
Bits Reset value Name Description
31 "0"
and_or
and/or bit:
0 - All bits of mask must fit with events,
1 - Only one bit of mask must fit with events # default 0
30 - 29 "00"
level_edge_event1
for event 1 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
28 - 27 "00"
level_edge_event0
for event 0 : level / edge sensitive:
              2'b00 sensitve to 1 level
              2'b01 sensitve to 0 level
              2'b10 sensitve to positive edge (low to high)
              2'b11 sensitve to negative edge (high to low)
26 0
-
 reserved
25 - 16 0x0
jmp_adr
jmp address (0-1023)
15 - 8 "11111111"
sel1
Select of event 1
7 - 0 "11111111"
sel0
Select of event 0


gpec_pfifo_mask
Pointer FIFO Mask Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank1 with utx0_32 (w mode).
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with ec_mask8 (r/w mode).
The gpec read-after-write register bypass is deactivated for this register.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0307c
Address@gxc_gpec00_regs : 0x07d0307c
Address@gxc_gpec01_regs : 0x07d0707c
Address@gxc_gpec02_regs : 0x07d0b07c
Address@gxc_gpec03_regs : 0x07d0f07c
Address@gxc_gpec04_regs : 0x07d1307c
Address@gxc_gpec05_regs : 0x07d1707c
Address@gxc_gpec06_regs : 0x07d1b07c
Address@gxc_gpec07_regs : 0x07d1f07c
Address@gxc_gpec10_regs : 0x07d4307c
Address@gxc_gpec11_regs : 0x07d4707c
Address@gxc_gpec12_regs : 0x07d4b07c
Address@gxc_gpec13_regs : 0x07d4f07c
Address@gxc_gpec14_regs : 0x07d5307c
Address@gxc_gpec15_regs : 0x07d5707c
Address@gxc_gpec16_regs : 0x07d5b07c
Address@gxc_gpec17_regs : 0x07d5f07c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
PFIFO nempty mask


gpec_pfifo_cfg
Pointer FIFO Configuration Register
The gpec read-after-write register bypass is deactivated for this register.
Configuration of the pfifo instance that is connected to the gpec issuing the read/write request.
When reading this register, the following values are returned:
31 - 24 : bucket_nempty[7:0] of token bucket instance 1
23 - 16 : bucket_nempty[7:0] of token bucket instance 0
15 - 00 : pfifo_irq[15:0]

Shared in gpec regmode_bank1 with utxe0_32 (w mode).
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with ec_mask9 (r/w mode).
The gpec read-after-write register bypass is deactivated for this register.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03080
Address@gxc_gpec00_regs : 0x07d03080
Address@gxc_gpec01_regs : 0x07d07080
Address@gxc_gpec02_regs : 0x07d0b080
Address@gxc_gpec03_regs : 0x07d0f080
Address@gxc_gpec04_regs : 0x07d13080
Address@gxc_gpec05_regs : 0x07d17080
Address@gxc_gpec06_regs : 0x07d1b080
Address@gxc_gpec07_regs : 0x07d1f080
Address@gxc_gpec10_regs : 0x07d43080
Address@gxc_gpec11_regs : 0x07d47080
Address@gxc_gpec12_regs : 0x07d4b080
Address@gxc_gpec13_regs : 0x07d4f080
Address@gxc_gpec14_regs : 0x07d53080
Address@gxc_gpec15_regs : 0x07d57080
Address@gxc_gpec16_regs : 0x07d5b080
Address@gxc_gpec17_regs : 0x07d5f080
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
inst
token bucket instance select (write-only)
22 - 20 "000"
bucket_sel
bucket number to issue the request to (write-only)
19 "0"
set_busy
write-one-to-set busy flag (write-only)
18 "0"
clr_busy
write-one-to-clear busy flag (write-only)
17 - 0 0x0
decrement
number of tokens to decrement from the bucket (write-only)


gpec_lut_bits
Look-Up Table Bits Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank1 with utx1_32 (w mode).
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with ec_maska (r/w mode).
The gpec read-after-write register bypass is deactivated for this register.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03084
Address@gxc_gpec00_regs : 0x07d03084
Address@gxc_gpec01_regs : 0x07d07084
Address@gxc_gpec02_regs : 0x07d0b084
Address@gxc_gpec03_regs : 0x07d0f084
Address@gxc_gpec04_regs : 0x07d13084
Address@gxc_gpec05_regs : 0x07d17084
Address@gxc_gpec06_regs : 0x07d1b084
Address@gxc_gpec07_regs : 0x07d1f084
Address@gxc_gpec10_regs : 0x07d43084
Address@gxc_gpec11_regs : 0x07d47084
Address@gxc_gpec12_regs : 0x07d4b084
Address@gxc_gpec13_regs : 0x07d4f084
Address@gxc_gpec14_regs : 0x07d53084
Address@gxc_gpec15_regs : 0x07d57084
Address@gxc_gpec16_regs : 0x07d5b084
Address@gxc_gpec17_regs : 0x07d5f084
Bits Reset value Name Description
31 - 16 0x0
lut_out
read: LUT output, write: write_mask for lut_in
15 - 0 0x0
lut_in
software defined LUT input bits


gpec_crc_data
CRC Data Register

Shared in gpec regmode_bank1 with utxe1_32 (w mode).
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.

Shared in gpec regmode_bank2 with ec_maskb (r/w mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03088
Address@gxc_gpec00_regs : 0x07d03088
Address@gxc_gpec01_regs : 0x07d07088
Address@gxc_gpec02_regs : 0x07d0b088
Address@gxc_gpec03_regs : 0x07d0f088
Address@gxc_gpec04_regs : 0x07d13088
Address@gxc_gpec05_regs : 0x07d17088
Address@gxc_gpec06_regs : 0x07d1b088
Address@gxc_gpec07_regs : 0x07d1f088
Address@gxc_gpec10_regs : 0x07d43088
Address@gxc_gpec11_regs : 0x07d47088
Address@gxc_gpec12_regs : 0x07d4b088
Address@gxc_gpec13_regs : 0x07d4f088
Address@gxc_gpec14_regs : 0x07d53088
Address@gxc_gpec15_regs : 0x07d57088
Address@gxc_gpec16_regs : 0x07d5b088
Address@gxc_gpec17_regs : 0x07d5f088
Bits Reset value Name Description
31 - 0 0x0
val
current crc value


gpec_irq
IRQ Register
This register has an additional write pipeline delay of 1 clock cycle.
Interface register to gxc_gpec_irq module of the corresponding gxc port.
Write access sets bits in gxc_gpec_irq.irq_raw (write-one-to-set).
W
0x00000000
Address@gxc_gpec_regs : 0x07c0308c
Address@gxc_gpec00_regs : 0x07d0308c
Address@gxc_gpec01_regs : 0x07d0708c
Address@gxc_gpec02_regs : 0x07d0b08c
Address@gxc_gpec03_regs : 0x07d0f08c
Address@gxc_gpec04_regs : 0x07d1308c
Address@gxc_gpec05_regs : 0x07d1708c
Address@gxc_gpec06_regs : 0x07d1b08c
Address@gxc_gpec07_regs : 0x07d1f08c
Address@gxc_gpec10_regs : 0x07d4308c
Address@gxc_gpec11_regs : 0x07d4708c
Address@gxc_gpec12_regs : 0x07d4b08c
Address@gxc_gpec13_regs : 0x07d4f08c
Address@gxc_gpec14_regs : 0x07d5308c
Address@gxc_gpec15_regs : 0x07d5708c
Address@gxc_gpec16_regs : 0x07d5b08c
Address@gxc_gpec17_regs : 0x07d5f08c
Bits Reset value Name Description
31 - 0 0x0
val
gpec IRQ bit vector


gpec_systime
System Time Register
Read access return systime_ns or systime_s depending on the following Latching FSM:
  State Init: Read returns systime_ns and latch systime_s, next state: Latched
  State Latched: Read returns latched systime_s, next state: Init
Sniffer mode is supported for gpec read accesses. In sniffer mode the Latching FSM does not change the state and systime_s is not latched.

Shared in gpec regmode_bank1 with gmac_tpu_systime (r mode).

Shared in gpec regmode_bank2 with gmac_tpu_systime_phy (r mode).
R
Address@gxc_gpec_regs : 0x07c03090
Address@gxc_gpec00_regs : 0x07d03090
Address@gxc_gpec01_regs : 0x07d07090
Address@gxc_gpec02_regs : 0x07d0b090
Address@gxc_gpec03_regs : 0x07d0f090
Address@gxc_gpec04_regs : 0x07d13090
Address@gxc_gpec05_regs : 0x07d17090
Address@gxc_gpec06_regs : 0x07d1b090
Address@gxc_gpec07_regs : 0x07d1f090
Address@gxc_gpec10_regs : 0x07d43090
Address@gxc_gpec11_regs : 0x07d47090
Address@gxc_gpec12_regs : 0x07d4b090
Address@gxc_gpec13_regs : 0x07d4f090
Address@gxc_gpec14_regs : 0x07d53090
Address@gxc_gpec15_regs : 0x07d57090
Address@gxc_gpec16_regs : 0x07d5b090
Address@gxc_gpec17_regs : 0x07d5f090
Bits Name Description
31 - 0 val
systime_ns or systime_s (see above)


gpec_counter
System Counter Register
Read access return counter_lo or counter_hi depending on the following Latching FSM:
  State Init: Read returns counter_lo and latch counter_hi, next state: Latched
  State Latched: Read returns latched counter_hi, next state: Init
Sniffer mode is supported for gpec read accesses. In sniffer mode the Latching FSM does not change the state and counter_hi is not latched.

Shared in gpec regmode_bank1 with gmac_tpu_counter (r mode).

Shared in gpec regmode_bank2 with gmac_tpu_counter_phy (r mode).
R
Address@gxc_gpec_regs : 0x07c03094
Address@gxc_gpec00_regs : 0x07d03094
Address@gxc_gpec01_regs : 0x07d07094
Address@gxc_gpec02_regs : 0x07d0b094
Address@gxc_gpec03_regs : 0x07d0f094
Address@gxc_gpec04_regs : 0x07d13094
Address@gxc_gpec05_regs : 0x07d17094
Address@gxc_gpec06_regs : 0x07d1b094
Address@gxc_gpec07_regs : 0x07d1f094
Address@gxc_gpec10_regs : 0x07d43094
Address@gxc_gpec11_regs : 0x07d47094
Address@gxc_gpec12_regs : 0x07d4b094
Address@gxc_gpec13_regs : 0x07d4f094
Address@gxc_gpec14_regs : 0x07d53094
Address@gxc_gpec15_regs : 0x07d57094
Address@gxc_gpec16_regs : 0x07d5b094
Address@gxc_gpec17_regs : 0x07d5f094
Bits Name Description
31 - 0 val
counter_lo or counter_hi (see above)


gpec_fifo_data
Pointer FIFO Data Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c03098
Address@gxc_gpec00_regs : 0x07d03098
Address@gxc_gpec01_regs : 0x07d07098
Address@gxc_gpec02_regs : 0x07d0b098
Address@gxc_gpec03_regs : 0x07d0f098
Address@gxc_gpec04_regs : 0x07d13098
Address@gxc_gpec05_regs : 0x07d17098
Address@gxc_gpec06_regs : 0x07d1b098
Address@gxc_gpec07_regs : 0x07d1f098
Address@gxc_gpec10_regs : 0x07d43098
Address@gxc_gpec11_regs : 0x07d47098
Address@gxc_gpec12_regs : 0x07d4b098
Address@gxc_gpec13_regs : 0x07d4f098
Address@gxc_gpec14_regs : 0x07d53098
Address@gxc_gpec15_regs : 0x07d57098
Address@gxc_gpec16_regs : 0x07d5b098
Address@gxc_gpec17_regs : 0x07d5f098
Bits Reset value Name Description
31 - 0 0x0
fifo_data
default 0


gpec_host_req
Host Request Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Interface register to gxc_gpec_irq module of the corresponding gxc port.
Read access returns gxc_gpec_irq.host_req_raw & gxc_gpec_irq.host_req_mask.
Write access clears bits in gxc_gpec_irq.host_req_raw (write-one-to-clear).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c0309c
Address@gxc_gpec00_regs : 0x07d0309c
Address@gxc_gpec01_regs : 0x07d0709c
Address@gxc_gpec02_regs : 0x07d0b09c
Address@gxc_gpec03_regs : 0x07d0f09c
Address@gxc_gpec04_regs : 0x07d1309c
Address@gxc_gpec05_regs : 0x07d1709c
Address@gxc_gpec06_regs : 0x07d1b09c
Address@gxc_gpec07_regs : 0x07d1f09c
Address@gxc_gpec10_regs : 0x07d4309c
Address@gxc_gpec11_regs : 0x07d4709c
Address@gxc_gpec12_regs : 0x07d4b09c
Address@gxc_gpec13_regs : 0x07d4f09c
Address@gxc_gpec14_regs : 0x07d5309c
Address@gxc_gpec15_regs : 0x07d5709c
Address@gxc_gpec16_regs : 0x07d5b09c
Address@gxc_gpec17_regs : 0x07d5f09c
Bits Reset value Name Description
31 - 0 0x0
val
host request bit vector


gpec_sr0
Shared Register 0
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with esc_bus_config (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Write access clears working_counter_match.
11 -  0 : esc_bus_adr
     15 : esc_bus_direct_access
26 - 16 : esc_bus_length (reserved in direct access)
29 - 28 : esc_bus_cmd
31 - 30 : esc_bus_mas (2'b00: byte, 2'b01: word, 2'b10: dword) (reserved in non direct access)
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030a0
Address@gxc_gpec00_regs : 0x07d030a0
Address@gxc_gpec01_regs : 0x07d070a0
Address@gxc_gpec02_regs : 0x07d0b0a0
Address@gxc_gpec03_regs : 0x07d0f0a0
Address@gxc_gpec04_regs : 0x07d130a0
Address@gxc_gpec05_regs : 0x07d170a0
Address@gxc_gpec06_regs : 0x07d1b0a0
Address@gxc_gpec07_regs : 0x07d1f0a0
Address@gxc_gpec10_regs : 0x07d430a0
Address@gxc_gpec11_regs : 0x07d470a0
Address@gxc_gpec12_regs : 0x07d4b0a0
Address@gxc_gpec13_regs : 0x07d4f0a0
Address@gxc_gpec14_regs : 0x07d530a0
Address@gxc_gpec15_regs : 0x07d570a0
Address@gxc_gpec16_regs : 0x07d5b0a0
Address@gxc_gpec17_regs : 0x07d5f0a0
Bits Reset value Name Description
31 - 0 0x0
SR0
Shared Register


gpec_sr1
Shared Register 1
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with esc_fcs_ok_wkc_match (r/w mode)
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Write access clears esc_info
  write 1 to this register to copy shadow register content to register
  write 0 to drop shadow register content
Read access returns working_counter_match
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030a4
Address@gxc_gpec00_regs : 0x07d030a4
Address@gxc_gpec01_regs : 0x07d070a4
Address@gxc_gpec02_regs : 0x07d0b0a4
Address@gxc_gpec03_regs : 0x07d0f0a4
Address@gxc_gpec04_regs : 0x07d130a4
Address@gxc_gpec05_regs : 0x07d170a4
Address@gxc_gpec06_regs : 0x07d1b0a4
Address@gxc_gpec07_regs : 0x07d1f0a4
Address@gxc_gpec10_regs : 0x07d430a4
Address@gxc_gpec11_regs : 0x07d470a4
Address@gxc_gpec12_regs : 0x07d4b0a4
Address@gxc_gpec13_regs : 0x07d4f0a4
Address@gxc_gpec14_regs : 0x07d530a4
Address@gxc_gpec15_regs : 0x07d570a4
Address@gxc_gpec16_regs : 0x07d5b0a4
Address@gxc_gpec17_regs : 0x07d5f0a4
Bits Reset value Name Description
31 - 0 0x0
SR1
Shared Register


gpec_sr2
Shared Register 2
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with esc_info (r mode)
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030a8
Address@gxc_gpec00_regs : 0x07d030a8
Address@gxc_gpec01_regs : 0x07d070a8
Address@gxc_gpec02_regs : 0x07d0b0a8
Address@gxc_gpec03_regs : 0x07d0f0a8
Address@gxc_gpec04_regs : 0x07d130a8
Address@gxc_gpec05_regs : 0x07d170a8
Address@gxc_gpec06_regs : 0x07d1b0a8
Address@gxc_gpec07_regs : 0x07d1f0a8
Address@gxc_gpec10_regs : 0x07d430a8
Address@gxc_gpec11_regs : 0x07d470a8
Address@gxc_gpec12_regs : 0x07d4b0a8
Address@gxc_gpec13_regs : 0x07d4f0a8
Address@gxc_gpec14_regs : 0x07d530a8
Address@gxc_gpec15_regs : 0x07d570a8
Address@gxc_gpec16_regs : 0x07d5b0a8
Address@gxc_gpec17_regs : 0x07d5f0a8
Bits Reset value Name Description
31 - 0 0x0
SR2
Shared Register


gpec_sr3
Shared Register 3
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with ecat_station_addr (r mode).
Register only accessible via gpec00 and gpec02.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030ac
Address@gxc_gpec00_regs : 0x07d030ac
Address@gxc_gpec01_regs : 0x07d070ac
Address@gxc_gpec02_regs : 0x07d0b0ac
Address@gxc_gpec03_regs : 0x07d0f0ac
Address@gxc_gpec04_regs : 0x07d130ac
Address@gxc_gpec05_regs : 0x07d170ac
Address@gxc_gpec06_regs : 0x07d1b0ac
Address@gxc_gpec07_regs : 0x07d1f0ac
Address@gxc_gpec10_regs : 0x07d430ac
Address@gxc_gpec11_regs : 0x07d470ac
Address@gxc_gpec12_regs : 0x07d4b0ac
Address@gxc_gpec13_regs : 0x07d4f0ac
Address@gxc_gpec14_regs : 0x07d530ac
Address@gxc_gpec15_regs : 0x07d570ac
Address@gxc_gpec16_regs : 0x07d5b0ac
Address@gxc_gpec17_regs : 0x07d5f0ac
Bits Reset value Name Description
31 - 0 0x0
SR3
Shared Register


gpec_sr4
Shared Register 4
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with ecat_alias_addr (r mode).
Register only accessible via gpec00 and gpec02.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030b0
Address@gxc_gpec00_regs : 0x07d030b0
Address@gxc_gpec01_regs : 0x07d070b0
Address@gxc_gpec02_regs : 0x07d0b0b0
Address@gxc_gpec03_regs : 0x07d0f0b0
Address@gxc_gpec04_regs : 0x07d130b0
Address@gxc_gpec05_regs : 0x07d170b0
Address@gxc_gpec06_regs : 0x07d1b0b0
Address@gxc_gpec07_regs : 0x07d1f0b0
Address@gxc_gpec10_regs : 0x07d430b0
Address@gxc_gpec11_regs : 0x07d470b0
Address@gxc_gpec12_regs : 0x07d4b0b0
Address@gxc_gpec13_regs : 0x07d4f0b0
Address@gxc_gpec14_regs : 0x07d530b0
Address@gxc_gpec15_regs : 0x07d570b0
Address@gxc_gpec16_regs : 0x07d5b0b0
Address@gxc_gpec17_regs : 0x07d5f0b0
Bits Reset value Name Description
31 - 0 0x0
SR4
Shared Register


gpec_sr5
Shared Register 5
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030b4
Address@gxc_gpec00_regs : 0x07d030b4
Address@gxc_gpec01_regs : 0x07d070b4
Address@gxc_gpec02_regs : 0x07d0b0b4
Address@gxc_gpec03_regs : 0x07d0f0b4
Address@gxc_gpec04_regs : 0x07d130b4
Address@gxc_gpec05_regs : 0x07d170b4
Address@gxc_gpec06_regs : 0x07d1b0b4
Address@gxc_gpec07_regs : 0x07d1f0b4
Address@gxc_gpec10_regs : 0x07d430b4
Address@gxc_gpec11_regs : 0x07d470b4
Address@gxc_gpec12_regs : 0x07d4b0b4
Address@gxc_gpec13_regs : 0x07d4f0b4
Address@gxc_gpec14_regs : 0x07d530b4
Address@gxc_gpec15_regs : 0x07d570b4
Address@gxc_gpec16_regs : 0x07d5b0b4
Address@gxc_gpec17_regs : 0x07d5f0b4
Bits Reset value Name Description
31 - 0 0x0
SR5
Shared Register


gpec_sr6
Shared Register 6
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030b8
Address@gxc_gpec00_regs : 0x07d030b8
Address@gxc_gpec01_regs : 0x07d070b8
Address@gxc_gpec02_regs : 0x07d0b0b8
Address@gxc_gpec03_regs : 0x07d0f0b8
Address@gxc_gpec04_regs : 0x07d130b8
Address@gxc_gpec05_regs : 0x07d170b8
Address@gxc_gpec06_regs : 0x07d1b0b8
Address@gxc_gpec07_regs : 0x07d1f0b8
Address@gxc_gpec10_regs : 0x07d430b8
Address@gxc_gpec11_regs : 0x07d470b8
Address@gxc_gpec12_regs : 0x07d4b0b8
Address@gxc_gpec13_regs : 0x07d4f0b8
Address@gxc_gpec14_regs : 0x07d530b8
Address@gxc_gpec15_regs : 0x07d570b8
Address@gxc_gpec16_regs : 0x07d5b0b8
Address@gxc_gpec17_regs : 0x07d5f0b8
Bits Reset value Name Description
31 - 0 0x0
SR6
Shared Register


gpec_sr7
Shared Register 7
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030bc
Address@gxc_gpec00_regs : 0x07d030bc
Address@gxc_gpec01_regs : 0x07d070bc
Address@gxc_gpec02_regs : 0x07d0b0bc
Address@gxc_gpec03_regs : 0x07d0f0bc
Address@gxc_gpec04_regs : 0x07d130bc
Address@gxc_gpec05_regs : 0x07d170bc
Address@gxc_gpec06_regs : 0x07d1b0bc
Address@gxc_gpec07_regs : 0x07d1f0bc
Address@gxc_gpec10_regs : 0x07d430bc
Address@gxc_gpec11_regs : 0x07d470bc
Address@gxc_gpec12_regs : 0x07d4b0bc
Address@gxc_gpec13_regs : 0x07d4f0bc
Address@gxc_gpec14_regs : 0x07d530bc
Address@gxc_gpec15_regs : 0x07d570bc
Address@gxc_gpec16_regs : 0x07d5b0bc
Address@gxc_gpec17_regs : 0x07d5f0bc
Bits Reset value Name Description
31 - 0 0x0
SR7
Shared Register


gpec_sr8
Shared Register 8
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with buf_man (r/w mode).
Register only accessible via gpec00 and gpec10.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with trigger_0_starttime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030c0
Address@gxc_gpec00_regs : 0x07d030c0
Address@gxc_gpec01_regs : 0x07d070c0
Address@gxc_gpec02_regs : 0x07d0b0c0
Address@gxc_gpec03_regs : 0x07d0f0c0
Address@gxc_gpec04_regs : 0x07d130c0
Address@gxc_gpec05_regs : 0x07d170c0
Address@gxc_gpec06_regs : 0x07d1b0c0
Address@gxc_gpec07_regs : 0x07d1f0c0
Address@gxc_gpec10_regs : 0x07d430c0
Address@gxc_gpec11_regs : 0x07d470c0
Address@gxc_gpec12_regs : 0x07d4b0c0
Address@gxc_gpec13_regs : 0x07d4f0c0
Address@gxc_gpec14_regs : 0x07d530c0
Address@gxc_gpec15_regs : 0x07d570c0
Address@gxc_gpec16_regs : 0x07d5b0c0
Address@gxc_gpec17_regs : 0x07d5f0c0
Bits Reset value Name Description
31 - 0 0x0
SR8
Shared Register


gpec_sr9
Shared Register 9
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with fmmusm_len_en (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with trigger_1_starttime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030c4
Address@gxc_gpec00_regs : 0x07d030c4
Address@gxc_gpec01_regs : 0x07d070c4
Address@gxc_gpec02_regs : 0x07d0b0c4
Address@gxc_gpec03_regs : 0x07d0f0c4
Address@gxc_gpec04_regs : 0x07d130c4
Address@gxc_gpec05_regs : 0x07d170c4
Address@gxc_gpec06_regs : 0x07d1b0c4
Address@gxc_gpec07_regs : 0x07d1f0c4
Address@gxc_gpec10_regs : 0x07d430c4
Address@gxc_gpec11_regs : 0x07d470c4
Address@gxc_gpec12_regs : 0x07d4b0c4
Address@gxc_gpec13_regs : 0x07d4f0c4
Address@gxc_gpec14_regs : 0x07d530c4
Address@gxc_gpec15_regs : 0x07d570c4
Address@gxc_gpec16_regs : 0x07d5b0c4
Address@gxc_gpec17_regs : 0x07d5f0c4
Bits Reset value Name Description
31 - 0 0x0
SR9
Shared Register


gpec_sr10
Shared Register 10
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_buf_statcfg (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with sample_0_pos_systime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030c8
Address@gxc_gpec00_regs : 0x07d030c8
Address@gxc_gpec01_regs : 0x07d070c8
Address@gxc_gpec02_regs : 0x07d0b0c8
Address@gxc_gpec03_regs : 0x07d0f0c8
Address@gxc_gpec04_regs : 0x07d130c8
Address@gxc_gpec05_regs : 0x07d170c8
Address@gxc_gpec06_regs : 0x07d1b0c8
Address@gxc_gpec07_regs : 0x07d1f0c8
Address@gxc_gpec10_regs : 0x07d430c8
Address@gxc_gpec11_regs : 0x07d470c8
Address@gxc_gpec12_regs : 0x07d4b0c8
Address@gxc_gpec13_regs : 0x07d4f0c8
Address@gxc_gpec14_regs : 0x07d530c8
Address@gxc_gpec15_regs : 0x07d570c8
Address@gxc_gpec16_regs : 0x07d5b0c8
Address@gxc_gpec17_regs : 0x07d5f0c8
Bits Reset value Name Description
31 - 0 0x0
SR10
Shared Register


gpec_sr11
Shared Register 11
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_read_event (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with sample_0_neg_systime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030cc
Address@gxc_gpec00_regs : 0x07d030cc
Address@gxc_gpec01_regs : 0x07d070cc
Address@gxc_gpec02_regs : 0x07d0b0cc
Address@gxc_gpec03_regs : 0x07d0f0cc
Address@gxc_gpec04_regs : 0x07d130cc
Address@gxc_gpec05_regs : 0x07d170cc
Address@gxc_gpec06_regs : 0x07d1b0cc
Address@gxc_gpec07_regs : 0x07d1f0cc
Address@gxc_gpec10_regs : 0x07d430cc
Address@gxc_gpec11_regs : 0x07d470cc
Address@gxc_gpec12_regs : 0x07d4b0cc
Address@gxc_gpec13_regs : 0x07d4f0cc
Address@gxc_gpec14_regs : 0x07d530cc
Address@gxc_gpec15_regs : 0x07d570cc
Address@gxc_gpec16_regs : 0x07d5b0cc
Address@gxc_gpec17_regs : 0x07d5f0cc
Bits Reset value Name Description
31 - 0 0x0
SR11
Shared Register


gpec_sr12
Shared Register 12
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_write_event (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with sample_1_pos_systime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030d0
Address@gxc_gpec00_regs : 0x07d030d0
Address@gxc_gpec01_regs : 0x07d070d0
Address@gxc_gpec02_regs : 0x07d0b0d0
Address@gxc_gpec03_regs : 0x07d0f0d0
Address@gxc_gpec04_regs : 0x07d130d0
Address@gxc_gpec05_regs : 0x07d170d0
Address@gxc_gpec06_regs : 0x07d1b0d0
Address@gxc_gpec07_regs : 0x07d1f0d0
Address@gxc_gpec10_regs : 0x07d430d0
Address@gxc_gpec11_regs : 0x07d470d0
Address@gxc_gpec12_regs : 0x07d4b0d0
Address@gxc_gpec13_regs : 0x07d4f0d0
Address@gxc_gpec14_regs : 0x07d530d0
Address@gxc_gpec15_regs : 0x07d570d0
Address@gxc_gpec16_regs : 0x07d5b0d0
Address@gxc_gpec17_regs : 0x07d5f0d0
Bits Reset value Name Description
31 - 0 0x0
SR12
Shared Register


gpec_sr13
Shared Register 13
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_first_byte_addressed (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with sample_1_neg_systime_ns (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030d4
Address@gxc_gpec00_regs : 0x07d030d4
Address@gxc_gpec01_regs : 0x07d070d4
Address@gxc_gpec02_regs : 0x07d0b0d4
Address@gxc_gpec03_regs : 0x07d0f0d4
Address@gxc_gpec04_regs : 0x07d130d4
Address@gxc_gpec05_regs : 0x07d170d4
Address@gxc_gpec06_regs : 0x07d1b0d4
Address@gxc_gpec07_regs : 0x07d1f0d4
Address@gxc_gpec10_regs : 0x07d430d4
Address@gxc_gpec11_regs : 0x07d470d4
Address@gxc_gpec12_regs : 0x07d4b0d4
Address@gxc_gpec13_regs : 0x07d4f0d4
Address@gxc_gpec14_regs : 0x07d530d4
Address@gxc_gpec15_regs : 0x07d570d4
Address@gxc_gpec16_regs : 0x07d5b0d4
Address@gxc_gpec17_regs : 0x07d5f0d4
Bits Reset value Name Description
31 - 0 0x0
SR13
Shared Register


gpec_sr14
Shared Register 14
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_last_byte_addressed (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with trigger_sample_status (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030d8
Address@gxc_gpec00_regs : 0x07d030d8
Address@gxc_gpec01_regs : 0x07d070d8
Address@gxc_gpec02_regs : 0x07d0b0d8
Address@gxc_gpec03_regs : 0x07d0f0d8
Address@gxc_gpec04_regs : 0x07d130d8
Address@gxc_gpec05_regs : 0x07d170d8
Address@gxc_gpec06_regs : 0x07d1b0d8
Address@gxc_gpec07_regs : 0x07d1f0d8
Address@gxc_gpec10_regs : 0x07d430d8
Address@gxc_gpec11_regs : 0x07d470d8
Address@gxc_gpec12_regs : 0x07d4b0d8
Address@gxc_gpec13_regs : 0x07d4f0d8
Address@gxc_gpec14_regs : 0x07d530d8
Address@gxc_gpec15_regs : 0x07d570d8
Address@gxc_gpec16_regs : 0x07d5b0d8
Address@gxc_gpec17_regs : 0x07d5f0d8
Bits Reset value Name Description
31 - 0 0x0
SR14
Shared Register


gpec_sr15
Shared Register 15
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Shared work register accessed by all gpecs and all gmacs.

Shared in gpec regmode_bank1 with sm_served (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with fmmusm_status_out (r mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030dc
Address@gxc_gpec00_regs : 0x07d030dc
Address@gxc_gpec01_regs : 0x07d070dc
Address@gxc_gpec02_regs : 0x07d0b0dc
Address@gxc_gpec03_regs : 0x07d0f0dc
Address@gxc_gpec04_regs : 0x07d130dc
Address@gxc_gpec05_regs : 0x07d170dc
Address@gxc_gpec06_regs : 0x07d1b0dc
Address@gxc_gpec07_regs : 0x07d1f0dc
Address@gxc_gpec10_regs : 0x07d430dc
Address@gxc_gpec11_regs : 0x07d470dc
Address@gxc_gpec12_regs : 0x07d4b0dc
Address@gxc_gpec13_regs : 0x07d4f0dc
Address@gxc_gpec14_regs : 0x07d530dc
Address@gxc_gpec15_regs : 0x07d570dc
Address@gxc_gpec16_regs : 0x07d5b0dc
Address@gxc_gpec17_regs : 0x07d5f0dc
Bits Reset value Name Description
31 - 0 0x0
SR15
Shared Register


gpec_statcfg0
gMAC0 Status and Configuration Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 10..14 do not require write masks), but upper 16 bits can have completey independent read functionality.

Shared in gpec regmode_bank1 with esc_data (r/w mode).
The gpec read-after-write register bypass is deactivated for this register.

Shared in gpec regmode_bank2 with host_req_msk_set (w mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030e0
Address@gxc_gpec00_regs : 0x07d030e0
Address@gxc_gpec01_regs : 0x07d070e0
Address@gxc_gpec02_regs : 0x07d0b0e0
Address@gxc_gpec03_regs : 0x07d0f0e0
Address@gxc_gpec04_regs : 0x07d130e0
Address@gxc_gpec05_regs : 0x07d170e0
Address@gxc_gpec06_regs : 0x07d1b0e0
Address@gxc_gpec07_regs : 0x07d1f0e0
Address@gxc_gpec10_regs : 0x07d430e0
Address@gxc_gpec11_regs : 0x07d470e0
Address@gxc_gpec12_regs : 0x07d4b0e0
Address@gxc_gpec13_regs : 0x07d4f0e0
Address@gxc_gpec14_regs : 0x07d530e0
Address@gxc_gpec15_regs : 0x07d570e0
Address@gxc_gpec16_regs : 0x07d5b0e0
Address@gxc_gpec17_regs : 0x07d5f0e0
Bits Reset value Name Description
31 - 0 0x0
val
see gxc_sr_statcfg0


gpec_statcfg1
gMAC1 Status and Configuration Register
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 10..14 do not require write masks), but upper 16 bits can have completey independent read functionality.

Shared in gpec regmode_bank1 with esc_direct_data (r/w mode).
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
for direct read: write esc_bus_config with direct access wait 2cc and read esc_direct_data
for direct write: write esc_direct_data first, write esc_bus_config with direct access

Shared in gpec regmode_bank2 with host_req_msk_rst (w mode).
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030e4
Address@gxc_gpec00_regs : 0x07d030e4
Address@gxc_gpec01_regs : 0x07d070e4
Address@gxc_gpec02_regs : 0x07d0b0e4
Address@gxc_gpec03_regs : 0x07d0f0e4
Address@gxc_gpec04_regs : 0x07d130e4
Address@gxc_gpec05_regs : 0x07d170e4
Address@gxc_gpec06_regs : 0x07d1b0e4
Address@gxc_gpec07_regs : 0x07d1f0e4
Address@gxc_gpec10_regs : 0x07d430e4
Address@gxc_gpec11_regs : 0x07d470e4
Address@gxc_gpec12_regs : 0x07d4b0e4
Address@gxc_gpec13_regs : 0x07d4f0e4
Address@gxc_gpec14_regs : 0x07d530e4
Address@gxc_gpec15_regs : 0x07d570e4
Address@gxc_gpec16_regs : 0x07d5b0e4
Address@gxc_gpec17_regs : 0x07d5f0e4
Bits Reset value Name Description
31 - 0 0x0
val
see gxc_sr_statcfg1


gpec_axi_wr_cfg
AXI Write Configuration Register
data dependence: don not write axi_data after axi_wr_cfg, use nop
Note: access won't start if axi_wr_addr is unaligned
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030e8
Address@gxc_gpec00_regs : 0x07d030e8
Address@gxc_gpec01_regs : 0x07d070e8
Address@gxc_gpec02_regs : 0x07d0b0e8
Address@gxc_gpec03_regs : 0x07d0f0e8
Address@gxc_gpec04_regs : 0x07d130e8
Address@gxc_gpec05_regs : 0x07d170e8
Address@gxc_gpec06_regs : 0x07d1b0e8
Address@gxc_gpec07_regs : 0x07d1f0e8
Address@gxc_gpec10_regs : 0x07d430e8
Address@gxc_gpec11_regs : 0x07d470e8
Address@gxc_gpec12_regs : 0x07d4b0e8
Address@gxc_gpec13_regs : 0x07d4f0e8
Address@gxc_gpec14_regs : 0x07d530e8
Address@gxc_gpec15_regs : 0x07d570e8
Address@gxc_gpec16_regs : 0x07d5b0e8
Address@gxc_gpec17_regs : 0x07d5f0e8
Bits Reset value Name Description
31 "0"
axi_wr_snrdy
read only:  axi_write access not ready
30 - 28 "000"
axi_wr_cfg
access size
      3'b000 : byte access (8 bit) (write access starts with writing axi_data)
      3'b001 : word access (16 bit) (write access starts with writing axi_data)
      3'b010 : dword access (32 bit) (write access starts with writing axi_data)
      3'b011 : 64 bit access (write access starts with 2nd axi_data write)
      3'b100 : 128 bit access (write access starts with 4th axi_data write)
      3'b101 : 256 bit access (write access starts with 8th axi_data write)
      3'b110 : 384 bit access (write access starts with 12th axi_data write)
      3'b111 : 512 bit access (write access starts with 16th axi_data write)
27 - 0 0x0
axi_wr_addr
address


gpec_axi_rd_cfg
AXI Read Configuration Register
data dependence: do not call read_axi after axi_rd_cfg, use nop
Note: access won't start if axi_rd_addr is unaligned
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030ec
Address@gxc_gpec00_regs : 0x07d030ec
Address@gxc_gpec01_regs : 0x07d070ec
Address@gxc_gpec02_regs : 0x07d0b0ec
Address@gxc_gpec03_regs : 0x07d0f0ec
Address@gxc_gpec04_regs : 0x07d130ec
Address@gxc_gpec05_regs : 0x07d170ec
Address@gxc_gpec06_regs : 0x07d1b0ec
Address@gxc_gpec07_regs : 0x07d1f0ec
Address@gxc_gpec10_regs : 0x07d430ec
Address@gxc_gpec11_regs : 0x07d470ec
Address@gxc_gpec12_regs : 0x07d4b0ec
Address@gxc_gpec13_regs : 0x07d4f0ec
Address@gxc_gpec14_regs : 0x07d530ec
Address@gxc_gpec15_regs : 0x07d570ec
Address@gxc_gpec16_regs : 0x07d5b0ec
Address@gxc_gpec17_regs : 0x07d5f0ec
Bits Reset value Name Description
31 "0"
axi_rd_snrdy
write:  1 writes config and start axi access, 0 only writes config
read:  axi_read access not ready
30 - 28 "000"
axi_rd_cfg
access size
      3'b000 : byte access (8 bit)
      3'b001 : word access (16 bit)
      3'b010 : dword access (32 bit)
      3'b011 : 64 bit access
      3'b100 : 128 bit access
      3'b101 : 256 bit access
      3'b110 : 384 bit access
      3'b111 : 512 bit access
27 - 0 0x0
axi_rd_addr
address


gpec_urtx0
gMAC0 URTX Register
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Sniffer mode is supported for gpec read accesses. In sniffer mode the read data is not withdrawn from the FIFO.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030f0
Address@gxc_gpec00_regs : 0x07d030f0
Address@gxc_gpec01_regs : 0x07d070f0
Address@gxc_gpec02_regs : 0x07d0b0f0
Address@gxc_gpec03_regs : 0x07d0f0f0
Address@gxc_gpec04_regs : 0x07d130f0
Address@gxc_gpec05_regs : 0x07d170f0
Address@gxc_gpec06_regs : 0x07d1b0f0
Address@gxc_gpec07_regs : 0x07d1f0f0
Address@gxc_gpec10_regs : 0x07d430f0
Address@gxc_gpec11_regs : 0x07d470f0
Address@gxc_gpec12_regs : 0x07d4b0f0
Address@gxc_gpec13_regs : 0x07d4f0f0
Address@gxc_gpec14_regs : 0x07d530f0
Address@gxc_gpec15_regs : 0x07d570f0
Address@gxc_gpec16_regs : 0x07d5b0f0
Address@gxc_gpec17_regs : 0x07d5f0f0
Bits Reset value Name Description
31 - 0 0x0
urtx0
read access: Lastly received bits (output of URX FIFO)
write access: Bits to be transmitted next (input of UTX FIFO)


gpec_urtx1
gMAC1 URTX Register
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Sniffer mode is supported for gpec read accesses. In sniffer mode the read data is not withdrawn from the FIFO.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030f4
Address@gxc_gpec00_regs : 0x07d030f4
Address@gxc_gpec01_regs : 0x07d070f4
Address@gxc_gpec02_regs : 0x07d0b0f4
Address@gxc_gpec03_regs : 0x07d0f0f4
Address@gxc_gpec04_regs : 0x07d130f4
Address@gxc_gpec05_regs : 0x07d170f4
Address@gxc_gpec06_regs : 0x07d1b0f4
Address@gxc_gpec07_regs : 0x07d1f0f4
Address@gxc_gpec10_regs : 0x07d430f4
Address@gxc_gpec11_regs : 0x07d470f4
Address@gxc_gpec12_regs : 0x07d4b0f4
Address@gxc_gpec13_regs : 0x07d4f0f4
Address@gxc_gpec14_regs : 0x07d530f4
Address@gxc_gpec15_regs : 0x07d570f4
Address@gxc_gpec16_regs : 0x07d5b0f4
Address@gxc_gpec17_regs : 0x07d5f0f4
Bits Reset value Name Description
31 - 0 0x0
urtx1
read access: Lastly received bits (output of URX FIFO)
write access: Bits to be transmitted next (input of UTX FIFO)


gpec_urtxe0
gMAC0 URTXE Register
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Sniffer mode is supported for gpec read accesses. In sniffer mode the read data is not withdrawn from the FIFO.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030f8
Address@gxc_gpec00_regs : 0x07d030f8
Address@gxc_gpec01_regs : 0x07d070f8
Address@gxc_gpec02_regs : 0x07d0b0f8
Address@gxc_gpec03_regs : 0x07d0f0f8
Address@gxc_gpec04_regs : 0x07d130f8
Address@gxc_gpec05_regs : 0x07d170f8
Address@gxc_gpec06_regs : 0x07d1b0f8
Address@gxc_gpec07_regs : 0x07d1f0f8
Address@gxc_gpec10_regs : 0x07d430f8
Address@gxc_gpec11_regs : 0x07d470f8
Address@gxc_gpec12_regs : 0x07d4b0f8
Address@gxc_gpec13_regs : 0x07d4f0f8
Address@gxc_gpec14_regs : 0x07d530f8
Address@gxc_gpec15_regs : 0x07d570f8
Address@gxc_gpec16_regs : 0x07d5b0f8
Address@gxc_gpec17_regs : 0x07d5f0f8
Bits Reset value Name Description
31 - 0 0x0
urtxe0
read access: Lastly received bits (output of URXE FIFO)
write access: Bits to be transmitted next (input of UTXE FIFO)


gpec_urtxe1
gMAC1 URTXE Register
Register only accessible via gpec00..gpec03, gpec10..gpec13.
This register has an additional write pipeline delay of 1 clock cycle.
The gpec read-after-write register bypass is deactivated for this register.
Sniffer mode is supported for gpec read accesses. In sniffer mode the read data is not withdrawn from the FIFO.
R/W
0x00000000
Address@gxc_gpec_regs : 0x07c030fc
Address@gxc_gpec00_regs : 0x07d030fc
Address@gxc_gpec01_regs : 0x07d070fc
Address@gxc_gpec02_regs : 0x07d0b0fc
Address@gxc_gpec03_regs : 0x07d0f0fc
Address@gxc_gpec04_regs : 0x07d130fc
Address@gxc_gpec05_regs : 0x07d170fc
Address@gxc_gpec06_regs : 0x07d1b0fc
Address@gxc_gpec07_regs : 0x07d1f0fc
Address@gxc_gpec10_regs : 0x07d430fc
Address@gxc_gpec11_regs : 0x07d470fc
Address@gxc_gpec12_regs : 0x07d4b0fc
Address@gxc_gpec13_regs : 0x07d4f0fc
Address@gxc_gpec14_regs : 0x07d530fc
Address@gxc_gpec15_regs : 0x07d570fc
Address@gxc_gpec16_regs : 0x07d5b0fc
Address@gxc_gpec17_regs : 0x07d5f0fc
Bits Reset value Name Description
31 - 0 0x0
urtxe1
read access: Lastly received bits (output of URXE FIFO)
write access: Bits to be transmitted next (input of UTXE FIFO)



Base Address Area: intram0_gxc, intram1_gxc

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram128_base
1-7ffe 4-1fff8 -  reserved
7fff 1fffc R/W intram128_end

intram128_base
Area size: 128kB
R/W
0x00000000
Address@intram0_gxc : 0x07c20000
Address@intram1_gxc : 0x07c40000
Bits Reset value Name Description
31 - 0 0
intram128_base


intram128_end
R/W
0x00000000
Address@intram0_gxc : 0x07c3fffc
Address@intram1_gxc : 0x07c5fffc
Bits Reset value Name Description
31 - 0 0
intram128_end



Base Address Area: intram2_gxc, intram3_gxc, mot_intram0, mot_intram1, mot_intram2, mot_intram3, sms_rx_ram, sms_tx_ram, sms_ac_ram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W intram64_base
1-3ffe 4-fff8 -  reserved
3fff fffc R/W intram64_end

intram64_base
Area size: 64kB
R/W
0x00000000
Address@intram2_gxc : 0x07c60000
Address@intram3_gxc : 0x07c70000
Address@mot_intram0 : 0x48000000
Address@mot_intram1 : 0x48010000
Address@mot_intram2 : 0x48020000
Address@mot_intram3 : 0x48030000
Address@sms_rx_ram : 0x60000000
Address@sms_tx_ram : 0x60040000
Address@sms_ac_ram : 0x60080000
Bits Reset value Name Description
31 - 0 0
intram64_base


intram64_end
R/W
0x00000000
Address@intram2_gxc : 0x07c6fffc
Address@intram3_gxc : 0x07c7fffc
Address@mot_intram0 : 0x4800fffc
Address@mot_intram1 : 0x4801fffc
Address@mot_intram2 : 0x4802fffc
Address@mot_intram3 : 0x4803fffc
Address@sms_rx_ram : 0x6000fffc
Address@sms_tx_ram : 0x6004fffc
Address@sms_ac_ram : 0x6008fffc
Bits Reset value Name Description
31 - 0 0
intram64_end



Base Address Area: gxc_pfifo0, gxc_pfifo1, gxc_pfifo2, gxc_pfifo3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_pfifo_start
1-e 4-38 -  reserved
f 3c - gxc_pfifo_end
10 40 R/W gxc_pfifo_reset
11 44 R gxc_pfifo_full
12 48 R gxc_pfifo_empty
13 4c R gxc_pfifo_overflow
14 50 R gxc_pfifo_underrun
15 54 R/W gxc_pfifo_avoid_ufl
16 58 R/W gxc_pfifo_avoid_ofl
17 5c R/W gxc_pfifo_nok
18-1f 60-7c -  reserved
20 80 R gxc_pfifo_fill_level_start
21-2e 84-b8 -  reserved
2f bc - gxc_pfifo_fill_level_end
30-3f c0-fc -  reserved

gxc_pfifo_start
Pointer FIFO table:
Each of the following addresses accesses a FIFO.
R/W
0x00000000
Address@gxc_pfifo0 : 0x07d22200
Address@gxc_pfifo1 : 0x07d22300
Address@gxc_pfifo2 : 0x07d62200
Address@gxc_pfifo3 : 0x07d62300
Bits Reset value Name Description
31 - 0 0x0
fifo_data
In/output data to/from FIFO:
write access: write data to FIFO
read access: read data from FIFO


gxc_pfifo_end

Address@gxc_pfifo0 : 0x07d2223c
Address@gxc_pfifo1 : 0x07d2233c
Address@gxc_pfifo2 : 0x07d6223c
Address@gxc_pfifo3 : 0x07d6233c
Bits Name Description
31 - 0 gxc_pfifo_end


gxc_pfifo_reset
Pointer FIFO Reset Vector:
This register allows to reset each of the FIFOs, i.e. set read and write pointer to lower border of FIFO, reset full, overflow, underrun flag and set empty flag.
The reset flag of adjacent FIFOs should be set before resizing the FIFO.
R/W
0x00000000
Address@gxc_pfifo0 : 0x07d22240
Address@gxc_pfifo1 : 0x07d22340
Address@gxc_pfifo2 : 0x07d62240
Address@gxc_pfifo3 : 0x07d62340
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
reset_fifo
Reset Vector, 1 bit per FIFO:
1: reset FIFO
0: normal work mode


gxc_pfifo_full
Pointer FIFO Full Vector:
This read only address shows the fifo_full flag of each FIFO.
R
Address@gxc_pfifo0 : 0x07d22244
Address@gxc_pfifo1 : 0x07d22344
Address@gxc_pfifo2 : 0x07d62244
Address@gxc_pfifo3 : 0x07d62344
Bits Name Description
31 - 16 -
 reserved
15 - 0 fifo_full
FIFO full vector, 1 bit per FIFO


gxc_pfifo_empty
Pointer FIFO Empty Vector:
This read only address shows the fifo_empty flag of each FIFO.
R
Address@gxc_pfifo0 : 0x07d22248
Address@gxc_pfifo1 : 0x07d22348
Address@gxc_pfifo2 : 0x07d62248
Address@gxc_pfifo3 : 0x07d62348
Bits Name Description
31 - 16 -
 reserved
15 - 0 fifo_empty
FIFO empty vector, 1 bit per FIFO


gxc_pfifo_overflow
Pointer FIFO Overflow Vector:
This read only address shows the fifo_overflow flag of each FIFO.
If the FIFO had an overflow, it should be reset.
R
Address@gxc_pfifo0 : 0x07d2224c
Address@gxc_pfifo1 : 0x07d2234c
Address@gxc_pfifo2 : 0x07d6224c
Address@gxc_pfifo3 : 0x07d6234c
Bits Name Description
31 - 16 -
 reserved
15 - 0 fifo_overflow
FIFO overflow vector, 1 bit per FIFO


gxc_pfifo_underrun
Pointer FIFO Underrun Vector:
This read only address shows the fifo_underrun flag of each FIFO.
If the FIFO had an underrun, it should be reset.
R
Address@gxc_pfifo0 : 0x07d22250
Address@gxc_pfifo1 : 0x07d22350
Address@gxc_pfifo2 : 0x07d62250
Address@gxc_pfifo3 : 0x07d62350
Bits Name Description
31 - 16 -
 reserved
15 - 0 fifo_underrun
FIFO underrun vector, 1 bit per FIFO


gxc_pfifo_avoid_ufl
Pointer FIFO Vector:
This register allows to avoid underruns for each FIFO..
A read access at empty FIFO returns 0 and underrun flag is not set, but pfifo_nok will indicate the failed access.
R/W
0x00000000
Address@gxc_pfifo0 : 0x07d22254
Address@gxc_pfifo1 : 0x07d22354
Address@gxc_pfifo2 : 0x07d62254
Address@gxc_pfifo3 : 0x07d62354
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
FIFO protect from underrun vector, 1 bit per FIFO


gxc_pfifo_avoid_ofl
Pointer FIFO  Vector:
This register allows to avoid overflows for each FIFO
A write access to a full FIFO will be ignored and overflow flag is not set, but pfifo_nok will indicate the failed access.
R/W
0x00000000
Address@gxc_pfifo0 : 0x07d22258
Address@gxc_pfifo1 : 0x07d22358
Address@gxc_pfifo2 : 0x07d62258
Address@gxc_pfifo3 : 0x07d62358
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
FIFO protect from overflow vector, 1 bit per FIFO


gxc_pfifo_nok
Pointer FIFO not okay Vector:
This register indicates failed fifo accesses (overflow or underrun) for each master.
Each bit indicates that the last fifo access was not successful,
the bit will be reset with the next successful access.
R/W
0x00000000
Address@gxc_pfifo0 : 0x07d2225c
Address@gxc_pfifo1 : 0x07d2235c
Address@gxc_pfifo2 : 0x07d6225c
Address@gxc_pfifo3 : 0x07d6235c
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 "0"
cpu
status of last access
15 "0"
gpec17
status of last access
14 "0"
gpec16
status of last access
13 "0"
gpec15
status of last access
12 "0"
gpec14
status of last access
11 "0"
gpec13
status of last access
10 "0"
gpec12
status of last access
9 "0"
gpec11
status of last access
8 "0"
gpec10
status of last access
7 "0"
gpec07
status of last access
6 "0"
gpec06
status of last access
5 "0"
gpec05
status of last access
4 "0"
gpec04
status of last access
3 "0"
gpec03
status of last access
2 "0"
gpec02
status of last access
1 "0"
gpec01
status of last access
0 "0"
gpec00
status of last access


gxc_pfifo_fill_level_start
Pointer FIFO Fill-Level table:
Each of the following addresses reads the fill-level of the appropriate FIFO.
R
Address@gxc_pfifo0 : 0x07d22280
Address@gxc_pfifo1 : 0x07d22380
Address@gxc_pfifo2 : 0x07d62280
Address@gxc_pfifo3 : 0x07d62380
Bits Name Description
31 - 10 -
 reserved
9 - 0 fill_level
actual number of words in appropriate FIFO
(not valid, if FIFO had an overflow or underrun)


gxc_pfifo_fill_level_end

Address@gxc_pfifo0 : 0x07d222bc
Address@gxc_pfifo1 : 0x07d223bc
Address@gxc_pfifo2 : 0x07d622bc
Address@gxc_pfifo3 : 0x07d623bc
Bits Name Description
31 - 0 gxc_pfifo_fill_level_end



Base Address Area: gxc_gpec0_irq, gxc_gpec1_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_gpec_irq_gpec_irq_raw
1 4 R/W gxc_gpec_irq_gpec_irq_masked
2 8 R/W gxc_gpec_irq_gpec_irq_mask_set
3 c R/W gxc_gpec_irq_gpec_irq_mask_rst
4 10 R/W gxc_gpec_irq_host_req_raw
5 14 R/W gxc_gpec_irq_host_req_mask
6-7 18-1c -  reserved

gxc_gpec_irq_gpec_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@gxc_gpec0_irq : 0x07d22400
Address@gxc_gpec1_irq : 0x07d62400
Bits Reset value Name Description
31 "0"
gpec_irq31
EVENT: IRQ from GPECs to CPU
30 "0"
gpec_irq30
EVENT: IRQ from GPECs to CPU
29 "0"
gpec_irq29
EVENT: IRQ from GPECs to CPU
28 "0"
gpec_irq28
EVENT: IRQ from GPECs to CPU
27 "0"
gpec_irq27
EVENT: IRQ from GPECs to CPU
26 "0"
gpec_irq26
EVENT: IRQ from GPECs to CPU
25 "0"
gpec_irq25
EVENT: IRQ from GPECs to CPU
24 "0"
gpec_irq24
EVENT: IRQ from GPECs to CPU
23 "0"
gpec_irq23
EVENT: IRQ from GPECs to CPU
22 "0"
gpec_irq22
EVENT: IRQ from GPECs to CPU
21 "0"
gpec_irq21
EVENT: IRQ from GPECs to CPU
20 "0"
gpec_irq20
EVENT: IRQ from GPECs to CPU
19 "0"
gpec_irq19
EVENT: IRQ from GPECs to CPU
18 "0"
gpec_irq18
EVENT: IRQ from GPECs to CPU
17 "0"
gpec_irq17
EVENT: IRQ from GPECs to CPU
16 "0"
gpec_irq16
EVENT: IRQ from GPECs to CPU
15 "0"
gpec_irq15
EVENT: IRQ from GPECs to CPU
14 "0"
gpec_irq14
EVENT: IRQ from GPECs to CPU
13 "0"
gpec_irq13
EVENT: IRQ from GPECs to CPU
12 "0"
gpec_irq12
EVENT: IRQ from GPECs to CPU
11 "0"
gpec_irq11
EVENT: IRQ from GPECs to CPU
10 "0"
gpec_irq10
EVENT: IRQ from GPECs to CPU
9 "0"
gpec_irq9
EVENT: IRQ from GPECs to CPU
8 "0"
gpec_irq8
EVENT: IRQ from GPECs to CPU
7 "0"
gpec_irq7
EVENT: IRQ from GPECs to CPU
6 "0"
gpec_irq6
EVENT: IRQ from GPECs to CPU
5 "0"
gpec_irq5
EVENT: IRQ from GPECs to CPU
4 "0"
gpec_irq4
EVENT: IRQ from GPECs to CPU
3 "0"
gpec_irq3
EVENT: IRQ from GPECs to CPU
2 "0"
gpec_irq2
EVENT: IRQ from GPECs to CPU
1 "0"
gpec_irq1
EVENT: IRQ from GPECs to CPU
0 "0"
gpec_irq0
EVENT: IRQ from GPECs to CPU


gxc_gpec_irq_gpec_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gxc_gpec_irq_gpec_irq_raw).
R/W
0x00000000
Address@gxc_gpec0_irq : 0x07d22404
Address@gxc_gpec1_irq : 0x07d62404
Bits Reset value Name Description
31 "0"
gpec_irq31
EVENT: IRQ from GPECs to CPU
30 "0"
gpec_irq30
EVENT: IRQ from GPECs to CPU
29 "0"
gpec_irq29
EVENT: IRQ from GPECs to CPU
28 "0"
gpec_irq28
EVENT: IRQ from GPECs to CPU
27 "0"
gpec_irq27
EVENT: IRQ from GPECs to CPU
26 "0"
gpec_irq26
EVENT: IRQ from GPECs to CPU
25 "0"
gpec_irq25
EVENT: IRQ from GPECs to CPU
24 "0"
gpec_irq24
EVENT: IRQ from GPECs to CPU
23 "0"
gpec_irq23
EVENT: IRQ from GPECs to CPU
22 "0"
gpec_irq22
EVENT: IRQ from GPECs to CPU
21 "0"
gpec_irq21
EVENT: IRQ from GPECs to CPU
20 "0"
gpec_irq20
EVENT: IRQ from GPECs to CPU
19 "0"
gpec_irq19
EVENT: IRQ from GPECs to CPU
18 "0"
gpec_irq18
EVENT: IRQ from GPECs to CPU
17 "0"
gpec_irq17
EVENT: IRQ from GPECs to CPU
16 "0"
gpec_irq16
EVENT: IRQ from GPECs to CPU
15 "0"
gpec_irq15
EVENT: IRQ from GPECs to CPU
14 "0"
gpec_irq14
EVENT: IRQ from GPECs to CPU
13 "0"
gpec_irq13
EVENT: IRQ from GPECs to CPU
12 "0"
gpec_irq12
EVENT: IRQ from GPECs to CPU
11 "0"
gpec_irq11
EVENT: IRQ from GPECs to CPU
10 "0"
gpec_irq10
EVENT: IRQ from GPECs to CPU
9 "0"
gpec_irq9
EVENT: IRQ from GPECs to CPU
8 "0"
gpec_irq8
EVENT: IRQ from GPECs to CPU
7 "0"
gpec_irq7
EVENT: IRQ from GPECs to CPU
6 "0"
gpec_irq6
EVENT: IRQ from GPECs to CPU
5 "0"
gpec_irq5
EVENT: IRQ from GPECs to CPU
4 "0"
gpec_irq4
EVENT: IRQ from GPECs to CPU
3 "0"
gpec_irq3
EVENT: IRQ from GPECs to CPU
2 "0"
gpec_irq2
EVENT: IRQ from GPECs to CPU
1 "0"
gpec_irq1
EVENT: IRQ from GPECs to CPU
0 "0"
gpec_irq0
EVENT: IRQ from GPECs to CPU


gxc_gpec_irq_gpec_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gxc_gpec_irq_gpec_irq_raw
R/W
0x00000000
Address@gxc_gpec0_irq : 0x07d22408
Address@gxc_gpec1_irq : 0x07d62408
Bits Reset value Name Description
31 "0"
gpec_irq31
EVENT: IRQ from GPECs to CPU
30 "0"
gpec_irq30
EVENT: IRQ from GPECs to CPU
29 "0"
gpec_irq29
EVENT: IRQ from GPECs to CPU
28 "0"
gpec_irq28
EVENT: IRQ from GPECs to CPU
27 "0"
gpec_irq27
EVENT: IRQ from GPECs to CPU
26 "0"
gpec_irq26
EVENT: IRQ from GPECs to CPU
25 "0"
gpec_irq25
EVENT: IRQ from GPECs to CPU
24 "0"
gpec_irq24
EVENT: IRQ from GPECs to CPU
23 "0"
gpec_irq23
EVENT: IRQ from GPECs to CPU
22 "0"
gpec_irq22
EVENT: IRQ from GPECs to CPU
21 "0"
gpec_irq21
EVENT: IRQ from GPECs to CPU
20 "0"
gpec_irq20
EVENT: IRQ from GPECs to CPU
19 "0"
gpec_irq19
EVENT: IRQ from GPECs to CPU
18 "0"
gpec_irq18
EVENT: IRQ from GPECs to CPU
17 "0"
gpec_irq17
EVENT: IRQ from GPECs to CPU
16 "0"
gpec_irq16
EVENT: IRQ from GPECs to CPU
15 "0"
gpec_irq15
EVENT: IRQ from GPECs to CPU
14 "0"
gpec_irq14
EVENT: IRQ from GPECs to CPU
13 "0"
gpec_irq13
EVENT: IRQ from GPECs to CPU
12 "0"
gpec_irq12
EVENT: IRQ from GPECs to CPU
11 "0"
gpec_irq11
EVENT: IRQ from GPECs to CPU
10 "0"
gpec_irq10
EVENT: IRQ from GPECs to CPU
9 "0"
gpec_irq9
EVENT: IRQ from GPECs to CPU
8 "0"
gpec_irq8
EVENT: IRQ from GPECs to CPU
7 "0"
gpec_irq7
EVENT: IRQ from GPECs to CPU
6 "0"
gpec_irq6
EVENT: IRQ from GPECs to CPU
5 "0"
gpec_irq5
EVENT: IRQ from GPECs to CPU
4 "0"
gpec_irq4
EVENT: IRQ from GPECs to CPU
3 "0"
gpec_irq3
EVENT: IRQ from GPECs to CPU
2 "0"
gpec_irq2
EVENT: IRQ from GPECs to CPU
1 "0"
gpec_irq1
EVENT: IRQ from GPECs to CPU
0 "0"
gpec_irq0
EVENT: IRQ from GPECs to CPU


gxc_gpec_irq_gpec_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : gpec_irq-gpec_irq0
  1  : gpec_irq-gpec_irq1
  2  : gpec_irq-gpec_irq2
  3  : gpec_irq-gpec_irq3
  4  : gpec_irq-gpec_irq4
  5  : gpec_irq-gpec_irq5
  6  : gpec_irq-gpec_irq6
  7  : gpec_irq-gpec_irq7
  8  : gpec_irq-gpec_irq8
  9  : gpec_irq-gpec_irq9
  10 : gpec_irq-gpec_irq10
  11 : gpec_irq-gpec_irq11
  12 : gpec_irq-gpec_irq12
  13 : gpec_irq-gpec_irq13
  14 : gpec_irq-gpec_irq14
  15 : gpec_irq-gpec_irq15
  16 : gpec_irq-gpec_irq16
  17 : gpec_irq-gpec_irq17
  18 : gpec_irq-gpec_irq18
  19 : gpec_irq-gpec_irq19
  20 : gpec_irq-gpec_irq20
  21 : gpec_irq-gpec_irq21
  22 : gpec_irq-gpec_irq22
  23 : gpec_irq-gpec_irq23
  24 : gpec_irq-gpec_irq24
  25 : gpec_irq-gpec_irq25
  26 : gpec_irq-gpec_irq26
  27 : gpec_irq-gpec_irq27
  28 : gpec_irq-gpec_irq28
  29 : gpec_irq-gpec_irq29
  30 : gpec_irq-gpec_irq30
  31 : gpec_irq-gpec_irq31
  32 : no active IRQ
R/W
0x00000000
Address@gxc_gpec0_irq : 0x07d2240c
Address@gxc_gpec1_irq : 0x07d6240c
Bits Reset value Name Description
31 "0"
gpec_irq31
EVENT: IRQ from GPECs to CPU
30 "0"
gpec_irq30
EVENT: IRQ from GPECs to CPU
29 "0"
gpec_irq29
EVENT: IRQ from GPECs to CPU
28 "0"
gpec_irq28
EVENT: IRQ from GPECs to CPU
27 "0"
gpec_irq27
EVENT: IRQ from GPECs to CPU
26 "0"
gpec_irq26
EVENT: IRQ from GPECs to CPU
25 "0"
gpec_irq25
EVENT: IRQ from GPECs to CPU
24 "0"
gpec_irq24
EVENT: IRQ from GPECs to CPU
23 "0"
gpec_irq23
EVENT: IRQ from GPECs to CPU
22 "0"
gpec_irq22
EVENT: IRQ from GPECs to CPU
21 "0"
gpec_irq21
EVENT: IRQ from GPECs to CPU
20 "0"
gpec_irq20
EVENT: IRQ from GPECs to CPU
19 "0"
gpec_irq19
EVENT: IRQ from GPECs to CPU
18 "0"
gpec_irq18
EVENT: IRQ from GPECs to CPU
17 "0"
gpec_irq17
EVENT: IRQ from GPECs to CPU
16 "0"
gpec_irq16
EVENT: IRQ from GPECs to CPU
15 "0"
gpec_irq15
EVENT: IRQ from GPECs to CPU
14 "0"
gpec_irq14
EVENT: IRQ from GPECs to CPU
13 "0"
gpec_irq13
EVENT: IRQ from GPECs to CPU
12 "0"
gpec_irq12
EVENT: IRQ from GPECs to CPU
11 "0"
gpec_irq11
EVENT: IRQ from GPECs to CPU
10 "0"
gpec_irq10
EVENT: IRQ from GPECs to CPU
9 "0"
gpec_irq9
EVENT: IRQ from GPECs to CPU
8 "0"
gpec_irq8
EVENT: IRQ from GPECs to CPU
7 "0"
gpec_irq7
EVENT: IRQ from GPECs to CPU
6 "0"
gpec_irq6
EVENT: IRQ from GPECs to CPU
5 "0"
gpec_irq5
EVENT: IRQ from GPECs to CPU
4 "0"
gpec_irq4
EVENT: IRQ from GPECs to CPU
3 "0"
gpec_irq3
EVENT: IRQ from GPECs to CPU
2 "0"
gpec_irq2
EVENT: IRQ from GPECs to CPU
1 "0"
gpec_irq1
EVENT: IRQ from GPECs to CPU
0 "0"
gpec_irq0
EVENT: IRQ from GPECs to CPU


gxc_gpec_irq_host_req_raw
Host request raw register: CPU -> gPEC
 Write access with '1' sets raw bit.
R/W
0x00000000
Address@gxc_gpec0_irq : 0x07d22410
Address@gxc_gpec1_irq : 0x07d62410
Bits Reset value Name Description
31 - 0 0x0
val



gxc_gpec_irq_host_req_mask
Host request mask register: CPU -> gPEC
R/W
0xffffffff
Address@gxc_gpec0_irq : 0x07d22414
Address@gxc_gpec1_irq : 0x07d62414
Bits Reset value Name Description
31 - 0 0xffffffff
val
write and read mask for debug



Base Address Area: gxc_sr

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_sr_sr0
1 4 R/W gxc_sr_sr1
2 8 R/W gxc_sr_sr2
3 c R/W gxc_sr_sr3
4 10 R/W gxc_sr_sr4
5 14 R/W gxc_sr_sr5
6 18 R/W gxc_sr_sr6
7 1c R/W gxc_sr_sr7
8 20 R/W gxc_sr_sr8
9 24 R/W gxc_sr_sr9
a 28 R/W gxc_sr_sr10
b 2c R/W gxc_sr_sr11
c 30 R/W gxc_sr_sr12
d 34 R/W gxc_sr_sr13
e 38 R/W gxc_sr_sr14
f 3c R/W gxc_sr_sr15
10 40 R/W gxc_sr_statcfg0
11 44 R/W gxc_sr_statcfg1
12 48 R/W gxc_sr_stat_bits
13 4c R/W gxc_sr_lut_bits
14 50 R/W gxc_sr_lut_cfg0
15 54 R/W gxc_sr_lut_cfg1
16 58 R/W gxc_sr_lut_cfg2
17 5c R/W gxc_sr_lut_cfg3
18 60 R/W gxc_sr_lut_cfg4
19 64 R/W gxc_sr_lut_cfg5
1a 68 R/W gxc_sr_lut_cfg6
1b 6c R/W gxc_sr_lut_cfg7
1c 70 R/W gxc_sr_lut_cfg8
1d 74 R/W gxc_sr_lut_cfg9
1e 78 R/W gxc_sr_lut_cfg10
1f 7c R/W gxc_sr_lut_cfg11
20 80 R/W gxc_sr_lut_cfg12
21 84 R/W gxc_sr_lut_cfg13
22 88 R/W gxc_sr_lut_cfg14
23 8c R/W gxc_sr_lut_cfg15
24-3f 90-fc -  reserved

gxc_sr_sr0
Shared Work Register 0
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62500
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr1
Shared Work Register 1:
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62504
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr2
Shared Work Register 2
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62508
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr3
Shared Work Register 3
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d6250c
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr4
Shared Work Register 4
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62510
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr5
Shared Work Register 5
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62514
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr6
Shared Work Register 6
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62518
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr7
Shared Work Register 7
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d6251c
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr8
Shared Work Register 8
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62520
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr9
Shared Work Register 9
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62524
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr10
Shared Work Register 10
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62528
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr11
Shared Work Register 11
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d6252c
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr12
Shared Work Register 12:
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62530
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr13
Shared Work Register 13
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62534
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr14
Shared Work Register 14:
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d62538
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_sr15
Shared Work Register 15
This register is shared between all gMACs, all gPECs and CPU.
R/W
0x00000000
Address : 0x07d6253c
Bits Reset value Name Description
31 - 0 0x0
val
Shared Register
This register is writable but can also be changed by hardware (GXC).


gxc_sr_statcfg0
Shared Config and Status Register of GMAC0:
This register is shared between all GMACs, all GPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 8..12 do not require write masks), but upper 16 bits can have completey independent read functionality.
If gxc_sys_ctrl-piomode is active, this will overwrite values of gpio* bits.
This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address : 0x07d62540
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
lmo_link_and_n_eld_bad_link
!eld_bad_link & link_mode_out_link
29 "0"
dr_err_or_crx_err_or_fcr_err
dr_err or crx_err or fcr_err are active
28 "0"
hdx1000
read only 1 GBit half duplex mode
hdx1000 = (link_mode_out_duplex==0) and (link_mode_out_speed==2)
27 "0"
link_mode_out_duplex
read only duplex status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_duplex
1: full duplex
0: half duplex
26 "0"
link_mode_out_link
read only link status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_link
1: link up
0: link down
25 - 24 "00"
link_mode_out_speed
read only speed status as in gxc_sys_ctrl.link_mode0_status.link_mode_out_speed
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
23 "0"
utxe_empty
utxe_empty (UTXE_FIFO empty)
22 "0"
utxe_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
21 "0"
urxe_bit32
bit 32 at output of URXE FIFO
20 "0"
urxe_rdy
Received bytes are valid at output of URX_FIFO
19 "0"
utx_empty
utx_empty (UTX_FIFO empty)
18 "0"
utx_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
17 "0"
urx_bit32
bit 32 at output of URX FIFO
16 "0"
urx_rdy
Received bytes are valid at output of URX_FIFO
15 0
-
 reserved
14 "0"
eld_bad_link
link_status from enhanced link detection unit.
Reset by writing 1 to this bit, requires no write mask
13 "0"
utxe_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTXE_FIFO, requires no write mask
12 "0"
urxe_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URXE_FIFO, requires no write mask
11 "0"
utx_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTX_FIFO, requires no write mask
10 "0"
urx_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URX_FIFO, requires no write mask
9 - 8 0
-
 reserved
7 "0"
gpio3_oe
GPIO3 pin output enable
6 "0"
gpio2_oe
GPIO2 pin output enable
5 "0"
gpio1_oe
GPIO1 pin output enable
4 "0"
gpio0_oe
GPIO0 pin output enable
3 "0"
gpio3
write: GPIO3 pin output: not used
read: GPIO3 pin input:  might be used as spis-mosi or spim-miso
2 "0"
gpio2
write: GPIO2 pin output: might be used as spim_clk
read: GPIO2 pin input:  connected to link (controls phy_led),
                         might be used as pb-din or spis-clk
1 "0"
gpio1
write: GPIO1 pin output: might be used as pb-dv spim-cs
read: GPIO1 pin input:  connected to rxsdf (samples systime),
                         might be used as spis-cs
0 "0"
gpio0
write: GPIO0 pin output: might be used as pb-dout or spis-miso or spim-mosi
read: GPIO0 pin input:  connected to txsdf (samples systime)


gxc_sr_statcfg1
Shared Config and Status Register of GMAC1:
This register is shared between all GMACs, all GPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits (exception: bits 8..12 do not require write masks), but upper 16 bits can have completey independent read functionality.
If gxc_sys_ctrl-piomode is active, this will overwrite values of gpio* bits.
This register has a write pipeline delay of 1 clock cycle.
R/W
0x00000000
Address : 0x07d62544
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
lmo_link_and_n_eld_bad_link
!eld_bad_link & link_mode_out_link
29 "0"
dr_err_or_crx_err_or_fcr_err
dr_err or crx_err or fcr_err are active
28 "0"
hdx1000
read only 1 GBit half duplex mode
hdx1000 = (link_mode_out_duplex==0) and (link_mode_out_speed==2)
27 "0"
link_mode_out_duplex
read only duplex status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_duplex
1: full duplex
0: half duplex
26 "0"
link_mode_out_link
read only link status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_link
1: link up
0: link down
25 - 24 "00"
link_mode_out_speed
read only speed status as in gxc_sys_ctrl.link_mode1_status.link_mode_out_speed
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
23 "0"
utxe_empty
utxe_empty (UTXE_FIFO empty)
22 "0"
utxe_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
21 "0"
urxe_bit32
bit 32 at output of URXE FIFO
20 "0"
urxe_rdy
Received bytes are valid at output of URX_FIFO
19 "0"
utx_empty
utx_empty (UTX_FIFO empty)
18 "0"
utx_nxt
Put next tx_word to UTX_FIFO: at least one entry of UTX_FIFO is empty
17 "0"
urx_bit32
bit 32 at output of URX FIFO
16 "0"
urx_rdy
Received bytes are valid at output of URX_FIFO
15 0
-
 reserved
14 "0"
eld_bad_link
link_status from enhanced link detection unit.
Reset by writing 1 to this bit, requires no write mask
13 "0"
utxe_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTXE_FIFO, requires no write mask
12 "0"
urxe_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URXE_FIFO, requires no write mask
11 "0"
utx_ufl
Transmit underflow (not enough data in UTX_FIFO).
Reset by writing 1 to this bit, resets UTX_FIFO, requires no write mask
10 "0"
urx_ovf
Receive overflow (too much data in URX_FIFO).
Reset by writing 1 to this bit, resets URX_FIFO, requires no write mask
9 - 8 0
-
 reserved
7 "0"
gpio3_oe
GPIO3 pin output enable
6 "0"
gpio2_oe
GPIO2 pin output enable
5 "0"
gpio1_oe
GPIO1 pin output enable
4 "0"
gpio0_oe
GPIO0 pin output enable
3 "0"
gpio3
write: GPIO3 pin output: not used
read: GPIO3 pin input:  might be used as spis-mosi or spim-miso
2 "0"
gpio2
write: GPIO2 pin output: might be used as spim_clk
read: GPIO2 pin input:  connected to link (controls phy_led),
                         might be used as pb-din or spis-clk
1 "0"
gpio1
write: GPIO1 pin output: might be used as pb-dv spim-cs
read: GPIO1 pin input:  connected to rxsdf (samples systime),
                         might be used as spis-cs
0 "0"
gpio0
write: GPIO0 pin output: might be used as pb-dout or spis-miso or spim-mosi
read: GPIO0 pin input:  connected to txsdf (samples systime)


gxc_sr_stat_bits
Status bits register
This register is shared between all gMACs, all gPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits.
R/W
0x00000000
Address : 0x07d62548
Bits Reset value Name Description
31 - 16 0x0
set_mask
set mask
15 - 0 0x0
flags
flags


gxc_sr_lut_bits
Look-Up Table (LUT) bits register containing all input and output bits of LUT0..15
This register is shared between all gMACs, all gPECs and CPU.
This register is a combined write mask register, i.e. at write upper 16 bits are write masks for lower 16 bits.
R/W
0x00000000
Address : 0x07d6254c
Bits Reset value Name Description
31 - 16 0x0
lut_out
read: output bits of LUT0..15
write: set mask for lut_in # default 0x0000
15 - 0 0x0
lut_in
software defined LUT input bits


gxc_sr_lut_cfg0
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[0].
R/W
0x00000000
Address : 0x07d62550
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
Look-Up Table, 1 lut_out bit value for each possible in0/in1 combination
This value represents one the following logical operations:
b0000: zero, lut_out = 0
b0001: nor, lut_out = !(in0 | in1)
b0010: bs, lut_out = !in0 & in1
b0011: inv1, lut_out = !in0
b0100: nimp, lut_out = in0 & !in1
b0101: inv2, lut_out = !in1
b0110: xor, lut_out = (in0 & !in1) | (!in0 & in1)
b0111: nand, lut_out = !(in0 & in1)
b1000: and, lut_out = in0 & in1
b1001: xnor, lut_out = (in0 & in1) | (!in0 & !in1)
b1010: mov2, lut_out = in1
b1011: imp, lut_out = !in0 | in1
b1100: mov1, lut_out = in0
b1101: bbe, lut_out = in0 | !in1
b1110: or, lut_out = in0 | in1
b1111: one, lut_out = 1
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
LUT in1 selector to select the signal to be connected to input1 of the LUT
see lut_in0_sel for possible values
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
LUT in0 selector to select the signal to be connected to input0 of the LUT
This value represets one of the following signals:
h00: gxc_sr_lut_bits.lut_in[0]
h01: gxc_sr_lut_bits.lut_in[1]
h02: gxc_sr_lut_bits.lut_in[2]
h03: gxc_sr_lut_bits.lut_in[3]
h04: gxc_sr_lut_bits.lut_in[4]
h05: gxc_sr_lut_bits.lut_in[5]
h06: gxc_sr_lut_bits.lut_in[6]
h07: gxc_sr_lut_bits.lut_in[7]
h08: gxc_sr_lut_bits.lut_in[8]
h09: gxc_sr_lut_bits.lut_in[9]
h0a: gxc_sr_lut_bits.lut_in[10]
h0b: gxc_sr_lut_bits.lut_in[11]
h0c: gxc_sr_lut_bits.lut_in[12]
h0d: gxc_sr_lut_bits.lut_in[13]
h0e: gxc_sr_lut_bits.lut_in[14]
h0f: gxc_sr_lut_bits.lut_in[15]
h10: gxc_sr_lut_bits.lut_out[0]
h11: gxc_sr_lut_bits.lut_out[1]
h12: gxc_sr_lut_bits.lut_out[2]
h13: gxc_sr_lut_bits.lut_out[3]
h14: gxc_sr_lut_bits.lut_out[8]
h15: gxc_sr_lut_bits.lut_out[9]
h16: gxc_sr_lut_bits.lut_out[10]
h17: gxc_sr_lut_bits.lut_out[11]
h18: gxc_sr_stat_bits.flags[0]
h19: gxc_sr_stat_bits.flags[1]
h1a: gxc_sr_stat_bits.flags[2]
h1b: gxc_sr_stat_bits.flags[3]
h1c: gxc_sr_stat_bits.flags[8]
h1d: gxc_sr_stat_bits.flags[9]
h1e: gxc_sr_stat_bits.flags[10]
h1f: gxc_sr_stat_bits.flags[11]
h20: gxc_sr_statcfg0.urx_rdy
h21: gxc_sr_statcfg0.urx_bit32
h22: gxc_sr_statcfg0.utx_empty
h23: gxc_sr_statcfg0.urxe_rdy
h24: gxc_sr_statcfg0.urxe_bit32
h25: gxc_sr_statcfg0.utxe_empty
h26: gxc_sr_statcfg0.eld_bad_link
h27: gxc_sr_statcfg0.dr_err_or_crx_err_or_fcr_err
h28: gxc_sr_statcfg0.link_mode_out_speed[0]
h29: gxc_sr_statcfg0.link_mode_out_speed[1]
h2a: gxc_sr_statcfg0.link_mode_out_link
h2b: gxc_sr_statcfg0.link_mode_out_duplex
h2c: gxc_sr_statcfg0.gpio_in[0]
h2d: gxc_sr_statcfg0.gpio_in[1]
h2e: gxc_sr_statcfg0.gpio_in[2]
h2f: gxc_sr_statcfg0.gpio_in[3]
h30: gxc_sr_statcfg1.urx_rdy
h31: gxc_sr_statcfg1.urx_bit32
h32: gxc_sr_statcfg1.utx_empty
h33: gxc_sr_statcfg1.urxe_rdy
h34: gxc_sr_statcfg1.urxe_bit32
h35: gxc_sr_statcfg1.utxe_empty
h36: gxc_sr_statcfg1.eld_bad_link
h37: gxc_sr_statcfg1.dr_err_or_crx_err_or_fcr_err
h38: gxc_sr_statcfg1.link_mode_out_speed[0]
h39: gxc_sr_statcfg1.link_mode_out_speed[1]
h3a: gxc_sr_statcfg1.link_mode_out_link
h3b: gxc_sr_statcfg1.link_mode_out_duplex
h3c: gxc_sr_statcfg1.gpio_in[0]
h3d: gxc_sr_statcfg1.gpio_in[1]
h3e: gxc_sr_statcfg1.gpio_in[2]
h3f: gxc_sr_statcfg1.gpio_in[3]


gxc_sr_lut_cfg1
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[1].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62554
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg2
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[2].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62558
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg3
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[3].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d6255c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg4
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[4].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62560
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg5
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[5].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62564
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg6
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[6].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62568
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg7
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[7].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d6256c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg8
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[8].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62570
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg9
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[9].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62574
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg10
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[10].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62578
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg11
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[11].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d6257c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg12
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[12].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62580
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg13
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[13].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62584
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg14
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[14].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d62588
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel


gxc_sr_lut_cfg15
Look-Up Table configuration register
Provides the inputs and behavior for gxc_sr_lut_bits.lut_out[15].
The register layout is identical to gxc_sr_lut_cfg0
R/W
0x00000000
Address : 0x07d6258c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
lut
see gxc_sr_lut_cfg0.lut
15 - 14 0
-
 reserved
13 - 8 "000000"
lut_in1_sel
see gxc_sr_lut_cfg0.lut_in1_sel
7 - 6 0
-
 reserved
5 - 0 "000000"
lut_in0_sel
see gxc_sr_lut_cfg0.lut_in0_sel



Base Address Area: gxc_start_stop

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_start_ctrl
1 4 R/W gxc_stop_ctrl
2 8 R/W gxc_clk_enable
3 c R/W gxc_clk_disable

gxc_start_ctrl
Start register for gxc processors
Change note: Bug in netx22xx_mpw, read access on this register changes the value, Workaround: write zero to register before reading
R/W
0x00000000
Address : 0x07d62780
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
tpu1
write '1' to start / read for status
24 "0"
rpu1
write '1' to start / read for status
23 "0"
gpec17
write '1' to start / read for status
22 "0"
gpec16
write '1' to start / read for status
21 "0"
gpec15
write '1' to start / read for status
20 "0"
gpec14
write '1' to start / read for status
19 "0"
gpec13
write '1' to start / read for status
18 "0"
gpec12
write '1' to start / read for status
17 "0"
gpec11
write '1' to start / read for status
16 "0"
gpec10
write '1' to start / read for status
15 - 10 0
-
 reserved
9 "0"
tpu0
write '1' to start / read for status
8 "0"
rpu0
write '1' to start / read for status
7 "0"
gpec07
write '1' to start / read for status
6 "0"
gpec06
write '1' to start / read for status
5 "0"
gpec05
write '1' to start / read for status
4 "0"
gpec04
write '1' to start / read for status
3 "0"
gpec03
write '1' to start / read for status
2 "0"
gpec02
write '1' to start / read for status
1 "0"
gpec01
write '1' to start / read for status
0 "0"
gpec00
write '1' to start / read for status


gxc_stop_ctrl
Stop register for gxc processors
Change note: Bug in netx22xx_mpw, read access on this register changes the value, Workaround: write zero to register before reading
R/W
0x00000000
Address : 0x07d62784
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
tpu1
write '1' to stop / read for status
24 "0"
rpu1
write '1' to stop / read for status
23 "0"
gpec17
write '1' to stop / read for status
22 "0"
gpec16
write '1' to stop / read for status
21 "0"
gpec15
write '1' to stop / read for status
20 "0"
gpec14
write '1' to stop / read for status
19 "0"
gpec13
write '1' to stop / read for status
18 "0"
gpec12
write '1' to stop / read for status
17 "0"
gpec11
write '1' to stop / read for status
16 "0"
gpec10
write '1' to stop / read for status
15 - 10 0
-
 reserved
9 "0"
tpu0
write '1' to stop / read for status
8 "0"
rpu0
write '1' to stop / read for status
7 "0"
gpec07
write '1' to stop / read for status
6 "0"
gpec06
write '1' to stop / read for status
5 "0"
gpec05
write '1' to stop / read for status
4 "0"
gpec04
write '1' to stop / read for status
3 "0"
gpec03
write '1' to stop / read for status
2 "0"
gpec02
write '1' to stop / read for status
1 "0"
gpec01
write '1' to stop / read for status
0 "0"
gpec00
write '1' to stop / read for status


gxc_clk_enable
Clock enable for all GXC_SYS internal clocks
all bits are reserved for future use, only esc_unit is used
Change note: Bug in netx22xx_mpw, read access on this register changes the value, Workaround: write zero to register before reading
R/W
0x00000000
Address : 0x07d62788
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 "0"
global_buf_man
write '1' to enable clock for global_buf_man / read for status
26 "0"
pfifo11
write '1' to enable clock for pfifo11 / read for status
25 "0"
pfifo10
write '1' to enable clock for pfifo10 / read for status
24 "0"
gmac1
write '1' to enable clock for gmac1 / read for status
23 "0"
gpec17
write '1' to enable clock for gpec17 / read for status
22 "0"
gpec16
write '1' to enable clock for gpec16 / read for status
21 "0"
gpec15
write '1' to enable clock for gpec15 / read for status
20 "0"
gpec14
write '1' to enable clock for gpec14 / read for status
19 "0"
gpec13
write '1' to enable clock for gpec13 / read for status
18 "0"
gpec12
write '1' to enable clock for gpec12 / read for status
17 "0"
gpec11
write '1' to enable clock for gpec11 / read for status
16 "0"
gpec10
write '1' to enable clock for gpec10 / read for status
15 - 12 0
-
 reserved
11 "0"
esc_unit
write '1' to enable clock for esc_unit / read for status
10 "0"
pfifo01
write '1' to enable clock for pfifo01 / read for status
9 "0"
pfifo00
write '1' to enable clock for pfifo00 / read for status
8 "0"
gmac0
write '1' to enable clock for gmac0 / read for status
7 "0"
gpec07
write '1' to enable clock for gpec07 / read for status
6 "0"
gpec06
write '1' to enable clock for gpec06 / read for status
5 "0"
gpec05
write '1' to enable clock for gpec05 / read for status
4 "0"
gpec04
write '1' to enable clock for gpec04 / read for status
3 "0"
gpec03
write '1' to enable clock for gpec03 / read for status
2 "0"
gpec02
write '1' to enable clock for gpec02 / read for status
1 "0"
gpec01
write '1' to enable clock for gpec01 / read for status
0 "0"
gpec00
write '1' to enable clock for gpec00 / read for status


gxc_clk_disable
Clock disable for all GXC_SYS internal clocks
all bits are reserved for future use, only esc_unit is used
Change note: Bug in netx22xx_mpw, read access on this register changes the value, Workaround: write zero to register before reading
R/W
0x00000000
Address : 0x07d6278c
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 "0"
global_buf_man
write '1' to disable clock for global_buf_man / read for status
26 "0"
pfifo11
write '1' to disable clock for pfifo11 / read for status
25 "0"
pfifo10
write '1' to disable clock for pfifo10 / read for status
24 "0"
gmac1
write '1' to disable clock for gmac1 / read for status
23 "0"
gpec17
write '1' to disable clock for gpec17 / read for status
22 "0"
gpec16
write '1' to disable clock for gpec16 / read for status
21 "0"
gpec15
write '1' to disable clock for gpec15 / read for status
20 "0"
gpec14
write '1' to disable clock for gpec14 / read for status
19 "0"
gpec13
write '1' to disable clock for gpec13 / read for status
18 "0"
gpec12
write '1' to disable clock for gpec12 / read for status
17 "0"
gpec11
write '1' to disable clock for gpec11 / read for status
16 "0"
gpec10
write '1' to disable clock for gpec10 / read for status
15 - 12 0
-
 reserved
11 "0"
esc_unit
write '1' to disable clock for esc_unit / read for status
10 "0"
pfifo01
write '1' to disable clock for pfifo01 / read for status
9 "0"
pfifo00
write '1' to disable clock for pfifo00 / read for status
8 "0"
gmac0
write '1' to disable clock for gmac0 / read for status
7 "0"
gpec07
write '1' to disable clock for gpec07 / read for status
6 "0"
gpec06
write '1' to disable clock for gpec06 / read for status
5 "0"
gpec05
write '1' to disable clock for gpec05 / read for status
4 "0"
gpec04
write '1' to disable clock for gpec04 / read for status
3 "0"
gpec03
write '1' to disable clock for gpec03 / read for status
2 "0"
gpec02
write '1' to disable clock for gpec02 / read for status
1 "0"
gpec01
write '1' to disable clock for gpec01 / read for status
0 "0"
gpec00
write '1' to disable clock for gpec00 / read for status



Base Address Area: gxc_buf_man

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_buf_man_gpec00
1 4 R/W gxc_buf_man_gpec10
2 8 R/W gxc_buf_man
3 c -  reserved

gxc_buf_man_gpec00
BMU port of 1st master (xPEC0):
This register address allows to access 16 buffer controllers, where each one handles buffer numbers (0..4) between up
to four processors. Due to the complex functionality in one register address, bits have different meaning depending on
request type and mode.
Getting a new buffer always happens with two command accesses:
1st: Write access: Tell the buf_manager the channel(s) (0..15) and whether you request read or write buffer.
Wait for two clock cycles, until new buffer number is calculated after any write access.
2nd: Read access: Read the buffer number (0..4).
This register is also accessible directly by xPEC0 with higher priority. Do not use this address, if xPEC0 uses the buffer manager.
R/W
0x00000007
Address : 0x07d62790
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 "0"
sm_update_dis
De-activate SM_auto_update mode by writing 1 to this bit.
10 "0"
sm_update_en
Activate SM_auto_update mode by writing 1 to this bit:
In SM_auto_update mode the requested buffer numbers of buffer managers 0..7 will automatically
be programmed to the FMMU_SM unit.
9 "0"
reset
Reset buf_manager controller of selected  channel (buf_nr).
This bit will automatically be reset.
8 "0"
parallel_mode
Activate parallel mode by writing 1 to this bit (other bits are ignored). To return to normal mode, write 0xffff0000 to this register.
In parallel mode, the behaviour of all bits of this register changes completely.
Parallel mode write access:
15.. 0:
Request bits of all 16 channels:
1: request new buffer or semaphore.
0: don't request buffer or semaphore.
31..16:
wr bits of all 16 channels:
1: request write buffer or semaphore.
0: request read buffer or semaphore.

Parallel mode read access:
1,0: Actual buffer number of channel 0.
 ...  
31,30: Actual buffer number of channel 15.

In parallel mode, the number of masters is limited to 2, resulting in 3 buffers per channel.
In parallel mode, buffers cannot be released without requesting new buffer numbers.
7 "0"
semaphore_mode
Activate 'semaphore mode' for this buf_nr by writing 1 to this bit. To return from semaphore-mode reset this channel.
In semaphore mode only buf_nr=0 (this master gets the semaphore) or
buf_nr=7 (master does not get semaphore) are returned.
Requesting or releasing a semaphore (by req_type) is allowed while switching to semaphore mode.
6 - 5 "00"
req_type
Request type bits are write-only:
00: request read buffer (or semaphore)
01: request write buffer (or release semaphore)
10: release write buffer (or release semaphore)
11: do not request new buffer or semaphore (used to only change channel)
4 0
-
 reserved
3 - 0 "0111"
buf_nr
Write access: number of buf_manager controller (0..15)
Read access: number of buffer (0..m+1), where m is the number of masters using this buf_manager


gxc_buf_man_gpec10
BMU port of 2nd master (xPEC1):
This register address allows to access 16 buffer controllers, where each one handles buffer numbers (0..4) between up
to four processors. Due to the complex functionality in one register address, bits have different meaning depending on
request type and mode.
Getting a new buffer always happens with two command accesses:
1st: Write access: Tell the buf_manager the channel(s) (0..15) and whether you request read or write buffer.
Wait for two clock cycles, until new buffer number is calculated after any write access.
2nd: Read access: Read the buffer number (0..4).
This register is also accessible directly by xPEC1 with higher priority. Do not use this address, if xPEC1 uses the buffer manager.
R/W
0x00000007
Address : 0x07d62794
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 "0"
sm_update_dis
De-activate SM_auto_update mode by writing 1 to this bit.
10 "0"
sm_update_en
Activate SM_auto_update mode by writing 1 to this bit:
In SM_auto_update mode the requested buffer numbers of buffer managers 0..7 will automatically
be programmed to the FMMU_SM unit.
9 "0"
reset
Reset buf_manager controller of selected  channel (buf_nr).
This bit will automatically be reset.
8 "0"
parallel_mode
Activate parallel mode by writing 1 to this bit (other bits are ignored). To return to normal mode, write 0xffff0000 to this register.
In parallel mode, the behaviour of all bits of this register changes completely.
Parallel mode write access:
15.. 0:
Request bits of all 16 channels:
1: request new buffer or semaphore.
0: don't request buffer or semaphore.
31..16:
wr bits of all 16 channels:
1: request write buffer or semaphore.
0: request read buffer or semaphore.

Parallel mode read access:
1,0: Actual buffer number of channel 0.
 ...  
31,30: Actual buffer number of channel 15.

In parallel mode, the number of masters is limited to 2, resulting in 3 buffers per channel.
In parallel mode, buffers cannot be released without requesting new buffer numbers.
7 "0"
semaphore_mode
Activate 'semaphore mode' for this buf_nr by writing 1 to this bit. To return from semaphore-mode reset this channel.
In semaphore mode only buf_nr=0 (this master gets the semaphore) or
buf_nr=7 (master does not get semaphore) are returned.
Requesting or releasing a semaphore (by req_type) is allowed while switching to semaphore mode.
6 - 5 "00"
req_type
Request type bits are write-only:
00: request read buffer (or semaphore)
01: request write buffer (or release semaphore)
10: release write buffer (or release semaphore)
11: do not request new buffer or semaphore (used to only change channel)
4 0
-
 reserved
3 - 0 "0111"
buf_nr
Write access: number of buf_manager controller (0..15)
Read access: number of buffer (0..m+1), where m is the number of masters using this buf_manager


gxc_buf_man
BMU-port of 3rd master (intlogic address area) or 4th master (intlogic-motion address area):
This register address allows to access 16 buffer controllers, where each one handles buffer numbers (0..4) between up
to four processors. Due to the complex functionality in one register address, bits have different meaning depending on
request type and mode.
Getting a new buffer always happens with two command accesses:
1st: Write access: Tell the buf_manager the channel(s) (0..15) and whether you request read or write buffer.
Wait for two clock cycles, until new buffer number is calculated after any write access.
2nd: Read access: Read the buffer number (0..4).
R/W
0x00000007
Address : 0x07d62798
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
reset
Reset buf_manager controller of selected  channel (buf_nr).
This bit will automatically be reset.
8 "0"
parallel_mode
Activate parallel mode by writing 1 to this bit (other bits are ignored). To return to normal mode, write 0xffff0000 to this register.
In parallel mode, the behaviour of all bits of this register changes completely.
Parallel mode write access:
15.. 0:
Request bits of all 16 channels:
1: request new buffer or semaphore.
0: don't request buffer or semaphore.
31..16:
wr bits of all 16 channels:
1: request write buffer or semaphore.
0: request read buffer or semaphore.

Parallel mode read access:
1,0: Actual buffer number of channel 0.
 ...  
31,30: Actual buffer number of channel 15.

In parallel mode, the number of masters is limited to 2, resulting in 3 buffers per channel.
In parallel mode, buffers cannot be released without requesting new buffer numbers.
7 "0"
semaphore_mode
Activate 'semaphore mode' for this buf_nr by writing 1 to this bit. To return from semaphore-mode reset this channel.
In semaphore mode only buf_nr=0 (this master gets the semaphore) or
buf_nr=7 (master does not get semaphore) are returned.
Requesting or releasing a semaphore (by req_type) is allowed while switching to semaphore mode.
6 - 5 "00"
req_type
Request type bits are write-only:
00: request read buffer (or semaphore)
01: request write buffer (or release semaphore)
10: release write buffer (or release semaphore)
11: do not request new buffer or semaphore (used to only change channel)
4 0
-
 reserved
3 - 0 "0111"
buf_nr
Write access: number of buf_manager controller (0..15)
Read access: number of buffer (0..m+1), where m is the number of masters using this buf_manager



Base Address Area: gxc_sys_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_gxc_sys_0_mbist_power0
1 4 R/W gen_ram_ctrl_gxc_sys_0_mbist_power1
2 8 R/W gen_ram_ctrl_gxc_sys_0_mbist_power2
3 c R/W gen_ram_ctrl_gxc_sys_0_mbist_power3
4 10 R/W gen_ram_ctrl_gxc_sys_0_mbist_power4
5 14 R/W gen_ram_ctrl_gxc_sys_0_mbist_power5
6 18 R/W gen_ram_ctrl_gxc_sys_0_mbist_power6
7 1c R/W gen_ram_ctrl_gxc_sys_0_mbist_power7
8 20 R/W gen_ram_ctrl_gxc_sys_0_mbist_power8
9 24 R/W gen_ram_ctrl_gxc_sys_0_mbist_power9
a 28 R/W gen_ram_ctrl_gxc_sys_0_mbist_power10
b 2c R/W gen_ram_ctrl_gxc_sys_0_mbist_power11
c 30 R/W gen_ram_ctrl_gxc_sys_0_mbist_power12
d 34 R/W gen_ram_ctrl_gxc_sys_0_mbist_power13
e 38 R/W gen_ram_ctrl_gxc_sys_0_mbist_power14
f 3c R/W gen_ram_ctrl_gxc_sys_0_mbist_power15
10 40 R/W gen_ram_ctrl_gxc_sys_0_mbist_power16
11 44 R/W gen_ram_ctrl_gxc_sys_0_mbist_power17
12 48 R/W gen_ram_ctrl_gxc_sys_0_mbist_power18
13 4c R/W gen_ram_ctrl_gxc_sys_0_mbist_power19
14 50 R/W gen_ram_ctrl_gxc_sys_0_mbist_power20
15 54 R/W gen_ram_ctrl_gxc_sys_0_mbist_power21
16 58 R/W gen_ram_ctrl_gxc_sys_0_mbist_power22
17 5c R/W gen_ram_ctrl_gxc_sys_0_mbist_power23
18 60 R/W gen_ram_ctrl_gxc_sys_0_mbist_power24
19 64 R/W gen_ram_ctrl_gxc_sys_0_mbist_power25
1a 68 R/W gen_ram_ctrl_gxc_sys_0_mbist_power26
1b 6c R/W gen_ram_ctrl_gxc_sys_0_mbist_power27
1c 70 R/W gen_ram_ctrl_gxc_sys_0_mbist_power28
1d 74 R/W gen_ram_ctrl_gxc_sys_0_mbist_power29
1e 78 R/W gen_ram_ctrl_gxc_sys_0_mbist_power30
1f 7c R/W gen_ram_ctrl_gxc_sys_0_mbist_power31
20 80 R/W gen_ram_ctrl_gxc_sys_0_mbist_power32
21 84 R/W gen_ram_ctrl_gxc_sys_0_mbist_power33
22 88 R/W gen_ram_ctrl_gxc_sys_0_mbist_power34
23 8c R/W gen_ram_ctrl_gxc_sys_0_mbist_power35
24 90 R/W gen_ram_ctrl_gxc_sys_0_mbist_power36
25 94 R/W gen_ram_ctrl_gxc_sys_0_mbist_power37
26 98 R/W gen_ram_ctrl_gxc_sys_0_mbist_power38
27 9c R/W gen_ram_ctrl_gxc_sys_0_mbist_power39
28 a0 R/W gen_ram_ctrl_gxc_sys_0_mbist_power40
29 a4 R/W gen_ram_ctrl_gxc_sys_0_mbist_power41
2a a8 R/W gen_ram_ctrl_gxc_sys_0_mbist_power42
2b ac R/W gen_ram_ctrl_gxc_sys_0_mbist_power43
2c b0 R/W gen_ram_ctrl_gxc_sys_0_mbist_power44
2d b4 R/W gen_ram_ctrl_gxc_sys_0_mbist_power45
2e b8 R/W gen_ram_ctrl_gxc_sys_0_mbist_power46
2f bc R/W gen_ram_ctrl_gxc_sys_0_mbist_power47
30 c0 R/W gen_ram_ctrl_gxc_sys_0_mbist_power48
31 c4 R/W gen_ram_ctrl_gxc_sys_0_mbist_power49
32 c8 R/W gen_ram_ctrl_gxc_sys_0_mbist_power50
33 cc R/W gen_ram_ctrl_gxc_sys_0_mbist_power51
34 d0 R/W gen_ram_ctrl_gxc_sys_0_mbist_power52
35-1ff d4-7fc -  reserved
200 800 R/W gen_ram_ctrl_gxc_sys_0_ecc0
201 804 R/W gen_ram_ctrl_gxc_sys_0_ecc1
202 808 R/W gen_ram_ctrl_gxc_sys_0_ecc2
203 80c R/W gen_ram_ctrl_gxc_sys_0_ecc3
204 810 R/W gen_ram_ctrl_gxc_sys_0_ecc4
205 814 R/W gen_ram_ctrl_gxc_sys_0_ecc5
206 818 R/W gen_ram_ctrl_gxc_sys_0_ecc6
207 81c R/W gen_ram_ctrl_gxc_sys_0_ecc7
208 820 R/W gen_ram_ctrl_gxc_sys_0_ecc8
209 824 R/W gen_ram_ctrl_gxc_sys_0_ecc9
20a 828 R/W gen_ram_ctrl_gxc_sys_0_ecc10
20b 82c R/W gen_ram_ctrl_gxc_sys_0_ecc11
20c 830 R/W gen_ram_ctrl_gxc_sys_0_ecc12
20d 834 R/W gen_ram_ctrl_gxc_sys_0_ecc13
20e 838 R/W gen_ram_ctrl_gxc_sys_0_ecc14
20f 83c R/W gen_ram_ctrl_gxc_sys_0_ecc15
210 840 R/W gen_ram_ctrl_gxc_sys_0_ecc16
211 844 R/W gen_ram_ctrl_gxc_sys_0_ecc17
212 848 R/W gen_ram_ctrl_gxc_sys_0_ecc18
213 84c R/W gen_ram_ctrl_gxc_sys_0_ecc19
214 850 R/W gen_ram_ctrl_gxc_sys_0_ecc20
215 854 R/W gen_ram_ctrl_gxc_sys_0_ecc21
216 858 R/W gen_ram_ctrl_gxc_sys_0_ecc22
217 85c R/W gen_ram_ctrl_gxc_sys_0_ecc23
218 860 R/W gen_ram_ctrl_gxc_sys_0_ecc24
219 864 R/W gen_ram_ctrl_gxc_sys_0_ecc25
21a 868 R/W gen_ram_ctrl_gxc_sys_0_ecc26
21b 86c R/W gen_ram_ctrl_gxc_sys_0_ecc27
21c 870 R/W gen_ram_ctrl_gxc_sys_0_ecc28
21d 874 R/W gen_ram_ctrl_gxc_sys_0_ecc29
21e 878 R/W gen_ram_ctrl_gxc_sys_0_ecc30
21f 87c R/W gen_ram_ctrl_gxc_sys_0_ecc31
220 880 R/W gen_ram_ctrl_gxc_sys_0_ecc32
221 884 R/W gen_ram_ctrl_gxc_sys_0_ecc33
222 888 R/W gen_ram_ctrl_gxc_sys_0_ecc34
223 88c R/W gen_ram_ctrl_gxc_sys_0_ecc35
224 890 R/W gen_ram_ctrl_gxc_sys_0_ecc36
225 894 R/W gen_ram_ctrl_gxc_sys_0_ecc37
226 898 R/W gen_ram_ctrl_gxc_sys_0_ecc38
227 89c R/W gen_ram_ctrl_gxc_sys_0_ecc39
228 8a0 R/W gen_ram_ctrl_gxc_sys_0_ecc40
229 8a4 R/W gen_ram_ctrl_gxc_sys_0_ecc41
22a 8a8 R/W gen_ram_ctrl_gxc_sys_0_ecc42
22b 8ac R/W gen_ram_ctrl_gxc_sys_0_ecc43
22c 8b0 R/W gen_ram_ctrl_gxc_sys_0_ecc44
22d-27f 8b4-9fc -  reserved
280 a00 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr0
281 a04 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr1
282 a08 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr2
283 a0c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr3
284 a10 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr4
285 a14 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr5
286 a18 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr6
287 a1c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr7
288 a20 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr8
289 a24 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr9
28a a28 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr10
28b a2c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr11
28c a30 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr12
28d a34 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr13
28e a38 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr14
28f a3c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr15
290 a40 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr16
291 a44 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr17
292 a48 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr18
293 a4c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr19
294 a50 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr20
295 a54 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr21
296 a58 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr22
297 a5c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr23
298 a60 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr24
299 a64 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr25
29a a68 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr26
29b a6c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr27
29c a70 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr28
29d a74 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr29
29e a78 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr30
29f a7c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr31
2a0 a80 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr32
2a1 a84 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr33
2a2 a88 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr34
2a3 a8c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr35
2a4 a90 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr36
2a5 a94 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr37
2a6 a98 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr38
2a7 a9c R gen_ram_ctrl_gxc_sys_0_ecc_status_corr39
2a8 aa0 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr40
2a9 aa4 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr41
2aa aa8 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr42
2ab aac R gen_ram_ctrl_gxc_sys_0_ecc_status_corr43
2ac ab0 R gen_ram_ctrl_gxc_sys_0_ecc_status_corr44
2ad-2ff ab4-bfc -  reserved
300 c00 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr3
304 c10 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr4
305 c14 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr5
306 c18 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr6
307 c1c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr7
308 c20 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr8
309 c24 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr9
30a c28 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr10
30b c2c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr11
30c c30 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr12
30d c34 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr13
30e c38 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr14
30f c3c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr15
310 c40 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr16
311 c44 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr17
312 c48 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr18
313 c4c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr19
314 c50 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr20
315 c54 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr21
316 c58 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr22
317 c5c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr23
318 c60 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr24
319 c64 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr25
31a c68 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr26
31b c6c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr27
31c c70 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr28
31d c74 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr29
31e c78 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr30
31f c7c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr31
320 c80 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr32
321 c84 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr33
322 c88 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr34
323 c8c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr35
324 c90 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr36
325 c94 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr37
326 c98 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr38
327 c9c R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr39
328 ca0 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr40
329 ca4 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr41
32a ca8 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr42
32b cac R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr43
32c cb0 R gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr44
32d-37f cb4-dfc -  reserved
380 e00 R/W gen_ram_ctrl_gxc_sys_0_irq_raw_reg0
381 e04 R/W gen_ram_ctrl_gxc_sys_0_irq_raw_reg1
382 e08 R/W gen_ram_ctrl_gxc_sys_0_irq_raw_reg2
383 e0c R/W gen_ram_ctrl_gxc_sys_0_irq_raw_reg3
384 e10 R/W gen_ram_ctrl_gxc_sys_0_irq_raw_reg4
385-38f e14-e3c -  reserved
390 e40 R/W gen_ram_ctrl_gxc_sys_0_irq_masked_reg0
391 e44 R/W gen_ram_ctrl_gxc_sys_0_irq_masked_reg1
392 e48 R/W gen_ram_ctrl_gxc_sys_0_irq_masked_reg2
393 e4c R/W gen_ram_ctrl_gxc_sys_0_irq_masked_reg3
394 e50 R/W gen_ram_ctrl_gxc_sys_0_irq_masked_reg4
395-39f e54-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg0
3a1 e84 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg1
3a2 e88 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg2
3a3 e8c R/W gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg3
3a4 e90 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg4
3a5-3af e94-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg0
3b1 ec4 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg1
3b2 ec8 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg2
3b3 ecc R/W gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg3
3b4 ed0 R/W gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg4
3b5-3be ed4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_gxc_sys_0_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_gxc_sys_0_mbist_power0
MBIST/power control and status register
For memory gxc_i.gxc_esc_unit_i.esc_sram2048x32_pram_i (2048x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power1
MBIST/power control and status register
For memory gxc_i.port[0].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power2
MBIST/power control and status register
For memory gxc_i.port[0].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power3
MBIST/power control and status register
For memory gxc_i.port[0].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6300c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power4
MBIST/power control and status register
For memory gxc_i.port[0].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power5
MBIST/power control and status register
For memory gxc_i.port[0].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power6
MBIST/power control and status register
For memory gxc_i.port[0].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power7
MBIST/power control and status register
For memory gxc_i.port[0].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6301c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power8
MBIST/power control and status register
For memory gxc_i.port[0].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63020
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power9
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63024
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power10
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63028
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power11
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6302c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power12
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63030
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power13
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63034
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power14
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63038
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power15
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6303c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power16
MBIST/power control and status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63040
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power17
MBIST/power control and status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63044
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power18
MBIST/power control and status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63048
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power19
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i0.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6304c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power20
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i1.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63050
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power21
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d63054
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power22
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i0.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63058
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power23
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i1.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6305c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power24
MBIST/power control and status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d63060
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power25
MBIST/power control and status register
For memory gxc_i.port[1].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63064
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power26
MBIST/power control and status register
For memory gxc_i.port[1].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63068
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power27
MBIST/power control and status register
For memory gxc_i.port[1].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6306c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power28
MBIST/power control and status register
For memory gxc_i.port[1].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63070
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power29
MBIST/power control and status register
For memory gxc_i.port[1].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63074
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power30
MBIST/power control and status register
For memory gxc_i.port[1].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63078
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power31
MBIST/power control and status register
For memory gxc_i.port[1].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6307c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power32
MBIST/power control and status register
For memory gxc_i.port[1].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63080
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power33
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63084
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power34
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63088
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power35
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6308c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power36
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63090
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power37
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63094
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power38
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d63098
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power39
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d6309c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power40
MBIST/power control and status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630a0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power41
MBIST/power control and status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630a4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power42
MBIST/power control and status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630a8
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power43
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i0.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630ac
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power44
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i1.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630b0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power45
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630b4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power46
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i0.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630b8
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power47
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_config_i00.gxc_rate_limiter_i.gxc_token_bucket_instance_i1.bucket_mem_i (8x53 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x07d630bc
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power48
MBIST/power control and status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630c0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power49
MBIST/power control and status register
For memory intram[0].gxc_sys_intram_i (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630c4
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power50
MBIST/power control and status register
For memory intram[1].gxc_sys_intram_i (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630c8
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power51
MBIST/power control and status register
For memory intram[2].gxc_sys_intram_i (4096x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630cc
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_mbist_power52
MBIST/power control and status register
For memory intram[3].gxc_sys_intram_i (4096x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x07d630d0
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gxc_sys_0_ecc0
ECC control and status register
For memory gxc_i.gxc_esc_unit_i.esc_sram2048x32_pram_i (2048x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc1
ECC control and status register
For memory gxc_i.port[0].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc2
ECC control and status register
For memory gxc_i.port[0].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc3
ECC control and status register
For memory gxc_i.port[0].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6380c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc4
ECC control and status register
For memory gxc_i.port[0].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63810
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc5
ECC control and status register
For memory gxc_i.port[0].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63814
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc6
ECC control and status register
For memory gxc_i.port[0].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63818
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc7
ECC control and status register
For memory gxc_i.port[0].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6381c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc8
ECC control and status register
For memory gxc_i.port[0].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63820
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc9
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63824
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc10
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63828
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc11
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d6382c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc12
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63830
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc13
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63834
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc14
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63838
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc15
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d6383c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc16
ECC control and status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63840
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc17
ECC control and status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x07d63844
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc18
ECC control and status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x07d63848
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc19
ECC control and status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6384c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc20
ECC control and status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63850
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc21
ECC control and status register
For memory gxc_i.port[1].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63854
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc22
ECC control and status register
For memory gxc_i.port[1].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63858
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc23
ECC control and status register
For memory gxc_i.port[1].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6385c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc24
ECC control and status register
For memory gxc_i.port[1].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63860
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc25
ECC control and status register
For memory gxc_i.port[1].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63864
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc26
ECC control and status register
For memory gxc_i.port[1].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63868
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc27
ECC control and status register
For memory gxc_i.port[1].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6386c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc28
ECC control and status register
For memory gxc_i.port[1].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d63870
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc29
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63874
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc30
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63878
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc31
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d6387c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc32
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63880
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc33
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63884
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc34
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63888
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc35
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d6388c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc36
ECC control and status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d63890
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc37
ECC control and status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x07d63894
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc38
ECC control and status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x07d63898
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc39
ECC control and status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d6389c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc40
ECC control and status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x07d638a0
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc41
ECC control and status register
For memory intram[0].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d638a4
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc42
ECC control and status register
For memory intram[1].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d638a8
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc43
ECC control and status register
For memory intram[2].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d638ac
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc44
ECC control and status register
For memory intram[3].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x07d638b0
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr0
ECC status register
For memory gxc_i.gxc_esc_unit_i.esc_sram2048x32_pram_i (2048x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr1
ECC status register
For memory gxc_i.port[0].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr2
ECC status register
For memory gxc_i.port[0].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr3
ECC status register
For memory gxc_i.port[0].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr4
ECC status register
For memory gxc_i.port[0].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr5
ECC status register
For memory gxc_i.port[0].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr6
ECC status register
For memory gxc_i.port[0].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr7
ECC status register
For memory gxc_i.port[0].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr8
ECC status register
For memory gxc_i.port[0].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a20
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr9
ECC status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a24
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr10
ECC status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a28
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr11
ECC status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a2c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr12
ECC status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a30
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr13
ECC status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a34
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr14
ECC status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a38
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr15
ECC status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a3c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr16
ECC status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a40
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr17
ECC status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a44
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr18
ECC status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a48
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr19
ECC status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a4c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr20
ECC status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a50
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr21
ECC status register
For memory gxc_i.port[1].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a54
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr22
ECC status register
For memory gxc_i.port[1].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a58
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr23
ECC status register
For memory gxc_i.port[1].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a5c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr24
ECC status register
For memory gxc_i.port[1].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a60
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr25
ECC status register
For memory gxc_i.port[1].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a64
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr26
ECC status register
For memory gxc_i.port[1].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a68
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr27
ECC status register
For memory gxc_i.port[1].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a6c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr28
ECC status register
For memory gxc_i.port[1].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a70
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr29
ECC status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a74
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr30
ECC status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a78
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr31
ECC status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a7c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr32
ECC status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a80
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr33
ECC status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a84
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr34
ECC status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a88
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr35
ECC status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a8c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr36
ECC status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a90
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr37
ECC status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a94
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr38
ECC status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a98
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr39
ECC status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63a9c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr40
ECC status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63aa0
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr41
ECC status register
For memory intram[0].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63aa4
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr42
ECC status register
For memory intram[1].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63aa8
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr43
ECC status register
For memory intram[2].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63aac
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_corr44
ECC status register
For memory intram[3].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63ab0
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr0
ECC status register
For memory gxc_i.gxc_esc_unit_i.esc_sram2048x32_pram_i (2048x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr1
ECC status register
For memory gxc_i.port[0].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr2
ECC status register
For memory gxc_i.port[0].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr3
ECC status register
For memory gxc_i.port[0].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr4
ECC status register
For memory gxc_i.port[0].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr5
ECC status register
For memory gxc_i.port[0].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr6
ECC status register
For memory gxc_i.port[0].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr7
ECC status register
For memory gxc_i.port[0].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr8
ECC status register
For memory gxc_i.port[0].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c20
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr9
ECC status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c24
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr10
ECC status register
For memory gxc_i.port[0].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c28
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr11
ECC status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c2c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr12
ECC status register
For memory gxc_i.port[0].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c30
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr13
ECC status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c34
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr14
ECC status register
For memory gxc_i.port[0].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c38
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr15
ECC status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c3c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr16
ECC status register
For memory gxc_i.port[0].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c40
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr17
ECC status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c44
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr18
ECC status register
For memory gxc_i.port[0].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c48
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr19
ECC status register
For memory gxc_i.port[0].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c4c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr20
ECC status register
For memory gxc_i.port[0].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c50
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr21
ECC status register
For memory gxc_i.port[1].gpec[0].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c54
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr22
ECC status register
For memory gxc_i.port[1].gpec[1].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c58
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr23
ECC status register
For memory gxc_i.port[1].gpec[2].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c5c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr24
ECC status register
For memory gxc_i.port[1].gpec[3].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c60
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr25
ECC status register
For memory gxc_i.port[1].gpec[4].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c64
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr26
ECC status register
For memory gxc_i.port[1].gpec[5].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c68
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr27
ECC status register
For memory gxc_i.port[1].gpec[6].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c6c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr28
ECC status register
For memory gxc_i.port[1].gpec[7].gxc_gpec_i.gpec_pram_i (1024x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c70
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr29
ECC status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c74
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr30
ECC status register
For memory gxc_i.port[1].gpec_dpram[0].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c78
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr31
ECC status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c7c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr32
ECC status register
For memory gxc_i.port[1].gpec_dpram[1].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c80
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr33
ECC status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c84
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr34
ECC status register
For memory gxc_i.port[1].gpec_dpram[2].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c88
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr35
ECC status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_a_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c8c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr36
ECC status register
For memory gxc_i.port[1].gpec_dpram[3].gxc_gpec_dpram_i.gpec_dram_b_i (2032x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c90
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr37
ECC status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_rpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c94
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr38
ECC status register
For memory gxc_i.port[1].gxc_gmac_i.gmac_tpu_i.program_ram (192x64 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c98
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr39
ECC status register
For memory gxc_i.port[1].pfifo[0].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63c9c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr40
ECC status register
For memory gxc_i.port[1].pfifo[1].gxc_pfifo_i.gxc_fifo_gen_i.gxc_pfifo_sram16kx32_i (4096x32 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63ca0
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr41
ECC status register
For memory intram[0].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63ca4
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr42
ECC status register
For memory intram[1].gxc_sys_intram_i (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63ca8
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr43
ECC status register
For memory intram[2].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63cac
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_ecc_status_noncorr44
ECC status register
For memory intram[3].gxc_sys_intram_i (4096x128 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x07d63cb0
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gxc_sys_0_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d63e00
Bits Reset value Name Description
31 "0"
mem_31_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
30 "0"
mem_30_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
29 "0"
mem_29_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
28 "0"
mem_28_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
27 "0"
mem_27_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
26 "0"
mem_26_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
25 "0"
mem_25_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
24 "0"
mem_24_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
23 "0"
mem_23_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
22 "0"
mem_22_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
21 "0"
mem_21_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
20 "0"
mem_20_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
19 "0"
mem_19_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
18 "0"
mem_18_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
17 "0"
mem_17_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
16 "0"
mem_16_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
15 "0"
mem_15_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
14 "0"
mem_14_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
13 "0"
mem_13_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
12 "0"
mem_12_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_11_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_10_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_9_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_raw_reg1
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d63e04
Bits Reset value Name Description
31 "0"
mem_18_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
30 "0"
mem_17_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
29 "0"
mem_16_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
28 "0"
mem_15_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
27 "0"
mem_14_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
26 "0"
mem_13_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
25 "0"
mem_12_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_11_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_10_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_9_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_44_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_43_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_42_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_41_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_40_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_39_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_38_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_37_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_36_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_35_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_34_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_33_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_32_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_raw_reg2
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d63e08
Bits Reset value Name Description
31 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_44_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_43_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_42_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_41_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_40_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_39_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_38_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_37_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_36_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_35_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_34_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_33_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_32_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_31_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_30_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_29_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_28_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_27_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_26_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_25_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_24_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_23_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_22_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_21_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_20_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_19_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_raw_reg3
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d63e0c
Bits Reset value Name Description
31 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_raw_reg4
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d63e10
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
mem_52_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_51_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_50_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_49_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_48_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_47_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_46_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg0).
R/W
0x00000000
Address : 0x07d63e40
Bits Reset value Name Description
31 "0"
mem_31_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
30 "0"
mem_30_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
29 "0"
mem_29_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
28 "0"
mem_28_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
27 "0"
mem_27_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
26 "0"
mem_26_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
25 "0"
mem_25_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
24 "0"
mem_24_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
23 "0"
mem_23_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
22 "0"
mem_22_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
21 "0"
mem_21_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
20 "0"
mem_20_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
19 "0"
mem_19_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
18 "0"
mem_18_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
17 "0"
mem_17_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
16 "0"
mem_16_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
15 "0"
mem_15_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
14 "0"
mem_14_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
13 "0"
mem_13_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
12 "0"
mem_12_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_11_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_10_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_9_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_masked_reg1
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg1).
R/W
0x00000000
Address : 0x07d63e44
Bits Reset value Name Description
31 "0"
mem_18_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
30 "0"
mem_17_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
29 "0"
mem_16_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
28 "0"
mem_15_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
27 "0"
mem_14_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
26 "0"
mem_13_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
25 "0"
mem_12_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_11_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_10_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_9_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_44_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_43_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_42_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_41_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_40_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_39_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_38_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_37_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_36_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_35_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_34_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_33_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_32_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_masked_reg2
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg2).
R/W
0x00000000
Address : 0x07d63e48
Bits Reset value Name Description
31 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_44_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_43_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_42_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_41_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_40_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_39_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_38_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_37_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_36_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_35_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_34_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_33_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_32_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_31_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_30_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_29_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_28_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_27_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_26_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_25_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_24_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_23_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_22_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_21_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_20_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_19_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_masked_reg3
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg3).
R/W
0x00000000
Address : 0x07d63e4c
Bits Reset value Name Description
31 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_masked_reg4
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg4).
R/W
0x00000000
Address : 0x07d63e50
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
mem_52_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_51_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_50_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_49_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_48_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_47_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_46_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg0
R/W
0x00000000
Address : 0x07d63e80
Bits Reset value Name Description
31 "0"
mem_31_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
30 "0"
mem_30_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
29 "0"
mem_29_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
28 "0"
mem_28_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
27 "0"
mem_27_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
26 "0"
mem_26_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
25 "0"
mem_25_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
24 "0"
mem_24_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
23 "0"
mem_23_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
22 "0"
mem_22_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
21 "0"
mem_21_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
20 "0"
mem_20_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
19 "0"
mem_19_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
18 "0"
mem_18_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
17 "0"
mem_17_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
16 "0"
mem_16_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
15 "0"
mem_15_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
14 "0"
mem_14_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
13 "0"
mem_13_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
12 "0"
mem_12_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_11_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_10_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_9_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg1
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg1
R/W
0x00000000
Address : 0x07d63e84
Bits Reset value Name Description
31 "0"
mem_18_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
30 "0"
mem_17_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
29 "0"
mem_16_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
28 "0"
mem_15_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
27 "0"
mem_14_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
26 "0"
mem_13_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
25 "0"
mem_12_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_11_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_10_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_9_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_44_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_43_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_42_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_41_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_40_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_39_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_38_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_37_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_36_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_35_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_34_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_33_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_32_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg2
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg2
R/W
0x00000000
Address : 0x07d63e88
Bits Reset value Name Description
31 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_44_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_43_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_42_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_41_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_40_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_39_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_38_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_37_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_36_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_35_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_34_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_33_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_32_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_31_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_30_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_29_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_28_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_27_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_26_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_25_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_24_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_23_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_22_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_21_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_20_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_19_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg3
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg3
R/W
0x00000000
Address : 0x07d63e8c
Bits Reset value Name Description
31 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_mask_set_reg4
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gxc_sys_0_irq_raw_reg4
R/W
0x00000000
Address : 0x07d63e90
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
mem_52_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_51_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_50_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_49_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_48_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_47_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_46_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 143 when no IRQ is set:
  0   : irq_reg0-mem_0_err_ecc_non_correctable
  1   : irq_reg0-mem_1_err_ecc_non_correctable
  2   : irq_reg0-mem_2_err_ecc_non_correctable
  3   : irq_reg0-mem_3_err_ecc_non_correctable
  4   : irq_reg0-mem_4_err_ecc_non_correctable
  5   : irq_reg0-mem_5_err_ecc_non_correctable
  6   : irq_reg0-mem_6_err_ecc_non_correctable
  7   : irq_reg0-mem_7_err_ecc_non_correctable
  8   : irq_reg0-mem_8_err_ecc_non_correctable
  9   : irq_reg0-mem_9_err_ecc_non_correctable
  10  : irq_reg0-mem_10_err_ecc_non_correctable
  11  : irq_reg0-mem_11_err_ecc_non_correctable
  12  : irq_reg0-mem_12_err_ecc_non_correctable
  13  : irq_reg0-mem_13_err_ecc_non_correctable
  14  : irq_reg0-mem_14_err_ecc_non_correctable
  15  : irq_reg0-mem_15_err_ecc_non_correctable
  16  : irq_reg0-mem_16_err_ecc_non_correctable
  17  : irq_reg0-mem_17_err_ecc_non_correctable
  18  : irq_reg0-mem_18_err_ecc_non_correctable
  19  : irq_reg0-mem_19_err_ecc_non_correctable
  20  : irq_reg0-mem_20_err_ecc_non_correctable
  21  : irq_reg0-mem_21_err_ecc_non_correctable
  22  : irq_reg0-mem_22_err_ecc_non_correctable
  23  : irq_reg0-mem_23_err_ecc_non_correctable
  24  : irq_reg0-mem_24_err_ecc_non_correctable
  25  : irq_reg0-mem_25_err_ecc_non_correctable
  26  : irq_reg0-mem_26_err_ecc_non_correctable
  27  : irq_reg0-mem_27_err_ecc_non_correctable
  28  : irq_reg0-mem_28_err_ecc_non_correctable
  29  : irq_reg0-mem_29_err_ecc_non_correctable
  30  : irq_reg0-mem_30_err_ecc_non_correctable
  31  : irq_reg0-mem_31_err_ecc_non_correctable
  32  : irq_reg1-mem_32_err_ecc_non_correctable
  33  : irq_reg1-mem_33_err_ecc_non_correctable
  34  : irq_reg1-mem_34_err_ecc_non_correctable
  35  : irq_reg1-mem_35_err_ecc_non_correctable
  36  : irq_reg1-mem_36_err_ecc_non_correctable
  37  : irq_reg1-mem_37_err_ecc_non_correctable
  38  : irq_reg1-mem_38_err_ecc_non_correctable
  39  : irq_reg1-mem_39_err_ecc_non_correctable
  40  : irq_reg1-mem_40_err_ecc_non_correctable
  41  : irq_reg1-mem_41_err_ecc_non_correctable
  42  : irq_reg1-mem_42_err_ecc_non_correctable
  43  : irq_reg1-mem_43_err_ecc_non_correctable
  44  : irq_reg1-mem_44_err_ecc_non_correctable
  45  : irq_reg1-mem_0_err_ecc_correctable
  46  : irq_reg1-mem_1_err_ecc_correctable
  47  : irq_reg1-mem_2_err_ecc_correctable
  48  : irq_reg1-mem_3_err_ecc_correctable
  49  : irq_reg1-mem_4_err_ecc_correctable
  50  : irq_reg1-mem_5_err_ecc_correctable
  51  : irq_reg1-mem_6_err_ecc_correctable
  52  : irq_reg1-mem_7_err_ecc_correctable
  53  : irq_reg1-mem_8_err_ecc_correctable
  54  : irq_reg1-mem_9_err_ecc_correctable
  55  : irq_reg1-mem_10_err_ecc_correctable
  56  : irq_reg1-mem_11_err_ecc_correctable
  57  : irq_reg1-mem_12_err_ecc_correctable
  58  : irq_reg1-mem_13_err_ecc_correctable
  59  : irq_reg1-mem_14_err_ecc_correctable
  60  : irq_reg1-mem_15_err_ecc_correctable
  61  : irq_reg1-mem_16_err_ecc_correctable
  62  : irq_reg1-mem_17_err_ecc_correctable
  63  : irq_reg1-mem_18_err_ecc_correctable
  64  : irq_reg2-mem_19_err_ecc_correctable
  65  : irq_reg2-mem_20_err_ecc_correctable
  66  : irq_reg2-mem_21_err_ecc_correctable
  67  : irq_reg2-mem_22_err_ecc_correctable
  68  : irq_reg2-mem_23_err_ecc_correctable
  69  : irq_reg2-mem_24_err_ecc_correctable
  70  : irq_reg2-mem_25_err_ecc_correctable
  71  : irq_reg2-mem_26_err_ecc_correctable
  72  : irq_reg2-mem_27_err_ecc_correctable
  73  : irq_reg2-mem_28_err_ecc_correctable
  74  : irq_reg2-mem_29_err_ecc_correctable
  75  : irq_reg2-mem_30_err_ecc_correctable
  76  : irq_reg2-mem_31_err_ecc_correctable
  77  : irq_reg2-mem_32_err_ecc_correctable
  78  : irq_reg2-mem_33_err_ecc_correctable
  79  : irq_reg2-mem_34_err_ecc_correctable
  80  : irq_reg2-mem_35_err_ecc_correctable
  81  : irq_reg2-mem_36_err_ecc_correctable
  82  : irq_reg2-mem_37_err_ecc_correctable
  83  : irq_reg2-mem_38_err_ecc_correctable
  84  : irq_reg2-mem_39_err_ecc_correctable
  85  : irq_reg2-mem_40_err_ecc_correctable
  86  : irq_reg2-mem_41_err_ecc_correctable
  87  : irq_reg2-mem_42_err_ecc_correctable
  88  : irq_reg2-mem_43_err_ecc_correctable
  89  : irq_reg2-mem_44_err_ecc_correctable
  90  : irq_reg2-mem_0_mbist_or_init_finished
  91  : irq_reg2-mem_1_mbist_or_init_finished
  92  : irq_reg2-mem_2_mbist_or_init_finished
  93  : irq_reg2-mem_3_mbist_or_init_finished
  94  : irq_reg2-mem_4_mbist_or_init_finished
  95  : irq_reg2-mem_5_mbist_or_init_finished
  96  : irq_reg3-mem_6_mbist_or_init_finished
  97  : irq_reg3-mem_7_mbist_or_init_finished
  98  : irq_reg3-mem_8_mbist_or_init_finished
  99  : irq_reg3-mem_9_mbist_or_init_finished
  100 : irq_reg3-mem_10_mbist_or_init_finished
  101 : irq_reg3-mem_11_mbist_or_init_finished
  102 : irq_reg3-mem_12_mbist_or_init_finished
  103 : irq_reg3-mem_13_mbist_or_init_finished
  104 : irq_reg3-mem_14_mbist_or_init_finished
  105 : irq_reg3-mem_15_mbist_or_init_finished
  106 : irq_reg3-mem_16_mbist_or_init_finished
  107 : irq_reg3-mem_17_mbist_or_init_finished
  108 : irq_reg3-mem_18_mbist_or_init_finished
  109 : irq_reg3-mem_19_mbist_or_init_finished
  110 : irq_reg3-mem_20_mbist_or_init_finished
  111 : irq_reg3-mem_21_mbist_or_init_finished
  112 : irq_reg3-mem_22_mbist_or_init_finished
  113 : irq_reg3-mem_23_mbist_or_init_finished
  114 : irq_reg3-mem_24_mbist_or_init_finished
  115 : irq_reg3-mem_25_mbist_or_init_finished
  116 : irq_reg3-mem_26_mbist_or_init_finished
  117 : irq_reg3-mem_27_mbist_or_init_finished
  118 : irq_reg3-mem_28_mbist_or_init_finished
  119 : irq_reg3-mem_29_mbist_or_init_finished
  120 : irq_reg3-mem_30_mbist_or_init_finished
  121 : irq_reg3-mem_31_mbist_or_init_finished
  122 : irq_reg3-mem_32_mbist_or_init_finished
  123 : irq_reg3-mem_33_mbist_or_init_finished
  124 : irq_reg3-mem_34_mbist_or_init_finished
  125 : irq_reg3-mem_35_mbist_or_init_finished
  126 : irq_reg3-mem_36_mbist_or_init_finished
  127 : irq_reg3-mem_37_mbist_or_init_finished
  128 : irq_reg4-mem_38_mbist_or_init_finished
  129 : irq_reg4-mem_39_mbist_or_init_finished
  130 : irq_reg4-mem_40_mbist_or_init_finished
  131 : irq_reg4-mem_41_mbist_or_init_finished
  132 : irq_reg4-mem_42_mbist_or_init_finished
  133 : irq_reg4-mem_43_mbist_or_init_finished
  134 : irq_reg4-mem_44_mbist_or_init_finished
  135 : irq_reg4-mem_45_mbist_or_init_finished
  136 : irq_reg4-mem_46_mbist_or_init_finished
  137 : irq_reg4-mem_47_mbist_or_init_finished
  138 : irq_reg4-mem_48_mbist_or_init_finished
  139 : irq_reg4-mem_49_mbist_or_init_finished
  140 : irq_reg4-mem_50_mbist_or_init_finished
  141 : irq_reg4-mem_51_mbist_or_init_finished
  142 : irq_reg4-mem_52_mbist_or_init_finished
  143 : no active IRQ
R/W
0x00000000
Address : 0x07d63ec0
Bits Reset value Name Description
31 "0"
mem_31_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
30 "0"
mem_30_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
29 "0"
mem_29_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
28 "0"
mem_28_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
27 "0"
mem_27_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
26 "0"
mem_26_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
25 "0"
mem_25_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
24 "0"
mem_24_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
23 "0"
mem_23_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
22 "0"
mem_22_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
21 "0"
mem_21_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
20 "0"
mem_20_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
19 "0"
mem_19_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
18 "0"
mem_18_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
17 "0"
mem_17_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
16 "0"
mem_16_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
15 "0"
mem_15_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
14 "0"
mem_14_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
13 "0"
mem_13_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
12 "0"
mem_12_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_11_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_10_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_9_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg1
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 143 when no IRQ is set:
  0   : irq_reg0-mem_0_err_ecc_non_correctable
  1   : irq_reg0-mem_1_err_ecc_non_correctable
  2   : irq_reg0-mem_2_err_ecc_non_correctable
  3   : irq_reg0-mem_3_err_ecc_non_correctable
  4   : irq_reg0-mem_4_err_ecc_non_correctable
  5   : irq_reg0-mem_5_err_ecc_non_correctable
  6   : irq_reg0-mem_6_err_ecc_non_correctable
  7   : irq_reg0-mem_7_err_ecc_non_correctable
  8   : irq_reg0-mem_8_err_ecc_non_correctable
  9   : irq_reg0-mem_9_err_ecc_non_correctable
  10  : irq_reg0-mem_10_err_ecc_non_correctable
  11  : irq_reg0-mem_11_err_ecc_non_correctable
  12  : irq_reg0-mem_12_err_ecc_non_correctable
  13  : irq_reg0-mem_13_err_ecc_non_correctable
  14  : irq_reg0-mem_14_err_ecc_non_correctable
  15  : irq_reg0-mem_15_err_ecc_non_correctable
  16  : irq_reg0-mem_16_err_ecc_non_correctable
  17  : irq_reg0-mem_17_err_ecc_non_correctable
  18  : irq_reg0-mem_18_err_ecc_non_correctable
  19  : irq_reg0-mem_19_err_ecc_non_correctable
  20  : irq_reg0-mem_20_err_ecc_non_correctable
  21  : irq_reg0-mem_21_err_ecc_non_correctable
  22  : irq_reg0-mem_22_err_ecc_non_correctable
  23  : irq_reg0-mem_23_err_ecc_non_correctable
  24  : irq_reg0-mem_24_err_ecc_non_correctable
  25  : irq_reg0-mem_25_err_ecc_non_correctable
  26  : irq_reg0-mem_26_err_ecc_non_correctable
  27  : irq_reg0-mem_27_err_ecc_non_correctable
  28  : irq_reg0-mem_28_err_ecc_non_correctable
  29  : irq_reg0-mem_29_err_ecc_non_correctable
  30  : irq_reg0-mem_30_err_ecc_non_correctable
  31  : irq_reg0-mem_31_err_ecc_non_correctable
  32  : irq_reg1-mem_32_err_ecc_non_correctable
  33  : irq_reg1-mem_33_err_ecc_non_correctable
  34  : irq_reg1-mem_34_err_ecc_non_correctable
  35  : irq_reg1-mem_35_err_ecc_non_correctable
  36  : irq_reg1-mem_36_err_ecc_non_correctable
  37  : irq_reg1-mem_37_err_ecc_non_correctable
  38  : irq_reg1-mem_38_err_ecc_non_correctable
  39  : irq_reg1-mem_39_err_ecc_non_correctable
  40  : irq_reg1-mem_40_err_ecc_non_correctable
  41  : irq_reg1-mem_41_err_ecc_non_correctable
  42  : irq_reg1-mem_42_err_ecc_non_correctable
  43  : irq_reg1-mem_43_err_ecc_non_correctable
  44  : irq_reg1-mem_44_err_ecc_non_correctable
  45  : irq_reg1-mem_0_err_ecc_correctable
  46  : irq_reg1-mem_1_err_ecc_correctable
  47  : irq_reg1-mem_2_err_ecc_correctable
  48  : irq_reg1-mem_3_err_ecc_correctable
  49  : irq_reg1-mem_4_err_ecc_correctable
  50  : irq_reg1-mem_5_err_ecc_correctable
  51  : irq_reg1-mem_6_err_ecc_correctable
  52  : irq_reg1-mem_7_err_ecc_correctable
  53  : irq_reg1-mem_8_err_ecc_correctable
  54  : irq_reg1-mem_9_err_ecc_correctable
  55  : irq_reg1-mem_10_err_ecc_correctable
  56  : irq_reg1-mem_11_err_ecc_correctable
  57  : irq_reg1-mem_12_err_ecc_correctable
  58  : irq_reg1-mem_13_err_ecc_correctable
  59  : irq_reg1-mem_14_err_ecc_correctable
  60  : irq_reg1-mem_15_err_ecc_correctable
  61  : irq_reg1-mem_16_err_ecc_correctable
  62  : irq_reg1-mem_17_err_ecc_correctable
  63  : irq_reg1-mem_18_err_ecc_correctable
  64  : irq_reg2-mem_19_err_ecc_correctable
  65  : irq_reg2-mem_20_err_ecc_correctable
  66  : irq_reg2-mem_21_err_ecc_correctable
  67  : irq_reg2-mem_22_err_ecc_correctable
  68  : irq_reg2-mem_23_err_ecc_correctable
  69  : irq_reg2-mem_24_err_ecc_correctable
  70  : irq_reg2-mem_25_err_ecc_correctable
  71  : irq_reg2-mem_26_err_ecc_correctable
  72  : irq_reg2-mem_27_err_ecc_correctable
  73  : irq_reg2-mem_28_err_ecc_correctable
  74  : irq_reg2-mem_29_err_ecc_correctable
  75  : irq_reg2-mem_30_err_ecc_correctable
  76  : irq_reg2-mem_31_err_ecc_correctable
  77  : irq_reg2-mem_32_err_ecc_correctable
  78  : irq_reg2-mem_33_err_ecc_correctable
  79  : irq_reg2-mem_34_err_ecc_correctable
  80  : irq_reg2-mem_35_err_ecc_correctable
  81  : irq_reg2-mem_36_err_ecc_correctable
  82  : irq_reg2-mem_37_err_ecc_correctable
  83  : irq_reg2-mem_38_err_ecc_correctable
  84  : irq_reg2-mem_39_err_ecc_correctable
  85  : irq_reg2-mem_40_err_ecc_correctable
  86  : irq_reg2-mem_41_err_ecc_correctable
  87  : irq_reg2-mem_42_err_ecc_correctable
  88  : irq_reg2-mem_43_err_ecc_correctable
  89  : irq_reg2-mem_44_err_ecc_correctable
  90  : irq_reg2-mem_0_mbist_or_init_finished
  91  : irq_reg2-mem_1_mbist_or_init_finished
  92  : irq_reg2-mem_2_mbist_or_init_finished
  93  : irq_reg2-mem_3_mbist_or_init_finished
  94  : irq_reg2-mem_4_mbist_or_init_finished
  95  : irq_reg2-mem_5_mbist_or_init_finished
  96  : irq_reg3-mem_6_mbist_or_init_finished
  97  : irq_reg3-mem_7_mbist_or_init_finished
  98  : irq_reg3-mem_8_mbist_or_init_finished
  99  : irq_reg3-mem_9_mbist_or_init_finished
  100 : irq_reg3-mem_10_mbist_or_init_finished
  101 : irq_reg3-mem_11_mbist_or_init_finished
  102 : irq_reg3-mem_12_mbist_or_init_finished
  103 : irq_reg3-mem_13_mbist_or_init_finished
  104 : irq_reg3-mem_14_mbist_or_init_finished
  105 : irq_reg3-mem_15_mbist_or_init_finished
  106 : irq_reg3-mem_16_mbist_or_init_finished
  107 : irq_reg3-mem_17_mbist_or_init_finished
  108 : irq_reg3-mem_18_mbist_or_init_finished
  109 : irq_reg3-mem_19_mbist_or_init_finished
  110 : irq_reg3-mem_20_mbist_or_init_finished
  111 : irq_reg3-mem_21_mbist_or_init_finished
  112 : irq_reg3-mem_22_mbist_or_init_finished
  113 : irq_reg3-mem_23_mbist_or_init_finished
  114 : irq_reg3-mem_24_mbist_or_init_finished
  115 : irq_reg3-mem_25_mbist_or_init_finished
  116 : irq_reg3-mem_26_mbist_or_init_finished
  117 : irq_reg3-mem_27_mbist_or_init_finished
  118 : irq_reg3-mem_28_mbist_or_init_finished
  119 : irq_reg3-mem_29_mbist_or_init_finished
  120 : irq_reg3-mem_30_mbist_or_init_finished
  121 : irq_reg3-mem_31_mbist_or_init_finished
  122 : irq_reg3-mem_32_mbist_or_init_finished
  123 : irq_reg3-mem_33_mbist_or_init_finished
  124 : irq_reg3-mem_34_mbist_or_init_finished
  125 : irq_reg3-mem_35_mbist_or_init_finished
  126 : irq_reg3-mem_36_mbist_or_init_finished
  127 : irq_reg3-mem_37_mbist_or_init_finished
  128 : irq_reg4-mem_38_mbist_or_init_finished
  129 : irq_reg4-mem_39_mbist_or_init_finished
  130 : irq_reg4-mem_40_mbist_or_init_finished
  131 : irq_reg4-mem_41_mbist_or_init_finished
  132 : irq_reg4-mem_42_mbist_or_init_finished
  133 : irq_reg4-mem_43_mbist_or_init_finished
  134 : irq_reg4-mem_44_mbist_or_init_finished
  135 : irq_reg4-mem_45_mbist_or_init_finished
  136 : irq_reg4-mem_46_mbist_or_init_finished
  137 : irq_reg4-mem_47_mbist_or_init_finished
  138 : irq_reg4-mem_48_mbist_or_init_finished
  139 : irq_reg4-mem_49_mbist_or_init_finished
  140 : irq_reg4-mem_50_mbist_or_init_finished
  141 : irq_reg4-mem_51_mbist_or_init_finished
  142 : irq_reg4-mem_52_mbist_or_init_finished
  143 : no active IRQ
R/W
0x00000000
Address : 0x07d63ec4
Bits Reset value Name Description
31 "0"
mem_18_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
30 "0"
mem_17_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
29 "0"
mem_16_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
28 "0"
mem_15_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
27 "0"
mem_14_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
26 "0"
mem_13_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
25 "0"
mem_12_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_11_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_10_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_9_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_44_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
11 "0"
mem_43_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
10 "0"
mem_42_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
9 "0"
mem_41_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
8 "0"
mem_40_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_39_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_38_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_37_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_36_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_35_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_34_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_33_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_32_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg2
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 143 when no IRQ is set:
  0   : irq_reg0-mem_0_err_ecc_non_correctable
  1   : irq_reg0-mem_1_err_ecc_non_correctable
  2   : irq_reg0-mem_2_err_ecc_non_correctable
  3   : irq_reg0-mem_3_err_ecc_non_correctable
  4   : irq_reg0-mem_4_err_ecc_non_correctable
  5   : irq_reg0-mem_5_err_ecc_non_correctable
  6   : irq_reg0-mem_6_err_ecc_non_correctable
  7   : irq_reg0-mem_7_err_ecc_non_correctable
  8   : irq_reg0-mem_8_err_ecc_non_correctable
  9   : irq_reg0-mem_9_err_ecc_non_correctable
  10  : irq_reg0-mem_10_err_ecc_non_correctable
  11  : irq_reg0-mem_11_err_ecc_non_correctable
  12  : irq_reg0-mem_12_err_ecc_non_correctable
  13  : irq_reg0-mem_13_err_ecc_non_correctable
  14  : irq_reg0-mem_14_err_ecc_non_correctable
  15  : irq_reg0-mem_15_err_ecc_non_correctable
  16  : irq_reg0-mem_16_err_ecc_non_correctable
  17  : irq_reg0-mem_17_err_ecc_non_correctable
  18  : irq_reg0-mem_18_err_ecc_non_correctable
  19  : irq_reg0-mem_19_err_ecc_non_correctable
  20  : irq_reg0-mem_20_err_ecc_non_correctable
  21  : irq_reg0-mem_21_err_ecc_non_correctable
  22  : irq_reg0-mem_22_err_ecc_non_correctable
  23  : irq_reg0-mem_23_err_ecc_non_correctable
  24  : irq_reg0-mem_24_err_ecc_non_correctable
  25  : irq_reg0-mem_25_err_ecc_non_correctable
  26  : irq_reg0-mem_26_err_ecc_non_correctable
  27  : irq_reg0-mem_27_err_ecc_non_correctable
  28  : irq_reg0-mem_28_err_ecc_non_correctable
  29  : irq_reg0-mem_29_err_ecc_non_correctable
  30  : irq_reg0-mem_30_err_ecc_non_correctable
  31  : irq_reg0-mem_31_err_ecc_non_correctable
  32  : irq_reg1-mem_32_err_ecc_non_correctable
  33  : irq_reg1-mem_33_err_ecc_non_correctable
  34  : irq_reg1-mem_34_err_ecc_non_correctable
  35  : irq_reg1-mem_35_err_ecc_non_correctable
  36  : irq_reg1-mem_36_err_ecc_non_correctable
  37  : irq_reg1-mem_37_err_ecc_non_correctable
  38  : irq_reg1-mem_38_err_ecc_non_correctable
  39  : irq_reg1-mem_39_err_ecc_non_correctable
  40  : irq_reg1-mem_40_err_ecc_non_correctable
  41  : irq_reg1-mem_41_err_ecc_non_correctable
  42  : irq_reg1-mem_42_err_ecc_non_correctable
  43  : irq_reg1-mem_43_err_ecc_non_correctable
  44  : irq_reg1-mem_44_err_ecc_non_correctable
  45  : irq_reg1-mem_0_err_ecc_correctable
  46  : irq_reg1-mem_1_err_ecc_correctable
  47  : irq_reg1-mem_2_err_ecc_correctable
  48  : irq_reg1-mem_3_err_ecc_correctable
  49  : irq_reg1-mem_4_err_ecc_correctable
  50  : irq_reg1-mem_5_err_ecc_correctable
  51  : irq_reg1-mem_6_err_ecc_correctable
  52  : irq_reg1-mem_7_err_ecc_correctable
  53  : irq_reg1-mem_8_err_ecc_correctable
  54  : irq_reg1-mem_9_err_ecc_correctable
  55  : irq_reg1-mem_10_err_ecc_correctable
  56  : irq_reg1-mem_11_err_ecc_correctable
  57  : irq_reg1-mem_12_err_ecc_correctable
  58  : irq_reg1-mem_13_err_ecc_correctable
  59  : irq_reg1-mem_14_err_ecc_correctable
  60  : irq_reg1-mem_15_err_ecc_correctable
  61  : irq_reg1-mem_16_err_ecc_correctable
  62  : irq_reg1-mem_17_err_ecc_correctable
  63  : irq_reg1-mem_18_err_ecc_correctable
  64  : irq_reg2-mem_19_err_ecc_correctable
  65  : irq_reg2-mem_20_err_ecc_correctable
  66  : irq_reg2-mem_21_err_ecc_correctable
  67  : irq_reg2-mem_22_err_ecc_correctable
  68  : irq_reg2-mem_23_err_ecc_correctable
  69  : irq_reg2-mem_24_err_ecc_correctable
  70  : irq_reg2-mem_25_err_ecc_correctable
  71  : irq_reg2-mem_26_err_ecc_correctable
  72  : irq_reg2-mem_27_err_ecc_correctable
  73  : irq_reg2-mem_28_err_ecc_correctable
  74  : irq_reg2-mem_29_err_ecc_correctable
  75  : irq_reg2-mem_30_err_ecc_correctable
  76  : irq_reg2-mem_31_err_ecc_correctable
  77  : irq_reg2-mem_32_err_ecc_correctable
  78  : irq_reg2-mem_33_err_ecc_correctable
  79  : irq_reg2-mem_34_err_ecc_correctable
  80  : irq_reg2-mem_35_err_ecc_correctable
  81  : irq_reg2-mem_36_err_ecc_correctable
  82  : irq_reg2-mem_37_err_ecc_correctable
  83  : irq_reg2-mem_38_err_ecc_correctable
  84  : irq_reg2-mem_39_err_ecc_correctable
  85  : irq_reg2-mem_40_err_ecc_correctable
  86  : irq_reg2-mem_41_err_ecc_correctable
  87  : irq_reg2-mem_42_err_ecc_correctable
  88  : irq_reg2-mem_43_err_ecc_correctable
  89  : irq_reg2-mem_44_err_ecc_correctable
  90  : irq_reg2-mem_0_mbist_or_init_finished
  91  : irq_reg2-mem_1_mbist_or_init_finished
  92  : irq_reg2-mem_2_mbist_or_init_finished
  93  : irq_reg2-mem_3_mbist_or_init_finished
  94  : irq_reg2-mem_4_mbist_or_init_finished
  95  : irq_reg2-mem_5_mbist_or_init_finished
  96  : irq_reg3-mem_6_mbist_or_init_finished
  97  : irq_reg3-mem_7_mbist_or_init_finished
  98  : irq_reg3-mem_8_mbist_or_init_finished
  99  : irq_reg3-mem_9_mbist_or_init_finished
  100 : irq_reg3-mem_10_mbist_or_init_finished
  101 : irq_reg3-mem_11_mbist_or_init_finished
  102 : irq_reg3-mem_12_mbist_or_init_finished
  103 : irq_reg3-mem_13_mbist_or_init_finished
  104 : irq_reg3-mem_14_mbist_or_init_finished
  105 : irq_reg3-mem_15_mbist_or_init_finished
  106 : irq_reg3-mem_16_mbist_or_init_finished
  107 : irq_reg3-mem_17_mbist_or_init_finished
  108 : irq_reg3-mem_18_mbist_or_init_finished
  109 : irq_reg3-mem_19_mbist_or_init_finished
  110 : irq_reg3-mem_20_mbist_or_init_finished
  111 : irq_reg3-mem_21_mbist_or_init_finished
  112 : irq_reg3-mem_22_mbist_or_init_finished
  113 : irq_reg3-mem_23_mbist_or_init_finished
  114 : irq_reg3-mem_24_mbist_or_init_finished
  115 : irq_reg3-mem_25_mbist_or_init_finished
  116 : irq_reg3-mem_26_mbist_or_init_finished
  117 : irq_reg3-mem_27_mbist_or_init_finished
  118 : irq_reg3-mem_28_mbist_or_init_finished
  119 : irq_reg3-mem_29_mbist_or_init_finished
  120 : irq_reg3-mem_30_mbist_or_init_finished
  121 : irq_reg3-mem_31_mbist_or_init_finished
  122 : irq_reg3-mem_32_mbist_or_init_finished
  123 : irq_reg3-mem_33_mbist_or_init_finished
  124 : irq_reg3-mem_34_mbist_or_init_finished
  125 : irq_reg3-mem_35_mbist_or_init_finished
  126 : irq_reg3-mem_36_mbist_or_init_finished
  127 : irq_reg3-mem_37_mbist_or_init_finished
  128 : irq_reg4-mem_38_mbist_or_init_finished
  129 : irq_reg4-mem_39_mbist_or_init_finished
  130 : irq_reg4-mem_40_mbist_or_init_finished
  131 : irq_reg4-mem_41_mbist_or_init_finished
  132 : irq_reg4-mem_42_mbist_or_init_finished
  133 : irq_reg4-mem_43_mbist_or_init_finished
  134 : irq_reg4-mem_44_mbist_or_init_finished
  135 : irq_reg4-mem_45_mbist_or_init_finished
  136 : irq_reg4-mem_46_mbist_or_init_finished
  137 : irq_reg4-mem_47_mbist_or_init_finished
  138 : irq_reg4-mem_48_mbist_or_init_finished
  139 : irq_reg4-mem_49_mbist_or_init_finished
  140 : irq_reg4-mem_50_mbist_or_init_finished
  141 : irq_reg4-mem_51_mbist_or_init_finished
  142 : irq_reg4-mem_52_mbist_or_init_finished
  143 : no active IRQ
R/W
0x00000000
Address : 0x07d63ec8
Bits Reset value Name Description
31 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_44_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
24 "0"
mem_43_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
23 "0"
mem_42_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
22 "0"
mem_41_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
21 "0"
mem_40_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
20 "0"
mem_39_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
19 "0"
mem_38_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
18 "0"
mem_37_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
17 "0"
mem_36_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_35_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_34_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_33_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_32_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_31_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_30_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_29_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_28_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_27_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_26_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
6 "0"
mem_25_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
5 "0"
mem_24_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
4 "0"
mem_23_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
3 "0"
mem_22_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_21_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_20_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_19_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error


gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg3
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 143 when no IRQ is set:
  0   : irq_reg0-mem_0_err_ecc_non_correctable
  1   : irq_reg0-mem_1_err_ecc_non_correctable
  2   : irq_reg0-mem_2_err_ecc_non_correctable
  3   : irq_reg0-mem_3_err_ecc_non_correctable
  4   : irq_reg0-mem_4_err_ecc_non_correctable
  5   : irq_reg0-mem_5_err_ecc_non_correctable
  6   : irq_reg0-mem_6_err_ecc_non_correctable
  7   : irq_reg0-mem_7_err_ecc_non_correctable
  8   : irq_reg0-mem_8_err_ecc_non_correctable
  9   : irq_reg0-mem_9_err_ecc_non_correctable
  10  : irq_reg0-mem_10_err_ecc_non_correctable
  11  : irq_reg0-mem_11_err_ecc_non_correctable
  12  : irq_reg0-mem_12_err_ecc_non_correctable
  13  : irq_reg0-mem_13_err_ecc_non_correctable
  14  : irq_reg0-mem_14_err_ecc_non_correctable
  15  : irq_reg0-mem_15_err_ecc_non_correctable
  16  : irq_reg0-mem_16_err_ecc_non_correctable
  17  : irq_reg0-mem_17_err_ecc_non_correctable
  18  : irq_reg0-mem_18_err_ecc_non_correctable
  19  : irq_reg0-mem_19_err_ecc_non_correctable
  20  : irq_reg0-mem_20_err_ecc_non_correctable
  21  : irq_reg0-mem_21_err_ecc_non_correctable
  22  : irq_reg0-mem_22_err_ecc_non_correctable
  23  : irq_reg0-mem_23_err_ecc_non_correctable
  24  : irq_reg0-mem_24_err_ecc_non_correctable
  25  : irq_reg0-mem_25_err_ecc_non_correctable
  26  : irq_reg0-mem_26_err_ecc_non_correctable
  27  : irq_reg0-mem_27_err_ecc_non_correctable
  28  : irq_reg0-mem_28_err_ecc_non_correctable
  29  : irq_reg0-mem_29_err_ecc_non_correctable
  30  : irq_reg0-mem_30_err_ecc_non_correctable
  31  : irq_reg0-mem_31_err_ecc_non_correctable
  32  : irq_reg1-mem_32_err_ecc_non_correctable
  33  : irq_reg1-mem_33_err_ecc_non_correctable
  34  : irq_reg1-mem_34_err_ecc_non_correctable
  35  : irq_reg1-mem_35_err_ecc_non_correctable
  36  : irq_reg1-mem_36_err_ecc_non_correctable
  37  : irq_reg1-mem_37_err_ecc_non_correctable
  38  : irq_reg1-mem_38_err_ecc_non_correctable
  39  : irq_reg1-mem_39_err_ecc_non_correctable
  40  : irq_reg1-mem_40_err_ecc_non_correctable
  41  : irq_reg1-mem_41_err_ecc_non_correctable
  42  : irq_reg1-mem_42_err_ecc_non_correctable
  43  : irq_reg1-mem_43_err_ecc_non_correctable
  44  : irq_reg1-mem_44_err_ecc_non_correctable
  45  : irq_reg1-mem_0_err_ecc_correctable
  46  : irq_reg1-mem_1_err_ecc_correctable
  47  : irq_reg1-mem_2_err_ecc_correctable
  48  : irq_reg1-mem_3_err_ecc_correctable
  49  : irq_reg1-mem_4_err_ecc_correctable
  50  : irq_reg1-mem_5_err_ecc_correctable
  51  : irq_reg1-mem_6_err_ecc_correctable
  52  : irq_reg1-mem_7_err_ecc_correctable
  53  : irq_reg1-mem_8_err_ecc_correctable
  54  : irq_reg1-mem_9_err_ecc_correctable
  55  : irq_reg1-mem_10_err_ecc_correctable
  56  : irq_reg1-mem_11_err_ecc_correctable
  57  : irq_reg1-mem_12_err_ecc_correctable
  58  : irq_reg1-mem_13_err_ecc_correctable
  59  : irq_reg1-mem_14_err_ecc_correctable
  60  : irq_reg1-mem_15_err_ecc_correctable
  61  : irq_reg1-mem_16_err_ecc_correctable
  62  : irq_reg1-mem_17_err_ecc_correctable
  63  : irq_reg1-mem_18_err_ecc_correctable
  64  : irq_reg2-mem_19_err_ecc_correctable
  65  : irq_reg2-mem_20_err_ecc_correctable
  66  : irq_reg2-mem_21_err_ecc_correctable
  67  : irq_reg2-mem_22_err_ecc_correctable
  68  : irq_reg2-mem_23_err_ecc_correctable
  69  : irq_reg2-mem_24_err_ecc_correctable
  70  : irq_reg2-mem_25_err_ecc_correctable
  71  : irq_reg2-mem_26_err_ecc_correctable
  72  : irq_reg2-mem_27_err_ecc_correctable
  73  : irq_reg2-mem_28_err_ecc_correctable
  74  : irq_reg2-mem_29_err_ecc_correctable
  75  : irq_reg2-mem_30_err_ecc_correctable
  76  : irq_reg2-mem_31_err_ecc_correctable
  77  : irq_reg2-mem_32_err_ecc_correctable
  78  : irq_reg2-mem_33_err_ecc_correctable
  79  : irq_reg2-mem_34_err_ecc_correctable
  80  : irq_reg2-mem_35_err_ecc_correctable
  81  : irq_reg2-mem_36_err_ecc_correctable
  82  : irq_reg2-mem_37_err_ecc_correctable
  83  : irq_reg2-mem_38_err_ecc_correctable
  84  : irq_reg2-mem_39_err_ecc_correctable
  85  : irq_reg2-mem_40_err_ecc_correctable
  86  : irq_reg2-mem_41_err_ecc_correctable
  87  : irq_reg2-mem_42_err_ecc_correctable
  88  : irq_reg2-mem_43_err_ecc_correctable
  89  : irq_reg2-mem_44_err_ecc_correctable
  90  : irq_reg2-mem_0_mbist_or_init_finished
  91  : irq_reg2-mem_1_mbist_or_init_finished
  92  : irq_reg2-mem_2_mbist_or_init_finished
  93  : irq_reg2-mem_3_mbist_or_init_finished
  94  : irq_reg2-mem_4_mbist_or_init_finished
  95  : irq_reg2-mem_5_mbist_or_init_finished
  96  : irq_reg3-mem_6_mbist_or_init_finished
  97  : irq_reg3-mem_7_mbist_or_init_finished
  98  : irq_reg3-mem_8_mbist_or_init_finished
  99  : irq_reg3-mem_9_mbist_or_init_finished
  100 : irq_reg3-mem_10_mbist_or_init_finished
  101 : irq_reg3-mem_11_mbist_or_init_finished
  102 : irq_reg3-mem_12_mbist_or_init_finished
  103 : irq_reg3-mem_13_mbist_or_init_finished
  104 : irq_reg3-mem_14_mbist_or_init_finished
  105 : irq_reg3-mem_15_mbist_or_init_finished
  106 : irq_reg3-mem_16_mbist_or_init_finished
  107 : irq_reg3-mem_17_mbist_or_init_finished
  108 : irq_reg3-mem_18_mbist_or_init_finished
  109 : irq_reg3-mem_19_mbist_or_init_finished
  110 : irq_reg3-mem_20_mbist_or_init_finished
  111 : irq_reg3-mem_21_mbist_or_init_finished
  112 : irq_reg3-mem_22_mbist_or_init_finished
  113 : irq_reg3-mem_23_mbist_or_init_finished
  114 : irq_reg3-mem_24_mbist_or_init_finished
  115 : irq_reg3-mem_25_mbist_or_init_finished
  116 : irq_reg3-mem_26_mbist_or_init_finished
  117 : irq_reg3-mem_27_mbist_or_init_finished
  118 : irq_reg3-mem_28_mbist_or_init_finished
  119 : irq_reg3-mem_29_mbist_or_init_finished
  120 : irq_reg3-mem_30_mbist_or_init_finished
  121 : irq_reg3-mem_31_mbist_or_init_finished
  122 : irq_reg3-mem_32_mbist_or_init_finished
  123 : irq_reg3-mem_33_mbist_or_init_finished
  124 : irq_reg3-mem_34_mbist_or_init_finished
  125 : irq_reg3-mem_35_mbist_or_init_finished
  126 : irq_reg3-mem_36_mbist_or_init_finished
  127 : irq_reg3-mem_37_mbist_or_init_finished
  128 : irq_reg4-mem_38_mbist_or_init_finished
  129 : irq_reg4-mem_39_mbist_or_init_finished
  130 : irq_reg4-mem_40_mbist_or_init_finished
  131 : irq_reg4-mem_41_mbist_or_init_finished
  132 : irq_reg4-mem_42_mbist_or_init_finished
  133 : irq_reg4-mem_43_mbist_or_init_finished
  134 : irq_reg4-mem_44_mbist_or_init_finished
  135 : irq_reg4-mem_45_mbist_or_init_finished
  136 : irq_reg4-mem_46_mbist_or_init_finished
  137 : irq_reg4-mem_47_mbist_or_init_finished
  138 : irq_reg4-mem_48_mbist_or_init_finished
  139 : irq_reg4-mem_49_mbist_or_init_finished
  140 : irq_reg4-mem_50_mbist_or_init_finished
  141 : irq_reg4-mem_51_mbist_or_init_finished
  142 : irq_reg4-mem_52_mbist_or_init_finished
  143 : no active IRQ
R/W
0x00000000
Address : 0x07d63ecc
Bits Reset value Name Description
31 "0"
mem_37_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
30 "0"
mem_36_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
29 "0"
mem_35_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
28 "0"
mem_34_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
27 "0"
mem_33_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
26 "0"
mem_32_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_31_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_30_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_29_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_28_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_27_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_26_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_25_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_24_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_23_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_22_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_21_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
14 "0"
mem_20_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_19_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_18_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_17_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_16_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_15_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_14_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_13_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_12_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_11_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_10_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_9_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_irq_mask_rst_reg4
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 143 when no IRQ is set:
  0   : irq_reg0-mem_0_err_ecc_non_correctable
  1   : irq_reg0-mem_1_err_ecc_non_correctable
  2   : irq_reg0-mem_2_err_ecc_non_correctable
  3   : irq_reg0-mem_3_err_ecc_non_correctable
  4   : irq_reg0-mem_4_err_ecc_non_correctable
  5   : irq_reg0-mem_5_err_ecc_non_correctable
  6   : irq_reg0-mem_6_err_ecc_non_correctable
  7   : irq_reg0-mem_7_err_ecc_non_correctable
  8   : irq_reg0-mem_8_err_ecc_non_correctable
  9   : irq_reg0-mem_9_err_ecc_non_correctable
  10  : irq_reg0-mem_10_err_ecc_non_correctable
  11  : irq_reg0-mem_11_err_ecc_non_correctable
  12  : irq_reg0-mem_12_err_ecc_non_correctable
  13  : irq_reg0-mem_13_err_ecc_non_correctable
  14  : irq_reg0-mem_14_err_ecc_non_correctable
  15  : irq_reg0-mem_15_err_ecc_non_correctable
  16  : irq_reg0-mem_16_err_ecc_non_correctable
  17  : irq_reg0-mem_17_err_ecc_non_correctable
  18  : irq_reg0-mem_18_err_ecc_non_correctable
  19  : irq_reg0-mem_19_err_ecc_non_correctable
  20  : irq_reg0-mem_20_err_ecc_non_correctable
  21  : irq_reg0-mem_21_err_ecc_non_correctable
  22  : irq_reg0-mem_22_err_ecc_non_correctable
  23  : irq_reg0-mem_23_err_ecc_non_correctable
  24  : irq_reg0-mem_24_err_ecc_non_correctable
  25  : irq_reg0-mem_25_err_ecc_non_correctable
  26  : irq_reg0-mem_26_err_ecc_non_correctable
  27  : irq_reg0-mem_27_err_ecc_non_correctable
  28  : irq_reg0-mem_28_err_ecc_non_correctable
  29  : irq_reg0-mem_29_err_ecc_non_correctable
  30  : irq_reg0-mem_30_err_ecc_non_correctable
  31  : irq_reg0-mem_31_err_ecc_non_correctable
  32  : irq_reg1-mem_32_err_ecc_non_correctable
  33  : irq_reg1-mem_33_err_ecc_non_correctable
  34  : irq_reg1-mem_34_err_ecc_non_correctable
  35  : irq_reg1-mem_35_err_ecc_non_correctable
  36  : irq_reg1-mem_36_err_ecc_non_correctable
  37  : irq_reg1-mem_37_err_ecc_non_correctable
  38  : irq_reg1-mem_38_err_ecc_non_correctable
  39  : irq_reg1-mem_39_err_ecc_non_correctable
  40  : irq_reg1-mem_40_err_ecc_non_correctable
  41  : irq_reg1-mem_41_err_ecc_non_correctable
  42  : irq_reg1-mem_42_err_ecc_non_correctable
  43  : irq_reg1-mem_43_err_ecc_non_correctable
  44  : irq_reg1-mem_44_err_ecc_non_correctable
  45  : irq_reg1-mem_0_err_ecc_correctable
  46  : irq_reg1-mem_1_err_ecc_correctable
  47  : irq_reg1-mem_2_err_ecc_correctable
  48  : irq_reg1-mem_3_err_ecc_correctable
  49  : irq_reg1-mem_4_err_ecc_correctable
  50  : irq_reg1-mem_5_err_ecc_correctable
  51  : irq_reg1-mem_6_err_ecc_correctable
  52  : irq_reg1-mem_7_err_ecc_correctable
  53  : irq_reg1-mem_8_err_ecc_correctable
  54  : irq_reg1-mem_9_err_ecc_correctable
  55  : irq_reg1-mem_10_err_ecc_correctable
  56  : irq_reg1-mem_11_err_ecc_correctable
  57  : irq_reg1-mem_12_err_ecc_correctable
  58  : irq_reg1-mem_13_err_ecc_correctable
  59  : irq_reg1-mem_14_err_ecc_correctable
  60  : irq_reg1-mem_15_err_ecc_correctable
  61  : irq_reg1-mem_16_err_ecc_correctable
  62  : irq_reg1-mem_17_err_ecc_correctable
  63  : irq_reg1-mem_18_err_ecc_correctable
  64  : irq_reg2-mem_19_err_ecc_correctable
  65  : irq_reg2-mem_20_err_ecc_correctable
  66  : irq_reg2-mem_21_err_ecc_correctable
  67  : irq_reg2-mem_22_err_ecc_correctable
  68  : irq_reg2-mem_23_err_ecc_correctable
  69  : irq_reg2-mem_24_err_ecc_correctable
  70  : irq_reg2-mem_25_err_ecc_correctable
  71  : irq_reg2-mem_26_err_ecc_correctable
  72  : irq_reg2-mem_27_err_ecc_correctable
  73  : irq_reg2-mem_28_err_ecc_correctable
  74  : irq_reg2-mem_29_err_ecc_correctable
  75  : irq_reg2-mem_30_err_ecc_correctable
  76  : irq_reg2-mem_31_err_ecc_correctable
  77  : irq_reg2-mem_32_err_ecc_correctable
  78  : irq_reg2-mem_33_err_ecc_correctable
  79  : irq_reg2-mem_34_err_ecc_correctable
  80  : irq_reg2-mem_35_err_ecc_correctable
  81  : irq_reg2-mem_36_err_ecc_correctable
  82  : irq_reg2-mem_37_err_ecc_correctable
  83  : irq_reg2-mem_38_err_ecc_correctable
  84  : irq_reg2-mem_39_err_ecc_correctable
  85  : irq_reg2-mem_40_err_ecc_correctable
  86  : irq_reg2-mem_41_err_ecc_correctable
  87  : irq_reg2-mem_42_err_ecc_correctable
  88  : irq_reg2-mem_43_err_ecc_correctable
  89  : irq_reg2-mem_44_err_ecc_correctable
  90  : irq_reg2-mem_0_mbist_or_init_finished
  91  : irq_reg2-mem_1_mbist_or_init_finished
  92  : irq_reg2-mem_2_mbist_or_init_finished
  93  : irq_reg2-mem_3_mbist_or_init_finished
  94  : irq_reg2-mem_4_mbist_or_init_finished
  95  : irq_reg2-mem_5_mbist_or_init_finished
  96  : irq_reg3-mem_6_mbist_or_init_finished
  97  : irq_reg3-mem_7_mbist_or_init_finished
  98  : irq_reg3-mem_8_mbist_or_init_finished
  99  : irq_reg3-mem_9_mbist_or_init_finished
  100 : irq_reg3-mem_10_mbist_or_init_finished
  101 : irq_reg3-mem_11_mbist_or_init_finished
  102 : irq_reg3-mem_12_mbist_or_init_finished
  103 : irq_reg3-mem_13_mbist_or_init_finished
  104 : irq_reg3-mem_14_mbist_or_init_finished
  105 : irq_reg3-mem_15_mbist_or_init_finished
  106 : irq_reg3-mem_16_mbist_or_init_finished
  107 : irq_reg3-mem_17_mbist_or_init_finished
  108 : irq_reg3-mem_18_mbist_or_init_finished
  109 : irq_reg3-mem_19_mbist_or_init_finished
  110 : irq_reg3-mem_20_mbist_or_init_finished
  111 : irq_reg3-mem_21_mbist_or_init_finished
  112 : irq_reg3-mem_22_mbist_or_init_finished
  113 : irq_reg3-mem_23_mbist_or_init_finished
  114 : irq_reg3-mem_24_mbist_or_init_finished
  115 : irq_reg3-mem_25_mbist_or_init_finished
  116 : irq_reg3-mem_26_mbist_or_init_finished
  117 : irq_reg3-mem_27_mbist_or_init_finished
  118 : irq_reg3-mem_28_mbist_or_init_finished
  119 : irq_reg3-mem_29_mbist_or_init_finished
  120 : irq_reg3-mem_30_mbist_or_init_finished
  121 : irq_reg3-mem_31_mbist_or_init_finished
  122 : irq_reg3-mem_32_mbist_or_init_finished
  123 : irq_reg3-mem_33_mbist_or_init_finished
  124 : irq_reg3-mem_34_mbist_or_init_finished
  125 : irq_reg3-mem_35_mbist_or_init_finished
  126 : irq_reg3-mem_36_mbist_or_init_finished
  127 : irq_reg3-mem_37_mbist_or_init_finished
  128 : irq_reg4-mem_38_mbist_or_init_finished
  129 : irq_reg4-mem_39_mbist_or_init_finished
  130 : irq_reg4-mem_40_mbist_or_init_finished
  131 : irq_reg4-mem_41_mbist_or_init_finished
  132 : irq_reg4-mem_42_mbist_or_init_finished
  133 : irq_reg4-mem_43_mbist_or_init_finished
  134 : irq_reg4-mem_44_mbist_or_init_finished
  135 : irq_reg4-mem_45_mbist_or_init_finished
  136 : irq_reg4-mem_46_mbist_or_init_finished
  137 : irq_reg4-mem_47_mbist_or_init_finished
  138 : irq_reg4-mem_48_mbist_or_init_finished
  139 : irq_reg4-mem_49_mbist_or_init_finished
  140 : irq_reg4-mem_50_mbist_or_init_finished
  141 : irq_reg4-mem_51_mbist_or_init_finished
  142 : irq_reg4-mem_52_mbist_or_init_finished
  143 : no active IRQ
R/W
0x00000000
Address : 0x07d63ed0
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
mem_52_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
13 "0"
mem_51_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
12 "0"
mem_50_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
11 "0"
mem_49_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
10 "0"
mem_48_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
9 "0"
mem_47_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
8 "0"
mem_46_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
7 "0"
mem_45_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
6 "0"
mem_44_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
5 "0"
mem_43_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_42_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_41_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_40_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_39_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
0 "0"
mem_38_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization


gen_ram_ctrl_gxc_sys_0_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x07d63efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: gxc_esc_unit

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ethercat_reg0
1 4 R/W ethercat_reg1
2 8 R/W ethercat_reg2
3 c R/W ethercat_reg3
4 10 R/W ethercat_reg4
5 14 R/W ethercat_reg5
6 18 R/W ethercat_reg6
7 1c R/W ethercat_reg7
8 20 R/W ethercat_reg8
9 24 R/W ethercat_reg9
a 28 R/W ethercat_reg10
b 2c R/W ethercat_reg11
c 30 R/W ethercat_reg12
d 34 R/W ethercat_reg13
e 38 R/W ethercat_reg14
f 3c R/W ethercat_reg15
10 40 R/W ethercat_reg16
11 44 R/W ethercat_reg17
12 48 R/W ethercat_reg18
13 4c R/W ethercat_reg19
14 50 R/W ethercat_reg20
15 54 R/W ethercat_reg21
16 58 R/W ethercat_reg22
17 5c R/W ethercat_reg23
18 60 R/W ethercat_reg24
19 64 R/W ethercat_reg25
1a 68 R/W ethercat_reg26
1b 6c R/W ethercat_reg27
1c 70 R/W ethercat_reg28
1d 74 R/W ethercat_reg29
1e 78 R/W ethercat_reg30
1f 7c R/W ethercat_reg31
20 80 R/W ethercat_reg32
21 84 R/W ethercat_reg33
22 88 R/W ethercat_reg34
23 8c R/W ethercat_reg35
24 90 R/W ethercat_reg36
25 94 R/W ethercat_reg37
26 98 R/W ethercat_reg38
27 9c R/W ethercat_reg39
28 a0 R/W ethercat_reg40
29 a4 R/W ethercat_reg41
2a a8 R/W ethercat_reg42
2b ac R/W ethercat_reg43
2c b0 R/W ethercat_reg44
2d b4 R/W ethercat_reg45
2e b8 R/W ethercat_reg46
2f bc R/W ethercat_reg47
30 c0 R/W ethercat_reg48
31 c4 R/W ethercat_reg49
32 c8 R/W ethercat_reg50
33 cc R/W ethercat_reg51
34 d0 R/W ethercat_reg52
35 d4 R/W ethercat_reg53
36 d8 R/W ethercat_reg54
37 dc R/W ethercat_reg55
38 e0 R/W ethercat_reg56
39 e4 R/W ethercat_reg57
3a e8 R/W ethercat_reg58
3b ec R/W ethercat_reg59
3c f0 R/W ethercat_reg60
3d f4 R/W ethercat_reg61
3e f8 R/W ethercat_reg62
3f fc R/W ethercat_reg63
40 100 R/W ethercat_reg64
41 104 R/W ethercat_reg65
42 108 R/W ethercat_reg66
43 10c R/W ethercat_reg67
44 110 R/W ethercat_reg68
45 114 R/W ethercat_reg69
46 118 R/W ethercat_reg70
47 11c R/W ethercat_reg71
48 120 R/W ethercat_reg72
49 124 R/W ethercat_reg73
4a 128 R/W ethercat_reg74
4b 12c R/W ethercat_reg75
4c 130 R/W ethercat_reg76
4d 134 R/W ethercat_reg77
4e 138 R/W ethercat_reg78
4f 13c R/W ethercat_reg79
50 140 R/W ethercat_reg80
51 144 R/W ethercat_reg81
52 148 R/W ethercat_reg82
53 14c R/W ethercat_reg83
54 150 R/W ethercat_reg84
55 154 R/W ethercat_reg85
56 158 R/W ethercat_reg86
57 15c R/W ethercat_reg87
58 160 R/W ethercat_reg88
59 164 R/W ethercat_reg89
5a 168 R/W ethercat_reg90
5b 16c R/W ethercat_reg91
5c 170 R/W ethercat_reg92
5d 174 R/W ethercat_reg93
5e 178 R/W ethercat_reg94
5f 17c R/W ethercat_reg95
60 180 R/W ethercat_reg96
61 184 R/W ethercat_reg97
62 188 R/W ethercat_reg98
63 18c R/W ethercat_reg99
64 190 R/W ethercat_reg100
65 194 R/W ethercat_reg101
66 198 R/W ethercat_reg102
67 19c R/W ethercat_reg103
68 1a0 R/W ethercat_reg104
69 1a4 R/W ethercat_reg105
6a 1a8 R/W ethercat_reg106
6b 1ac R/W ethercat_reg107
6c 1b0 R/W ethercat_reg108
6d 1b4 R/W ethercat_reg109
6e 1b8 R/W ethercat_reg110
6f 1bc R/W ethercat_reg111
70 1c0 R/W ethercat_reg112
71 1c4 R/W ethercat_reg113
72 1c8 R/W ethercat_reg114
73 1cc R/W ethercat_reg115
74 1d0 R/W ethercat_reg116
75 1d4 R/W ethercat_reg117
76 1d8 R/W ethercat_reg118
77 1dc R/W ethercat_reg119
78 1e0 R/W ethercat_reg120
79 1e4 R/W ethercat_reg121
7a 1e8 R/W ethercat_reg122
7b 1ec R/W ethercat_reg123
7c 1f0 R/W ethercat_reg124
7d 1f4 R/W ethercat_reg125
7e 1f8 R/W ethercat_reg126
7f 1fc R/W ethercat_reg127
80 200 R ethercat_shadow_reg0
81 204 R ethercat_shadow_reg1
82 208 R ethercat_shadow_reg2
83 20c R ethercat_shadow_reg3
84 210 R ethercat_shadow_reg4
85 214 R ethercat_shadow_reg5
86 218 R ethercat_shadow_reg6
87 21c R ethercat_shadow_reg7
88 220 R/W ethercat_shadow_reg8
89 224 R/W ethercat_shadow_reg9
8a 228 R/W ethercat_shadow_reg10
8b 22c R/W ethercat_shadow_reg11
8c 230 R/W ethercat_shadow_reg12
8d 234 R/W ethercat_shadow_reg13
8e 238 R/W ethercat_shadow_reg14
8f 23c R/W ethercat_shadow_reg15
90 240 R/W ethercat_shadow_reg16
91 244 R/W ethercat_shadow_reg17
92 248 R/W ethercat_shadow_reg18
93 24c R/W ethercat_shadow_reg19
94 250 R/W ethercat_shadow_reg20
95 254 R/W ethercat_shadow_reg21
96 258 R/W ethercat_shadow_reg22
97 25c R/W ethercat_shadow_reg23
98 260 R/W ethercat_shadow_reg24
99 264 R/W ethercat_shadow_reg25
9a 268 R/W ethercat_shadow_reg26
9b 26c R/W ethercat_shadow_reg27
9c 270 R/W ethercat_shadow_reg28
9d 274 R/W ethercat_shadow_reg29
9e 278 R/W ethercat_shadow_reg30
9f 27c R/W ethercat_shadow_reg31
a0 280 R/W ethercat_shadow_reg32
a1 284 R/W ethercat_shadow_reg33
a2 288 R/W ethercat_shadow_reg34
a3 28c R/W ethercat_shadow_reg35
a4 290 R/W ethercat_shadow_reg36
a5 294 R/W ethercat_shadow_reg37
a6 298 R/W ethercat_shadow_reg38
a7 29c R/W ethercat_shadow_reg39
a8 2a0 R/W ethercat_shadow_reg40
a9 2a4 R/W ethercat_shadow_reg41
aa 2a8 R/W ethercat_shadow_reg42
ab 2ac R/W ethercat_shadow_reg43
ac 2b0 R/W ethercat_shadow_reg44
ad 2b4 R/W ethercat_shadow_reg45
ae 2b8 R/W ethercat_shadow_reg46
af 2bc R/W ethercat_shadow_reg47
b0 2c0 R/W ethercat_shadow_reg48
b1 2c4 R/W ethercat_shadow_reg49
b2 2c8 R/W ethercat_shadow_reg50
b3 2cc R/W ethercat_shadow_reg51
b4 2d0 R/W ethercat_shadow_reg52
b5 2d4 R/W ethercat_shadow_reg53
b6 2d8 R/W ethercat_shadow_reg54
b7 2dc R/W ethercat_shadow_reg55
b8 2e0 R/W ethercat_shadow_reg56
b9 2e4 R/W ethercat_shadow_reg57
ba 2e8 R/W ethercat_shadow_reg58
bb 2ec R/W ethercat_shadow_reg59
bc 2f0 R/W ethercat_shadow_reg60
bd 2f4 R/W ethercat_shadow_reg61
be 2f8 R/W ethercat_shadow_reg62
bf 2fc R/W ethercat_shadow_reg63
c0 300 R/W ethercat_shadow_reg64
c1 304 R/W ethercat_shadow_reg65
c2 308 R/W ethercat_shadow_reg66
c3 30c R/W ethercat_shadow_reg67
c4 310 R/W ethercat_shadow_reg68
c5 314 R/W ethercat_shadow_reg69
c6 318 R/W ethercat_shadow_reg70
c7 31c R/W ethercat_shadow_reg71
c8 320 R/W ethercat_shadow_reg72
c9 324 R/W ethercat_shadow_reg73
ca 328 R/W ethercat_shadow_reg74
cb 32c R/W ethercat_shadow_reg75
cc 330 R/W ethercat_shadow_reg76
cd 334 R/W ethercat_shadow_reg77
ce 338 R/W ethercat_shadow_reg78
cf 33c R/W ethercat_shadow_reg79
d0 340 R/W ethercat_shadow_reg80
d1 344 R/W ethercat_shadow_reg81
d2 348 R/W ethercat_shadow_reg82
d3 34c R/W ethercat_shadow_reg83
d4 350 R/W ethercat_shadow_reg84
d5 354 R/W ethercat_shadow_reg85
d6 358 R/W ethercat_shadow_reg86
d7 35c R/W ethercat_shadow_reg87
d8 360 R/W ethercat_shadow_reg88
d9 364 R/W ethercat_shadow_reg89
da 368 R/W ethercat_shadow_reg90
db 36c R/W ethercat_shadow_reg91
dc 370 R/W ethercat_shadow_reg92
dd 374 R/W ethercat_shadow_reg93
de 378 R/W ethercat_shadow_reg94
df 37c R/W ethercat_shadow_reg95
e0 380 R/W ethercat_shadow_reg96
e1 384 R/W ethercat_shadow_reg97
e2 388 R/W ethercat_shadow_reg98
e3 38c R/W ethercat_shadow_reg99
e4 390 R/W ethercat_shadow_reg100
e5 394 R/W ethercat_shadow_reg101
e6 398 R/W ethercat_shadow_reg102
e7 39c R/W ethercat_shadow_reg103
e8 3a0 R/W ethercat_shadow_reg104
e9 3a4 R/W ethercat_shadow_reg105
ea 3a8 R/W ethercat_shadow_reg106
eb 3ac R/W ethercat_shadow_reg107
ec 3b0 R/W ethercat_shadow_reg108
ed 3b4 R/W ethercat_shadow_reg109
ee 3b8 R/W ethercat_shadow_reg110
ef 3bc R/W ethercat_shadow_reg111
f0 3c0 R/W ethercat_shadow_reg112
f1 3c4 R/W ethercat_shadow_reg113
f2 3c8 R/W ethercat_shadow_reg114
f3 3cc R/W ethercat_shadow_reg115
f4 3d0 R/W ethercat_shadow_reg116
f5 3d4 R/W ethercat_shadow_reg117
f6 3d8 R/W ethercat_shadow_reg118
f7 3dc R/W ethercat_shadow_reg119
f8 3e0 R/W ethercat_shadow_reg120
f9 3e4 R/W ethercat_shadow_reg121
fa 3e8 R/W ethercat_shadow_reg122
fb 3ec R/W ethercat_shadow_reg123
fc 3f0 R/W ethercat_shadow_reg124
fd 3f4 R/W ethercat_shadow_reg125
fe 3f8 R/W ethercat_shadow_reg126
ff 3fc R/W ethercat_shadow_reg127
100 400 R/W ethercat_shadow_reg128
101 404 R/W ethercat_shadow_reg129
102 408 R/W ethercat_shadow_reg130
103 40c R/W ethercat_shadow_reg131
104 410 R/W ethercat_shadow_reg132
105 414 R/W ethercat_shadow_reg133
106 418 R/W ethercat_shadow_reg134
107 41c R/W ethercat_shadow_reg135
108 420 R/W ethercat_shadow_reg136
109 424 R/W ethercat_shadow_reg137
10a 428 R/W ethercat_shadow_reg138
10b 42c R/W ethercat_shadow_reg139
10c 430 R/W ethercat_shadow_reg140
10d 434 R/W ethercat_shadow_reg141
10e 438 R/W ethercat_shadow_reg142
10f 43c R/W ethercat_shadow_reg143
110 440 R/W ethercat_shadow_reg144
111 444 R/W ethercat_shadow_reg145
112 448 R/W ethercat_shadow_reg146
113 44c R/W ethercat_shadow_reg147
114 450 R/W ethercat_shadow_reg148
115 454 R/W ethercat_shadow_reg149
116 458 R/W ethercat_shadow_reg150
117 45c R/W ethercat_shadow_reg151
118 460 R/W ethercat_shadow_reg152
119 464 R/W ethercat_shadow_reg153
11a 468 R/W ethercat_shadow_reg154
11b 46c R/W ethercat_shadow_reg155
11c 470 R/W ethercat_shadow_reg156
11d 474 R/W ethercat_shadow_reg157
11e 478 R/W ethercat_shadow_reg158
11f 47c R/W ethercat_shadow_reg159
120 480 R/W ethercat_shadow_reg160
121 484 R/W ethercat_shadow_reg161
122 488 R/W ethercat_shadow_reg162
123 48c R/W ethercat_shadow_reg163
124 490 R/W ethercat_shadow_reg164
125 494 R/W ethercat_shadow_reg165
126 498 R/W ethercat_shadow_reg166
127 49c R/W ethercat_shadow_reg167
128 4a0 R/W ethercat_shadow_reg168
129 4a4 R/W ethercat_shadow_reg169
12a 4a8 R/W ethercat_shadow_reg170
12b 4ac R/W ethercat_shadow_reg171
12c 4b0 R/W ethercat_shadow_reg172
12d 4b4 R/W ethercat_shadow_reg173
12e 4b8 R/W ethercat_shadow_reg174
12f 4bc R/W ethercat_shadow_reg175
130 4c0 R/W ethercat_shadow_reg176
131 4c4 R/W ethercat_shadow_reg177
132 4c8 R/W ethercat_shadow_reg178
133 4cc R/W ethercat_shadow_reg179
134 4d0 R/W ethercat_shadow_reg180
135 4d4 R/W ethercat_shadow_reg181
136 4d8 R/W ethercat_shadow_reg182
137 4dc R/W ethercat_shadow_reg183
138 4e0 R/W ethercat_shadow_reg184
139 4e4 R/W ethercat_shadow_reg185
13a 4e8 R/W ethercat_shadow_reg186
13b 4ec R/W ethercat_shadow_reg187
13c 4f0 R/W ethercat_shadow_reg188
13d 4f4 R/W ethercat_shadow_reg189
13e 4f8 R/W ethercat_shadow_reg190
13f 4fc R/W ethercat_shadow_reg191
140 500 R/W ethercat_shadow_reg192
141 504 R/W ethercat_shadow_reg193
142 508 R/W ethercat_shadow_reg194
143 50c R/W ethercat_shadow_reg195
144 510 R/W ethercat_shadow_reg196
145 514 R/W ethercat_shadow_reg197
146 518 R/W ethercat_shadow_reg198
147 51c R/W ethercat_shadow_reg199
148 520 R/W ethercat_shadow_reg200
149 524 R/W ethercat_shadow_reg201
14a 528 R/W ethercat_shadow_reg202
14b 52c R/W ethercat_shadow_reg203
14c 530 R/W ethercat_shadow_reg204
14d 534 R/W ethercat_shadow_reg205
14e 538 R/W ethercat_shadow_reg206
14f 53c R/W ethercat_shadow_reg207
150 540 R/W ethercat_shadow_reg208
151 544 R/W ethercat_shadow_reg209
152 548 R/W ethercat_shadow_reg210
153 54c R/W ethercat_shadow_reg211
154 550 R/W ethercat_shadow_reg212
155 554 R/W ethercat_shadow_reg213
156 558 R/W ethercat_shadow_reg214
157 55c R/W ethercat_shadow_reg215
158 560 R/W ethercat_shadow_reg216
159 564 R/W ethercat_shadow_reg217
15a 568 R/W ethercat_shadow_reg218
15b 56c R/W ethercat_shadow_reg219
15c 570 R/W ethercat_shadow_reg220
15d 574 R/W ethercat_shadow_reg221
15e 578 R/W ethercat_shadow_reg222
15f 57c R/W ethercat_shadow_reg223
160 580 R/W ethercat_shadow_reg224
161 584 R/W ethercat_shadow_reg225
162 588 R/W ethercat_shadow_reg226
163 58c R/W ethercat_shadow_reg227
164 590 R/W ethercat_shadow_reg228
165 594 R/W ethercat_shadow_reg229
166 598 R/W ethercat_shadow_reg230
167 59c R/W ethercat_shadow_reg231
168 5a0 R/W ethercat_shadow_reg232
169 5a4 R/W ethercat_shadow_reg233
16a 5a8 R/W ethercat_shadow_reg234
16b 5ac R/W ethercat_shadow_reg235
16c 5b0 R/W ethercat_shadow_reg236
16d 5b4 R/W ethercat_shadow_reg237
16e 5b8 R/W ethercat_shadow_reg238
16f 5bc R/W ethercat_shadow_reg239
170 5c0 R/W ethercat_shadow_reg240
171 5c4 R/W ethercat_shadow_reg241
172 5c8 R/W ethercat_shadow_reg242
173 5cc R/W ethercat_shadow_reg243
174 5d0 R/W ethercat_shadow_reg244
175 5d4 R/W ethercat_shadow_reg245
176 5d8 R/W ethercat_shadow_reg246
177 5dc R/W ethercat_shadow_reg247
178 5e0 R/W ethercat_shadow_reg248
179 5e4 R/W ethercat_shadow_reg249
17a 5e8 R/W ethercat_shadow_reg250
17b 5ec R/W ethercat_shadow_reg251
17c 5f0 R/W ethercat_shadow_reg252
17d 5f4 R/W ethercat_shadow_reg253
17e 5f8 R/W ethercat_shadow_reg254
17f 5fc R/W ethercat_shadow_reg255
180 600 R/W ethercat_config
181 604 R ethercat_info
182 608 -  reserved
183 60c R/W ethercat_phys_addr_offset
184 610 R/W ethercat_phys_last_addr
185 614 R/W ethercat_sm_not_write_allowed_addr
186 618 R/W ethercat_fmmusm_read_addr_in
187 61c R/W ethercat_fmmusm_write_addr_in
188 620 R ethercat_sm_read_addr_out
189 624 R ethercat_sm_write_addr_out
18a 628 R ethercat_fmmu_read_bit_rol_pos
18b 62c R ethercat_fmmu_read_bit_mask
18c 630 R ethercat_fmmu_write_bit_rol_pos
18d 634 R ethercat_fmmu_write_bit_mask
18e 638 R/W ethercat_fmmusm_len_en
18f 63c R ethercat_fmmusm_status_out
190 640 R/W ethercat_sm_buf_statcfg
191 644 R/W ethercat_sm_read_event
192 648 R/W ethercat_sm_write_event
193 64c R/W ethercat_sm_first_byte_addressed
194 650 R/W ethercat_sm_last_byte_addressed
195 654 R/W ethercat_sm_served
196 658 R/W ethercat_event_req
197 65c R/W ethercat_dl_stat
198-1ff 660-7fc -  reserved

ethercat_reg0
in write enable area for match on write action
R/W
0x00000000
Address : 0x07d82000
Bits Reset value Name Description
31 - 24 "00000000"
mii0_link_down_cnt

23 - 16 "00000000"
mii0_mii_err_cnt

15 - 8 "00000000"
mii0_frwd_err_cnt

7 - 0 "00000000"
mii0_frame_err_cnt



ethercat_reg1
in write enable area for match on write action
R/W
0x00000000
Address : 0x07d82004
Bits Reset value Name Description
31 - 24 "00000000"
mii1_link_down_cnt

23 - 16 "00000000"
mii1_mii_err_cnt

15 - 8 "00000000"
mii1_frwd_err_cnt

7 - 0 "00000000"
mii1_frame_err_cnt



ethercat_reg2
FMMU 0 config register
R/W
0x00000000
Address : 0x07d82008
Bits Reset value Name Description
31 - 0 0x0
fmmu0_log_startaddr



ethercat_reg3
FMMU 0 config register
R/W
0x07000000
Address : 0x07d8200c
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu0_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu0_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu0_length
Length of FMMU-area in bytes


ethercat_reg4
FMMU 0 config register
R/W
0x00000000
Address : 0x07d82010
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu0_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu0_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu0_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu0_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg5
FMMU 1 config register
R/W
0x00000000
Address : 0x07d82014
Bits Reset value Name Description
31 - 0 0x0
fmmu1_log_startaddr



ethercat_reg6
FMMU 1 config register
R/W
0x07000000
Address : 0x07d82018
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu1_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu1_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu1_length
Length of FMMU-area in bytes


ethercat_reg7
FMMU 1 config register
R/W
0x00000000
Address : 0x07d8201c
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu1_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu1_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu1_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu1_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg8
FMMU 2 config register
R/W
0x00000000
Address : 0x07d82020
Bits Reset value Name Description
31 - 0 0x0
fmmu2_log_startaddr



ethercat_reg9
FMMU 2 config register
R/W
0x07000000
Address : 0x07d82024
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu2_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu2_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu2_length
Length of FMMU-area in bytes


ethercat_reg10
FMMU 2 config register
R/W
0x00000000
Address : 0x07d82028
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu2_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu2_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu2_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu2_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg11
FMMU 3 config register
R/W
0x00000000
Address : 0x07d8202c
Bits Reset value Name Description
31 - 0 0x0
fmmu3_log_startaddr



ethercat_reg12
FMMU 3 config register
R/W
0x07000000
Address : 0x07d82030
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu3_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu3_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu3_length
Length of FMMU-area in bytes


ethercat_reg13
FMMU 3 config register
R/W
0x00000000
Address : 0x07d82034
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu3_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu3_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu3_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu3_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg14
FMMU 4 config register
R/W
0x00000000
Address : 0x07d82038
Bits Reset value Name Description
31 - 0 0x0
fmmu4_log_startaddr



ethercat_reg15
FMMU 4 config register
R/W
0x07000000
Address : 0x07d8203c
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu4_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu4_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu4_length
Length of FMMU-area in bytes


ethercat_reg16
FMMU 4 config register
R/W
0x00000000
Address : 0x07d82040
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu4_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu4_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu4_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu4_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg17
FMMU 5 config register
R/W
0x00000000
Address : 0x07d82044
Bits Reset value Name Description
31 - 0 0x0
fmmu5_log_startaddr



ethercat_reg18
FMMU 5 config register
R/W
0x07000000
Address : 0x07d82048
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu5_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu5_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu5_length
Length of FMMU-area in bytes


ethercat_reg19
FMMU 5 config register
R/W
0x00000000
Address : 0x07d8204c
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu5_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu5_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu5_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu5_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg20
FMMU 6 config register
R/W
0x00000000
Address : 0x07d82050
Bits Reset value Name Description
31 - 0 0x0
fmmu6_log_startaddr



ethercat_reg21
FMMU 6 config register
R/W
0x07000000
Address : 0x07d82054
Bits Reset value Name Description
31 - 27 "00000"
res31_27

26 - 24 "111"
fmmu6_log_stop_bit
Logical stop bit, used for bitwise addressing.
Restricted for use inside one byte.
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu6_log_start_bit
Logical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 13 "000"
res15_13

12 - 0 0x0
fmmu6_length
Length of FMMU-area in bytes


ethercat_reg22
FMMU 6 config register
R/W
0x00000000
Address : 0x07d82058
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
fmmu6_proc_wr_enable
Enable FMMU-mapping for write access of process channel
24 "0"
fmmu6_proc_rd_enable
Enable FMMU-mapping for read access of process channel
23 - 19 "00000"
res23_19

18 - 16 "000"
fmmu6_phys_start_bit
Physical start bit, used for bitwise addressing.
Restricted for use inside one byte.
15 - 14 "00"
res15_14

13 - 0 0x0
fmmu6_phys_startaddr
Physical byte address inside 8kByte gPEC data memory


ethercat_reg23
R/W
0x00000000
Address : 0x07d8205c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg24
R/W
0x00000000
Address : 0x07d82060
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg25
R/W
0x00000000
Address : 0x07d82064
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg26
R/W
0x00000000
Address : 0x07d82068
Bits Reset value Name Description
31 - 25 "0000000"
res31_25

24 "0"
fmmu3_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
23 - 17 "0000000"
res23_17

16 "0"
fmmu2_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
15 - 9 "0000000"
res15_9

8 "0"
fmmu1_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
7 - 1 "0000000"
res7_1

0 "0"
fmmu0_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable


ethercat_reg27
R/W
0x00000000
Address : 0x07d8206c
Bits Reset value Name Description
31 - 25 "0000000"
res31_25

24 "0"
fmmu7_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
23 - 17 "0000000"
res23_17

16 "0"
fmmu6_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
15 - 9 "0000000"
res15_9

8 "0"
fmmu5_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable
7 - 1 "0000000"
res7_1

0 "0"
fmmu4_proc_enable
FMMU enable for process channel (1:active, 0: only forward) proc_enable


ethercat_reg28
SM 0 config register
R/W
0x00000000
Address : 0x07d82070
Bits Reset value Name Description
31 - 16 0x0
sm0_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm0_startaddr
Physical start address of SM-area


ethercat_reg29
SM 1 config register
R/W
0x00000000
Address : 0x07d82074
Bits Reset value Name Description
31 - 16 0x0
sm1_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm1_startaddr
Physical start address of SM-area


ethercat_reg30
SM 2 config register
R/W
0x00000000
Address : 0x07d82078
Bits Reset value Name Description
31 - 16 0x0
sm2_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm2_startaddr
Physical start address of SM-area


ethercat_reg31
SM 3 config register
R/W
0x00000000
Address : 0x07d8207c
Bits Reset value Name Description
31 - 16 0x0
sm3_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm3_startaddr
Physical start address of SM-area


ethercat_reg32
SM 4 config register
R/W
0x00000000
Address : 0x07d82080
Bits Reset value Name Description
31 - 16 0x0
sm4_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm4_startaddr
Physical start address of SM-area


ethercat_reg33
SM 5 config register
R/W
0x00000000
Address : 0x07d82084
Bits Reset value Name Description
31 - 16 0x0
sm5_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm5_startaddr
Physical start address of SM-area


ethercat_reg34
SM 6 config register
R/W
0x00000000
Address : 0x07d82088
Bits Reset value Name Description
31 - 16 0x0
sm6_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm6_startaddr
Physical start address of SM-area


ethercat_reg35
SM 7 config register
R/W
0x00000000
Address : 0x07d8208c
Bits Reset value Name Description
31 - 16 0x0
sm7_length
Length of SM-area in bytes,
tripled in case of 3-buffer method
15 - 0 0x0
sm7_startaddr
Physical start address of SM-area


ethercat_reg36
R/W
0x00000000
Address : 0x07d82090
Bits Reset value Name Description
31 "0"
res31

30 "0"
sm3_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
29 "0"
sm3_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
28 "0"
sm3_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
27 "0"
res27

26 "0"
sm3_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
25 "0"
sm3_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
24 "0"
res24

23 "0"
res23

22 "0"
sm2_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
21 "0"
sm2_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
20 "0"
sm2_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
19 "0"
res19

18 "0"
sm2_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
17 "0"
sm2_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
16 "0"
res16

15 "0"
res15

14 "0"
sm1_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
13 "0"
sm1_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
12 "0"
sm1_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
11 "0"
res11

10 "0"
sm1_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
9 "0"
sm1_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
8 "0"
res8

7 "0"
res7

6 "0"
sm0_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
5 "0"
sm0_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
4 "0"
sm0_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
3 "0"
res3

2 "0"
sm0_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
1 "0"
sm0_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
0 "0"
res0



ethercat_reg37
R/W
0x00000000
Address : 0x07d82094
Bits Reset value Name Description
31 "0"
res31

30 "0"
sm7_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
29 "0"
sm7_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
28 "0"
sm7_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
27 "0"
res27

26 "0"
sm7_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
25 "0"
sm7_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
24 "0"
res24

23 "0"
res23

22 "0"
sm6_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
21 "0"
sm6_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
20 "0"
sm6_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
19 "0"
res19

18 "0"
sm6_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
17 "0"
sm6_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
16 "0"
res16

15 "0"
res15

14 "0"
sm5_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
13 "0"
sm5_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
12 "0"
sm5_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
11 "0"
res11

10 "0"
sm5_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
9 "0"
sm5_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
8 "0"
res8

7 "0"
res7

6 "0"
sm4_cfg_wdg_en
Watchdog Trigger Enable: 0: Disabled 1: Enabled
5 "0"
sm4_cfg_al_event_en
Interrupt in AL Event Request Register: 0: Disabled 1: Enabled
4 "0"
sm4_cfg_ecat_event_en
Interrupt in ECAT Event Request Register: 0: Disabled 1: Enabled
3 "0"
res3

2 "0"
sm4_cfg_write_read
Write/Read:
0: read:  EtherCAT read,  ARM write
1: write: EtherCAT write, ARM read
1 "0"
sm4_cfg_buf_method
Buffer method
0: 3 buffer method method
1: 1 buffer method
0 "0"
res0



ethercat_reg38
R/W
0x00000000
Address : 0x07d82098
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
sm3_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
24 "0"
sm3_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
23 - 18 "000000"
res23_18

17 "0"
sm2_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
16 "0"
sm2_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
15 - 10 "000000"
res15_10

9 "0"
sm1_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
8 "0"
sm1_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
7 - 2 "000000"
res7_2

1 "0"
sm0_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
0 "0"
sm0_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel


ethercat_reg39
R/W
0x00000000
Address : 0x07d8209c
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
sm7_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
24 "0"
sm7_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
23 - 18 "000000"
res23_18

17 "0"
sm6_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
16 "0"
sm6_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
15 - 10 "000000"
res15_10

9 "0"
sm5_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
8 "0"
sm5_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel
7 - 2 "000000"
res7_2

1 "0"
sm4_repeat_req
A toggle of Repeat Request means that a mailbox retry is needed (primarily used in conjunction with ECAT Read Mailbox)
0 "0"
sm4_proc_enable
Enable for process channel
0: Sync-manager is disabled for process channel
1: Sync-manager is enabled for process channel


ethercat_reg40
R/W
0x00000000
Address : 0x07d820a0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 17 "0000000"
res23_17
mapped to EtherCAT register address 0x103
16 "0"
alias_address_enable
Station alias: 0: Ignore Station Alias 1: Alias can be used for all configured address command types (FPRD, FPWR, FPRW, FRMW)
15 - 0 0x0
station_address



ethercat_reg41
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d820a4
Bits Reset value Name Description
31 - 0 0x0
trigger_0_starttime_ns



ethercat_reg42
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d820a8
Bits Reset value Name Description
31 - 0 0x0
trigger_0_starttime_s



ethercat_reg43
R/W
0x00000000
Address : 0x07d820ac
Bits Reset value Name Description
31 - 24 "00000000"
byte_3
reserved
23 - 16 "00000000"
byte_2
reserved
15 - 8 "00000000"
byte_1
reserved
7 - 0 "00000000"
proc_err_cnt



ethercat_reg44
ECAT Event masking of the ECAT Event Request Events for mapping into ECAT event field of EtherCAT frames: 1/0: Corresponding ECAT Event Request register bit is mapped / not mapped
R/W
0x00000000
Address : 0x07d820b0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3
reserved
23 - 16 "00000000"
byte_2
reserved
15 - 12 "0000"
res15_12
reserved
11 "0"
mask_sm_status_7

10 "0"
mask_sm_status_6

9 "0"
mask_sm_status_5

8 "0"
mask_sm_status_4

7 "0"
mask_sm_status_3

6 "0"
mask_sm_status_2

5 "0"
mask_sm_status_1

4 "0"
mask_sm_status_0

3 "0"
mask_al_status_event

2 "0"
mask_dl_status_event

1 "0"
res1
reserved
0 "0"
mask_dc_latch_event



ethercat_reg45
R/W
0x00000000
Address : 0x07d820b4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg46
R/W
0x00000000
Address : 0x07d820b8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg47
R/W
0x00000000
Address : 0x07d820bc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg48
R/W
0x00000000
Address : 0x07d820c0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg49
R/W
0x00000000
Address : 0x07d820c4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg50
R/W
0x00000000
Address : 0x07d820c8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg51
R/W
0x00000000
Address : 0x07d820cc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg52
R/W
0x00000000
Address : 0x07d820d0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg53
R/W
0x00000000
Address : 0x07d820d4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg54
R/W
0x00000000
Address : 0x07d820d8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg55
R/W
0x00000000
Address : 0x07d820dc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg56
R/W
0x00000000
Address : 0x07d820e0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg57
R/W
0x00000000
Address : 0x07d820e4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg58
R/W
0x00000000
Address : 0x07d820e8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg59
R/W
0x00000000
Address : 0x07d820ec
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg60
R/W
0x00000000
Address : 0x07d820f0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg61
R/W
0x00000000
Address : 0x07d820f4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg62
R/W
0x00000000
Address : 0x07d820f8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg63
R/W
0x00000000
Address : 0x07d820fc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg64
R/W
0x30303030
Address : 0x07d82100
Bits Reset value Name Description
31 - 30 "00"
res31_30

29 - 28 "11"
sm3_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
27 "0"
sm3_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
26 "0"
res26

25 "0"
sm3_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
24 "0"
sm3_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
23 - 22 "00"
res23_22

21 - 20 "11"
sm2_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
19 "0"
sm2_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
18 "0"
res18

17 "0"
sm2_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
16 "0"
sm2_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
15 - 14 "00"
res15_14

13 - 12 "11"
sm1_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
11 "0"
sm1_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
10 "0"
res10

9 "0"
sm1_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
8 "0"
sm1_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
7 - 6 "00"
res7_6

5 - 4 "11"
sm0_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
3 "0"
sm0_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
2 "0"
res2

1 "0"
sm0_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
0 "0"
sm0_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read


ethercat_reg65
R/W
0x30303030
Address : 0x07d82104
Bits Reset value Name Description
31 - 30 "00"
res31_30

29 - 28 "11"
sm7_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
27 "0"
sm7_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
26 "0"
res26

25 "0"
sm7_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
24 "0"
sm7_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
23 - 22 "00"
res23_22

21 - 20 "11"
sm6_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
19 "0"
sm6_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
18 "0"
res18

17 "0"
sm6_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
16 "0"
sm6_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
15 - 14 "00"
res15_14

13 - 12 "11"
sm5_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
11 "0"
sm5_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
10 "0"
res10

9 "0"
sm5_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
8 "0"
sm5_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read
7 - 6 "00"
res7_6

5 - 4 "11"
sm4_buf_nr
Buffered mode: buffer status (last written buffer):
00: 1st buffer
01: 2nd buffer
10: 3rd buffer
11: (no buffer written)
Mailbox mode: reserved
3 "0"
sm4_buf_full
 Mailbox mode: mailbox status:
0: Mailbox empty
1: Mailbox full
Buffered mode: reserved
2 "0"
res2

1 "0"
sm4_read_event
Interrupt Read:
1: Interrupt after buffer was completely and successfully read
0: Interrupt cleared after first byte of buffer was written
0 "0"
sm4_write_event
Interrupt Write:
1: Interrupt after buffer was completely and successfully written
0: Interrupt cleared after first byte of buffer was read


ethercat_reg66
R/W
0x00000000
Address : 0x07d82108
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
sm3_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
24 "0"
sm3_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
23 - 18 "000000"
res23_18

17 "0"
sm2_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
16 "0"
sm2_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
15 - 10 "000000"
res15_10

9 "0"
sm1_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
8 "0"
sm1_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
7 - 2 "000000"
res7_2

1 "0"
sm0_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
0 "0"
sm0_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM


ethercat_reg67
R/W
0x00000000
Address : 0x07d8210c
Bits Reset value Name Description
31 - 26 "000000"
res31_26

25 "0"
sm7_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
24 "0"
sm7_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
23 - 18 "000000"
res23_18

17 "0"
sm6_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
16 "0"
sm6_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
15 - 10 "000000"
res15_10

9 "0"
sm5_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
8 "0"
sm5_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM
7 - 2 "000000"
res7_2

1 "0"
sm4_repeat_ack
If this is set to the same value as that set by Repeat Request, the ARM acknowledges the execution of a previous set Repeat request.
0 "0"
sm4_dis_by_arm
Sync-manager locked by ARM
0: Sync-manager is operable
1: Sync-manager is locked by ARM


ethercat_reg68
R/W
0x00000000
Address : 0x07d82110
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 0 0x0
alias_address



ethercat_reg69
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82114
Bits Reset value Name Description
31 - 0 0x0
trigger_1_starttime_ns



ethercat_reg70
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82118
Bits Reset value Name Description
31 - 0 0x0
trigger_1_starttime_s



ethercat_reg71
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d8211c
Bits Reset value Name Description
31 - 0 0x0
sample_0_pos_systime_ns



ethercat_reg72
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82120
Bits Reset value Name Description
31 - 0 0x0
sample_0_pos_systime_s



ethercat_reg73
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82124
Bits Reset value Name Description
31 - 0 0x0
sample_0_neg_systime_ns



ethercat_reg74
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82128
Bits Reset value Name Description
31 - 0 0x0
sample_0_neg_systime_s



ethercat_reg75
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d8212c
Bits Reset value Name Description
31 - 0 0x0
sample_1_pos_systime_ns



ethercat_reg76
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82130
Bits Reset value Name Description
31 - 0 0x0
sample_1_pos_systime_s



ethercat_reg77
lower part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82134
Bits Reset value Name Description
31 - 0 0x0
sample_1_neg_systime_ns



ethercat_reg78
upper part of 64 bit register, Register bytes 1..7 are internally latched (ESC_REG_UNIT / ARM independently) when byte 0 is read
R/W
0x00000000
Address : 0x07d82138
Bits Reset value Name Description
31 - 0 0x0
sample_1_neg_systime_s



ethercat_reg79
ECAT Event request
R/W
0x00000000
Address : 0x07d8213c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3
reserved
23 - 16 "00000000"
byte_2
reserved
15 - 12 "0000"
res15_12
reserved
11 "0"
sm_status_7

10 "0"
sm_status_6

9 "0"
sm_status_5

8 "0"
sm_status_4

7 "0"
sm_status_3

6 "0"
sm_status_2

5 "0"
sm_status_1

4 "0"
sm_status_0

3 "0"
al_status_event

2 "0"
dl_status_event

1 "0"
res1
reserved
0 "0"
dc_latch_event



ethercat_reg80
ECAT DL Status
R/W
0x00000000
Address : 0x07d82140
Bits Reset value Name Description
31 - 24 "00000000"
byte_3
reserved
23 - 16 "00000000"
byte_2
reserved
15 - 0 0x0
bit15_0



ethercat_reg81
Trigger Latch Status
R/W
0x00000000
Address : 0x07d82144
Bits Reset value Name Description
31 - 27 "00000"
res31_27
reserved
26 "0"
sample_1_in

25 "0"
sample_1_negedge_status

24 "0"
sample_1_posedge_status

23 - 19 "00000"
res23_19
reserved
18 "0"
sample_0_in

17 "0"
sample_0_negedge_status

16 "0"
sample_0_posedge_status

15 - 9 "0000000"
res15_9
reserved
8 "0"
sync1_status

7 - 1 "0000000"
res7_1
reserved
0 "0"
sync0_status



ethercat_reg82
R/W
0x00000000
Address : 0x07d82148
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg83
R/W
0x00000000
Address : 0x07d8214c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg84
R/W
0x00000000
Address : 0x07d82150
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg85
R/W
0x00000000
Address : 0x07d82154
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg86
R/W
0x00000000
Address : 0x07d82158
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg87
R/W
0x00000000
Address : 0x07d8215c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg88
R/W
0x00000000
Address : 0x07d82160
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg89
R/W
0x00000000
Address : 0x07d82164
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg90
R/W
0x00000000
Address : 0x07d82168
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg91
R/W
0x00000000
Address : 0x07d8216c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg92
R/W
0x00000000
Address : 0x07d82170
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg93
R/W
0x00000000
Address : 0x07d82174
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg94
R/W
0x00000000
Address : 0x07d82178
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg95
R/W
0x00000000
Address : 0x07d8217c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg96
R/W
0x00000000
Address : 0x07d82180
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg97
R/W
0x00000000
Address : 0x07d82184
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg98
R/W
0x00000000
Address : 0x07d82188
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg99
R/W
0x00000000
Address : 0x07d8218c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg100
R/W
0x00000000
Address : 0x07d82190
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg101
R/W
0x00000000
Address : 0x07d82194
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg102
R/W
0x00000000
Address : 0x07d82198
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg103
R/W
0x00000000
Address : 0x07d8219c
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg104
R/W
0x00000000
Address : 0x07d821a0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg105
R/W
0x00000000
Address : 0x07d821a4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg106
R/W
0x00000000
Address : 0x07d821a8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg107
R/W
0x00000000
Address : 0x07d821ac
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg108
R/W
0x00000000
Address : 0x07d821b0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg109
R/W
0x00000000
Address : 0x07d821b4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg110
R/W
0x00000000
Address : 0x07d821b8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg111
R/W
0x00000000
Address : 0x07d821bc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg112
R/W
0x00000000
Address : 0x07d821c0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg113
R/W
0x00000000
Address : 0x07d821c4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg114
R/W
0x00000000
Address : 0x07d821c8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg115
R/W
0x00000000
Address : 0x07d821cc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg116
R/W
0x00000000
Address : 0x07d821d0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg117
R/W
0x00000000
Address : 0x07d821d4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg118
R/W
0x00000000
Address : 0x07d821d8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg119
R/W
0x00000000
Address : 0x07d821dc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg120
R/W
0x00000000
Address : 0x07d821e0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg121
R/W
0x00000000
Address : 0x07d821e4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg122
R/W
0x00000000
Address : 0x07d821e8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg123
R/W
0x00000000
Address : 0x07d821ec
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg124
R/W
0x00000000
Address : 0x07d821f0
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg125
R/W
0x00000000
Address : 0x07d821f4
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg126
R/W
0x00000000
Address : 0x07d821f8
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_reg127
R/W
0x00000000
Address : 0x07d821fc
Bits Reset value Name Description
31 - 24 "00000000"
byte_3

23 - 16 "00000000"
byte_2

15 - 8 "00000000"
byte_1

7 - 0 "00000000"
byte_0



ethercat_shadow_reg0
reserved
R
Address : 0x07d82200
Bits Name Description
31 - 0 ethercat_shadow_reg0


ethercat_shadow_reg1
reserved
R
Address : 0x07d82204
Bits Name Description
31 - 0 ethercat_shadow_reg1


ethercat_shadow_reg2
reserved
R
Address : 0x07d82208
Bits Name Description
31 - 0 ethercat_shadow_reg2


ethercat_shadow_reg3
reserved
R
Address : 0x07d8220c
Bits Name Description
31 - 0 ethercat_shadow_reg3


ethercat_shadow_reg4
reserved
R
Address : 0x07d82210
Bits Name Description
31 - 0 ethercat_shadow_reg4


ethercat_shadow_reg5
reserved
R
Address : 0x07d82214
Bits Name Description
31 - 0 ethercat_shadow_reg5


ethercat_shadow_reg6
reserved
R
Address : 0x07d82218
Bits Name Description
31 - 0 ethercat_shadow_reg6


ethercat_shadow_reg7
reserved
R
Address : 0x07d8221c
Bits Name Description
31 - 0 ethercat_shadow_reg7


ethercat_shadow_reg8
R/W
0x00000000
Address : 0x07d82220
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg9
R/W
0x00000000
Address : 0x07d82224
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg10
R/W
0x00000000
Address : 0x07d82228
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg11
R/W
0x00000000
Address : 0x07d8222c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg12
R/W
0x00000000
Address : 0x07d82230
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg13
R/W
0x00000000
Address : 0x07d82234
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg14
R/W
0x00000000
Address : 0x07d82238
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg15
R/W
0x00000000
Address : 0x07d8223c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg16
R/W
0x00000000
Address : 0x07d82240
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg17
R/W
0x00000000
Address : 0x07d82244
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg18
R/W
0x00000000
Address : 0x07d82248
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg19
R/W
0x00000000
Address : 0x07d8224c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg20
R/W
0x00000000
Address : 0x07d82250
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg21
R/W
0x00000000
Address : 0x07d82254
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg22
R/W
0x00000000
Address : 0x07d82258
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg23
R/W
0x00000000
Address : 0x07d8225c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg24
R/W
0x00000000
Address : 0x07d82260
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg25
R/W
0x00000000
Address : 0x07d82264
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg26
R/W
0x00000000
Address : 0x07d82268
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg27
R/W
0x00000000
Address : 0x07d8226c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg28
R/W
0x00000000
Address : 0x07d82270
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg29
R/W
0x00000000
Address : 0x07d82274
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg30
R/W
0x00000000
Address : 0x07d82278
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg31
R/W
0x00000000
Address : 0x07d8227c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg32
R/W
0x00000000
Address : 0x07d82280
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg33
R/W
0x00000000
Address : 0x07d82284
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg34
R/W
0x00000000
Address : 0x07d82288
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg35
R/W
0x00000000
Address : 0x07d8228c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg36
R/W
0x00000000
Address : 0x07d82290
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg37
R/W
0x00000000
Address : 0x07d82294
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg38
R/W
0x00000000
Address : 0x07d82298
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg39
R/W
0x00000000
Address : 0x07d8229c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg40
R/W
0x00000000
Address : 0x07d822a0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg41
R/W
0x00000000
Address : 0x07d822a4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg42
R/W
0x00000000
Address : 0x07d822a8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg43
R/W
0x00000000
Address : 0x07d822ac
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg44
R/W
0x00000000
Address : 0x07d822b0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg45
R/W
0x00000000
Address : 0x07d822b4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg46
R/W
0x00000000
Address : 0x07d822b8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg47
R/W
0x00000000
Address : 0x07d822bc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg48
R/W
0x00000000
Address : 0x07d822c0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg49
R/W
0x00000000
Address : 0x07d822c4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg50
R/W
0x00000000
Address : 0x07d822c8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg51
R/W
0x00000000
Address : 0x07d822cc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg52
R/W
0x00000000
Address : 0x07d822d0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg53
R/W
0x00000000
Address : 0x07d822d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg54
R/W
0x00000000
Address : 0x07d822d8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg55
R/W
0x00000000
Address : 0x07d822dc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg56
R/W
0x00000000
Address : 0x07d822e0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg57
R/W
0x00000000
Address : 0x07d822e4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg58
R/W
0x00000000
Address : 0x07d822e8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg59
R/W
0x00000000
Address : 0x07d822ec
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg60
R/W
0x00000000
Address : 0x07d822f0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg61
R/W
0x00000000
Address : 0x07d822f4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg62
R/W
0x00000000
Address : 0x07d822f8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg63
R/W
0x00000000
Address : 0x07d822fc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg64
R/W
0x00000000
Address : 0x07d82300
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg65
R/W
0x00000000
Address : 0x07d82304
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg66
R/W
0x00000000
Address : 0x07d82308
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg67
R/W
0x00000000
Address : 0x07d8230c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg68
R/W
0x00000000
Address : 0x07d82310
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg69
R/W
0x00000000
Address : 0x07d82314
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg70
R/W
0x00000000
Address : 0x07d82318
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg71
R/W
0x00000000
Address : 0x07d8231c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg72
R/W
0x00000000
Address : 0x07d82320
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg73
R/W
0x00000000
Address : 0x07d82324
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg74
R/W
0x00000000
Address : 0x07d82328
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg75
R/W
0x00000000
Address : 0x07d8232c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg76
R/W
0x00000000
Address : 0x07d82330
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg77
R/W
0x00000000
Address : 0x07d82334
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg78
R/W
0x00000000
Address : 0x07d82338
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg79
R/W
0x00000000
Address : 0x07d8233c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg80
R/W
0x00000000
Address : 0x07d82340
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg81
R/W
0x00000000
Address : 0x07d82344
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg82
R/W
0x00000000
Address : 0x07d82348
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg83
R/W
0x00000000
Address : 0x07d8234c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg84
R/W
0x00000000
Address : 0x07d82350
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg85
R/W
0x00000000
Address : 0x07d82354
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg86
R/W
0x00000000
Address : 0x07d82358
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg87
R/W
0x00000000
Address : 0x07d8235c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg88
R/W
0x00000000
Address : 0x07d82360
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg89
R/W
0x00000000
Address : 0x07d82364
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg90
R/W
0x00000000
Address : 0x07d82368
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg91
R/W
0x00000000
Address : 0x07d8236c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg92
R/W
0x00000000
Address : 0x07d82370
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg93
R/W
0x00000000
Address : 0x07d82374
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg94
R/W
0x00000000
Address : 0x07d82378
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg95
R/W
0x00000000
Address : 0x07d8237c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg96
R/W
0x00000000
Address : 0x07d82380
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg97
R/W
0x00000000
Address : 0x07d82384
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg98
R/W
0x00000000
Address : 0x07d82388
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg99
R/W
0x00000000
Address : 0x07d8238c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg100
R/W
0x00000000
Address : 0x07d82390
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg101
R/W
0x00000000
Address : 0x07d82394
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg102
R/W
0x00000000
Address : 0x07d82398
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg103
R/W
0x00000000
Address : 0x07d8239c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg104
R/W
0x00000000
Address : 0x07d823a0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg105
R/W
0x00000000
Address : 0x07d823a4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg106
R/W
0x00000000
Address : 0x07d823a8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg107
R/W
0x00000000
Address : 0x07d823ac
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg108
R/W
0x00000000
Address : 0x07d823b0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg109
R/W
0x00000000
Address : 0x07d823b4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg110
R/W
0x00000000
Address : 0x07d823b8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg111
R/W
0x00000000
Address : 0x07d823bc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg112
R/W
0x00000000
Address : 0x07d823c0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg113
R/W
0x00000000
Address : 0x07d823c4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg114
R/W
0x00000000
Address : 0x07d823c8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg115
R/W
0x00000000
Address : 0x07d823cc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg116
R/W
0x00000000
Address : 0x07d823d0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg117
R/W
0x00000000
Address : 0x07d823d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg118
R/W
0x00000000
Address : 0x07d823d8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg119
R/W
0x00000000
Address : 0x07d823dc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg120
R/W
0x00000000
Address : 0x07d823e0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg121
R/W
0x00000000
Address : 0x07d823e4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg122
R/W
0x00000000
Address : 0x07d823e8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg123
R/W
0x00000000
Address : 0x07d823ec
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg124
R/W
0x00000000
Address : 0x07d823f0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg125
R/W
0x00000000
Address : 0x07d823f4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg126
R/W
0x00000000
Address : 0x07d823f8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg127
R/W
0x00000000
Address : 0x07d823fc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg128
R/W
0x00000000
Address : 0x07d82400
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg129
R/W
0x00000000
Address : 0x07d82404
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg130
R/W
0x00000000
Address : 0x07d82408
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg131
R/W
0x00000000
Address : 0x07d8240c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg132
R/W
0x00000000
Address : 0x07d82410
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg133
R/W
0x00000000
Address : 0x07d82414
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg134
R/W
0x00000000
Address : 0x07d82418
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg135
R/W
0x00000000
Address : 0x07d8241c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg136
R/W
0x00000000
Address : 0x07d82420
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg137
R/W
0x00000000
Address : 0x07d82424
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg138
R/W
0x00000000
Address : 0x07d82428
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg139
R/W
0x00000000
Address : 0x07d8242c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg140
R/W
0x00000000
Address : 0x07d82430
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg141
R/W
0x00000000
Address : 0x07d82434
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg142
R/W
0x00000000
Address : 0x07d82438
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg143
R/W
0x00000000
Address : 0x07d8243c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg144
R/W
0x00000000
Address : 0x07d82440
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg145
R/W
0x00000000
Address : 0x07d82444
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg146
R/W
0x00000000
Address : 0x07d82448
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg147
R/W
0x00000000
Address : 0x07d8244c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg148
R/W
0x00000000
Address : 0x07d82450
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg149
R/W
0x00000000
Address : 0x07d82454
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg150
R/W
0x00000000
Address : 0x07d82458
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg151
R/W
0x00000000
Address : 0x07d8245c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg152
R/W
0x00000000
Address : 0x07d82460
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg153
R/W
0x00000000
Address : 0x07d82464
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg154
R/W
0x00000000
Address : 0x07d82468
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg155
R/W
0x00000000
Address : 0x07d8246c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg156
R/W
0x00000000
Address : 0x07d82470
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg157
R/W
0x00000000
Address : 0x07d82474
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg158
R/W
0x00000000
Address : 0x07d82478
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg159
R/W
0x00000000
Address : 0x07d8247c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg160
R/W
0x00000000
Address : 0x07d82480
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg161
R/W
0x00000000
Address : 0x07d82484
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg162
R/W
0x00000000
Address : 0x07d82488
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg163
R/W
0x00000000
Address : 0x07d8248c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg164
R/W
0x00000000
Address : 0x07d82490
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg165
R/W
0x00000000
Address : 0x07d82494
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg166
R/W
0x00000000
Address : 0x07d82498
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg167
R/W
0x00000000
Address : 0x07d8249c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg168
R/W
0x00000000
Address : 0x07d824a0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg169
R/W
0x00000000
Address : 0x07d824a4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg170
R/W
0x00000000
Address : 0x07d824a8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg171
R/W
0x00000000
Address : 0x07d824ac
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg172
R/W
0x00000000
Address : 0x07d824b0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg173
R/W
0x00000000
Address : 0x07d824b4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg174
R/W
0x00000000
Address : 0x07d824b8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg175
R/W
0x00000000
Address : 0x07d824bc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg176
R/W
0x00000000
Address : 0x07d824c0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg177
R/W
0x00000000
Address : 0x07d824c4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg178
R/W
0x00000000
Address : 0x07d824c8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg179
R/W
0x00000000
Address : 0x07d824cc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg180
R/W
0x00000000
Address : 0x07d824d0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg181
R/W
0x00000000
Address : 0x07d824d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg182
R/W
0x00000000
Address : 0x07d824d8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg183
R/W
0x00000000
Address : 0x07d824dc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg184
R/W
0x00000000
Address : 0x07d824e0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg185
R/W
0x00000000
Address : 0x07d824e4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg186
R/W
0x00000000
Address : 0x07d824e8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg187
R/W
0x00000000
Address : 0x07d824ec
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg188
R/W
0x00000000
Address : 0x07d824f0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg189
R/W
0x00000000
Address : 0x07d824f4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg190
R/W
0x00000000
Address : 0x07d824f8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg191
R/W
0x00000000
Address : 0x07d824fc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg192
R/W
0x00000000
Address : 0x07d82500
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg193
R/W
0x00000000
Address : 0x07d82504
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg194
R/W
0x00000000
Address : 0x07d82508
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg195
R/W
0x00000000
Address : 0x07d8250c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg196
R/W
0x00000000
Address : 0x07d82510
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg197
R/W
0x00000000
Address : 0x07d82514
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg198
R/W
0x00000000
Address : 0x07d82518
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg199
R/W
0x00000000
Address : 0x07d8251c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg200
R/W
0x00000000
Address : 0x07d82520
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg201
R/W
0x00000000
Address : 0x07d82524
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg202
R/W
0x00000000
Address : 0x07d82528
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg203
R/W
0x00000000
Address : 0x07d8252c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg204
R/W
0x00000000
Address : 0x07d82530
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg205
R/W
0x00000000
Address : 0x07d82534
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg206
R/W
0x00000000
Address : 0x07d82538
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg207
R/W
0x00000000
Address : 0x07d8253c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg208
R/W
0x00000000
Address : 0x07d82540
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg209
R/W
0x00000000
Address : 0x07d82544
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg210
R/W
0x00000000
Address : 0x07d82548
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg211
R/W
0x00000000
Address : 0x07d8254c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg212
R/W
0x00000000
Address : 0x07d82550
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg213
R/W
0x00000000
Address : 0x07d82554
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg214
R/W
0x00000000
Address : 0x07d82558
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg215
R/W
0x00000000
Address : 0x07d8255c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg216
R/W
0x00000000
Address : 0x07d82560
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg217
R/W
0x00000000
Address : 0x07d82564
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg218
R/W
0x00000000
Address : 0x07d82568
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg219
R/W
0x00000000
Address : 0x07d8256c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg220
R/W
0x00000000
Address : 0x07d82570
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg221
R/W
0x00000000
Address : 0x07d82574
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg222
R/W
0x00000000
Address : 0x07d82578
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg223
R/W
0x00000000
Address : 0x07d8257c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg224
R/W
0x00000000
Address : 0x07d82580
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg225
R/W
0x00000000
Address : 0x07d82584
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg226
R/W
0x00000000
Address : 0x07d82588
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg227
R/W
0x00000000
Address : 0x07d8258c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg228
R/W
0x00000000
Address : 0x07d82590
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg229
R/W
0x00000000
Address : 0x07d82594
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg230
R/W
0x00000000
Address : 0x07d82598
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg231
R/W
0x00000000
Address : 0x07d8259c
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg232
R/W
0x00000000
Address : 0x07d825a0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg233
R/W
0x00000000
Address : 0x07d825a4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg234
R/W
0x00000000
Address : 0x07d825a8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg235
R/W
0x00000000
Address : 0x07d825ac
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg236
R/W
0x00000000
Address : 0x07d825b0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg237
R/W
0x00000000
Address : 0x07d825b4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg238
R/W
0x00000000
Address : 0x07d825b8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg239
R/W
0x00000000
Address : 0x07d825bc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg240
R/W
0x00000000
Address : 0x07d825c0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg241
R/W
0x00000000
Address : 0x07d825c4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg242
R/W
0x00000000
Address : 0x07d825c8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg243
R/W
0x00000000
Address : 0x07d825cc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg244
R/W
0x00000000
Address : 0x07d825d0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg245
R/W
0x00000000
Address : 0x07d825d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg246
R/W
0x00000000
Address : 0x07d825d8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg247
R/W
0x00000000
Address : 0x07d825dc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg248
R/W
0x00000000
Address : 0x07d825e0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg249
R/W
0x00000000
Address : 0x07d825e4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg250
R/W
0x00000000
Address : 0x07d825e8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg251
R/W
0x00000000
Address : 0x07d825ec
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg252
R/W
0x00000000
Address : 0x07d825f0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg253
R/W
0x00000000
Address : 0x07d825f4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg254
R/W
0x00000000
Address : 0x07d825f8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_shadow_reg255
R/W
0x00000000
Address : 0x07d825fc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
write

7 - 0 "00000000"
byte



ethercat_config
R/W
0x00000000
Address : 0x07d82600
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 - 0 "000"
gpec
reserved function hard wired to 3'b000
3'b000 gpec00
3'b001 gpec01
3'b010 gpec02
3'b011 gpec03
3'b100 gpec10
3'b101 gpec11
3'b110 gpec12
3'b111 gpec13


ethercat_info
register is set with fcs_ok
on match set info bit number
in info mode 5 and 6, on read match set (info bit number + 1)
R
Address : 0x07d82604
Bits Name Description
31 - 0 val
info


ethercat_phys_addr_offset
Physical offset of phys. ECAT address and gPEC data ram address
R/W
0x00000000
Address : 0x07d8260c
Bits Reset value Name Description
31 - 16 0x0
phys_addr_offset_register_area
Physical offset of phys. ECAT address and gPEC data ram address for phys_ECAT_addr<0x1000
sm_write_addr_out = physical write address to access + phys_addr_offset_register_area
sm_read_addr_out  = physical read address to access  + phys_addr_offset_register_area
15 - 0 0x0
phys_addr_offset
Physical offset of phys. ECAT address and gPEC data ram address for phys_ECAT_addr>=0x1000
sm_write_addr_out = physical write address to access + phys_addr_offset
sm_read_addr_out  = physical read address to access  + phys_addr_offset


ethercat_phys_last_addr
R/W
0x00001fff
Address : 0x07d82610
Bits Reset value Name Description
31 - 30 "00"
sm7_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm7_cfg_len + sm7_cfg_add) * buf_nr
29 - 28 "00"
sm6_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm6_cfg_len + sm6_cfg_add) * buf_nr
27 - 26 "00"
sm5_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm5_cfg_len + sm5_cfg_add) * buf_nr
25 - 24 "00"
sm4_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm4_cfg_len + sm4_cfg_add) * buf_nr
23 - 22 "00"
sm3_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm3_cfg_len + sm3_cfg_add) * buf_nr
21 - 20 "00"
sm2_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm2_cfg_len + sm2_cfg_add) * buf_nr
19 - 18 "00"
sm1_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm1_cfg_len + sm1_cfg_add) * buf_nr
17 - 16 "00"
sm0_cfg_add
add value to get DW-aligned triple buffer addresses: sm_phys_addr = fmmu_addr_out + (sm0_cfg_len + sm0_cfg_add) * buf_nr
15 - 0 0x1fff
phys_last_addr
last accessible ecat data memory address within gPEC memory, (0x1000-phys_offset_data_ram_start+ecat data size-1)
IF (sm_read_addr_out  > phys_last_addr) THEN { read to ecat data memory is locked (read_allowed=0) }
IF (sm_write_addr_out > phys_last_addr) THEN { write to ecat data memory is locked (write_allowed=0) }


ethercat_sm_not_write_allowed_addr
substitution gpec dram address in case of write not allowed
R/W
0x00001fff
Address : 0x07d82614
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 0 0x1fff
val



ethercat_fmmusm_read_addr_in
Read address from EtherCAT telegram
Write access by gPEC at adr_gPEC_r6
R/W
0x00000000
Address : 0x07d82618
Bits Reset value Name Description
31 - 0 0x0
read_adr
Read address from EtherCAT telegram


ethercat_fmmusm_write_addr_in
Write address from EtherCAT telegram
Write access by gPEC at adr_gPEC_r7
R/W
0x00000000
Address : 0x07d8261c
Bits Reset value Name Description
31 - 0 0x0
write_adr
Write address from EtherCAT telegram


ethercat_sm_read_addr_out
Physical read address in gPEC RAM
Read access by gPEC at adr_gPEC_r6
R
Address : 0x07d82620
Bits Name Description
31 - 13 -
 reserved
12 - 0 sm_read_adr_out
Physical read address in gPEC RAM
process by FMMU and SM


ethercat_sm_write_addr_out
Physical write address in gPEC RAM
Read access by gPEC at adr_gPEC_r7
R
Address : 0x07d82624
Bits Name Description
31 - 13 -
 reserved
12 - 0 sm_write_adr_out
Physical write address in gPEC RAM
process by FMMU and SM


ethercat_fmmu_read_bit_rol_pos
Shift and mask value for bitwise read access
For direct use with combined rol-and command.
Read access by gPEC at adr_statcfg2
R
Address : 0x07d82628
Bits Name Description
31 - 16 -
 reserved
15 - 8 fmmu_read_bit_mask
mask for combined rol-and command,
same as at adr_fmmu_read_bit_mask
7 - 5 fmmu_read_bit_maskmode
always 3'b010: and-mask-mode with upper mask-bits=0
4 - 0 fmmu_read_bit_rol
rotate left value for bitwise read from RAM to bitstream.
Rotates byte from RAM to correct position for insertion into stream,
 num of pos to rotate left = neg. number of pos if rotate right,
 values in range (-7..7).
For bitwise read from RAM to UTX perform:
 rol   R3,       [RAMrd]b, fmmu_read_bit_rol_pos  // shift and AND-mask bits from RAM
 nimp  R4,       URX,      fmmu_read_bit_mask     // delete to be changed bits
 or    UTX,      R3,       R4                     // insert bits
 wait


ethercat_fmmu_read_bit_mask
AND-mask for bitwise read access
In case of read_allowed==0, mask is set to 0.
Read access by gPEC at adr_statcfg3
R
Address : 0x07d8262c
Bits Name Description
31 - 8 -
 reserved
7 - 0 fmmu_read_bit_mask
AND mask for bitwise read from RAM to bitstream
1: Bit of UTX-Byte is read from RAM
0: Bit of UTX-Byte is read from stream (URX)
Used in combination with fmmu_read_bit_rol_pos (s.a.).


ethercat_fmmu_write_bit_rol_pos
Shift and mask value for bitwise write access.
For direct use with combined rol-and command.
Read access by gPEC at adr_urtx2
R
Address : 0x07d82630
Bits Name Description
31 - 16 -
 reserved
15 - 8 fmmu_write_bit_mask
mask for combined rol-and command,
same as at adr_fmmu_write_bit_mask
7 - 5 fmmu_write_bit_maskmode
always 3'b010: and-mask-mode with upper mask-bits=0
4 - 0 fmmu_write_bit_rol
rotate left value for bitwise write from bitstream to RAM.
Rotates byte from URX to correct position for insertion into RAM,
 num of pos to rotate left = neg. number of pos if rotate right,
 values in range (-7..7).
For bitwise write from URX to RAM perform:
 rol   R1,       URX.snif, fmmu_write_bit_rol_pos // shift and AND-mask bits from URX-FIFO, dont change URX-FIFO
 nimp  R2,       [RAMwr]b, fmmu_write_bit_mask    // delete to be changed bits from RAM
 or    R1,       R1,       R2                     // insert bits
 mv    UTX,      URX                              // also forward to stream
 storewait [RAMwr]b, R1                           // write modified val to RAM and wait

For bitwise read/write from URX and RAMrd to UTX and RAMwr perform:
 rol   R1,       URX.snif, fmmu_write_bit_rol_pos // shift and AND-mask bits from URX-FIFO, dont change URX-FIFO
 nimp  R2,       [RAMwr]b, fmmu_write_bit_mask    // delete to be changed bits from RAM
 rol   R3,       [RAMrd]b, fmmu_read_bit_rol_pos  // shift and AND-mask bits from RAM
 nimp  R4,       URX,      fmmu_read_bit_mask     // delete to be changed bits
 or    UTX,      R3,       R4                     // insert bits
 or    R1,       R1,       R2                     // insert bits
 storewait [RAMwr]b, R1                           // write modified val to RAM and wait


ethercat_fmmu_write_bit_mask
AND-mask for bitwise write access
In case of write_allowed==0, mask is set to 0.
Read access by gPEC at adr_urtx3
R
Address : 0x07d82634
Bits Name Description
31 - 8 -
 reserved
7 - 0 fmmu_write_bit_mask
AND mask for bitwise write from bitstream to RAM
1: Bit of RAM Byte is written from stream (URX)
0: Bit of RAM Byte is unchanged
Used in combination with fmmu_write_bit_rol_pos (s.a.).


ethercat_fmmusm_len_en
Logical address enable from EtherCAT command
Read/Write access by gPEC at adr_gPEC_sr8
R/W
0x00000000
Address : 0x07d82638
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
wr_en
1/0: check/no_check for write direction
17 "0"
rd_en
1/0: check/no_check for read direction
16 "0"
log_addr_en
Logical address enable
1: fmmusm_read_addr_in and fmmusm_write_addr_in are logical addresses
0: fmmusm_read_addr_in and fmmusm_write_addr_in are physical addresses (bypass fmmu)
15 - 0 0x0
ecat_len
Length of EtherCAT telegram:
If UTX_COUNT == ecat_len
an event is generated (ecat_fin),
and furthermore calculations are blocked (allowed=0).


ethercat_fmmusm_status_out
FMMU and SM match status:
Flags [31,30] are connected to event controller.
Read access by gPEC at adr_gPEC_sr9
R
Address : 0x07d8263c
Bits Name Description
31 ecat_fin
EtherCAT telegram is finished (utx_count == fmmusm_len_en.ecat_len)
30 allowed
Read or write allowed, bitwise or bytewise
29 allowed_bitwise
Read or write bitwise allowed
----------------------------------------------------------------------
28 - 26 -
 reserved
25 write_fmmu_match_bitwise
1: fmmu bitwise write match, write address translation successful, write access is bitwise
24 read_fmmu_match_bitwise
1: fmmu bitwise read match, read address translation successful, read access is bitwise
23 write_fmmu_no_match
1: no fmmu write match, write address translation failed, write_fmmu_match_nr is invalid
22 - 20 write_fmmu_match_nr
Number of actual matching fmmu manager for write access (0..7), write_fmmu_match_nr is invalid
19 read_fmmu_no_match
1: no fmmu read match, read address translation failed, read_fmmu_match_nr is invalid
18 - 16 read_fmmu_match_nr
Number of actual matching fmmu manager for read access (0..7)
----------------------------------------------------------------------
15 write_allowed_bitwise
1/0: write access type is bitwise/bytewise, only valid if %write_allowed%==1
14 write_allowed
1/0: gPEC memory address %sm_write_addr_out% is released/ locked for writing
13 write_sm_lba
Actual Sync Manager (write_sm_nr) matches on last byte, only valid if write_allowed==1
12 write_sm_fba
Actual Sync Manager (write_sm_nr) matches on first byte, only valid if write_allowed==1
11 write_sm_no_match
1: No sync manager matches for writing -> direct access into gPEC Memory (register or data area).
Write access is allowed, if last_phys_data_addr is not exceeded.
0: Any sync manager matches for Writing:
Write access is allowed, depending on diversse enables, buf_method, fba, lba,...
10 - 8 write_sm_nr
Number of actual matching sync manager for write access (0..7), independent on %write_allowed%
7 read_allowed_bitwise
1/0: read access type is bitwise/bytewise, only valid if %read_allowed%==1
6 read_allowed
1/0: gPEC memory address %sm_read_addr_out% is released/ locked for reading
5 read_sm_lba
Actual Sync Manager (read_sm_nr) matches on last byte, only valid if read_allowed==1
4 read_sm_fba
Actual Sync Manager (read_sm_nr) matches on first byte, only valid if read_allowed==1
3 read_sm_no_match
1: No sync manager matches for reading -> direct access into gPEC Memory (register or data area).
Read access is allowed, if last_phys_data_addr is not exceeded.
0: Any sync manager matches for reading:
Read access is allowed, depending on diversse enables, buf_method, fba, lba,...
2 - 0 read_sm_nr
Number of actual matching sync manager for read access (0..7), independent on %read_allowed%


ethercat_sm_buf_statcfg
Config bits set by gPEC, if any 3-buffer-SM gets new buffer.
Writable in parallel with mask by all gPECs, ARM and BUF_MAN.
Read/Write access by gPEC at adr_gPEC_sr10
R/W
0x00ffff00
Address : 0x07d82640
Bits Reset value Name Description
31 "0"
buf_mask7
Write mask: change only bits of SM7:
Depending on sm7_cfg_mode.buf_method, mask acts on buf_nr_7 or buf_full_7.
30 "0"
buf_mask6
Write mask: change only bits of SM6:
Depending on sm6_cfg_mode.buf_method, mask acts on buf_nr_6 or buf_full_6.
29 "0"
buf_mask5
Write mask: change only bits of SM5:
Depending on sm5_cfg_mode.buf_method, mask acts on buf_nr_5 or buf_full_5.
28 "0"
buf_mask4
Write mask: change only bits of SM4:
Depending on sm4_cfg_mode.buf_method, mask acts on buf_nr_4 or buf_full_4.
27 "0"
buf_mask3
Write mask: change only bits of SM3:
Depending on sm3_cfg_mode.buf_method, mask acts on buf_nr_3 or buf_full_3.
26 "0"
buf_mask2
Write mask: change only bits of SM2:
Depending on sm2_cfg_mode.buf_method, mask acts on buf_nr_2 or buf_full_2.
25 "0"
buf_mask1
Write mask: change only bits of SM1:
Depending on sm1_cfg_mode.buf_method, mask acts on buf_nr_1 or buf_full_1.
24 "0"
buf_mask0
Write mask: change only bits of SM0:
Depending on sm0_cfg_mode.buf_method, mask acts on buf_nr_0 or buf_full_0.
23 - 22 "11"
buf_nr_7
Buffer number in use by gPEC of SM7, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
21 - 20 "11"
buf_nr_6
Buffer number in use by gPEC of SM6, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
19 - 18 "11"
buf_nr_5
Buffer number in use by gPEC of SM5, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
17 - 16 "11"
buf_nr_4
Buffer number in use by gPEC of SM4, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
15 - 14 "11"
buf_nr_3
Buffer number in use by gPEC of SM3, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
13 - 12 "11"
buf_nr_2
Buffer number in use by gPEC of SM2, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
11 - 10 "11"
buf_nr_1
Buffer number in use by gPEC of SM1, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
9 - 8 "11"
buf_nr_0
Buffer number in use by gPEC of SM0, if 3 buffer method is activated.
Usually set by BUF_MAN (not by software).
7 "0"
buf_full_7
Buffer of SM7 in use by gPEC is full, if 1 buffer method is activated.
6 "0"
buf_full_6
Buffer of SM6 in use by gPEC is full, if 1 buffer method is activated.
5 "0"
buf_full_5
Buffer of SM5 in use by gPEC is full, if 1 buffer method is activated.
4 "0"
buf_full_4
Buffer of SM4 in use by gPEC is full, if 1 buffer method is activated.
3 "0"
buf_full_3
Buffer of SM3 in use by gPEC is full, if 1 buffer method is activated.
2 "0"
buf_full_2
Buffer of SM2 in use by gPEC is full, if 1 buffer method is activated.
1 "0"
buf_full_1
Buffer of SM1 in use by gPEC is full, if 1 buffer method is activated.
0 "0"
buf_full_0
Buffer of SM0 in use by gPEC is full, if 1 buffer method is activated.


ethercat_sm_read_event
Read Event status bits of all SM, process channel:
Writable in parallel with mask by all gPECs and ARM.
Reset by FMMUSM at first_byte_addressed and write_allowed.
Read/Write access by gPEC at adr_gPEC_sr11
R/W
0x00000000
Address : 0x07d82644
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
read_event_mask7
write mask: change only bit of SM7
22 "0"
read_event_mask6
write mask: change only bit of SM6
21 "0"
read_event_mask5
write mask: change only bit of SM5
20 "0"
read_event_mask4
write mask: change only bit of SM4
19 "0"
read_event_mask3
write mask: change only bit of SM3
18 "0"
read_event_mask2
write mask: change only bit of SM2
17 "0"
read_event_mask1
write mask: change only bit of SM1
16 "0"
read_event_mask0
write mask: change only bit of SM0
15 - 8 0
-
 reserved
7 "0"
read_event_7
SM7 read event
6 "0"
read_event_6
SM6 read event
5 "0"
read_event_5
SM5 read event
4 "0"
read_event_4
SM4 read event
3 "0"
read_event_3
SM3 read event
2 "0"
read_event_2
SM2 read event
1 "0"
read_event_1
SM1 read event
0 "0"
read_event_0
SM0 read event


ethercat_sm_write_event
Write Event status bits of all SM, process channel
Writable in parallel with mask by all gPECs and ARM.
Reset by FMMUSM at first_byte_addressed and read_allowed.
Read/Write access by gPEC at adr_gPEC_sr12
R/W
0x00000000
Address : 0x07d82648
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
write_event_mask7
write mask: change only bit of SM7
22 "0"
write_event_mask6
write mask: change only bit of SM6
21 "0"
write_event_mask5
write mask: change only bit of SM5
20 "0"
write_event_mask4
write mask: change only bit of SM4
19 "0"
write_event_mask3
write mask: change only bit of SM3
18 "0"
write_event_mask2
write mask: change only bit of SM2
17 "0"
write_event_mask1
write mask: change only bit of SM1
16 "0"
write_event_mask0
write mask: change only bit of SM0
15 - 8 0
-
 reserved
7 "0"
write_event_7
SM7 write event
6 "0"
write_event_6
SM6 write event
5 "0"
write_event_5
SM5 write event
4 "0"
write_event_4
SM4 write event
3 "0"
write_event_3
SM3 write event
2 "0"
write_event_2
SM2 write event
1 "0"
write_event_1
SM1 write event
0 "0"
write_event_0
SM0 write event


ethercat_sm_first_byte_addressed
First byte addressed status bits of all SM, process channel:
Set by HW, if first byte was addressed.
Reset by SW (gPEC or ARM), by writing 1 on appropriate bit (usually after FCSok/fail).
Resetable in parallel by all gPECs and ARM.
Bits 31:8 are read only versions of other registers for faster update of register area.
Read/Write access by gPEC at adr_gPEC_sr13
R/W
0x00000000
Address : 0x07d8264c
Bits Reset value Name Description
31 - 30 "00"
buf_nr_3
read only version of sm_buf_statcfg.buf_nr_3
29 "0"
buf_full_3
read only version of sm_buf_statcfg.buf_full_3
28 0
-
 reserved
27 "0"
read_event_3
read only version of sm_read_event.read_event_3
26 "0"
write_event_3
read only version of sm_write_event.write_event_3
25 - 24 "00"
buf_nr_2
read only version of sm_buf_statcfg.buf_nr_2
23 "0"
buf_full_2
read only version of sm_buf_statcfg.buf_full_2
22 0
-
 reserved
21 "0"
read_event_2
read only version of sm_read_event.read_event_2
20 "0"
write_event_2
read only version of sm_write_event.write_event_2
19 - 18 "00"
buf_nr_1
read only version of sm_buf_statcfg.buf_nr_1
17 "0"
buf_full_1
read only version of sm_buf_statcfg.buf_full_1
16 0
-
 reserved
15 "0"
read_event_1
read only version of sm_read_event.read_event_1
14 "0"
write_event_1
read only version of sm_write_event.write_event_1
13 - 12 "00"
buf_nr_0
read only version of sm_buf_statcfg.buf_nr_0
11 "0"
buf_full_0
read only version of sm_buf_statcfg.buf_full_0
10 0
-
 reserved
9 "0"
read_event_0
read only version of sm_read_event.read_event_0
8 "0"
write_event_0
read only version of sm_write_event.write_event_0
7 "0"
fba_7
SM7 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
6 "0"
fba_6
SM6 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
5 "0"
fba_5
SM5 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
4 "0"
fba_4
SM4 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
3 "0"
fba_3
SM3 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
2 "0"
fba_2
SM2 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
1 "0"
fba_1
SM1 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area
0 "0"
fba_0
SM0 matches first byte of its address area
0: match only for first address (byte) of SM-address-area (len=1)
1: match on whole SM-address-area


ethercat_sm_last_byte_addressed
Last byte addressed status bits of all SM, process channel:
Set by HW, if last byte was addressed.
Reset by SW (gPEC or ARM), by writing 1 on appropriate bit (usually after FCSok/fail).
Resetable in parallel by all gPECs and ARM.
Bits 31:8 are read only versions of other registers for faster update of register area.
Read/Write access by gPEC at adr_gPEC_sr14
R/W
0x00000000
Address : 0x07d82650
Bits Reset value Name Description
31 - 30 "00"
buf_nr_7
read only version of sm_buf_statcfg.buf_nr_7
29 "0"
buf_full_7
read only version of sm_buf_statcfg.buf_full_7
28 0
-
 reserved
27 "0"
read_event_7
read only version of sm_read_event.read_event_7
26 "0"
write_event_7
read only version of sm_write_event.write_event_7
25 - 24 "00"
buf_nr_6
read only version of sm_buf_statcfg.buf_nr_6
23 "0"
buf_full_6
read only version of sm_buf_statcfg.buf_full_6
22 0
-
 reserved
21 "0"
read_event_6
read only version of sm_read_event.read_event_6
20 "0"
write_event_6
read only version of sm_write_event.write_event_6
19 - 18 "00"
buf_nr_5
read only version of sm_buf_statcfg.buf_nr_5
17 "0"
buf_full_5
read only version of sm_buf_statcfg.buf_full_5
16 0
-
 reserved
15 "0"
read_event_5
read only version of sm_read_event.read_event_5
14 "0"
write_event_5
read only version of sm_write_event.write_event_5
13 - 12 "00"
buf_nr_4
read only version of sm_buf_statcfg.buf_nr_4
11 "0"
buf_full_4
read only version of sm_buf_statcfg.buf_full_4
10 0
-
 reserved
9 "0"
read_event_4
read only version of sm_read_event.read_event_4
8 "0"
write_event_4
read only version of sm_write_event.write_event_4
7 "0"
lba_7
SM7 matches last byte of its address area
6 "0"
lba_6
SM6 matches last byte of its address area
5 "0"
lba_5
SM5 matches last byte of its address area
4 "0"
lba_4
SM4 matches last byte of its address area
3 "0"
lba_3
SM3 matches last byte of its address area
2 "0"
lba_2
SM2 matches last byte of its address area
1 "0"
lba_1
SM1 matches last byte of its address area
0 "0"
lba_0
SM0 matches last byte of its address area


ethercat_sm_served
Served status bits of all SM, process channel:
Set by HW, if SM gives write_allowed or read_allowed.
Reset by SW (gPEC or ARM), by writing 1 on appropriate bit (usually after FCSok/fail).
Read/Write access by gPEC at adr_gPEC_sr15
R/W
0x00000000
Address : 0x07d82654
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
any_proc_write_match
Any write access was allowed, i.e. any SM matched for write or direct write access
8 "0"
any_proc_read_match
Any read access was allowed, i.e. any SM matched for read or direct read access
7 "0"
srvd_7
SM7 address area was read or write accessed by gPEC
6 "0"
srvd_6
SM6 address area was read or write accessed by gPEC
5 "0"
srvd_5
SM5 address area was read or write accessed by gPEC
4 "0"
srvd_4
SM4 address area was read or write accessed by gPEC
3 "0"
srvd_3
SM3 address area was read or write accessed by gPEC
2 "0"
srvd_2
SM2 address area was read or write accessed by gPEC
1 "0"
srvd_1
SM1 address area was read or write accessed by gPEC
0 "0"
srvd_0
SM0 address area was read or write accessed by gPEC


ethercat_event_req
R/W
0x00000000
Address : 0x07d82658
Bits Reset value Name Description
31 - 16 0x0
write_mask
write 1'b1 to write bits 15-12, 3, 2, 1
15 - 12 "0000"
res15_12

11 - 4 0
-
 reserved
3 "0"
al_status_event

2 "0"
dl_status_event

1 "0"
bit1

0 0
-
 reserved


ethercat_dl_stat
R/W
0x00000000
Address : 0x07d8265c
Bits Reset value Name Description
31 - 16 0x0
write_mask
write 1'b1 to write bits 15-0
15 - 0 0x0
bit15_0




Base Address Area: gxc_pfifo0_config, gxc_pfifo1_config, gxc_pfifo2_config, gxc_pfifo3_config

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_pfifo_config_mask
1 4 R/W gxc_pfifo_config_ab_sel
2 8 R gxc_pfifo_config_nempty_masked_a
3 c R gxc_pfifo_config_nempty_masked_b
4 10 R gxc_pfifo_config_irq
5 14 R/W gxc_pfifo_config_event_sel
6 18 R/W gxc_pfifo_config_prio_lock
7 1c R/W gxc_pfifo_config_queue_nempty_man
8 20 R/W gxc_pfifo_config_queue_nempty_sel
9 24 R/W gxc_pfifo_config_border0
a 28 R/W gxc_pfifo_config_border1
b 2c R/W gxc_pfifo_config_border2
c 30 R/W gxc_pfifo_config_border3
d 34 R/W gxc_pfifo_config_border4
e 38 R/W gxc_pfifo_config_border5
f 3c R/W gxc_pfifo_config_border6
10 40 R/W gxc_pfifo_config_border7
11 44 R/W gxc_pfifo_config_border8
12 48 R/W gxc_pfifo_config_border9
13 4c R/W gxc_pfifo_config_border10
14 50 R/W gxc_pfifo_config_border11
15 54 R/W gxc_pfifo_config_border12
16 58 R/W gxc_pfifo_config_border13
17 5c R/W gxc_pfifo_config_border14
18 60 R/W gxc_pfifo_config_border15
19 64 R/W gxc_pfifo_config_nempty_irq_sel0
1a 68 R/W gxc_pfifo_config_nempty_irq_sel1
1b 6c R gxc_pfifo_config_irq_raw
1c 70 R/W gxc_pfifo_config_irq_masked
1d 74 R/W gxc_pfifo_config_irq_mask_set
1e 78 R/W gxc_pfifo_config_irq_mask_rst
1f 7c -  reserved

gxc_pfifo_config_mask
nempty mask:
AND mask to enable not empty signals of each FIFO.
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82800
Address@gxc_pfifo1_config : 0x07d82880
Address@gxc_pfifo2_config : 0x07d82900
Address@gxc_pfifo3_config : 0x07d82980
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
one mask bit per FIFO


gxc_pfifo_config_ab_sel
AB select:
Selects for each FIFO, if not empty irq/event is output to GPEC port A of B.
0: select port A to GPECs
1: select port B to GPECs
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82804
Address@gxc_pfifo1_config : 0x07d82884
Address@gxc_pfifo2_config : 0x07d82904
Address@gxc_pfifo3_config : 0x07d82984
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
one select bit per FIFO


gxc_pfifo_config_nempty_masked_a
nempty masked A:
Read only value of masked, port_selected and ab_selected vector of port A.
R
Address@gxc_pfifo0_config : 0x07d82808
Address@gxc_pfifo1_config : 0x07d82888
Address@gxc_pfifo2_config : 0x07d82908
Address@gxc_pfifo3_config : 0x07d82988
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
masked not empty vector of channel A


gxc_pfifo_config_nempty_masked_b
nempty masked B:
Read only value of masked, port_selected and ab_selected vector of port B.
R
Address@gxc_pfifo0_config : 0x07d8280c
Address@gxc_pfifo1_config : 0x07d8288c
Address@gxc_pfifo2_config : 0x07d8290c
Address@gxc_pfifo3_config : 0x07d8298c
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
masked not empty vector B


gxc_pfifo_config_irq
IRQ/Event number:
Shows highest active irq/event for each GPEC port.
R
Address@gxc_pfifo0_config : 0x07d82810
Address@gxc_pfifo1_config : 0x07d82890
Address@gxc_pfifo2_config : 0x07d82910
Address@gxc_pfifo3_config : 0x07d82990
Bits Name Description
31 - 13 -
 reserved
12 - 8 pfifo_irq_num_b
shows highest set bit position within pfifo_nempty_masked_B
7 - 5 -
 reserved
4 - 0 pfifo_irq_num_a
shows highest set bit position within pfifo_nempty_masked_A


gxc_pfifo_config_event_sel
Event select:
Select for each FIFO event to GPEC's Event Controller:
0: use not empty signal from FIFO directly
1: use masked and port_selected not empty signal
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82814
Address@gxc_pfifo1_config : 0x07d82894
Address@gxc_pfifo2_config : 0x07d82914
Address@gxc_pfifo3_config : 0x07d82994
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
rate_limiter1_en
enables AND-masking of pfifo_nempty[15:8] with bucket_nempty vector of token_bucket_instance1
16 "0"
rate_limiter0_en
enables AND-masking of pfifo_nempty[7:0] with bucket_nempty vector of token_bucket_instance0
15 - 0 0x0
val
one select bit per FIFO


gxc_pfifo_config_prio_lock
this register can lock one gpec master in pfifo arbiter to highest priority
use of nr: gpec00 = 0, gpec01 = 1, gpec02 = 2, gpec03 = 3 gpec04 = 4, gpec05 = 5, gpec06 = 6, gpec07 = 7
           gpec10 = 8, gpec11 = 9, gpec12 = 10, gpec13 = 11 gpec14 = 12, gpec15 = 13, gpec16 = 14, gpec17 = 15
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82818
Address@gxc_pfifo1_config : 0x07d82898
Address@gxc_pfifo2_config : 0x07d82918
Address@gxc_pfifo3_config : 0x07d82998
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
lock
lock bit
3 - 0 "0000"
nr
number of fifo locked to highest priority


gxc_pfifo_config_queue_nempty_man
Remark: This register is also writable by GPECs
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d8281c
Address@gxc_pfifo1_config : 0x07d8289c
Address@gxc_pfifo2_config : 0x07d8291c
Address@gxc_pfifo3_config : 0x07d8299c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
one manual nempty bit per queue


gxc_pfifo_config_queue_nempty_sel
This register selects the input nempty signals for the mask functionality from four different sources:
selN = 0: ~pfifo_empty[N]
selN = 1: host_req[N + instance_num * 16]
selN = 2: queue_nempty_man[N]
selN = 3: host_req[N + instance_num * 16] OR queue_nempty_man[N]
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82820
Address@gxc_pfifo1_config : 0x07d828a0
Address@gxc_pfifo2_config : 0x07d82920
Address@gxc_pfifo3_config : 0x07d829a0
Bits Reset value Name Description
31 - 30 "00"
sel15
selector for queue 15
29 - 28 "00"
sel14
selector for queue 14
27 - 26 "00"
sel13
selector for queue 13
25 - 24 "00"
sel12
selector for queue 12
23 - 22 "00"
sel11
selector for queue 11
21 - 20 "00"
sel10
selector for queue 10
19 - 18 "00"
sel9
selector for queue 9
17 - 16 "00"
sel8
selector for queue 8
15 - 14 "00"
sel7
selector for queue 7
13 - 12 "00"
sel6
selector for queue 6
11 - 10 "00"
sel5
selector for queue 5
9 - 8 "00"
sel4
selector for queue 4
7 - 6 "00"
sel3
selector for queue 3
5 - 4 "00"
sel2
selector for queue 2
3 - 2 "00"
sel1
selector for queue 1
1 - 0 "00"
sel0
selector for queue 0


gxc_pfifo_config_border0
Upper Border of FIFO 0:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000000ff
Address@gxc_pfifo0_config : 0x07d82824
Address@gxc_pfifo1_config : 0x07d828a4
Address@gxc_pfifo2_config : 0x07d82924
Address@gxc_pfifo3_config : 0x07d829a4
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border1
Upper Border of FIFO 1:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000001ff
Address@gxc_pfifo0_config : 0x07d82828
Address@gxc_pfifo1_config : 0x07d828a8
Address@gxc_pfifo2_config : 0x07d82928
Address@gxc_pfifo3_config : 0x07d829a8
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x1ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border2
Upper Border of FIFO 2:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000002ff
Address@gxc_pfifo0_config : 0x07d8282c
Address@gxc_pfifo1_config : 0x07d828ac
Address@gxc_pfifo2_config : 0x07d8292c
Address@gxc_pfifo3_config : 0x07d829ac
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x2ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border3
Upper Border of FIFO 3:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000003ff
Address@gxc_pfifo0_config : 0x07d82830
Address@gxc_pfifo1_config : 0x07d828b0
Address@gxc_pfifo2_config : 0x07d82930
Address@gxc_pfifo3_config : 0x07d829b0
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x3ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border4
Upper Border of FIFO 4:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000004ff
Address@gxc_pfifo0_config : 0x07d82834
Address@gxc_pfifo1_config : 0x07d828b4
Address@gxc_pfifo2_config : 0x07d82934
Address@gxc_pfifo3_config : 0x07d829b4
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x4ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border5
Upper Border of FIFO 5:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000005ff
Address@gxc_pfifo0_config : 0x07d82838
Address@gxc_pfifo1_config : 0x07d828b8
Address@gxc_pfifo2_config : 0x07d82938
Address@gxc_pfifo3_config : 0x07d829b8
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x5ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border6
Upper Border of FIFO 6:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000006ff
Address@gxc_pfifo0_config : 0x07d8283c
Address@gxc_pfifo1_config : 0x07d828bc
Address@gxc_pfifo2_config : 0x07d8293c
Address@gxc_pfifo3_config : 0x07d829bc
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x6ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border7
Upper Border of FIFO 7:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000007ff
Address@gxc_pfifo0_config : 0x07d82840
Address@gxc_pfifo1_config : 0x07d828c0
Address@gxc_pfifo2_config : 0x07d82940
Address@gxc_pfifo3_config : 0x07d829c0
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x7ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border8
Upper Border of FIFO 8:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000008ff
Address@gxc_pfifo0_config : 0x07d82844
Address@gxc_pfifo1_config : 0x07d828c4
Address@gxc_pfifo2_config : 0x07d82944
Address@gxc_pfifo3_config : 0x07d829c4
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x8ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border9
Upper Border of FIFO 9:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x000009ff
Address@gxc_pfifo0_config : 0x07d82848
Address@gxc_pfifo1_config : 0x07d828c8
Address@gxc_pfifo2_config : 0x07d82948
Address@gxc_pfifo3_config : 0x07d829c8
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x9ff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border10
Upper Border of FIFO 10:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000aff
Address@gxc_pfifo0_config : 0x07d8284c
Address@gxc_pfifo1_config : 0x07d828cc
Address@gxc_pfifo2_config : 0x07d8294c
Address@gxc_pfifo3_config : 0x07d829cc
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xaff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border11
Upper Border of FIFO 11:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000bff
Address@gxc_pfifo0_config : 0x07d82850
Address@gxc_pfifo1_config : 0x07d828d0
Address@gxc_pfifo2_config : 0x07d82950
Address@gxc_pfifo3_config : 0x07d829d0
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xbff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border12
Upper Border of FIFO 12:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000cff
Address@gxc_pfifo0_config : 0x07d82854
Address@gxc_pfifo1_config : 0x07d828d4
Address@gxc_pfifo2_config : 0x07d82954
Address@gxc_pfifo3_config : 0x07d829d4
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xcff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border13
Upper Border of FIFO 13:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000dff
Address@gxc_pfifo0_config : 0x07d82858
Address@gxc_pfifo1_config : 0x07d828d8
Address@gxc_pfifo2_config : 0x07d82958
Address@gxc_pfifo3_config : 0x07d829d8
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xdff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border14
Upper Border of FIFO 14:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000eff
Address@gxc_pfifo0_config : 0x07d8285c
Address@gxc_pfifo1_config : 0x07d828dc
Address@gxc_pfifo2_config : 0x07d8295c
Address@gxc_pfifo3_config : 0x07d829dc
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xeff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_border15
Upper Border of FIFO 15:
Each PFIFO module has a 4kx32 bit RAM, where all FIFOs data is stored sequentially.
Each FIFO starts at the upper border + 1 of the preceding FIFO and ends at its upper border.
If a border between two FIFOs is moved, the adjacent FIFOs should be reset first.
R/W
0x00000fff
Address@gxc_pfifo0_config : 0x07d82860
Address@gxc_pfifo1_config : 0x07d828e0
Address@gxc_pfifo2_config : 0x07d82960
Address@gxc_pfifo3_config : 0x07d829e0
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0xfff
border
last address of RAM used by appropriate FIFO, = (first address-1) of next FIFO.


gxc_pfifo_config_nempty_irq_sel0
Not-empty-IRQ-select:
To handle data from Pointer FIFOs to CPU in priority levels,
each FIFO can assign a not-emply signal to 1 of 8 IRQs (0..7) or none(8).
This register holds IRQ numbers for FIFOs 0..7.
R/W
0x88888888
Address@gxc_pfifo0_config : 0x07d82864
Address@gxc_pfifo1_config : 0x07d828e4
Address@gxc_pfifo2_config : 0x07d82964
Address@gxc_pfifo3_config : 0x07d829e4
Bits Reset value Name Description
31 - 28 "1000"
irq_nr_fifo7
Number of assigned IRQ for FIFO 7
27 - 24 "1000"
irq_nr_fifo6
Number of assigned IRQ for FIFO 6
23 - 20 "1000"
irq_nr_fifo5
Number of assigned IRQ for FIFO 5
19 - 16 "1000"
irq_nr_fifo4
Number of assigned IRQ for FIFO 4
15 - 12 "1000"
irq_nr_fifo3
Number of assigned IRQ for FIFO 3
11 - 8 "1000"
irq_nr_fifo2
Number of assigned IRQ for FIFO 2
7 - 4 "1000"
irq_nr_fifo1
Number of assigned IRQ for FIFO 1
3 - 0 "1000"
irq_nr_fifo0
Number of assigned IRQ for FIFO 0


gxc_pfifo_config_nempty_irq_sel1
Not-empty-IRQ-select:
To handle data from Pointer FIFOs to CPU in priority levels,
each FIFO can assign a not-emply signal to 1 of 8 IRQs (0..7) or none(8).
This register holds IRQ numbers for FIFOs 8..15.
R/W
0x88888888
Address@gxc_pfifo0_config : 0x07d82868
Address@gxc_pfifo1_config : 0x07d828e8
Address@gxc_pfifo2_config : 0x07d82968
Address@gxc_pfifo3_config : 0x07d829e8
Bits Reset value Name Description
31 - 28 "1000"
irq_nr_fifo15
Number of assigned IRQ for FIFO 15
27 - 24 "1000"
irq_nr_fifo14
Number of assigned IRQ for FIFO 14
23 - 20 "1000"
irq_nr_fifo13
Number of assigned IRQ for FIFO 13
19 - 16 "1000"
irq_nr_fifo12
Number of assigned IRQ for FIFO 12
15 - 12 "1000"
irq_nr_fifo11
Number of assigned IRQ for FIFO 11
11 - 8 "1000"
irq_nr_fifo10
Number of assigned IRQ for FIFO 10
7 - 4 "1000"
irq_nr_fifo9
Number of assigned IRQ for FIFO 9
3 - 0 "1000"
irq_nr_fifo8
Number of assigned IRQ for FIFO 8


gxc_pfifo_config_irq_raw
gxc_pfifo_config raw IRQ:
Read access shows status of unmasked IRQs.
R
Address@gxc_pfifo0_config : 0x07d8286c
Address@gxc_pfifo1_config : 0x07d828ec
Address@gxc_pfifo2_config : 0x07d8296c
Address@gxc_pfifo3_config : 0x07d829ec
Bits Name Description
31 - 8 -
 reserved
7 nempty_prio_7
not empty prio7 IRQ
6 nempty_prio_6
not empty prio6 IRQ
5 nempty_prio_5
not empty prio5 IRQ
4 nempty_prio_4
not empty prio4 IRQ
3 nempty_prio_3
not empty prio3 IRQ
2 nempty_prio_2
not empty prio2 IRQ
1 nempty_prio_1
not empty prio1 IRQ
0 nempty_prio_0
not empty prio0 IRQ


gxc_pfifo_config_irq_masked
gxc_pfifo_config masked IRQ:
Read access shows status of masked IRQs.
Write access is for debug only:
'1' sets irq_raw to 1.
'0' sets irq_raw to value coming from HW
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82870
Address@gxc_pfifo1_config : 0x07d828f0
Address@gxc_pfifo2_config : 0x07d82970
Address@gxc_pfifo3_config : 0x07d829f0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
nempty_prio_7
not empty prio7 IRQ
6 "0"
nempty_prio_6
not empty prio6 IRQ
5 "0"
nempty_prio_5
not empty prio5 IRQ
4 "0"
nempty_prio_4
not empty prio4 IRQ
3 "0"
nempty_prio_3
not empty prio3 IRQ
2 "0"
nempty_prio_2
not empty prio2 IRQ
1 "0"
nempty_prio_1
not empty prio1 IRQ
0 "0"
nempty_prio_0
not empty prio0 IRQ


gxc_pfifo_config_irq_mask_set
gxc_pfifo_config IRQ mask set:
The IRQ mask register enables interrupt requests for corresponding interrupt sources.
As its bits might be changed by different software tasks,
the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to irq_raw.
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82874
Address@gxc_pfifo1_config : 0x07d828f4
Address@gxc_pfifo2_config : 0x07d82974
Address@gxc_pfifo3_config : 0x07d829f4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
nempty_prio_7
not empty prio7 IRQ
6 "0"
nempty_prio_6
not empty prio6 IRQ
5 "0"
nempty_prio_5
not empty prio5 IRQ
4 "0"
nempty_prio_4
not empty prio4 IRQ
3 "0"
nempty_prio_3
not empty prio3 IRQ
2 "0"
nempty_prio_2
not empty prio2 IRQ
1 "0"
nempty_prio_1
not empty prio1 IRQ
0 "0"
nempty_prio_0
not empty prio0 IRQ


gxc_pfifo_config_irq_mask_rst
gxc_pfifo_config IRQ mask reset:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows bit number of the lowest active bit in irq_masked or 8 when no bit is set.
R/W
0x00000000
Address@gxc_pfifo0_config : 0x07d82878
Address@gxc_pfifo1_config : 0x07d828f8
Address@gxc_pfifo2_config : 0x07d82978
Address@gxc_pfifo3_config : 0x07d829f8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
nempty_prio_7
not empty prio7 IRQ
6 "0"
nempty_prio_6
not empty prio6 IRQ
5 "0"
nempty_prio_5
not empty prio5 IRQ
4 "0"
nempty_prio_4
not empty prio4 IRQ
3 "0"
nempty_prio_3
not empty prio3 IRQ
2 "0"
nempty_prio_2
not empty prio2 IRQ
1 "0"
nempty_prio_1
not empty prio1 IRQ
0 "0"
nempty_prio_0
not empty prio0 IRQ



Base Address Area: gxc_phy_ctrl0, gxc_phy_ctrl1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_int_phy_ctrl_led_cfg
1 4 R/W gxc_int_phy_ctrl_led_blink_cfg01
2 8 R/W gxc_int_phy_ctrl_led_blink_seq01
3 c R/W gxc_int_phy_ctrl_led_blink_cfg23
4 10 R/W gxc_int_phy_ctrl_led_blink_seq23
5 14 R/W gxc_int_phy_ctrl_led0_cfg
6 18 R/W gxc_int_phy_ctrl_led1_cfg
7 1c R/W gxc_int_phy_ctrl_led2_cfg
8 20 R/W gxc_int_phy_ctrl_led3_cfg
9 24 R/W gxc_int_phy_ctrl_led
a 28 R/W gxc_int_phy_ctrl_enhanced_link_detection0
b 2c R/W gxc_int_phy_ctrl_enhanced_link_detection1
c-f 30-3c -  reserved

gxc_int_phy_ctrl_led_cfg
PHY global LED config and status register
R/W
0x00000001
Address@gxc_phy_ctrl0 : 0x07d82a00
Address@gxc_phy_ctrl1 : 0x07d82a40
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 "0"
man3
manual value 3
10 "0"
man2
manual value 2
9 "0"
man1
manual value 1
8 "0"
man0
manual value 0
7 - 6 0
-
 reserved
5 - 4 -
speed_ro
Read only speed status as in external_config.config_link_mode.link_mode_out
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
11: undefined (in case of select of undefined input)
3 -
link_ro
Read only link status as in external_config.config_link_mode.link_mode_out
1: link up
0: link down
2 -
duplex_ro
Read only duplex status as in external_config.config_link_mode.link_mode_out
1: full duplex
0: half duplex
1 -
rx_tx_active_ro
Read only: shows activity on receive or transmit line.
Active when (rx_dv | (tx_en & link)) for 130ms
0 "1"
legacy_enable
use legacy mode as defined in register gxc_int_phy_ctrl_led.


gxc_int_phy_ctrl_led_blink_cfg01
Blinking config register for LED0 and LED1
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a04
Address@gxc_phy_ctrl1 : 0x07d82a44
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 8 "0000"
blink_len
Length of blink sequence
 0000: blink disabled, blink phase = blink_seq[0]
 0001: use bits 0..1 of blink_seq
 0010: use bits 0..2 of blink_seq
        ...
 1111: use bits 0..15 of blink_seq
7 - 4 0
-
 reserved
3 - 0 "0000"
period
Blinking period in steps of 50ms
  0: 50ms
 15: 400ms


gxc_int_phy_ctrl_led_blink_seq01
Blinking sequence register for LED0 and LED1
R/W
0x00000001
Address@gxc_phy_ctrl0 : 0x07d82a08
Address@gxc_phy_ctrl1 : 0x07d82a48
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x1
val
Bits of blink sequence


gxc_int_phy_ctrl_led_blink_cfg23
Blinking config register for LED2 and LED3
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a0c
Address@gxc_phy_ctrl1 : 0x07d82a4c
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 8 "0000"
blink_len
Length of blink sequence
 0000: blink disabled, blink phase = blink_seq[0]
 0001: use bits 0..1 of blink_seq
 0010: use bits 0..2 of blink_seq
        ...
 1111: use bits 0..15 of blink_seq
7 - 4 0
-
 reserved
3 - 0 "0000"
period
Blinking period in steps of 50ms
  0: 50ms
 15: 400ms


gxc_int_phy_ctrl_led_blink_seq23
Blinking sequence register for LED2 and LED3
R/W
0x00000001
Address@gxc_phy_ctrl0 : 0x07d82a10
Address@gxc_phy_ctrl1 : 0x07d82a50
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x1
val
Bits of blink sequence


gxc_int_phy_ctrl_led0_cfg
 PHY LED0 config register
 Each LED can be configured with 2 values for low and high blink-phase.
 The value defines a combination of input signals according to the following table:
value act link dup sp10 sp100 sp1000 description
----- --- ---- --- ---- ----- ------ -----------
0: - - - - - - no condition, always 0
1: - - - - - - no condition, always 1
2: - - - - - - manual value man0
3: - - - - - - manual value man1
4: - - - - - - manual value man2
5: - - - - - - manual value man3
6: - - - 1 0 0 speed10
7: - - - 0 1 1 not speed10 (speed100 or speed1000)
8: - - - 0 1 0 speed100
9: - - - 1 0 1 not speed100 (speed10 or speed1000)
10: - - - 0 0 1 speed1000
11: - - - 1 1 0 not speed1000 (speed10 or speed100)
12: - - 0 - - - half duplex
13: - - 0 1 0 0 half duplex and speed10
14: - - 0 0 1 1 half duplex and not speed10 (speed100 or speed1000)
15: - - 0 0 1 0 half duplex and speed100
16: - - 0 1 0 1 half duplex and not speed100 (speed10 or speed1000)
17: - - 0 0 0 1 half duplex and speed1000
18: - - 0 1 1 0 half duplex and not speed1000 (speed10 or speed100)
19: - - 1 - - - full duplex
20: - - 1 1 0 0 full duplex and speed10
21: - - 1 0 1 1 full duplex and not speed10 (speed100 or speed1000)
22: - - 1 0 1 0 full duplex and speed100
23: - - 1 1 0 1 full duplex and not speed100 (speed10 or speed1000)
24: - - 1 0 0 1 full duplex and speed1000
25: - - 1 1 1 0 full duplex and not speed1000 (speed10 or speed100)
26: - 0 - - - - no link
27: - 1 - - - - link = 1
28: - 1 - 1 0 0 link and speed10
29: - 1 - 0 1 1 link and not speed10 (speed100 or speed1000)
30: - 1 - 0 1 0 link and speed100
31: - 1 - 1 0 1 link and not speed100 (speed10 or speed1000)
32: - 1 - 0 0 1 link and speed1000
33: - 1 - 1 1 0 link and not speed1000 (speed10 or speed100)
34: - 1 0 - - - link and half duplex
35: - 1 0 1 0 0 link and half duplex and speed10
36: - 1 0 0 1 1 link and half duplex and not speed10 (speed100 or speed1000)
37: - 1 0 0 1 0 link and half duplex and speed100
38: - 1 0 1 0 1 link and half duplex and not speed100 (speed10 or speed1000)
39: - 1 0 0 0 1 link and half duplex and speed1000
40: - 1 0 1 1 0 link and half duplex and not speed1000 (speed10 or speed100)
41: - 1 1 - - - link and full duplex
42: - 1 1 1 0 0 link and full duplex and speed10
43: - 1 1 0 1 1 link and full duplex and not speed10 (speed100 or speed1000)
44: - 1 1 0 1 0 link and full duplex and speed100
45: - 1 1 1 0 1 link and full duplex and not speed100 (speed10 or speed1000)
46: - 1 1 0 0 1 link and full duplex and speed1000
47: - 1 1 1 1 0 link and full duplex and not speed1000 (speed10 or speed100)
48: 0 - - - - - activity = 0
49: 0 - - 1 0 0 no activity and speed10
50: 0 - - 0 1 1 no activity and not speed10 (speed100 or speed1000)
51: 0 - - 0 1 0 no activity and speed100
52: 0 - - 1 0 1 no activity and not speed100 (speed10 or speed1000)
53: 0 - - 0 0 1 no activity and speed1000
54: 0 - - 1 1 0 no activity and not speed1000 (speed10 or speed100)
55: 0 - 0 - - - no activity and half duplex
56: 0 - 0 1 0 0 no activity and half duplex and speed10
57: 0 - 0 0 1 1 no activity and half duplex and not speed10 (speed100 or speed1000)
58: 0 - 0 0 1 0 no activity and half duplex and speed100
59: 0 - 0 1 0 1 no activity and half duplex and not speed100 (speed10 or speed1000)
60: 0 - 0 0 0 1 no activity and half duplex and speed1000
61: 0 - 0 1 1 0 no activity and half duplex and not speed1000 (speed10 or speed100)
62: 0 - 1 - - - no activity and full duplex
63: 0 - 1 1 0 0 no activity and full duplex and speed10
64: 0 - 1 0 1 1 no activity and full duplex and not speed10 (speed100 or speed1000)
65: 0 - 1 0 1 0 no activity and full duplex and speed100
66: 0 - 1 1 0 1 no activity and full duplex and not speed100 (speed10 or speed1000)
67: 0 - 1 0 0 1 no activity and full duplex and speed1000
68: 0 - 1 1 1 0 no activity and full duplex and not speed1000 (speed10 or speed100)
69: 0 1 - - - - no activity and link
70: 0 1 - 1 0 0 no activity and link and speed10
71: 0 1 - 0 1 1 no activity and link and not speed10 (speed100 or speed1000)
72: 0 1 - 0 1 0 no activity and link and speed100
73: 0 1 - 1 0 1 no activity and link and not speed100 (speed10 or speed1000)
74: 0 1 - 0 0 1 no activity and link and speed1000
75: 0 1 - 1 1 0 no activity and link and not speed1000 (speed10 or speed100)
76: 0 1 0 - - - no activity and link and half duplex
77: 0 1 0 1 0 0 no activity and link and half duplex and speed10
78: 0 1 0 0 1 1 no activity and link and half duplex and not speed10 (speed100 or speed1000)
79: 0 1 0 0 1 0 no activity and link and half duplex and speed100
80: 0 1 0 1 0 1 no activity and link and half duplex and not speed100 (speed10 or speed1000)
81: 0 1 0 0 0 1 no activity and link and half duplex and speed1000
82: 0 1 0 1 1 0 no activity and link and half duplex and not speed1000 (speed10 or speed100)
83: 0 1 1 - - - no activity and link and full duplex
84: 0 1 1 1 0 0 no activity and link and full duplex and speed10
85: 0 1 1 0 1 1 no activity and link and full duplex and not speed10 (speed100 or speed1000)
86: 0 1 1 0 1 0 no activity and link and full duplex and speed100
87: 0 1 1 1 0 1 no activity and link and full duplex and not speed100 (speed10 or speed1000)
88: 0 1 1 0 0 1 no activity and link and full duplex and speed1000
89: 0 1 1 1 1 0 no activity and link and full duplex and not speed1000 (speed10 or speed100)
90: 1 - - - - - activity = 1
91: 1 - - 1 0 0 activity and speed10
92: 1 - - 0 1 1 activity and not speed10 (speed100 or speed1000)
93: 1 - - 0 1 0 activity and speed100
94: 1 - - 1 0 1 activity and not speed100 (speed10 or speed1000)
95: 1 - - 0 0 1 activity and speed1000
96: 1 - - 1 1 0 activity and not speed1000 (speed10 or speed100)
97: 1 - 0 - - - activity and half duplex
98: 1 - 0 1 0 0 activity and half duplex and speed10
99: 1 - 0 0 1 1 activity and half duplex and not speed10 (speed100 or speed1000)
100: 1 - 0 0 1 0 activity and half duplex and speed100
101: 1 - 0 1 0 1 activity and half duplex and not speed100 (speed10 or speed1000)
102: 1 - 0 0 0 1 activity and half duplex and speed1000
103: 1 - 0 1 1 0 activity and half duplex and not speed1000 (speed10 or speed100)
104: 1 - 1 - - - activity and full duplex
105: 1 - 1 1 0 0 activity and full duplex and speed10
106: 1 - 1 0 1 1 activity and full duplex and not speed10 (speed100 or speed1000)
107: 1 - 1 0 1 0 activity and full duplex and speed100
108: 1 - 1 1 0 1 activity and full duplex and not speed100 (speed10 or speed1000)
109: 1 - 1 0 0 1 activity and full duplex and speed1000
110: 1 - 1 1 1 0 activity and full duplex and not speed1000 (speed10 or speed100)
111: 1 1 - - - - activity and link
112: 1 1 - 1 0 0 activity and link and speed10
113: 1 1 - 0 1 1 activity and link and not speed10 (speed100 or speed1000)
114: 1 1 - 0 1 0 activity and link and speed100
115: 1 1 - 1 0 1 activity and link and not speed100 (speed10 or speed1000)
116: 1 1 - 0 0 1 activity and link and speed1000
117: 1 1 - 1 1 0 activity and link and not speed1000 (speed10 or speed100)
118: 1 1 0 - - - activity and link and half duplex
119: 1 1 0 1 0 0 activity and link and half duplex and speed10
120: 1 1 0 0 1 1 activity and link and half duplex and not speed10 (speed100 or speed1000)
121: 1 1 0 0 1 0 activity and link and half duplex and speed100
122: 1 1 0 1 0 1 activity and link and half duplex and not speed100 (speed10 or speed1000)
123: 1 1 0 0 0 1 activity and link and half duplex and speed1000
124: 1 1 0 1 1 0 activity and link and half duplex and not speed1000 (speed10 or speed100)
125: 1 1 1 - - - activity and link and full duplex
126: 1 1 1 1 0 0 activity and link and full duplex and speed10
127: 1 1 1 0 1 1 activity and link and full duplex and not speed10 (speed100 or speed1000)
128: 1 1 1 0 1 0 activity and link and full duplex and speed100
129: 1 1 1 1 0 1 activity and link and full duplex and not speed100 (speed10 or speed1000)
130: 1 1 1 0 0 1 activity and link and full duplex and speed1000
131: 1 1 1 1 1 0 activity and link and full duplex and not speed1000 (speed10 or speed100)
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a14
Address@gxc_phy_ctrl1 : 0x07d82a54
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
blink_low_condition
blink low condition (s. table at led0_cfg register description)
7 - 0 "00000000"
blink_high_condition
blink high condition (s. table at led0_cfg register description)


gxc_int_phy_ctrl_led1_cfg
PHY LED1 config register
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a18
Address@gxc_phy_ctrl1 : 0x07d82a58
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
blink_low_condition
blink low condition (s. table at led0_cfg register description)
7 - 0 "00000000"
blink_high_condition
blink high condition (s. table at led0_cfg register description)


gxc_int_phy_ctrl_led2_cfg
PHY LED2 config register
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a1c
Address@gxc_phy_ctrl1 : 0x07d82a5c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
blink_low_condition
blink low condition (s. table at led0_cfg register description)
7 - 0 "00000000"
blink_high_condition
blink high condition (s. table at led0_cfg register description)


gxc_int_phy_ctrl_led3_cfg
PHY LED3 config register
R/W
0x00000000
Address@gxc_phy_ctrl0 : 0x07d82a20
Address@gxc_phy_ctrl1 : 0x07d82a60
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
blink_low_condition
blink low condition (s. table at led0_cfg register description)
7 - 0 "00000000"
blink_high_condition
blink high condition (s. table at led0_cfg register description)


gxc_int_phy_ctrl_led
Legacy PHY LED config and status register
This register is only active, if led_cfg-legacy_enable is set.
R/W
0x00004000
Address@gxc_phy_ctrl0 : 0x07d82a24
Address@gxc_phy_ctrl1 : 0x07d82a64
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 12 "0100"
interval
flashing interval in 10 ms steps, only valid in modes b10 and  b11
0..15 = 10..160 ms
Note:
   For simulation and test purpose interval step is 1us instead of 10ms when
   quick_count is used.
11 - 10 0
-
 reserved
9 - 8 "00"
mode
flashing mode:
 00: Disabled
LED0/1: programmable by led0,led1 bits. Default: Off.
 01:
Static
LED0=PHY.link_status
LED1=PHY.receive_activity | PHY.transmit_activity
 10:

Flashing
LED0=PHY.link
LED1=PHY.receive_activity | PHY.transmit_activity,
if (PHY.receive_activity | transmit_activity)==1 then LED1 is inverted in flash intervals).
 11:
Combined
LED0=off: no link, LED0=on: link, no activity, LED0 toggeling: link, activity
LED1=off
Note:
   On means high-driven.
   Off means low-driven.
7 "0"
led1
In mode '00' this bit can be used to control LED1 manually (0:off, 1:on).
In other modes this bit is not writable and shows calculated signal from PHY_LED statemachine for LED1.
6 "0"
led0
Same as led1 for LED0.
5 - 4 -
speed_ro
Read only speed status as in external_config.config_link_mode.link_mode_out
00: 10 Mbit
01: 100 Mbit
10: 1 Gbit
11: undefined (in case of select of undefined input)
3 -
link_ro
Read only link status as in external_config.config_link_mode.link_mode_out
1: link up
0: link down
2 -
duplex_ro
Read only duplex status as in external_config.config_link_mode.link_mode_out
1: full duplex
0: half duplex
1 0
-
 reserved
0 -
rx_tx_active_ro
Read only: shows activity on receive or transmit line.
Active when (rx_dv | (tx_en & link)) for 130ms


gxc_int_phy_ctrl_enhanced_link_detection0
Enhanced link detection config register0:
Enhanced link detection is necessary with old PHYs, that do not support proper link down detection.
At these PHYs a broken link can be detected according to RXER, FCR, DRE and CRX.
R/W
0x00100000
Address@gxc_phy_ctrl0 : 0x07d82a28
Address@gxc_phy_ctrl1 : 0x07d82a68
Bits Reset value Name Description
31 -
eld_bad_link_ro
status of enhanced link detection (read only)
30 - 24 0
-
 reserved
23 - 20 "0001"
sub
Value subtracted in case of no error
19 - 0 -
counter_ro
Actual eld-counter value (read only):
Once per RXC incoming errors are evaluated and
counter is increased by add in case of an error or decreased by sub otherwise.
Counter can be reset by xPEC using xpec_statcfg or xmac_config_shared register.


gxc_int_phy_ctrl_enhanced_link_detection1
Enhanced link detection config register1:
Enhanced link detection is necessary with old PHYs, that do not support proper link down detection.
At these PHYs a broken link can be detected according to RXER, FCR, DRE and CRX.
R/W
0x01000800
Address@gxc_phy_ctrl0 : 0x07d82a2c
Address@gxc_phy_ctrl1 : 0x07d82a6c
Bits Reset value Name Description
31 - 20 0x10
add
Value added in case of an error
19 - 0 0x800
threshold
Threshold to compare with counter:
Set bad_link if counter>threshold, reset bad_link by XC-software.



Base Address Area: gxc_sys_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R gxc_sys_ctrl_mii0_in
1 4 R/W gxc_sys_ctrl_mii0_oe
2 8 R/W gxc_sys_ctrl_mii0_piomode
3 c R/W gxc_sys_ctrl_mii0_pioout
4 10 R gxc_sys_ctrl_mii1_in
5 14 R/W gxc_sys_ctrl_mii1_oe
6 18 R/W gxc_sys_ctrl_mii1_piomode
7 1c R/W gxc_sys_ctrl_mii1_pioout
8 20 R gxc_sys_ctrl_rmii0_in
9 24 R/W gxc_sys_ctrl_rmii0_oe
a 28 R/W gxc_sys_ctrl_rmii0_piomode
b 2c R/W gxc_sys_ctrl_rmii0_pioout
c 30 R gxc_sys_ctrl_rmii1_in
d 34 R/W gxc_sys_ctrl_rmii1_oe
e 38 R/W gxc_sys_ctrl_rmii1_piomode
f 3c R/W gxc_sys_ctrl_rmii1_pioout
10 40 R gxc_sys_ctrl_rgmii0_in
11 44 R/W gxc_sys_ctrl_rgmii0_oe
12 48 R/W gxc_sys_ctrl_rgmii0_piomode
13 4c R/W gxc_sys_ctrl_rgmii0_pioout
14 50 R gxc_sys_ctrl_rgmii1_in
15 54 R/W gxc_sys_ctrl_rgmii1_oe
16 58 R/W gxc_sys_ctrl_rgmii1_piomode
17 5c R/W gxc_sys_ctrl_rgmii1_pioout
18 60 R gxc_sys_ctrl_sgmii0_in
19 64 R gxc_sys_ctrl_sgmii1_in
1a-1f 68-7c -  reserved
20 80 R/W gxc_sys_ctrl_link_mode0_config
21 84 R/W gxc_sys_ctrl_link_mode0_status
22 88 R/W gxc_sys_ctrl_link_mode1_config
23 8c R/W gxc_sys_ctrl_link_mode1_status
24 90 R/W gxc_sys_ctrl_gpec_rx_frame_err_mii_err_counter
25 94 R/W gxc_sys_ctrl_gpec_rx_frwd_err_link_down_counter
26 98 R/W gxc_sys_ctrl_gpec_rx_proc_err_counter
27 9c -  reserved
28 a0 R/W gxc_sys_ctrl_gmac_rpu0_counter_0
29 a4 R/W gxc_sys_ctrl_gmac_rpu0_counter_1
2a a8 R/W gxc_sys_ctrl_gmac_rpu1_counter_0
2b ac R/W gxc_sys_ctrl_gmac_rpu1_counter_1
2c b0 R/W gxc_sys_ctrl_swap
2d b4 R/W gxc_sys_ctrl_io_polarity
2e b8 R/W gxc_sys_ctrl_rxtx_data_bitswap
2f bc R/W gxc_sys_ctrl_txclk_sync
30 c0 R/W gxc_sys_ctrl_miimu0
31 c4 R/W gxc_sys_ctrl_miimu1
32 c8 R/W gxc_sys_ctrl_miimu_cfg
33 cc R/W gxc_sys_ctrl_miimu_sw
34 d0 R/W gxc_sys_ctrl_intram_prio
35 d4 R/W gxc_sys_ctrl_irq_raw
36 d8 R/W gxc_sys_ctrl_irq_masked
37 dc R/W gxc_sys_ctrl_irq_mask_set
38 e0 R/W gxc_sys_ctrl_irq_mask_rst
39-3f e4-fc -  reserved

gxc_sys_ctrl_mii0_in
PIO mode input register of MII0 and GPIO0
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b00
Bits Name Description
31 - 20 -
 reserved
19 gpio3
gxc0_io3 pin
18 gpio2
gxc0_io2 pin
17 gpio1
gxc0_io1 pin
16 gpio0
gxc0_io0 pin
15 - 13 -
 reserved
12 mii_txsfd
mii0_txsfd pin
11 mii_rxsfd
mii0_rxsfd pin
10 mii_txclk
mii0_txclk pin
9 mii_link
mii0_link pin
8 mii_col
mii0_col pin
7 mii_crs
mii0_crs pin
6 mii_rxer
mii0_rxer pin
5 mii_rxdv
mii0_rxdv pin
4 mii_rxd3
mii0_rxd3 pin
3 mii_rxd2
mii0_rxd2 pin
2 mii_rxd1
mii0_rxd1 pin
1 mii_rxd0
mii0_rxd0 pin
0 mii_rxclk
mii0_rxclk pin


gxc_sys_ctrl_mii0_oe
Output enable register of MII0 and GPIO0
This register defines the output enable signal of the related module pin.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b04
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc0_io3 pin
18 "0"
gpio2
gxc0_io2 pin
17 "0"
gpio1
gxc0_io1 pin
16 "0"
gpio0
gxc0_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii0_txer pin
4 "0"
mii_txen
mii0_txen pin
3 "0"
mii_txd3
mii0_txd3 pin
2 "0"
mii_txd2
mii0_txd2 pin
1 "0"
mii_txd1
mii0_txd1 pin
0 "0"
mii_txd0
mii0_txd0 pin


gxc_sys_ctrl_mii0_piomode
PIO mode enable register of MII0 and GPIO0
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b08
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc0_io3 pin
18 "0"
gpio2
gxc0_io2 pin
17 "0"
gpio1
gxc0_io1 pin
16 "0"
gpio0
gxc0_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii0_txer pin
4 "0"
mii_txen
mii0_txen pin
3 "0"
mii_txd3
mii0_txd3 pin
2 "0"
mii_txd2
mii0_txd2 pin
1 "0"
mii_txd1
mii0_txd1 pin
0 "0"
mii_txd0
mii0_txd0 pin


gxc_sys_ctrl_mii0_pioout
PIO mode output value register of MII0 and GPIO0
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b0c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc0_io3 pin
18 "0"
gpio2
gxc0_io2 pin
17 "0"
gpio1
gxc0_io1 pin
16 "0"
gpio0
gxc0_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii0_txer pin
4 "0"
mii_txen
mii0_txen pin
3 "0"
mii_txd3
mii0_txd3 pin
2 "0"
mii_txd2
mii0_txd2 pin
1 "0"
mii_txd1
mii0_txd1 pin
0 "0"
mii_txd0
mii0_txd0 pin


gxc_sys_ctrl_mii1_in
PIO mode input register of MII1 and GPIO1
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b10
Bits Name Description
31 - 20 -
 reserved
19 gpio3
gxc0_io3 pin
18 gpio2
gxc0_io2 pin
17 gpio1
gxc0_io1 pin
16 gpio0
gxc0_io0 pin
15 - 13 -
 reserved
12 mii_txsfd
mii0_txsfd pin
11 mii_rxsfd
mii0_rxsfd pin
10 mii_txclk
mii1_txclk pin
9 mii_link
mii1_link pin
8 mii_col
mii1_col pin
7 mii_crs
mii1_crs pin
6 mii_rxer
mii1_rxer pin
5 mii_rxdv
mii1_rxdv pin
4 mii_rxd3
mii1_rxd3 pin
3 mii_rxd2
mii1_rxd2 pin
2 mii_rxd1
mii1_rxd1 pin
1 mii_rxd0
mii1_rxd0 pin
0 mii_rxclk
mii1_rxclk pin


gxc_sys_ctrl_mii1_oe
Output enable register of MII1 and GPIO1
This register defines the output enable signal of the related module pin.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b14
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc1_io3 pin
18 "0"
gpio2
gxc1_io2 pin
17 "0"
gpio1
gxc1_io1 pin
16 "0"
gpio0
gxc1_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii1_txer pin
4 "0"
mii_txen
mii1_txen pin
3 "0"
mii_txd3
mii1_txd3 pin
2 "0"
mii_txd2
mii1_txd2 pin
1 "0"
mii_txd1
mii1_txd1 pin
0 "0"
mii_txd0
mii1_txd0 pin


gxc_sys_ctrl_mii1_piomode
PIO mode enable register of MII1 and GPIO1
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b18
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc1_io3 pin
18 "0"
gpio2
gxc1_io2 pin
17 "0"
gpio1
gxc1_io1 pin
16 "0"
gpio0
gxc1_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii1_txer pin
4 "0"
mii_txen
mii1_txen pin
3 "0"
mii_txd3
mii1_txd3 pin
2 "0"
mii_txd2
mii1_txd2 pin
1 "0"
mii_txd1
mii1_txd1 pin
0 "0"
mii_txd0
mii1_txd0 pin


gxc_sys_ctrl_mii1_pioout
PIO mode output value register of MII1 and GPIO1
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b1c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
gpio3
gxc1_io3 pin
18 "0"
gpio2
gxc1_io2 pin
17 "0"
gpio1
gxc1_io1 pin
16 "0"
gpio0
gxc1_io0 pin
15 - 6 0
-
 reserved
5 "0"
mii_txer
mii1_txer pin
4 "0"
mii_txen
mii1_txen pin
3 "0"
mii_txd3
mii1_txd3 pin
2 "0"
mii_txd2
mii1_txd2 pin
1 "0"
mii_txd1
mii1_txd1 pin
0 "0"
mii_txd0
mii1_txd0 pin


gxc_sys_ctrl_rmii0_in
PIO mode input register of RMII0
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b20
Bits Name Description
31 - 8 -
 reserved
7 rmii_txsfd
rmii0_txsfd pin
6 rmii_rxsfd
rmii0_rxsfd pin
5 rmii_link
rmii0_link pin
4 rmii_rxer
rmii0_rxer pin
3 rmii_crsdv
rmii0_crsdv pin
2 rmii_rxd1
rmii0_rxd1 pin
1 rmii_rxd0
rmii0_rxd0 pin
0 rmii_refclk
rmii0_refclk pin


gxc_sys_ctrl_rmii0_oe
Output enable register of RMII0
This register defines the output enable signal of the related module pin.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b24
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii0_txen pin
1 "0"
rmii_txd1
rmii0_txd1 pin
0 "0"
rmii_txd0
rmii0_txd0 pin


gxc_sys_ctrl_rmii0_piomode
PIO mode enable register of RMII0
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b28
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii0_txen pin
1 "0"
rmii_txd1
rmii0_txd1 pin
0 "0"
rmii_txd0
rmii0_txd0 pin


gxc_sys_ctrl_rmii0_pioout
PIO mode output value register of RMII0
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b2c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii0_txen pin
1 "0"
rmii_txd1
rmii0_txd1 pin
0 "0"
rmii_txd0
rmii0_txd0 pin


gxc_sys_ctrl_rmii1_in
PIO mode input register of RMII1
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b30
Bits Name Description
31 - 8 -
 reserved
7 rmii_txsfd
rmii1_txsfd pin
6 rmii_rxsfd
rmii1_rxsfd pin
5 rmii_link
rmii1_link pin
4 rmii_rxer
rmii1_rxer pin
3 rmii_crsdv
rmii1_crsdv pin
2 rmii_rxd1
rmii1_rxd1 pin
1 rmii_rxd0
rmii1_rxd0 pin
0 rmii_refclk
rmii1_refclk pin


gxc_sys_ctrl_rmii1_oe
Output enable register of RMII1
This register defines the output enable signal of the related module pin.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b34
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii1_txen pin
1 "0"
rmii_txd1
rmii1_txd1 pin
0 "0"
rmii_txd0
rmii1_txd0 pin


gxc_sys_ctrl_rmii1_piomode
PIO mode enable register of RMII1
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b38
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii1_txen pin
1 "0"
rmii_txd1
rmii1_txd1 pin
0 "0"
rmii_txd0
rmii1_txd0 pin


gxc_sys_ctrl_rmii1_pioout
PIO mode output value register of RMII1
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b3c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
rmii_txen
rmii1_txen pin
1 "0"
rmii_txd1
rmii1_txd1 pin
0 "0"
rmii_txd0
rmii1_txd0 pin


gxc_sys_ctrl_rgmii0_in
PIO mode input register of RGMII0
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b40
Bits Name Description
31 - 9 -
 reserved
8 rgmii_link
rgmii_link pin
7 rgmii_txsfd
rgmii_txsfd pin
6 rgmii_rxsfd
rgmii_rxsfd pin
5 rgmii_rxctl
rgmii_rxctl pin
4 rgmii_rxd3
rgmii_rxd3 pin
3 rgmii_rxd2
rgmii_rxd2 pin
2 rgmii_rxd1
rgmii_rxd1 pin
1 rgmii_rxd0
rgmii_rxd0 pin
0 rgmii_rxc
rgmii_rxc pin


gxc_sys_ctrl_rgmii0_oe
Output enable register of RGMII0
This register defines the output enable signal of the related module pin.
Bits 9:6 are only valid in piomode and overwrite the value in SR-statcfg0[7:4].
Bits 5:0 of this register are directly connected to module pins, independent on piomode.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b44
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_rgmii0_piomode
PIO mode enable register of RGMII0
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b48
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_rgmii0_pioout
PIO mode output value register of RGMII0
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b4c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_rgmii1_in
PIO mode input register of RGMII1
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b50
Bits Name Description
31 - 9 -
 reserved
8 rgmii_link
rgmii_link pin
7 rgmii_txsfd
rgmii_txsfd pin
6 rgmii_rxsfd
rgmii_rxsfd pin
5 rgmii_rxctl
rgmii_rxctl pin
4 rgmii_rxd3
rgmii_rxd3 pin
3 rgmii_rxd2
rgmii_rxd2 pin
2 rgmii_rxd1
rgmii_rxd1 pin
1 rgmii_rxd0
rgmii_rxd0 pin
0 rgmii_rxc
rgmii_rxc pin


gxc_sys_ctrl_rgmii1_oe
Output enable register of RGMII1
This register defines the output enable signal of the related module pin.
Bits 9:6 are only valid in piomode and overwrite the value in SR-statcfg1[7:4].
Bits 5:0 of this register are directly connected to module pins, independent on piomode.
After reset all oe bits are disabled, hence these bits should be activated by software.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b54
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_rgmii1_piomode
PIO mode enable register of RGMII1
This register defines whether a module pin is driven by the module function or set directly by the pioout register.
0: PIO mode off = module outputs are controlled by HW
1: PIO mode on  = module outputs are controlled by pioout register.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b58
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_rgmii1_pioout
PIO mode output value register of RGMII1
This register defines the output value of the related module pin.
These register bits are only active, if the related piomode bit is set.
Values set here might be delayed by some clock cylces before external value changes.
R/W
0x00000000
Address : 0x07d82b5c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rgmii_txctl
rgmii_txctl pin
4 "0"
rgmii_txd3
rgmii_txd3 pin
3 "0"
rgmii_txd2
rgmii_txd2 pin
2 "0"
rgmii_txd1
rgmii_txd1 pin
1 "0"
rgmii_txd0
rgmii_txd0 pin
0 "0"
rgmii_txc
rgmii_txc pin


gxc_sys_ctrl_sgmii0_in
PIO mode input register of SGMII0
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b60
Bits Name Description
31 - 3 -
 reserved
2 sgmii_link
SGMII link signal from PHY via extra pad
1 sgmii_rxsfd
SGMII rxsfd timestamp pulse from PHY via extra pad
0 sgmii_txsfd
SGMII txsfd timestamp pulse from PHY via extra pad


gxc_sys_ctrl_sgmii1_in
PIO mode input register of SGMII1
This register is read only and shows the input of the related module pin.
It is intended for PIO-mode or simple interconnect test of the module.
Input values shown here might be delayed by some clock cylces.
R
Address : 0x07d82b64
Bits Name Description
31 - 3 -
 reserved
2 sgmii_link
SGMII link signal from PHY via extra pad
1 sgmii_rxsfd
SGMII rxsfd timestamp pulse from PHY via extra pad
0 sgmii_txsfd
SGMII txsfd timestamp pulse from PHY via extra pad


gxc_sys_ctrl_link_mode0_config
GMAC0 configuration for external connection
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x07d82b80
Bits Reset value Name Description
31 "0"
rgmii_delay_txc_wm
Write mask of rgmii_delay_txc
30 - 28 "000"
ext_mode_wm
Write mask of ext_mode
27 "0"
link_mode_man_duplex_wm
Write mask of link_mode_man_duplex
26 "0"
link_mode_man_link_wm
Write mask of link_mode_man_link
25 - 24 "00"
link_mode_man_speed_wm
Write mask of link_mode_man_speed
23 "0"
auto_down_man_up_wm
Write mask of auto_down_man_up
22 "0"
inband_status_filter_dis_wm
Write mask of inband_status_filter_dis
21 - 20 "00"
sel_duplex_wm
Write mask of sel_duplex
19 - 18 "00"
sel_link_wm
Write mask of sel_link
17 - 16 "00"
sel_speed_wm
Write mask of sel_speed
15 "0"
rgmii_delay_txc
Delay RGMII_TXC by 2ns.
0: external RGMII_TXC changes with RGMII_TXD/TXCTL (standard compliant, but requires external delay)
1: external RGMII_TXC changes 2ns after RGMII_TXD/TXCTL (no external delay needed)
14 - 12 "000"
ext_mode
Mode of external interface:
000: nibble FIFO reset (and High-Z Outputs, TBD: Konflikt mit ..._oe Registern)
010: MII mode
011: RMII mode
100: RGMII mode
101: SGMII mode
11 "0"
link_mode_man_duplex
Manually set link_mode for duplex
0: half duplex
1: full duplex
10 "0"
link_mode_man_link
Manually set link_mode for link or reactivate link in auto_down_man_up mode:
0: no link
1: link active
9 - 8 "00"
link_mode_man_speed
Manually set link_mode for speed
00: 10 MBit
01: 100 MBit
10: 1 GBit
7 "0"
auto_down_man_up
Mode to prevent link from PHY to reactivate internal link before software is ready.
If active, link from PHY (link_mode_phy_link) is ANDed with manual link (link_mode_man_link) and
manual link is automatically reset if link from PHY goes down.
To reactivate link, software must set manual link and link from PHY must be active.
Works only with automatic link from PHY (sel_link!=0).
6 "0"
inband_status_filter_dis
Disable inband status filter:
Inband status signals for link, speed and duplex are transferred in RGMII and SGMII during IFG.
0: filter inband status signals, i.e. accept new value after receiving 4 unchanged consecutive signals.
1: use inband status signals without filtering.
5 - 4 "00"
sel_duplex
Select duplex input
0: set manually (bit link_mode_man_duplex)
1: reserved
2: from RGMII or SGMII inband status (see link_mode_inband_duplex)
3 - 2 "00"
sel_link
Select link input
0: set manually (see link_mode_man_link)
1: from external pin (see link_mode_ext_in_link)
2: from RGMII or SGMII inband status (link at external PHY, see link_mode_inband_link)
3: from SGMII inband status (link of connection to PHY)
1 - 0 "00"
sel_speed
Select speed input
0: set manually (bits link_mode_man_speed)
1: reserved
2: from RGMII or SGMII inband status (see link_mode_inband_speed)
3: derived from speed of input clock TBD: also for MII


gxc_sys_ctrl_link_mode0_status
GMAC0 status of external connection
All bits are read only, writing 1 to inband_err_up_lo_mismatch resets this bit.
R/W
0x00003300
Address : 0x07d82b84
Bits Reset value Name Description
31 "0"
inband_err_up_lo_mismatch
Inband detection error was here: rxdv=0 and rxer=0 but upper and lower nibble do not match
In case of a mismatch, inband information is simply derived from bits 3:0 of received byte.
This bit is set by hardware and can be reset by writing 1 to this bit.
30 - 14 0
-
 reserved
13 - 12 "11"
link_mode_rxclk_speed
read only link_mode derived from RX_CLK
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of ext_mode_rmii or ext_mode_sgmii)
Note: This bit is independent on rx_swap.
11 "0"
link_mode_inband_duplex
read only link_mode coming from RGMII or SGMII inband detection
0: half duplex
1: full duplex
Note: This bit is independent on rx_swap.
10 "0"
link_mode_inband_link
read only link_mode coming from RGMII or SGMII inband detection
Note: In SGMII mode, this bit shows link at external PHY.
0: no link
1: link active
Note: This bit is independent on rx_swap.
9 - 8 "11"
link_mode_inband_speed
read only link_mode coming from RGMII or SGMII inband detection
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of ext_mode_mii or ext_mode_rmii or not yet detected from rx-data)
Note: These bits are independant on rx_swap.
7 0
-
 reserved
6 "0"
link_mode_ext_in_link
read only link_mode coming from external pin (depending on ext_mode)
0: no link
1: link active
Note: This bit is independent on rx_swap.
5 0
-
 reserved
4 "0"
link_mode_phy_link
read only link_mode for link from PHY (external pin or inband status)
0: no link
1: link active
Note: This bit is independant on rx_swap.
3 "0"
link_mode_out_duplex
read only link_mode for duplex as used in GMAC
0: half duplex
1: full duplex
Note: This bit is independant on rx_swap.
2 "0"
link_mode_out_link
read only link_mode for link as used in GMAC
0: no link
1: link active
Note: This bit is independant on rx_swap.
1 - 0 "00"
link_mode_out_speed
read only link_mode for speed as used in GMAC
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of select of undefined input)
Note: These bits are independant on rx_swap.


gxc_sys_ctrl_link_mode1_config
GMAC1 configuration for external connection
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x07d82b88
Bits Reset value Name Description
31 "0"
rgmii_delay_txc_wm
Write mask of rgmii_delay_txc
30 - 28 "000"
ext_mode_wm
Write mask of ext_mode
27 "0"
link_mode_man_duplex_wm
Write mask of link_mode_man_duplex
26 "0"
link_mode_man_link_wm
Write mask of link_mode_man_link
25 - 24 "00"
link_mode_man_speed_wm
Write mask of link_mode_man_speed
23 "0"
auto_down_man_up_wm
Write mask of auto_down_man_up
22 "0"
inband_status_filter_dis_wm
Write mask of inband_status_filter_dis
21 - 20 "00"
sel_duplex_wm
Write mask of sel_duplex
19 - 18 "00"
sel_link_wm
Write mask of sel_link
17 - 16 "00"
sel_speed_wm
Write mask of sel_speed
15 "0"
rgmii_delay_txc
Delay RGMII_TXC by 2ns.
0: external RGMII_TXC changes with RGMII_TXD/TXCTL (standard compliant, but requires external delay)
1: external RGMII_TXC changes 2ns after RGMII_TXD/TXCTL (no external delay needed)
14 - 12 "000"
ext_mode
Mode of external interface:
000: nibble FIFO reset (and High-Z Outputs, TBD)
010: MII mode
011: RMII mode
100: RGMII mode
101: SGMII mode
11 "0"
link_mode_man_duplex
Manually set link_mode for duplex
0: half duplex
1: full duplex
10 "0"
link_mode_man_link
Manually set link_mode for link or reactivate link in auto_down_man_up mode:
0: no link
1: link active
9 - 8 "00"
link_mode_man_speed
Manually set link_mode for speed
00: 10 MBit
01: 100 MBit
10: 1 GBit
7 "0"
auto_down_man_up
Mode to prevent link from PHY to reactivate internal link before software is ready.
If active, link from PHY (link_mode_phy_link) is ANDed with manual link (link_mode_man_link) and
manual link is automatically reset if link from PHY goes down.
To reactivate link, software must set manual link and link from PHY must be active.
Works only with automatic link from PHY (sel_link!=0).
6 "0"
inband_status_filter_dis
disable inband status filter
0: filter inband status signals, i.e. change value after detection of 10 unchanged consecutive values.
1: use inband status signals (link, speed, duplex) as detected in RGMII/SGMII IFG.
5 - 4 "00"
sel_duplex
Select duplex input
0: set manually (bit link_mode_man_duplex)
1: reserved
2: from RGMII inband status (see link_mode_inband_duplex)
3 - 2 "00"
sel_link
Select link input
0: set manually (see link_mode_man_link)
1: from external pin (see link_mode_ext_in_link)
2: from RGMII or SGMII inband status (link at external PHY, see link_mode_inband_link)
3: from SGMII inband status (link of connection to PHY)
1 - 0 "00"
sel_speed
Select speed input
0: set manually (bits link_mode_man_speed)
1: reserved
2: from RGMII or SGMII inband status (see link_mode_inband_speed)
3: derived from speed of input clock


gxc_sys_ctrl_link_mode1_status
GMAC1 status of external connection
All bits are read only, writing 1 to inband_err_up_lo_mismatch resets this bit.
R/W
0x00003300
Address : 0x07d82b8c
Bits Reset value Name Description
31 "0"
inband_err_up_lo_mismatch
Inband detection error was here: rxdv=0 and rxer=0 but upper and lower nibble do not match
In case of a mismatch, inband information is simply derived from bits 3:0 of received byte.
This bit is set by hardware and can be reset by writing 1 to this bit.
30 - 14 0
-
 reserved
13 - 12 "11"
link_mode_rxclk_speed
read only link_mode derived from RX_CLK
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of ext_mode_rmii or ext_mode_sgmii)
Note: These bits are independent on rx_swap.
11 "0"
link_mode_inband_duplex
read only link_mode coming from RGMII or SGMII inband detection
0: half duplex
1: full duplex
Note: This bit is independent on rx_swap.
10 "0"
link_mode_inband_link
read only link_mode coming from RGMII or SGMII inband detection
Note: In SGMII mode, this bit shows link at external PHY.
0: no link
1: link active
Note: This bit is independent on rx_swap.
9 - 8 "11"
link_mode_inband_speed
read only link_mode coming from RGMII or SGMII inband detection
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of ext_mode_mii or ext_mode_rmii or not yet detected from rx-data)
Note: These bits are independant on rx_swap.
7 0
-
 reserved
6 "0"
link_mode_ext_in_link
read only link_mode coming from external pin (depending on ext_mode)
0: no link
1: link active
Note: This bit is independent on rx_swap.
5 0
-
 reserved
4 "0"
link_mode_phy_link
read only link_mode for link from PHY (external pin or inband status)
0: no link
1: link active
Note: This bit is independant on rx_swap.
3 "0"
link_mode_out_duplex
read only link_mode for duplex as used in GMAC
0: half duplex
1: full duplex
Note: This bit is independant on rx_swap.
2 "0"
link_mode_out_link
read only link_mode for link as used in GMAC
0: no link
1: link active
Note: This bit is independant on rx_swap.
1 - 0 "00"
link_mode_out_speed
read only link_mode for speed as used in GMAC
00: 10 MBit
01: 100 MBit
10: 1 GBit
11: undefined (in case of select of undefined input)
Note: These bits are independant on rx_swap.


gxc_sys_ctrl_gpec_rx_frame_err_mii_err_counter
RX frame error counter and MII rxerr counters of both channels
Register is not directly writable, but bits can be deleted by writing 1 to the corresponding position.
R/W
0x00000000
Address : 0x07d82b90
Bits Reset value Name Description
31 - 24 "00000000"
mii1_mii_err_cnt
MII1 rxerr count
Counts (R)GMII errors until 0xff is reached.
(R)GMII errors are Data Reception Error, False Carrier and Carrier Extension Error.
The (R)GMII port can be selected by mii_err_cnt_sel.
This counter is independent on rx_swap.
23 - 16 "00000000"
mii1_frame_err_cnt
MII1 Frame error count
Counts frame_err_cnt pulses until 0xff is reached.
GMAC generates frame_err_cnt pulses by writing to rx_frame_err_cnt[0].
The GMAC generating the rx_frame_err_cnt pulses can be selected by frame_err_cnt_sel.
This counter is independent on rx_swap.
15 - 8 "00000000"
mii0_mii_err_cnt
MII0 rxerr count
Counts (R)GMII errors until 0xff is reached.
(R)GMII errors are Data Reception Error, False Carrier and Carrier Extension Error.
The (R)GMII port can be selected by mii_err_cnt_sel.
This counter is independent on rx_swap.
7 - 0 "00000000"
mii0_frame_err_cnt
MII0 Frame error count
Counts frame_err_cnt pulses until 0xff is reached.
GMAC generates frame_err_cnt pulses by writing to rx_frame_err_cnt[0].
The GMAC generating the rx_frame_err_cnt pulses can be selected by frame_err_cnt_sel.
This counter is independent on rx_swap.


gxc_sys_ctrl_gpec_rx_frwd_err_link_down_counter
RX forward error counter and MII link down counters of both channels.
Register is not directly writable, but bits can be deleted by writing 1 to the corresponding position.
R/W
0x00000000
Address : 0x07d82b94
Bits Reset value Name Description
31 - 24 "00000000"
mii1_link_down_cnt
MII1 link down count
Counts falling edges of link down until 0xff is reached.
The link signal is selected by link_mode1_config.sel_link.
The (R)GMII port can be selected by link_down_cnt_sel.
This counter is independent on rx_swap.
23 - 16 "00000000"
mii0_link_down_cnt
MII0 link down count
Counts falling edges of link down until 0xff is reached.
The link signal is selected by link_mode0_config.sel_link.
The (R)GMII port can be selected by link_down_cnt_sel.
This counter is independent on rx_swap.
15 - 8 "00000000"
mii1_frwd_err_cnt
MII1 Forward error count
Counts frwd_err_cnt pulses until 0xff is reached.
GMAC generates frwd_err_cnt pulses by writing to rx_frame_err_cnt[1].
The GMAC generating the rx_frame_err_cnt pulses can be selected by frwd_err_cnt_sel.
This counter is independent on rx_swap.
7 - 0 "00000000"
mii0_frwd_err_cnt
TBD MII0 Forward error count
Counts frwd_err_cnt pulses until 0xff is reached.
GMAC generates frwd_err_cnt pulses by writing to rx_frame_err_cnt[1].
The GMAC generating the rx_frame_err_cnt pulses can be selected by frwd_err_cnt_sel.
This counter is independent on rx_swap.


gxc_sys_ctrl_gpec_rx_proc_err_counter
RX processing error counter.
Register is not directly writable, but bits can be deleted by writing 1 to the corresponding position.
R/W
0x00000000
Address : 0x07d82b98
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
proc_err_cnt
Processing error count
Counts up, if gmac0.rx_frame_err_cnt[2] or gmac1.rx_frame_err_cnt[2] is set.
Counting is stopped when 0xff is reached.
This counter is independent on rx_swap and mii_err_cnt_sel. // TBD: mii_err_cnt_sel


gxc_sys_ctrl_gmac_rpu0_counter_0
GMAC_RPU0 counter_0:
This register increments (wrap around), if GMAC0 writes to its rx_frame_err_cnt.cnt0 bit.
R/W
0x00000000
Address : 0x07d82ba0
Bits Reset value Name Description
31 - 0 0x0
val
Actual value of counter


gxc_sys_ctrl_gmac_rpu0_counter_1
GMAC_RPU0 counter_1:
This register increments (wrap around), if GMAC0 writes to its rx_frame_err_cnt.cnt1 bit.
R/W
0x00000000
Address : 0x07d82ba4
Bits Reset value Name Description
31 - 0 0x0
val
Actual value of counter


gxc_sys_ctrl_gmac_rpu1_counter_0
GMAC_RPU1 counter_0:
This register increments (wrap around), if GMAC1 writes to its rx_frame_err_cnt.cnt0 bit.
R/W
0x00000000
Address : 0x07d82ba8
Bits Reset value Name Description
31 - 0 0x0
val
Actual value of counter


gxc_sys_ctrl_gmac_rpu1_counter_1
GMAC_RPU1 counter_1:
This register increments (wrap around), if GMAC1 writes to its rx_frame_err_cnt.cnt1 bit.
R/W
0x00000000
Address : 0x07d82bac
Bits Reset value Name Description
31 - 0 0x0
val
Actual value of counter


gxc_sys_ctrl_swap
Configuration of Receive and Transmit Swap of external MII/GMII/RGMII interfacs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
Change note: After netx22xx_mpw tx_swap0 and tx_swap1 are combined to tx_swap (both bits are ORed).
R/W
0x00000000
Address : 0x07d82bb0
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
link_down_cnt1_dis_wm
Write mask of link_down_cnt1_dis
24 "0"
link_down_cnt0_dis_wm
Write mask of link_down_cnt0_dis
23 "0"
mii_err_cnt1_dis_wm
Write mask of mii_err_cnt1_dis
22 "0"
mii_err_cnt0_dis_wm
Write mask of mii_err_cnt0_dis
21 "0"
frwd_err_cnt_sel_wm
Write mask of frwd_err_cnt_sel
20 "0"
frame_err_cnt_sel_wm
Write mask of frame_err_cnt_sel
19 "0"
tx_swap1_wm
Write mask of tx_swap1
18 "0"
rx_swap1_wm
Write mask of rx_swap1
17 "0"
tx_swap0_wm
Write mask of tx_swap0
16 "0"
rx_swap0_wm
Write mask of rx_swap0
15 - 10 0
-
 reserved
9 "0"
link_down_cnt1_dis
Disable counting of link_down_cnt1:
0: mii1_link_down_cnt counts at link1 down
1: mii1_link_down_cnt does not count
8 "0"
link_down_cnt0_dis
Disable counting of link_down_cnt0:
0: mii0_link_down_cnt counts at link0 down
1: mii0_link_down_cnt does not count
7 "0"
mii_err_cnt1_dis
Disable counting of mii1_mii_err_cnt:
0: mii1_mii_err_cnt counts at (R)GMII1 error
1: mii1_mii_err_cnt does not count
6 "0"
mii_err_cnt0_dis
Disable counting of mii0_mii_err_cnt:
0: mii0_mii_err_cnt counts at (R)GMII0 error
1: mii0_mii_err_cnt does not count
5 "0"
frwd_err_cnt_sel
Select frwd_err_cnt:
0: mii0_frwd_err_cnt counts via GMAC0 register, mii1_frwd_err_cnt counts via GMAC1 register
1: mii0_frwd_err_cnt counts via GMAC1 register, mii1_frwd_err_cnt counts via GMAC0 register
4 "0"
frame_err_cnt_sel
Select frame_err_cnt:
0: mii0_frame_err_cnt counts via GMAC0 register, mii1_frame_err_cnt counts via GMAC1 register
1: mii0_frame_err_cnt counts via GMAC1 register, mii1_frame_err_cnt counts via GMAC0 register
3 "0"
tx_swap1
Swap TX signals between gMACs.
If enabled, output signals from GMAC0 (RGMII_TXCLK, TXD, TXEN, TXER) are output at GMAC1 IOs.
The MII_TXCLK and COL/CRS inputs of gMAC1 are switched by tx_swap0.
Attention: Currently no hazard prevention in the moment of switching is done (TBD?).
2 "0"
rx_swap1
Swap RX signals between gMACs.
If enabled, signals from GMAC0 IOs (RXCLK, RXD, RXDV, RXER) are used in GMAC1.
Attention: Currently no hazard prevention in the moment of switching is done (TBD?).
1 "0"
tx_swap0
Swap TX signals between gMACs.
If enabled, output signals from GMAC1 (RGMII_TXCLK, TXD, TXEN, TXER) are output at GMAC0 IOs.
The MII_TXCLK and COL/CRS inputs of gMAC0 are switched by tx_swap1.
Attention: Currently no hazard prevention in the moment of switching is done (TBD?).
0 "0"
rx_swap0
Swap RX signals between gMACs.
If enabled, signals from GMAC1 IOs (RXCLK, RXD, RXDV, RXER) are used in GMAC0.
Attention: Currently no hazard prevention in the moment of switching is done (TBD?).


gxc_sys_ctrl_io_polarity
Configuration of inversion of some IOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x07d82bb4
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
inv_gmac1_txsfd_wm
Write mask of inv_gmac1_txsfd
29 "0"
inv_gmac1_rxsfd_wm
Write mask of inv_gmac1_rxsfd
28 "0"
inv_gmac1_link_wm
Write mask of inv_gmac1_link
27 "0"
inv_gmac1_gpio3_wm
Write mask of inv_gmac1_gpio3
26 "0"
inv_gmac1_gpio2_wm
Write mask of inv_gmac1_gpio2
25 "0"
inv_gmac1_gpio1_wm
Write mask of inv_gmac1_gpio1
24 "0"
inv_gmac1_gpio0_wm
Write mask of inv_gmac1_gpio0
23 0
-
 reserved
22 "0"
inv_gmac0_txsfd_wm
Write mask of inv_gmac0_txsfd
21 "0"
inv_gmac0_rxsfd_wm
Write mask of inv_gmac0_rxsfd
20 "0"
inv_gmac0_link_wm
Write mask of inv_gmac0_link
19 "0"
inv_gmac0_gpio3_wm
Write mask of inv_gmac0_gpio3
18 "0"
inv_gmac0_gpio2_wm
Write mask of inv_gmac0_gpio2
17 "0"
inv_gmac0_gpio1_wm
Write mask of inv_gmac0_gpio1
16 "0"
inv_gmac0_gpio0_wm
Write mask of inv_gmac0_gpio0
15 0
-
 reserved
14 "0"
inv_gmac1_txsfd
invert txsfd signals of gmac1
13 "0"
inv_gmac1_rxsfd
invert rxsfd signals of gmac1
12 "0"
inv_gmac1_link
invert link signals of gmac1
11 "0"
inv_gmac1_gpio3
invert incoming xc1_gpio3
10 "0"
inv_gmac1_gpio2
invert incoming xc1_gpio2
9 "0"
inv_gmac1_gpio1
invert incoming xc1_gpio1
8 "0"
inv_gmac1_gpio0
invert incoming xc1_gpio0
7 0
-
 reserved
6 "0"
inv_gmac0_txsfd
invert txsfd signals of gmac0
5 "0"
inv_gmac0_rxsfd
invert rxsfd signals of gmac0
4 "0"
inv_gmac0_link
invert link signals of gmac0
3 "0"
inv_gmac0_gpio3
invert incoming xc0_gpio3
2 "0"
inv_gmac0_gpio2
invert incoming xc0_gpio2
1 "0"
inv_gmac0_gpio1
invert incoming xc0_gpio1
0 "0"
inv_gmac0_gpio0
invert incoming xc0_gpio0


gxc_sys_ctrl_rxtx_data_bitswap
Configuration of swap of rx and tx data for better external PCB routing
Note: pio_mode rx/tx data will not be swapped
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x07d82bb8
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
bitswap_txd1_wm
Write mask of bitswap_txd1
18 "0"
bitswap_txd0_wm
Write mask of bitswap_txd0
17 "0"
bitswap_rxd1_wm
Write mask of bitswap_rxd1
16 "0"
bitswap_rxd0_wm
Write mask of bitswap_rxd0
15 - 4 0
-
 reserved
3 "0"
bitswap_txd1
bitwise swaps tx data of XC port 1
depending on ext_mode:
extmode_rmii: com_rmii1_txd[1:0]  -> com_rmii1_txd[0:1]
extmode_mii: com_mii1_txd[3:0]   -> com_mii1_txd[0:3]
extmode_rgmii: com_rgmii1_txd[3:0] -> com_rgmii1_txd[0:3]
extmode_sgmii: no bitswap
2 "0"
bitswap_txd0
bitwise swaps tx data of XC port 0
depending on ext_mode:
extmode_rmii: com_rmii0_txd[1:0]  -> com_rmii0_txd[0:1]
extmode_mii: com_mii0_txd[3:0]   -> com_mii0_txd[0:3]
extmode_rgmii: com_rgmii0_txd[3:0] -> com_rgmii0_txd[0:3]
extmode_sgmii: no bitswap
1 "0"
bitswap_rxd1
bitwise swaps rx data of XC port 1
depending on ext_mode:
extmode_rmii: com_rmii1_rxd[1:0]  -> com_rmii1_rxd[0:1]
extmode_mii: com_mii1_rxd[3:0]   -> com_mii1_rxd[0:3]
extmode_rgmii: com_rgmii1_rxd[3:0] -> com_rgmii1_rxd[0:3]
extmode_sgmii: no bitswap
0 "0"
bitswap_rxd0
bitwise swaps rx data of XC port 0
depending on ext_mode:
extmode_rmii: com_rmii0_rxd[1:0]  -> com_rmii0_rxd[0:1]
extmode_mii: com_mii0_rxd[3:0]   -> com_mii0_rxd[0:3]
extmode_rgmii: com_rgmii0_rxd[3:0] -> com_rgmii0_rxd[0:3]
extmode_sgmii: no bitswap


gxc_sys_ctrl_txclk_sync
Synchronize RGMII.TXCLK to CLK25OUT:
CLK25OUT is the netx22xx output pad used as clock input for an external Ethernet PHY.
This signal is generated by XTAL and is also reference for netX system PLLs.
In RGMII-100 mode some PHYs can run in low-latency mode, if TXCLK is in a synchronous position to CLK25OUT.
This register allows to set a delay between the posedge of CLK25OUT and TXCLK.
R/W
0x00000000
Address : 0x07d82bbc
Bits Reset value Name Description
31 - 24 -
clk2txc_1_ro
Read only value of measured delay between CLK25OUT and RGMII1_TXCLK:
The TXCLK signal at the output pad will have a propagation delay compared to the same signal generated in OBU.
Also the posedge pulse of CLK25OUT will have a different propagation delay compared to the same signal at XTAL.
All propagation delays will vary with operating conditions.
To measure and find a delay_val independant on propagation delays, posedge pulses are generated directly at feedback of pads CLK25OUT and COM_RGMII_TXC.
This clk2txc_ro value shows the distance between CLK25OUT and TXCLKLK in steps of 2ns.
This value will only change, if a TXCLK pulse is found between two CLK25OUT pulses.
23 - 16 -
clk2txc_0_ro
Read only value of measured delay between CLK25OUT and RGMII0_TXCLK:
The TXCLK signal at the output pad will have a propagation delay compared to the same signal generated in OBU.
Also the posedge pulse of CLK25OUT will have a different propagation delay compared to the same signal at XTAL.
All propagation delays will vary with operating conditions.
To measure and find a delay_val independant on propagation delays, posedge pulses are generated directly at feedback of pads CLK25OUT and COM_RGMII_TXC.
This clk2txc_ro value shows the distance between CLK25OUT and TXCLK in steps of 2ns.
This value will only change, if a TXCLK pulse is found between two CLK25OUT pulses.
15 - 8 "00000000"
delay_val1
Delay between posedge of CLK25OUT and start of XC1_TXCLK in steps of 2ns.
When writing 1 to bit 24 of this register, the global_counter of GMAC1-OBU will be synchronized to the rising edge of CLK25OUT delayed by this value.
TXCLK signals of RGMII and SGMII are derived from the global_counter of GMAC1_OBU.
Note: Synchronisation cannot produce hazards in TXCLK signals, as it only adds wait cycles to the global counter.
7 - 0 "00000000"
delay_val0
Delay between posedge of CLK25OUT and start of XC0_TXCLK in steps of 2ns.
When writing 1 to bit 16 of this register, the global_counter of GMAC0-OBU will be synchronized to the rising edge of CLK25OUT delayed by this value.
TXCLK signals of RGMII and SGMII are derived from the global_counter of GMAC0_OBU.
Note: Synchronisation cannot produce hazards in TXCLK signals, as it only adds wait cycles to the global counter.


gxc_sys_ctrl_miimu0
MDIO FSM interface address 0 (e.g. for GPEC access)
Writing to miimu0 or miimu1 (with snrdy=1) starts sending an MDIO frame to external Ethernet PHY.
Two addresses (miimu0 and miimu1) are intended to arbitrate accesses of 2 masters (e.g. GPEC working on miimu0 and ARM working on miimu1)
on the same hardware module.
Before requesting the next MDIO frame wait for snrdy=0 (the whole register is not writable at snrdy=1).
R/W
0x00000018
Address : 0x07d82bc0
Bits Reset value Name Description
31 - 16 0x0
data
Data to or from PHY register
15 - 11 "00000"
regaddr
Register address (REGAD or DEVAD)
10 - 6 "00000"
phyaddr
PHY address (PHYAD or PRTAD)
5 - 4 "01"
op
Operation mode (OP field):
Standard ST (clause 22):
10: Read
01: Write
Extended ST (clause 45):
00: Address
01: Write
10: Post-read-increment-address
11: Read
3 "1"
st
2nd bit of STart field:
1: ST=01 (Standard, see clause 22 of IEEE 802.3-2018)
0: ST=00 (Extension, see clause 45 of IEEE 802.3-2018)
2 "0"
rd_nw
Read access (used for TA and data field):
1: Read, set in modes [st,op]=[1,10],[0,10],[0,11]
0: Write, set in other modes
1 "0"
arbiter_lock
lock arbiter:
Set this bit to send sequential requests.
miimu1 will only get access to the miimu module, after the next request to miimu0 is finished.
0 "0"
snrdy
Start not ready:
Set by software, reset by hardware if transmission is finished


gxc_sys_ctrl_miimu1
MDIO FSM interface address 1 (e.g. for ARM access)
Writing to miimu0 or miimu1 (with snrdy=1) starts sending an MDIO frame to external Ethernet PHY.
Two addresses (miimu0 and miimu1) are intended to arbitrate accesses of 2 masters (e.g. GPEC working on miimu0 and ARM working on miimu1)
on the same hardware module.
Before requesting the next MDIO frame wait for snrdy=0 (the whole register is not writable at snrdy=1).
R/W
0x00000018
Address : 0x07d82bc4
Bits Reset value Name Description
31 - 16 0x0
data
Data to or from PHY register
15 - 11 "00000"
regaddr
Register address (REGAD or DEVAD)
10 - 6 "00000"
phyaddr
PHY address (PHYAD or PRTAD)
5 - 4 "01"
op
Operation mode (OP field):
Standard ST (clause 22):
10: Read
01: Write
Extended ST (clause 45):
00: Address
01: Write
10: Post-read-increment-address
11: Read
3 "1"
st
2nd bit of STart field:
1: ST=01 (Standard, see clause 22 of IEEE 802.3-2018)
0: ST=00 (Extension, see clause 45 of IEEE 802.3-2018)
2 "0"
rd_nw
Read access (used for TA and data field):
1: Read, set in modes [st,op]=[1,10],[0,10],[0,11]
0: Write, set in other modes
1 "0"
arbiter_lock
lock arbiter:
Set this bit to send sequential requests.
miimu0 will only get access to the miimu module, after the next request to miimu1 is finished.
0 "0"
snrdy
Start not ready:
Set by software, reset by hardware if transmission is finished


gxc_sys_ctrl_miimu_cfg
MDIO config:
R/W
0x000000a0
Address : 0x07d82bc8
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
mdc_oe
MDC-output-enable
Note: MDC_OE can also be used in software-mode. It should be set after reset.
7 "1"
rta
Read Turn Around field:
0: one bit
1: two bits
Must always be set to 1.
6 "0"
mdc_period
MDC period:
0: 200ns
1: 400ns
5 - 0 "100000"
preamble
length of preamble


gxc_sys_ctrl_miimu_sw
MDIO software interface for external PHYs:
This register allows to control all bits of MDIO interface in software.
It is intended as alternative to using the MDIO FSM, in  case if upcoming standards, that are not supported by MDIO FSM..
R/W
0x00000000
Address : 0x07d82bcc
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
loopback
MDIO-data-out to data-in loopback for test purpose.
0: no loopback, MDIO-data-in comes from PHY.
1: loopback, MDIO-data-in comes from current MDIO-data-out.
Note: Loopback can also be used in non-software-mode.
7 -
mdi_ro
current MDI value
6 "0"
mdoe
MDOE value for software mode
5 "0"
mdo
MDO value for software mode
4 "0"
mdc
MDC value for software mode
3 - 1 0
-
 reserved
0 "0"
enable
Enables software mode:
MDC, MDO and MDOE are set by software.


gxc_sys_ctrl_intram_prio
Configuration of all GXC_SYS internal IMTRAMs with AXI2MEM interface
R/W
0x00000000
Address : 0x07d82bd0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 6 "00"
intram3
2'b00: round robin between read an write access
2'b01: read access has priority
2'b10: write access has priority
2'b11: reserved
5 - 4 "00"
intram2
2'b00: round robin between read an write access
2'b01: read access has priority
2'b10: write access has priority
2'b11: reserved
3 - 2 "00"
intram1
2'b00: round robin between read an write access
2'b01: read access has priority
2'b10: write access has priority
2'b11: reserved
1 - 0 "00"
intram0
2'b00: round robin between read an write access
2'b01: read access has priority
2'b10: write access has priority
2'b11: reserved


gxc_sys_ctrl_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d82bd4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
phy1_link_change
Event: Link at PHY1 changed
0 "0"
phy0_link_change
Event: Link at PHY0 changed


gxc_sys_ctrl_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gxc_sys_ctrl_irq_raw).
R/W
0x00000000
Address : 0x07d82bd8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
phy1_link_change
Event: Link at PHY1 changed
0 "0"
phy0_link_change
Event: Link at PHY0 changed


gxc_sys_ctrl_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gxc_sys_ctrl_irq_raw
R/W
0x00000000
Address : 0x07d82bdc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
phy1_link_change
Event: Link at PHY1 changed
0 "0"
phy0_link_change
Event: Link at PHY0 changed


gxc_sys_ctrl_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 2 when no IRQ is set:
  0 : irq-phy0_link_change
  1 : irq-phy1_link_change
  2 : no active IRQ
R/W
0x00000000
Address : 0x07d82be0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
phy1_link_change
Event: Link at PHY1 changed
0 "0"
phy0_link_change
Event: Link at PHY0 changed



Base Address Area: gxc_trigger_lt

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_trigger_mode
1 4 R/W gxc_trigger_impulse_length
2 8 R/W gxc_trigger_offset_lower
3 c R/W gxc_trigger_offset_upper
4 10 R/W gxc_trigger_sync1_interval
5 14 R/W gxc_trigger_activate
6 18 R/W gxc_trigger_0_starttime_s
7 1c R/W gxc_trigger_0_starttime_ns
8 20 R/W gxc_trigger_1_starttime_s
9 24 R/W gxc_trigger_1_starttime_ns
a 28 R/W gxc_trigger_0_cyc_time
b 2c R/W gxc_trigger_1_cyc_time
c 30 R/W gxc_sample_mode
d 34 R/W gxc_sample_offset_lower
e 38 R/W gxc_sample_offset_upper
f 3c R/W gxc_sample_activate
10 40 R/W gxc_sample_0_pos_systime_s
11 44 R/W gxc_sample_0_pos_systime_ns
12 48 R/W gxc_sample_0_neg_systime_s
13 4c R/W gxc_sample_0_neg_systime_ns
14 50 R/W gxc_sample_1_pos_systime_s
15 54 R/W gxc_sample_1_pos_systime_ns
16 58 R/W gxc_sample_1_neg_systime_s
17 5c R/W gxc_sample_1_neg_systime_ns
18 60 R/W gxc_trigger_sample_status
19 64 R/W gxc_trigger_sample_irq_raw
1a 68 R/W gxc_trigger_sample_irq_masked
1b 6c R/W gxc_trigger_sample_irq_mask_set
1c 70 R/W gxc_trigger_sample_irq_mask_rst
1d-3f 74-fc -  reserved

gxc_trigger_mode
Sync Out mode register
R/W
0x00000000
Address : 0x07d82c00
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 12 "0000"
cyc1_count
cycle counter for sync 1, 0..16 (0=endless, 1..16 times) (normal mode only)
write cycle counter before trigger_1_starttime_ns
writing trigger_1_starttime_ns restarts cycle counter/timer
number of added pulses after Sync1 event, 0/1: no added pulses, 2..15 lead to 1..14 added pulses after sync1 event
11 - 9 0
-
 reserved
8 "0"
trigger_mode
trigger unit mode:
1/0: ecat (sync1 depends on sync0) / normal (sync0 and sync1 are independent)
7 0
-
 reserved
6 "0"
sync1_oe
1/0: sync1 output enabled/disabled
5 "0"
sync1_polarity
1/0: sync1 high/low active
4 "0"
sync1_output_driver
1/0: sync1 open/push-pull
3 0
-
 reserved
2 "0"
sync0_oe
1/0: sync0 output enabled/disabled
1 "0"
sync0_polarity
1/0: sync0 high/low active
0 "0"
sync0_output_driver
1/0: sync0 open/push-pull


gxc_trigger_impulse_length
Sync Out impulse length register
R/W
0x00000000
Address : 0x07d82c04
Bits Reset value Name Description
31 - 16 0x0
sync1_impulse_length
impulse length Sync1 signal (in Units of cc), 0x0000: activates acknowledge mode
impulse length + 1 [cc], to configure 2..2^16 pulse width use values 1..2^15
15 - 0 0x0
sync0_impulse_length
impulse length Sync0 signal (in Units of cc), 0x0000: activates acknowledge mode
impulse length + 1 [cc], to configure 2..2^16 pulse width use values 1..2^15


gxc_trigger_offset_lower
Sync Out systime_ns offset register
R/W
0x00000000
Address : 0x07d82c08
Bits Reset value Name Description
31 - 0 0x0
val
trigger_offset register for NextSync0SysTime and NextSync1SysTime
may only be != 0 when systime_border = 0xffffffff


gxc_trigger_offset_upper
Sync Out systime_s offset register
R/W
0x00000000
Address : 0x07d82c0c
Bits Reset value Name Description
31 - 0 0x0
val
trigger_offset register for NextSync0SysTime and NextSync1SysTime
may only be != 0 when systime_border = 0xffffffff


gxc_trigger_sync1_interval
Sync Out sync1 interval register
R/W
0x00000000
Address : 0x07d82c10
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 - 0 0x0
sync1_interval
sync1 interval
important: use multiple of 0xa (10)


gxc_trigger_activate
Sync Out activate register
R/W
0x00000000
Address : 0x07d82c14
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sync1_activate
1/0: sync1 activated/deactivated
1 "0"
sync0_activate
1/0: sync0 activated/deactivated
0 "0"
trigger_unit_activate
0->1 (posedge): activates trigger unit cyclic functions
normal mode: unit waits for trigger_0_starttime and trigger_1_starttime independently
ecat mode: unit waits for trigger_0_starttime
1->0 (negedge): reset trigger unit state machine (internal signals)


gxc_trigger_0_starttime_s
Sync Out start time 0 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c18
Bits Reset value Name Description
31 - 0 0x0
systime_s
write: system time s when 1st sync0 event shall occur
read: systime_s value of next sync0 event


gxc_trigger_0_starttime_ns
Sync Out start time 0 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c1c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
write: system time ns when 1st sync0 event shall occur
read: systime_ns value of next sync0 event


gxc_trigger_1_starttime_s
Sync Out start time 1 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c20
Bits Reset value Name Description
31 - 0 0x0
systime_s
write: systime_s when 1st sync1 event shall occur
read: systime_s value of next sync1 event


gxc_trigger_1_starttime_ns
Sync Out start time 1 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c24
Bits Reset value Name Description
31 - 0 0x0
systime_ns
write: systime_ns when 1st sync1 event shall occur
read: systime_ns value of next sync1 event
In ecat mode the trigger_1_starttime_ns must be configured manuelly with trigger_0_starttime_ns + trigger_1_cycle_time before activation of the unit


gxc_trigger_0_cyc_time
Sync Out cycle time 0 register
R/W
0x00000000
Address : 0x07d82c28
Bits Reset value Name Description
31 - 0 0x0
systime_ns
Time between two consecutive SYNC0 Signals
cyclic functions are disabled if CYC_TIME0==0 -> single event usage
if cycle time not zero then cyletime > 40 ns and < systime_border


gxc_trigger_1_cyc_time
Sync Out cycle time 1 register
R/W
0x00000000
Address : 0x07d82c2c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
normal mode: Time between two consecutive SYNC1 Signal
ecat mode: Time between SYNC1 Signal and SYNC0 Signal
if cycle time not zero then cyletime > 40 ns and < systime_border


gxc_sample_mode
Latch In mode register
R/W
0x00000000
Address : 0x07d82c30
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
sample_1_negedge_mode
latch1 negative edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
8 "0"
sample_1_posedge_mode
latch1 positive edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
7 - 2 0
-
 reserved
1 "0"
sample_0_negedge_mode
latch0 negative edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
0 "0"
sample_0_posedge_mode
latch0 positive edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)


gxc_sample_offset_lower
sample systime offset register bits 31 to 0
R/W
0x00000000
Address : 0x07d82c34
Bits Reset value Name Description
31 - 0 0x0
val
offset register for sample systime
may only be != 0 when systime_border = 0xffffffff


gxc_sample_offset_upper
sample systime offset register bits 63 to 32
R/W
0x00000000
Address : 0x07d82c38
Bits Reset value Name Description
31 - 0 0x0
val
offset register for sample systime
may only be != 0 when systime_border = 0xffffffff


gxc_sample_activate
Latch In activate register
R/W
0x00000000
Address : 0x07d82c3c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
latch1_ecat_controlled
1: latch status is cleared on read by esc_runit / 0: status is not cleared on read by esc_runit
1 "0"
latch0_ecat_controlled
1: latch status is cleared on read by esc_runit / 0: status is not cleared on read by esc_runit
0 "0"
latch_unit_activate
0->1 (posedge)/ 1->0 (negedge): latching enabled/disabled (reset internal statemachine)


gxc_sample_0_pos_systime_s
Latch In sample 0 positive edge systime_s
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c40
Bits Reset value Name Description
31 - 0 0x0
systime_s
systime_s when posedge at latch 0 occurred


gxc_sample_0_pos_systime_ns
Latch In sample 0 positive edge systime_ns
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c44
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when posedge at latch 0 occurred


gxc_sample_0_neg_systime_s
Latch In sample 0 negative edge systime_s
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c48
Bits Reset value Name Description
31 - 0 0x0
systime_s
systime_s when negedge at latch 0 occurred


gxc_sample_0_neg_systime_ns
Latch In sample 0 negative edge systime_ns
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c4c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when negedge at latch 0 occurred


gxc_sample_1_pos_systime_s
Latch In sample 1 positive edge systime_s
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c50
Bits Reset value Name Description
31 - 0 0x0
systime_s
systime_s when posedge at latch 1 occurred


gxc_sample_1_pos_systime_ns
Latch In sample 1 positive edge systime_ns
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c54
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when posedge at latch 1 occurred


gxc_sample_1_neg_systime_s
Latch In sample 1 negative edge systime_s
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c58
Bits Reset value Name Description
31 - 0 0x0
systime_s
systime_s when negedge at latch 1 occurred


gxc_sample_1_neg_systime_ns
Latch In sample 1 negative edge systime_ns
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82c5c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when negedge at latch 1 occurred


gxc_trigger_sample_status
Sync Out / Latch In status register
changed by hardware, write access (1'b1) clears the status
R/W
0x00000000
Address : 0x07d82c60
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
sample_1_in
current value at latch1
25 "0"
sample_1_negedge_status
1/0: negative edge detected/not detected at latch 1
24 "0"
sample_1_posedge_status
1/0: positive edge detected/not detected at latch 1
23 - 19 0
-
 reserved
18 "0"
sample_0_in
current value at latch0
17 "0"
sample_0_negedge_status
1/0: negative edge detected/not detected at latch 0
16 "0"
sample_0_posedge_status
1/0: positive edge detected/not detected at latch 0
15 - 9 0
-
 reserved
8 "0"
sync1_status
status of sync1
7 - 1 0
-
 reserved
0 "0"
sync0_status
status of sync0


gxc_trigger_sample_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d82c64
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_trigger_sample_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gxc_trigger_sample_irq_raw).
R/W
0x00000000
Address : 0x07d82c68
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_trigger_sample_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gxc_trigger_sample_irq_raw
R/W
0x00000000
Address : 0x07d82c6c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_trigger_sample_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 6 when no IRQ is set:
  0 : irq-sync0_irq
  1 : irq-sync1_irq
  2 : irq-latch0_posedge_irq
  3 : irq-latch0_negedge_irq
  4 : irq-latch1_posedge_irq
  5 : irq-latch1_negedge_irq
  6 : no active IRQ
R/W
0x00000000
Address : 0x07d82c70
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt



Base Address Area: gxc_trigger_lt_global

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_global_trigger_mode
1 4 R/W gxc_global_trigger_impulse_length
2 8 R/W gxc_global_trigger_offset_lower
3 c -  reserved
4 10 R/W gxc_global_trigger_sync1_interval
5 14 R/W gxc_global_trigger_activate
6 18 R/W gxc_global_trigger_0_starttime_ns
7 1c R/W gxc_global_trigger_1_starttime_ns
8 20 R/W gxc_global_trigger_0_cyc_time
9 24 R/W gxc_global_trigger_1_cyc_time
a 28 R/W gxc_global_sample_mode
b 2c R/W gxc_global_sample_offset_lower
c 30 -  reserved
d 34 R/W gxc_global_sample_activate
e 38 R/W gxc_global_sample_0_pos_systime_ns
f 3c R/W gxc_global_sample_0_neg_systime_ns
10 40 R/W gxc_global_sample_1_pos_systime_ns
11 44 R/W gxc_global_sample_1_neg_systime_ns
12 48 R/W gxc_global_trigger_sample_status
13 4c R/W gxc_global_trigger_sample_irq_raw
14 50 R/W gxc_global_trigger_sample_irq_masked
15 54 R/W gxc_global_trigger_sample_irq_mask_set
16 58 R/W gxc_global_trigger_sample_irq_mask_rst
17-3f 5c-fc -  reserved

gxc_global_trigger_mode
Sync Out mode register
R/W
0x00000000
Address : 0x07d82d00
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 12 "0000"
cyc1_count
cycle counter for sync 1, 0..16 (0=endless, 1..16 times) (normal mode only)
write cycle counter before trigger_1_starttime_ns
writing trigger_1_starttime_ns restarts cycle counter/timer
number of added pulses after Sync1 event, 0/1: no added pulses, 2..15 lead to 1..14 added pulses after sync1 event
11 - 9 0
-
 reserved
8 "0"
trigger_mode
trigger unit mode:
1/0: ecat (sync1 depends on sync0) / normal (sync0 and sync1 are independent)
7 0
-
 reserved
6 "0"
sync1_oe
1/0: sync1 output enabled/disabled
5 "0"
sync1_polarity
1/0: sync1 high/low active
4 "0"
sync1_output_driver
1/0: sync1 open/push-pull
3 0
-
 reserved
2 "0"
sync0_oe
1/0: sync0 output enabled/disabled
1 "0"
sync0_polarity
1/0: sync0 high/low active
0 "0"
sync0_output_driver
1/0: sync0 open/push-pull


gxc_global_trigger_impulse_length
Sync Out impulse length register
R/W
0x00000000
Address : 0x07d82d04
Bits Reset value Name Description
31 - 16 0x0
sync1_impulse_length
impulse length Sync1 signal (in Units of cc), 0x0000: activates acknowledge mode
impulse length + 1 [cc], to configure 2..2^16 pulse width use values 1..2^15
15 - 0 0x0
sync0_impulse_length
impulse length Sync0 signal (in Units of cc), 0x0000: activates acknowledge mode
impulse length + 1 [cc], to configure 2..2^16 pulse width use values 1..2^15


gxc_global_trigger_offset_lower
Sync Out systime_ns offset register
R/W
0x00000000
Address : 0x07d82d08
Bits Reset value Name Description
31 - 0 0x0
val
trigger_offset register for NextSync0SysTime and NextSync1SysTime
may only be != 0 when systime_border = 0xffffffff


gxc_global_trigger_sync1_interval
Sync Out sync1 interval register
R/W
0x00000000
Address : 0x07d82d10
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 - 0 0x0
sync1_interval
sync1 interval
important: use multiple of 0xa (10)


gxc_global_trigger_activate
Sync Out activate register
R/W
0x00000000
Address : 0x07d82d14
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sync1_activate
1/0: sync1 activated/deactivated
1 "0"
sync0_activate
1/0: sync0 activated/deactivated
0 "0"
trigger_unit_activate
0->1 (posedge): activates trigger unit cyclic functions
normal mode: unit waits for trigger_0_starttime and trigger_1_starttime independently
ecat mode: unit waits for trigger_0_starttime
1->0 (negedge): reset trigger unit state machine (internal signals)


gxc_global_trigger_0_starttime_ns
Sync Out start time 0 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82d18
Bits Reset value Name Description
31 - 0 0x0
systime_ns
write: system time ns when 1st sync0 event shall occur
read: systime_ns value of next sync0 event


gxc_global_trigger_1_starttime_ns
Sync Out start time 1 register
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
changed by hardware
R/W
0x00000000
Address : 0x07d82d1c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
write: systime_ns when 1st sync1 event shall occur
read: systime_ns value of next sync1 event
In ecat mode the trigger_1_starttime_ns must be configured manuelly with trigger_0_starttime_ns + trigger_1_cycle_time before activation of the unit


gxc_global_trigger_0_cyc_time
Sync Out cycle time 0 register
R/W
0x00000000
Address : 0x07d82d20
Bits Reset value Name Description
31 - 0 0x0
systime_ns
Time between two consecutive SYNC0 Signals
cyclic functions are disabled if CYC_TIME0==0 -> single event usage
if cycle time not zero then cyletime > 40 ns and < systime_border


gxc_global_trigger_1_cyc_time
Sync Out cycle time 1 register
R/W
0x00000000
Address : 0x07d82d24
Bits Reset value Name Description
31 - 0 0x0
systime_ns
normal mode: Time between two consecutive SYNC1 Signal
ecat mode: Time between SYNC1 Signal and SYNC0 Signal
if cycle time not zero then cyletime > 40 ns and < systime_border


gxc_global_sample_mode
Latch In mode register
R/W
0x00000000
Address : 0x07d82d28
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
sample_1_negedge_mode
latch1 negative edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
8 "0"
sample_1_posedge_mode
latch1 positive edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
7 - 2 0
-
 reserved
1 "0"
sample_0_negedge_mode
latch0 negative edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)
0 "0"
sample_0_posedge_mode
latch0 positive edge mode
0: continuous sampling (status not set) 1: single sampling (latch status must be reset before latching enabled again)


gxc_global_sample_offset_lower
sample systime offset register bits 31 to 0
R/W
0x00000000
Address : 0x07d82d2c
Bits Reset value Name Description
31 - 0 0x0
val
offset register for sample systime
may only be != 0 when systime_border = 0xffffffff


gxc_global_sample_activate
Latch In activate register
R/W
0x00000000
Address : 0x07d82d34
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
latch_unit_activate
0->1 (posedge)/ 1->0 (negedge): latching enabled/disabled (reset internal statemachine)


gxc_global_sample_0_pos_systime_ns
Latch In sample 0 positive edge systime_ns
changed by hardware
R/W
0x00000000
Address : 0x07d82d38
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when posedge at latch 0 occurred


gxc_global_sample_0_neg_systime_ns
Latch In sample 0 negative edge systime_ns
changed by hardware
R/W
0x00000000
Address : 0x07d82d3c
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when negedge at latch 0 occurred


gxc_global_sample_1_pos_systime_ns
Latch In sample 1 positive edge systime_ns
changed by hardware
R/W
0x00000000
Address : 0x07d82d40
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when posedge at latch 1 occurred


gxc_global_sample_1_neg_systime_ns
Latch In sample 1 negative edge systime_ns
changed by hardware
R/W
0x00000000
Address : 0x07d82d44
Bits Reset value Name Description
31 - 0 0x0
systime_ns
systime_ns when negedge at latch 1 occurred


gxc_global_trigger_sample_status
Sync Out / Latch In status register
changed by hardware, write access (1'b1) clears the status
R/W
0x00000000
Address : 0x07d82d48
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
sample_1_in
current value at latch1
25 "0"
sample_1_negedge_status
1/0: negative edge detected/not detected at latch 1
24 "0"
sample_1_posedge_status
1/0: positive edge detected/not detected at latch 1
23 - 19 0
-
 reserved
18 "0"
sample_0_in
current value at latch0
17 "0"
sample_0_negedge_status
1/0: negative edge detected/not detected at latch 0
16 "0"
sample_0_posedge_status
1/0: positive edge detected/not detected at latch 0
15 - 9 0
-
 reserved
8 "0"
sync1_status
status of sync1
7 - 1 0
-
 reserved
0 "0"
sync0_status
status of sync0


gxc_global_trigger_sample_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x07d82d4c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_global_trigger_sample_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gxc_global_trigger_sample_irq_raw).
R/W
0x00000000
Address : 0x07d82d50
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_global_trigger_sample_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gxc_global_trigger_sample_irq_raw
R/W
0x00000000
Address : 0x07d82d54
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt


gxc_global_trigger_sample_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 6 when no IRQ is set:
  0 : irq-sync0_irq
  1 : irq-sync1_irq
  2 : irq-latch0_posedge_irq
  3 : irq-latch0_negedge_irq
  4 : irq-latch1_posedge_irq
  5 : irq-latch1_negedge_irq
  6 : no active IRQ
R/W
0x00000000
Address : 0x07d82d58
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
latch1_negedge_irq
Event: latch1 negedge interrupt
4 "0"
latch1_posedge_irq
Event: latch1 posedge interrupt
3 "0"
latch0_negedge_irq
Event: latch0 negedge interrupt
2 "0"
latch0_posedge_irq
Event: latch0 posedge interrupt
1 "0"
sync1_irq
Event: sync1 interrupt
0 "0"
sync0_irq
Event: sync0 interrupt



Base Address Area: gxc_systime

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_systime_s
1 4 R/W gxc_systime_ns
2 8 R/W gxc_systime_border
3 c R/W gxc_systime_count_value
4 10 R/W gxc_systime_global_s
5 14 R/W gxc_systime_global_ns
6 18 R/W gxc_systime_global_border
7 1c R/W gxc_systime_global_count_value
8 20 R/W gxc_counter_hi
9 24 R/W gxc_counter_lo
a 28 -  reserved
b 2c R/W gxc_counter_count_value
c 30 R/W gxc_reset_gpec_sample_regs0
d 34 R/W gxc_reset_gpec_sample_regs1
e-3f 38-fc -  reserved

gxc_systime_s
Upper SYSTIME register:
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
R/W
0x00000000
Address : 0x07d82e00
Bits Reset value Name Description
31 - 0 0x0
val
Systime high
value is incremented, if systime_ns reaches systime_border
Sample systime_ns at read access to systime_s.


gxc_systime_ns
Lower SYSTIME register:
To allow consistent values of systime_s and systime_ns, lower bits of systime is latched to systime_ns, when systime_s is read.
If no systime_s is read before (or at 2nd read access of systime_ns), the actual value of systime_ns is read.
R/W
0x00000000
Address : 0x07d82e04
Bits Reset value Name Description
31 - 0 0x0
val
Systime low:
Sample systime_ns at read access to systime_s.
Without sample read systime_s, read the actual value of systime_ns.


gxc_systime_border
SYSTIME border register
R/W
0x3b9ac9ff
Address : 0x07d82e08
Bits Reset value Name Description
31 - 0 0x3b9ac9ff
val
Systime border for lower systime:
systime_ns counts from 0 to this value (inlcuded),
i.e. systime_ns counts modulo (systime_border + 1)
Attention: the border value Bit 3 to 0 must be b'1111 (hex f) for all netX systime - match functions


gxc_systime_count_value
SYSTIME count register
R/W
0x00000000
Address : 0x07d82e0c
Bits Reset value Name Description
31 - 0 0x0
val
Each clock cycle (systime_count_value >> 28) c
will be added to systime (rate multiplier for IEEE1588).
Value 0x20000000 can be used for counting in 2ns (ethernet clock) steps.


gxc_systime_global_s
Upper SYSTIME_GLOBAL register:
To allow consistent values of systime_global_s and systime_global_ns, lower bits of systime_global is latched to systime_global_ns, when systime_global_s is read.
R/W
0x00000000
Address : 0x07d82e10
Bits Reset value Name Description
31 - 0 0x0
val
Systime high
value is incremented, if systime_global_ns reaches systime_global_border
Sample systime_global_ns at read access to systime_global_s.


gxc_systime_global_ns
Lower SYSTIME_GLOBAL register:
To allow consistent values of systime_global_s and systime_global_ns, lower bits of systime_global is latched to systime_global_ns, when systime_global_s is read.
If no systime_global_s is read before (or at 2nd read access of systime_global_ns), the actual value of systime_global_ns is read.
R/W
0x00000000
Address : 0x07d82e14
Bits Reset value Name Description
31 - 0 0x0
val
Systime_global low:
Sample systime_global_ns at read access to systime_global_s.
Without sample read systime_global_s, read the actual value of systime_global_ns.


gxc_systime_global_border
SYSTIME_GLOBAL border register
R/W
0x3b9ac9ff
Address : 0x07d82e18
Bits Reset value Name Description
31 - 0 0x3b9ac9ff
val
Systime_global border for lower systime_global:
systime_global_ns counts from 0 to this value (inlcuded),
i.e. systime_global_ns counts modulo (systime_global_border + 1)
Attention: the border value Bit 3 to 0 must be b'1111 (hex f) for all netX systime - match functions


gxc_systime_global_count_value
SYSTIME_GLOBAL count register
R/W
0x00000000
Address : 0x07d82e1c
Bits Reset value Name Description
31 - 0 0x0
val
Each clock cycle (systime_global_count_value >> 28) c
will be added to systime (rate multiplier for IEEE1588).
Value 0x20000000 can be used for counting in 2ns (ethernet clock) steps.


gxc_counter_hi
Upper COUNTER counter:
R/W
0x00000000
Address : 0x07d82e20
Bits Reset value Name Description
31 - 0 0x0
val
Counter high
value is incremented, if counter_lo reaches 0xffffffff
Sample counter_lo at read access to counter_up.


gxc_counter_lo
Lower COUNTER counter:
To allow consistent values of adr_counter_lo and counter_up, lower bits of counter is latched to counter_lo, when counter_up is read.
If no counter_up is read before (or at 2nd read access of counter_lo), the actual value of counter_lo is read.
R/W
0x00000000
Address : 0x07d82e24
Bits Reset value Name Description
31 - 0 0x0
val
Counter low:
Sample counter_lo at read access to counter_hi.
Without sample read counter_hi, read the actual value of counter_lo.


gxc_counter_count_value
COUNTER count register
R/W
0x00000000
Address : 0x07d82e2c
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
val
Each clock cycle


gxc_reset_gpec_sample_regs0
Write 1 to the corresponding bit (with write mask) to reset sample state.
Clear the bit after writing,
not clearing the bit leads to disable the sample logic, gpec always reads systime_lo
This register is a write mask register
R/W
0x00000000
Address : 0x07d82e30
Bits Reset value Name Description
31 "0"
gpec07_counter_reset_wm
Write mask of gpec07_counter_reset
30 "0"
gpec07_systime_reset_wm
Write mask of gpec07_systime_reset
29 "0"
gpec06_counter_reset_wm
Write mask of gpec06_counter_reset
28 "0"
gpec06_systime_reset_wm
Write mask of gpec06_systime_reset
27 "0"
gpec05_counter_reset_wm
Write mask of gpec05_counter_reset
26 "0"
gpec05_systime_reset_wm
Write mask of gpec05_systime_reset
25 "0"
gpec04_counter_reset_wm
Write mask of gpec04_counter_reset
24 "0"
gpec04_systime_reset_wm
Write mask of gpec04_systime_reset
23 "0"
gpec03_counter_reset_wm
Write mask of gpec03_counter_reset
22 "0"
gpec03_systime_reset_wm
Write mask of gpec03_systime_reset
21 "0"
gpec02_counter_reset_wm
Write mask of gpec02_counter_reset
20 "0"
gpec02_systime_reset_wm
Write mask of gpec02_systime_reset
19 "0"
gpec01_counter_reset_wm
Write mask of gpec01_counter_reset
18 "0"
gpec01_systime_reset_wm
Write mask of gpec01_systime_reset
17 "0"
gpec00_counter_reset_wm
Write mask of gpec00_counter_reset
16 "0"
gpec00_systime_reset_wm
Write mask of gpec00_systime_reset
15 "0"
gpec07_counter_reset
reset counter sample state
14 "0"
gpec07_systime_reset
reset systime sample state
13 "0"
gpec06_counter_reset
reset counter sample state
12 "0"
gpec06_systime_reset
reset systime sample state
11 "0"
gpec05_counter_reset
reset counter sample state
10 "0"
gpec05_systime_reset
reset systime sample state
9 "0"
gpec04_counter_reset
reset counter sample state
8 "0"
gpec04_systime_reset
reset systime sample state
7 "0"
gpec03_counter_reset
reset counter sample state
6 "0"
gpec03_systime_reset
reset systime sample state
5 "0"
gpec02_counter_reset
reset counter sample state
4 "0"
gpec02_systime_reset
reset systime sample state
3 "0"
gpec01_counter_reset
reset counter sample state
2 "0"
gpec01_systime_reset
reset systime sample state
1 "0"
gpec00_counter_reset
reset counter sample state
0 "0"
gpec00_systime_reset
reset systime sample state


gxc_reset_gpec_sample_regs1
Write 1 to the corresponding bit (with write mask) to reset sample state.
Clear the bit after writing,
not clearing the bit leads to disable the sample logic, gpec always reads systime_lo
This register is a write mask register
R/W
0x00000000
Address : 0x07d82e34
Bits Reset value Name Description
31 "0"
gpec17_counter_reset_wm
Write mask of gpec17_counter_reset
30 "0"
gpec17_systime_reset_wm
Write mask of gpec17_systime_reset
29 "0"
gpec16_counter_reset_wm
Write mask of gpec16_counter_reset
28 "0"
gpec16_systime_reset_wm
Write mask of gpec16_systime_reset
27 "0"
gpec15_counter_reset_wm
Write mask of gpec15_counter_reset
26 "0"
gpec15_systime_reset_wm
Write mask of gpec15_systime_reset
25 "0"
gpec14_counter_reset_wm
Write mask of gpec14_counter_reset
24 "0"
gpec14_systime_reset_wm
Write mask of gpec14_systime_reset
23 "0"
gpec13_counter_reset_wm
Write mask of gpec13_counter_reset
22 "0"
gpec13_systime_reset_wm
Write mask of gpec13_systime_reset
21 "0"
gpec12_counter_reset_wm
Write mask of gpec12_counter_reset
20 "0"
gpec12_systime_reset_wm
Write mask of gpec12_systime_reset
19 "0"
gpec11_counter_reset_wm
Write mask of gpec11_counter_reset
18 "0"
gpec11_systime_reset_wm
Write mask of gpec11_systime_reset
17 "0"
gpec10_counter_reset_wm
Write mask of gpec10_counter_reset
16 "0"
gpec10_systime_reset_wm
Write mask of gpec10_systime_reset
15 "0"
gpec17_counter_reset
reset counter sample state
14 "0"
gpec17_systime_reset
reset systime sample state
13 "0"
gpec16_counter_reset
reset counter sample state
12 "0"
gpec16_systime_reset
reset systime sample state
11 "0"
gpec15_counter_reset
reset counter sample state
10 "0"
gpec15_systime_reset
reset systime sample state
9 "0"
gpec14_counter_reset
reset counter sample state
8 "0"
gpec14_systime_reset
reset systime sample state
7 "0"
gpec13_counter_reset
reset counter sample state
6 "0"
gpec13_systime_reset
reset systime sample state
5 "0"
gpec12_counter_reset
reset counter sample state
4 "0"
gpec12_systime_reset
reset systime sample state
3 "0"
gpec11_counter_reset
reset counter sample state
2 "0"
gpec11_systime_reset
reset systime sample state
1 "0"
gpec10_counter_reset
reset counter sample state
0 "0"
gpec10_systime_reset
reset systime sample state



Base Address Area: gxc_systime_lt

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R gxc_lt_systime_ns
1 4 R gxc_lt_systime_s
2 8 R gxc_lt_systime_global_ns
3 c R gxc_lt_systime_global_s
4 10 R gxc_lt_counter_lo
5 14 R gxc_lt_counter_hi
6 18 W gxc_lt_systimes_latch
7 1c -  reserved

gxc_lt_systime_ns
systime_ns last latched value
R
Address : 0x07d82f00
Bits Name Description
31 - 0 val
systime_ns last latched value


gxc_lt_systime_s
systime_s last latched value
R
Address : 0x07d82f04
Bits Name Description
31 - 0 val
systime_s last latched value


gxc_lt_systime_global_ns
systime_global_ns last latched value
R
Address : 0x07d82f08
Bits Name Description
31 - 0 val
systime_global_ns last latched value


gxc_lt_systime_global_s
systime_global_s last latched value
R
Address : 0x07d82f0c
Bits Name Description
31 - 0 val
systime_global_s last latched value


gxc_lt_counter_lo
counter_lo last latched value
R
Address : 0x07d82f10
Bits Name Description
31 - 0 val
counter_lo last latched value


gxc_lt_counter_hi
counter_hi last latched value
R
Address : 0x07d82f14
Bits Name Description
31 - 0 val
counter_hi last latched value


gxc_lt_systimes_latch
latch systimes by writing 1'b1 to the assigned bit
W
0x00000000
Address : 0x07d82f18
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
counter_hi

4 "0"
counter_lo

3 "0"
systime_global_s

2 "0"
systime_global_ns

1 "0"
systime_s

0 "0"
systime_ns




Base Address Area: gxc_distribute_sync, gxc_distribute_sync_global

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gxc_distribute_sync_select
1 4 R/W gxc_distribute_sync_periode
2 8 R/W gxc_distribute_sync_time_ns
3 c R/W gxc_distribute_sync_time_s
4 10 R/W gxc_distribute_sync_enable
5-7 14-1c -  reserved

gxc_distribute_sync_select
R/W
0x00000000
Address@gxc_distribute_sync : 0x07d82f20
Address@gxc_distribute_sync_global : 0x07d82f40
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
sync0_1
select sync 0 or sync 1 from trigger_lt for external sync


gxc_distribute_sync_periode
config periode for clock sync, 20 for systime in ns, 2 for systime in ns/10
R/W
0x00000000
Address@gxc_distribute_sync : 0x07d82f24
Address@gxc_distribute_sync_global : 0x07d82f44
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
periode for clock sync


gxc_distribute_sync_time_ns
Configure distribution synchronization start time in nanoseconds
Write a value to the register to set the start time
R/W
0x00000000
Address@gxc_distribute_sync : 0x07d82f28
Address@gxc_distribute_sync_global : 0x07d82f48
Bits Reset value Name Description
31 - 0 0x0
val
Distribution synchronization time nanoseconds


gxc_distribute_sync_time_s
Configure distribution synchronization start time in seconds
Write a value to the register to set the start time
R/W
0x00000000
Address@gxc_distribute_sync : 0x07d82f2c
Address@gxc_distribute_sync_global : 0x07d82f4c
Bits Reset value Name Description
31 - 0 0x0
val
Distribution synchronization time seconds


gxc_distribute_sync_enable
R/W
0x00000000
Address@gxc_distribute_sync : 0x07d82f30
Address@gxc_distribute_sync_global : 0x07d82f50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
cycle
enable cycle sync
0 "0"
clk
enable clock sync



Base Address Area: gxc_global_buf_man

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W global_read_buffer_0
1 4 R/W global_read_buffer_1
2 8 R/W global_read_buffer_2
3 c R/W global_read_buffer_3
4 10 R/W global_read_buffer_4
5 14 R/W global_read_buffer_5
6 18 R/W global_read_buffer_6
7 1c R/W global_read_buffer_7
8 20 R/W global_read_buffer_8
9 24 R/W global_read_buffer_9
a 28 R/W global_read_buffer_10
b 2c R/W global_read_buffer_11
c 30 R/W global_read_buffer_12
d 34 R/W global_read_buffer_13
e 38 R/W global_read_buffer_14
f 3c R/W global_read_buffer_15
10 40 R/W global_read_buffer_16
11 44 R/W global_read_buffer_17
12 48 R/W global_read_buffer_18
13 4c R/W global_read_buffer_19
14 50 R/W global_read_buffer_20
15 54 R/W global_read_buffer_21
16 58 R/W global_read_buffer_22
17 5c R/W global_read_buffer_23
18 60 R/W global_read_buffer_24
19 64 R/W global_read_buffer_25
1a 68 R/W global_read_buffer_26
1b 6c R/W global_read_buffer_27
1c 70 R/W global_read_buffer_28
1d 74 R/W global_read_buffer_29
1e 78 R/W global_read_buffer_30
1f 7c R/W global_read_buffer_31
20 80 R/W global_read_buffer_32
21 84 R/W global_read_buffer_33
22 88 R/W global_read_buffer_34
23 8c R/W global_read_buffer_35
24 90 R/W global_read_buffer_36
25 94 R/W global_read_buffer_37
26 98 R/W global_read_buffer_38
27 9c R/W global_read_buffer_39
28 a0 R/W global_read_buffer_40
29 a4 R/W global_read_buffer_41
2a a8 R/W global_read_buffer_42
2b ac R/W global_read_buffer_43
2c b0 R/W global_read_buffer_44
2d b4 R/W global_read_buffer_45
2e b8 R/W global_read_buffer_46
2f bc R/W global_read_buffer_47
30 c0 R/W global_read_buffer_48
31 c4 R/W global_read_buffer_49
32 c8 R/W global_read_buffer_50
33 cc R/W global_read_buffer_51
34 d0 R/W global_read_buffer_52
35 d4 R/W global_read_buffer_53
36 d8 R/W global_read_buffer_54
37 dc R/W global_read_buffer_55
38 e0 R/W global_read_buffer_56
39 e4 R/W global_read_buffer_57
3a e8 R/W global_read_buffer_58
3b ec R/W global_read_buffer_59
3c f0 R/W global_read_buffer_60
3d f4 R/W global_read_buffer_61
3e f8 R/W global_read_buffer_62
3f fc R/W global_read_buffer_63
40 100 R/W global_read_buffer_64
41 104 R/W global_read_buffer_65
42 108 R/W global_read_buffer_66
43 10c R/W global_read_buffer_67
44 110 R/W global_read_buffer_68
45 114 R/W global_read_buffer_69
46 118 R/W global_read_buffer_70
47 11c R/W global_read_buffer_71
48 120 R/W global_read_buffer_72
49 124 R/W global_read_buffer_73
4a 128 R/W global_read_buffer_74
4b 12c R/W global_read_buffer_75
4c 130 R/W global_read_buffer_76
4d 134 R/W global_read_buffer_77
4e 138 R/W global_read_buffer_78
4f 13c R/W global_read_buffer_79
50 140 R/W global_read_buffer_80
51 144 R/W global_read_buffer_81
52 148 R/W global_read_buffer_82
53 14c R/W global_read_buffer_83
54 150 R/W global_read_buffer_84
55 154 R/W global_read_buffer_85
56 158 R/W global_read_buffer_86
57 15c R/W global_read_buffer_87
58 160 R/W global_read_buffer_88
59 164 R/W global_read_buffer_89
5a 168 R/W global_read_buffer_90
5b 16c R/W global_read_buffer_91
5c 170 R/W global_read_buffer_92
5d 174 R/W global_read_buffer_93
5e 178 R/W global_read_buffer_94
5f 17c R/W global_read_buffer_95
60 180 R/W global_read_buffer_96
61 184 R/W global_read_buffer_97
62 188 R/W global_read_buffer_98
63 18c R/W global_read_buffer_99
64 190 R/W global_read_buffer_100
65 194 R/W global_read_buffer_101
66 198 R/W global_read_buffer_102
67 19c R/W global_read_buffer_103
68 1a0 R/W global_read_buffer_104
69 1a4 R/W global_read_buffer_105
6a 1a8 R/W global_read_buffer_106
6b 1ac R/W global_read_buffer_107
6c 1b0 R/W global_read_buffer_108
6d 1b4 R/W global_read_buffer_109
6e 1b8 R/W global_read_buffer_110
6f 1bc R/W global_read_buffer_111
70 1c0 R/W global_read_buffer_112
71 1c4 R/W global_read_buffer_113
72 1c8 R/W global_read_buffer_114
73 1cc R/W global_read_buffer_115
74 1d0 R/W global_read_buffer_116
75 1d4 R/W global_read_buffer_117
76 1d8 R/W global_read_buffer_118
77 1dc R/W global_read_buffer_119
78 1e0 R/W global_read_buffer_120
79 1e4 R/W global_read_buffer_121
7a 1e8 R/W global_read_buffer_122
7b 1ec R/W global_read_buffer_123
7c 1f0 R/W global_read_buffer_124
7d 1f4 R/W global_read_buffer_125
7e 1f8 R/W global_read_buffer_126
7f 1fc R/W global_read_buffer_127
80 200 R/W global_read_buffer_128
81 204 R/W global_read_buffer_129
82 208 R/W global_read_buffer_130
83 20c R/W global_read_buffer_131
84 210 R/W global_read_buffer_132
85 214 R/W global_read_buffer_133
86 218 R/W global_read_buffer_134
87 21c R/W global_read_buffer_135
88 220 R/W global_read_buffer_136
89 224 R/W global_read_buffer_137
8a 228 R/W global_read_buffer_138
8b 22c R/W global_read_buffer_139
8c 230 R/W global_read_buffer_140
8d 234 R/W global_read_buffer_141
8e 238 R/W global_read_buffer_142
8f 23c R/W global_read_buffer_143
90 240 R/W global_read_buffer_144
91 244 R/W global_read_buffer_145
92 248 R/W global_read_buffer_146
93 24c R/W global_read_buffer_147
94 250 R/W global_read_buffer_148
95 254 R/W global_read_buffer_149
96 258 R/W global_read_buffer_150
97 25c R/W global_read_buffer_151
98 260 R/W global_read_buffer_152
99 264 R/W global_read_buffer_153
9a 268 R/W global_read_buffer_154
9b 26c R/W global_read_buffer_155
9c 270 R/W global_read_buffer_156
9d 274 R/W global_read_buffer_157
9e 278 R/W global_read_buffer_158
9f 27c R/W global_read_buffer_159
a0 280 R/W global_read_buffer_160
a1 284 R/W global_read_buffer_161
a2 288 R/W global_read_buffer_162
a3 28c R/W global_read_buffer_163
a4 290 R/W global_read_buffer_164
a5 294 R/W global_read_buffer_165
a6 298 R/W global_read_buffer_166
a7 29c R/W global_read_buffer_167
a8 2a0 R/W global_read_buffer_168
a9 2a4 R/W global_read_buffer_169
aa 2a8 R/W global_read_buffer_170
ab 2ac R/W global_read_buffer_171
ac 2b0 R/W global_read_buffer_172
ad 2b4 R/W global_read_buffer_173
ae 2b8 R/W global_read_buffer_174
af 2bc R/W global_read_buffer_175
b0 2c0 R/W global_read_buffer_176
b1 2c4 R/W global_read_buffer_177
b2 2c8 R/W global_read_buffer_178
b3 2cc R/W global_read_buffer_179
b4 2d0 R/W global_read_buffer_180
b5 2d4 R/W global_read_buffer_181
b6 2d8 R/W global_read_buffer_182
b7 2dc R/W global_read_buffer_183
b8 2e0 R/W global_read_buffer_184
b9 2e4 R/W global_read_buffer_185
ba 2e8 R/W global_read_buffer_186
bb 2ec R/W global_read_buffer_187
bc 2f0 R/W global_read_buffer_188
bd 2f4 R/W global_read_buffer_189
be 2f8 R/W global_read_buffer_190
bf 2fc R/W global_read_buffer_191
c0 300 R/W global_read_buffer_192
c1 304 R/W global_read_buffer_193
c2 308 R/W global_read_buffer_194
c3 30c R/W global_read_buffer_195
c4 310 R/W global_read_buffer_196
c5 314 R/W global_read_buffer_197
c6 318 R/W global_read_buffer_198
c7 31c R/W global_read_buffer_199
c8 320 R/W global_read_buffer_200
c9 324 R/W global_read_buffer_201
ca 328 R/W global_read_buffer_202
cb 32c R/W global_read_buffer_203
cc 330 R/W global_read_buffer_204
cd 334 R/W global_read_buffer_205
ce 338 R/W global_read_buffer_206
cf 33c R/W global_read_buffer_207
d0 340 R/W global_read_buffer_208
d1 344 R/W global_read_buffer_209
d2 348 R/W global_read_buffer_210
d3 34c R/W global_read_buffer_211
d4 350 R/W global_read_buffer_212
d5 354 R/W global_read_buffer_213
d6 358 R/W global_read_buffer_214
d7 35c R/W global_read_buffer_215
d8 360 R/W global_read_buffer_216
d9 364 R/W global_read_buffer_217
da 368 R/W global_read_buffer_218
db 36c R/W global_read_buffer_219
dc 370 R/W global_read_buffer_220
dd 374 R/W global_read_buffer_221
de 378 R/W global_read_buffer_222
df 37c R/W global_read_buffer_223
e0 380 R/W global_read_buffer_224
e1 384 R/W global_read_buffer_225
e2 388 R/W global_read_buffer_226
e3 38c R/W global_read_buffer_227
e4 390 R/W global_read_buffer_228
e5 394 R/W global_read_buffer_229
e6 398 R/W global_read_buffer_230
e7 39c R/W global_read_buffer_231
e8 3a0 R/W global_read_buffer_232
e9 3a4 R/W global_read_buffer_233
ea 3a8 R/W global_read_buffer_234
eb 3ac R/W global_read_buffer_235
ec 3b0 R/W global_read_buffer_236
ed 3b4 R/W global_read_buffer_237
ee 3b8 R/W global_read_buffer_238
ef 3bc R/W global_read_buffer_239
f0 3c0 R/W global_read_buffer_240
f1 3c4 R/W global_read_buffer_241
f2 3c8 R/W global_read_buffer_242
f3 3cc R/W global_read_buffer_243
f4 3d0 R/W global_read_buffer_244
f5 3d4 R/W global_read_buffer_245
f6 3d8 R/W global_read_buffer_246
f7 3dc R/W global_read_buffer_247
f8 3e0 R/W global_read_buffer_248
f9 3e4 R/W global_read_buffer_249
fa 3e8 R/W global_read_buffer_250
fb 3ec R/W global_read_buffer_251
fc 3f0 R/W global_read_buffer_252
fd 3f4 R/W global_read_buffer_253
fe 3f8 R/W global_read_buffer_254
ff 3fc R/W global_read_buffer_255
100 400 R/W global_read_buffer_256
101 404 R/W global_read_buffer_257
102 408 R/W global_read_buffer_258
103 40c R/W global_read_buffer_259
104 410 R/W global_read_buffer_260
105 414 R/W global_read_buffer_261
106 418 R/W global_read_buffer_262
107 41c R/W global_read_buffer_263
108 420 R/W global_read_buffer_264
109 424 R/W global_read_buffer_265
10a 428 R/W global_read_buffer_266
10b 42c R/W global_read_buffer_267
10c 430 R/W global_read_buffer_268
10d 434 R/W global_read_buffer_269
10e 438 R/W global_read_buffer_270
10f 43c R/W global_read_buffer_271
110 440 R/W global_read_buffer_272
111 444 R/W global_read_buffer_273
112 448 R/W global_read_buffer_274
113 44c R/W global_read_buffer_275
114 450 R/W global_read_buffer_276
115 454 R/W global_read_buffer_277
116 458 R/W global_read_buffer_278
117 45c R/W global_read_buffer_279
118 460 R/W global_read_buffer_280
119 464 R/W global_read_buffer_281
11a 468 R/W global_read_buffer_282
11b 46c R/W global_read_buffer_283
11c 470 R/W global_read_buffer_284
11d 474 R/W global_read_buffer_285
11e 478 R/W global_read_buffer_286
11f 47c R/W global_read_buffer_287
120 480 R/W global_read_buffer_288
121 484 R/W global_read_buffer_289
122 488 R/W global_read_buffer_290
123 48c R/W global_read_buffer_291
124 490 R/W global_read_buffer_292
125 494 R/W global_read_buffer_293
126 498 R/W global_read_buffer_294
127 49c R/W global_read_buffer_295
128 4a0 R/W global_read_buffer_296
129 4a4 R/W global_read_buffer_297
12a 4a8 R/W global_read_buffer_298
12b 4ac R/W global_read_buffer_299
12c 4b0 R/W global_read_buffer_300
12d 4b4 R/W global_read_buffer_301
12e 4b8 R/W global_read_buffer_302
12f 4bc R/W global_read_buffer_303
130 4c0 R/W global_read_buffer_304
131 4c4 R/W global_read_buffer_305
132 4c8 R/W global_read_buffer_306
133 4cc R/W global_read_buffer_307
134 4d0 R/W global_read_buffer_308
135 4d4 R/W global_read_buffer_309
136 4d8 R/W global_read_buffer_310
137 4dc R/W global_read_buffer_311
138 4e0 R/W global_read_buffer_312
139 4e4 R/W global_read_buffer_313
13a 4e8 R/W global_read_buffer_314
13b 4ec R/W global_read_buffer_315
13c 4f0 R/W global_read_buffer_316
13d 4f4 R/W global_read_buffer_317
13e 4f8 R/W global_read_buffer_318
13f 4fc R/W global_read_buffer_319
140 500 R/W global_read_buffer_320
141 504 R/W global_read_buffer_321
142 508 R/W global_read_buffer_322
143 50c R/W global_read_buffer_323
144 510 R/W global_read_buffer_324
145 514 R/W global_read_buffer_325
146 518 R/W global_read_buffer_326
147 51c R/W global_read_buffer_327
148 520 R/W global_read_buffer_328
149 524 R/W global_read_buffer_329
14a 528 R/W global_read_buffer_330
14b 52c R/W global_read_buffer_331
14c 530 R/W global_read_buffer_332
14d 534 R/W global_read_buffer_333
14e 538 R/W global_read_buffer_334
14f 53c R/W global_read_buffer_335
150 540 R/W global_read_buffer_336
151 544 R/W global_read_buffer_337
152 548 R/W global_read_buffer_338
153 54c R/W global_read_buffer_339
154 550 R/W global_read_buffer_340
155 554 R/W global_read_buffer_341
156 558 R/W global_read_buffer_342
157 55c R/W global_read_buffer_343
158 560 R/W global_read_buffer_344
159 564 R/W global_read_buffer_345
15a 568 R/W global_read_buffer_346
15b 56c R/W global_read_buffer_347
15c 570 R/W global_read_buffer_348
15d 574 R/W global_read_buffer_349
15e 578 R/W global_read_buffer_350
15f 57c R/W global_read_buffer_351
160 580 R/W global_read_buffer_352
161 584 R/W global_read_buffer_353
162 588 R/W global_read_buffer_354
163 58c R/W global_read_buffer_355
164 590 R/W global_read_buffer_356
165 594 R/W global_read_buffer_357
166 598 R/W global_read_buffer_358
167 59c R/W global_read_buffer_359
168 5a0 R/W global_read_buffer_360
169 5a4 R/W global_read_buffer_361
16a 5a8 R/W global_read_buffer_362
16b 5ac R/W global_read_buffer_363
16c 5b0 R/W global_read_buffer_364
16d 5b4 R/W global_read_buffer_365
16e 5b8 R/W global_read_buffer_366
16f 5bc R/W global_read_buffer_367
170 5c0 R/W global_read_buffer_368
171 5c4 R/W global_read_buffer_369
172 5c8 R/W global_read_buffer_370
173 5cc R/W global_read_buffer_371
174 5d0 R/W global_read_buffer_372
175 5d4 R/W global_read_buffer_373
176 5d8 R/W global_read_buffer_374
177 5dc R/W global_read_buffer_375
178 5e0 R/W global_read_buffer_376
179 5e4 R/W global_read_buffer_377
17a 5e8 R/W global_read_buffer_378
17b 5ec R/W global_read_buffer_379
17c 5f0 R/W global_read_buffer_380
17d 5f4 R/W global_read_buffer_381
17e 5f8 R/W global_read_buffer_382
17f 5fc R/W global_read_buffer_383
180 600 R/W global_read_buffer_384
181 604 R/W global_read_buffer_385
182 608 R/W global_read_buffer_386
183 60c R/W global_read_buffer_387
184 610 R/W global_read_buffer_388
185 614 R/W global_read_buffer_389
186 618 R/W global_read_buffer_390
187 61c R/W global_read_buffer_391
188 620 R/W global_read_buffer_392
189 624 R/W global_read_buffer_393
18a 628 R/W global_read_buffer_394
18b 62c R/W global_read_buffer_395
18c 630 R/W global_read_buffer_396
18d 634 R/W global_read_buffer_397
18e 638 R/W global_read_buffer_398
18f 63c R/W global_read_buffer_399
190 640 R/W global_read_buffer_400
191 644 R/W global_read_buffer_401
192 648 R/W global_read_buffer_402
193 64c R/W global_read_buffer_403
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390 e40 R/W global_write_buffer_400
391 e44 R/W global_write_buffer_401
392 e48 R/W global_write_buffer_402
393 e4c R/W global_write_buffer_403
394 e50 R/W global_write_buffer_404
395 e54 R/W global_write_buffer_405
396 e58 R/W global_write_buffer_406
397 e5c R/W global_write_buffer_407
398 e60 R/W global_write_buffer_408
399 e64 R/W global_write_buffer_409
39a e68 R/W global_write_buffer_410
39b e6c R/W global_write_buffer_411
39c e70 R/W global_write_buffer_412
39d e74 R/W global_write_buffer_413
39e e78 R/W global_write_buffer_414
39f e7c R/W global_write_buffer_415
3a0 e80 R/W global_write_buffer_416
3a1 e84 R/W global_write_buffer_417
3a2 e88 R/W global_write_buffer_418
3a3 e8c R/W global_write_buffer_419
3a4 e90 R/W global_write_buffer_420
3a5 e94 R/W global_write_buffer_421
3a6 e98 R/W global_write_buffer_422
3a7 e9c R/W global_write_buffer_423
3a8 ea0 R/W global_write_buffer_424
3a9 ea4 R/W global_write_buffer_425
3aa ea8 R/W global_write_buffer_426
3ab eac R/W global_write_buffer_427
3ac eb0 R/W global_write_buffer_428
3ad eb4 R/W global_write_buffer_429
3ae eb8 R/W global_write_buffer_430
3af ebc R/W global_write_buffer_431
3b0 ec0 R/W global_write_buffer_432
3b1 ec4 R/W global_write_buffer_433
3b2 ec8 R/W global_write_buffer_434
3b3 ecc R/W global_write_buffer_435
3b4 ed0 R/W global_write_buffer_436
3b5 ed4 R/W global_write_buffer_437
3b6 ed8 R/W global_write_buffer_438
3b7 edc R/W global_write_buffer_439
3b8 ee0 R/W global_write_buffer_440
3b9 ee4 R/W global_write_buffer_441
3ba ee8 R/W global_write_buffer_442
3bb eec R/W global_write_buffer_443
3bc ef0 R/W global_write_buffer_444
3bd ef4 R/W global_write_buffer_445
3be ef8 R/W global_write_buffer_446
3bf efc R/W global_write_buffer_447
3c0 f00 R/W global_write_buffer_448
3c1 f04 R/W global_write_buffer_449
3c2 f08 R/W global_write_buffer_450
3c3 f0c R/W global_write_buffer_451
3c4 f10 R/W global_write_buffer_452
3c5 f14 R/W global_write_buffer_453
3c6 f18 R/W global_write_buffer_454
3c7 f1c R/W global_write_buffer_455
3c8 f20 R/W global_write_buffer_456
3c9 f24 R/W global_write_buffer_457
3ca f28 R/W global_write_buffer_458
3cb f2c R/W global_write_buffer_459
3cc f30 R/W global_write_buffer_460
3cd f34 R/W global_write_buffer_461
3ce f38 R/W global_write_buffer_462
3cf f3c R/W global_write_buffer_463
3d0 f40 R/W global_write_buffer_464
3d1 f44 R/W global_write_buffer_465
3d2 f48 R/W global_write_buffer_466
3d3 f4c R/W global_write_buffer_467
3d4 f50 R/W global_write_buffer_468
3d5 f54 R/W global_write_buffer_469
3d6 f58 R/W global_write_buffer_470
3d7 f5c R/W global_write_buffer_471
3d8 f60 R/W global_write_buffer_472
3d9 f64 R/W global_write_buffer_473
3da f68 R/W global_write_buffer_474
3db f6c R/W global_write_buffer_475
3dc f70 R/W global_write_buffer_476
3dd f74 R/W global_write_buffer_477
3de f78 R/W global_write_buffer_478
3df f7c R/W global_write_buffer_479
3e0 f80 R/W global_write_buffer_480
3e1 f84 R/W global_write_buffer_481
3e2 f88 R/W global_write_buffer_482
3e3 f8c R/W global_write_buffer_483
3e4 f90 R/W global_write_buffer_484
3e5 f94 R/W global_write_buffer_485
3e6 f98 R/W global_write_buffer_486
3e7 f9c R/W global_write_buffer_487
3e8 fa0 R/W global_write_buffer_488
3e9 fa4 R/W global_write_buffer_489
3ea fa8 R/W global_write_buffer_490
3eb fac R/W global_write_buffer_491
3ec fb0 R/W global_write_buffer_492
3ed fb4 R/W global_write_buffer_493
3ee fb8 R/W global_write_buffer_494
3ef fbc R/W global_write_buffer_495
3f0 fc0 R/W global_write_buffer_496
3f1 fc4 R/W global_write_buffer_497
3f2 fc8 R/W global_write_buffer_498
3f3 fcc R/W global_write_buffer_499
3f4 fd0 R/W global_write_buffer_500
3f5 fd4 R/W global_write_buffer_501
3f6 fd8 R/W global_write_buffer_502
3f7 fdc R/W global_write_buffer_503
3f8 fe0 R/W global_write_buffer_504
3f9 fe4 R/W global_write_buffer_505
3fa fe8 R/W global_write_buffer_506
3fb fec R/W global_write_buffer_507
3fc ff0 R/W global_write_buffer_508
3fd ff4 R/W global_write_buffer_509
3fe ff8 R/W global_write_buffer_510
3ff ffc R/W global_write_buffer_511

global_read_buffer_0
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84000
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_1
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84004
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_2
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84008
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_3
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8400c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_4
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84010
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_5
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84014
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_6
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84018
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_7
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8401c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_8
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84020
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_9
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84024
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_10
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84028
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_11
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8402c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_12
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84030
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_13
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84034
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_14
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84038
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_15
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8403c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_16
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84040
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_17
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84044
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_18
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84048
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_19
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8404c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_20
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84050
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_21
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84054
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_22
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84058
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_23
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8405c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_24
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84060
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_25
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84064
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_26
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84068
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_27
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8406c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_28
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84070
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_29
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84074
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_30
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84078
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_31
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8407c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_32
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84080
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_33
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84084
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_34
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84088
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_35
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8408c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_36
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84090
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_37
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84094
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_38
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84098
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_39
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8409c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_40
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_41
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_42
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_43
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_44
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_45
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_46
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_47
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_48
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_49
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_50
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_51
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_52
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_53
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_54
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_55
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_56
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_57
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_58
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_59
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_60
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_61
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_62
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_63
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d840fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_64
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84100
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_65
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84104
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_66
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84108
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_67
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8410c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_68
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84110
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_69
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84114
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_70
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84118
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_71
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8411c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_72
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84120
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_73
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84124
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_74
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84128
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_75
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8412c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_76
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84130
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_77
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84134
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_78
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84138
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_79
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8413c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_80
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84140
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_81
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84144
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_82
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84148
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_83
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8414c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_84
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84150
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_85
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84154
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_86
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84158
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_87
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8415c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_88
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84160
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_89
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84164
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_90
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84168
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_91
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8416c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_92
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84170
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_93
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84174
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_94
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84178
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_95
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8417c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_96
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84180
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_97
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84184
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_98
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84188
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_99
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8418c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_100
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84190
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_101
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84194
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_102
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84198
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_103
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8419c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_104
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_105
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_106
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_107
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_108
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_109
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_110
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_111
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_112
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_113
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_114
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_115
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_116
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_117
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_118
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_119
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_120
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_121
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_122
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_123
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_124
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_125
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_126
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_127
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d841fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_128
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84200
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_129
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84204
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_130
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84208
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_131
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8420c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_132
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84210
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_133
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84214
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_134
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84218
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_135
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8421c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_136
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84220
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_137
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84224
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_138
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84228
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_139
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8422c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_140
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84230
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_141
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84234
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_142
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84238
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_143
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8423c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_144
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84240
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_145
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84244
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_146
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84248
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_147
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8424c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_148
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84250
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_149
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84254
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_150
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84258
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_151
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8425c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_152
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84260
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_153
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84264
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_154
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84268
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_155
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8426c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_156
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84270
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_157
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84274
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_158
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84278
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_159
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8427c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_160
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84280
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_161
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84284
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_162
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84288
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_163
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8428c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_164
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84290
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_165
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84294
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_166
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84298
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_167
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8429c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_168
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_169
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_170
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_171
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_172
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_173
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_174
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_175
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_176
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_177
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_178
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_179
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_180
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_181
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_182
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_183
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_184
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_185
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_186
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_187
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_188
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_189
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_190
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_191
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d842fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_192
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84300
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_193
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84304
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_194
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84308
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_195
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8430c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_196
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84310
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_197
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84314
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_198
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84318
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_199
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8431c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_200
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84320
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_201
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84324
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_202
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84328
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_203
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8432c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_204
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84330
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_205
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84334
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_206
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84338
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_207
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8433c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_208
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84340
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_209
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84344
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_210
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84348
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_211
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8434c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_212
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84350
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_213
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84354
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_214
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84358
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_215
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8435c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_216
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84360
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_217
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84364
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_218
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84368
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_219
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8436c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_220
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84370
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_221
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84374
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_222
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84378
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_223
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8437c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_224
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84380
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_225
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84384
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_226
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84388
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_227
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8438c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_228
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84390
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_229
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84394
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_230
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84398
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_231
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8439c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_232
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_233
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_234
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_235
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_236
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_237
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_238
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_239
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_240
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_241
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_242
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_243
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_244
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_245
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_246
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_247
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_248
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_249
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_250
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_251
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_252
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_253
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_254
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_255
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d843fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_256
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84400
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_257
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84404
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_258
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84408
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_259
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8440c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_260
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84410
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_261
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84414
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_262
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84418
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_263
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8441c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_264
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84420
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_265
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84424
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_266
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84428
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_267
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8442c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_268
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84430
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_269
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84434
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_270
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84438
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_271
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8443c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_272
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84440
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_273
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84444
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_274
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84448
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_275
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8444c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_276
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84450
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_277
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84454
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_278
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84458
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_279
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8445c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_280
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84460
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_281
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84464
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_282
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84468
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_283
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8446c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_284
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84470
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_285
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84474
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_286
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84478
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_287
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8447c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_288
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84480
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_289
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84484
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_290
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84488
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_291
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8448c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_292
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84490
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_293
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84494
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_294
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84498
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_295
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8449c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_296
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_297
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_298
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_299
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_300
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_301
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_302
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_303
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_304
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_305
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_306
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_307
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_308
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_309
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_310
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_311
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_312
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_313
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_314
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_315
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_316
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_317
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_318
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_319
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d844fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_320
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84500
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_321
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84504
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_322
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84508
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_323
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8450c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_324
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84510
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_325
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84514
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_326
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84518
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_327
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8451c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_328
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84520
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_329
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84524
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_330
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84528
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_331
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8452c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_332
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84530
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_333
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84534
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_334
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84538
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_335
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8453c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_336
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84540
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_337
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84544
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_338
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84548
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_339
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8454c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_340
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84550
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_341
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84554
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_342
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84558
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_343
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8455c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_344
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84560
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_345
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84564
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_346
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84568
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_347
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8456c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_348
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84570
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_349
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84574
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_350
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84578
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_351
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8457c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_352
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84580
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_353
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84584
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_354
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84588
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_355
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8458c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_356
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84590
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_357
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84594
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_358
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84598
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_359
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8459c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_360
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_361
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_362
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_363
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_364
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_365
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_366
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_367
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_368
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_369
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_370
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_371
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_372
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_373
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_374
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_375
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_376
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_377
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_378
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_379
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_380
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_381
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_382
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_383
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d845fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_384
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84600
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_385
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84604
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_386
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84608
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_387
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8460c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_388
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84610
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_389
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84614
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_390
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84618
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_391
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8461c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_392
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84620
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_393
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84624
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_394
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84628
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_395
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8462c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_396
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84630
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_397
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84634
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_398
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84638
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_399
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8463c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_400
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84640
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_401
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84644
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_402
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84648
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_403
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8464c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_404
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84650
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_405
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84654
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_406
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84658
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_407
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8465c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_408
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84660
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_409
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84664
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_410
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84668
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_411
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8466c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_412
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84670
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_413
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84674
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_414
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84678
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_415
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8467c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_416
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84680
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_417
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84684
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_418
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84688
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_419
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8468c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_420
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84690
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_421
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84694
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_422
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84698
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_423
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8469c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_424
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_425
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_426
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_427
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_428
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_429
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_430
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_431
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_432
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_433
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_434
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_435
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_436
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_437
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_438
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_439
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_440
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_441
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_442
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_443
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_444
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_445
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_446
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_447
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d846fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_448
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84700
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_449
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84704
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_450
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84708
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_451
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8470c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_452
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84710
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_453
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84714
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_454
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84718
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_455
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8471c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_456
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84720
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_457
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84724
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_458
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84728
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_459
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8472c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_460
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84730
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_461
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84734
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_462
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84738
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_463
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8473c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_464
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84740
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_465
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84744
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_466
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84748
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_467
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8474c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_468
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84750
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_469
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84754
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_470
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84758
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_471
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8475c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_472
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84760
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_473
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84764
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_474
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84768
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_475
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8476c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_476
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84770
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_477
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84774
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_478
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84778
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_479
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8477c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_480
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84780
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_481
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84784
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_482
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84788
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_483
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8478c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_484
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84790
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_485
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84794
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_486
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d84798
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_487
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d8479c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_488
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_489
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_490
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_491
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_492
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_493
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_494
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_495
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_496
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_497
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_498
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_499
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_500
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_501
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_502
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_503
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_504
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_505
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_506
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_507
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_508
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_509
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_510
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_read_buffer_511
read: get read buffer number
write reset buffer states
R/W
0x00000003
Address : 0x07d847fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "11"
val
read: read buffer number[0,1,2] , [3] = empty-no buffer


global_write_buffer_0
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84800
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_1
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84804
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_2
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84808
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_3
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8480c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_4
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84810
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_5
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84814
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_6
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84818
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_7
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8481c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_8
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84820
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_9
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84824
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_10
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84828
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_11
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8482c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_12
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84830
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_13
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84834
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_14
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84838
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_15
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8483c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_16
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84840
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_17
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84844
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_18
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84848
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_19
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8484c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_20
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84850
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_21
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84854
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_22
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84858
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_23
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8485c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_24
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84860
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_25
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84864
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_26
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84868
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_27
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8486c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_28
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84870
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_29
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84874
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_30
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84878
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_31
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8487c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_32
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84880
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_33
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84884
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_34
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84888
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_35
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8488c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_36
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84890
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_37
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84894
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_38
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84898
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_39
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8489c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_40
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_41
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_42
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_43
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_44
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_45
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_46
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_47
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_48
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_49
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_50
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_51
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_52
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_53
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_54
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_55
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_56
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_57
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_58
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_59
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_60
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_61
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_62
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_63
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d848fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_64
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84900
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_65
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84904
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_66
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84908
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_67
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8490c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_68
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84910
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_69
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84914
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_70
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84918
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_71
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8491c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_72
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84920
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_73
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84924
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_74
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84928
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_75
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8492c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_76
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84930
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_77
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84934
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_78
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84938
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_79
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8493c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_80
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84940
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_81
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84944
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_82
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84948
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_83
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8494c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_84
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84950
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_85
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84954
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_86
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84958
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_87
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8495c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_88
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84960
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_89
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84964
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_90
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84968
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_91
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8496c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_92
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84970
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_93
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84974
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_94
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84978
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_95
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8497c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_96
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84980
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_97
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84984
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_98
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84988
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_99
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8498c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_100
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84990
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_101
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84994
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_102
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84998
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_103
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d8499c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_104
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849a0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_105
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849a4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_106
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849a8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_107
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849ac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_108
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849b0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_109
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849b4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_110
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849b8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_111
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849bc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_112
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849c0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_113
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849c4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_114
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849c8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_115
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849cc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_116
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_117
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849d4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_118
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849d8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_119
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849dc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_120
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849e0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_121
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_122
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849e8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_123
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849ec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_124
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849f0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_125
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849f4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_126
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849f8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_127
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d849fc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_128
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_129
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_130
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_131
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_132
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_133
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_134
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_135
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_136
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_137
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_138
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_139
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_140
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_141
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_142
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_143
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_144
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_145
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_146
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_147
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_148
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_149
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_150
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_151
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_152
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_153
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_154
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_155
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_156
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_157
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_158
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_159
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_160
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_161
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_162
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_163
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_164
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_165
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_166
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_167
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84a9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_168
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84aa0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_169
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84aa4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_170
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84aa8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_171
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84aac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_172
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ab0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_173
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ab4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_174
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ab8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_175
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84abc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_176
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ac0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_177
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ac4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_178
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ac8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_179
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84acc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_180
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ad0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_181
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ad4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_182
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ad8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_183
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84adc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_184
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ae0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_185
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ae4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_186
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ae8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_187
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84aec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_188
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84af0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_189
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84af4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_190
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84af8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_191
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84afc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_192
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_193
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_194
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_195
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_196
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_197
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_198
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_199
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_200
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_201
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_202
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_203
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_204
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_205
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_206
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_207
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_208
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_209
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_210
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_211
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_212
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_213
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_214
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_215
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_216
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_217
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_218
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_219
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_220
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_221
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_222
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_223
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_224
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_225
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_226
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_227
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_228
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_229
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_230
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_231
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84b9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_232
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ba0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_233
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ba4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_234
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ba8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_235
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_236
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bb0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_237
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bb4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_238
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bb8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_239
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bbc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_240
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bc0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_241
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bc4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_242
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bc8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_243
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bcc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_244
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bd0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_245
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bd4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_246
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bd8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_247
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bdc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_248
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84be0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_249
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84be4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_250
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84be8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_251
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_252
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bf0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_253
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bf4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_254
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bf8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_255
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84bfc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_256
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_257
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_258
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_259
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_260
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_261
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_262
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_263
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_264
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_265
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_266
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_267
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_268
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_269
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_270
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_271
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_272
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_273
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_274
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_275
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_276
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_277
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_278
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_279
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_280
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_281
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_282
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_283
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_284
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_285
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_286
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_287
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_288
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_289
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_290
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_291
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_292
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_293
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_294
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_295
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84c9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_296
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ca0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_297
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ca4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_298
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ca8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_299
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_300
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cb0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_301
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cb4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_302
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cb8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_303
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cbc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_304
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cc0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_305
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cc4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_306
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cc8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_307
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ccc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_308
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cd0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_309
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cd4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_310
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cd8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_311
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cdc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_312
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ce0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_313
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ce4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_314
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ce8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_315
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_316
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cf0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_317
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cf4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_318
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cf8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_319
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84cfc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_320
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_321
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_322
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_323
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_324
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_325
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_326
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_327
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_328
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_329
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_330
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_331
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_332
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_333
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_334
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_335
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_336
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_337
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_338
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_339
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_340
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_341
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_342
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_343
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_344
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_345
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_346
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_347
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_348
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_349
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_350
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_351
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_352
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_353
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_354
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_355
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_356
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_357
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_358
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_359
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84d9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_360
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84da0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_361
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84da4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_362
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84da8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_363
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_364
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84db0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_365
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84db4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_366
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84db8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_367
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dbc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_368
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dc0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_369
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dc4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_370
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dc8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_371
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dcc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_372
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dd0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_373
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dd4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_374
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dd8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_375
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ddc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_376
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84de0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_377
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84de4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_378
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84de8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_379
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_380
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84df0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_381
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84df4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_382
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84df8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_383
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84dfc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_384
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_385
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_386
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_387
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_388
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_389
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_390
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_391
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_392
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_393
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_394
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_395
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_396
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_397
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_398
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_399
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_400
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_401
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_402
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_403
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_404
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_405
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_406
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_407
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_408
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_409
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_410
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_411
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_412
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_413
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_414
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_415
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_416
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_417
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_418
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_419
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_420
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_421
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_422
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_423
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84e9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_424
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ea0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_425
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ea4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_426
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ea8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_427
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84eac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_428
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84eb0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_429
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84eb4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_430
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84eb8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_431
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ebc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_432
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ec0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_433
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ec4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_434
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ec8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_435
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ecc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_436
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ed0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_437
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ed4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_438
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ed8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_439
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84edc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_440
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ee0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_441
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ee4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_442
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ee8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_443
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84eec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_444
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ef0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_445
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ef4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_446
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ef8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_447
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84efc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_448
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f00
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_449
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_450
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f08
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_451
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f0c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_452
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f10
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_453
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f14
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_454
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f18
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_455
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f1c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_456
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f20
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_457
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f24
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_458
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f28
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_459
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f2c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_460
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f30
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_461
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_462
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f38
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_463
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f3c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_464
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f40
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_465
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f44
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_466
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f48
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_467
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f4c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_468
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f50
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_469
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f54
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_470
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f58
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_471
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f5c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_472
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f60
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_473
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f64
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_474
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f68
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_475
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f6c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_476
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f70
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_477
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f74
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_478
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f78
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_479
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f7c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_480
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f80
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_481
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f84
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_482
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f88
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_483
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f8c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_484
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f90
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_485
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_486
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f98
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_487
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84f9c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_488
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fa0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_489
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fa4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_490
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fa8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_491
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fac
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_492
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fb0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_493
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fb4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_494
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fb8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_495
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fbc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_496
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fc0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_497
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fc4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_498
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fc8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_499
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fcc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_500
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fd0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_501
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fd4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_502
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fd8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_503
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fdc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_504
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fe0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_505
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fe4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_506
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fe8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_507
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84fec
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_508
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ff0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_509
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ff4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_510
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ff8
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]


global_write_buffer_511
read: get write buffer number and release write buffer
write: nothing
R/W
0x00000000
Address : 0x07d84ffc
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
val
read: write buffer number[0,1,2]



Base Address Area: stm_apb

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-300 0-c00 -  reserved
301 c04 W stm_apb_stmdmastartr
302 c08 W stm_apb_stmdmastopr
303 c0c R stm_apb_stmdmastatr
304 c10 R/W stm_apb_stmdmactlr
305-33e c14-cf8 -  reserved
33f cfc R stm_apb_stmdmaidr
340 d00 R/W stm_apb_stmheer
341-347 d04-d1c -  reserved
348 d20 R/W stm_apb_stmheter
349-357 d24-d5c -  reserved
358 d60 R/W stm_apb_stmhebsr
359 d64 R/W stm_apb_stmhemcr
35a d68 R/W stm_apb_stmheextmuxr
35b-37c d6c-df0 -  reserved
37d df4 R stm_apb_stmhemastr
37e df8 R stm_apb_stmhefeat1r
37f dfc R stm_apb_stmheidr
380 e00 R/W stm_apb_stmsper
381-387 e04-e1c -  reserved
388 e20 R/W stm_apb_stmspter
389-397 e24-e5c -  reserved
398 e60 R/W stm_apb_stmspscr
399 e64 R/W stm_apb_stmspmscr
39a e68 R/W stm_apb_stmspoverrider
39b e6c R/W stm_apb_stmspmoverrider
39c e70 R/W stm_apb_stmsptrigcsr
39d-39f e74-e7c -  reserved
3a0 e80 R/W stm_apb_stmtcsr
3a1 e84 W stm_apb_stmtsstimr
3a2 e88 -  reserved
3a3 e8c R/W stm_apb_stmtsfreqr
3a4 e90 R/W stm_apb_stmsyncr
3a5 e94 R/W stm_apb_stmauxcr
3a6-3a7 e98-e9c -  reserved
3a8 ea0 R stm_apb_stmfeat1r
3a9 ea4 R stm_apb_stmfeat2r
3aa ea8 R stm_apb_stmfeat3r
3ab-3b9 eac-ee4 -  reserved
3ba ee8 W stm_apb_stmittrigger
3bb eec W stm_apb_stmitatbdata0
3bc ef0 R stm_apb_stmitatbctr2
3bd ef4 W stm_apb_stmitatbid
3be ef8 W stm_apb_stmitatbctr0
3bf efc -  reserved
3c0 f00 R/W stm_apb_stmitctrl
3c1-3e7 f04-f9c -  reserved
3e8 fa0 R/W stm_apb_stmclaimset
3e9 fa4 R/W stm_apb_stmclaimclr
3ea-3eb fa8-fac -  reserved
3ec fb0 W stm_apb_stmlar
3ed fb4 R stm_apb_stmlsr
3ee fb8 R stm_apb_stmauthstatus
3ef fbc R stm_apb_stmdevarch
3f0-3f1 fc0-fc4 -  reserved
3f2 fc8 R stm_apb_stmdevid
3f3 fcc R stm_apb_stmdevtype
3f4 fd0 R stm_apb_stmpidr4
3f5-3f7 fd4-fdc -  reserved
3f8 fe0 R stm_apb_stmpidr0
3f9 fe4 R stm_apb_stmpidr1
3fa fe8 R stm_apb_stmpidr2
3fb fec R stm_apb_stmpidr3
3fc ff0 R stm_apb_stmcidr0
3fd ff4 R stm_apb_stmcidr1
3fe ff8 R stm_apb_stmcidr2
3ff ffc R stm_apb_stmcidr3
400-3fff 1000-fffc -  reserved

stm_apb_stmdmastartr
DMA Transfer Start Register
W
0x00000000
Address : 0x10170c04
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
start
Start a DMA transfer


stm_apb_stmdmastopr
DMA Transfer Stop Register
W
0x00000000
Address : 0x10170c08
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
stop
Stop a DMA transfer


stm_apb_stmdmastatr
DMA Transfer Status Register
R
Address : 0x10170c0c
Bits Name Description
31 - 1 -
 reserved
0 status
Status of the DMA peripheral request interface:
b0 = interface is idle
b1 = interface is active.


stm_apb_stmdmactlr
DMA Control Register
R/W
0x00000000
Address : 0x10170c10
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 2 "00"
sens
Determines the sensitivity of the DMA request to the current buffer level in the STM:
0b00 Buffer is < 25% full
0b01 Buffer is < 50% full
0b10 Buffer is < 75% full
0b11 Buffer is < 100% full
1 - 0 0
-
 reserved


stm_apb_stmdmaidr
DMA ID Register
R
Address : 0x10170cfc
Bits Name Description
31 - 12 -
 reserved
11 - 8 vendspec
Identifies vendor-specific modifications or mappings
7 - 4 classrev
Identifies the revision of the programmers model
3 - 0 class
Identifies the programmers model:
0b0010   Hardware event control.


stm_apb_stmheer
Hardware Event Enable Register
R/W
0x00000000
Address : 0x10170d00
Bits Reset value Name Description
31 - 0 0x0
hee
Hardware event enable, with one bit per hardware event:
b0 = hardware event disabled
b1 = hardware event enabled.
Reset value is UNKNOWN.


stm_apb_stmheter
Hardware Event Trigger Enable Register
R/W
0x00000000
Address : 0x10170d20
Bits Reset value Name Description
31 - 0 0x0
hete
Bit mask to enable trigger generation from the hardware events, with one bit per hardware event:
b0 = disabled
b1 = enabled.
Reset value is UNKNOWN.


stm_apb_stmhebsr
Hardware Event Bypass Status Register
R/W
0x00000000
Address : 0x10170d60
Bits Reset value Name Description
31 - 0 0x0
hebs
Selects the bank of 32 hardware events to control.
Reset value of each bit is b0.


stm_apb_stmhemcr
Hardware Event Master Control Register
R/W
0x00000000
Address : 0x10170d64
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
atbtrigen
ATB trigger enable on events being monitored using the STMHETER.
When set, this bit enables the STM to use the ATID value of 0x7D.
Reset value is UNKNOWN.
This bit is implemented only when the STMFEAT1R.TRACEBUS is b0001.
6 "0"
trigclear
When TRIGCTL indicates single-shot mode, this bit is used to clear TRIGSTATUS:
b0 = no effect
b1 = clears TRIGSTATUS if TRIGSTATUS is b1.
Writing a b1 to this bit when in multi-shot mode is UNPREDICTABLE.
5 "0"
trigstatus
When TRIGCTL indicates single-shot mode, this indicates whether the single trigger has occurred:
b0 = trigger has not occurred
b1 = trigger has occurred.
In multi-shot mode this bit is always UNKNOWN.
4 "0"
trigctl
Trigger Control:
b0 = triggers are multi-shot
b1 = triggers are single-shot.
Reset value is UNKNOWN.
This bit is implemented only when the STMFEAT1R.TRIGCTL is b10.
3 0
-
 reserved
2 "0"
errdetect
Enable error detection on the hardware event tracing:
b0 = disabled
b1 = enabled.
If an event cannot be traced, this bit enables indication of the lost information.
Reset value is UNKNOWN.
1 "0"
compen
Enable leading zero suppression of hardware event data values in the trace stream:
b0 = disabled
b1 = enabled.
Reset value is UNKNOWN.
0 "0"
en
Enable Hardware Event Tracing:
b0 = disabled
b1 = enabled.
To enable hardware event tracing, the STMTCSR.EN bit must also be b1.
Reset value is b0.


stm_apb_stmheextmuxr
Hardware Event External Multiplex Control Register
R/W
0x00000000
Address : 0x10170d68
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
extmux
Specifies the value that the optional external multiplexing logic uses to select the hardware events to connect to the STM.
The value of this register is output from the STM on the HEEXTMUX[7:0] signals.
The behavior of the multiplexing logic is IMPLEMENTATION DEFINED.
This field is reset to zero.


stm_apb_stmhemastr
Hardware Event Master Number Register
R
Address : 0x10170df4
Bits Name Description
31 - 16 -
 reserved
15 - 0 master
The master number for hardware event trace.
Reset value is IMPLEMENTATION DEFINED.


stm_apb_stmhefeat1r
Hardware Event Features 1 Register
R
Address : 0x10170df8
Bits Name Description
31 -
 reserved
30 - 28 heextmuxsize
The size of the STMHEEXTMUXR.EXTMUX bit field. 0b011 ..8 bits wide.
27 - 24 -
 reserved
23 - 15 numhe
Number of hardware events supported. 0 to 256 events are supported.
14 - 6 -
 reserved
5 - 4 hecomp
Data compression on hardware event tracing support:
b00 = Data compression support is not defined here. Use the part number of the device to determine if data compression is supported.
b01 = No data compression supported.
b10 = Data compression always enabled
b11 = Data compression support is programmable. STMHEMCR.COMPEN is implemented.
3 hemastr
STMHEMASTR support:
b0 = STMHEMASTR is RO.
b1 = STMHEMASTR is RW.
2 heerr
Hardware event error detection support:
b0 = Hardware event error detection not implemented.
b1 = Hardware event error detection implemented. STMHEMCR.ERRDETECT is implemented.
1 -
 reserved
0 heter
STMHETER support:
b0 = STMHETER is not implemented.
b1 = STMHETER is implemented.


stm_apb_stmheidr
Hardware Event ID Register
R
Address : 0x10170dfc
Bits Name Description
31 - 12 -
 reserved
11 - 8 vendspec
Identifies vendor-specific modifications or mappings:
0b0000   Vendor-specific information.
7 - 4 classrev
Identifies the revision of the programmers model:
0b0001   Revision.
3 - 0 class
Identifies the programmers model:
0b0001   Hardware event control.


stm_apb_stmsper
Stimulus Port Enable Register
R/W
0x00000000
Address : 0x10170e00
Bits Reset value Name Description
31 - 0 0x0
spe
Stimulus port enable, with one bit per stimulus port:
b0 = stimulus port disabled
b1 = stimulus port enabled.
The reset value of each bit is b0.
Note: Bit [0] applies to the lowest-numbered port and bit [31] to the highest-numbered port.


stm_apb_stmspter
Stimulus Port Trigger Enable Register
R/W
0x00000000
Address : 0x10170e20
Bits Reset value Name Description
31 - 0 0x0
spte
Bit mask to enable trigger generation from the stimulus port registers, with one bit per stimulus
port register:
b0 = disabled
b1 = enabled.
The reset value of each bit is b0.
Note: Bit [0] applies to the lowest-numbered port and bit [31] to the highest-numbered port.


stm_apb_stmspscr
Stimulus Port Selection Configuration Register
R/W
0x00000000
Address : 0x10170e60
Bits Reset value Name Description
31 - 20 0x0
portsel
Port Selection. This field defines which stimulus ports the STMSPTER and/or STMSPER apply to.
The size of this field is defined by the number of implemented stimulus ports.
The reset value is UNKNOWN.
19 - 2 0
-
 reserved
1 - 0 "00"
portctl
This defines how the port selection is applied:
b00 = Port selection not used
b01 = Port selection applies only to the STMSPTER
b10 = Reserved
b11 = Port selection applies to both the STMSPER and STMSPTER.
The reset value is b00.


stm_apb_stmspmscr
Stimulus Port Master Select Configuration Register
R/W
0x00000000
Address : 0x10170e64
Bits Reset value Name Description
31 - 15 0x0
mastsel
Master Selection. This field defines which master the STMSPSCR applies to.
The size of this field is defined by the number of implemented masters.
The reset value is UNKNOWN.
14 - 1 0
-
 reserved
0 "0"
mastctl
This bit defines how the master is applied:
b0 = Master selection not used
b1 = Master selection applies to the STMSPSCR.
The reset value is b0.


stm_apb_stmspoverrider
Stimulus Port Override Register
R/W
0x00000000
Address : 0x10170e68
Bits Reset value Name Description
31 - 15 0x0
portsel
Port selection.
This field defines which stimulus ports the override controls apply to.
The size of this field is defined by the number of implemented stimulus ports.
The reset value is UNKNOWN.
14 - 3 0
-
 reserved
2 "0"
overts
Timestamping override.
This override requests all stimulus port writes that cause trace to be traced with a timestamp (where possible). As with normal operation, this does not ensure all packets are generated with timestamps.
This field is independent of OVERCTL and PORTSEL and STMSPMOVERRIDER.
b0 = override not enabled
b1 = override enabled.
The reset value is b0.
1 - 0 "00"
overctl
This defines how the port selection is applied:
b00 = override controls disabled
b01 = ports selected by PORTSEL always behave as guaranteed transactions
b10 = ports selected by PORTSEL always behave as invariant timing transactions
b11 = Reserved.
The reset value is b00.


stm_apb_stmspmoverrider
Stimulus Port Master Override Register
R/W
0x00000000
Address : 0x10170e6c
Bits Reset value Name Description
31 - 15 0x0
mastsel
Master selection.
This field defines which master the override controls apply to.
The size of this field is defined by the number of implemented masters.
The reset value is UNKNOWN.
14 - 1 0
-
 reserved
0 "0"
mastctl
This bit defines how the master selection is applied:
b0 = Master selection not enabled. STMSPOVERRIDER applies equally to all masters.
b1 = Master selection enabled. STMSPOVERRIDER applies to the masters selected by MASTSEL.
The reset value is b0.


stm_apb_stmsptrigcsr
Stimulus Port Trigger Control and Status Register
R/W
0x00000000
Address : 0x10170e70
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
atbtrigen_dir
ATB trigger enable on direct writes to TRIG locations in an Extended Stimulus Port.
When set, this bit enables the STM to use the ATID value of 0x7D when software writes to the TRIG locations.
The reset value is b0.
3 "0"
atbtrigen_te
ATB trigger enable on writes to Stimulus Ports being monitored using the STMSPTER.
When set, this bit enables the STM to use the ATID value of 0x7D when software writes to an enabled Stimulus Port.
The reset value is b0.
2 "0"
trigclear
When TRIGCTL indicates single-shot mode, this bit is used to clear TRIGSTATUS:
b0 = no effect
b1 = clears TRIGSTATUS if TRIGSTATUS is b1.
Writing a b1 to this bit when in multi-shot mode is Unpredictable.
1 "0"
trigstatus
When TRIGCTL indicates single-shot mode, this bit indicates whether the single trigger has occurred:
b0 = trigger has not occurred
b1 = trigger has occurred.
In multi-shot mode this bit is always UNK/SBZP.
0 "0"
trigctl
Trigger control:
b0 = triggers are multi-shot
b1 = triggers are single-shot
The reset value is b0.


stm_apb_stmtcsr
Trace Control and Status Register
R/W
0x00000000
Address : 0x10170e80
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
busy
STM is busy, for example the STM trace FIFO is not empty.
The reset value is IMPLEMENTATION SPECIFIC.
22 - 16 "0000000"
traceid
TRACEID[6:0] value.
The reset value is UNKNOWN.
15 - 10 0
-
 reserved
9 - 8 "00"
tsprescale
Timestamp prescaler. The reference clock source is selected by SWOEN:
b00 = no prescaling
b01 = divide by 4
b10 = divide by 16
b11 = divide by 64.
The reset value is b00.
7 - 6 0
-
 reserved
5 "0"
compen
Compression enable for stimulus ports:
b0 = compression disabled, data transfers are transmitted at the size of the transaction
b1 = compression enabled, data transfers are compressed to save bandwidth.
The reset value is b0.
4 "0"
swoen
Enables asynchronous-specific usage model for timestamps, when TSEN==b1:
b0 = Timestamp counter uses a system clock and counts continuously.
b1 = Timestamp counter uses a clock from an external trace output interface.
The timestamp counter is held in reset while the trace output line is idle.
The reset value is b0.
3 "0"
hwten
Enable hardware event trace packet emission.
The reset value is b0.
2 "0"
syncen
Enable synchronization packets. Synchronization period is defined by the STMSYNCR, if implemented, or by another IMPLEMENTATION DEFINED mechanism.
The reset value is b0c.
1 "0"
tsen
Enable timestamps. Timestamp behavior might be qualified by SWOEN.
When this bit is zero no timestamps are generated and, when using STPv2, FREQ packets are not generated.
The reset value is b0.
0 "0"
en
Global STM enable. Always present.
The reset value is b0.


stm_apb_stmtsstimr
Timestamp Stimulus Register
W
0x00000000
Address : 0x10170e84
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
forcets
Force timestamp stimulus. A write to this register with this bit as b1 requests the next stimulus port write which causes trace to be upgraded to have a timestamp.
Writes with this bit b0 are ignored.


stm_apb_stmtsfreqr
Timestamp Frequency Register
R/W
0x00000000
Address : 0x10170e8c
Bits Reset value Name Description
31 - 0 0x0
freq
The timestamp frequency in Hz.
The reset value is IMPLEMENTATION DEFINED.


stm_apb_stmsyncr
Synchronization Control Register
R/W
0x00000000
Address : 0x10170e90
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
mode
Mode control:
b0 = COUNT[11:0] defines a value N. Synchronization period is N bytes.
b1 = COUNT[11:7] defines a value N. Synchronization period is 2N bytes.
N must be in the range of 12 to 27 inclusive and other values are UNPREDICTABLE.
The reset value is b0.
11 - 0 0x0
count
Counter value for the number of bytes between synchronization packets.
Reads return the value of this register.
The reset value is IMPLEMENTATION DEFINED.


stm_apb_stmauxcr
Auxiliary Control Register
R/W
0x00000000
Address : 0x10170e94
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
qhwevoverride
Low-power interface override when hardware event tracing is enabled:
0b0    The STM can accept a quiescence request on the STM low-power interface when the STMHEMCR.EN bit is set to 0b1.
0b1    If the STMHEMCR.EN bit is set to 0b1, all quiescence requests on the STM low-power interface are denied.
Reset value is 0b0.
6 - 3 0
-
 reserved
2 "0"
priorinvdis
Controls arbitration between the AXI interface and the hardware event observation interface during flush:
0b0    Priority inversion. When the AXI flush completes, the hardware event observation interface gets priority until the hardware event observation interface flush completes.
0b1    Priority inversion disabled. The AXI always has priority over the hardware event observation interface.
Reset value is 0b0.
1 "0"
asyncpe
ASYNC priority:
0b0    Always lower than trace.
0b1    Escalates on second synchronization request.
Reset value is 0b0.
0 "0"
fifoaf
Auto-flush:
0b0    Disabled.
0b1    Enabled. The STM automatically drains all data even if the ATB interface is not fully utilized.
Reset value is 0b0.


stm_apb_stmfeat1r
Features 1 Register
R
Address : 0x10170ea0
Bits Name Description
31 - 24 -
 reserved
23 - 22 swoen
STMTCSR.SWOEN support:
b00 = Support not defined here. Support for STMTCSR.SWOEN can be detected by direct access to the STMTCSR.
b01 = STMTCSR.SWOEN not implemented.
b10 = STMTCSR.SWOEN implemented.
21 - 20 syncen
STMTCSR.SYNCEN support:
b00 = Support not defined here. Support for STMTCSR.SYNCEN can be detected by direct access to the STMTCSR.
b01 = STMTCSR.SYNCEN not implemented and always reads as b0.
b10 = STMTCSR.SYNCEN implemented but always reads as b1.
b11 = STMTCSR.SYNCEN implemented and is writeable.
19 - 18 hwten
STMTCSR.HWTEN support:
b00 = Support not defined here. Support for STMTCSR.HWTEN can be detected by direct access to the STMTCSR.
b01 = STMTCSR.HWTEN not implemented.
b10 = STMTCSR.HWTEN implemented.
17 - 16 tsprescale
Timestamp prescale support:
b00 = Support not defined here. Support for timestamp prescaling can be detected by direct access to the STMTCSR.
b01 = Timestamp prescale not implemented.
b10 = Timestamp prescale implemented.
15 - 14 trigctl
Trigger control support:
b00 = Trigger support not defined here.
b01 = Multi-shot triggers supported only.
b10 = Multi-shot and single-shot triggers supported. STMSPTRIGCSR.TRIGCTL implemented.
13 - 10 tracebus
Trace bus support:
b0000 = CoreSight ATB implemented. STMTCSR.TRACEID implemented.
b0001 = CoreSight ATB plus ATB trigger support implemented.
STMTCSR.TRACEID and STMSPTRIGCSR.ATBTRIGEN_DIR and STMSPTRIGCSR.ATBTRIGEN_TE implemented.
9 - 8 sync
STMSYNCR support:
b00 = Support not defined here. Support for the STMSYNCR can be detected by direct access to the STMSYNCR.
b01 = STMSYNCR not implemented.
b10 = STMSYNCR implemented without MODE control.
b11 = STMSYNCR implemented with MODE control.
7 forcets
STMTSSTIMR support:
b0 = STMTSSTIMR bit [0] not implemented.
b1 = STMTSSTIMR bit [0] implemented.
6 tsfreq
Timestamp frequency indication configuration:
b0 = STMTSFREQR is read-only.
b1 = STMTSFREQR is read-write.
5 - 4 ts
Timestamp support:
b00 = Differential timestamps implemented.
b01 = Absolute timestamps implemented.
b10 = Timestamping not implemented.
3 - 0 prot
Protocol type:
b0001 = STPv2.


stm_apb_stmfeat2r
Features 2 Register
R
Address : 0x10170ea4
Bits Name Description
31 - 18 -
 reserved
17 - 16 sptype
TStimulus Port type support:
b00 = Only Basic Stimulus Ports implemented.
b01 = Only Extended Stimulus Ports implemented.
b10 = Both Basic and Extended Stimulus Ports implemented.
15 - 12 dsize
Fundamental data size:
b0000 = 32-bit data.
b0001 = 64-bit data.
11 -
 reserved
10 - 9 sptrtype
Stimulus Port Transaction Type support:
b00 = Only invariant timing transactions are supported.
b01 = Only guaranteed transactions are supported.
b10 = Both invariant timing and guaranteed transactions are supported.
8 - 7 privmask
STMPRIVMASKR support:
b00 = STMPRIVMASKR support not defined here. Support for the STMPRIVMASKR can be detected by direct access to the STMPRIVMASKR.
b01 = STMPRIVMASKR not implemented.
b10 = STMPRIVMASKR implemented.
6 spoverride
STMSPOVERRIDER and STMSPMOVERRIDER support:
b0 = STMSPOVERRIDER and STMSPMOVERRIDER not implemented.
b1 = STMSPOVERRIDER and STMSPMOVERRIDER implemented.
5 - 4 spcomp
Data compression on stimulus ports support:
b00 = Data compression support is not defined here. Use the part number of the device to determine if data compression is supported.
b01 = No data compression supported.
b10 = Data compression always enabled.
b11 = Data compression support is programmable. STMTCSR.COMPEN is implemented.
3 -
 reserved
2 sper
STMSPER presence:
b0 = STMSPER is implemented.
1 - 0 spter
STMSPTER support:
b00 = STMSPTER presence is not indicated here, check the STMSPTER.
b01 = STMSPTER is not implemented.
b10 = STMSPTER is implemented.


stm_apb_stmfeat3r
Features 3 Register
R
Address : 0x10170ea8
Bits Name Description
31 - 16 -
 reserved
15 - 0 nummast
The number of stimulus port masters implemented, minus 1. For example:
0x0000 = 1 master implemented
0x00FF = 256 masters implemented.


stm_apb_stmittrigger
Integration Test for Cross-Trigger Outputs Register
W
0x00000000
Address : 0x10170ee8
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
asyncout_w
Sets the value of the ASYNCOUT output signal in integration mode:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
2 "0"
trigouthete_w
Sets the value of the TRIGOUTHETE output signal in integration mode:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
1 "0"
trigoutsw_w
Sets the value of the TRIGOUTSW output signal in integration mode:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
0 "0"
trigoutspte_w
Sets the value of the TRIGOUTSPTE output signal in integration mode:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.


stm_apb_stmitatbdata0
Integration Mode ATB Data 0 register
W
0x00000000
Address : 0x10170eec
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
atdatam63_w
Sets the value of the ATDATAM[63] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
7 "0"
atdatam55_w
Sets the value of the ATDATAM[55] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
6 "0"
atdatam47_w
Sets the value of the ATDATAM[47] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
5 "0"
atdatam39_w
Sets the value of the ATDATAM[39] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
4 "0"
atdatam31_w
Sets the value of the ATDATAM[31] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
3 "0"
atdatam23_w
Sets the value of the ATDATAM[23] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
2 "0"
atdatam15_w
Sets the value of the ATDATAM[15] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
1 "0"
atdatam7_w
Sets the value of the ATDATAM[7] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
0 "0"
atdatam0_w
Sets the value of the ATDATAM[0] output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.


stm_apb_stmitatbctr2
Integration Mode ATB Control 2 register
R
Address : 0x10170ef0
Bits Name Description
31 - 2 -
 reserved
1 afvalidm_r
Reads the value of the AFVALIDM input signal:
0b1    The signal is at logic 0b1.
0b0    The signal is at logic 0b0.
0 atreadym_r
Reads the value of the ATREADYM input signal:
0b1    The signal is at logic 0b1.
0b0    The signal is at logic 0b0.


stm_apb_stmitatbid
Integration Mode ATB Identification register
W
0x00000000
Address : 0x10170ef4
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 - 0 "0000000"
atidm_w
Sets the value of the ATIDM output signal.


stm_apb_stmitatbctr0
Integration Mode ATB Control 0 register
W
0x00000000
Address : 0x10170ef8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 8 "000"
atbytesm_w
Sets the value of the ATBYTESM output signal:
0b111    Drive logic 0b111.
0b110    Drive logic 0b110.
0b101    Drive logic 0b101.
0b100    Drive logic 0b100.
0b011    Drive logic 0b011.
0b010    Drive logic 0b010.
0b001    Drive logic 0b001.
0b000    Drive logic 0b000.
7 - 2 0
-
 reserved
1 "0"
afreadym_w
Sets the value of the AFREADYM output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.
0 "0"
atvalidm_w
Sets the value of the ATVALIDM output signal:
0b1    Drive logic 0b1.
0b0    Drive logic 0b0.


stm_apb_stmitctrl
Integration Mode Control register
R/W
0x00000000
Address : 0x10170f00
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ime
Enables the component to switch between functional and integration mode.
0b1    Enable integration mode.
0b0    Disable integration mode.


stm_apb_stmclaimset
Claim Tag Set Register
R/W
0x00000000
Address : 0x10170fa0
Bits Reset value Name Description
31 - 0 0x0
claimset
On reads, each bit reads as b1 if the claim tag bit is implemented.
For example if four claim tag bits are implemented, this register reads as 0xF.
On writes, a b1 in a bit position causes the corresponding claim tag bit to be set.


stm_apb_stmclaimclr
Claim Tag Clear Register
R/W
0x00000000
Address : 0x10170fa4
Bits Reset value Name Description
31 - 0 0x0
claimclr
On reads, each bit reads as one if the claim tag bit is set.
On writes, a b1 in a bit position causes the corresponding claim tag bit to be cleared.
On a reset the claim tags are reset to b0.


stm_apb_stmlar
Lock Access Register
W
0x00000000
Address : 0x10170fb0
Bits Reset value Name Description
31 - 0 0x0
key
Ignores writes when the PADDRDBG31 signal is HIGH.
When the PADDRDBG31 signal is LOW, a write of 0xC5ACCE55 unlocks the lock control mechanism, enabling writes with the PADDRDBG31 signal LOW.
Other values lock the lock control mechanism, preventing any more writes with the PADDRDBG31 signal LOW, except to the STMLAR.


stm_apb_stmlsr
Lock Status Register
R
Address : 0x10170fb4
Bits Name Description
31 - 3 -
 reserved
2 type
RAZ. Indicates that the STMLAR is 32 bits.
1 locked
Indicates whether the STM configuration registers are locked:
b0 = Writes to the configuration registers are permitted.
b1 = STM is locked. Writes to the configuration registers are ignored.
If this register is accesses from an interface where the lock mechanism is ignored, for
example, an external debugger, this field reads as b0 regardless of whether the STM is locked.
The reset value of this bit is b1 for accesses from interfaces where the lock mechanism is required.
0 present
Indicates whether the lock mechanism is implemented for this interface:
b0 = This access is from an interface that ignores the lock mechanism. The Locked bit reads as b0 and writes to the STMLAR are ignored.
b1 = This access is from an interface that requires the STM to be unlocked.


stm_apb_stmauthstatus
Authentication Status register
R
Address : 0x10170fb8
Bits Name Description
31 - 8 -
 reserved
7 - 6 snid
Indicates the security level for Secure non-invasive debug:
0b10    Disabled.
0b11    Enabled.
5 - 4 sid
Indicates the security level for Secure invasive debug:
0b10    Disabled.
0b11    Enabled.
3 - 2 nsnid
Indicates the security level for Non-secure non-invasive debug:
0b10    Disabled.
0b11    Enabled.
1 - 0 nsid
Indicates the security level for Non-secure invasive debug:
0b10    Disabled.
0b11    Enabled.


stm_apb_stmdevarch
Device Architecture register
R
Address : 0x10170fbc
Bits Name Description
31 - 21 architect
Defines the architect of the component:
Bits[31:28] Indicates the JEP106 continuation code.
Bits[27:21] Indicates the JEP106 identification code.
See the Standard Manufacturer?s Identification Code for information about JEP106.
For the STM-500, ARM is the architect, and this 11-bit field returns 0x23B.
20 present
Indicates the presence of the STMDEVARCH register:
0b1    The STMDEVARCH register is present.
19 - 16 revision
Architecture revision. Returns the revision of the architecture that the ARCHID field specifies.
For the STM, this value is 0x1, indicating the STMv1.1 architecture.
15 - 0 archid
Architecture ID. Returns a value that identifies the architecture of the component.
For the STM, this value is 0x0A63, indicating the STMv1.1 architecture.


stm_apb_stmdevid
Device Configuration register
R
Address : 0x10170fc8
Bits Name Description
31 - 17 -
 reserved
16 - 0 numsp
Indicates the number of stimulus ports implemented.
For example:
0x00020 = 32 stimulus ports implemented
0x10000 = 65536 stimulus ports implemented.


stm_apb_stmdevtype
Device Type Identifier register
R
Address : 0x10170fcc
Bits Name Description
31 - 8 -
 reserved
7 - 4 sub
Sub-classification within the major category:
0b0110    The component generates trace based on software and hardware stimulus.
3 - 0 major
Major classification grouping for the debug or trace component:
0b0011    The component is a trace source.


stm_apb_stmpidr4
Peripheral ID4 Register
R
Address : 0x10170fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. 0x0: The device only occupies 4KB of memory.
3 - 0 des_2
JEP Continuation


stm_apb_stmpidr0
Peripheral ID0 Register
R
Address : 0x10170fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


stm_apb_stmpidr1
Peripheral ID1 Register
R
Address : 0x10170fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


stm_apb_stmpidr2
Peripheral ID2 Register
R
Address : 0x10170fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


stm_apb_stmpidr3
Peripheral ID3 Register
R
Address : 0x10170fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


stm_apb_stmcidr0
Component ID0 Register
R
Address : 0x10170ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


stm_apb_stmcidr1
Component ID1 Register
R
Address : 0x10170ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


stm_apb_stmcidr2
Component ID2 Register
R
Address : 0x10170ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


stm_apb_stmcidr3
Component ID3 Register
R
Address : 0x10170ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: system_id

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R system_id_bsys_cfg0
1 4 R system_id_bsys_cfg1
2 8 R system_id_bsys_cfg2
3 c R system_id_bsys_cfg3
4-f 10-3c -  reserved
10 40 R system_id_soc_id
11-3f1 44-fc4 -  reserved
3f2 fc8 R system_id_iidr
3f3 fcc -  reserved
3f4 fd0 R system_id_pid4
3f5 fd4 R system_id_pid5
3f6 fd8 R system_id_pid6
3f7 fdc R system_id_pid7
3f8 fe0 R system_id_pid0
3f9 fe4 R system_id_pid1
3fa fe8 R system_id_pid2
3fb fec R system_id_pid3
3fc ff0 R system_id_cid0
3fd ff4 R system_id_cid1
3fe ff8 R system_id_cid2
3ff ffc R system_id_cid3

system_id_bsys_cfg0
Base System Configuration 0
R
Address : 0x1a000000
Bits Name Description
31 - 4 -
 reserved
3 - 0 num_host_cpu
Number of Host processor cores used


system_id_bsys_cfg1
Base System Configuration 1
R
Address : 0x1a000004
Bits Name Description
31 - 16 -
 reserved
15 - 12 ext_sys3
External System 3 Configuration, For SSE-710 this field always reads as 0x0 (not implemented).
11 - 8 ext_sys2
External System 2 Configuration, For SSE-710 this field always reads as 0x0 (not implemented).
7 - 4 ext_sys1
External System 1 Configuration, For SSE-710 this field always reads as 0x3 (ARM TrustZone).
3 - 0 ext_sys0
External System 0 Configuration, For SSE-710 this field always reads as 0x3 (ARM TrustZone).


system_id_bsys_cfg2
Base System Configuration 2
R
Address : 0x1a000008
Bits Name Description
31 - 25 -
 reserved
24 ocvm_en
Indicates if the OCVM interface is supported
23 - 20 num_exp_mst
Number of Expansion Master interfaces, For SSE-710 this field always reads as 0x2.
19 - 16 num_exp_slv
Number of Expansion Slave interfaces, For SSE-710 this field always reads as 0x2.
15 - 0 -
 reserved


system_id_bsys_cfg3
Base System Configuration 3
R
Address : 0x1a00000c
Bits Name Description
31 - 0 system_id_bsys_cfg3


system_id_soc_id
SoC Identification
R
Address : 0x1a000040
Bits Name Description
31 - 20 product_id
User defined value identifying the SoC.
19 - 16 variant
User defined value variant or major revision of the SoC.
15 - 12 revision
Use defined value used to distinguish minor revisions of the SoC.
11 - 0 implementer
Contains the JEP106 code of the company that used the SoC.


system_id_iidr
Implementer Identification Register
R
Address : 0x1a000fc8
Bits Name Description
31 - 20 product_id
Product ID of SSE-710, For SSE-710 this field always reads as 0x762.
19 - 16 variant
Variant or major revision of SSE-710
15 - 12 revision
Minor revisions of SSE-710
11 - 0 implementer
Contains the JEP106 code of the company that implemented SSE-710, For SSE-710 this field always reads as 0x43b.


system_id_pid4
Peripheral ID Register 4
R
Address : 0x1a000fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


system_id_pid5
Peripheral ID Register 5
R
Address : 0x1a000fd4
Bits Name Description
31 - 0 system_id_pid5


system_id_pid6
Peripheral ID Register 6
R
Address : 0x1a000fd8
Bits Name Description
31 - 0 system_id_pid6


system_id_pid7
Peripheral ID Register 7
R
Address : 0x1a000fdc
Bits Name Description
31 - 0 system_id_pid7


system_id_pid0
Peripheral ID Register 0
R
Address : 0x1a000fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


system_id_pid1
Peripheral ID Register 1
R
Address : 0x1a000fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


system_id_pid2
Peripheral ID Register 2
R
Address : 0x1a000fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


system_id_pid3
Peripheral ID Register 3
R
Address : 0x1a000fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


system_id_cid0
Component ID Register 0
R
Address : 0x1a000ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


system_id_cid1
Component ID Register 1
R
Address : 0x1a000ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


system_id_cid2
Component ID Register 2
R
Address : 0x1a000ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


system_id_cid3
Component ID Register 3
R
Address : 0x1a000ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: host_base_sys_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W host_base_sys_ctrl_cluster_config
1-3 4-c -  reserved
4 10 R/W host_base_sys_ctrl_pe0_config
5 14 R/W host_base_sys_ctrl_pe0_rvbaraddr_lw
6 18 R host_base_sys_ctrl_pe0_rvbaraddr_up
7 1c -  reserved
8 20 R/W host_base_sys_ctrl_pe1_config
9 24 R/W host_base_sys_ctrl_pe1_rvbaraddr_lw
a 28 R host_base_sys_ctrl_pe1_rvbaraddr_up
b 2c -  reserved
c 30 R/W host_base_sys_ctrl_pe2_config
d 34 R/W host_base_sys_ctrl_pe2_rvbaraddr_lw
e 38 R host_base_sys_ctrl_pe2_rvbaraddr_up
f 3c -  reserved
10 40 R/W host_base_sys_ctrl_pe3_config
11 44 R/W host_base_sys_ctrl_pe3_rvbaraddr_lw
12 48 R host_base_sys_ctrl_pe3_rvbaraddr_up
13-7f 4c-1fc -  reserved
80 200 R host_base_sys_ctrl_host_rst_syn
81-bf 204-2fc -  reserved
c0 300 R/W host_base_sys_ctrl_host_cpu_boot_msk
c1 304 R/W host_base_sys_ctrl_host_cpu_clus_pwr_req
c2 308 R/W host_base_sys_ctrl_host_cpu_wakeup
c3 30c -  reserved
c4 310 R/W host_base_sys_ctrl_ext_sys0_rst_ctrl
c5 314 R host_base_sys_ctrl_ext_sys0_rst_st
c6 318 R/W host_base_sys_ctrl_ext_sys1_rst_ctrl
c7 31c R host_base_sys_ctrl_ext_sys1_rst_st
c8 320 R/W host_base_sys_ctrl_ext_sys2_rst_ctrl
c9 324 R host_base_sys_ctrl_ext_sys2_rst_st
ca 328 R/W host_base_sys_ctrl_ext_sys3_rst_ctrl
cb 32c R host_base_sys_ctrl_ext_sys3_rst_st
cc-ff 330-3fc -  reserved
100 400 R/W host_base_sys_ctrl_bsys_pwr_req
101 404 R host_base_sys_ctrl_bsys_pwr_st
102-13f 408-4fc -  reserved
140 500 R host_base_sys_ctrl_host_sys_lctrl_st
141 504 W host_base_sys_ctrl_host_sys_lctrl_set
142 508 W host_base_sys_ctrl_host_sys_lctrl_clr
143-1ff 50c-7fc -  reserved
200 800 R/W host_base_sys_ctrl_hostcpuclk_ctrl
201 804 R/W host_base_sys_ctrl_hostcpuclk_div0
202 808 R/W host_base_sys_ctrl_hostcpuclk_div1
203 80c -  reserved
204 810 R/W host_base_sys_ctrl_gicclk_ctrl
205 814 R/W host_base_sys_ctrl_gicclk_div0
206-207 818-81c -  reserved
208 820 R/W host_base_sys_ctrl_aclk_ctrl
209 824 R/W host_base_sys_ctrl_aclk_div0
20a-20b 828-82c -  reserved
20c 830 R/W host_base_sys_ctrl_ctrlclk_ctrl
20d 834 R/W host_base_sys_ctrl_ctrlclk_div0
20e-20f 838-83c -  reserved
210 840 R/W host_base_sys_ctrl_dbgclk_ctrl
211 844 R/W host_base_sys_ctrl_dbgclk_div0
212-213 848-84c -  reserved
214 850 R/W host_base_sys_ctrl_hostuartclk_ctrl
215 854 R/W host_base_sys_ctrl_hostuartclk_div0
216-217 858-85c -  reserved
218 860 R/W host_base_sys_ctrl_refclk_ctrl
219-27f 864-9fc -  reserved
280 a00 R host_base_sys_ctrl_clkforce_st
281 a04 W host_base_sys_ctrl_clkforce_set
282 a08 W host_base_sys_ctrl_clkforce_clr
283 a0c -  reserved
284 a10 R host_base_sys_ctrl_pll_st
285-2bf a14-afc -  reserved
2c0 b00 R host_base_sys_ctrl_host_ppu_int_st
2c1-3f3 b04-fcc -  reserved
3f4 fd0 R host_base_sys_ctrl_pid4
3f5 fd4 R host_base_sys_ctrl_pid5
3f6 fd8 R host_base_sys_ctrl_pid6
3f7 fdc R host_base_sys_ctrl_pid7
3f8 fe0 R host_base_sys_ctrl_pid0
3f9 fe4 R host_base_sys_ctrl_pid1
3fa fe8 R host_base_sys_ctrl_pid2
3fb fec R host_base_sys_ctrl_pid3
3fc ff0 R host_base_sys_ctrl_cid0
3fd ff4 R host_base_sys_ctrl_cid1
3fe ff8 R host_base_sys_ctrl_cid2
3ff ffc R host_base_sys_ctrl_cid3

host_base_sys_ctrl_cluster_config
Cluster static config register
R/W
0x00000000
Address : 0x1a010000
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
cryptodisable
Disable the cryptographic extensions of the Host CPU Cores.


host_base_sys_ctrl_pe0_config
Processing element static config register
R/W
0x00000000
Address : 0x1a010010
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
aa64naa32
Select initial register width state.
This field is only implemented if the HOST_CPU_TYPE is 2 or 3, otherwise it is Reserved and treated as RAZ/WI.
Possible field values are: 0 AArch32, 1 AArch64.
Changes in this field only take effect at a power on reset of the core.
2 "0"
vinithi
Locations of the exception vectors at reset.
Sets the initial value of SCTLR.V.
Possible field values are:
0: Exception vector start at 0x0000_00000.
1: Exception vector start at 0xFFFF_00000.
Changes in this field only take effect at a reset of the core.
1 "0"
cfgte
Enabling T32 exceptions. Sets the initial value of the SCTLR.TE.
Possible field values are:
0: Exceptions taken in Arm(v7) or AArch32(v8) state.
1: Exceptions taken in Thumb32 state.
Changes in this field only take effect at a reset of the core.
0 "0"
cfgend
Endianness configuration at reset. Sets the initial value of the SCTLR_EL3.EE and SCTR_S.EE bits.
Possible field values are:
0: Little Endian.
1: Big Endian.
Changes in this field only take effect at a reset of the core.


host_base_sys_ctrl_pe0_rvbaraddr_lw
R/W
0x00000000
Address : 0x1a010014
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_pe0_rvbaraddr_lw


host_base_sys_ctrl_pe0_rvbaraddr_up
R
Address : 0x1a010018
Bits Name Description
31 - 0 host_base_sys_ctrl_pe0_rvbaraddr_up


host_base_sys_ctrl_pe1_config
Processing element static config register
R/W
0x00000000
Address : 0x1a010020
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
aa64naa32
Select initial register width state.
This field is only implemented if the HOST_CPU_TYPE is 2 or 3, otherwise it is Reserved and treated as RAZ/WI.
Possible field values are: 0 AArch32, 1 AArch64.
Changes in this field only take effect at a power on reset of the core.
2 "0"
vinithi
Locations of the exception vectors at reset.
Sets the initial value of SCTLR.V.
Possible field values are:
0: Exception vector start at 0x0000_00000.
1: Exception vector start at 0xFFFF_00000.
Changes in this field only take effect at a reset of the core.
1 "0"
cfgte
Enabling T32 exceptions. Sets the initial value of the SCTLR.TE.
Possible field values are:
0: Exceptions taken in Arm(v7) or AArch32(v8) state.
1: Exceptions taken in Thumb32 state.
Changes in this field only take effect at a reset of the core.
0 "0"
cfgend
Endianness configuration at reset. Sets the initial value of the SCTLR_EL3.EE and SCTR_S.EE bits.
Possible field values are:
0: Little Endian.
1: Big Endian.
Changes in this field only take effect at a reset of the core.


host_base_sys_ctrl_pe1_rvbaraddr_lw
R/W
0x00000000
Address : 0x1a010024
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_pe1_rvbaraddr_lw


host_base_sys_ctrl_pe1_rvbaraddr_up
R
Address : 0x1a010028
Bits Name Description
31 - 0 host_base_sys_ctrl_pe1_rvbaraddr_up


host_base_sys_ctrl_pe2_config
Processing element static config register
R/W
0x00000000
Address : 0x1a010030
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
aa64naa32
Select initial register width state.
This field is only implemented if the HOST_CPU_TYPE is 2 or 3, otherwise it is Reserved and treated as RAZ/WI.
Possible field values are: 0 AArch32, 1 AArch64.
Changes in this field only take effect at a power on reset of the core.
2 "0"
vinithi
Locations of the exception vectors at reset.
Sets the initial value of SCTLR.V.
Possible field values are:
0: Exception vector start at 0x0000_00000.
1: Exception vector start at 0xFFFF_00000.
Changes in this field only take effect at a reset of the core.
1 "0"
cfgte
Enabling T32 exceptions. Sets the initial value of the SCTLR.TE.
Possible field values are:
0: Exceptions taken in Arm(v7) or AArch32(v8) state.
1: Exceptions taken in Thumb32 state.
Changes in this field only take effect at a reset of the core.
0 "0"
cfgend
Endianness configuration at reset. Sets the initial value of the SCTLR_EL3.EE and SCTR_S.EE bits.
Possible field values are:
0: Little Endian.
1: Big Endian.
Changes in this field only take effect at a reset of the core.


host_base_sys_ctrl_pe2_rvbaraddr_lw
R/W
0x00000000
Address : 0x1a010034
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_pe2_rvbaraddr_lw


host_base_sys_ctrl_pe2_rvbaraddr_up
R
Address : 0x1a010038
Bits Name Description
31 - 0 host_base_sys_ctrl_pe2_rvbaraddr_up


host_base_sys_ctrl_pe3_config
Processing element static config register
R/W
0x00000000
Address : 0x1a010040
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
aa64naa32
Select initial register width state.
This field is only implemented if the HOST_CPU_TYPE is 2 or 3, otherwise it is Reserved and treated as RAZ/WI.
Possible field values are: 0 AArch32, 1 AArch64.
Changes in this field only take effect at a power on reset of the core.
2 "0"
vinithi
Locations of the exception vectors at reset.
Sets the initial value of SCTLR.V.
Possible field values are:
0: Exception vector start at 0x0000_00000.
1: Exception vector start at 0xFFFF_00000.
Changes in this field only take effect at a reset of the core.
1 "0"
cfgte
Enabling T32 exceptions. Sets the initial value of the SCTLR.TE.
Possible field values are:
0: Exceptions taken in Arm(v7) or AArch32(v8) state.
1: Exceptions taken in Thumb32 state.
Changes in this field only take effect at a reset of the core.
0 "0"
cfgend
Endianness configuration at reset. Sets the initial value of the SCTLR_EL3.EE and SCTR_S.EE bits.
Possible field values are:
0: Little Endian.
1: Big Endian.
Changes in this field only take effect at a reset of the core.


host_base_sys_ctrl_pe3_rvbaraddr_lw
R/W
0x00000000
Address : 0x1a010044
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_pe3_rvbaraddr_lw


host_base_sys_ctrl_pe3_rvbaraddr_up
R
Address : 0x1a010048
Bits Name Description
31 - 0 host_base_sys_ctrl_pe3_rvbaraddr_up


host_base_sys_ctrl_host_rst_syn
R
Address : 0x1a010200
Bits Name Description
31 - 0 host_base_sys_ctrl_host_rst_syn


host_base_sys_ctrl_host_cpu_boot_msk
Host CPU boot mask register
R/W
0x00000001
Address : 0x1a010300
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0001"
boot_msk
Configures which Host CPU Cores automatically boot when the CLUSTOP domain exits OFF or MEM_RET.
Each bit in this field corresponds to a Host CPU Core, with bit 0 corresponding to Host CPU Core 0 and bit 1 corresponding to Host CPU Core 1.
Bit values:
0: Host CPU Core x does not automatically boot on CLUSTOP domain exit from OFF or MEM_RET.
1: Host CPU Core x does automatically boot on CLUSTOP domain exit from OFF or MEM_RET.
Changes in this field only take effect at the next CLUSTOP transitions from OFF or MEM_RET.


host_base_sys_ctrl_host_cpu_clus_pwr_req
R/W
0x00000000
Address : 0x1a010304
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
mem_ret_req
Possible field values are:
0: When entering a low power mode, the last level cache of the Host CPU is not required to be retained.
1: When entering a low power mode, the last level cache of the Host CPU is required to be retained.
0 "0"
pwr_req
Possible field values are:
0: CLUSTOP can enter a low power mode, when all CORE{0-3} domains are OFF and the GIC is idle.
1: CLUSTOP is required to be in a power mode greater than or equal to FUNC_RET even when all CORE{0-3} domains are OFF.


host_base_sys_ctrl_host_cpu_wakeup
Host CPU wakeup register
R/W
0x00000000
Address : 0x1a010308
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0000"
core_wakeup
Host CPU core wakeup
Each bit in this field corresponds to a Host CPU Core, with bit 0 corresponding to Host CPU Core 0 and bit 1 corresponding to Host CPU Core 1.


host_base_sys_ctrl_ext_sys0_rst_ctrl
External system reset control register
R/W
0x00000000
Address : 0x1a010310
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for External System.
0 "0"
cpuwait
CPU Wait control.
Possible field values are:
0: CPUWAIT signal of the External System is de-asserted.
1: CPUWAIT signal of the External System is asserted.
Once CPUWAIT becomes 0b0 any attempt to revert 0b1 is ignored.
This field only returns to 0b1 when any of the following occur:
- External Power-on reset.
- Internal Power-on reset.
- Debug reset.
- Host System reset.
- Reset of the associated External System.
This field becomes RO when associated EXT_SYS{0-3}_CPUWAIT_WEN is 0b0.
Any attempt to set this field to 0b0 by software is ignored.


host_base_sys_ctrl_ext_sys0_rst_st
External system reset status register
R
Address : 0x1a010314
Bits Name Description
31 - 3 -
 reserved
2 - 1 rst_ack
Status of reset request
Possible field values are:
00: No reset requested.
01: Reset request unable to complete.
10: Reset request complete.
11: Reserved.
0 -
 reserved


host_base_sys_ctrl_ext_sys1_rst_ctrl
External system reset control register
R/W
0x00000000
Address : 0x1a010318
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for External System.
0 "0"
cpuwait
CPU Wait control.
Possible field values are:
0: CPUWAIT signal of the External System is de-asserted.
1: CPUWAIT signal of the External System is asserted.
Once CPUWAIT becomes 0b0 any attempt to revert 0b1 is ignored.
This field only returns to 0b1 when any of the following occur:
- External Power-on reset.
- Internal Power-on reset.
- Debug reset.
- Host System reset.
- Reset of the associated External System.
This field becomes RO when associated EXT_SYS{0-3}_CPUWAIT_WEN is 0b0.
Any attempt to set this field to 0b0 by software is ignored.


host_base_sys_ctrl_ext_sys1_rst_st
External system reset status register
R
Address : 0x1a01031c
Bits Name Description
31 - 3 -
 reserved
2 - 1 rst_ack
Status of reset request
Possible field values are:
00: No reset requested.
01: Reset request unable to complete.
10: Reset request complete.
11: Reserved.
0 -
 reserved


host_base_sys_ctrl_ext_sys2_rst_ctrl
External system reset control register
R/W
0x00000000
Address : 0x1a010320
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for External System.
0 "0"
cpuwait
CPU Wait control.
Possible field values are:
0: CPUWAIT signal of the External System is de-asserted.
1: CPUWAIT signal of the External System is asserted.
Once CPUWAIT becomes 0b0 any attempt to revert 0b1 is ignored.
This field only returns to 0b1 when any of the following occur:
- External Power-on reset.
- Internal Power-on reset.
- Debug reset.
- Host System reset.
- Reset of the associated External System.
This field becomes RO when associated EXT_SYS{0-3}_CPUWAIT_WEN is 0b0.
Any attempt to set this field to 0b0 by software is ignored.


host_base_sys_ctrl_ext_sys2_rst_st
External system reset status register
R
Address : 0x1a010324
Bits Name Description
31 - 3 -
 reserved
2 - 1 rst_ack
Status of reset request
Possible field values are:
00: No reset requested.
01: Reset request unable to complete.
10: Reset request complete.
11: Reserved.
0 -
 reserved


host_base_sys_ctrl_ext_sys3_rst_ctrl
External system reset control register
R/W
0x00000000
Address : 0x1a010328
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for External System.
0 "0"
cpuwait
CPU Wait control.
Possible field values are:
0: CPUWAIT signal of the External System is de-asserted.
1: CPUWAIT signal of the External System is asserted.
Once CPUWAIT becomes 0b0 any attempt to revert 0b1 is ignored.
This field only returns to 0b1 when any of the following occur:
- External Power-on reset.
- Internal Power-on reset.
- Debug reset.
- Host System reset.
- Reset of the associated External System.
This field becomes RO when associated EXT_SYS{0-3}_CPUWAIT_WEN is 0b0.
Any attempt to set this field to 0b0 by software is ignored.


host_base_sys_ctrl_ext_sys3_rst_st
External system reset status register
R
Address : 0x1a01032c
Bits Name Description
31 - 3 -
 reserved
2 - 1 rst_ack
Status of reset request
Possible field values are:
00: No reset requested.
01: Reset request unable to complete.
10: Reset request complete.
11: Reserved.
0 -
 reserved


host_base_sys_ctrl_bsys_pwr_req
Base system power request register
R/W
0x00000000
Address : 0x1a010400
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 3 "000"
systop_pwr_req
Selects SYSTOP power domain behavior when no activity in the domain.
Possible field values are:
000: No request for logic or volatile memory to be powered.
001: No request for logic to be powered, but volatile memory must be retained.
01x: Request for logic to be powered, but volatile memory can be either powered or retained.
1xx: Request for logic and volatile memory to be powered.
2 "0"
dbgtop_pwr_req
Selects DBGTOP power domain behavior when no activity in the domain.
Possible field values are:
0: No request for DBGTOP to be powered.
1: Request for DBGTOP to be powered.
1 "0"
refclk_req
Request REFCLK.
Possible field values are:
0: No request for REFCLK to be supplied.
1: Request for REFCLK to be supplied.
0 "0"
wakeup_en
Host System wakeup enable.
Possible field values are:
0: Wakeup for Host System is disabled
1: Wakeup for Host System is enabled.


host_base_sys_ctrl_bsys_pwr_st
Base system power status register
R
Address : 0x1a010404
Bits Name Description
31 - 6 -
 reserved
5 - 3 systop_pwr_st
SYSTOP power domain status.
Possible field values are:
000: SYSTOP is in the OFF or WARM_RST power mode.
001: SYSTOP is in the MEM_RET power mode.
010: SYSTOP is in the FUNC_RET powet mode.
100: SYSTOP is in the ON power mode.
2 dbgtop_pwr_st
DBGTOP power domain status.
Possible field values are:
0: DBGTOP is in the OFF or WARM_RST power mode.
1: DBGTOP is in the ON power mode.
1 - 0 -
 reserved


host_base_sys_ctrl_host_sys_lctrl_st
R
Address : 0x1a010500
Bits Name Description
31 - 0 host_base_sys_ctrl_host_sys_lctrl_st


host_base_sys_ctrl_host_sys_lctrl_set
W
0x00000000
Address : 0x1a010504
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_host_sys_lctrl_set


host_base_sys_ctrl_host_sys_lctrl_clr
W
0x00000000
Address : 0x1a010508
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_host_sys_lctrl_clr


host_base_sys_ctrl_hostcpuclk_ctrl
Hpst CPU clock control register
R/W
0x00000001
Address : 0x1a010800
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for HOSTCPUCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for HOSTCPUCLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
0x04: CPUPLL.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_hostcpuclk_div0
Host CPU clock divider 0 register
R/W
0x00000000
Address : 0x1a010804
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 8 0
-
 reserved
7 - 0 "00000000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_hostcpuclk_div1
Host CPU clock divider 1 register
R/W
0x00000000
Address : 0x1a010808
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to CPUPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to CPUPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_gicclk_ctrl
GIC clock control register
R/W
0x00000001
Address : 0x1a010810
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated.
This field is Reserved and treated as RAZ/WI when GIC_TYPE is 0 or 1.
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for GICCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for GICCLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_gicclk_div0
GIC clock divider 0 register
R/W
0x00000000
Address : 0x1a010814
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_aclk_ctrl
AXI clock control register
R/W
0x00000001
Address : 0x1a010820
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated.
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for ACLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for ACLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_aclk_div0
AXI clock divider 0 register
R/W
0x00000000
Address : 0x1a010824
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_ctrlclk_ctrl
Control clock control register
R/W
0x00000001
Address : 0x1a010830
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated.
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for CTRLCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for CTRLCLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_ctrlclk_div0
Control clock divider 0 register
R/W
0x00000000
Address : 0x1a010834
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_dbgclk_ctrl
Debug clock control register
R/W
0x00000001
Address : 0x1a010840
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated.
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for DBGCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for DBGCLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_dbgclk_div0
Debug clock divider 0 register
R/W
0x00000000
Address : 0x1a010844
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_hostuartclk_ctrl
Host UART clock control register
R/W
0x00000001
Address : 0x1a010850
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for HOSTUARTCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for HOSTUARTCLK.
Possible field values are:
0x00: Clock gate.
0x01: REFCLK.
0x02: SYSPLL.
0x03: S32KCLK.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_hostuartclk_div0
Host UART clock divider 0 register
R/W
0x00000000
Address : 0x1a010854
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SYSPLL.
For possible field values see 'clkdiv' bit field.
15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv
Select the value of the integer divider applied to SYSPLL.
Possible field values are:
0x00: Divide by 1.
0x01: Divide by 2.
...
0x1f: Divide by 32.


host_base_sys_ctrl_refclk_ctrl
REFCLK clock control register
R/W
0x00000001
Address : 0x1a010860
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated.
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for REFCLK.
For possible field values see 'clkselect' bit field.
7 - 0 "00000001"
clkselect
Select the clock source for REFCLK.
Possible field values are:
0x01: REFCLK.
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


host_base_sys_ctrl_clkforce_st
R
Address : 0x1a010a00
Bits Name Description
31 - 0 host_base_sys_ctrl_clkforce_st


host_base_sys_ctrl_clkforce_set
W
0x00000000
Address : 0x1a010a04
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_clkforce_set


host_base_sys_ctrl_clkforce_clr
W
0x00000000
Address : 0x1a010a08
Bits Reset value Name Description
31 - 0 0
host_base_sys_ctrl_clkforce_clr


host_base_sys_ctrl_pll_st
PLL status register
R
Address : 0x1a010a10
Bits Name Description
31 - 2 -
 reserved
1 cpuplllock_st
 Status of the CPUPLLLOCK input.
0 sysplllock_st
 Status of the SYSPLLLOCK input.


host_base_sys_ctrl_host_ppu_int_st
R
Address : 0x1a010b00
Bits Name Description
31 - 0 host_base_sys_ctrl_host_ppu_int_st


host_base_sys_ctrl_pid4
Peripheral ID Register 4
R
Address : 0x1a010fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


host_base_sys_ctrl_pid5
Peripheral ID Register 5
R
Address : 0x1a010fd4
Bits Name Description
31 - 0 host_base_sys_ctrl_pid5


host_base_sys_ctrl_pid6
Peripheral ID Register 6
R
Address : 0x1a010fd8
Bits Name Description
31 - 0 host_base_sys_ctrl_pid6


host_base_sys_ctrl_pid7
Peripheral ID Register 7
R
Address : 0x1a010fdc
Bits Name Description
31 - 0 host_base_sys_ctrl_pid7


host_base_sys_ctrl_pid0
Peripheral ID Register 0
R
Address : 0x1a010fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


host_base_sys_ctrl_pid1
Peripheral ID Register 1
R
Address : 0x1a010fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


host_base_sys_ctrl_pid2
Peripheral ID Register 2
R
Address : 0x1a010fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


host_base_sys_ctrl_pid3
Peripheral ID Register 3
R
Address : 0x1a010fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


host_base_sys_ctrl_cid0
Component ID Register 0
R
Address : 0x1a010ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


host_base_sys_ctrl_cid1
Component ID Register 1
R
Address : 0x1a010ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


host_base_sys_ctrl_cid2
Component ID Register 2
R
Address : 0x1a010ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


host_base_sys_ctrl_cid3
Component ID Register 3
R
Address : 0x1a010ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: app_firewall_ppu, app_systop_ppu, app_dbgtop_ppu, app_clustop_ppu, app_core_ppu0, secenc_secenctop_ppu

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ppu_pwpr
1 4 R/W ppu_pmer
2 8 R ppu_pwsr
3 c -  reserved
4 10 R ppu_disr
5 14 R ppu_misr
6 18 R ppu_stsr
7 1c R/W ppu_unlk
8 20 R/W ppu_pwcr
9 24 R/W ppu_ptcr
a-b 28-2c -  reserved
c 30 R/W ppu_imr
d 34 R/W ppu_aimr
e 38 R/W ppu_isr
f 3c R/W ppu_aisr
10 40 R/W ppu_iesr
11 44 R/W ppu_opsr
12-13 48-4c -  reserved
14 50 R/W ppu_funrr
15 54 R/W ppu_fulrr
16 58 R/W ppu_memrr
17-57 5c-15c -  reserved
58 160 R/W ppu_edtr0
59 164 R/W ppu_edtr1
5a-5b 168-16c -  reserved
5c 170 R/W ppu_dcdr0
5d 174 R/W ppu_dcdr1
5e-3eb 178-fac -  reserved
3ec fb0 R ppu_idr0
3ed fb4 R ppu_idr1
3ee-3f1 fb8-fc4 -  reserved
3f2 fc8 R ppu_iidr
3f3 fcc R ppu_aidr
3f4 fd0 R ppu_pid4
3f5 fd4 R ppu_pid5
3f6 fd8 R ppu_pid6
3f7 fdc R ppu_pid7
3f8 fe0 R ppu_pid0
3f9 fe4 R ppu_pid1
3fa fe8 R ppu_pid2
3fb fec R ppu_pid3
3fc ff0 R ppu_cid0
3fd ff4 R ppu_cid1
3fe ff8 R ppu_cid2
3ff ffc R ppu_cid3

ppu_pwpr
Power Policy Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020000
Address@app_systop_ppu : 0x1a030000
Address@app_dbgtop_ppu : 0x1a040000
Address@app_clustop_ppu : 0x1bc00000
Address@app_core_ppu0 : 0x1bc10000
Address@secenc_secenctop_ppu : 0x5008d000
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
op_dyn_en
Operating mode dynamic transition enable. When this bit is set to 0b1 dynamic transitions are enabled for operating modes, allowing transitions to be initiated by changes on operating mode devactive inputs.
23 - 20 0
-
 reserved
19 - 16 "0000"
op_policy
Operating mode policy. When static operating mode transitions are enabled, op_dyn_en is set to 0b0, then this is the target operating mode for the ppu.
When dynamic operating mode transitions are enabled, op_dyn_en is set to 0b1, then this is the minimum operating mode for the ppu.
15 - 13 0
-
 reserved
12 "0"
lock_en
Lock enable bit.
11 - 9 0
-
 reserved
8 "0"
pwr_dyn_en
Power mode dynamic transition enable. When this bit is set to 0b1 dynamic transitions are enabled for power modes, allowing transitions to be initiated by changes on power mode devactive inputs.
7 - 4 0
-
 reserved
3 - 0 "0000"
pwr_policy
Power mode policy. When static power mode transitions are enabled, wr_dyn_en is set to 0b0, this is the target power mode for the ppu.
When dynamic power mode transitions are enabled, pwr_dyn_en is set to 0b1, this is the minimum power mode for the ppu.


ppu_pmer
Power Mode Emulation Enable Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020004
Address@app_systop_ppu : 0x1a030004
Address@app_dbgtop_ppu : 0x1a040004
Address@app_clustop_ppu : 0x1bc00004
Address@app_core_ppu0 : 0x1bc10004
Address@secenc_secenctop_ppu : 0x5008d004
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
emu_en
Power mode emulation enable.
When this bit is set to 0b1 transitions to off and mem_ret instead transition to off_emu and mem_ret_emu.


ppu_pwsr
Power Status Register
R
Address@app_firewall_ppu : 0x1a020008
Address@app_systop_ppu : 0x1a030008
Address@app_dbgtop_ppu : 0x1a040008
Address@app_clustop_ppu : 0x1bc00008
Address@app_core_ppu0 : 0x1bc10008
Address@secenc_secenctop_ppu : 0x5008d008
Bits Name Description
31 - 25 -
 reserved
24 op_dyn_status
Operating mode dynamic transition status.
When set to 0b1 operating mode dynamic transitions are enabled.
23 - 20 -
 reserved
19 - 16 op_status
Operating mode status.
These bits reflect the current operating mode of the ppu.
15 - 13 -
 reserved
12 lock_status
Lock status.
When set to 0b1 the ppu is locked in the current mode.
When set to 0b0 the ppu is not locked in the current mode.
11 - 9 -
 reserved
8 pwr_dyn_status
Power mode dynamic transition status.
When set to 0b1 power mode dynamic transitions are enabled.
7 - 4 -
 reserved
3 - 0 pwr_status
Power mode status.
These bits reflect the current power mode of the ppu.


ppu_disr
Device Interface Input Current Status Register
R
Address@app_firewall_ppu : 0x1a020010
Address@app_systop_ppu : 0x1a030010
Address@app_dbgtop_ppu : 0x1a040010
Address@app_clustop_ppu : 0x1bc00010
Address@app_core_ppu0 : 0x1bc10010
Address@secenc_secenctop_ppu : 0x5008d010
Bits Name Description
31 - 24 op_devactive_status
Status of the operating mode devactive inputs.
23 - 11 -
 reserved
10 - 0 pwr_devactive_status
Status of the power mode devactive inputs.
For q-channel: There is one bit for each device interface q-channel devqactive.
For example, bit 0 is for the q-channel 0 devqactive, and bit 1 for the q-channel 1 devqactive.
For a q-channel ppu bits [10:8] are always reserved as only 8 device interface q-channels are supported.
For p-channel: There is one bit for each bit of the power mode devpactive inputs.
For example, bit 10 is for devpactive[10], and bit 9 is for devpactive[9].
Bit 0 relates to devpactive[0] and is always 0.


ppu_misr
Miscellaneous Input Current Status Register
R
Address@app_firewall_ppu : 0x1a020014
Address@app_systop_ppu : 0x1a030014
Address@app_dbgtop_ppu : 0x1a040014
Address@app_clustop_ppu : 0x1bc00014
Address@app_core_ppu0 : 0x1bc10014
Address@secenc_secenctop_ppu : 0x5008d014
Bits Name Description
31 - 24 -
 reserved
23 - 16 devdeny_status
Status of the device interface devdeny inputs.
For q-channel: There is one bit for each device interface devqdeny.
For example, bit 16 is for q-channel 0 devqdeny, and bit 17 for q-channel 1 devqdeny.
For p-channel: Bit 16 is for the device interface devpdeny. Other bits are reserved.
15 - 8 devaccept_status
Status of the device interface devaccept inputs.
For q-channel: There is one bit for each device interface devqacceptn.
For example, bit 8 is for q-channel 0 devqacceptn and bit 9 for q-channel 1 devqacceptn.
For p-channel: Bit 8 is for the device interface devpaccept. Other bits are reserved.
7 - 1 -
 reserved
0 pcsmpaccept_status
The status of the pcsmpaccept input.


ppu_stsr
Stored Status Register
R
Address@app_firewall_ppu : 0x1a020018
Address@app_systop_ppu : 0x1a030018
Address@app_dbgtop_ppu : 0x1a040018
Address@app_clustop_ppu : 0x1bc00018
Address@app_core_ppu0 : 0x1bc10018
Address@secenc_secenctop_ppu : 0x5008d018
Bits Name Description
31 - 8 -
 reserved
7 - 0 stored_devdeny
Status of the devdeny signals from the last device interface q-channel transition.
For q-channel:
There is one bit for each device interface devqdeny.
For example, bit 0 is for q-channel 0 devqdeny, and bit 1 for q-channel 1 devqdeny.
For a q-channel ppu with a single q-channel this field is reserved.
For p-channel: This field is reserved.


ppu_unlk
Unlock register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a02001c
Address@app_systop_ppu : 0x1a03001c
Address@app_dbgtop_ppu : 0x1a04001c
Address@app_clustop_ppu : 0x1bc0001c
Address@app_core_ppu0 : 0x1bc1001c
Address@secenc_secenctop_ppu : 0x5008d01c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
unlock
When 0b1 is written to this bit the ppu is unlocked from a locked power mode.
A read always returns 0b0.


ppu_pwcr
Power Configuration Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020020
Address@app_systop_ppu : 0x1a030020
Address@app_dbgtop_ppu : 0x1a040020
Address@app_clustop_ppu : 0x1bc00020
Address@app_core_ppu0 : 0x1bc10020
Address@secenc_secenctop_ppu : 0x5008d020
Bits Reset value Name Description
31 - 24 "00000000"
op_devactiveen
These bits enable the operating mode devactive inputs.
When a bit is to 0b1 the related devactive input is enabled, when set to 0b0 it is disabled.
All supported bits are reset to 0b1.
When operating modes are not supported this field is reserved.
23 - 19 0
-
 reserved
18 - 8 0x0
wr_devactiveen
These bits enable the power mode devactive inputs.
When a bit is to 0b1 the related devactive input is enabled, when set to 0b0 it is disabled.
All available bits are reset to 0b1.
For q-channel: There is one bit for each device interface q-channel devqactive.
For example, bit 8 is for the q-channel 0 devqactive, and bit 9 for the q-channel 1 devqactive.
For a q-channel ppu bits [18:16] are always reserved as only 8 device interface q-channels are supported.
For p-channel: There is one bit for each bit of the devpactive input.
For example, bit 18 is for devpactive[10], and bit 17 is for devpactive[9].
Bit 8 relates to devpactive[0] and is always 0b0.
7 - 0 "00000000"
devreqen
When set to 0b1 enables the device interface handshake for transitions.
All available bits are reset to 0b1.
For q-channel: There is one bit for each device interface channel.
For example, bit 0 is for q-channel 0, and bit 1 is for q-channel 1.
For p-channel: Bit 0 is for the single p-channel. Other bits are reserved.


ppu_ptcr
Power Mode Transition Configuration Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020024
Address@app_systop_ppu : 0x1a030024
Address@app_dbgtop_ppu : 0x1a040024
Address@app_clustop_ppu : 0x1bc00024
Address@app_core_ppu0 : 0x1bc10024
Address@secenc_secenctop_ppu : 0x5008d024
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
dbg_recov_porst_en
0b0 ?devporesetn is not asserted when in dbg_recov.
0b1 ?devporesetn is asserted when in dbg_recov.
This bit should not be modified when the ppu is in dbg_recov, or the ppu is in transition, if it is then ppu behavior is unpredictable.
If dbg_recov is not supported this bit is reserved.
0 "0"
warm_rst_devreqen
0b0 - The ppu does not perform a device interface handshake when transitioning between on and warm_rst.
0b1 - The ppu performs a device interface handshake when transitioning between on and warm_rst.
This bit should not be modified when the ppu is in warm_rst, or if the ppu is performing a transition, otherwise ppu behavior is unpredictable.
For a q-channel ppu this setting disables all q-channels for this transition.


ppu_imr
Interrupt Mask Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020030
Address@app_systop_ppu : 0x1a030030
Address@app_dbgtop_ppu : 0x1a040030
Address@app_clustop_ppu : 0x1bc00030
Address@app_core_ppu0 : 0x1bc10030
Address@secenc_secenctop_ppu : 0x5008d030
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
locked_irq_mask
Locked event mask.
If the locked interrupt event is not supported, then this bit is reserved.
4 "0"
emu_deny_irq_mask
Emulation transition denial event mask.
When both off_emu and mem_ret_emu are not supported, or for a q-channel ppu, this bit is reserved.
3 "0"
emu_accept_irq_mask
Emulation transition acceptance event mask.
If both off_emu and mem_ret_emu are not supported this bit is reserved.
2 "0"
sta_deny_irq_mask
Static transition denial event mask.
1 "0"
sta_accept_irq_mask
Static transition acceptance event mask.
0 "0"
sta_policy_trn_irq_mask
Static full policy transition completion event mask.


ppu_aimr
Additional Interrupt Mask Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020034
Address@app_systop_ppu : 0x1a030034
Address@app_dbgtop_ppu : 0x1a040034
Address@app_clustop_ppu : 0x1bc00034
Address@app_core_ppu0 : 0x1bc10034
Address@secenc_secenctop_ppu : 0x5008d034
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
sta_policy_op_irq_mask
Static operating policy transition completion event status.
If the operating policy transition completion event is not supported this bit is reserved.
3 "0"
sta_policy_pwr_irq_mask
Static power policy transition completion event status.
If the power policy transition completion event is not supported this bit is reserved.
2 "0"
dyn_deny_irq_mask
Dynamic transition denial event mask.
When no dynamic transitions are supported this field is reserved.
1 "0"
dyn_accept_irq_mask
Dynamic transition acceptance event mask.
When no dynamic transitions are supported this field is reserved.
0 "0"
unspt_policy_irq_mask
Unsupported Policy event mask.


ppu_isr
Interrupt Status Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020038
Address@app_systop_ppu : 0x1a030038
Address@app_dbgtop_ppu : 0x1a040038
Address@app_clustop_ppu : 0x1bc00038
Address@app_core_ppu0 : 0x1bc10038
Address@secenc_secenctop_ppu : 0x5008d038
Bits Reset value Name Description
31 - 24 "00000000"
op_active_edge_irq
Indicates which operating mode devpactive inputs caused the input edge event.
When operating modes are not supported this field is reserved.
23 - 19 0
-
 reserved
18 - 8 0x0
pwr_active_edge_irq
Indicates which power mode devactive inputs caused the input edge event.
For q-channel: There is one bit for each device q-channel devqactive.
For example, bit 8 is for the q-channel 0 devqactive, and bit 9 for the q-channel 1 devqactive.
For a q-channel ppu bits [18:16] are always reserved as only 8 device interface q-channels are supported.
For p-channel: There is one bit for each bit of the power mode devpactive group.
For example, bit 18 is for devpactive[10], and bit 17 is for devpactive[9].
Bit 8 relates to devpactive[0] and is always 0.
7 "0"
other_irq
Indicates there is an interrupt event pending in the Additional Interrupt Status Register (ppu_aisr).
6 0
-
 reserved
5 "0"
locked_irq
Locked event status.
If the locked event is not supported this bit is reserved.
4 "0"
emu_deny_irq
Emulated transition denial event status.
When both off_emu and mem_ret_emu are not supported, or for a q-channel ppu, this bit is reserved.
3 "0"
emu_accept_irq
Emulated transition acceptance event status.
When both off_emu and mem_ret_emu are not supported this bit is reserved.
2 "0"
sta_deny_irq
Static transition denial event status.
1 "0"
sta_accept_irq
Static transition acceptance event status.
0 "0"
sta_policy_trn_irq
Static full policy transition completion event status.


ppu_aisr
Additional Interrupt Status Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a02003c
Address@app_systop_ppu : 0x1a03003c
Address@app_dbgtop_ppu : 0x1a04003c
Address@app_clustop_ppu : 0x1bc0003c
Address@app_core_ppu0 : 0x1bc1003c
Address@secenc_secenctop_ppu : 0x5008d03c
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
sta_policy_op_irq
Static operating policy transition completion event status.
If the operating policy transition completion event is not supported this bit is reserved.
3 "0"
sta_policy_pwr_irq
Static power policy transition completion event status.
If the power policy transition completion event is not supported this bit is reserved.
2 "0"
dyn_deny_irq
Dynamic transition denial event status.
When no dynamic transitions are supported this field is reserved.
1 "0"
dyn_accept_irq
Dynamic transition acceptance event status.
When no dynamic transitions are supported this field is reserved.
0 "0"
unspt_policy_irq
Unsupported Policy event status.


ppu_iesr
Input Edge Sensitivity Register.
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020040
Address@app_systop_ppu : 0x1a030040
Address@app_dbgtop_ppu : 0x1a040040
Address@app_clustop_ppu : 0x1bc00040
Address@app_core_ppu0 : 0x1bc10040
Address@secenc_secenctop_ppu : 0x5008d040
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 20 "00"
devactive10_edge
For q-channel: Reserved.
For p-channel: devactive 10 edge sensitivity.
19 - 18 "00"
devactive09_edge
For q-channel: Reserved.
For p-channel: devactive 9 edge sensitivity.
17 - 16 "00"
devactive08_edge
For q-channel: Reserved.
For p-channel: devactive 8 edge sensitivity.
15 - 14 "00"
devactive07_edge
devactive 7 edge sensitivity.
13 - 12 "00"
devactive06_edge
devactive 6 edge sensitivity.
11 - 10 "00"
devactive05_edge
devactive 5 edge sensitivity.
9 - 8 "00"
devactive04_edge
devactive 4 edge sensitivity.
7 - 6 "00"
devactive03_edge
devactive 3 edge sensitivity.
5 - 4 "00"
devactive02_edge
devactive 2 edge sensitivity.
3 - 2 "00"
devactive01_edge
devactive 1 edge sensitivity.
1 - 0 "00"
devactive00_edge
For q-channel: devactive 0 edge sensitivity.
For p-channel: Reserved.


ppu_opsr
Operating Mode Active Edge Sensitivity Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020044
Address@app_systop_ppu : 0x1a030044
Address@app_dbgtop_ppu : 0x1a040044
Address@app_clustop_ppu : 0x1bc00044
Address@app_core_ppu0 : 0x1bc10044
Address@secenc_secenctop_ppu : 0x5008d044
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 14 "00"
devactive23_edge
devpactive 23 edge sensitivity
13 - 12 "00"
devactive22_edge
devpactive 22 edge sensitivity
11 - 10 "00"
devactive21_edge
devpactive 21 edge sensitivity
9 - 8 "00"
devactive20_edge
devpactive 20 edge sensitivity
7 - 6 "00"
devactive19_edge
devpactive 19 edge sensitivity
5 - 4 "00"
devactive18_edge
devpactive 18 edge sensitivity
3 - 2 "00"
devactive17_edge
devpactive 17 edge sensitivity
1 - 0 "00"
devactive16_edge
devpactive 16 edge sensitivity


ppu_funrr
Functional Retention RAM Configuration Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020050
Address@app_systop_ppu : 0x1a030050
Address@app_dbgtop_ppu : 0x1a040050
Address@app_clustop_ppu : 0x1bc00050
Address@app_core_ppu0 : 0x1bc10050
Address@secenc_secenctop_ppu : 0x5008d050
Bits Reset value Name Description
31 - 0 0
ppu_funrr


ppu_fulrr
Full Retention RAM Configuration Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020054
Address@app_systop_ppu : 0x1a030054
Address@app_dbgtop_ppu : 0x1a040054
Address@app_clustop_ppu : 0x1bc00054
Address@app_core_ppu0 : 0x1bc10054
Address@secenc_secenctop_ppu : 0x5008d054
Bits Reset value Name Description
31 - 0 0
ppu_fulrr


ppu_memrr
Memory Retention RAM Configuration Register
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020058
Address@app_systop_ppu : 0x1a030058
Address@app_dbgtop_ppu : 0x1a040058
Address@app_clustop_ppu : 0x1bc00058
Address@app_core_ppu0 : 0x1bc10058
Address@secenc_secenctop_ppu : 0x5008d058
Bits Reset value Name Description
31 - 0 0
ppu_memrr


ppu_edtr0
Power Mode Entry Delay Register 0
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020160
Address@app_systop_ppu : 0x1a030160
Address@app_dbgtop_ppu : 0x1a040160
Address@app_clustop_ppu : 0x1bc00160
Address@app_core_ppu0 : 0x1bc10160
Address@secenc_secenctop_ppu : 0x5008d160
Bits Reset value Name Description
31 - 24 "00000000"
full_ret_del
Delay to entering full_ret.
If full_ret is not supported this field is reserved.
23 - 16 "00000000"
logic_ret_del
Delay to entering logic_ret.
If logic_ret is not supported this field is reserved.
15 - 8 "00000000"
mem_ret_del
Delay to entering mem_ret and mem_ret_emu.
If mem_ret is not supported, then this field is reserved.
7 - 0 "00000000"
off_del
Delay to entering off and off_emu.


ppu_edtr1
Power Mode Entry Delay Register 1
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020164
Address@app_systop_ppu : 0x1a030164
Address@app_dbgtop_ppu : 0x1a040164
Address@app_clustop_ppu : 0x1bc00164
Address@app_core_ppu0 : 0x1bc10164
Address@secenc_secenctop_ppu : 0x5008d164
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
func_ret_del
Delay to entering func_ret.
If func_ret is not supported this field is reserved.
7 - 0 "00000000"
mem_off_del
Delay to entering mem_off.
If mem_off is not supported this field is reserved.


ppu_dcdr0
Device Control Delay Configuration Register 0
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020170
Address@app_systop_ppu : 0x1a030170
Address@app_dbgtop_ppu : 0x1a040170
Address@app_clustop_ppu : 0x1bc00170
Address@app_core_ppu0 : 0x1bc10170
Address@secenc_secenctop_ppu : 0x5008d170
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000000"
rst_hwstat_dly
Delay from reset de-assertion to hwstat update.
15 - 8 "00000000"
iso_clken_dly
Delay from isolation enable de-assertion to clock enable assertion.
7 - 0 "00000000"
clken_rst_dly
Delay from clock enable assertion to reset de-assertion.


ppu_dcdr1
Device Control Delay Configuration Register 1
R/W
0x00000000
Address@app_firewall_ppu : 0x1a020174
Address@app_systop_ppu : 0x1a030174
Address@app_dbgtop_ppu : 0x1a040174
Address@app_clustop_ppu : 0x1bc00174
Address@app_core_ppu0 : 0x1bc10174
Address@secenc_secenctop_ppu : 0x5008d174
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
clken_iso_dly
Delay from clock enable de-assertion to isolation enable assertion.
7 - 0 "00000000"
iso_rst_dly
Delay from isolation enable assertion to reset assertion.


ppu_idr0
PPU Identification Register 0
R
Address@app_firewall_ppu : 0x1a020fb0
Address@app_systop_ppu : 0x1a030fb0
Address@app_dbgtop_ppu : 0x1a040fb0
Address@app_clustop_ppu : 0x1bc00fb0
Address@app_core_ppu0 : 0x1bc10fb0
Address@secenc_secenctop_ppu : 0x5008dfb0
Bits Name Description
31 - 30 -
 reserved
29 dyn_wrm_rst_spt
Dynamic warm_rst support.
Always set to 0b0 for a q-channel ppu.
28 dyn_on_spt
Dynamic on support.
27 dyn_func_ret_spt
Dynamic func_ret support.
26 dyn_full_ret_spt
Dynamic full_ret support.
25 dyn_mem_off_spt
Dynamic mem_off support.
24 dyn_lgc_ret_spt
Dynamic logic_ret support.
Always set to 0b0 for a q-channel ppu.
23 dyn_mem_ret_emu_spt
Dynamic mem_ret_emu support
22 dyn_mem_ret_spt
Dynamic mem_ret support.
21 dyn_off_emu_spt
Dynamic off_emu support.
20 dyn_off_spt
Dynamic off support.
19 -
 reserved
18 sta_dbg_recov_spt
dbg_recov support.
Always set to 0b0 for a q-channel ppu.
17 sta_wrm_rst_spt
warm_rst support.
16 sta_on_spt
on support.
15 sta_func_ret_spt
func_ret support.
14 sta_full_ret_spt
full_ret support.
13 sta_mem_off_spt
mem_off support.
12 sta_lgc_ret_spt
logic_ret support.
Always set to 0b0 for a q-channel ppu.
11 sta_mem_ret_emu_spt
mem_ret_emu support.
10 sta_mem_ret_spt
mem_ret support.
9 sta_off_emu_spt
off_emu support.
8 sta_off_spt
off support.
7 - 4 num_opmode
No. of operating modes supported is num_opmode + 1.
3 - 0 devchan
No. of Device Interface Channels
- q-channel ppu: The number of q-channels (minimum of 1).
- p-channel ppu: Set to 0.


ppu_idr1
PPU Identification Register 1
R
Address@app_firewall_ppu : 0x1a020fb4
Address@app_systop_ppu : 0x1a030fb4
Address@app_dbgtop_ppu : 0x1a040fb4
Address@app_clustop_ppu : 0x1bc00fb4
Address@app_core_ppu0 : 0x1bc10fb4
Address@secenc_secenctop_ppu : 0x5008dfb4
Bits Name Description
31 - 13 -
 reserved
12 off_mem_ret_trans
off to mem_ret direct transition.
Indicates if direct transitions from off to mem_ret and from off_emu to mem_ret_emu are supported.
11 -
 reserved
10 op_active
Operating mode use model for dynamic transitions.
9 sta_policy_op_irq_spt
Operating policy transition completion event status.
8 sta_policy_pwr_irq_spt
Power policy transition completion event status.
7 -
 reserved
6 func_ret_ram_reg
Indicates if the ppu_funrr register is present or reserved.
0b0 - Reserved.
0b1 - Present.
5 full_ret_ram_reg
Indicates if the ppu_fulrr register is present or reserved.
0b0 - Reserved.
0b1 - Present.
4 mem_ret_ram_reg
Indicates if the ppu_memrr register is present or reserved.
0b0 - Reserved.
0b1 - Present.
3 -
 reserved
2 lock_spt
Lock and the lock interrupt event are supported.
1 sw_dev_del_spt
Software device delay control configuration support.
0 pwr_mode_entry_del_spt
Power mode entry delay support.


ppu_iidr
Implementation Identification Register
R
Address@app_firewall_ppu : 0x1a020fc8
Address@app_systop_ppu : 0x1a030fc8
Address@app_dbgtop_ppu : 0x1a040fc8
Address@app_clustop_ppu : 0x1bc00fc8
Address@app_core_ppu0 : 0x1bc10fc8
Address@secenc_secenctop_ppu : 0x5008dfc8
Bits Name Description
31 - 20 product_id
IMPLEMENTATION DEFINED value identifying the ppu part.
19 - 16 variant
IMPLEMENTATION DEFINED value used to distinguish product variants, or major revisions of the product.
15 - 12 revision
IMPLEMENTATION DEFINED value used to distinguish minor revisions of the product.
11 - 0 implementer
Implementer identification.
[11:8] The JEP106 continuation code of the implementer.
[7] Always 0.
[6:0] The JEP106 identity code of the implementer.
For an arm implementation, bits [11:0] are 0x43b.


ppu_aidr
Architecture Identification Register
R
Address@app_firewall_ppu : 0x1a020fcc
Address@app_systop_ppu : 0x1a030fcc
Address@app_dbgtop_ppu : 0x1a040fcc
Address@app_clustop_ppu : 0x1bc00fcc
Address@app_core_ppu0 : 0x1bc10fcc
Address@secenc_secenctop_ppu : 0x5008dfcc
Bits Name Description
31 - 8 -
 reserved
7 - 4 arch_rev_major
0x1 - ppu architecture major revision 1.
Other Values - Reserved.
3 - 0 arch_rev_minor
0x1 - ppu Architecture minor revision 1.
Other Values - Reserved.


ppu_pid4
Peripheral ID Register 4
R
Address@app_firewall_ppu : 0x1a020fd0
Address@app_systop_ppu : 0x1a030fd0
Address@app_dbgtop_ppu : 0x1a040fd0
Address@app_clustop_ppu : 0x1bc00fd0
Address@app_core_ppu0 : 0x1bc10fd0
Address@secenc_secenctop_ppu : 0x5008dfd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


ppu_pid5
Peripheral ID Register 5
R
Address@app_firewall_ppu : 0x1a020fd4
Address@app_systop_ppu : 0x1a030fd4
Address@app_dbgtop_ppu : 0x1a040fd4
Address@app_clustop_ppu : 0x1bc00fd4
Address@app_core_ppu0 : 0x1bc10fd4
Address@secenc_secenctop_ppu : 0x5008dfd4
Bits Name Description
31 - 0 ppu_pid5


ppu_pid6
Peripheral ID Register 6
R
Address@app_firewall_ppu : 0x1a020fd8
Address@app_systop_ppu : 0x1a030fd8
Address@app_dbgtop_ppu : 0x1a040fd8
Address@app_clustop_ppu : 0x1bc00fd8
Address@app_core_ppu0 : 0x1bc10fd8
Address@secenc_secenctop_ppu : 0x5008dfd8
Bits Name Description
31 - 0 ppu_pid6


ppu_pid7
Peripheral ID Register 7
R
Address@app_firewall_ppu : 0x1a020fdc
Address@app_systop_ppu : 0x1a030fdc
Address@app_dbgtop_ppu : 0x1a040fdc
Address@app_clustop_ppu : 0x1bc00fdc
Address@app_core_ppu0 : 0x1bc10fdc
Address@secenc_secenctop_ppu : 0x5008dfdc
Bits Name Description
31 - 0 ppu_pid7


ppu_pid0
Peripheral ID Register 0
R
Address@app_firewall_ppu : 0x1a020fe0
Address@app_systop_ppu : 0x1a030fe0
Address@app_dbgtop_ppu : 0x1a040fe0
Address@app_clustop_ppu : 0x1bc00fe0
Address@app_core_ppu0 : 0x1bc10fe0
Address@secenc_secenctop_ppu : 0x5008dfe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part id


ppu_pid1
Peripheral ID Register 1
R
Address@app_firewall_ppu : 0x1a020fe4
Address@app_systop_ppu : 0x1a030fe4
Address@app_dbgtop_ppu : 0x1a040fe4
Address@app_clustop_ppu : 0x1bc00fe4
Address@app_core_ppu0 : 0x1bc10fe4
Address@secenc_secenctop_ppu : 0x5008dfe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of jep 106 identity
3 - 0 part_1
Bits [11:8] of part id


ppu_pid2
Peripheral ID Register 2
R
Address@app_firewall_ppu : 0x1a020fe8
Address@app_systop_ppu : 0x1a030fe8
Address@app_dbgtop_ppu : 0x1a040fe8
Address@app_clustop_ppu : 0x1bc00fe8
Address@app_core_ppu0 : 0x1bc10fe8
Address@secenc_secenctop_ppu : 0x5008dfe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of jedec jep106 identification scheme
2 - 0 des_1
Bits [6:4] of jep 106 identity


ppu_pid3
Peripheral ID Register 3
R
Address@app_firewall_ppu : 0x1a020fec
Address@app_systop_ppu : 0x1a030fec
Address@app_dbgtop_ppu : 0x1a040fec
Address@app_clustop_ppu : 0x1bc00fec
Address@app_core_ppu0 : 0x1bc10fec
Address@secenc_secenctop_ppu : 0x5008dfec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


ppu_cid0
Component ID Register 0
R
Address@app_firewall_ppu : 0x1a020ff0
Address@app_systop_ppu : 0x1a030ff0
Address@app_dbgtop_ppu : 0x1a040ff0
Address@app_clustop_ppu : 0x1bc00ff0
Address@app_core_ppu0 : 0x1bc10ff0
Address@secenc_secenctop_ppu : 0x5008dff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


ppu_cid1
Component ID Register 1
R
Address@app_firewall_ppu : 0x1a020ff4
Address@app_systop_ppu : 0x1a030ff4
Address@app_dbgtop_ppu : 0x1a040ff4
Address@app_clustop_ppu : 0x1bc00ff4
Address@app_core_ppu0 : 0x1bc10ff4
Address@secenc_secenctop_ppu : 0x5008dff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


ppu_cid2
Component ID Register 2
R
Address@app_firewall_ppu : 0x1a020ff8
Address@app_systop_ppu : 0x1a030ff8
Address@app_dbgtop_ppu : 0x1a040ff8
Address@app_clustop_ppu : 0x1bc00ff8
Address@app_core_ppu0 : 0x1bc10ff8
Address@secenc_secenctop_ppu : 0x5008dff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


ppu_cid3
Component ID Register 3
R
Address@app_firewall_ppu : 0x1a020ffc
Address@app_systop_ppu : 0x1a030ffc
Address@app_dbgtop_ppu : 0x1a040ffc
Address@app_clustop_ppu : 0x1bc00ffc
Address@app_core_ppu0 : 0x1bc10ffc
Address@secenc_secenctop_ppu : 0x5008dffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: refclk_cnt_ctrl, s32k_cnt_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cnt_ctrl_cntcr
1 4 R cnt_ctrl_cntsr
2 8 R/W cnt_ctrl_cntcv0
3 c R/W cnt_ctrl_cntcv1
4-6 10-18 -  reserved
7 1c R cnt_ctrl_cntid
8 20 R/W cnt_ctrl_cntfid0
9 24 R/W cnt_ctrl_cntfid1
a-2f 28-bc -  reserved
30 c0 R/W cnt_ctrl_cntscr
31 c4 -  reserved
32 c8 R cnt_ctrl_cntsvl
33 cc R cnt_ctrl_cntsvu
34-3f3 d0-fcc -  reserved
3f4 fd0 R cnt_ctrl_counterid0
3f5 fd4 R cnt_ctrl_counterid1
3f6 fd8 R cnt_ctrl_counterid2
3f7 fdc R cnt_ctrl_counterid3
3f8 fe0 R cnt_ctrl_counterid4
3f9 fe4 R cnt_ctrl_counterid5
3fa fe8 R cnt_ctrl_counterid6
3fb fec R cnt_ctrl_counterid7
3fc ff0 R cnt_ctrl_counterid8
3fd ff4 R cnt_ctrl_counterid9
3fe ff8 R cnt_ctrl_counterid10
3ff ffc R cnt_ctrl_counterid11

cnt_ctrl_cntcr
Counter Control Register
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a200000
Address@s32k_cnt_ctrl : 0x1a400000
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 8 0x0
fcreq
Frequency change request. Indicates the number of the entry in the Frequency modes table to select.
Selecting an unimplemented entry, or an entry that contains 0, has no effect on the counter.
7 - 3 0
-
 reserved
2 "0"
scen
Scale Enable.
0b0 Scaling is not enabled. The counter value is incremented by 0x1.0000000 for each counter tick.
0b1 Scaling is enabled. The counter is incremented by cntscr.scaleval for each counter tick.
The scen bit can only be changed when the counter is disabled, when cntcr.en == 0.
1 "0"
hdbg
Halt-on-debug. Controls whether a Halt-on-debug signal halts the system counter:
0b0 System counter ignores Halt-on-debug.
0b1 Asserted Halt-on-debug signal halts system counter update.
0 "0"
en
Enables the counter:
0b0 System counter disabled.
0b1 System counter enabled.


cnt_ctrl_cntsr
Counter Status Register
R
Address@refclk_cnt_ctrl : 0x1a200004
Address@s32k_cnt_ctrl : 0x1a400004
Bits Name Description
31 - 8 fcack
Frequency change acknowledge.
7 - 2 -
 reserved
1 dbgh
Indicates whether the counter is halted because the Halt-on-debug signal is asserted:
0b0 Counter is not halted.
0b1 Counter is halted.
0 -
 reserved


cnt_ctrl_cntcv0
Counter Count Value register 0
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a200008
Address@s32k_cnt_ctrl : 0x1a400008
Bits Reset value Name Description
31 - 0 0x0
countvalue
Indicates the counter value [31:0]


cnt_ctrl_cntcv1
Counter Count Value register 1
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a20000c
Address@s32k_cnt_ctrl : 0x1a40000c
Bits Reset value Name Description
31 - 0 0x0
countvalue
Indicates the counter value [63:32]


cnt_ctrl_cntid
Counter Identification Register
R
Address@refclk_cnt_ctrl : 0x1a20001c
Address@s32k_cnt_ctrl : 0x1a40001c
Bits Name Description
31 - 4 -
 reserved
3 - 0 cntsc
Indicates whether Counter Scaling is implemented.
0b0000: Counter scaling is not implemented.
0b0001: Counter scaling is implemented.
All other values are reserved.


cnt_ctrl_cntfid0
Counter Frequency ID 0
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a200020
Address@s32k_cnt_ctrl : 0x1a400020
Bits Reset value Name Description
31 - 0 0x0
frequency
The base frequency of the system counter, in Hz.


cnt_ctrl_cntfid1
Counter Frequency ID 1
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a200024
Address@s32k_cnt_ctrl : 0x1a400024
Bits Reset value Name Description
31 - 0 0x0
frequency
A system counter update frequency, in Hz.
Must be an exact divisor of the base frequency.
Arm strongly recommends that all frequency values in the Frequency modes table are integer power-of-two divisors of the base frequency.
When the system timer is operating at a lower frequency than the base frequency, the increment applied at each counter update is given by:
increment = (base frequency) / (selected frequency)


cnt_ctrl_cntscr
Counter Scale Register
R/W
0x00000000
Address@refclk_cnt_ctrl : 0x1a2000c0
Address@s32k_cnt_ctrl : 0x1a4000c0
Bits Reset value Name Description
31 - 0 0x0
scaleval
Scale Value.
When counter scaling is enabled, scaleval is the amount added to the counter value for every counter tick.
Counter tick is defined as one period of the current operating frequency of the Generic counter.
scaleval is expressed as an unsigned fixed point number with an 8-bit integer value and a 24-bit fractional value.
cntscr.scaleval can only be changed when cntcr.en == 0.
If the value of this field is changed when cntcr.en == 1:
- The counter value becomes UNKNOWN.
- The counter value remains UNKNOWN on future ticks of the clock.


cnt_ctrl_cntsvl
R
Address@refclk_cnt_ctrl : 0x1a2000c8
Address@s32k_cnt_ctrl : 0x1a4000c8
Bits Name Description
31 - 0 cnt_ctrl_cntsvl


cnt_ctrl_cntsvu
R
Address@refclk_cnt_ctrl : 0x1a2000cc
Address@s32k_cnt_ctrl : 0x1a4000cc
Bits Name Description
31 - 0 cnt_ctrl_cntsvu


cnt_ctrl_counterid0
Peripheral ID Register 4
R
Address@refclk_cnt_ctrl : 0x1a200fd0
Address@s32k_cnt_ctrl : 0x1a400fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


cnt_ctrl_counterid1
Peripheral ID Register 5
R
Address@refclk_cnt_ctrl : 0x1a200fd4
Address@s32k_cnt_ctrl : 0x1a400fd4
Bits Name Description
31 - 0 cnt_ctrl_counterid1


cnt_ctrl_counterid2
Peripheral ID Register 6
R
Address@refclk_cnt_ctrl : 0x1a200fd8
Address@s32k_cnt_ctrl : 0x1a400fd8
Bits Name Description
31 - 0 cnt_ctrl_counterid2


cnt_ctrl_counterid3
Peripheral ID Register 7
R
Address@refclk_cnt_ctrl : 0x1a200fdc
Address@s32k_cnt_ctrl : 0x1a400fdc
Bits Name Description
31 - 0 cnt_ctrl_counterid3


cnt_ctrl_counterid4
Peripheral ID Register 0
R
Address@refclk_cnt_ctrl : 0x1a200fe0
Address@s32k_cnt_ctrl : 0x1a400fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cnt_ctrl_counterid5
Peripheral ID Register 1
R
Address@refclk_cnt_ctrl : 0x1a200fe4
Address@s32k_cnt_ctrl : 0x1a400fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cnt_ctrl_counterid6
Peripheral ID Register 2
R
Address@refclk_cnt_ctrl : 0x1a200fe8
Address@s32k_cnt_ctrl : 0x1a400fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


cnt_ctrl_counterid7
Peripheral ID Register 3
R
Address@refclk_cnt_ctrl : 0x1a200fec
Address@s32k_cnt_ctrl : 0x1a400fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


cnt_ctrl_counterid8
Component ID Register 0
R
Address@refclk_cnt_ctrl : 0x1a200ff0
Address@s32k_cnt_ctrl : 0x1a400ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cnt_ctrl_counterid9
Component ID Register 1
R
Address@refclk_cnt_ctrl : 0x1a200ff4
Address@s32k_cnt_ctrl : 0x1a400ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cnt_ctrl_counterid10
Component ID Register 2
R
Address@refclk_cnt_ctrl : 0x1a200ff8
Address@s32k_cnt_ctrl : 0x1a400ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cnt_ctrl_counterid11
Component ID Register 3
R
Address@refclk_cnt_ctrl : 0x1a200ffc
Address@s32k_cnt_ctrl : 0x1a400ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: refclk_cnt_read, s32k_cnt_read

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cnt_read_cntcv0
1 4 R/W cnt_read_cntcv1
2-3f3 8-fcc -  reserved
3f4 fd0 R cnt_read_counterid0
3f5 fd4 R cnt_read_counterid1
3f6 fd8 R cnt_read_counterid2
3f7 fdc R cnt_read_counterid3
3f8 fe0 R cnt_read_counterid4
3f9 fe4 R cnt_read_counterid5
3fa fe8 R cnt_read_counterid6
3fb fec R cnt_read_counterid7
3fc ff0 R cnt_read_counterid8
3fd ff4 R cnt_read_counterid9
3fe ff8 R cnt_read_counterid10
3ff ffc R cnt_read_counterid11

cnt_read_cntcv0
Counter Count Value register 0
R/W
0x00000000
Address@refclk_cnt_read : 0x1a210000
Address@s32k_cnt_read : 0x1a410000
Bits Reset value Name Description
31 - 0 0x0
countvalue
Indicates the counter value [31:0]


cnt_read_cntcv1
Counter Count Value register 1
R/W
0x00000000
Address@refclk_cnt_read : 0x1a210004
Address@s32k_cnt_read : 0x1a410004
Bits Reset value Name Description
31 - 0 0x0
countvalue
Indicates the counter value [63:32]


cnt_read_counterid0
Peripheral ID Register 4
R
Address@refclk_cnt_read : 0x1a210fd0
Address@s32k_cnt_read : 0x1a410fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


cnt_read_counterid1
Peripheral ID Register 5
R
Address@refclk_cnt_read : 0x1a210fd4
Address@s32k_cnt_read : 0x1a410fd4
Bits Name Description
31 - 0 cnt_read_counterid1


cnt_read_counterid2
Peripheral ID Register 6
R
Address@refclk_cnt_read : 0x1a210fd8
Address@s32k_cnt_read : 0x1a410fd8
Bits Name Description
31 - 0 cnt_read_counterid2


cnt_read_counterid3
Peripheral ID Register 7
R
Address@refclk_cnt_read : 0x1a210fdc
Address@s32k_cnt_read : 0x1a410fdc
Bits Name Description
31 - 0 cnt_read_counterid3


cnt_read_counterid4
Peripheral ID Register 0
R
Address@refclk_cnt_read : 0x1a210fe0
Address@s32k_cnt_read : 0x1a410fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cnt_read_counterid5
Peripheral ID Register 1
R
Address@refclk_cnt_read : 0x1a210fe4
Address@s32k_cnt_read : 0x1a410fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cnt_read_counterid6
Peripheral ID Register 2
R
Address@refclk_cnt_read : 0x1a210fe8
Address@s32k_cnt_read : 0x1a410fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


cnt_read_counterid7
Peripheral ID Register 3
R
Address@refclk_cnt_read : 0x1a210fec
Address@s32k_cnt_read : 0x1a410fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


cnt_read_counterid8
Component ID Register 0
R
Address@refclk_cnt_read : 0x1a210ff0
Address@s32k_cnt_read : 0x1a410ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cnt_read_counterid9
Component ID Register 1
R
Address@refclk_cnt_read : 0x1a210ff4
Address@s32k_cnt_read : 0x1a410ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cnt_read_counterid10
Component ID Register 2
R
Address@refclk_cnt_read : 0x1a210ff8
Address@s32k_cnt_read : 0x1a410ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cnt_read_counterid11
Component ID Register 3
R
Address@refclk_cnt_read : 0x1a210ffc
Address@s32k_cnt_read : 0x1a410ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: refclk_cnt_ctl, s32k_cnt_ctl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cnt_ctl_cntfrq
1 4 R/W cnt_ctl_cntnsar
2 8 R/W cnt_ctl_cnttidr
3-f c-3c -  reserved
10 40 R/W cnt_ctl_cntacr0
11 44 R/W cnt_ctl_cntacr1
12 48 R/W cnt_ctl_cntacr2
13 4c R/W cnt_ctl_cntacr3
14-3f3 50-fcc -  reserved
3f4 fd0 R cnt_ctl_counterid0
3f5 fd4 R cnt_ctl_counterid1
3f6 fd8 R cnt_ctl_counterid2
3f7 fdc R cnt_ctl_counterid3
3f8 fe0 R cnt_ctl_counterid4
3f9 fe4 R cnt_ctl_counterid5
3fa fe8 R cnt_ctl_counterid6
3fb fec R cnt_ctl_counterid7
3fc ff0 R cnt_ctl_counterid8
3fd ff4 R cnt_ctl_counterid9
3fe ff8 R cnt_ctl_counterid10
3ff ffc R cnt_ctl_counterid11

cnt_ctl_cntfrq
Counter Frequency register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220000
Address@s32k_cnt_ctl : 0x1a420000
Bits Reset value Name Description
31 - 0 0x0
clock_frequency
Clock frequency. Indicates the system counter clock frequency, in Hz


cnt_ctl_cntnsar
Counter Non-Secure Access register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220004
Address@s32k_cnt_ctl : 0x1a420004
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
ns_vector
Non-secure access to frame 0..7. The possible values of each bit are:
0b0: Secure access only. Behaves as RES0 to Non-secure accesses.
0b1: Secure and Non-secure accesses permitted.


cnt_ctl_cnttidr
Counter Timer ID register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220008
Address@s32k_cnt_ctl : 0x1a420008
Bits Reset value Name Description
31 - 28 "0000"
frame7
A 4-bit field indicating the features of frame cntbase7
27 - 24 "0000"
frame6
A 4-bit field indicating the features of frame cntbase6
23 - 20 "0000"
frame5
A 4-bit field indicating the features of frame cntbase5
19 - 16 "0000"
frame4
A 4-bit field indicating the features of frame cntbase4
15 - 12 "0000"
frame3
A 4-bit field indicating the features of frame cntbase3
11 - 8 "0000"
frame2
A 4-bit field indicating the features of frame cntbase2
7 - 4 "0000"
frame1
A 4-bit field indicating the features of frame cntbase1
3 - 0 "0000"
frame0
A 4-bit field indicating the features of frame cntbase0


cnt_ctl_cntacr0
Counter 0 Access Control register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220040
Address@s32k_cnt_ctl : 0x1a420040
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rwpt
Read/write access to the EL1 Physical Timer registers cntp_cval, cntp_tval, and cntp_ctl.
4 "0"
rwvt
Read/write access to the Virtual Timer register cntv_cval, cntv_tval, and cntv_ctl.
3 "0"
rvoff
Read-only access to cntvoff.
2 "0"
rfrq
Read-only access to cntfrq.
1 "0"
rvct
Read-only access to cntvct.
0 "0"
rpct
Read-only access to cntpct.


cnt_ctl_cntacr1
Counter 1 Access Control register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220044
Address@s32k_cnt_ctl : 0x1a420044
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rwpt
Read/write access to the EL1 Physical Timer registers cntp_cval, cntp_tval, and cntp_ctl.
4 "0"
rwvt
Read/write access to the Virtual Timer register cntv_cval, cntv_tval, and cntv_ctl.
3 "0"
rvoff
Read-only access to cntvoff.
2 "0"
rfrq
Read-only access to cntfrq.
1 "0"
rvct
Read-only access to cntvct.
0 "0"
rpct
Read-only access to cntpct.


cnt_ctl_cntacr2
Counter 2 Access Control register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a220048
Address@s32k_cnt_ctl : 0x1a420048
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rwpt
Read/write access to the EL1 Physical Timer registers cntp_cval, cntp_tval, and cntp_ctl.
4 "0"
rwvt
Read/write access to the Virtual Timer register cntv_cval, cntv_tval, and cntv_ctl.
3 "0"
rvoff
Read-only access to cntvoff.
2 "0"
rfrq
Read-only access to cntfrq.
1 "0"
rvct
Read-only access to cntvct.
0 "0"
rpct
Read-only access to cntpct.


cnt_ctl_cntacr3
Counter 3 Access Control register
R/W
0x00000000
Address@refclk_cnt_ctl : 0x1a22004c
Address@s32k_cnt_ctl : 0x1a42004c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
rwpt
Read/write access to the EL1 Physical Timer registers cntp_cval, cntp_tval, and cntp_ctl.
4 "0"
rwvt
Read/write access to the Virtual Timer register cntv_cval, cntv_tval, and cntv_ctl.
3 "0"
rvoff
Read-only access to cntvoff.
2 "0"
rfrq
Read-only access to cntfrq.
1 "0"
rvct
Read-only access to cntvct.
0 "0"
rpct
Read-only access to cntpct.


cnt_ctl_counterid0
Peripheral ID Register 4
R
Address@refclk_cnt_ctl : 0x1a220fd0
Address@s32k_cnt_ctl : 0x1a420fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


cnt_ctl_counterid1
Peripheral ID Register 5
R
Address@refclk_cnt_ctl : 0x1a220fd4
Address@s32k_cnt_ctl : 0x1a420fd4
Bits Name Description
31 - 0 cnt_ctl_counterid1


cnt_ctl_counterid2
Peripheral ID Register 6
R
Address@refclk_cnt_ctl : 0x1a220fd8
Address@s32k_cnt_ctl : 0x1a420fd8
Bits Name Description
31 - 0 cnt_ctl_counterid2


cnt_ctl_counterid3
Peripheral ID Register 7
R
Address@refclk_cnt_ctl : 0x1a220fdc
Address@s32k_cnt_ctl : 0x1a420fdc
Bits Name Description
31 - 0 cnt_ctl_counterid3


cnt_ctl_counterid4
Peripheral ID Register 0
R
Address@refclk_cnt_ctl : 0x1a220fe0
Address@s32k_cnt_ctl : 0x1a420fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cnt_ctl_counterid5
Peripheral ID Register 1
R
Address@refclk_cnt_ctl : 0x1a220fe4
Address@s32k_cnt_ctl : 0x1a420fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cnt_ctl_counterid6
Peripheral ID Register 2
R
Address@refclk_cnt_ctl : 0x1a220fe8
Address@s32k_cnt_ctl : 0x1a420fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


cnt_ctl_counterid7
Peripheral ID Register 3
R
Address@refclk_cnt_ctl : 0x1a220fec
Address@s32k_cnt_ctl : 0x1a420fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


cnt_ctl_counterid8
Component ID Register 0
R
Address@refclk_cnt_ctl : 0x1a220ff0
Address@s32k_cnt_ctl : 0x1a420ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cnt_ctl_counterid9
Component ID Register 1
R
Address@refclk_cnt_ctl : 0x1a220ff4
Address@s32k_cnt_ctl : 0x1a420ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cnt_ctl_counterid10
Component ID Register 2
R
Address@refclk_cnt_ctl : 0x1a220ff8
Address@s32k_cnt_ctl : 0x1a420ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cnt_ctl_counterid11
Component ID Register 3
R
Address@refclk_cnt_ctl : 0x1a220ffc
Address@s32k_cnt_ctl : 0x1a420ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: refclk_cnt0, refclk_cnt1, refclk_cnt2, refclk_cnt3, s32k_cnt0, s32k_cnt1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R cnt_cntpct0
1 4 R cnt_cntpct1
2 8 R cnt_cntvct0
3 c R cnt_cntvct1
4 10 R cnt_cntfrq
5 14 R/W cnt_cntel0acr
6 18 R cnt_cntvoff0
7 1c R cnt_cntvoff1
8 20 R/W cnt_cntp_cval0
9 24 R/W cnt_cntp_cval1
a 28 R/W cnt_cntp_tval
b 2c R/W cnt_cntp_ctl
c 30 R/W cnt_cntv_cval0
d 34 R/W cnt_cntv_cval1
e 38 R/W cnt_cntv_tval
f 3c R/W cnt_cntv_ctl
10-3f3 40-fcc -  reserved
3f4 fd0 R cnt_counterid0
3f5 fd4 R cnt_counterid1
3f6 fd8 R cnt_counterid2
3f7 fdc R cnt_counterid3
3f8 fe0 R cnt_counterid4
3f9 fe4 R cnt_counterid5
3fa fe8 R cnt_counterid6
3fb fec R cnt_counterid7
3fc ff0 R cnt_counterid8
3fd ff4 R cnt_counterid9
3fe ff8 R cnt_counterid10
3ff ffc R cnt_counterid11

cnt_cntpct0
Physical Count register 0
R
Address@refclk_cnt0 : 0x1a230000
Address@refclk_cnt1 : 0x1a240000
Address@refclk_cnt2 : 0x1a250000
Address@refclk_cnt3 : 0x1a260000
Address@s32k_cnt0 : 0x1a430000
Address@s32k_cnt1 : 0x1a440000
Bits Name Description
31 - 0 count_value
Physical count value bits 31:0


cnt_cntpct1
Physical Count register 1
R
Address@refclk_cnt0 : 0x1a230004
Address@refclk_cnt1 : 0x1a240004
Address@refclk_cnt2 : 0x1a250004
Address@refclk_cnt3 : 0x1a260004
Address@s32k_cnt0 : 0x1a430004
Address@s32k_cnt1 : 0x1a440004
Bits Name Description
31 - 0 count_value
Physical count value bits 63:32


cnt_cntvct0
Virtual Count register 0
R
Address@refclk_cnt0 : 0x1a230008
Address@refclk_cnt1 : 0x1a240008
Address@refclk_cnt2 : 0x1a250008
Address@refclk_cnt3 : 0x1a260008
Address@s32k_cnt0 : 0x1a430008
Address@s32k_cnt1 : 0x1a440008
Bits Name Description
31 - 0 count_value
Virtual count value bits 31:0


cnt_cntvct1
Virtual Count register 1
R
Address@refclk_cnt0 : 0x1a23000c
Address@refclk_cnt1 : 0x1a24000c
Address@refclk_cnt2 : 0x1a25000c
Address@refclk_cnt3 : 0x1a26000c
Address@s32k_cnt0 : 0x1a43000c
Address@s32k_cnt1 : 0x1a44000c
Bits Name Description
31 - 0 count_value
Virtual count value bits 63:32


cnt_cntfrq
Counter Frequency register
R
Address@refclk_cnt0 : 0x1a230010
Address@refclk_cnt1 : 0x1a240010
Address@refclk_cnt2 : 0x1a250010
Address@refclk_cnt3 : 0x1a260010
Address@s32k_cnt0 : 0x1a430010
Address@s32k_cnt1 : 0x1a440010
Bits Name Description
31 - 0 clock_frequency
Clock frequency. Indicates the system counter clock frequency, in Hz


cnt_cntel0acr
Counter EL0 Access Control Register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230014
Address@refclk_cnt1 : 0x1a240014
Address@refclk_cnt2 : 0x1a250014
Address@refclk_cnt3 : 0x1a260014
Address@s32k_cnt0 : 0x1a430014
Address@s32k_cnt1 : 0x1a440014
Bits Reset value Name Description
31 - 0 0
cnt_cntel0acr


cnt_cntvoff0
Virtual Offset register
R
Address@refclk_cnt0 : 0x1a230018
Address@refclk_cnt1 : 0x1a240018
Address@refclk_cnt2 : 0x1a250018
Address@refclk_cnt3 : 0x1a260018
Address@s32k_cnt0 : 0x1a430018
Address@s32k_cnt1 : 0x1a440018
Bits Name Description
31 - 0 cnt_cntvoff0


cnt_cntvoff1
Virtual Offset register
R
Address@refclk_cnt0 : 0x1a23001c
Address@refclk_cnt1 : 0x1a24001c
Address@refclk_cnt2 : 0x1a25001c
Address@refclk_cnt3 : 0x1a26001c
Address@s32k_cnt0 : 0x1a43001c
Address@s32k_cnt1 : 0x1a44001c
Bits Name Description
31 - 0 cnt_cntvoff1


cnt_cntp_cval0
Physical Timer CompareValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230020
Address@refclk_cnt1 : 0x1a240020
Address@refclk_cnt2 : 0x1a250020
Address@refclk_cnt3 : 0x1a260020
Address@s32k_cnt0 : 0x1a430020
Address@s32k_cnt1 : 0x1a440020
Bits Reset value Name Description
31 - 0 0x0
compare_value
Holds the EL1 physical timer CompareValue bits 31:0


cnt_cntp_cval1
Physical Timer CompareValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230024
Address@refclk_cnt1 : 0x1a240024
Address@refclk_cnt2 : 0x1a250024
Address@refclk_cnt3 : 0x1a260024
Address@s32k_cnt0 : 0x1a430024
Address@s32k_cnt1 : 0x1a440024
Bits Reset value Name Description
31 - 0 0x0
compare_value
Holds the EL1 physical timer CompareValue bits 63:32


cnt_cntp_tval
Physical TimerValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230028
Address@refclk_cnt1 : 0x1a240028
Address@refclk_cnt2 : 0x1a250028
Address@refclk_cnt3 : 0x1a260028
Address@s32k_cnt0 : 0x1a430028
Address@s32k_cnt1 : 0x1a440028
Bits Reset value Name Description
31 - 0 0x0
timer_value
The TimerValue view of the EL1 physical timer


cnt_cntp_ctl
Physical Timer Control register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a23002c
Address@refclk_cnt1 : 0x1a24002c
Address@refclk_cnt2 : 0x1a25002c
Address@refclk_cnt3 : 0x1a26002c
Address@s32k_cnt0 : 0x1a43002c
Address@s32k_cnt1 : 0x1a44002c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
istatus
The status of the timer. This bit indicates whether the timer condition is met:
0b0: Timer condition is not met.
0b1: Timer condition is met.
1 "0"
imask
Timer interrupt mask bit. Permitted values are:
0b0: Timer interrupt is not masked by the imask bit
0b1: Timer interrupt is masked by the imask bit
0 "0"
enable
Enables the timer. Permitted values are:
0b0: Timer disabled
0b1: Timer enabled


cnt_cntv_cval0
Virtual Timer CompareValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230030
Address@refclk_cnt1 : 0x1a240030
Address@refclk_cnt2 : 0x1a250030
Address@refclk_cnt3 : 0x1a260030
Address@s32k_cnt0 : 0x1a430030
Address@s32k_cnt1 : 0x1a440030
Bits Reset value Name Description
31 - 0 0x0
compare_value
Holds the virtual timer CompareValue bits 31:0


cnt_cntv_cval1
Virtual Timer CompareValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230034
Address@refclk_cnt1 : 0x1a240034
Address@refclk_cnt2 : 0x1a250034
Address@refclk_cnt3 : 0x1a260034
Address@s32k_cnt0 : 0x1a430034
Address@s32k_cnt1 : 0x1a440034
Bits Reset value Name Description
31 - 0 0x0
compare_value
Holds the virtual timer CompareValue bits 63:32


cnt_cntv_tval
Virtual TimerValue register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a230038
Address@refclk_cnt1 : 0x1a240038
Address@refclk_cnt2 : 0x1a250038
Address@refclk_cnt3 : 0x1a260038
Address@s32k_cnt0 : 0x1a430038
Address@s32k_cnt1 : 0x1a440038
Bits Reset value Name Description
31 - 0 0x0
timer_value
The TimerValue view of the virtual timer


cnt_cntv_ctl
Virtual Timer Control register
R/W
0x00000000
Address@refclk_cnt0 : 0x1a23003c
Address@refclk_cnt1 : 0x1a24003c
Address@refclk_cnt2 : 0x1a25003c
Address@refclk_cnt3 : 0x1a26003c
Address@s32k_cnt0 : 0x1a43003c
Address@s32k_cnt1 : 0x1a44003c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
istatus
The status of the timer. This bit indicates whether the timer condition is met:
0b0: Timer condition is not met.
0b1: Timer condition is met.
1 "0"
imask
Timer interrupt mask bit. Permitted values are:
0b0: Timer interrupt is not masked by the imask bit
0b1: Timer interrupt is masked by the imask bit
0 "0"
enable
Enables the timer. Permitted values are:
0b0: Timer disabled
0b1: Timer enabled


cnt_counterid0
Peripheral ID Register 4
R
Address@refclk_cnt0 : 0x1a230fd0
Address@refclk_cnt1 : 0x1a240fd0
Address@refclk_cnt2 : 0x1a250fd0
Address@refclk_cnt3 : 0x1a260fd0
Address@s32k_cnt0 : 0x1a430fd0
Address@s32k_cnt1 : 0x1a440fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


cnt_counterid1
Peripheral ID Register 5
R
Address@refclk_cnt0 : 0x1a230fd4
Address@refclk_cnt1 : 0x1a240fd4
Address@refclk_cnt2 : 0x1a250fd4
Address@refclk_cnt3 : 0x1a260fd4
Address@s32k_cnt0 : 0x1a430fd4
Address@s32k_cnt1 : 0x1a440fd4
Bits Name Description
31 - 0 cnt_counterid1


cnt_counterid2
Peripheral ID Register 6
R
Address@refclk_cnt0 : 0x1a230fd8
Address@refclk_cnt1 : 0x1a240fd8
Address@refclk_cnt2 : 0x1a250fd8
Address@refclk_cnt3 : 0x1a260fd8
Address@s32k_cnt0 : 0x1a430fd8
Address@s32k_cnt1 : 0x1a440fd8
Bits Name Description
31 - 0 cnt_counterid2


cnt_counterid3
Peripheral ID Register 7
R
Address@refclk_cnt0 : 0x1a230fdc
Address@refclk_cnt1 : 0x1a240fdc
Address@refclk_cnt2 : 0x1a250fdc
Address@refclk_cnt3 : 0x1a260fdc
Address@s32k_cnt0 : 0x1a430fdc
Address@s32k_cnt1 : 0x1a440fdc
Bits Name Description
31 - 0 cnt_counterid3


cnt_counterid4
Peripheral ID Register 0
R
Address@refclk_cnt0 : 0x1a230fe0
Address@refclk_cnt1 : 0x1a240fe0
Address@refclk_cnt2 : 0x1a250fe0
Address@refclk_cnt3 : 0x1a260fe0
Address@s32k_cnt0 : 0x1a430fe0
Address@s32k_cnt1 : 0x1a440fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cnt_counterid5
Peripheral ID Register 1
R
Address@refclk_cnt0 : 0x1a230fe4
Address@refclk_cnt1 : 0x1a240fe4
Address@refclk_cnt2 : 0x1a250fe4
Address@refclk_cnt3 : 0x1a260fe4
Address@s32k_cnt0 : 0x1a430fe4
Address@s32k_cnt1 : 0x1a440fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cnt_counterid6
Peripheral ID Register 2
R
Address@refclk_cnt0 : 0x1a230fe8
Address@refclk_cnt1 : 0x1a240fe8
Address@refclk_cnt2 : 0x1a250fe8
Address@refclk_cnt3 : 0x1a260fe8
Address@s32k_cnt0 : 0x1a430fe8
Address@s32k_cnt1 : 0x1a440fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


cnt_counterid7
Peripheral ID Register 3
R
Address@refclk_cnt0 : 0x1a230fec
Address@refclk_cnt1 : 0x1a240fec
Address@refclk_cnt2 : 0x1a250fec
Address@refclk_cnt3 : 0x1a260fec
Address@s32k_cnt0 : 0x1a430fec
Address@s32k_cnt1 : 0x1a440fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


cnt_counterid8
Component ID Register 0
R
Address@refclk_cnt0 : 0x1a230ff0
Address@refclk_cnt1 : 0x1a240ff0
Address@refclk_cnt2 : 0x1a250ff0
Address@refclk_cnt3 : 0x1a260ff0
Address@s32k_cnt0 : 0x1a430ff0
Address@s32k_cnt1 : 0x1a440ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cnt_counterid9
Component ID Register 1
R
Address@refclk_cnt0 : 0x1a230ff4
Address@refclk_cnt1 : 0x1a240ff4
Address@refclk_cnt2 : 0x1a250ff4
Address@refclk_cnt3 : 0x1a260ff4
Address@s32k_cnt0 : 0x1a430ff4
Address@s32k_cnt1 : 0x1a440ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cnt_counterid10
Component ID Register 2
R
Address@refclk_cnt0 : 0x1a230ff8
Address@refclk_cnt1 : 0x1a240ff8
Address@refclk_cnt2 : 0x1a250ff8
Address@refclk_cnt3 : 0x1a260ff8
Address@s32k_cnt0 : 0x1a430ff8
Address@s32k_cnt1 : 0x1a440ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cnt_counterid11
Component ID Register 3
R
Address@refclk_cnt0 : 0x1a230ffc
Address@refclk_cnt1 : 0x1a240ffc
Address@refclk_cnt2 : 0x1a250ffc
Address@refclk_cnt3 : 0x1a260ffc
Address@s32k_cnt0 : 0x1a430ffc
Address@s32k_cnt1 : 0x1a440ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: app_ns_wdog_ctrl, app_secure_wdog_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W wdg_ctrl_wcs
1 4 -  reserved
2 8 R/W wdg_ctrl_wor0
3 c R/W wdg_ctrl_wor1
4 10 R/W wdg_ctrl_wcv0
5 14 R/W wdg_ctrl_wcv1
6-3f2 18-fc8 -  reserved
3f3 fcc R wdg_ctrl_w_iidr
3f4 fd0 R wdg_ctrl_id0
3f5 fd4 R wdg_ctrl_id1
3f6 fd8 R wdg_ctrl_id2
3f7 fdc R wdg_ctrl_id3
3f8 fe0 R wdg_ctrl_id4
3f9 fe4 R wdg_ctrl_id5
3fa fe8 R wdg_ctrl_id6
3fb fec R wdg_ctrl_id7
3fc ff0 R wdg_ctrl_id8
3fd ff4 R wdg_ctrl_id9
3fe ff8 R wdg_ctrl_id10
3ff ffc R wdg_ctrl_id11

wdg_ctrl_wcs
Watchdog control and status register
R/W
0x00000000
Address@app_ns_wdog_ctrl : 0x1a300000
Address@app_secure_wdog_ctrl : 0x1a320000
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 - 1 "00"
status
A read of these bits indicates the current state of the watchdog signals;
bit [2] reflects the status of ws1 and bit [1] reflects the status of ws0.
A write to these bits has no effect.
0 "0"
enable
A write of 1 to this bit enables the watchdog, a 0 disables the watchdog.
A read of these bits indicates the current state of the watchdog enable.
The watchdog enable bit resets to 0 on watchdog cold reset.


wdg_ctrl_wor0
Watchdog offset register
R/W
0x00000000
Address@app_ns_wdog_ctrl : 0x1a300008
Address@app_secure_wdog_ctrl : 0x1a320008
Bits Reset value Name Description
31 - 0 0x0
offset_value
lower 32 bits of the unsigned watchdog countdown timer value


wdg_ctrl_wor1
Watchdog offset register
R/W
0x00000000
Address@app_ns_wdog_ctrl : 0x1a30000c
Address@app_secure_wdog_ctrl : 0x1a32000c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
offset_value
upper 16 bits of the watchdog countdown timer value


wdg_ctrl_wcv0
Watchdog compare value
R/W
0x00000000
Address@app_ns_wdog_ctrl : 0x1a300010
Address@app_secure_wdog_ctrl : 0x1a320010
Bits Reset value Name Description
31 - 0 0x0
compare_value
current lower watchdog compare value


wdg_ctrl_wcv1
Watchdog compare value
R/W
0x00000000
Address@app_ns_wdog_ctrl : 0x1a300014
Address@app_secure_wdog_ctrl : 0x1a320014
Bits Reset value Name Description
31 - 0 0x0
compare_value
current upper watchdog compare value


wdg_ctrl_w_iidr
Watchdog Interface Identification Register
R
Address@app_ns_wdog_ctrl : 0x1a300fcc
Address@app_secure_wdog_ctrl : 0x1a320fcc
Bits Name Description
31 - 20 productid
An implementation defined product identifier.
19 - 16 arch_version
Revision field for the generic watchdog architecture. The value of this field depends on the generic watchdog architecture version:
0x1 for generic watchdog v1
15 - 12 revision
An implementation defined revision number for the component.
11 - 0 implementer
Contains the jep106 code of the company that implemented the generic watchdog.


wdg_ctrl_id0
Peripheral ID Register 4
R
Address@app_ns_wdog_ctrl : 0x1a300fd0
Address@app_secure_wdog_ctrl : 0x1a320fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4kb occupied by the block. This field is deprecated.
3 - 0 des_2
jep continuation


wdg_ctrl_id1
Peripheral ID Register 5
R
Address@app_ns_wdog_ctrl : 0x1a300fd4
Address@app_secure_wdog_ctrl : 0x1a320fd4
Bits Name Description
31 - 0 wdg_ctrl_id1


wdg_ctrl_id2
Peripheral ID Register 6
R
Address@app_ns_wdog_ctrl : 0x1a300fd8
Address@app_secure_wdog_ctrl : 0x1a320fd8
Bits Name Description
31 - 0 wdg_ctrl_id2


wdg_ctrl_id3
Peripheral ID Register 7
R
Address@app_ns_wdog_ctrl : 0x1a300fdc
Address@app_secure_wdog_ctrl : 0x1a320fdc
Bits Name Description
31 - 0 wdg_ctrl_id3


wdg_ctrl_id4
Peripheral ID Register 0
R
Address@app_ns_wdog_ctrl : 0x1a300fe0
Address@app_secure_wdog_ctrl : 0x1a320fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part id


wdg_ctrl_id5
Peripheral ID Register 1
R
Address@app_ns_wdog_ctrl : 0x1a300fe4
Address@app_secure_wdog_ctrl : 0x1a320fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of jep 106 identity
3 - 0 part_1
Bits [11:8] of part id


wdg_ctrl_id6
Peripheral ID Register 2
R
Address@app_ns_wdog_ctrl : 0x1a300fe8
Address@app_secure_wdog_ctrl : 0x1a320fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of jedec jep106 identification scheme
2 - 0 des_1
Bits [6:4] of jep 106 identity


wdg_ctrl_id7
Peripheral ID Register 3
R
Address@app_ns_wdog_ctrl : 0x1a300fec
Address@app_secure_wdog_ctrl : 0x1a320fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


wdg_ctrl_id8
Component ID Register 0
R
Address@app_ns_wdog_ctrl : 0x1a300ff0
Address@app_secure_wdog_ctrl : 0x1a320ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


wdg_ctrl_id9
Component ID Register 1
R
Address@app_ns_wdog_ctrl : 0x1a300ff4
Address@app_secure_wdog_ctrl : 0x1a320ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


wdg_ctrl_id10
Component ID Register 2
R
Address@app_ns_wdog_ctrl : 0x1a300ff8
Address@app_secure_wdog_ctrl : 0x1a320ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


wdg_ctrl_id11
Component ID Register 3
R
Address@app_ns_wdog_ctrl : 0x1a300ffc
Address@app_secure_wdog_ctrl : 0x1a320ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: app_ns_wdog_refresh, app_secure_wdog_refresh

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W wdg_refresh_wrr
1-3f2 4-fc8 -  reserved
3f3 fcc R wdg_refresh_w_iidr
3f4 fd0 R wdg_refresh_id0
3f5 fd4 R wdg_refresh_id1
3f6 fd8 R wdg_refresh_id2
3f7 fdc R wdg_refresh_id3
3f8 fe0 R wdg_refresh_id4
3f9 fe4 R wdg_refresh_id5
3fa fe8 R wdg_refresh_id6
3fb fec R wdg_refresh_id7
3fc ff0 R wdg_refresh_id8
3fd ff4 R wdg_refresh_id9
3fe ff8 R wdg_refresh_id10
3ff ffc R wdg_refresh_id11

wdg_refresh_wrr
Watchdog refresh register.
R/W
0x00000000
Address@app_ns_wdog_refresh : 0x1a310000
Address@app_secure_wdog_refresh : 0x1a330000
Bits Reset value Name Description
31 - 0 0x0
reg
A write to this location causes the watchdog to refresh and start a new watch period.
A read has no effect and returns 0.


wdg_refresh_w_iidr
Watchdog Interface Identification Register
R
Address@app_ns_wdog_refresh : 0x1a310fcc
Address@app_secure_wdog_refresh : 0x1a330fcc
Bits Name Description
31 - 20 productid
An implementation defined product identifier.
19 - 16 arch_version
Revision field for the generic watchdog architecture. The value of this field depends on the generic watchdog architecture version:
0x1 for generic watchdog v1
15 - 12 revision
An implementation defined revision number for the component.
11 - 0 implementer
Contains the jep106 code of the company that implemented the generic watchdog.


wdg_refresh_id0
Peripheral ID Register 4
R
Address@app_ns_wdog_refresh : 0x1a310fd0
Address@app_secure_wdog_refresh : 0x1a330fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4kb occupied by the block. This field is deprecated.
3 - 0 des_2
jep continuation


wdg_refresh_id1
Peripheral ID Register 5
R
Address@app_ns_wdog_refresh : 0x1a310fd4
Address@app_secure_wdog_refresh : 0x1a330fd4
Bits Name Description
31 - 0 wdg_refresh_id1


wdg_refresh_id2
Peripheral ID Register 6
R
Address@app_ns_wdog_refresh : 0x1a310fd8
Address@app_secure_wdog_refresh : 0x1a330fd8
Bits Name Description
31 - 0 wdg_refresh_id2


wdg_refresh_id3
Peripheral ID Register 7
R
Address@app_ns_wdog_refresh : 0x1a310fdc
Address@app_secure_wdog_refresh : 0x1a330fdc
Bits Name Description
31 - 0 wdg_refresh_id3


wdg_refresh_id4
Peripheral ID Register 0
R
Address@app_ns_wdog_refresh : 0x1a310fe0
Address@app_secure_wdog_refresh : 0x1a330fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part id


wdg_refresh_id5
Peripheral ID Register 1
R
Address@app_ns_wdog_refresh : 0x1a310fe4
Address@app_secure_wdog_refresh : 0x1a330fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of jep 106 identity
3 - 0 part_1
Bits [11:8] of part id


wdg_refresh_id6
Peripheral ID Register 2
R
Address@app_ns_wdog_refresh : 0x1a310fe8
Address@app_secure_wdog_refresh : 0x1a330fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of jedec jep106 identification scheme
2 - 0 des_1
Bits [6:4] of jep 106 identity


wdg_refresh_id7
Peripheral ID Register 3
R
Address@app_ns_wdog_refresh : 0x1a310fec
Address@app_secure_wdog_refresh : 0x1a330fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


wdg_refresh_id8
Component ID Register 0
R
Address@app_ns_wdog_refresh : 0x1a310ff0
Address@app_secure_wdog_refresh : 0x1a330ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


wdg_refresh_id9
Component ID Register 1
R
Address@app_ns_wdog_refresh : 0x1a310ff4
Address@app_secure_wdog_refresh : 0x1a330ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


wdg_refresh_id10
Component ID Register 2
R
Address@app_ns_wdog_refresh : 0x1a310ff8
Address@app_secure_wdog_refresh : 0x1a330ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


wdg_refresh_id11
Component ID Register 3
R
Address@app_ns_wdog_refresh : 0x1a310ffc
Address@app_secure_wdog_refresh : 0x1a330ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: interrupt_router

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W interrupt_router_int_rtr_ctrl
1-3 4-c -  reserved
4 10 R/W interrupt_router_ld_ctrl
5-3f 14-fc -  reserved
40 100 R interrupt_router_shd_int_info
41 104 R/W interrupt_router_shd_int_cfg
42 108 R/W interrupt_router_shd_int_lctrl
43 10c R/W interrupt_router_shd_int_sel
44-3a3 110-e8c -  reserved
3a4 e90 R/W interrupt_router_int_rtr_tmp_st
3a5-3e7 e94-f9c -  reserved
3e8 fa0 R/W interrupt_router_int_rtr_cap
3e9-3eb fa4-fac -  reserved
3ec fb0 R/W interrupt_router_int_rtr_cfg
3ed-3f3 fb4-fcc -  reserved
3f4 fd0 R interrupt_router_pid4
3f5 fd4 R interrupt_router_pid5
3f6 fd8 R interrupt_router_pid6
3f7 fdc R interrupt_router_pid7
3f8 fe0 R interrupt_router_pid0
3f9 fe4 R interrupt_router_pid1
3fa fe8 R interrupt_router_pid2
3fb fec R interrupt_router_pid3
3fc ff0 R interrupt_router_cid0
3fd ff4 R interrupt_router_cid1
3fe ff8 R interrupt_router_cid2
3ff ffc R interrupt_router_cid3

interrupt_router_int_rtr_ctrl
Interrupt Router Control Register
R/W
0x00000000
Address : 0x1a500000
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
err
Configures the response for configuration accesses which generate a configuration access error:
0: No error
1: Error


interrupt_router_ld_ctrl
Lockdown Control Register
R/W
0x00000000
Address : 0x1a500010
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ldi_st
Lockdown interface status.
Indicates the current value of the lockdown interface:
0: Lockdown interface is de-asserted
1: Lockdown interface is asserted
1 - 0 "00"
lock
Indicates the lock state of the interrupt router:
0b00: Open lockdown state.
0b01: Reserved and treated as 0b00
0b10: Partial lockdown state
0b11: Full lockdown state


interrupt_router_shd_int_info
Shared Interrupt Information Register
R
Address : 0x1a500100
Bits Name Description
31 - 16 -
 reserved
15 - 0 ici_dst
Interrupt controller destination.
Each bit indicates whether the interrupt selected by the shd_int_sel.int_sel field, can be routed to ici interface associated with the bit, starting with bit 0 for ici0 to bit 3 for ici3:
0: Shared interrupt cannot be routed to the ici{x}
1: Shared interrupt can be routed to the ici{x}
The value of this field is defined by the si{x}_ici_dst configuration option.


interrupt_router_shd_int_cfg
Shared Interrupt Configuration Register
R/W
0x00000000
Address : 0x1a500104
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
ici_en
Interrupt controller enable.
Each bit selects whether the interrupt selected by the shd_int_sel.int_sel field, is routed to the ici interface associated with the bit, starting with bit 0 for ici0 to bit 3 for ici3:
0: Shared interrupt not routed to the ici{x}
1: Shared interrupt routed to the ici{x}
Bits, where the respective bit in the shd)_int_info.ici_dst field is 0b0 are reserved and treated as raz/wi.
The default value of this field is defined by the si{x}_def_ici configuration option.


interrupt_router_shd_int_lctrl
Shared Interrupt Lock Control Register
R/W
0x00000000
Address : 0x1a500108
Bits Reset value Name Description
31 "0"
lock
Control the lock status of the interrupt selected by the shd_int_sel.int_sel field:
0b0: Shared interrupt is not locked
0b1: Shared interrupt is locked
This field becomes read-only when this field is set to 0b1 and the ld_ctrl.lock field is set to 0b10 or 0b11.
30 - 0 0
-
 reserved


interrupt_router_shd_int_sel
Shared Interrupt Select Register
R/W
0x00000000
Address : 0x1a50010c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
int_sel
Selects which interrupt the shd_int_info, shd_int_cfg and shd_int_lctrl registers refer to.
When int_sel is greater than num_shd_int, the fields in shd_int_info, shd_int_cfg and shd_int_lctrl are reserved and treated as raz/wi.


interrupt_router_int_rtr_tmp_st
Interrupt Router Tamper Status Register
R/W
0x00000000
Address : 0x1a500e90
Bits Reset value Name Description
31 "0"
tmp_st_vld
Indicates whether the int_rtr_tmp_st register contains valid data or not:
- 0: int_rtr_tmp_st does not contain valid data
- 1: int_rtr_tmp_st contains valid data
This field is written 1 to clear, writing a value of 0 has no effect.
30 "0"
tmp_st_overflw
Indicates whether a tamper transaction occurred, while the
int_rtr_tmp_st.tmp_st_vld was 1:
- 0: No tamper transaction overflow occurred
- 1: Tamper transaction overflow occurred
This field is written 1 to clear, writing a value of 0 has no effect.
29 - 13 0
-
 reserved
12 - 11 "00"
tmp_trans_addr
Address of the register accessed by the tamper transaction.
When tmp_st_vld is 0 this field is not valid.
10 - 0 0
-
 reserved


interrupt_router_int_rtr_cap
Interrupt Router Capability Register
R/W
0x00000000
Address : 0x1a500fa0
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0000"
lde_lvl
Level of the lockdown extension implemented by the interrupt router.
Read as 0x2 - lde.2 is implemented.


interrupt_router_int_rtr_cfg
Interrupt Router Configuration Register
R/W
0x00000000
Address : 0x1a500fb0
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
num_ici
Number of interrupt controllers interrupt interface (ici)s supported by the interrupt router: 0x3: 4 icis supported
15 - 0 0x0
num_shd_int
Number of shared interrupts supported by the interrupt router:
0x0: 1 shared interrupt
0x1: 2 shared interrupts
...
0x18b: 395 shared interrupts


interrupt_router_pid4
Peripheral ID Register 4
R
Address : 0x1a500fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4kb occupied by the block. This field is deprecated.
3 - 0 des_2
jep continuation


interrupt_router_pid5
Peripheral ID Register 5
R
Address : 0x1a500fd4
Bits Name Description
31 - 0 interrupt_router_pid5


interrupt_router_pid6
Peripheral ID Register 6
R
Address : 0x1a500fd8
Bits Name Description
31 - 0 interrupt_router_pid6


interrupt_router_pid7
Peripheral ID Register 7
R
Address : 0x1a500fdc
Bits Name Description
31 - 0 interrupt_router_pid7


interrupt_router_pid0
Peripheral ID Register 0
R
Address : 0x1a500fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part id


interrupt_router_pid1
Peripheral ID Register 1
R
Address : 0x1a500fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of jep 106 identity
3 - 0 part_1
Bits [11:8] of part id


interrupt_router_pid2
Peripheral ID Register 2
R
Address : 0x1a500fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of jedec jep106 identification scheme
2 - 0 des_1
Bits [6:4] of jep 106 identity


interrupt_router_pid3
Peripheral ID Register 3
R
Address : 0x1a500fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


interrupt_router_cid0
Component ID Register 0
R
Address : 0x1a500ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


interrupt_router_cid1
Component ID Register 1
R
Address : 0x1a500ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 1


interrupt_router_cid2
Component ID Register 2
R
Address : 0x1a500ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


interrupt_router_cid3
Component ID Register 3
R
Address : 0x1a500ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: cor_uart0, cor_uart1, secenc_uart

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W uart_pl011_uartdr
1 4 R/W uart_pl011_uartrsr
2-5 8-14 -  reserved
6 18 R uart_pl011_uartfr
7 1c -  reserved
8 20 R/W uart_pl011_uartilpr
9 24 R/W uart_pl011_uartibrd
a 28 R/W uart_pl011_uartfbrd
b 2c R/W uart_pl011_uartlcr_h
c 30 R/W uart_pl011_uartcr
d 34 R/W uart_pl011_uartifls
e 38 R/W uart_pl011_uartimsc
f 3c R uart_pl011_uartris
10 40 R uart_pl011_uartmis
11 44 W uart_pl011_uarticr
12 48 R/W uart_pl011_uartdmacr
13-3f7 4c-fdc -  reserved
3f8 fe0 R uart_pl011_uartperiphid0
3f9 fe4 R uart_pl011_uartperiphid1
3fa fe8 R uart_pl011_uartperiphid2
3fb fec R uart_pl011_uartperiphid3
3fc ff0 R uart_pl011_uartpcellid0
3fd ff4 R uart_pl011_uartpcellid1
3fe ff8 R uart_pl011_uartpcellid2
3ff ffc R uart_pl011_uartpcellid3

uart_pl011_uartdr
Data Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510000
Address@cor_uart1 : 0x1a520000
Address@secenc_uart : 0x50090000
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 "0"
oe
overrun error. this bit is set to 1 if data is received and the receive fifo is already full.
this is cleared to 0 once there is an empty space in the fifo and a new character can be written to it.
10 "0"
be
break error. this bit is set to 1 if a break condition was detected, indicating that the received data input
was held low for longer than a full-word transmission time (defined as start, data, parity and stop bits).
in fifo mode, this error is associated with the character at the top of the fifo.
when a break occurs, only one 0 character is loaded into the fifo.
the next character is only enabled after the receive data input goes to a 1 (marking state), and the next valid start bit is received.
9 "0"
pe
parity error. when set to 1, it indicates that the parity of the received data character does not match the parity that the eps and sps bits in the line control register, uartlcr_h.
in fifo mode, this error is associated with the character at the top of the fifo.
8 "0"
fe
framing error. when set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
in fifo mode, this error is associated with the character at the top of the fifo.
7 - 0 "00000000"
data
receive (read) data character.
transmit (write) data character.


uart_pl011_uartrsr
Receive Status Register/Error Clear Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510004
Address@cor_uart1 : 0x1a520004
Address@secenc_uart : 0x50090004
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
oe
overrun error. this bit is set to 1 if data is received and the fifo is already full.
this bit is cleared to 0 by a write to uartecr.
the fifo contents remain valid because no more data is written when the fifo is full, only the contents of the shift register are overwritten. the cpu must now read the data, to empty the fifo.
2 "0"
be
break error. this bit is set to 1 if a break condition was detected, indicating that the received data input was held low for longer than a full-word transmission time (defined as start, data, parity, and stop bits).
this bit is cleared to 0 after a write to uartecr.
in fifo mode, this error is associated with the character at the top of the fifo.
when a break occurs, only one 0 character is loaded into the fifo.
the next character is only enabled after the receive data input goes to a 1 (marking state) and the next valid start bit is received.
1 "0"
pe
parity error. when set to 1, it indicates that the parity of the received data character does not match the parity that the eps and sps bits in the line control register, uartlcr_h.
this bit is cleared to 0 by a write to uartecr.
in fifo mode, this error is associated with the character at the top of the fifo.
0 "0"
fe
framing error. when set to 1, it indicates that the received character did not have a valid stop bit (a valid stop bit is 1).
this bit is cleared to 0 by a write to uartecr.
in fifo mode, this error is associated with the character at the top of the fifo.


uart_pl011_uartfr
Flag Register
R
Address@cor_uart0 : 0x1a510018
Address@cor_uart1 : 0x1a520018
Address@secenc_uart : 0x50090018
Bits Name Description
31 - 9 -
 reserved
8 ri
ring indicator. this bit is the complement of the uart ring indicator, nuartri, modem status input.
that is, the bit is 1 when nuartri is low.
7 txfe
transmit fifo empty. the meaning of this bit depends on the state of the fen bit in the line control register, uartlcr_h.
if the fifo is disabled, this bit is set when the transmit holding register is empty.
if the fifo is enabled, the txfe bit is set when the transmit fifo is empty.
this bit does not indicate if there is data in the transmit shift register.
6 rxff
receive fifo full. the meaning of this bit depends on the state of the fen bit in the uartlcr_h register.
if the fifo is disabled, this bit is set when the receive holding register is full.
if the fifo is enabled, the rxff bit is set when the receive fifo is full.
5 txff
transmit fifo full. the meaning of this bit depends on the state of the fen bit in the uartlcr_h register.
if the fifo is disabled, this bit is set when the transmit holding register is full.
if the fifo is enabled, the txff bit is set when the transmit fifo is full.
4 rxfe
receive fifo empty. the meaning of this bit depends on the state of the fen bit in the uartlcr_h register.
if the fifo is disabled, this bit is set when the receive holding register is empty.
if the fifo is enabled, the rxfe bit is set when the receive fifo is empty.
3 busy
uart busy. if this bit is set to 1, the uart is busy transmitting data.
this bit remains set until the complete byte, including all the stop bits, has been sent from the shift register.
this bit is set as soon as the transmit fifo becomes non-empty, regardless of whether the uart is enabled or not.
2 dcd
data carrier detect. this bit is the complement of the uart data carrier detect, nuartdcd, modem status input.
that is, the bit is 1 when nuartdcd is low.
1 dsr
data set ready. this bit is the complement of the uart data set ready, nuartdsr, modem status input.
that is, the bit is 1 when nuartdsr is low.
0 cts
clear to send. this bit is the complement of the uart clear to send, nuartcts, modem status input.
that is, the bit is 1 when nuartcts is low.


uart_pl011_uartilpr
IrDA Low-Power Counter Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510020
Address@cor_uart1 : 0x1a520020
Address@secenc_uart : 0x50090020
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
ilpdvsr
8-bit low-power divisor value.
these bits are cleared to 0 at reset.
note: zero is an illegal value.
programming a zero value results in no irlpbaud16 pulses being generated.


uart_pl011_uartibrd
Integer Baud Rate Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510024
Address@cor_uart1 : 0x1a520024
Address@secenc_uart : 0x50090024
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
baud_divint
the integer baud rate divisor. these bits are cleared to 0 on reset.


uart_pl011_uartfbrd
Fractional Baud Rate Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510028
Address@cor_uart1 : 0x1a520028
Address@secenc_uart : 0x50090028
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "000000"
baud_divfrac
the fractional baud rate divisor. these bits are cleared to 0 on reset.


uart_pl011_uartlcr_h
Line Control Register
R/W
0x00000000
Address@cor_uart0 : 0x1a51002c
Address@cor_uart1 : 0x1a52002c
Address@secenc_uart : 0x5009002c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
sps
stick parity select.
0 = stick parity is disabled
1 = either:
- if the eps bit is 0 then the parity bit is transmitted and checked as a 1.
- if the eps bit is 1 then the parity bit is transmitted and checked as a 0.
this bit has no effect when the pen bit disables parity checking and generation.
6 - 5 "00"
wlen
word length. these bits indicate the number of data bits transmitted or received in a frame as follows:
b11 = 8 bits
b10 = 7 bits
b01 = 6 bits
b00 = 5 bits.
4 "0"
fen
enable fifos:
0 = fifos are disabled (character mode) that is, the fifos become 1-byte-deep holding registers.
1 = transmit and receive fifo buffers are enabled (fifo mode).
3 "0"
stp2
two stop bits select. if this bit is set to 1, two stop bits are transmitted at the end of the frame.
the receive logic does not check for two stop bits being received.
2 "0"
eps
even parity select. controls the type of parity the uart uses during transmission and reception:
0 = odd parity. the uart generates or checks for an odd number of 1s in the data and parity bits.
1 = even parity. the uart generates or checks for an even number of 1s in the data and parity bits.
this bit has no effect when the pen bit disables parity checking and generation.
1 "0"
pen
parity enable:
0 = parity is disabled and no parity bit added to the data frame.
1 = parity checking and generation is enabled.
0 "0"
brk
send break. if this bit is set to 1, a low-level is continually output on the uarttxd output, after completing transmission of the current character.
for the proper execution of the break command, the software must set this bit for at least two complete frames.
for normal use, this bit must be cleared to 0.


uart_pl011_uartcr
Control Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510030
Address@cor_uart1 : 0x1a520030
Address@secenc_uart : 0x50090030
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
ctsen
cts hardware flow control enable. if this bit is set to 1, cts hardware flow control is enabled.
data is only transmitted when the nuartcts signal is asserted.
14 "0"
rtsen
rts hardware flow control enable. if this bit is set to 1, rts hardware flow control is enabled.
data is only requested when there is space in the receive fifo for it to be received.
13 "0"
out2
this bit is the complement of the uart out2 (nuartout2) modem status output.
that is, when the bit is programmed to a 1, the output is 0.
for dte this can be used as ring indicator (ri).
12 "0"
out1
this bit is the complement of the uart out1 (nuartout1) modem status output.
that is, when the bit is programmed to a 1 the output is 0. for dte this can be used as data carrier detect (dcd).
11 "0"
rts
request to send. this bit is the complement of the uart request to send, nuartrts, modem status output.
that is, when the bit is programmed to a 1 then nuartrts is low.
10 "0"
dtr
data transmit ready. this bit is the complement of the uart data transmit ready, nuartdtr, modem status output.
that is, when the bit is programmed to a 1 then nuartdtr is low.
9 "0"
rxe
receive enable. if this bit is set to 1, the receive section of the uart is enabled.
data reception occurs for either uart signals or sir signals depending on the setting of the siren bit.
when the uart is disabled in the middle of reception, it completes the current character before stopping.
8 "0"
txe
transmit enable. if this bit is set to 1, the transmit section of the uart is enabled.
data transmission occurs for either uart signals, or sir signals depending on the setting of the siren bit.
when the uart is disabled in the middle of transmission, it completes the current character before stopping.
7 "0"
lbe
loopback enable. if this bit is set to 1 and the siren bit is set to 1 and the sirtest bit in the test control register, uarttcr is set to 1, then the nsirout path is inverted, and fed through to the sirin path.
the sirtest bit in the test register must be set to 1 to override the normal half-duplex sir operation.
this must be the requirement for accessing the test registers during normal operation, and sirtest must be cleared to 0 when loopback testing is finished.
this feature reduces the amount of external coupling required during system test.
if this bit is set to 1, and the sirtest bit is set to 0, the uarttxd path is fed through to the uartrxd path.
in either sir mode or uart mode, when this bit is set, the modem outputs are also fed through to the modem inputs.
this bit is cleared to 0 on reset, to disable loopback.
6 - 3 0
-
 reserved
2 "0"
sirlp
sir low-power irda mode. this bit selects the irda encoding mode.
if this bit is cleared to 0, low-level bits are transmitted as an active high pulse with a width of 3/16th of the bit period.
if this bit is set to 1, low-level bits are transmitted with a pulse width that is 3 times the period of the irlpbaud16 input signal, regardless of the selected bit rate.
setting this bit uses less power, but might reduce transmission distances.
1 "0"
siren
sir enable:
0 = irda sir endec is disabled. nsirout remains low (no light pulse generated), and signal transitions on sirin have no effect.
1 = irda sir endec is enabled. data is transmitted and received on nsirout and sirin.
uarttxd remains high, in the marking state. signal transitions on uartrxd or modem status inputs have no effect.
this bit has no effect if the uarten bit disables the uart.
0 "0"
uarten
uart enable:
0 = uart is disabled. if the uart is disabled in the middle of transmission or reception, it completes the current character before stopping.
1 = the uart is enabled. data transmission and reception occurs for either uart signals or sir signals depending on the setting of the siren bit.


uart_pl011_uartifls
Interrupt FIFO Level Select Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510034
Address@cor_uart1 : 0x1a520034
Address@secenc_uart : 0x50090034
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 3 "000"
rxiflsel
receive interrupt fifo level select. the trigger points for the receive interrupt are as follows:
b000 = receive fifo becomes >= 1/8 full
b001 = receive fifo becomes >= 1/4 full
b010 = receive fifo becomes >= 1/2 full
b011 = receive fifo becomes >= 3/4 full
b100 = receive fifo becomes >= 7/8 full
b101-b111 = reserved.
2 - 0 "000"
txiflsel
transmit interrupt fifo level select. the trigger points for the transmit interrupt are as follows:
b000 = transmit fifo becomes >= 1/8 full
b001 = transmit fifo becomes >= 1/4 full
b010 = Transmit FIFO becomes >= 1/2 full
b011 = Transmit FIFO becomes >= 3/4 full
b100 = Transmit FIFO becomes >= 7/8 full
b101-b111 = reserved.


uart_pl011_uartimsc
Interrupt Mask Set/Clear Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510038
Address@cor_uart1 : 0x1a520038
Address@secenc_uart : 0x50090038
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
oeim
Overrun error interrupt mask. A read returns the current mask for the UARTOEINTR interrupt.
On a write of 1, the mask of the UARTOEINTR interrupt is set. A write of 0 clears the mask.
9 "0"
beim
Break error interrupt mask. A read returns the current mask for the UARTBEINTR interrupt.
On a write of 1, the mask of the UARTBEINTR interrupt is set. A write of 0 clears the mask.
8 "0"
peim
Parity error interrupt mask. A read returns the current mask for the UARTPEINTR interrupt.
On a write of 1, the mask of the UARTPEINTR interrupt is set. A write of 0 clears the mask.
7 "0"
feim
Framing error interrupt mask. A read returns the current mask for the UARTFEINTR interrupt.
On a write of 1, the mask of the UARTFEINTR interrupt is set. A write of 0 clears the mask.
6 "0"
rtim
Receive timeout interrupt mask. A read returns the current mask for the UARTRTINTR interrupt.
On a write of 1, the mask of the UARTRTINTR interrupt is set. A write of 0 clears the mask.
5 "0"
txim
Transmit interrupt mask. A read returns the current mask for the UARTTXINTR interrupt.
On a write of 1, the mask of the UARTTXINTR interrupt is set. A write of 0 clears the mask.
4 "0"
rxim
Receive interrupt mask. A read returns the current mask for the UARTRXINTR interrupt.
On a write of 1, the mask of the UARTRXINTR interrupt is set. A write of 0 clears the mask.
3 "0"
dsrmim
nUARTDSR modem interrupt mask. A read returns the current mask for the UARTDSRINTR interrupt.
On a write of 1, the mask of the UARTDSRINTR interrupt is set. A write of 0 clears the mask.
2 "0"
dcdmim
nUARTDCD modem interrupt mask. A read returns the current mask for the UARTDCDINTR interrupt.
On a write of 1, the mask of the UARTDCDINTR interrupt is set. A write of 0 clears the mask.
1 "0"
ctsmim
nUARTCTS modem interrupt mask. A read returns the current mask for the UARTCTSINTR interrupt.
On a write of 1, the mask of the UARTCTSINTR interrupt is set. A write of 0 clears the mask.
0 "0"
rimim
nUARTRI modem interrupt mask. A read returns the current mask for the UARTRIINTR interrupt.
On a write of 1, the mask of the UARTRIINTR interrupt is set. A write of 0 clears the mask.


uart_pl011_uartris
Raw Interrupt Status Register
R
Address@cor_uart0 : 0x1a51003c
Address@cor_uart1 : 0x1a52003c
Address@secenc_uart : 0x5009003c
Bits Name Description
31 - 11 -
 reserved
10 oeris
Overrun error interrupt status. Returns the raw interrupt state of the UARTOEINTR interrupt.
9 beris
Break error interrupt status. Returns the raw interrupt state of the UARTBEINTR interrupt.
8 peris
Parity error interrupt status. Returns the raw interrupt state of the UARTPEINTR interrupt.
7 feris
Framing error interrupt status. Returns the raw interrupt state of the UARTFEINTR interrupt.
6 rtris
Receive timeout interrupt status. Returns the raw interrupt state of the UARTRTINTR interrupt.
5 txris
Transmit interrupt status. Returns the raw interrupt state of the UARTTXINTR interrupt.
4 rxris
Receive interrupt status. Returns the raw interrupt state of the UARTRXINTR interrupt.
3 dsrrmis
nUARTDSR modem interrupt status. Returns the raw interrupt state of the UARTDSRINTR interrupt.
2 dcdrmis
nUARTDCD modem interrupt status. Returns the raw interrupt state of the UARTDCDINTR interrupt.
1 ctsrmis
nUARTCTS modem interrupt status. Returns the raw interrupt state of the UARTCTSINTR interrupt.
0 rirmis
nUARTRI modem interrupt status. Returns the raw interrupt state of the UARTRIINTR interrupt.


uart_pl011_uartmis
Masked Interrupt Status Register
R
Address@cor_uart0 : 0x1a510040
Address@cor_uart1 : 0x1a520040
Address@secenc_uart : 0x50090040
Bits Name Description
31 - 11 -
 reserved
10 oemis
Overrun error masked interrupt status. Returns the masked interrupt state of the UARTOEINTR interrupt.
9 bemis
Break error masked interrupt status. Returns the masked interrupt state of the UARTBEINTR interrupt.
8 pemis
Parity error masked interrupt status. Returns the masked interrupt state of the UARTPEINTR interrupt.
7 femis
Framing error masked interrupt status. Returns the masked interrupt state of the UARTFEINTR interrupt.
6 rtmis
Receive timeout masked interrupt status. Returns the masked interrupt state of the UARTRTINTR interrupt.
5 txmis
Transmit masked interrupt status. Returns the masked interrupt state of the UARTTXINTR interrupt.
4 rxmis
Receive masked interrupt status. Returns the masked interrupt state of the UARTRXINTR interrupt.
3 dsrmmis
nUARTDSR modem masked interrupt status. Returns the masked interrupt state of the UARTDSRINTR interrupt.
2 dcdmmis
nUARTDCD modem masked interrupt status. Returns the masked interrupt state of the UARTDCDINTR interrupt.
1 ctsmmis
nUARTCTS modem masked interrupt status. Returns the masked interrupt state of the UARTCTSINTR interrupt.
0 rimmis
nUARTRI modem masked interrupt status. Returns the masked interrupt state of the UARTRIINTR interrupt.


uart_pl011_uarticr
Interrupt Clear Register
W
0x00000000
Address@cor_uart0 : 0x1a510044
Address@cor_uart1 : 0x1a520044
Address@secenc_uart : 0x50090044
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
oeic
Overrun error interrupt clear. Clears the UARTOEINTR interrupt.
9 "0"
beic
Break error interrupt clear. Clears the UARTBEINTR interrupt.
8 "0"
peic
Parity error interrupt clear. Clears the UARTPEINTR interrupt.
7 "0"
feic
Framing error interrupt clear. Clears the UARTFEINTR interrupt.
6 "0"
rtic
Receive timeout interrupt clear. Clears the UARTRTINTR interrupt.
5 "0"
txic
Transmit interrupt clear. Clears the UARTTXINTR interrupt.
4 "0"
rxic
Receive interrupt clear. Clears the UARTRXINTR interrupt.
3 "0"
dsrmic
nUARTDSR modem interrupt clear. Clears the UARTDSRINTR interrupt.
2 "0"
dcdmic
nUARTDCD modem interrupt clear. Clears the UARTDCDINTR interrupt.
1 "0"
ctsmic
nUARTCTS modem interrupt clear. Clears the UARTCTSINTR interrupt.
0 "0"
rimic
nUARTRI modem interrupt clear. Clears the UARTRIINTR interrupt.


uart_pl011_uartdmacr
DMA Control Register
R/W
0x00000000
Address@cor_uart0 : 0x1a510048
Address@cor_uart1 : 0x1a520048
Address@secenc_uart : 0x50090048
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
dmaonerr
DMA on error. If this bit is set to 1, the DMA receive request outputs, UARTRXDMASREQ or UARTRXDMABREQ, are disabled when the UART error interrupt is asserted.
1 "0"
txdmae
Transmit DMA enable. If this bit is set to 1, DMA for the transmit FIFO is enabled.
0 "0"
rxdmae
Receive DMA enable. If this bit is set to 1, DMA for the receive FIFO is enabled.


uart_pl011_uartperiphid0
Peripheral Identification Register 0
R
Address@cor_uart0 : 0x1a510fe0
Address@cor_uart1 : 0x1a520fe0
Address@secenc_uart : 0x50090fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 partnumber0
These bits read back as 0x11


uart_pl011_uartperiphid1
Peripheral Identification Register 1
R
Address@cor_uart0 : 0x1a510fe4
Address@cor_uart1 : 0x1a520fe4
Address@secenc_uart : 0x50090fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 designer0
These bits read back as 0x1
3 - 0 partnumber1
These bits read back as 0x0


uart_pl011_uartperiphid2
Peripheral Identification Register 2
R
Address@cor_uart0 : 0x1a510fe8
Address@cor_uart1 : 0x1a520fe8
Address@secenc_uart : 0x50090fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
This field depends on the revision of the UART
3 - 0 designer1
These bits read back as 0x4


uart_pl011_uartperiphid3
Peripheral Identification Register 3
R
Address@cor_uart0 : 0x1a510fec
Address@cor_uart1 : 0x1a520fec
Address@secenc_uart : 0x50090fec
Bits Name Description
31 - 8 -
 reserved
7 - 0 configuration
These bits read back as 0x00


uart_pl011_uartpcellid0
PrimeCell Identification Register 0
R
Address@cor_uart0 : 0x1a510ff0
Address@cor_uart1 : 0x1a520ff0
Address@secenc_uart : 0x50090ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 uartpcellid0
These bits read back as 0x0D


uart_pl011_uartpcellid1
PrimeCell Identification Register 1
R
Address@cor_uart0 : 0x1a510ff4
Address@cor_uart1 : 0x1a520ff4
Address@secenc_uart : 0x50090ff4
Bits Name Description
31 - 8 -
 reserved
7 - 0 uartpcellid1
These bits read back as 0xF0


uart_pl011_uartpcellid2
PrimeCell Identification Register 2
R
Address@cor_uart0 : 0x1a510ff8
Address@cor_uart1 : 0x1a520ff8
Address@secenc_uart : 0x50090ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 uartpcellid2
These bits read back as 0x05


uart_pl011_uartpcellid3
PrimeCell Identification Register 3
R
Address@cor_uart0 : 0x1a510ffc
Address@cor_uart1 : 0x1a520ffc
Address@secenc_uart : 0x50090ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 uartpcellid3
These bits read back as 0xB1



Base Address Area: host_sys_fw_ctrl, secenc_fw_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W fw_ctrl_fw_ctrl
1 4 R fw_ctrl_fw_st
2 8 -  reserved
3 c R/W fw_ctrl_fw_sr_ctrl
4 10 R fw_ctrl_ld_ctrl
5-3f 14-fc -  reserved
40 100 R/W fw_ctrl_pe_ctrl
41 104 R fw_ctrl_pe_st
42 108 R/W fw_ctrl_pe_bps
43 10c R/W fw_ctrl_rwe_ctrl
44 110 R/W fw_ctrl_rgn_ctrl0
45 114 R/W fw_ctrl_rgn_ctrl1
46 118 R/W fw_ctrl_rgn_lctrl
47 11c R fw_ctrl_rgn_st
48 120 R/W fw_ctrl_rgn_cfg0
49 124 R/W fw_ctrl_rgn_cfg1
4a 128 R/W fw_ctrl_rgn_size
4b 12c -  reserved
4c 130 R/W fw_ctrl_rgn_tcfg0
4d 134 R/W fw_ctrl_rgn_tcfg1
4e 138 R/W fw_ctrl_rgn_tcfg2
4f 13c -  reserved
50 140 R/W fw_ctrl_rgn_mid0
51 144 R/W fw_ctrl_rgn_mpl0
52 148 R/W fw_ctrl_rgn_mid1
53 14c R/W fw_ctrl_rgn_mpl1
54 150 R/W fw_ctrl_rgn_mid2
55 154 R/W fw_ctrl_rgn_mpl2
56 158 R/W fw_ctrl_rgn_mid3
57 15c R/W fw_ctrl_rgn_mpl3
58-5f 160-17c -  reserved
60 180 R fw_ctrl_fe_tal
61 184 R fw_ctrl_fe_tau
62 188 R fw_ctrl_fe_tp
63 18c R fw_ctrl_fe_mid
64 190 R/W fw_ctrl_fe_ctrl
65-7f 194-1fc -  reserved
80 200 R/W fw_ctrl_me_ctrl
81 204 R fw_ctrl_me_st
82-97 208-25c -  reserved
98 260 R fw_ctrl_edr_tal
99 264 R fw_ctrl_edr_tau
9a 268 R fw_ctrl_edr_tp
9b 26c R fw_ctrl_edr_mid
9c 270 R/W fw_ctrl_edr_ctrl
9d-33f 274-cfc -  reserved
340 d00 R/W fw_ctrl_fc0_int_st
341 d04 R/W fw_ctrl_fc1_int_st
342 d08 R/W fw_ctrl_fc2_int_st
343 d0c R/W fw_ctrl_fc3_int_st
344 d10 R/W fw_ctrl_fc4_int_st
345 d14 R/W fw_ctrl_fc5_int_st
346 d18 R/W fw_ctrl_fc6_int_st
347 d1c R/W fw_ctrl_fc7_int_st
348 d20 R/W fw_ctrl_fc8_int_st
349 d24 R/W fw_ctrl_fc9_int_st
34a d28 R/W fw_ctrl_fc10_int_st
34b d2c R/W fw_ctrl_fc11_int_st
34c d30 R/W fw_ctrl_fc12_int_st
34d d34 R/W fw_ctrl_fc13_int_st
34e d38 R/W fw_ctrl_fc14_int_st
34f d3c R/W fw_ctrl_fc15_int_st
350 d40 R/W fw_ctrl_fc16_int_st
351 d44 R/W fw_ctrl_fc17_int_st
352 d48 R/W fw_ctrl_fc18_int_st
353 d4c R/W fw_ctrl_fc19_int_st
354 d50 R/W fw_ctrl_fc20_int_st
355 d54 R/W fw_ctrl_fc21_int_st
356 d58 R/W fw_ctrl_fc22_int_st
357 d5c R/W fw_ctrl_fc23_int_st
358 d60 R/W fw_ctrl_fc24_int_st
359 d64 R/W fw_ctrl_fc25_int_st
35a d68 R/W fw_ctrl_fc26_int_st
35b d6c R/W fw_ctrl_fc27_int_st
35c d70 R/W fw_ctrl_fc28_int_st
35d d74 R/W fw_ctrl_fc29_int_st
35e d78 R/W fw_ctrl_fc30_int_st
35f d7c R/W fw_ctrl_fc31_int_st
360-363 d80-d8c -  reserved
364 d90 R fw_ctrl_fw_int_st
365-37f d94-dfc -  reserved
380 e00 R/W fw_ctrl_fc0_int_msk
381 e04 R/W fw_ctrl_fc1_int_msk
382 e08 R/W fw_ctrl_fc2_int_msk
383 e0c R/W fw_ctrl_fc3_int_msk
384 e10 R/W fw_ctrl_fc4_int_msk
385 e14 R/W fw_ctrl_fc5_int_msk
386 e18 R/W fw_ctrl_fc6_int_msk
387 e1c R/W fw_ctrl_fc7_int_msk
388 e20 R/W fw_ctrl_fc8_int_msk
389 e24 R/W fw_ctrl_fc9_int_msk
38a e28 R/W fw_ctrl_fc10_int_msk
38b e2c R/W fw_ctrl_fc11_int_msk
38c e30 R/W fw_ctrl_fc12_int_msk
38d e34 R/W fw_ctrl_fc13_int_msk
38e e38 R/W fw_ctrl_fc14_int_msk
38f e3c R/W fw_ctrl_fc15_int_msk
390 e40 R/W fw_ctrl_fc16_int_msk
391 e44 R/W fw_ctrl_fc17_int_msk
392 e48 R/W fw_ctrl_fc18_int_msk
393 e4c R/W fw_ctrl_fc19_int_msk
394 e50 R/W fw_ctrl_fc20_int_msk
395 e54 R/W fw_ctrl_fc21_int_msk
396 e58 R/W fw_ctrl_fc22_int_msk
397 e5c R/W fw_ctrl_fc23_int_msk
398 e60 R/W fw_ctrl_fc24_int_msk
399 e64 R/W fw_ctrl_fc25_int_msk
39a e68 R/W fw_ctrl_fc26_int_msk
39b e6c R/W fw_ctrl_fc27_int_msk
39c e70 R/W fw_ctrl_fc28_int_msk
39d e74 R/W fw_ctrl_fc29_int_msk
39e e78 R/W fw_ctrl_fc30_int_msk
39f e7c R/W fw_ctrl_fc31_int_msk
3a0-3a3 e80-e8c -  reserved
3a4 e90 R fw_ctrl_fw_tmp_ta
3a5 e94 -  reserved
3a6 e98 R fw_ctrl_fw_tmp_tp
3a7 e9c R fw_ctrl_fw_tmp_mid
3a8 ea0 R/W fw_ctrl_fw_tmp_ctrl
3a9-3e7 ea4-f9c -  reserved
3e8 fa0 R fw_ctrl_fc_cap0
3e9 fa4 R fw_ctrl_fc_cap1
3ea fa8 R fw_ctrl_fc_cap2
3eb fac R fw_ctrl_fc_cap3
3ec fb0 R fw_ctrl_fc_cfg0
3ed fb4 R fw_ctrl_fc_cfg1
3ee fb8 R fw_ctrl_fc_cfg2
3ef fbc R fw_ctrl_fc_cfg3
3f0-3f1 fc0-fc4 -  reserved
3f2 fc8 R fw_ctrl_iidr
3f3 fcc R fw_ctrl_aidr
3f4 fd0 R fw_ctrl_pid4
3f5 fd4 R fw_ctrl_pid5
3f6 fd8 R fw_ctrl_pid6
3f7 fdc R fw_ctrl_pid7
3f8 fe0 R fw_ctrl_pid0
3f9 fe4 R fw_ctrl_pid1
3fa fe8 R fw_ctrl_pid2
3fb fec R fw_ctrl_pid3
3fc ff0 R fw_ctrl_cid0
3fd ff4 R fw_ctrl_cid1
3fe ff8 R fw_ctrl_cid2
3ff ffc R fw_ctrl_cid3

fw_ctrl_fw_ctrl
Firewall Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800000
Address@secenc_fw_ctrl : 0x50200000
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
raz
Configures the value returned for read accesses which generate a Configuration Access Error.
0b0: Read data is based on the StreamID
0b1: Read data is all 0s
0 "0"
err
Configures the response for transactions which generate a Configuration Access Error.
0b0: No error
0b1: Error


fw_ctrl_fw_st
Firewall Status Register
R
Address@host_sys_fw_ctrl : 0x1a800004
Address@secenc_fw_ctrl : 0x50200004
Bits Name Description
31 - 2 -
 reserved
1 raz
Indicates the value returned for read accesses which generate a Configuration Access Error.
0b0: Read data is based on the StreamID
0b1: Read data is all 0s
0 err
Indicates the response for transactions which generate a Configuration Access Error.
0b0: No error
0b1: Error


fw_ctrl_fw_sr_ctrl
Firewall Shadow Register Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a80000c
Address@secenc_fw_ctrl : 0x5020000c
Bits Reset value Name Description
31 "0"
sr_rdy
Indicates when the shadow registers are ready.
0b0: Shadow registers are not ready.
0b1: Shadow registers are ready.
30 - 1 0
-
 reserved
0 "0"
sr_pwr
Shadow register power request when Firewall Controller enters the Disconnected state:
0b0: No request for the shadow registers to retain their values the next time the Firewall Controller enters the Disconnected state.
0b1: Request for the shadow registers to retain their values the next time the Firewall Controller enters the Disconnected state.
This field is Reserved and treated as RAZ/WI when SRE.0 is implemented.


fw_ctrl_ld_ctrl
Lockdown Control Register
R
Address@host_sys_fw_ctrl : 0x1a800010
Address@secenc_fw_ctrl : 0x50200010
Bits Name Description
31 - 3 -
 reserved
2 ldi_st
Lockdown interface status.
Indicates the current value of the Lockdown interface:
0: Lockdown interface is de-asserted
1: Lockdown interface is asserted
1 - 0 lock
Indicates the lock state of the Interrupt Router:
0b00: Open lockdown state.
0b01: Reserved and treated as 0b00
0b10: Partial lockdown state
0b11: Full lockdown state


fw_ctrl_pe_ctrl
Protection Extension Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800100
Address@secenc_fw_ctrl : 0x50200100
Bits Reset value Name Description
31 "0"
en
Request the Firewall Components protection logic enables or disables.
0b0: Request the Firewall Components protection logic becomes disabled.
0b1: Request the Firewall Components protection logic becomes enabled.
The reset value of this field is 0b0 for all Firewall Components other than the Firewall
Controller which resets to 0b1.
30 - 6 0
-
 reserved
5 "0"
bypass_msk
Request Firewall Component behavior to Bypass interface.
0b0: Firewall Component uses the value of the Bypass interface to calculate whether it is bypassed or not.
0b1: Firewall Component ignores the value of the Bypass interface and treats the value as 0b0 to calculate whether it is bypassed or not.
4 "0"
fe_pwr
Request Fault Entry power behavior.
0b0: Fault Entry does not prevent entry into a Disconnected state.
0b1: Fault Entry does prevent entry into a Disconnected state.
3 - 2 "00"
flt_cfg
Requested Fault Configuration Configures the behavior of the Firewall Component when a transaction enters the Faulted state.
0b00: Reserved and treated as 10
0b01: Reserved and treated as 10
0b10: Terminate transaction, generate a fault entry and Access or Programming Error interrupt.
0b11: Terminate transaction, but no fault entry or Access or Programming Error interrupt are generated.
1 "0"
raz
Requested behavior for read data returned for read transactions terminated by the Firewall Component.
0b0: Read data is based on the StreamID
0b1: Read data all 0s
0 "0"
err
Requested behavior for responses for transactions terminated by the Firewall Component.
0b0: No error
0b1: Error


fw_ctrl_pe_st
Firewall Component Status Register
R
Address@host_sys_fw_ctrl : 0x1a800104
Address@secenc_fw_ctrl : 0x50200104
Bits Name Description
31 en
Status of the Firewall Components protection logic.
0b0: Firewall Components protection logic is disabled.
0b1: Firewall Components protection logic is enabled.
When SRE.1 is implemented and the Firewall Component has entered the Disconnected state this field matches the value in PE_CTRL.EN.
As if the request to change from enabled to disabled or disabled to enabled has completed.
The reset value matches the reset value of PE_CTRL.EN.
30 - 6 -
 reserved
5 bypass_msk
Firewall Component behavior to Bypass interface.
0b0: Firewall Component uses the value of the Bypass interface to calculate whether it is bypassed or not.
0b1: Firewall Component ignores the value of the Bypass interface and treats the value as 0b0 to calculate whether it is bypassed or not.
4 fe_pwr
Fault Entry power behavior.
0b0: Fault Entry does not prevent entry into a Disconnected state.
0b1: Fault Entry does prevent entry into a Disconnected state.
3 - 2 flt_cfg
Fault Configuration
Behavior of the Firewall Component when a transaction enters the Faulted state.
0b00: Reserved
0b01: Reserved
0b10: Terminate transaction, generate a fault entry and Access or Programming Error interrupt.
0b11: Terminate transaction, but no fault entry or Access or Programming Error interrupt are generated.
1 raz
Value returned for read accesses when the Firewall Component terminates the transaction.
0b0: Read data is based on the StreamID
0b1: Read data is all 0s
0 err
Response for a transaction terminated by the Firewall Component.
0b0: No error
0b1: Error


fw_ctrl_pe_bps
Protection Extension Bypass Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800108
Address@secenc_fw_ctrl : 0x50200108
Bits Reset value Name Description
31 "0"
bypass_vld
Indicates whether the values in the BYPASS_ST and BYPASS_IF_ST is valid or not.
0b0: Values are not valid
0b1: Values are valid
The behavior of this field depends the level of SRE implemented by the Firewall.
SRE.0: This field always reads as 0b1
SRE.1: This field reads as 0b1 only when the Firewall Component is in the Connected state. Otherwise this field reads as 0b0.
30 - 2 0
-
 reserved
1 "0"
bypass_st
Indicates if the Firewall Components protection logic is bypassed or not.
0b0: Firewall Components protection logic is not bypassed.
0b1: Firewall Components protection logic is bypassed.
0 "0"
bypass_if_st
Bypass interface status
The reset value of this field depends on the value of the Bypass interface of the Firewall Component.


fw_ctrl_rwe_ctrl
RWE Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a80010c
Address@secenc_fw_ctrl : 0x5020010c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
rgn_indx
Region Index
Selects the region to which the RWE refers to.
The width of this field is dependent on the log2(FC_CFG1.NUM_RGN+1) rounded up to the nearest whole number. Any unused bits are Reserved and treated as RAZ/WI.


fw_ctrl_rgn_ctrl0
Region Control Register 0
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800110
Address@secenc_fw_ctrl : 0x50200110
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Region enable
0b0: Request to disable the region
0b1: Request to enable the region


fw_ctrl_rgn_ctrl1
Region Control Register 1
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800114
Address@secenc_fw_ctrl : 0x50200114
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
mpe3_en
Master enable for MPE3
0b0: Request to disable Master permission entry 3.
0b1: Request to enable Master permission entry 3.
Only implemented when FC_CFG2.NUM_MPE is 3. Otherwise this field is Reserved and treated as RAZ/WI.
3 "0"
mpe2_en
Master enable for MPE2
0b0: Request to disable Master permission entry 2.
0b0: Request to enable Master permission entry 2.
Only implemented when FC_CFG2.NUM_MPE is 2 or greater. Otherwise this field is Reserved and treated as RAZ/WI.
2 "0"
mpe1_en
Master enable for MPE1
0b0: Request to disable Master permission entry 1.
0b1: Request to enable Master permission entry 1.
Only implemented when FC_CFG2.NUM_MPE is 1 or greater. Otherwise this field is Reserved and treated as RAZ/WI.
1 "0"
mpe0_en
Master enable for MPE0
0b0: Request to disable Master permission entry. 0
0b1: Request to enable Master permission entry 0.
0 0
-
 reserved


fw_ctrl_rgn_lctrl
Region Lock Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800118
Address@secenc_fw_ctrl : 0x50200118
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
lock
Control the lock status of the region.
0b0: Region is unlocked
0b1: Region is locked
When this field is 1 a configuration access which attempts to update any of the following fields:
- RGN_CTRL{0-1}
- RGN_CFG{0-1}
- RGN_SIZE
- RGN_TCFG{0-2}
- RGN_MID{0-3}
- RGN_MPL{0-3}
Generates:
- A Configuration Access Error
- A Tamper interrupt and Tamper report, if there is no valid Tamper report present. Otherwise, a Tamper Overflow interrupt is generated.
This field is Reserved and treated as RAZ/WI when LDE.0 or LDE.1 is implemented.
When any of the following occur:
- Firewall Components enter the Full lockdown state
- Firewall Components enter the Partial lockdown state and this field is set to 1
This field becomes RO and any attempt to update this field generates:
- A Configuration Access Error
- A Tamper interrupt and Tamper report, if there is no valid Tamper report present. Otherwise, a Tamper Overflow interrupt is generated.


fw_ctrl_rgn_st
FRegion Status Register
R
Address@host_sys_fw_ctrl : 0x1a80011c
Address@secenc_fw_ctrl : 0x5020011c
Bits Name Description
31 - 5 -
 reserved
4 mpe3_en
Master enable for MPE3:
- 0b0: Master permission entry 3 is disabled.
- 0b1: Master permission entry 3 is enabled.
Only when a master permission entry is enabled is an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID3 and RGN_MPL3 are read-only and attempts to update the registers will generate a Configuration Access Error.
3 mpe2_en
Master enable for MPE2:
- 0b0: Master permission entry 2 is disabled.
- 0b1: Master permission entry 2 is enabled.
Only when a master permission entry is enabled will an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID2 and RGN_MPL2 are read-only and attempts to update the registers will generate a Configuration Access Error.
2 mpe1_en
Master enable for MPE1:
- 0b0: Master permission entry 1 is disabled.
- 0b1: Master permission entry 1 is enabled.
Only when a master permission entry is enabled will an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID1 and RGN_MPL1 are read-only and attempts to update the registers will generate a Configuration Access Error.
1 en
Region enable:
- 0b0: Region disable
- 0b1: Region enable
When set to 1 the following registers are read-only:
- RGN_CFG0
- RGN_CFG1
- RGN_TCFG0
- RGN_TCFG1
- RGN_TCFG2
- RGN_SIZE
Any attempt to write to these registers, when the region is enabled, generates a Configuration Access Error.
0 -
 reserved


fw_ctrl_rgn_cfg0
Region Config Register 0
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800120
Address@secenc_fw_ctrl : 0x50200120
Bits Reset value Name Description
31 - 5 0x0
base_addr
The lower 32 bits base address of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
Any unimplemented bits are Reserved and treated as RAZ/WI.
If MXRS and MNRS are equal, then all bits in this register are Reserved and treated as RAZ/WI.
4 - 0 0
-
 reserved


fw_ctrl_rgn_cfg1
Region Config Register 1
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800124
Address@secenc_fw_ctrl : 0x50200124
Bits Reset value Name Description
31 - 0 0x0
base_addr
The upper 32 bits base address of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
Any unimplemented bits are Reserved and treated as RAZ/WI.
If MXRS and MNRS are equal, then all bits in this register are Reserved and treated as RAZ/WI.


fw_ctrl_rgn_size
Region Size Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800128
Address@secenc_fw_ctrl : 0x50200128
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
mulnpo2
Selects whether the region is defined with a base address and size or a base and upper address.
0b0: Region defined by a base address and size, which must be a power of 2. The value of RGN_SIZE.SIZE is used.
0b1: Region defined by a base and upper address, which must both be an integer multiple of MNRS. The value of RGN_SIZE.SIZE is ignored.
This field is Reserved and treated as RAZ/WI when RSE.0 is implemented.
7 - 0 "00000000"
size
TThe size of the region.
0x00: 0B
0x05: 32B
0x06: 64B
-
0x0C: 4KB
0x0D: 8KB
-
0x40: 16KB
The legal values this field can be set to depend on the MNRS and MXRS of the Firewall Component. If software attempts to set this field to a value which is:
- Greater than 0x40
- Less than MNRS of the Firewall. Component
- Greater than MXRS of the Firewall Component
The field is set to 0x00 instead.
When this field reads as 0x00 does not match against any transactions.
The value of the RGN_SIZE field is only used if RGN_SIZE.MULnPO2 is 0.
Otherwise the field is ignored.


fw_ctrl_rgn_tcfg0
Region Translation Config Register 0
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800130
Address@secenc_fw_ctrl : 0x50200130
Bits Reset value Name Description
31 - 5 0x0
output_addr
The output address or the upper address range of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
 Any unimplemented bits are Reserved and treated as RAZ/WI.
4 - 0 0
-
 reserved


fw_ctrl_rgn_tcfg1
Region Translation Config Register 1
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800134
Address@secenc_fw_ctrl : 0x50200134
Bits Reset value Name Description
31 - 0 0x0
upper_addr
The output address or the upper address range of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
 Any unimplemented bits are Reserved and treated as RAZ/WI.


fw_ctrl_rgn_tcfg2
Region Translation Config Register 2
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800138
Address@secenc_fw_ctrl : 0x50200138
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
addr_trans_en
Address Translation enable:
0b0: Address translation is disabled. The output transaction has the same address as the incoming transaction.
0b1: Address translation is enabled.
This field is Reserved and treated as RAZ/WI when:
- TE.1 or lower is implemented
- PE.2 is implemented for the Default Region
- Regions 0-2 for Firewall Controller
16 "0"
ma_trans_en
Memory Attribute Translation enable
0b0: Memory attribute translation is disabled. The output transaction has the same memory attribute as the incoming transaction.
0b1: Memory attribute translation is enabled. The output transactions memory attribute is as defined in RGN_TCG2.MA.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.MA_SPT is 0b0
- TE.0 is implemented
15 - 14 "00"
instr
Output transaction instruction or data:
0b00: Use incoming transaction value.
0b01: Reserved and treated as 00.
0b10: Data
0b11: Instruction
This field only affects read transactions.
All write transactions are considered as data and outgoing write transactions are outputted as data access.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.INST_SPT is 0b0
- TE.0 is implemented
13 - 12 "00"
priv
Output transaction privileged level
0b00: Use incoming privileged level.
0b01:Reserved and treated as 00.
0b10: Unprivileged
0b11: Privileged
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.PRIV_SPT is 0b0
- TE.0 is implemented
11 - 4 "00000000"
ma
Output transaction memory attribute
Defines the memory type, cache allocation policy and whether it is transient or not for the output transaction.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.MA_SPT is 0b0
- TE.0 is implemented
3 - 2 "00"
sh
Output transaction shareability.
0b00: Non-shareable.
0b01: Use incoming shareability.
0b10: Outer shareable.
0b11: Inner shareable.
This field is Reserved and treated as WI and as reads as 0b01, when either:
FC_CFG1.SH_SPT is 0.
or TE.0 is implemented.
1 - 0 "00"
ns
Output transaction security
0b00: Output transaction is marked with the same security as incoming transaction.
0b01: Reserved and treated as 0b00.
0b10: Output transaction is marked as Secure.
0b11: Output transaction is marked as Non-secure.
This only applies if the incoming transaction was Secure.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0b0
- TE.0 is implemented


fw_ctrl_rgn_mid0
Region MasterID Register 0
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800140
Address@secenc_fw_ctrl : 0x50200140
Bits Reset value Name Description
31 - 0 0x0
mst_id
MasterID. The value of the MasterID part of the StreamID which the transaction must have to match this MPE.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.
This field is read-only when FC_CFG2.SINGLE_MST is 0b1.


fw_ctrl_rgn_mpl0
Region Master Permission List Register 0
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800144
Address@secenc_fw_ctrl : 0x50200144
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
any_mst
Selects whether entry is used for all transactions, irrespective of MasterID.
0b0: MPE only used if MasterID of transaction and MPE match
0b1: MPE used irrespective of transaction MasterID
This field is read-only when FC_CFG2.SINGLE_MST is 1.
This field is Reserved and treated as RAZ/WI for RGN_MPL{1-3}.
11 "0"
spx
Secure privilege execute enable
0b0: Secure privileged instruction fetches are not allowed.
0b1: Secure privileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
- FC_CFG1.INST_SPT is 0
10 "0"
spw
Secure privilege write enable
0b0: Secure privileged data write operations are not allowed.
0b1: Secure privileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
9 "0"
spr
Secure privilege read enable
0b0: Secure privileged data read operations are not allowed.
0b1: Secure privileged data read operations are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
8 "0"
sux
Secure unprivileged execute enable
0b0: Secure unprivileged instruction fetches are not allowed.
0b1: Secure unprivileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.INST_SPT is 0
7 "0"
suw
Secure unprivileged write enable
0b0: Secure unprivileged data write operations are not allowed.
0b1: Secure unprivileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when
FC_CFG1.SEC_SPT is 0.
6 "0"
sur
Secure unprivileged read enable
0b0: Secure unprivileged data read operations are not allowed.
0b1: Secure unprivileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when
FC_CFG1.SEC_SPT is 0.
5 "0"
nspx
Non-secure privilege execute enable
0b0: Non-secure privileged instruction fetches are not allowed.
0b1: Non-secure privileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.PRIV_SPT is 0
- FC_CFG1.INST_SPT is 0
4 "0"
nspw
Non-secure privilege write enable
0b0: Non-secure privileged data write operations are not allowed.
0b1: Non-secure privileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.PRIV_SPT is 0.
3 "0"
nspr
Non-secure privilege read enable
0b0: Non-secure privileged data read operations are not allowed.
0b1: Non-secure privileged data read operations are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.PRIV_SPT is 0.
2 "0"
nsux
Non-secure unprivileged execute enable
0b0: Non-secure unprivileged instruction fetches are not allowed.
0b1: Non-secure unprivileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.INST_SPT is 0.
1 "0"
nsuw
Non-secure unprivileged write enable
0b0: Non-secure unprivileged data write operations are not allowed.
0b1: Non-secure unprivileged data write operations are allowed
0 "0"
nsur
Non-secure unprivileged read enable
0b0: Non-secure unprivileged data read operations are not allowed.
0b1: Non-secure unprivileged data read operations are allowed.


fw_ctrl_rgn_mid1
Region MasterID Register 1
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800148
Address@secenc_fw_ctrl : 0x50200148
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mid1


fw_ctrl_rgn_mpl1
Region Master Permission List Register 1
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a80014c
Address@secenc_fw_ctrl : 0x5020014c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mpl1


fw_ctrl_rgn_mid2
Region MasterID Register 2
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800150
Address@secenc_fw_ctrl : 0x50200150
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mid2


fw_ctrl_rgn_mpl2
Region Master Permission List Register 2
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800154
Address@secenc_fw_ctrl : 0x50200154
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mpl2


fw_ctrl_rgn_mid3
Region MasterID Register 3
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800158
Address@secenc_fw_ctrl : 0x50200158
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mid3


fw_ctrl_rgn_mpl3
Region Master Permission List Register 3
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a80015c
Address@secenc_fw_ctrl : 0x5020015c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_rgn_mpl3


fw_ctrl_fe_tal
Fault Entry Transaction Address Lower Register
R
Address@host_sys_fw_ctrl : 0x1a800180
Address@secenc_fw_ctrl : 0x50200180
Bits Name Description
31 - 0 fault_addr_lwr
Fault transaction address lower.
This field is RAZ when FE_CTRL.FE_VLD is 0.


fw_ctrl_fe_tau
Fault Entry Transaction Address Upper Register
R
Address@host_sys_fw_ctrl : 0x1a800184
Address@secenc_fw_ctrl : 0x50200184
Bits Name Description
31 - 0 fault_addr_upr
Fault transaction address upper.
This field is RAZ when FE_CTRL.FE_VLD is 0.


fw_ctrl_fe_tp
Fault Entry Transaction Properties Register
R
Address@host_sys_fw_ctrl : 0x1a800188
Address@secenc_fw_ctrl : 0x50200188
Bits Name Description
31 - 22 -
 reserved
21 w
Indicates whether the transaction was a read or write:
0b0: Read
0b1: Write
20 - 19 -
 reserved
18 instr
Indicates whether the transaction was an instruction or data access:
0b0: Data
0b1: Instruction
17 priv
Indicates the privileged level of the transaction:
0b0: Unprivileged
0b1: Privileged
16 ns
Indicates the security level of the transaction:
0b0: Secure
0b1: Non-secure
When SE.0 is implemented this field is Reserved and is treated as RAO/WI.
15 - 0 -
 reserved


fw_ctrl_fe_mid
Fault Entry MasterID Register
R
Address@host_sys_fw_ctrl : 0x1a80018c
Address@secenc_fw_ctrl : 0x5020018c
Bits Name Description
31 - 0 mst_id
The reset value of this field depends on the value of FC_CFG2.SINGLE_MST:
Indicates the MasterID of the master which issued the transaction.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.


fw_ctrl_fe_ctrl
Fault Entry Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800190
Address@secenc_fw_ctrl : 0x50200190
Bits Reset value Name Description
31 "0"
last_fe
Indicates if this fault entry is the last valid entry:
0b0: Entry is the not last valid fault entry.
0b1: Entry is the last valid fault entry.
30 "0"
fe_vld
Indicates whether the FWE is pointing to a valid fault entry:
0b0: FWE is pointing to an invalid fault entry.
0b1: FWE is pointing to a valid fault entry.
When this field is 0b0 the following fields, in the FWE, read as 0x0:
- FE_TAL
- FE_TAU
- FE_TP
- FE_MID
- FE_CTRL.FLT_TYPE
29 - 4 0
-
 reserved
3 "0"
flt_type
Indicates the fault type:
0b0: Transaction fault
0b1: Programming fault
2 - 1 0
-
 reserved
0 "0"
ack
Acknowledge the transaction. This field always reads as 0b0.
Writes to this field behave as follows:
0b0: Ignored
0b1: Fault transaction is acknowledged
Writes to this register are ignored if FE_CTRL.FE_VLD is 0b0.


fw_ctrl_me_ctrl
Monitor Extension Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800200
Address@secenc_fw_ctrl : 0x50200200
Bits Reset value Name Description
31 "0"
en
Request the Firewall Components monitor logic enables or disables.
0b0: Request to disable the Firewall Components monitor logic
0b1: Request to enable the Firewall Components monitor logic
30 - 5 0
-
 reserved
4 "0"
edr_pwr
Request error detection reports power behavior.
0b0: Error detection report does not prevent entry into a Disconnected state
0b1: Error detection report does prevent entry into a Disconnected state
3 - 2 0
-
 reserved
1 "0"
rdum
Request behavior for read data returned for a read transaction which has caused an error.
0b0: Read data is based on the StreamID
0b1: Read data is left unmodified
0 0
-
 reserved


fw_ctrl_me_st
Monitor Extension Status Register
R
Address@host_sys_fw_ctrl : 0x1a800204
Address@secenc_fw_ctrl : 0x50200204
Bits Name Description
31 en
Status of the Firewall Components monitor logic enables or disables.
0b0: Firewall Components monitor logic is disabled.
0b1: Firewall Components monitor logic is enabled.
When SRE.1 is implemented and the Firewall Component has entered the Disconnected state this field matches the value in ME_CTRL.EN.
As if the request to change from enabled to disable or disabled to enabled has completed.
30 - 5 -
 reserved
4 edr_pwr
Error detection reports power behavior.
0b0: Error detection report does not prevent entry into a Disconnected state.
0b1: Error detection report does prevent entry into a Disconnected state.
3 - 2 -
 reserved
1 rdum
Request behavior for read data returned for a read transaction which has caused an error.
0b0: Read data is based on the StreamID
0b1: Read data is left unmodified
0 -
 reserved


fw_ctrl_edr_tal
Error Detection Report Transaction Address Lower Register
R
Address@host_sys_fw_ctrl : 0x1a800260
Address@secenc_fw_ctrl : 0x50200260
Bits Name Description
31 - 0 error_addr_lwr
Error transaction address lower.
This field is RAZ when EDR_CTRL.EDR_VLD is 0.


fw_ctrl_edr_tau
Error Detection Report Transaction Address Upper Register
R
Address@host_sys_fw_ctrl : 0x1a800264
Address@secenc_fw_ctrl : 0x50200264
Bits Name Description
31 - 0 error_addr_upr
Error transaction address upper.
This field is RAZ when EDR_CTRL.EDR_VLD is 0.


fw_ctrl_edr_tp
Error Detection Transaction Properties Register
R
Address@host_sys_fw_ctrl : 0x1a800268
Address@secenc_fw_ctrl : 0x50200268
Bits Name Description
31 - 22 -
 reserved
21 w
Indicates whether the transaction, which caused the error, was a read or write.
0b0: Read
0b1: Write
20 - 19 -
 reserved
18 instr
Indicates whether the transaction, which caused the error, was an instruction or data access.
0b0: Data
0b1: Instruction
17 priv
Indicates the privileged level of the transaction, which caused the error.
0b0: Unprivileged.
0b1: Privileged.
16 ns
Indicates the security level of the transaction.
0b0: Secure
0b1: Non-secure
15 - 0 -
 reserved


fw_ctrl_edr_mid
Error Detection Report MasterID Register
R
Address@host_sys_fw_ctrl : 0x1a80026c
Address@secenc_fw_ctrl : 0x5020026c
Bits Name Description
31 - 0 mst_id
Indicates the MasterID of the transaction which caused the error.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.


fw_ctrl_edr_ctrl
Error Detection Report Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800270
Address@secenc_fw_ctrl : 0x50200270
Bits Reset value Name Description
31 "0"
last_edr
Indicates if this error detection entry is the last valid entry.
0b0: Report is not the last valid error detection report.
0b1: Report is the last valid error detection report.
30 "0"
edr_vld
Indicates whether the EDW is pointing to a valid error detection report.
0b0: EDW is pointing to an invalid error detection report.
0b1: EDW is pointing to a valid error detection report.
When this field is 0b0 the values in the following registers read as 0:
- EDR_TAL
- EDR_TAU
- EDR_TP
- EDR_MID
29 - 1 0
-
 reserved
0 "0"
ack
Acknowledge the error transaction.
This field always reads as 0b0.
Writes to this field behave as follows:
0b0: Ignored
0b1: Error detection report is acknowledged.
Writes to this register are ignored if EDR_CTRL.EDR_VLD is 0b0.


fw_ctrl_fc0_int_st
Firewall Component 0 Interrupt Status Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d00
Address@secenc_fw_ctrl : 0x50200d00
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
ed_ovrflw_st
Indicates whether an error detection report overflow has occurred in the Firewall Component.
0b0: No error detection report overflow has occurred
0b1: Error detection report overflow has occurred
This field is write 1 to clear, writing 0 to this field has no effect.
3 "0"
ed_st
Indicates whether the Firewall Component has detected an error response and generated an error detection report.
0b0: No error response has been detected
0b1: Error response has been detected
This field is write 1 to clear, writing 0 to this field has no effect.
2 "0"
flt_ovrflw_st
Indicates whether a fault entry overflow has occurred in the Firewall Component.
0b0: No fault entry overflow has occurred
0b1: Fault entry overflow has occurred
This field is write 1 to clear, writing 0 to this field has no effect.
1 "0"
prog_err_st
Indicates whether the Firewall Component has detected a Programming Error.
0b0: No Programming Error has occurred.
0b1: Programming Error has occurred.
This field is write 1 to clear, writing 0 to this field has no effect.
0 "0"
acc_err_st
Indicates whether the Firewall Component has detected an Access Error.
0b0: No Access Error has occurred.
0b1: An Access Error has occurred.
This field is write 1 to clear, writing 0 to this field has no effect.


fw_ctrl_fc1_int_st
Firewall Component 1 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d04
Address@secenc_fw_ctrl : 0x50200d04
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc1_int_st


fw_ctrl_fc2_int_st
Firewall Component 2 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d08
Address@secenc_fw_ctrl : 0x50200d08
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc2_int_st


fw_ctrl_fc3_int_st
Firewall Component 3 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d0c
Address@secenc_fw_ctrl : 0x50200d0c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc3_int_st


fw_ctrl_fc4_int_st
Firewall Component 4 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d10
Address@secenc_fw_ctrl : 0x50200d10
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc4_int_st


fw_ctrl_fc5_int_st
Firewall Component 5 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d14
Address@secenc_fw_ctrl : 0x50200d14
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc5_int_st


fw_ctrl_fc6_int_st
Firewall Component 6 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d18
Address@secenc_fw_ctrl : 0x50200d18
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc6_int_st


fw_ctrl_fc7_int_st
Firewall Component 7 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d1c
Address@secenc_fw_ctrl : 0x50200d1c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc7_int_st


fw_ctrl_fc8_int_st
Firewall Component 8 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d20
Address@secenc_fw_ctrl : 0x50200d20
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc8_int_st


fw_ctrl_fc9_int_st
Firewall Component 9 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d24
Address@secenc_fw_ctrl : 0x50200d24
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc9_int_st


fw_ctrl_fc10_int_st
Firewall Component 10 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d28
Address@secenc_fw_ctrl : 0x50200d28
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc10_int_st


fw_ctrl_fc11_int_st
Firewall Component 11 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d2c
Address@secenc_fw_ctrl : 0x50200d2c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc11_int_st


fw_ctrl_fc12_int_st
Firewall Component 12 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d30
Address@secenc_fw_ctrl : 0x50200d30
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc12_int_st


fw_ctrl_fc13_int_st
Firewall Component 13 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d34
Address@secenc_fw_ctrl : 0x50200d34
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc13_int_st


fw_ctrl_fc14_int_st
Firewall Component 14 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d38
Address@secenc_fw_ctrl : 0x50200d38
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc14_int_st


fw_ctrl_fc15_int_st
Firewall Component 15 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d3c
Address@secenc_fw_ctrl : 0x50200d3c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc15_int_st


fw_ctrl_fc16_int_st
Firewall Component 16 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d40
Address@secenc_fw_ctrl : 0x50200d40
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc16_int_st


fw_ctrl_fc17_int_st
Firewall Component 17 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d44
Address@secenc_fw_ctrl : 0x50200d44
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc17_int_st


fw_ctrl_fc18_int_st
Firewall Component 18 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d48
Address@secenc_fw_ctrl : 0x50200d48
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc18_int_st


fw_ctrl_fc19_int_st
Firewall Component 19 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d4c
Address@secenc_fw_ctrl : 0x50200d4c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc19_int_st


fw_ctrl_fc20_int_st
Firewall Component 20 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d50
Address@secenc_fw_ctrl : 0x50200d50
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc20_int_st


fw_ctrl_fc21_int_st
Firewall Component 21 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d54
Address@secenc_fw_ctrl : 0x50200d54
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc21_int_st


fw_ctrl_fc22_int_st
Firewall Component 22 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d58
Address@secenc_fw_ctrl : 0x50200d58
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc22_int_st


fw_ctrl_fc23_int_st
Firewall Component 23 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d5c
Address@secenc_fw_ctrl : 0x50200d5c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc23_int_st


fw_ctrl_fc24_int_st
Firewall Component 24 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d60
Address@secenc_fw_ctrl : 0x50200d60
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc24_int_st


fw_ctrl_fc25_int_st
Firewall Component 25 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d64
Address@secenc_fw_ctrl : 0x50200d64
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc25_int_st


fw_ctrl_fc26_int_st
Firewall Component 26 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d68
Address@secenc_fw_ctrl : 0x50200d68
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc26_int_st


fw_ctrl_fc27_int_st
Firewall Component 27 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d6c
Address@secenc_fw_ctrl : 0x50200d6c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc27_int_st


fw_ctrl_fc28_int_st
Firewall Component 28 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d70
Address@secenc_fw_ctrl : 0x50200d70
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc28_int_st


fw_ctrl_fc29_int_st
Firewall Component 29 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d74
Address@secenc_fw_ctrl : 0x50200d74
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc29_int_st


fw_ctrl_fc30_int_st
Firewall Component 30 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d78
Address@secenc_fw_ctrl : 0x50200d78
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc30_int_st


fw_ctrl_fc31_int_st
Firewall Component 31 Interrupt Status Register
For detailed information refer to 'fc0_int_st' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800d7c
Address@secenc_fw_ctrl : 0x50200d7c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc31_int_st


fw_ctrl_fw_int_st
Firewall Interrupt Status Register
R
Address@host_sys_fw_ctrl : 0x1a800d90
Address@secenc_fw_ctrl : 0x50200d90
Bits Name Description
31 - 0 fc_int_st
Interrupt status for the associated Firewall Component. There is a bit per Firewall Component which indicates if any bit in the associated FC{0-31}_INT_ST register is 1.
Any bits associated with a Firewall Component which is not implemented are Reserved and treated as RAZ/WI:
- 0b0: No interrupt is asserted by Firewall Component.
- 0b1: Interrupt is asserted by Firewall Component.
Bit 0 is for Firewall Component 0, while bit 31 is for Firewall Component 31.


fw_ctrl_fc0_int_msk
Firewall Component 0 Interrupt Mask Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e00
Address@secenc_fw_ctrl : 0x50200e00
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
ed_ovrflw_msk
Selects whether Error Detection Overflow interrupts are masked.
0 - Error Detection Overflow interrupts are reported to the system.
1 - Error Detection Overflow interrupt is not reported to the system.
This field is Reserved and treated as RAZ/WI when ME.0 is implemented.
3 "0"
ed_msk
Selects whether Error Detection interrupts are masked.
0 - Error Detection interrupts are reported to the system.
1 - Error Detection interrupt is not report to the system.
This field is Reserved and treated as RAZ/WI when ME.0 is implemented.
2 "0"
flt_ovrflw_msk
Selects whether Fault Event Overflow interrupts are masked.
0 - Fault Event Overflow interrupts are reported to the system.
1 - Fault Event Overflow interrupts are not reported to the system.
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.
1 "0"
prog_err_msk
Selects whether Programming Error interrupts are masked.
0 - Programming Error interrupts are reported to the system.
1 - Programming Error interrupts are not reported to the system.
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.
0 "0"
acc_err_msk
Selects whether Access Error interrupts are masked.
0 - Access Error interrupts are reported to the system.
1 - Access Error interrupts are not reported to the system.
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.


fw_ctrl_fc1_int_msk
Firewall Component 1 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e04
Address@secenc_fw_ctrl : 0x50200e04
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc1_int_msk


fw_ctrl_fc2_int_msk
Firewall Component 2 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e08
Address@secenc_fw_ctrl : 0x50200e08
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc2_int_msk


fw_ctrl_fc3_int_msk
Firewall Component 3 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e0c
Address@secenc_fw_ctrl : 0x50200e0c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc3_int_msk


fw_ctrl_fc4_int_msk
Firewall Component 4 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e10
Address@secenc_fw_ctrl : 0x50200e10
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc4_int_msk


fw_ctrl_fc5_int_msk
Firewall Component 5 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e14
Address@secenc_fw_ctrl : 0x50200e14
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc5_int_msk


fw_ctrl_fc6_int_msk
Firewall Component 6 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e18
Address@secenc_fw_ctrl : 0x50200e18
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc6_int_msk


fw_ctrl_fc7_int_msk
Firewall Component 7 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e1c
Address@secenc_fw_ctrl : 0x50200e1c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc7_int_msk


fw_ctrl_fc8_int_msk
Firewall Component 8 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e20
Address@secenc_fw_ctrl : 0x50200e20
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc8_int_msk


fw_ctrl_fc9_int_msk
Firewall Component 9 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e24
Address@secenc_fw_ctrl : 0x50200e24
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc9_int_msk


fw_ctrl_fc10_int_msk
Firewall Component 10 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e28
Address@secenc_fw_ctrl : 0x50200e28
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc10_int_msk


fw_ctrl_fc11_int_msk
Firewall Component 11 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e2c
Address@secenc_fw_ctrl : 0x50200e2c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc11_int_msk


fw_ctrl_fc12_int_msk
Firewall Component 12 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e30
Address@secenc_fw_ctrl : 0x50200e30
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc12_int_msk


fw_ctrl_fc13_int_msk
Firewall Component 13 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e34
Address@secenc_fw_ctrl : 0x50200e34
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc13_int_msk


fw_ctrl_fc14_int_msk
Firewall Component 14 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e38
Address@secenc_fw_ctrl : 0x50200e38
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc14_int_msk


fw_ctrl_fc15_int_msk
Firewall Component 15 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e3c
Address@secenc_fw_ctrl : 0x50200e3c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc15_int_msk


fw_ctrl_fc16_int_msk
Firewall Component 16 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e40
Address@secenc_fw_ctrl : 0x50200e40
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc16_int_msk


fw_ctrl_fc17_int_msk
Firewall Component 17 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e44
Address@secenc_fw_ctrl : 0x50200e44
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc17_int_msk


fw_ctrl_fc18_int_msk
Firewall Component 18 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e48
Address@secenc_fw_ctrl : 0x50200e48
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc18_int_msk


fw_ctrl_fc19_int_msk
Firewall Component 19 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e4c
Address@secenc_fw_ctrl : 0x50200e4c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc19_int_msk


fw_ctrl_fc20_int_msk
Firewall Component 20 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e50
Address@secenc_fw_ctrl : 0x50200e50
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc20_int_msk


fw_ctrl_fc21_int_msk
Firewall Component 21 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e54
Address@secenc_fw_ctrl : 0x50200e54
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc21_int_msk


fw_ctrl_fc22_int_msk
Firewall Component 22 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e58
Address@secenc_fw_ctrl : 0x50200e58
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc22_int_msk


fw_ctrl_fc23_int_msk
Firewall Component 23 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e5c
Address@secenc_fw_ctrl : 0x50200e5c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc23_int_msk


fw_ctrl_fc24_int_msk
Firewall Component 24 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e60
Address@secenc_fw_ctrl : 0x50200e60
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc24_int_msk


fw_ctrl_fc25_int_msk
Firewall Component 25 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e64
Address@secenc_fw_ctrl : 0x50200e64
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc25_int_msk


fw_ctrl_fc26_int_msk
Firewall Component 26 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e68
Address@secenc_fw_ctrl : 0x50200e68
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc26_int_msk


fw_ctrl_fc27_int_msk
Firewall Component 27 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e6c
Address@secenc_fw_ctrl : 0x50200e6c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc27_int_msk


fw_ctrl_fc28_int_msk
Firewall Component 28 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e70
Address@secenc_fw_ctrl : 0x50200e70
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc28_int_msk


fw_ctrl_fc29_int_msk
Firewall Component 29 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e74
Address@secenc_fw_ctrl : 0x50200e74
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc29_int_msk


fw_ctrl_fc30_int_msk
Firewall Component 30 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e78
Address@secenc_fw_ctrl : 0x50200e78
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc30_int_msk


fw_ctrl_fc31_int_msk
Firewall Component 31 Interrupt Mask Register
For detailed information refer to 'fc0_int_msk' register description.
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800e7c
Address@secenc_fw_ctrl : 0x50200e7c
Bits Reset value Name Description
31 - 0 0
fw_ctrl_fc31_int_msk


fw_ctrl_fw_tmp_ta
Firewall Tamper Transaction Address Register
R
Address@host_sys_fw_ctrl : 0x1a800e90
Address@secenc_fw_ctrl : 0x50200e90
Bits Name Description
31 - 21 -
 reserved
20 - 2 tmp_trans_addr
Address of the accessed register which caused the tamper report to be generated
1 - 0 -
 reserved


fw_ctrl_fw_tmp_tp
Firewall Tamper Transaction Properties Register
R
Address@host_sys_fw_ctrl : 0x1a800e98
Address@secenc_fw_ctrl : 0x50200e98
Bits Name Description
31 - 18 -
 reserved
17 priv
Indicates the privileged level of the transaction which generated the tamper report.
0b0: Unprivileged
0b1: Privileged
16 ns
Indicates the security level of the transaction which generated the tamper report.
0b0: Secure
0b1: Non-secure
15 - 0 -
 reserved


fw_ctrl_fw_tmp_mid
Firewall Tamper MasterID Register
R
Address@host_sys_fw_ctrl : 0x1a800e9c
Address@secenc_fw_ctrl : 0x50200e9c
Bits Name Description
31 - 0 mst_id
Indicates the MasterID of the transaction which caused the tamper report.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.


fw_ctrl_fw_tmp_ctrl
Firewall Tamper Control Register
R/W
0x00000000
Address@host_sys_fw_ctrl : 0x1a800ea0
Address@secenc_fw_ctrl : 0x50200ea0
Bits Reset value Name Description
31 "0"
tr_vld
Indicates whether there is a valid tamper report or not.
0b0: No valid tamper report
0b1: Valid tamper report
When this field is 0 the values in the following registers read as 0:
- FW_TMP_TA
- FW_TMP_TP
- FW_TMP_MID
30 "0"
ack
Acknowledge the Tamper report
This field always reads as 0.
Writes to this field behave as follows:
0b0: Ignored
0b1: Tamper report acknowledged
Writes to this register are ignored if FW_TMP_CTRL.TR_VLD is 0.
29 - 0 0
-
 reserved


fw_ctrl_fc_cap0
Firewall Component Capability Register 0
R
Address@host_sys_fw_ctrl : 0x1a800fa0
Address@secenc_fw_ctrl : 0x50200fa0
Bits Name Description
31 - 28 -
 reserved
27 - 24 se_lvl
Level of the Security Extension used by the Firewall.
0x0: SE.0 is implemented
0x1: SE.1 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
23 - 20 sre_lvl
Level of the Save and Restore Extension used by the Firewall.
0x0: SRE.0 is implemented
0x1: SRE.1 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
19 - 16 lde_lvl
Level of the Lockdown Extension implemented by the Firewall.
0x0: LDE.0 is implemented
0x1: LDE.1 is implemented
0x2: LDE.2 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
15 - 12 te_lvl
Level of the Translation Extension implemented by Firewall Component.
0x0: TE.0 is implemented
0x1: TE.1 is implemented
0x2: TE.2 is implemented
All other values are Reserved.
This field must always be 0x0 when the FC_CAP0.PE_LVL is 0x0.
11 - 8 rse_lvl
Level of the Region Size Extension implemented by Firewall Component.
0x0: RSE.0 is implemented
0x1: RSE.1 is implemented
All other values are Reserved.
This field must always be 0x0 when the FC_CAP0.PE_LVL is 0x0.
7 - 4 me_lvl
Level of the Monitor Extension implemented by the Firewall Component.
0x0: TE.0 is implemented
0x1: TE.1 is implemented
All other values are Reserved.
3 - 0 pe_lvl
Level of the Protection Extension implemented by the Firewall Component.
0x0: PE.0 is implemented
0x1: PE.1 is implemented
0x2: PE.2 is implemented
All other values are Reserved.


fw_ctrl_fc_cap1
Firewall Component Capability Register 1
R
Address@host_sys_fw_ctrl : 0x1a800fa4
Address@secenc_fw_ctrl : 0x50200fa4
Bits Name Description
31 - 0 fw_ctrl_fc_cap1


fw_ctrl_fc_cap2
Firewall Component Capability Register 2
R
Address@host_sys_fw_ctrl : 0x1a800fa8
Address@secenc_fw_ctrl : 0x50200fa8
Bits Name Description
31 - 0 fw_ctrl_fc_cap2


fw_ctrl_fc_cap3
Firewall Component Capability Register 3
R
Address@host_sys_fw_ctrl : 0x1a800fac
Address@secenc_fw_ctrl : 0x50200fac
Bits Name Description
31 - 0 fw_ctrl_fc_cap3


fw_ctrl_fc_cfg0
Firewall Component Capability Register 0
R
Address@host_sys_fw_ctrl : 0x1a800fb0
Address@secenc_fw_ctrl : 0x50200fb0
Bits Name Description
31 - 5 -
 reserved
4 - 0 fc_id
Firewall Component ID


fw_ctrl_fc_cfg1
Firewall Component Configuration Register 1
R
Address@host_sys_fw_ctrl : 0x1a800fb4
Address@secenc_fw_ctrl : 0x50200fb4
Bits Name Description
31 - 21 -
 reserved
20 sec_spt
Firewall Component support for checking the security of the incoming transaction and setting the security of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when SE.0 is implemented and 1 when SE.1 is implemented.
19 ma_spt
Firewall Component support for setting the memory type of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when TE.0 is implemented.
18 sh_spt
Firewall Component support for setting the shareability of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when TE.0 is implemented.
17 inst_spt
Firewall Component support for checking whether the incoming transaction is an instruction or data access and setting the instruction property of the outgoing transaction.
0b0: Not supported
0b1: Supported
16 priv_spt
Firewall Component support for checking the privileged level of the incoming transaction and setting the privileged level of the outgoing transaction.
0b0: Not supported
0b1: Supported
15 - 14 -
 reserved
13 - 12 num_mpe
Number of MPEs implemented, per region, in the Firewall Component.
0b00: 1 MPE per region
0b01: 2 MPEs per region
0b10: 3 MPEs per region
0b11: 4 MPEs per region
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.
11 -
 reserved
10 - 8 mnrs
Minimum Region Size
0x1: 64B, 0x2: 128B, 0x3: 256B, 0x4: 512B, 0x5: 1KB, 0x6: 2KB, 0x7: 4KB
7 - 0 num_rgn
Number of regions implemented in the Firewall Component.
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.


fw_ctrl_fc_cfg2
Firewall Component Configuration Register 2
R
Address@host_sys_fw_ctrl : 0x1a800fb8
Address@secenc_fw_ctrl : 0x50200fb8
Bits Name Description
31 single_mst
Whether the Firewall Component supports a single MasterID.
0b0: Firewall Component supports more than one MasterID.
0b1: Firewall Component supports only one MasterID.
30 - 21 -
 reserved
20 - 13 prot_size
Protection Size. The value of this field indicates the range of addresses which the Firewall Component protects.
0x00: 0B, 0x05: 32B, 0x06: 64B, ... 0x0C: 4K, 0x0D: 8KB, ... 0x40: 16EB
12 - 8 mst_id_width
Maximum MasterID field width of the Bus interfaces of the Firewall Component.
which the Firewall Component protects.
0x00: 1 bit of MasterID, 0x01: 2 bits of MasterID ... 0x1F: 32 bits of MasterID
When a Firewall Component supports more than one Bus Slave or Master interface this field is set to the largest width used.
7 -
 reserved
6 - 0 mxrs
The Maximum Region Size the Firewall Component Supports.
0x05: 32B, 0x06: 64B, ... 0x0C: 4KB, 0x0D: 8KB ... 0x40: 16EB
All other values are Reserved.
This field is Reserved and treated as RAZ/WI invalid for a Firewall Component which implements PE.0.


fw_ctrl_fc_cfg3
Firewall Component Configuration Register 3
R
Address@host_sys_fw_ctrl : 0x1a800fbc
Address@secenc_fw_ctrl : 0x50200fbc
Bits Name Description
31 - 6 -
 reserved
5 - 0 num_fc
Number of Firewall Components implemented.
The number of Firewall Components which are implemented in the Firewall is NUM_FC+1.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.


fw_ctrl_iidr
Implementation Identification Register
R
Address@host_sys_fw_ctrl : 0x1a800fc8
Address@secenc_fw_ctrl : 0x50200fc8
Bits Name Description
31 - 20 product_id
Firewall part ID
19 - 16 variant
Firewall varient
15 - 12 revision
Firewall revision
11 - 0 implementer
Contains the JEP106 code of Arm.
- [11:8] JEP106 continuation code of implementer
- [7] Always 0
- [6:0] JEP106 identity code of implementer


fw_ctrl_aidr
Architecture Identification Register
R
Address@host_sys_fw_ctrl : 0x1a800fcc
Address@secenc_fw_ctrl : 0x50200fcc
Bits Name Description
31 - 8 -
 reserved
7 - 4 arch_major_rev
Firewall Architecture Major Revision
0x0 - Major Revision 0
All other values are reserved.
3 - 0 arch_minor_rev
Firewall Architecture Minor Revision
0x0 - Minor Revision 0
All other values are reserved.


fw_ctrl_pid4
Peripheral ID Register 4
R
Address@host_sys_fw_ctrl : 0x1a800fd0
Address@secenc_fw_ctrl : 0x50200fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


fw_ctrl_pid5
Peripheral ID Register 5
R
Address@host_sys_fw_ctrl : 0x1a800fd4
Address@secenc_fw_ctrl : 0x50200fd4
Bits Name Description
31 - 0 fw_ctrl_pid5


fw_ctrl_pid6
Peripheral ID Register 6
R
Address@host_sys_fw_ctrl : 0x1a800fd8
Address@secenc_fw_ctrl : 0x50200fd8
Bits Name Description
31 - 0 fw_ctrl_pid6


fw_ctrl_pid7
Peripheral ID Register 7
R
Address@host_sys_fw_ctrl : 0x1a800fdc
Address@secenc_fw_ctrl : 0x50200fdc
Bits Name Description
31 - 0 fw_ctrl_pid7


fw_ctrl_pid0
Peripheral ID Register 0
R
Address@host_sys_fw_ctrl : 0x1a800fe0
Address@secenc_fw_ctrl : 0x50200fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


fw_ctrl_pid1
Peripheral ID Register 1
R
Address@host_sys_fw_ctrl : 0x1a800fe4
Address@secenc_fw_ctrl : 0x50200fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


fw_ctrl_pid2
Peripheral ID Register 2
R
Address@host_sys_fw_ctrl : 0x1a800fe8
Address@secenc_fw_ctrl : 0x50200fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


fw_ctrl_pid3
Peripheral ID Register 3
R
Address@host_sys_fw_ctrl : 0x1a800fec
Address@secenc_fw_ctrl : 0x50200fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


fw_ctrl_cid0
Component ID Register 0
R
Address@host_sys_fw_ctrl : 0x1a800ff0
Address@secenc_fw_ctrl : 0x50200ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


fw_ctrl_cid1
Component ID Register 1
R
Address@host_sys_fw_ctrl : 0x1a800ff4
Address@secenc_fw_ctrl : 0x50200ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


fw_ctrl_cid2
Component ID Register 2
R
Address@host_sys_fw_ctrl : 0x1a800ff8
Address@secenc_fw_ctrl : 0x50200ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


fw_ctrl_cid3
Component ID Register 3
R
Address@host_sys_fw_ctrl : 0x1a800ffc
Address@secenc_fw_ctrl : 0x50200ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: host_sys_fw_comp_sysperi, host_sys_fw_comp_dbgperi, host_sys_fw_comp_aonperi, host_sys_fw_comp_envm, host_sys_fw_comp_cvm, host_sys_fw_comp_hostcpu, host_sys_fw_comp_com, host_sys_fw_comp_mot, host_sys_fw_comp_hperi_slv, host_sys_fw_comp_sms_slv, host_sys_fw_comp_hperi_mst, host_sys_fw_comp_sms_mst, host_sys_fw_comp_evm, host_sys_fw_comp_debug, secenc_fw_comp_fc1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-3 0-c -  reserved
4 10 R/W fw_comp_ld_ctrl
5-3f 14-fc -  reserved
40 100 R/W fw_comp_pe_ctrl
41 104 R fw_comp_pe_st
42 108 R/W fw_comp_pe_bps
43 10c R/W fw_comp_rwe_ctrl
44 110 R/W fw_comp_rgn_ctrl0
45 114 R/W fw_comp_rgn_ctrl1
46 118 R/W fw_comp_rgn_lctrl
47 11c R fw_comp_rgn_st
48 120 R/W fw_comp_rgn_cfg0
49 124 R/W fw_comp_rgn_cfg1
4a 128 R/W fw_comp_rgn_size
4b 12c -  reserved
4c 130 R/W fw_comp_rgn_tcfg0
4d 134 R/W fw_comp_rgn_tcfg1
4e 138 R/W fw_comp_rgn_tcfg2
4f 13c -  reserved
50 140 R/W fw_comp_rgn_mid0
51 144 R/W fw_comp_rgn_mpl0
52 148 R/W fw_comp_rgn_mid1
53 14c R/W fw_comp_rgn_mpl1
54 150 R/W fw_comp_rgn_mid2
55 154 R/W fw_comp_rgn_mpl2
56 158 R/W fw_comp_rgn_mid3
57 15c R/W fw_comp_rgn_mpl3
58-5f 160-17c -  reserved
60 180 R fw_comp_fe_tal
61 184 R fw_comp_fe_tau
62 188 R fw_comp_fe_tp
63 18c R fw_comp_fe_mid
64 190 R/W fw_comp_fe_ctrl
65-7f 194-1fc -  reserved
80 200 R/W fw_comp_me_ctrl
81 204 R fw_comp_me_st
82-97 208-25c -  reserved
98 260 R fw_comp_edr_tal
99 264 R fw_comp_edr_tau
9a 268 R fw_comp_edr_tp
9b 26c R fw_comp_edr_mid
9c 270 R/W fw_comp_edr_ctrl
9d-3e7 274-f9c -  reserved
3e8 fa0 R fw_comp_fc_cap0
3e9 fa4 R fw_comp_fc_cap1
3ea fa8 R fw_comp_fc_cap2
3eb fac R fw_comp_fc_cap3
3ec fb0 R fw_comp_fc_cfg0
3ed fb4 R fw_comp_fc_cfg1
3ee fb8 R fw_comp_fc_cfg2
3ef fbc R fw_comp_fc_cfg3
3f0-3ff fc0-ffc -  reserved

fw_comp_ld_ctrl
Lockdown Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810010
Address@host_sys_fw_comp_dbgperi : 0x1a820010
Address@host_sys_fw_comp_aonperi : 0x1a830010
Address@host_sys_fw_comp_envm : 0x1a840010
Address@host_sys_fw_comp_cvm : 0x1a850010
Address@host_sys_fw_comp_hostcpu : 0x1a860010
Address@host_sys_fw_comp_com : 0x1a870010
Address@host_sys_fw_comp_mot : 0x1a880010
Address@host_sys_fw_comp_hperi_slv : 0x1a890010
Address@host_sys_fw_comp_sms_slv : 0x1a8a0010
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0010
Address@host_sys_fw_comp_sms_mst : 0x1a8c0010
Address@host_sys_fw_comp_evm : 0x1a8d0010
Address@host_sys_fw_comp_debug : 0x1a8e0010
Address@secenc_fw_comp_fc1 : 0x50210010
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
ldi_st
Lockdown interface status.
Indicates the current value of the Lockdown interface.
0b0: Lockdown interface is de-asserted.
0b1: Lockdown interface is asserted.
This field reads as 0b0 for Firewall Components other than the Firewall Controller.
The value of this register is dependent on the value of the Lockdown interface of the Firewall.
0 "0"
lock
Indicates the lock state of the Firewall Component.
0b00: Open lockdown state
0b01: Reserved and treated as 0b00
0b10: Partial lockdown state. When LDE.1 is implemented this value is Reserved and treated as 0b00.
0b11: Full lockdown state
0b0: No error
0b1: Error


fw_comp_pe_ctrl
Protection Extension Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810100
Address@host_sys_fw_comp_dbgperi : 0x1a820100
Address@host_sys_fw_comp_aonperi : 0x1a830100
Address@host_sys_fw_comp_envm : 0x1a840100
Address@host_sys_fw_comp_cvm : 0x1a850100
Address@host_sys_fw_comp_hostcpu : 0x1a860100
Address@host_sys_fw_comp_com : 0x1a870100
Address@host_sys_fw_comp_mot : 0x1a880100
Address@host_sys_fw_comp_hperi_slv : 0x1a890100
Address@host_sys_fw_comp_sms_slv : 0x1a8a0100
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0100
Address@host_sys_fw_comp_sms_mst : 0x1a8c0100
Address@host_sys_fw_comp_evm : 0x1a8d0100
Address@host_sys_fw_comp_debug : 0x1a8e0100
Address@secenc_fw_comp_fc1 : 0x50210100
Bits Reset value Name Description
31 "0"
en
Request the Firewall Components protection logic enables or disables.
0b0: Request the Firewall Components protection logic becomes disabled.
0b1: Request the Firewall Components protection logic becomes enabled.
The reset value of this field is 0b0 for all Firewall Components other than the Firewall
Controller which resets to 0b1.
30 - 6 0
-
 reserved
5 "0"
bypass_msk
Request Firewall Component behavior to Bypass interface.
0b0: Firewall Component uses the value of the Bypass interface to calculate whether it is bypassed or not.
0b1: Firewall Component ignores the value of the Bypass interface and treats the value as 0b0 to calculate whether it is bypassed or not.
4 "0"
fe_pwr
Request Fault Entry power behavior.
0b0: Fault Entry does not prevent entry into a Disconnected state.
0b1: Fault Entry does prevent entry into a Disconnected state.
3 - 2 "00"
flt_cfg
Requested Fault Configuration Configures the behavior of the Firewall Component when a transaction enters the Faulted state.
0b00: Reserved and treated as 10
0b01: Reserved and treated as 10
0b10: Terminate transaction, generate a fault entry and Access or Programming Error interrupt.
0b11: Terminate transaction, but no fault entry or Access or Programming Error interrupt are generated.
1 "0"
raz
Requested behavior for read data returned for read transactions terminated by the Firewall Component.
0b0: Read data is based on the StreamID
0b1: Read data all 0s
0 "0"
err
Requested behavior for responses for transactions terminated by the Firewall Component.
0b0: No error
0b1: Error


fw_comp_pe_st
Firewall Component Status Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810104
Address@host_sys_fw_comp_dbgperi : 0x1a820104
Address@host_sys_fw_comp_aonperi : 0x1a830104
Address@host_sys_fw_comp_envm : 0x1a840104
Address@host_sys_fw_comp_cvm : 0x1a850104
Address@host_sys_fw_comp_hostcpu : 0x1a860104
Address@host_sys_fw_comp_com : 0x1a870104
Address@host_sys_fw_comp_mot : 0x1a880104
Address@host_sys_fw_comp_hperi_slv : 0x1a890104
Address@host_sys_fw_comp_sms_slv : 0x1a8a0104
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0104
Address@host_sys_fw_comp_sms_mst : 0x1a8c0104
Address@host_sys_fw_comp_evm : 0x1a8d0104
Address@host_sys_fw_comp_debug : 0x1a8e0104
Address@secenc_fw_comp_fc1 : 0x50210104
Bits Name Description
31 en
Status of the Firewall Components protection logic.
0b0: Firewall Components protection logic is disabled.
0b1: Firewall Components protection logic is enabled.
When SRE.1 is implemented and the Firewall Component has entered the Disconnected state this field matches the value in PE_CTRL.EN.
As if the request to change from enabled to disabled or disabled to enabled has completed.
The reset value matches the reset value of PE_CTRL.EN.
30 - 6 -
 reserved
5 bypass_msk
Firewall Component behavior to Bypass interface.
0b0: Firewall Component uses the value of the Bypass interface to calculate whether it is bypassed or not.
0b1: Firewall Component ignores the value of the Bypass interface and treats the value as 0b0 to calculate whether it is bypassed or not.
4 fe_pwr
Fault Entry power behavior.
0b0: Fault Entry does not prevent entry into a Disconnected state.
0b1: Fault Entry does prevent entry into a Disconnected state.
3 - 2 flt_cfg
Fault Configuration
Behavior of the Firewall Component when a transaction enters the Faulted state.
0b00: Reserved
0b01: Reserved
0b10: Terminate transaction, generate a fault entry and Access or Programming Error interrupt.
0b11: Terminate transaction, but no fault entry or Access or Programming Error interrupt are generated.
1 raz
Value returned for read accesses when the Firewall Component terminates the transaction.
0b0: Read data is based on the StreamID
0b1: Read data is all 0s
0 err
Response for a transaction terminated by the Firewall Component.
0b0: No error
0b1: Error


fw_comp_pe_bps
Protection Extension Bypass Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810108
Address@host_sys_fw_comp_dbgperi : 0x1a820108
Address@host_sys_fw_comp_aonperi : 0x1a830108
Address@host_sys_fw_comp_envm : 0x1a840108
Address@host_sys_fw_comp_cvm : 0x1a850108
Address@host_sys_fw_comp_hostcpu : 0x1a860108
Address@host_sys_fw_comp_com : 0x1a870108
Address@host_sys_fw_comp_mot : 0x1a880108
Address@host_sys_fw_comp_hperi_slv : 0x1a890108
Address@host_sys_fw_comp_sms_slv : 0x1a8a0108
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0108
Address@host_sys_fw_comp_sms_mst : 0x1a8c0108
Address@host_sys_fw_comp_evm : 0x1a8d0108
Address@host_sys_fw_comp_debug : 0x1a8e0108
Address@secenc_fw_comp_fc1 : 0x50210108
Bits Reset value Name Description
31 "0"
bypass_vld
Indicates whether the values in the BYPASS_ST and BYPASS_IF_ST is valid or not.
0b0: Values are not valid
0b1: Values are valid
The behavior of this field depends the level of SRE implemented by the Firewall.
SRE.0: This field always reads as 0b1
SRE.1: This field reads as 0b1 only when the Firewall Component is in the Connected state. Otherwise this field reads as 0b0.
30 - 2 0
-
 reserved
1 "0"
bypass_st
Indicates if the Firewall Components protection logic is bypassed or not.
0b0: Firewall Components protection logic is not bypassed.
0b1: Firewall Components protection logic is bypassed.
0 "0"
bypass_if_st
Bypass interface status
The reset value of this field depends on the value of the Bypass interface of the Firewall Component.


fw_comp_rwe_ctrl
RWE Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a81010c
Address@host_sys_fw_comp_dbgperi : 0x1a82010c
Address@host_sys_fw_comp_aonperi : 0x1a83010c
Address@host_sys_fw_comp_envm : 0x1a84010c
Address@host_sys_fw_comp_cvm : 0x1a85010c
Address@host_sys_fw_comp_hostcpu : 0x1a86010c
Address@host_sys_fw_comp_com : 0x1a87010c
Address@host_sys_fw_comp_mot : 0x1a88010c
Address@host_sys_fw_comp_hperi_slv : 0x1a89010c
Address@host_sys_fw_comp_sms_slv : 0x1a8a010c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b010c
Address@host_sys_fw_comp_sms_mst : 0x1a8c010c
Address@host_sys_fw_comp_evm : 0x1a8d010c
Address@host_sys_fw_comp_debug : 0x1a8e010c
Address@secenc_fw_comp_fc1 : 0x5021010c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
rgn_indx
Region Index
Selects the region to which the RWE refers to.
The width of this field is dependent on the log2(FC_CFG1.NUM_RGN+1) rounded up to the nearest whole number. Any unused bits are Reserved and treated as RAZ/WI.


fw_comp_rgn_ctrl0
Region Control Register 0
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810110
Address@host_sys_fw_comp_dbgperi : 0x1a820110
Address@host_sys_fw_comp_aonperi : 0x1a830110
Address@host_sys_fw_comp_envm : 0x1a840110
Address@host_sys_fw_comp_cvm : 0x1a850110
Address@host_sys_fw_comp_hostcpu : 0x1a860110
Address@host_sys_fw_comp_com : 0x1a870110
Address@host_sys_fw_comp_mot : 0x1a880110
Address@host_sys_fw_comp_hperi_slv : 0x1a890110
Address@host_sys_fw_comp_sms_slv : 0x1a8a0110
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0110
Address@host_sys_fw_comp_sms_mst : 0x1a8c0110
Address@host_sys_fw_comp_evm : 0x1a8d0110
Address@host_sys_fw_comp_debug : 0x1a8e0110
Address@secenc_fw_comp_fc1 : 0x50210110
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Region enable
0b0: Request to disable the region
0b1: Request to enable the region


fw_comp_rgn_ctrl1
Region Control Register 1
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810114
Address@host_sys_fw_comp_dbgperi : 0x1a820114
Address@host_sys_fw_comp_aonperi : 0x1a830114
Address@host_sys_fw_comp_envm : 0x1a840114
Address@host_sys_fw_comp_cvm : 0x1a850114
Address@host_sys_fw_comp_hostcpu : 0x1a860114
Address@host_sys_fw_comp_com : 0x1a870114
Address@host_sys_fw_comp_mot : 0x1a880114
Address@host_sys_fw_comp_hperi_slv : 0x1a890114
Address@host_sys_fw_comp_sms_slv : 0x1a8a0114
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0114
Address@host_sys_fw_comp_sms_mst : 0x1a8c0114
Address@host_sys_fw_comp_evm : 0x1a8d0114
Address@host_sys_fw_comp_debug : 0x1a8e0114
Address@secenc_fw_comp_fc1 : 0x50210114
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
mpe3_en
Master enable for MPE3
0b0: Request to disable Master permission entry 3.
0b1: Request to enable Master permission entry 3.
Only implemented when FC_CFG2.NUM_MPE is 3. Otherwise this field is Reserved and treated as RAZ/WI.
3 "0"
mpe2_en
Master enable for MPE2
0b0: Request to disable Master permission entry 2.
0b0: Request to enable Master permission entry 2.
Only implemented when FC_CFG2.NUM_MPE is 2 or greater. Otherwise this field is Reserved and treated as RAZ/WI.
2 "0"
mpe1_en
Master enable for MPE1
0b0: Request to disable Master permission entry 1.
0b1: Request to enable Master permission entry 1.
Only implemented when FC_CFG2.NUM_MPE is 1 or greater. Otherwise this field is Reserved and treated as RAZ/WI.
1 "0"
mpe0_en
Master enable for MPE0
0b0: Request to disable Master permission entry. 0
0b1: Request to enable Master permission entry 0.
0 0
-
 reserved


fw_comp_rgn_lctrl
Region Lock Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810118
Address@host_sys_fw_comp_dbgperi : 0x1a820118
Address@host_sys_fw_comp_aonperi : 0x1a830118
Address@host_sys_fw_comp_envm : 0x1a840118
Address@host_sys_fw_comp_cvm : 0x1a850118
Address@host_sys_fw_comp_hostcpu : 0x1a860118
Address@host_sys_fw_comp_com : 0x1a870118
Address@host_sys_fw_comp_mot : 0x1a880118
Address@host_sys_fw_comp_hperi_slv : 0x1a890118
Address@host_sys_fw_comp_sms_slv : 0x1a8a0118
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0118
Address@host_sys_fw_comp_sms_mst : 0x1a8c0118
Address@host_sys_fw_comp_evm : 0x1a8d0118
Address@host_sys_fw_comp_debug : 0x1a8e0118
Address@secenc_fw_comp_fc1 : 0x50210118
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
lock
Control the lock status of the region.
0b0: Region is unlocked
0b1: Region is locked
When this field is 1 a configuration access which attempts to update any of the following fields:
- RGN_CTRL{0-1}
- RGN_CFG{0-1}
- RGN_SIZE
- RGN_TCFG{0-2}
- RGN_MID{0-3}
- RGN_MPL{0-3}
Generates:
- A Configuration Access Error
- A Tamper interrupt and Tamper report, if there is no valid Tamper report present. Otherwise, a Tamper Overflow interrupt is generated.
This field is Reserved and treated as RAZ/WI when LDE.0 or LDE.1 is implemented.
When any of the following occur:
- Firewall Components enter the Full lockdown state
- Firewall Components enter the Partial lockdown state and this field is set to 1
This field becomes RO and any attempt to update this field generates:
- A Configuration Access Error
- A Tamper interrupt and Tamper report, if there is no valid Tamper report present. Otherwise, a
Tamper Overflow interrupt is generated.


fw_comp_rgn_st
FRegion Status Register
R
Address@host_sys_fw_comp_sysperi : 0x1a81011c
Address@host_sys_fw_comp_dbgperi : 0x1a82011c
Address@host_sys_fw_comp_aonperi : 0x1a83011c
Address@host_sys_fw_comp_envm : 0x1a84011c
Address@host_sys_fw_comp_cvm : 0x1a85011c
Address@host_sys_fw_comp_hostcpu : 0x1a86011c
Address@host_sys_fw_comp_com : 0x1a87011c
Address@host_sys_fw_comp_mot : 0x1a88011c
Address@host_sys_fw_comp_hperi_slv : 0x1a89011c
Address@host_sys_fw_comp_sms_slv : 0x1a8a011c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b011c
Address@host_sys_fw_comp_sms_mst : 0x1a8c011c
Address@host_sys_fw_comp_evm : 0x1a8d011c
Address@host_sys_fw_comp_debug : 0x1a8e011c
Address@secenc_fw_comp_fc1 : 0x5021011c
Bits Name Description
31 - 5 -
 reserved
4 mpe3_en
Master enable for MPE3:
- 0b0: Master permission entry 3 is disabled.
- 0b1: Master permission entry 3 is enabled.
Only when a master permission entry is enabled is an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID3 and RGN_MPL3 are read-only and attempts to update the registers will generate a Configuration Access Error.
3 mpe2_en
Master enable for MPE2:
- 0b0: Master permission entry 2 is disabled.
- 0b1: Master permission entry 2 is enabled.
Only when a master permission entry is enabled will an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID2 and RGN_MPL2 are read-only and attempts to update the registers will generate a Configuration Access Error.
2 mpe1_en
Master enable for MPE1:
- 0b0: Master permission entry 1 is disabled.
- 0b1: Master permission entry 1 is enabled.
Only when a master permission entry is enabled will an incoming transaction be allowed to match against the entry.
When this field is 1, RGN_MID1 and RGN_MPL1 are read-only and attempts to update the registers will generate a Configuration Access Error.
1 en
Region enable:
- 0b0: Region disable
- 0b1: Region enable
When set to 1 the following registers are read-only:
- RGN_CFG0
- RGN_CFG1
- RGN_TCFG0
- RGN_TCFG1
- RGN_TCFG2
- RGN_SIZE
Any attempt to write to these registers, when the region is enabled, generates a Configuration Access Error.
0 -
 reserved


fw_comp_rgn_cfg0
Region Config Register 0
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810120
Address@host_sys_fw_comp_dbgperi : 0x1a820120
Address@host_sys_fw_comp_aonperi : 0x1a830120
Address@host_sys_fw_comp_envm : 0x1a840120
Address@host_sys_fw_comp_cvm : 0x1a850120
Address@host_sys_fw_comp_hostcpu : 0x1a860120
Address@host_sys_fw_comp_com : 0x1a870120
Address@host_sys_fw_comp_mot : 0x1a880120
Address@host_sys_fw_comp_hperi_slv : 0x1a890120
Address@host_sys_fw_comp_sms_slv : 0x1a8a0120
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0120
Address@host_sys_fw_comp_sms_mst : 0x1a8c0120
Address@host_sys_fw_comp_evm : 0x1a8d0120
Address@host_sys_fw_comp_debug : 0x1a8e0120
Address@secenc_fw_comp_fc1 : 0x50210120
Bits Reset value Name Description
31 - 5 0x0
base_addr
The lower 32 bits base address of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
Any unimplemented bits are Reserved and treated as RAZ/WI.
If MXRS and MNRS are equal, then all bits in this register are Reserved and treated as RAZ/WI.
4 - 0 0
-
 reserved


fw_comp_rgn_cfg1
Region Config Register 1
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810124
Address@host_sys_fw_comp_dbgperi : 0x1a820124
Address@host_sys_fw_comp_aonperi : 0x1a830124
Address@host_sys_fw_comp_envm : 0x1a840124
Address@host_sys_fw_comp_cvm : 0x1a850124
Address@host_sys_fw_comp_hostcpu : 0x1a860124
Address@host_sys_fw_comp_com : 0x1a870124
Address@host_sys_fw_comp_mot : 0x1a880124
Address@host_sys_fw_comp_hperi_slv : 0x1a890124
Address@host_sys_fw_comp_sms_slv : 0x1a8a0124
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0124
Address@host_sys_fw_comp_sms_mst : 0x1a8c0124
Address@host_sys_fw_comp_evm : 0x1a8d0124
Address@host_sys_fw_comp_debug : 0x1a8e0124
Address@secenc_fw_comp_fc1 : 0x50210124
Bits Reset value Name Description
31 - 0 0x0
base_addr
The upper 32 bits base address of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
Any unimplemented bits are Reserved and treated as RAZ/WI.
If MXRS and MNRS are equal, then all bits in this register are Reserved and treated as RAZ/WI.


fw_comp_rgn_size
Region Size Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810128
Address@host_sys_fw_comp_dbgperi : 0x1a820128
Address@host_sys_fw_comp_aonperi : 0x1a830128
Address@host_sys_fw_comp_envm : 0x1a840128
Address@host_sys_fw_comp_cvm : 0x1a850128
Address@host_sys_fw_comp_hostcpu : 0x1a860128
Address@host_sys_fw_comp_com : 0x1a870128
Address@host_sys_fw_comp_mot : 0x1a880128
Address@host_sys_fw_comp_hperi_slv : 0x1a890128
Address@host_sys_fw_comp_sms_slv : 0x1a8a0128
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0128
Address@host_sys_fw_comp_sms_mst : 0x1a8c0128
Address@host_sys_fw_comp_evm : 0x1a8d0128
Address@host_sys_fw_comp_debug : 0x1a8e0128
Address@secenc_fw_comp_fc1 : 0x50210128
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
mulnpo2
Selects whether the region is defined with a base address and size or a base and upper address.
0b0: Region defined by a base address and size, which must be a power of 2. The value of RGN_SIZE.SIZE is used.
0b1: Region defined by a base and upper address, which must both be an integer multiple of MNRS. The value of RGN_SIZE.SIZE is ignored.
This field is Reserved and treated as RAZ/WI when RSE.0 is implemented.
7 - 0 "00000000"
size
TThe size of the region.
0x00: 0B
0x05: 32B
0x06: 64B
-
0x0C: 4KB
0x0D: 8KB
-
0x40: 16KB
The legal values this field can be set to depend on the MNRS and MXRS of the Firewall Component. If software attempts to set this field to a value which is:
- Greater than 0x40
- Less than MNRS of the Firewall. Component
- Greater than MXRS of the Firewall Component
The field is set to 0x00 instead.
When this field reads as 0x00 does not match against any transactions.
The value of the RGN_SIZE field is only used if RGN_SIZE.MULnPO2 is 0.
Otherwise the field is ignored.


fw_comp_rgn_tcfg0
Region Translation Config Register 0
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810130
Address@host_sys_fw_comp_dbgperi : 0x1a820130
Address@host_sys_fw_comp_aonperi : 0x1a830130
Address@host_sys_fw_comp_envm : 0x1a840130
Address@host_sys_fw_comp_cvm : 0x1a850130
Address@host_sys_fw_comp_hostcpu : 0x1a860130
Address@host_sys_fw_comp_com : 0x1a870130
Address@host_sys_fw_comp_mot : 0x1a880130
Address@host_sys_fw_comp_hperi_slv : 0x1a890130
Address@host_sys_fw_comp_sms_slv : 0x1a8a0130
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0130
Address@host_sys_fw_comp_sms_mst : 0x1a8c0130
Address@host_sys_fw_comp_evm : 0x1a8d0130
Address@host_sys_fw_comp_debug : 0x1a8e0130
Address@secenc_fw_comp_fc1 : 0x50210130
Bits Reset value Name Description
31 - 5 0x0
output_addr
The output address or the upper address range of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
 Any unimplemented bits are Reserved and treated as RAZ/WI.
4 - 0 0
-
 reserved


fw_comp_rgn_tcfg1
Region Translation Config Register 1
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810134
Address@host_sys_fw_comp_dbgperi : 0x1a820134
Address@host_sys_fw_comp_aonperi : 0x1a830134
Address@host_sys_fw_comp_envm : 0x1a840134
Address@host_sys_fw_comp_cvm : 0x1a850134
Address@host_sys_fw_comp_hostcpu : 0x1a860134
Address@host_sys_fw_comp_com : 0x1a870134
Address@host_sys_fw_comp_mot : 0x1a880134
Address@host_sys_fw_comp_hperi_slv : 0x1a890134
Address@host_sys_fw_comp_sms_slv : 0x1a8a0134
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0134
Address@host_sys_fw_comp_sms_mst : 0x1a8c0134
Address@host_sys_fw_comp_evm : 0x1a8d0134
Address@host_sys_fw_comp_debug : 0x1a8e0134
Address@secenc_fw_comp_fc1 : 0x50210134
Bits Reset value Name Description
31 - 0 0x0
upper_addr
The output address or the upper address range of the region.
The width of this field depends on the MXRS and MNRS properties for the Firewall Component.
Number of bits implemented is log2(MXRS)-1 to log2(MNRS), starting at bit log2(MNRS).
 Any unimplemented bits are Reserved and treated as RAZ/WI.


fw_comp_rgn_tcfg2
Region Translation Config Register 2
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810138
Address@host_sys_fw_comp_dbgperi : 0x1a820138
Address@host_sys_fw_comp_aonperi : 0x1a830138
Address@host_sys_fw_comp_envm : 0x1a840138
Address@host_sys_fw_comp_cvm : 0x1a850138
Address@host_sys_fw_comp_hostcpu : 0x1a860138
Address@host_sys_fw_comp_com : 0x1a870138
Address@host_sys_fw_comp_mot : 0x1a880138
Address@host_sys_fw_comp_hperi_slv : 0x1a890138
Address@host_sys_fw_comp_sms_slv : 0x1a8a0138
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0138
Address@host_sys_fw_comp_sms_mst : 0x1a8c0138
Address@host_sys_fw_comp_evm : 0x1a8d0138
Address@host_sys_fw_comp_debug : 0x1a8e0138
Address@secenc_fw_comp_fc1 : 0x50210138
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
addr_trans_en
Address Translation enable:
0b0: Address translation is disabled. The output transaction has the same address as the incoming transaction.
0b1: Address translation is enabled.
This field is Reserved and treated as RAZ/WI when:
- TE.1 or lower is implemented
- PE.2 is implemented for the Default Region
- Regions 0-2 for Firewall Controller
16 "0"
ma_trans_en
Memory Attribute Translation enable
0b0: Memory attribute translation is disabled. The output transaction has the same memory attribute as the incoming transaction.
0b1: Memory attribute translation is enabled. The output transactions memory attribute is as defined in RGN_TCG2.MA.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.MA_SPT is 0b0
- TE.0 is implemented
15 - 14 "00"
instr
Output transaction instruction or data:
0b00: Use incoming transaction value.
0b01: Reserved and treated as 00.
0b10: Data
0b11: Instruction
This field only affects read transactions.
All write transactions are considered as data and outgoing write transactions are outputted as data access.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.INST_SPT is 0b0
- TE.0 is implemented
13 - 12 "00"
priv
Output transaction privileged level
0b00: Use incoming privileged level.
0b01:Reserved and treated as 00.
0b10: Unprivileged
0b11: Privileged
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.PRIV_SPT is 0b0
- TE.0 is implemented
11 - 4 "00000000"
ma
Output transaction memory attribute
Defines the memory type, cache allocation policy and whether it is transient or not for the output transaction.
This field is Reserved and treated as RAZ/WI when either:
- FC_CFG1.MA_SPT is 0b0
- TE.0 is implemented
3 - 2 "00"
sh
Output transaction shareability.
0b00: Non-shareable.
0b01: Use incoming shareability.
0b10: Outer shareable.
0b11: Inner shareable.
This field is Reserved and treated as WI and as reads as 0b01, when either:
FC_CFG1.SH_SPT is 0.
or TE.0 is implemented.
1 - 0 "00"
ns
Output transaction security
0b00: Output transaction is marked with the same security as incoming transaction.
0b01: Reserved and treated as 0b00.
0b10: Output transaction is marked as Secure.
0b11: Output transaction is marked as Non-secure.
This only applies if the incoming transaction was Secure.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0b0
- TE.0 is implemented


fw_comp_rgn_mid0
Region MasterID Register 0
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810140
Address@host_sys_fw_comp_dbgperi : 0x1a820140
Address@host_sys_fw_comp_aonperi : 0x1a830140
Address@host_sys_fw_comp_envm : 0x1a840140
Address@host_sys_fw_comp_cvm : 0x1a850140
Address@host_sys_fw_comp_hostcpu : 0x1a860140
Address@host_sys_fw_comp_com : 0x1a870140
Address@host_sys_fw_comp_mot : 0x1a880140
Address@host_sys_fw_comp_hperi_slv : 0x1a890140
Address@host_sys_fw_comp_sms_slv : 0x1a8a0140
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0140
Address@host_sys_fw_comp_sms_mst : 0x1a8c0140
Address@host_sys_fw_comp_evm : 0x1a8d0140
Address@host_sys_fw_comp_debug : 0x1a8e0140
Address@secenc_fw_comp_fc1 : 0x50210140
Bits Reset value Name Description
31 - 0 0x0
mst_id
MasterID. The value of the MasterID part of the StreamID which the transaction must have to match this MPE.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.
This field is read-only when FC_CFG2.SINGLE_MST is 0b1.


fw_comp_rgn_mpl0
Region Master Permission List Register 0
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810144
Address@host_sys_fw_comp_dbgperi : 0x1a820144
Address@host_sys_fw_comp_aonperi : 0x1a830144
Address@host_sys_fw_comp_envm : 0x1a840144
Address@host_sys_fw_comp_cvm : 0x1a850144
Address@host_sys_fw_comp_hostcpu : 0x1a860144
Address@host_sys_fw_comp_com : 0x1a870144
Address@host_sys_fw_comp_mot : 0x1a880144
Address@host_sys_fw_comp_hperi_slv : 0x1a890144
Address@host_sys_fw_comp_sms_slv : 0x1a8a0144
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0144
Address@host_sys_fw_comp_sms_mst : 0x1a8c0144
Address@host_sys_fw_comp_evm : 0x1a8d0144
Address@host_sys_fw_comp_debug : 0x1a8e0144
Address@secenc_fw_comp_fc1 : 0x50210144
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
any_mst
Selects whether entry is used for all transactions, irrespective of MasterID.
0b0: MPE only used if MasterID of transaction and MPE match
0b1: MPE used irrespective of transaction MasterID
This field is read-only when FC_CFG2.SINGLE_MST is 1.
This field is Reserved and treated as RAZ/WI for RGN_MPL{1-3}.
11 "0"
spx
Secure privilege execute enable
0b0: Secure privileged instruction fetches are not allowed.
0b1: Secure privileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
- FC_CFG1.INST_SPT is 0
10 "0"
spw
Secure privilege write enable
0b0: Secure privileged data write operations are not allowed.
0b1: Secure privileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
9 "0"
spr
Secure privilege read enable
0b0: Secure privileged data read operations are not allowed.
0b1: Secure privileged data read operations are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.PRIV_SPT is 0
8 "0"
sux
Secure unprivileged execute enable
0b0: Secure unprivileged instruction fetches are not allowed.
0b1: Secure unprivileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.SEC_SPT is 0
- FC_CFG1.INST_SPT is 0
7 "0"
suw
Secure unprivileged write enable
0b0: Secure unprivileged data write operations are not allowed.
0b1: Secure unprivileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when
FC_CFG1.SEC_SPT is 0.
6 "0"
sur
Secure unprivileged read enable
0b0: Secure unprivileged data read operations are not allowed.
0b1: Secure unprivileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when
FC_CFG1.SEC_SPT is 0.
5 "0"
nspx
Non-secure privilege execute enable
0b0: Non-secure privileged instruction fetches are not allowed.
0b1: Non-secure privileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when any of the following are true:
- FC_CFG1.PRIV_SPT is 0
- FC_CFG1.INST_SPT is 0
4 "0"
nspw
Non-secure privilege write enable
0b0: Non-secure privileged data write operations are not allowed.
0b1: Non-secure privileged data write operations are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.PRIV_SPT is 0.
3 "0"
nspr
Non-secure privilege read enable
0b0: Non-secure privileged data read operations are not allowed.
0b1: Non-secure privileged data read operations are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.PRIV_SPT is 0.
2 "0"
nsux
Non-secure unprivileged execute enable
0b0: Non-secure unprivileged instruction fetches are not allowed.
0b1: Non-secure unprivileged instruction fetches are allowed.
This field is Reserved and treated as RAZ/WI when FC_CFG1.INST_SPT is 0.
1 "0"
nsuw
Non-secure unprivileged write enable
0b0: Non-secure unprivileged data write operations are not allowed.
0b1: Non-secure unprivileged data write operations are allowed
0 "0"
nsur
Non-secure unprivileged read enable
0b0: Non-secure unprivileged data read operations are not allowed.
0b1: Non-secure unprivileged data read operations are allowed.


fw_comp_rgn_mid1
Region MasterID Register 1
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810148
Address@host_sys_fw_comp_dbgperi : 0x1a820148
Address@host_sys_fw_comp_aonperi : 0x1a830148
Address@host_sys_fw_comp_envm : 0x1a840148
Address@host_sys_fw_comp_cvm : 0x1a850148
Address@host_sys_fw_comp_hostcpu : 0x1a860148
Address@host_sys_fw_comp_com : 0x1a870148
Address@host_sys_fw_comp_mot : 0x1a880148
Address@host_sys_fw_comp_hperi_slv : 0x1a890148
Address@host_sys_fw_comp_sms_slv : 0x1a8a0148
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0148
Address@host_sys_fw_comp_sms_mst : 0x1a8c0148
Address@host_sys_fw_comp_evm : 0x1a8d0148
Address@host_sys_fw_comp_debug : 0x1a8e0148
Address@secenc_fw_comp_fc1 : 0x50210148
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mid1


fw_comp_rgn_mpl1
Region Master Permission List Register 1
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a81014c
Address@host_sys_fw_comp_dbgperi : 0x1a82014c
Address@host_sys_fw_comp_aonperi : 0x1a83014c
Address@host_sys_fw_comp_envm : 0x1a84014c
Address@host_sys_fw_comp_cvm : 0x1a85014c
Address@host_sys_fw_comp_hostcpu : 0x1a86014c
Address@host_sys_fw_comp_com : 0x1a87014c
Address@host_sys_fw_comp_mot : 0x1a88014c
Address@host_sys_fw_comp_hperi_slv : 0x1a89014c
Address@host_sys_fw_comp_sms_slv : 0x1a8a014c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b014c
Address@host_sys_fw_comp_sms_mst : 0x1a8c014c
Address@host_sys_fw_comp_evm : 0x1a8d014c
Address@host_sys_fw_comp_debug : 0x1a8e014c
Address@secenc_fw_comp_fc1 : 0x5021014c
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mpl1


fw_comp_rgn_mid2
Region MasterID Register 2
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810150
Address@host_sys_fw_comp_dbgperi : 0x1a820150
Address@host_sys_fw_comp_aonperi : 0x1a830150
Address@host_sys_fw_comp_envm : 0x1a840150
Address@host_sys_fw_comp_cvm : 0x1a850150
Address@host_sys_fw_comp_hostcpu : 0x1a860150
Address@host_sys_fw_comp_com : 0x1a870150
Address@host_sys_fw_comp_mot : 0x1a880150
Address@host_sys_fw_comp_hperi_slv : 0x1a890150
Address@host_sys_fw_comp_sms_slv : 0x1a8a0150
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0150
Address@host_sys_fw_comp_sms_mst : 0x1a8c0150
Address@host_sys_fw_comp_evm : 0x1a8d0150
Address@host_sys_fw_comp_debug : 0x1a8e0150
Address@secenc_fw_comp_fc1 : 0x50210150
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mid2


fw_comp_rgn_mpl2
Region Master Permission List Register 2
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810154
Address@host_sys_fw_comp_dbgperi : 0x1a820154
Address@host_sys_fw_comp_aonperi : 0x1a830154
Address@host_sys_fw_comp_envm : 0x1a840154
Address@host_sys_fw_comp_cvm : 0x1a850154
Address@host_sys_fw_comp_hostcpu : 0x1a860154
Address@host_sys_fw_comp_com : 0x1a870154
Address@host_sys_fw_comp_mot : 0x1a880154
Address@host_sys_fw_comp_hperi_slv : 0x1a890154
Address@host_sys_fw_comp_sms_slv : 0x1a8a0154
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0154
Address@host_sys_fw_comp_sms_mst : 0x1a8c0154
Address@host_sys_fw_comp_evm : 0x1a8d0154
Address@host_sys_fw_comp_debug : 0x1a8e0154
Address@secenc_fw_comp_fc1 : 0x50210154
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mpl2


fw_comp_rgn_mid3
Region MasterID Register 3
For detailed information refer to 'rgn_mid0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810158
Address@host_sys_fw_comp_dbgperi : 0x1a820158
Address@host_sys_fw_comp_aonperi : 0x1a830158
Address@host_sys_fw_comp_envm : 0x1a840158
Address@host_sys_fw_comp_cvm : 0x1a850158
Address@host_sys_fw_comp_hostcpu : 0x1a860158
Address@host_sys_fw_comp_com : 0x1a870158
Address@host_sys_fw_comp_mot : 0x1a880158
Address@host_sys_fw_comp_hperi_slv : 0x1a890158
Address@host_sys_fw_comp_sms_slv : 0x1a8a0158
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0158
Address@host_sys_fw_comp_sms_mst : 0x1a8c0158
Address@host_sys_fw_comp_evm : 0x1a8d0158
Address@host_sys_fw_comp_debug : 0x1a8e0158
Address@secenc_fw_comp_fc1 : 0x50210158
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mid3


fw_comp_rgn_mpl3
Region Master Permission List Register 3
For detailed information refer to 'rgn_mpl0' register description.
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a81015c
Address@host_sys_fw_comp_dbgperi : 0x1a82015c
Address@host_sys_fw_comp_aonperi : 0x1a83015c
Address@host_sys_fw_comp_envm : 0x1a84015c
Address@host_sys_fw_comp_cvm : 0x1a85015c
Address@host_sys_fw_comp_hostcpu : 0x1a86015c
Address@host_sys_fw_comp_com : 0x1a87015c
Address@host_sys_fw_comp_mot : 0x1a88015c
Address@host_sys_fw_comp_hperi_slv : 0x1a89015c
Address@host_sys_fw_comp_sms_slv : 0x1a8a015c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b015c
Address@host_sys_fw_comp_sms_mst : 0x1a8c015c
Address@host_sys_fw_comp_evm : 0x1a8d015c
Address@host_sys_fw_comp_debug : 0x1a8e015c
Address@secenc_fw_comp_fc1 : 0x5021015c
Bits Reset value Name Description
31 - 0 0
fw_comp_rgn_mpl3


fw_comp_fe_tal
Fault Entry Transaction Address Lower Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810180
Address@host_sys_fw_comp_dbgperi : 0x1a820180
Address@host_sys_fw_comp_aonperi : 0x1a830180
Address@host_sys_fw_comp_envm : 0x1a840180
Address@host_sys_fw_comp_cvm : 0x1a850180
Address@host_sys_fw_comp_hostcpu : 0x1a860180
Address@host_sys_fw_comp_com : 0x1a870180
Address@host_sys_fw_comp_mot : 0x1a880180
Address@host_sys_fw_comp_hperi_slv : 0x1a890180
Address@host_sys_fw_comp_sms_slv : 0x1a8a0180
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0180
Address@host_sys_fw_comp_sms_mst : 0x1a8c0180
Address@host_sys_fw_comp_evm : 0x1a8d0180
Address@host_sys_fw_comp_debug : 0x1a8e0180
Address@secenc_fw_comp_fc1 : 0x50210180
Bits Name Description
31 - 0 fault_addr_lwr
Fault transaction address lower.
This field is RAZ when FE_CTRL.FE_VLD is 0.


fw_comp_fe_tau
Fault Entry Transaction Address Upper Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810184
Address@host_sys_fw_comp_dbgperi : 0x1a820184
Address@host_sys_fw_comp_aonperi : 0x1a830184
Address@host_sys_fw_comp_envm : 0x1a840184
Address@host_sys_fw_comp_cvm : 0x1a850184
Address@host_sys_fw_comp_hostcpu : 0x1a860184
Address@host_sys_fw_comp_com : 0x1a870184
Address@host_sys_fw_comp_mot : 0x1a880184
Address@host_sys_fw_comp_hperi_slv : 0x1a890184
Address@host_sys_fw_comp_sms_slv : 0x1a8a0184
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0184
Address@host_sys_fw_comp_sms_mst : 0x1a8c0184
Address@host_sys_fw_comp_evm : 0x1a8d0184
Address@host_sys_fw_comp_debug : 0x1a8e0184
Address@secenc_fw_comp_fc1 : 0x50210184
Bits Name Description
31 - 0 fault_addr_upr
Fault transaction address upper.
This field is RAZ when FE_CTRL.FE_VLD is 0.


fw_comp_fe_tp
Fault Entry Transaction Properties Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810188
Address@host_sys_fw_comp_dbgperi : 0x1a820188
Address@host_sys_fw_comp_aonperi : 0x1a830188
Address@host_sys_fw_comp_envm : 0x1a840188
Address@host_sys_fw_comp_cvm : 0x1a850188
Address@host_sys_fw_comp_hostcpu : 0x1a860188
Address@host_sys_fw_comp_com : 0x1a870188
Address@host_sys_fw_comp_mot : 0x1a880188
Address@host_sys_fw_comp_hperi_slv : 0x1a890188
Address@host_sys_fw_comp_sms_slv : 0x1a8a0188
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0188
Address@host_sys_fw_comp_sms_mst : 0x1a8c0188
Address@host_sys_fw_comp_evm : 0x1a8d0188
Address@host_sys_fw_comp_debug : 0x1a8e0188
Address@secenc_fw_comp_fc1 : 0x50210188
Bits Name Description
31 - 22 -
 reserved
21 w
Indicates whether the transaction was a read or write:
0b0: Read
0b1: Write
20 - 19 -
 reserved
18 instr
Indicates whether the transaction was an instruction or data access:
0b0: Data
0b1: Instruction
17 priv
Indicates the privileged level of the transaction:
0b0: Unprivileged
0b1: Privileged
16 ns
Indicates the security level of the transaction:
0b0: Secure
0b1: Non-secure
When SE.0 is implemented this field is Reserved and is treated as RAO/WI.
15 - 0 -
 reserved


fw_comp_fe_mid
Fault Entry MasterID Register
R
Address@host_sys_fw_comp_sysperi : 0x1a81018c
Address@host_sys_fw_comp_dbgperi : 0x1a82018c
Address@host_sys_fw_comp_aonperi : 0x1a83018c
Address@host_sys_fw_comp_envm : 0x1a84018c
Address@host_sys_fw_comp_cvm : 0x1a85018c
Address@host_sys_fw_comp_hostcpu : 0x1a86018c
Address@host_sys_fw_comp_com : 0x1a87018c
Address@host_sys_fw_comp_mot : 0x1a88018c
Address@host_sys_fw_comp_hperi_slv : 0x1a89018c
Address@host_sys_fw_comp_sms_slv : 0x1a8a018c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b018c
Address@host_sys_fw_comp_sms_mst : 0x1a8c018c
Address@host_sys_fw_comp_evm : 0x1a8d018c
Address@host_sys_fw_comp_debug : 0x1a8e018c
Address@secenc_fw_comp_fc1 : 0x5021018c
Bits Name Description
31 - 0 mst_id
The reset value of this field depends on the value of FC_CFG2.SINGLE_MST:
Indicates the MasterID of the master which issued the transaction.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.


fw_comp_fe_ctrl
Fault Entry Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810190
Address@host_sys_fw_comp_dbgperi : 0x1a820190
Address@host_sys_fw_comp_aonperi : 0x1a830190
Address@host_sys_fw_comp_envm : 0x1a840190
Address@host_sys_fw_comp_cvm : 0x1a850190
Address@host_sys_fw_comp_hostcpu : 0x1a860190
Address@host_sys_fw_comp_com : 0x1a870190
Address@host_sys_fw_comp_mot : 0x1a880190
Address@host_sys_fw_comp_hperi_slv : 0x1a890190
Address@host_sys_fw_comp_sms_slv : 0x1a8a0190
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0190
Address@host_sys_fw_comp_sms_mst : 0x1a8c0190
Address@host_sys_fw_comp_evm : 0x1a8d0190
Address@host_sys_fw_comp_debug : 0x1a8e0190
Address@secenc_fw_comp_fc1 : 0x50210190
Bits Reset value Name Description
31 "0"
last_fe
Indicates if this fault entry is the last valid entry:
0b0: Entry is the not last valid fault entry.
0b1: Entry is the last valid fault entry.
30 "0"
fe_vld
Indicates whether the FWE is pointing to a valid fault entry:
0b0: FWE is pointing to an invalid fault entry.
0b1: FWE is pointing to a valid fault entry.
When this field is 0b0 the following fields, in the FWE, read as 0x0:
- FE_TAL
- FE_TAU
- FE_TP
- FE_MID
- FE_CTRL.FLT_TYPE
29 - 4 0
-
 reserved
3 "0"
flt_type
Indicates the fault type:
0b0: Transaction fault
0b1: Programming fault
2 - 1 0
-
 reserved
0 "0"
ack
Acknowledge the transaction. This field always reads as 0b0.
Writes to this field behave as follows:
0b0: Ignored
0b1: Fault transaction is acknowledged
Writes to this register are ignored if FE_CTRL.FE_VLD is 0b0.


fw_comp_me_ctrl
Monitor Extension Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810200
Address@host_sys_fw_comp_dbgperi : 0x1a820200
Address@host_sys_fw_comp_aonperi : 0x1a830200
Address@host_sys_fw_comp_envm : 0x1a840200
Address@host_sys_fw_comp_cvm : 0x1a850200
Address@host_sys_fw_comp_hostcpu : 0x1a860200
Address@host_sys_fw_comp_com : 0x1a870200
Address@host_sys_fw_comp_mot : 0x1a880200
Address@host_sys_fw_comp_hperi_slv : 0x1a890200
Address@host_sys_fw_comp_sms_slv : 0x1a8a0200
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0200
Address@host_sys_fw_comp_sms_mst : 0x1a8c0200
Address@host_sys_fw_comp_evm : 0x1a8d0200
Address@host_sys_fw_comp_debug : 0x1a8e0200
Address@secenc_fw_comp_fc1 : 0x50210200
Bits Reset value Name Description
31 "0"
en
Request the Firewall Components monitor logic enables or disables.
0b0: Request to disable the Firewall Components monitor logic
0b1: Request to enable the Firewall Components monitor logic
30 - 5 0
-
 reserved
4 "0"
edr_pwr
Request error detection reports power behavior.
0b0: Error detection report does not prevent entry into a Disconnected state
0b1: Error detection report does prevent entry into a Disconnected state
3 - 2 0
-
 reserved
1 "0"
rdum
Request behavior for read data returned for a read transaction which has caused an error.
0b0: Read data is based on the StreamID
0b1: Read data is left unmodified
0 0
-
 reserved


fw_comp_me_st
Monitor Extension Status Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810204
Address@host_sys_fw_comp_dbgperi : 0x1a820204
Address@host_sys_fw_comp_aonperi : 0x1a830204
Address@host_sys_fw_comp_envm : 0x1a840204
Address@host_sys_fw_comp_cvm : 0x1a850204
Address@host_sys_fw_comp_hostcpu : 0x1a860204
Address@host_sys_fw_comp_com : 0x1a870204
Address@host_sys_fw_comp_mot : 0x1a880204
Address@host_sys_fw_comp_hperi_slv : 0x1a890204
Address@host_sys_fw_comp_sms_slv : 0x1a8a0204
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0204
Address@host_sys_fw_comp_sms_mst : 0x1a8c0204
Address@host_sys_fw_comp_evm : 0x1a8d0204
Address@host_sys_fw_comp_debug : 0x1a8e0204
Address@secenc_fw_comp_fc1 : 0x50210204
Bits Name Description
31 en
Status of the Firewall Components monitor logic enables or disables.
0b0: Firewall Components monitor logic is disabled.
0b1: Firewall Components monitor logic is enabled.
When SRE.1 is implemented and the Firewall Component has entered the Disconnected state this field matches the value in ME_CTRL.EN.
As if the request to change from enabled to disable or disabled to enabled has completed.
30 - 5 -
 reserved
4 edr_pwr
Error detection reports power behavior.
0b0: Error detection report does not prevent entry into a Disconnected state.
0b1: Error detection report does prevent entry into a Disconnected state.
3 - 2 -
 reserved
1 rdum
Request behavior for read data returned for a read transaction which has caused an error.
0b0: Read data is based on the StreamID
0b1: Read data is left unmodified
0 -
 reserved


fw_comp_edr_tal
Error Detection Report Transaction Address Lower Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810260
Address@host_sys_fw_comp_dbgperi : 0x1a820260
Address@host_sys_fw_comp_aonperi : 0x1a830260
Address@host_sys_fw_comp_envm : 0x1a840260
Address@host_sys_fw_comp_cvm : 0x1a850260
Address@host_sys_fw_comp_hostcpu : 0x1a860260
Address@host_sys_fw_comp_com : 0x1a870260
Address@host_sys_fw_comp_mot : 0x1a880260
Address@host_sys_fw_comp_hperi_slv : 0x1a890260
Address@host_sys_fw_comp_sms_slv : 0x1a8a0260
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0260
Address@host_sys_fw_comp_sms_mst : 0x1a8c0260
Address@host_sys_fw_comp_evm : 0x1a8d0260
Address@host_sys_fw_comp_debug : 0x1a8e0260
Address@secenc_fw_comp_fc1 : 0x50210260
Bits Name Description
31 - 0 error_addr_lwr
Error transaction address lower.
This field is RAZ when EDR_CTRL.EDR_VLD is 0.


fw_comp_edr_tau
Error Detection Report Transaction Address Upper Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810264
Address@host_sys_fw_comp_dbgperi : 0x1a820264
Address@host_sys_fw_comp_aonperi : 0x1a830264
Address@host_sys_fw_comp_envm : 0x1a840264
Address@host_sys_fw_comp_cvm : 0x1a850264
Address@host_sys_fw_comp_hostcpu : 0x1a860264
Address@host_sys_fw_comp_com : 0x1a870264
Address@host_sys_fw_comp_mot : 0x1a880264
Address@host_sys_fw_comp_hperi_slv : 0x1a890264
Address@host_sys_fw_comp_sms_slv : 0x1a8a0264
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0264
Address@host_sys_fw_comp_sms_mst : 0x1a8c0264
Address@host_sys_fw_comp_evm : 0x1a8d0264
Address@host_sys_fw_comp_debug : 0x1a8e0264
Address@secenc_fw_comp_fc1 : 0x50210264
Bits Name Description
31 - 0 error_addr_upr
Error transaction address upper.
This field is RAZ when EDR_CTRL.EDR_VLD is 0.


fw_comp_edr_tp
Error Detection Transaction Properties Register
R
Address@host_sys_fw_comp_sysperi : 0x1a810268
Address@host_sys_fw_comp_dbgperi : 0x1a820268
Address@host_sys_fw_comp_aonperi : 0x1a830268
Address@host_sys_fw_comp_envm : 0x1a840268
Address@host_sys_fw_comp_cvm : 0x1a850268
Address@host_sys_fw_comp_hostcpu : 0x1a860268
Address@host_sys_fw_comp_com : 0x1a870268
Address@host_sys_fw_comp_mot : 0x1a880268
Address@host_sys_fw_comp_hperi_slv : 0x1a890268
Address@host_sys_fw_comp_sms_slv : 0x1a8a0268
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0268
Address@host_sys_fw_comp_sms_mst : 0x1a8c0268
Address@host_sys_fw_comp_evm : 0x1a8d0268
Address@host_sys_fw_comp_debug : 0x1a8e0268
Address@secenc_fw_comp_fc1 : 0x50210268
Bits Name Description
31 - 22 -
 reserved
21 w
Indicates whether the transaction, which caused the error, was a read or write.
0b0: Read
0b1: Write
20 - 19 -
 reserved
18 instr
Indicates whether the transaction, which caused the error, was an instruction or data access.
0b0: Data
0b1: Instruction
17 priv
Indicates the privileged level of the transaction, which caused the error.
0b0: Unprivileged.
0b1: Privileged.
16 ns
Indicates the security level of the transaction.
0b0: Secure
0b1: Non-secure
15 - 0 -
 reserved


fw_comp_edr_mid
Error Detection Report MasterID Register
R
Address@host_sys_fw_comp_sysperi : 0x1a81026c
Address@host_sys_fw_comp_dbgperi : 0x1a82026c
Address@host_sys_fw_comp_aonperi : 0x1a83026c
Address@host_sys_fw_comp_envm : 0x1a84026c
Address@host_sys_fw_comp_cvm : 0x1a85026c
Address@host_sys_fw_comp_hostcpu : 0x1a86026c
Address@host_sys_fw_comp_com : 0x1a87026c
Address@host_sys_fw_comp_mot : 0x1a88026c
Address@host_sys_fw_comp_hperi_slv : 0x1a89026c
Address@host_sys_fw_comp_sms_slv : 0x1a8a026c
Address@host_sys_fw_comp_hperi_mst : 0x1a8b026c
Address@host_sys_fw_comp_sms_mst : 0x1a8c026c
Address@host_sys_fw_comp_evm : 0x1a8d026c
Address@host_sys_fw_comp_debug : 0x1a8e026c
Address@secenc_fw_comp_fc1 : 0x5021026c
Bits Name Description
31 - 0 mst_id
Indicates the MasterID of the transaction which caused the error.
The width of this field depends on the value of FC_CFG2.MST_ID_WIDTH.
Any unused bits are Reserved and treated as RAZ/WI.


fw_comp_edr_ctrl
Error Detection Report Control Register
R/W
0x00000000
Address@host_sys_fw_comp_sysperi : 0x1a810270
Address@host_sys_fw_comp_dbgperi : 0x1a820270
Address@host_sys_fw_comp_aonperi : 0x1a830270
Address@host_sys_fw_comp_envm : 0x1a840270
Address@host_sys_fw_comp_cvm : 0x1a850270
Address@host_sys_fw_comp_hostcpu : 0x1a860270
Address@host_sys_fw_comp_com : 0x1a870270
Address@host_sys_fw_comp_mot : 0x1a880270
Address@host_sys_fw_comp_hperi_slv : 0x1a890270
Address@host_sys_fw_comp_sms_slv : 0x1a8a0270
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0270
Address@host_sys_fw_comp_sms_mst : 0x1a8c0270
Address@host_sys_fw_comp_evm : 0x1a8d0270
Address@host_sys_fw_comp_debug : 0x1a8e0270
Address@secenc_fw_comp_fc1 : 0x50210270
Bits Reset value Name Description
31 "0"
last_edr
Indicates if this error detection entry is the last valid entry.
0b0: Report is not the last valid error detection report.
0b1: Report is the last valid error detection report.
30 "0"
edr_vld
Indicates whether the EDW is pointing to a valid error detection report.
0b0: EDW is pointing to an invalid error detection report.
0b1: EDW is pointing to a valid error detection report.
When this field is 0b0 the values in the following registers read as 0:
- EDR_TAL
- EDR_TAU
- EDR_TP
- EDR_MID
29 - 1 0
-
 reserved
0 "0"
ack
Acknowledge the error transaction.
This field always reads as 0b0.
Writes to this field behave as follows:
0b0: Ignored
0b1: Error detection report is acknowledged.
Writes to this register are ignored if EDR_CTRL.EDR_VLD is 0b0.


fw_comp_fc_cap0
Firewall Component Capability Register 0
R
Address@host_sys_fw_comp_sysperi : 0x1a810fa0
Address@host_sys_fw_comp_dbgperi : 0x1a820fa0
Address@host_sys_fw_comp_aonperi : 0x1a830fa0
Address@host_sys_fw_comp_envm : 0x1a840fa0
Address@host_sys_fw_comp_cvm : 0x1a850fa0
Address@host_sys_fw_comp_hostcpu : 0x1a860fa0
Address@host_sys_fw_comp_com : 0x1a870fa0
Address@host_sys_fw_comp_mot : 0x1a880fa0
Address@host_sys_fw_comp_hperi_slv : 0x1a890fa0
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa0
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa0
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa0
Address@host_sys_fw_comp_evm : 0x1a8d0fa0
Address@host_sys_fw_comp_debug : 0x1a8e0fa0
Address@secenc_fw_comp_fc1 : 0x50210fa0
Bits Name Description
31 - 28 -
 reserved
27 - 24 se_lvl
Level of the Security Extension used by the Firewall.
0x0: SE.0 is implemented
0x1: SE.1 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
23 - 20 sre_lvl
Level of the Save and Restore Extension used by the Firewall.
0x0: SRE.0 is implemented
0x1: SRE.1 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
19 - 16 lde_lvl
Level of the Lockdown Extension implemented by the Firewall.
0x0: LDE.0 is implemented
0x1: LDE.1 is implemented
0x2: LDE.2 is implemented
All other values are Reserved.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.
15 - 12 te_lvl
Level of the Translation Extension implemented by Firewall Component.
0x0: TE.0 is implemented
0x1: TE.1 is implemented
0x2: TE.2 is implemented
All other values are Reserved.
This field must always be 0x0 when the FC_CAP0.PE_LVL is 0x0.
11 - 8 rse_lvl
Level of the Region Size Extension implemented by Firewall Component.
0x0: RSE.0 is implemented
0x1: RSE.1 is implemented
All other values are Reserved.
This field must always be 0x0 when the FC_CAP0.PE_LVL is 0x0.
7 - 4 me_lvl
Level of the Monitor Extension implemented by the Firewall Component.
0x0: TE.0 is implemented
0x1: TE.1 is implemented
All other values are Reserved.
3 - 0 pe_lvl
Level of the Protection Extension implemented by the Firewall Component.
0x0: PE.0 is implemented
0x1: PE.1 is implemented
0x2: PE.2 is implemented
All other values are Reserved.


fw_comp_fc_cap1
Firewall Component Capability Register 1
R
Address@host_sys_fw_comp_sysperi : 0x1a810fa4
Address@host_sys_fw_comp_dbgperi : 0x1a820fa4
Address@host_sys_fw_comp_aonperi : 0x1a830fa4
Address@host_sys_fw_comp_envm : 0x1a840fa4
Address@host_sys_fw_comp_cvm : 0x1a850fa4
Address@host_sys_fw_comp_hostcpu : 0x1a860fa4
Address@host_sys_fw_comp_com : 0x1a870fa4
Address@host_sys_fw_comp_mot : 0x1a880fa4
Address@host_sys_fw_comp_hperi_slv : 0x1a890fa4
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa4
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa4
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa4
Address@host_sys_fw_comp_evm : 0x1a8d0fa4
Address@host_sys_fw_comp_debug : 0x1a8e0fa4
Address@secenc_fw_comp_fc1 : 0x50210fa4
Bits Name Description
31 - 0 fw_comp_fc_cap1


fw_comp_fc_cap2
Firewall Component Capability Register 2
R
Address@host_sys_fw_comp_sysperi : 0x1a810fa8
Address@host_sys_fw_comp_dbgperi : 0x1a820fa8
Address@host_sys_fw_comp_aonperi : 0x1a830fa8
Address@host_sys_fw_comp_envm : 0x1a840fa8
Address@host_sys_fw_comp_cvm : 0x1a850fa8
Address@host_sys_fw_comp_hostcpu : 0x1a860fa8
Address@host_sys_fw_comp_com : 0x1a870fa8
Address@host_sys_fw_comp_mot : 0x1a880fa8
Address@host_sys_fw_comp_hperi_slv : 0x1a890fa8
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fa8
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fa8
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fa8
Address@host_sys_fw_comp_evm : 0x1a8d0fa8
Address@host_sys_fw_comp_debug : 0x1a8e0fa8
Address@secenc_fw_comp_fc1 : 0x50210fa8
Bits Name Description
31 - 0 fw_comp_fc_cap2


fw_comp_fc_cap3
Firewall Component Capability Register 3
R
Address@host_sys_fw_comp_sysperi : 0x1a810fac
Address@host_sys_fw_comp_dbgperi : 0x1a820fac
Address@host_sys_fw_comp_aonperi : 0x1a830fac
Address@host_sys_fw_comp_envm : 0x1a840fac
Address@host_sys_fw_comp_cvm : 0x1a850fac
Address@host_sys_fw_comp_hostcpu : 0x1a860fac
Address@host_sys_fw_comp_com : 0x1a870fac
Address@host_sys_fw_comp_mot : 0x1a880fac
Address@host_sys_fw_comp_hperi_slv : 0x1a890fac
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fac
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fac
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fac
Address@host_sys_fw_comp_evm : 0x1a8d0fac
Address@host_sys_fw_comp_debug : 0x1a8e0fac
Address@secenc_fw_comp_fc1 : 0x50210fac
Bits Name Description
31 - 0 fw_comp_fc_cap3


fw_comp_fc_cfg0
Firewall Component Capability Register 0
R
Address@host_sys_fw_comp_sysperi : 0x1a810fb0
Address@host_sys_fw_comp_dbgperi : 0x1a820fb0
Address@host_sys_fw_comp_aonperi : 0x1a830fb0
Address@host_sys_fw_comp_envm : 0x1a840fb0
Address@host_sys_fw_comp_cvm : 0x1a850fb0
Address@host_sys_fw_comp_hostcpu : 0x1a860fb0
Address@host_sys_fw_comp_com : 0x1a870fb0
Address@host_sys_fw_comp_mot : 0x1a880fb0
Address@host_sys_fw_comp_hperi_slv : 0x1a890fb0
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb0
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb0
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb0
Address@host_sys_fw_comp_evm : 0x1a8d0fb0
Address@host_sys_fw_comp_debug : 0x1a8e0fb0
Address@secenc_fw_comp_fc1 : 0x50210fb0
Bits Name Description
31 - 5 -
 reserved
4 - 0 fc_id
Firewall Component ID


fw_comp_fc_cfg1
Firewall Component Configuration Register 1
R
Address@host_sys_fw_comp_sysperi : 0x1a810fb4
Address@host_sys_fw_comp_dbgperi : 0x1a820fb4
Address@host_sys_fw_comp_aonperi : 0x1a830fb4
Address@host_sys_fw_comp_envm : 0x1a840fb4
Address@host_sys_fw_comp_cvm : 0x1a850fb4
Address@host_sys_fw_comp_hostcpu : 0x1a860fb4
Address@host_sys_fw_comp_com : 0x1a870fb4
Address@host_sys_fw_comp_mot : 0x1a880fb4
Address@host_sys_fw_comp_hperi_slv : 0x1a890fb4
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb4
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb4
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb4
Address@host_sys_fw_comp_evm : 0x1a8d0fb4
Address@host_sys_fw_comp_debug : 0x1a8e0fb4
Address@secenc_fw_comp_fc1 : 0x50210fb4
Bits Name Description
31 - 21 -
 reserved
20 sec_spt
Firewall Component support for checking the security of the incoming transaction and setting the security of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when SE.0 is implemented and 1 when SE.1 is implemented.
19 ma_spt
Firewall Component support for setting the memory type of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when TE.0 is implemented.
18 sh_spt
Firewall Component support for setting the shareability of the outgoing transaction.
0b0: Not supported
0b1: Supported
This field is 0b0 when TE.0 is implemented.
17 inst_spt
Firewall Component support for checking whether the incoming transaction is an instruction or data access and setting the instruction property of the outgoing transaction.
0b0: Not supported
0b1: Supported
16 priv_spt
Firewall Component support for checking the privileged level of the incoming transaction and setting the privileged level of the outgoing transaction.
0b0: Not supported
0b1: Supported
15 - 14 -
 reserved
13 - 12 num_mpe
Number of MPEs implemented, per region, in the Firewall Component.
0b00: 1 MPE per region
0b01: 2 MPEs per region
0b10: 3 MPEs per region
0b11: 4 MPEs per region
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.
11 -
 reserved
10 - 8 mnrs
Minimum Region Size
0x1: 64B, 0x2: 128B, 0x3: 256B, 0x4: 512B, 0x5: 1KB, 0x6: 2KB, 0x7: 4KB
7 - 0 num_rgn
Number of regions implemented in the Firewall Component.
This field is Reserved and treated as RAZ/WI when PE.0 is implemented.


fw_comp_fc_cfg2
Firewall Component Configuration Register 2
R
Address@host_sys_fw_comp_sysperi : 0x1a810fb8
Address@host_sys_fw_comp_dbgperi : 0x1a820fb8
Address@host_sys_fw_comp_aonperi : 0x1a830fb8
Address@host_sys_fw_comp_envm : 0x1a840fb8
Address@host_sys_fw_comp_cvm : 0x1a850fb8
Address@host_sys_fw_comp_hostcpu : 0x1a860fb8
Address@host_sys_fw_comp_com : 0x1a870fb8
Address@host_sys_fw_comp_mot : 0x1a880fb8
Address@host_sys_fw_comp_hperi_slv : 0x1a890fb8
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fb8
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fb8
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fb8
Address@host_sys_fw_comp_evm : 0x1a8d0fb8
Address@host_sys_fw_comp_debug : 0x1a8e0fb8
Address@secenc_fw_comp_fc1 : 0x50210fb8
Bits Name Description
31 single_mst
Whether the Firewall Component supports a single MasterID.
0b0: Firewall Component supports more than one MasterID.
0b1: Firewall Component supports only one MasterID.
30 - 21 -
 reserved
20 - 13 prot_size
Protection Size. The value of this field indicates the range of addresses which the Firewall Component protects.
0x00: 0B, 0x05: 32B, 0x06: 64B, ... 0x0C: 4K, 0x0D: 8KB, ... 0x40: 16EB
12 - 8 mst_id_width
Maximum MasterID field width of the Bus interfaces of the Firewall Component.
which the Firewall Component protects.
0x00: 1 bit of MasterID, 0x01: 2 bits of MasterID ... 0x1F: 32 bits of MasterID
When a Firewall Component supports more than one Bus Slave or Master interface this field is set to the largest width used.
7 -
 reserved
6 - 0 mxrs
The Maximum Region Size the Firewall Component Supports.
0x05: 32B, 0x06: 64B, ... 0x0C: 4KB, 0x0D: 8KB ... 0x40: 16EB
All other values are Reserved.
This field is Reserved and treated as RAZ/WI invalid for a Firewall Component which implements PE.0.


fw_comp_fc_cfg3
Firewall Component Configuration Register 3
R
Address@host_sys_fw_comp_sysperi : 0x1a810fbc
Address@host_sys_fw_comp_dbgperi : 0x1a820fbc
Address@host_sys_fw_comp_aonperi : 0x1a830fbc
Address@host_sys_fw_comp_envm : 0x1a840fbc
Address@host_sys_fw_comp_cvm : 0x1a850fbc
Address@host_sys_fw_comp_hostcpu : 0x1a860fbc
Address@host_sys_fw_comp_com : 0x1a870fbc
Address@host_sys_fw_comp_mot : 0x1a880fbc
Address@host_sys_fw_comp_hperi_slv : 0x1a890fbc
Address@host_sys_fw_comp_sms_slv : 0x1a8a0fbc
Address@host_sys_fw_comp_hperi_mst : 0x1a8b0fbc
Address@host_sys_fw_comp_sms_mst : 0x1a8c0fbc
Address@host_sys_fw_comp_evm : 0x1a8d0fbc
Address@host_sys_fw_comp_debug : 0x1a8e0fbc
Address@secenc_fw_comp_fc1 : 0x50210fbc
Bits Name Description
31 - 6 -
 reserved
5 - 0 num_fc
Number of Firewall Components implemented.
The number of Firewall Components which are implemented in the Firewall is NUM_FC+1.
For Firewall Components, other than 0, this field is Reserved and treated as RAZ/WI.



Base Address Area: app_mhu_sender_app2com0, mot_mhu_sender_mot2app0, com_mhu_sender_com2app0, app_mhu_sender_app2com1, mot_mhu_sender_mot2app1, com_mhu_sender_com2app1, app_mhu_sender_app2mot0, mot_mhu_sender_mot2se0, com_mhu_sender_com2se0, app_mhu_sender_app2mot1, mot_mhu_sender_mot2se1, com_mhu_sender_com2se1, app_mhu_sender_app2se0, app_mhu_sender_app2se1, secenc_mhu_sender_se2app0, secenc_mhu_sender_se2app1, secenc_mhu_sender_se2com0, secenc_mhu_sender_se2com1, secenc_mhu_sender_se2mot0, secenc_mhu_sender_se2mot1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R mhu_sender_ch0_st
1-2 4-8 -  reserved
3 c W mhu_sender_ch0_set
4 10 R mhu_sender_ch0_int_st
5 14 R mhu_sender_ch0_int_clr
6 18 R/W mhu_sender_ch0_int_en
7 1c -  reserved
8 20 R mhu_sender_ch1_st
9-a 24-28 -  reserved
b 2c W mhu_sender_ch1_set
c 30 R mhu_sender_ch1_int_st
d 34 R mhu_sender_ch1_int_clr
e 38 R/W mhu_sender_ch1_int_en
f-3df 3c-f7c -  reserved
3e0 f80 R mhu_sender_mhu_cfg
3e1 f84 R/W mhu_sender_resp_cfg
3e2 f88 R/W mhu_sender_access_request
3e3 f8c R mhu_sender_access_ready
3e4 f90 R mhu_sender_int_st
3e5 f94 W mhu_sender_int_clr
3e6 f98 R/W mhu_sender_int_en
3e7 f9c -  reserved
3e8 fa0 R mhu_sender_chcomb_int_st0
3e9 fa4 R mhu_sender_chcomb_int_st1
3ea fa8 R mhu_sender_chcomb_int_st2
3eb fac R mhu_sender_chcomb_int_st3
3ec-3f1 fb0-fc4 -  reserved
3f2 fc8 R mhu_sender_iidr
3f3 fcc R mhu_sender_aidr
3f4 fd0 R mhu_sender_pid4
3f5 fd4 R mhu_sender_pid5
3f6 fd8 R mhu_sender_pid6
3f7 fdc R mhu_sender_pid7
3f8 fe0 R mhu_sender_pid0
3f9 fe4 R mhu_sender_pid1
3fa fe8 R mhu_sender_pid2
3fb fec R mhu_sender_pid3
3fc ff0 R mhu_sender_cid0
3fd ff4 R mhu_sender_cid1
3fe ff8 R mhu_sender_cid2
3ff ffc R mhu_sender_cid3

mhu_sender_ch0_st
Channel 0 Status register
R
Address@app_mhu_sender_app2com0 : 0x1b000000
Address@mot_mhu_sender_mot2app0 : 0x1b010000
Address@com_mhu_sender_com2app0 : 0x1b010000
Address@app_mhu_sender_app2com1 : 0x1b020000
Address@mot_mhu_sender_mot2app1 : 0x1b030000
Address@com_mhu_sender_com2app1 : 0x1b030000
Address@app_mhu_sender_app2mot0 : 0x1b040000
Address@mot_mhu_sender_mot2se0 : 0x1b050000
Address@com_mhu_sender_com2se0 : 0x1b050000
Address@app_mhu_sender_app2mot1 : 0x1b060000
Address@mot_mhu_sender_mot2se1 : 0x1b070000
Address@com_mhu_sender_com2se1 : 0x1b070000
Address@app_mhu_sender_app2se0 : 0x1b800000
Address@app_mhu_sender_app2se1 : 0x1b820000
Address@secenc_mhu_sender_se2app0 : 0x50003000
Address@secenc_mhu_sender_se2app1 : 0x50005000
Address@secenc_mhu_sender_se2com0 : 0x50010000
Address@secenc_mhu_sender_se2com1 : 0x50012000
Address@secenc_mhu_sender_se2mot0 : 0x50014000
Address@secenc_mhu_sender_se2mot1 : 0x50016000
Bits Name Description
31 - 0 flags
Display the status of channel flags.
Each bit can be used as an individual flag or bits can be grouped.
The way in which the register is used depends on the transport protocol that is employed.
Bits in this register are set by writing 0b1 to the corresponding bits in the ch_set register.
Writing 0b1 to bits in the ch_clr register clears the corresponding bits in the ch_st register.
If software:
Sets a bit that is already set, the bit remains set.
Clears a bit that is already cleared, the bit remains cleared.
Sets and clears a bit at the same time, the bit remains set.


mhu_sender_ch0_set
Channel 0 Set register
W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b00000c
Address@mot_mhu_sender_mot2app0 : 0x1b01000c
Address@com_mhu_sender_com2app0 : 0x1b01000c
Address@app_mhu_sender_app2com1 : 0x1b02000c
Address@mot_mhu_sender_mot2app1 : 0x1b03000c
Address@com_mhu_sender_com2app1 : 0x1b03000c
Address@app_mhu_sender_app2mot0 : 0x1b04000c
Address@mot_mhu_sender_mot2se0 : 0x1b05000c
Address@com_mhu_sender_com2se0 : 0x1b05000c
Address@app_mhu_sender_app2mot1 : 0x1b06000c
Address@mot_mhu_sender_mot2se1 : 0x1b07000c
Address@com_mhu_sender_com2se1 : 0x1b07000c
Address@app_mhu_sender_app2se0 : 0x1b80000c
Address@app_mhu_sender_app2se1 : 0x1b82000c
Address@secenc_mhu_sender_se2app0 : 0x5000300c
Address@secenc_mhu_sender_se2app1 : 0x5000500c
Address@secenc_mhu_sender_se2com0 : 0x5001000c
Address@secenc_mhu_sender_se2com1 : 0x5001200c
Address@secenc_mhu_sender_se2mot0 : 0x5001400c
Address@secenc_mhu_sender_se2mot1 : 0x5001600c
Bits Reset value Name Description
31 - 0 0x0
flags
Set the channel flags.
Writing 0b1 to bits in this register sets the corresponding bits in the ch_st register.
Writing 0b0 to bits in this register has no effect. Each bit always reads as 0b0.


mhu_sender_ch0_int_st
Channel 0 Interrupt Status register
R
Address@app_mhu_sender_app2com0 : 0x1b000010
Address@mot_mhu_sender_mot2app0 : 0x1b010010
Address@com_mhu_sender_com2app0 : 0x1b010010
Address@app_mhu_sender_app2com1 : 0x1b020010
Address@mot_mhu_sender_mot2app1 : 0x1b030010
Address@com_mhu_sender_com2app1 : 0x1b030010
Address@app_mhu_sender_app2mot0 : 0x1b040010
Address@mot_mhu_sender_mot2se0 : 0x1b050010
Address@com_mhu_sender_com2se0 : 0x1b050010
Address@app_mhu_sender_app2mot1 : 0x1b060010
Address@mot_mhu_sender_mot2se1 : 0x1b070010
Address@com_mhu_sender_com2se1 : 0x1b070010
Address@app_mhu_sender_app2se0 : 0x1b800010
Address@app_mhu_sender_app2se1 : 0x1b820010
Address@secenc_mhu_sender_se2app0 : 0x50003010
Address@secenc_mhu_sender_se2app1 : 0x50005010
Address@secenc_mhu_sender_se2com0 : 0x50010010
Address@secenc_mhu_sender_se2com1 : 0x50012010
Address@secenc_mhu_sender_se2mot0 : 0x50014010
Address@secenc_mhu_sender_se2mot1 : 0x50016010
Bits Name Description
31 - 1 -
 reserved
0 ch_clr
Displays the status of the channel clear interrupt.
0b0 indicates that a channel clear interrupt has not occurred.
0b1 indicates that a channel cleat interrupt is generated.
This field is set to 0b1 when the Receiver writes to the ch_clr register.
There is no requirement for the field to be set to 0b1 if, at the point at which the write occurs, the Sender domain is:
Not powered on
Held in reset
This field is set to 0b0 when the Sender writes 0b1 to the ch_int_clr.ch_clr field.
The process of setting this field to 0b1 takes priority over setting it to 0b0.
ch_int_en is not an interrupt mask register, but it enables and disables the interrupt
generation itself.


mhu_sender_ch0_int_clr
Channel 0 Interrupt Clear register
R
Address@app_mhu_sender_app2com0 : 0x1b000014
Address@mot_mhu_sender_mot2app0 : 0x1b010014
Address@com_mhu_sender_com2app0 : 0x1b010014
Address@app_mhu_sender_app2com1 : 0x1b020014
Address@mot_mhu_sender_mot2app1 : 0x1b030014
Address@com_mhu_sender_com2app1 : 0x1b030014
Address@app_mhu_sender_app2mot0 : 0x1b040014
Address@mot_mhu_sender_mot2se0 : 0x1b050014
Address@com_mhu_sender_com2se0 : 0x1b050014
Address@app_mhu_sender_app2mot1 : 0x1b060014
Address@mot_mhu_sender_mot2se1 : 0x1b070014
Address@com_mhu_sender_com2se1 : 0x1b070014
Address@app_mhu_sender_app2se0 : 0x1b800014
Address@app_mhu_sender_app2se1 : 0x1b820014
Address@secenc_mhu_sender_se2app0 : 0x50003014
Address@secenc_mhu_sender_se2app1 : 0x50005014
Address@secenc_mhu_sender_se2com0 : 0x50010014
Address@secenc_mhu_sender_se2com1 : 0x50012014
Address@secenc_mhu_sender_se2mot0 : 0x50014014
Address@secenc_mhu_sender_se2mot1 : 0x50016014
Bits Name Description
31 - 1 -
 reserved
0 ch_clr
Clears the channel clear interrupt.
Writing 0b1 to this field clears the interrupt. Writing 0b0 to this field has no effect.
This field always reads as 0b0.


mhu_sender_ch0_int_en
Channel 0 Interrupt Enable register
R/W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b000018
Address@mot_mhu_sender_mot2app0 : 0x1b010018
Address@com_mhu_sender_com2app0 : 0x1b010018
Address@app_mhu_sender_app2com1 : 0x1b020018
Address@mot_mhu_sender_mot2app1 : 0x1b030018
Address@com_mhu_sender_com2app1 : 0x1b030018
Address@app_mhu_sender_app2mot0 : 0x1b040018
Address@mot_mhu_sender_mot2se0 : 0x1b050018
Address@com_mhu_sender_com2se0 : 0x1b050018
Address@app_mhu_sender_app2mot1 : 0x1b060018
Address@mot_mhu_sender_mot2se1 : 0x1b070018
Address@com_mhu_sender_com2se1 : 0x1b070018
Address@app_mhu_sender_app2se0 : 0x1b800018
Address@app_mhu_sender_app2se1 : 0x1b820018
Address@secenc_mhu_sender_se2app0 : 0x50003018
Address@secenc_mhu_sender_se2app1 : 0x50005018
Address@secenc_mhu_sender_se2com0 : 0x50010018
Address@secenc_mhu_sender_se2com1 : 0x50012018
Address@secenc_mhu_sender_se2mot0 : 0x50014018
Address@secenc_mhu_sender_se2mot1 : 0x50016018
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ch_clr
Enables and disables generation of the channel clear interrupt.
Writing 0b1 to this field enables generation of the interrupt.
Writing 0b0 to this field disables interrupt generation.


mhu_sender_ch1_st
Channel 1 Status register
R
Address@app_mhu_sender_app2com0 : 0x1b000020
Address@mot_mhu_sender_mot2app0 : 0x1b010020
Address@com_mhu_sender_com2app0 : 0x1b010020
Address@app_mhu_sender_app2com1 : 0x1b020020
Address@mot_mhu_sender_mot2app1 : 0x1b030020
Address@com_mhu_sender_com2app1 : 0x1b030020
Address@app_mhu_sender_app2mot0 : 0x1b040020
Address@mot_mhu_sender_mot2se0 : 0x1b050020
Address@com_mhu_sender_com2se0 : 0x1b050020
Address@app_mhu_sender_app2mot1 : 0x1b060020
Address@mot_mhu_sender_mot2se1 : 0x1b070020
Address@com_mhu_sender_com2se1 : 0x1b070020
Address@app_mhu_sender_app2se0 : 0x1b800020
Address@app_mhu_sender_app2se1 : 0x1b820020
Address@secenc_mhu_sender_se2app0 : 0x50003020
Address@secenc_mhu_sender_se2app1 : 0x50005020
Address@secenc_mhu_sender_se2com0 : 0x50010020
Address@secenc_mhu_sender_se2com1 : 0x50012020
Address@secenc_mhu_sender_se2mot0 : 0x50014020
Address@secenc_mhu_sender_se2mot1 : 0x50016020
Bits Name Description
31 - 0 flags
Display the status of channel flags.
Each bit can be used as an individual flag or bits can be grouped.
The way in which the register is used depends on the transport protocol that is employed.
Bits in this register are set by writing 0b1 to the corresponding bits in the ch_set register.
Writing 0b1 to bits in the ch_clr register clears the corresponding bits in the ch_st register.
If software:
Sets a bit that is already set, the bit remains set.
Clears a bit that is already cleared, the bit remains cleared.
Sets and clears a bit at the same time, the bit remains set.


mhu_sender_ch1_set
Channel 1 Set register
W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b00002c
Address@mot_mhu_sender_mot2app0 : 0x1b01002c
Address@com_mhu_sender_com2app0 : 0x1b01002c
Address@app_mhu_sender_app2com1 : 0x1b02002c
Address@mot_mhu_sender_mot2app1 : 0x1b03002c
Address@com_mhu_sender_com2app1 : 0x1b03002c
Address@app_mhu_sender_app2mot0 : 0x1b04002c
Address@mot_mhu_sender_mot2se0 : 0x1b05002c
Address@com_mhu_sender_com2se0 : 0x1b05002c
Address@app_mhu_sender_app2mot1 : 0x1b06002c
Address@mot_mhu_sender_mot2se1 : 0x1b07002c
Address@com_mhu_sender_com2se1 : 0x1b07002c
Address@app_mhu_sender_app2se0 : 0x1b80002c
Address@app_mhu_sender_app2se1 : 0x1b82002c
Address@secenc_mhu_sender_se2app0 : 0x5000302c
Address@secenc_mhu_sender_se2app1 : 0x5000502c
Address@secenc_mhu_sender_se2com0 : 0x5001002c
Address@secenc_mhu_sender_se2com1 : 0x5001202c
Address@secenc_mhu_sender_se2mot0 : 0x5001402c
Address@secenc_mhu_sender_se2mot1 : 0x5001602c
Bits Reset value Name Description
31 - 0 0x0
flags
Set the channel flags.
Writing 0b1 to bits in this register sets the corresponding bits in the ch_st register.
Writing 0b0 to bits in this register has no effect. Each bit always reads as 0b0.


mhu_sender_ch1_int_st
Channel 1 Interrupt Status register
R
Address@app_mhu_sender_app2com0 : 0x1b000030
Address@mot_mhu_sender_mot2app0 : 0x1b010030
Address@com_mhu_sender_com2app0 : 0x1b010030
Address@app_mhu_sender_app2com1 : 0x1b020030
Address@mot_mhu_sender_mot2app1 : 0x1b030030
Address@com_mhu_sender_com2app1 : 0x1b030030
Address@app_mhu_sender_app2mot0 : 0x1b040030
Address@mot_mhu_sender_mot2se0 : 0x1b050030
Address@com_mhu_sender_com2se0 : 0x1b050030
Address@app_mhu_sender_app2mot1 : 0x1b060030
Address@mot_mhu_sender_mot2se1 : 0x1b070030
Address@com_mhu_sender_com2se1 : 0x1b070030
Address@app_mhu_sender_app2se0 : 0x1b800030
Address@app_mhu_sender_app2se1 : 0x1b820030
Address@secenc_mhu_sender_se2app0 : 0x50003030
Address@secenc_mhu_sender_se2app1 : 0x50005030
Address@secenc_mhu_sender_se2com0 : 0x50010030
Address@secenc_mhu_sender_se2com1 : 0x50012030
Address@secenc_mhu_sender_se2mot0 : 0x50014030
Address@secenc_mhu_sender_se2mot1 : 0x50016030
Bits Name Description
31 - 1 -
 reserved
0 ch_clr
Displays the status of the channel clear interrupt.
0b0 indicates that a channel clear interrupt has not occurred.
0b1 indicates that a channel cleat interrupt is generated.
This field is set to 0b1 when the Receiver writes to the ch_clr register.
There is no requirement for the field to be set to 0b1 if, at the point at which the write occurs, the Sender domain is:
Not powered on
Held in reset
This field is set to 0b0 when the Sender writes 0b1 to the ch_int_clr.ch_clr field.
The process of setting this field to 0b1 takes priority over setting it to 0b0.
ch_int_en is not an interrupt mask register, but it enables and disables the interrupt
generation itself.


mhu_sender_ch1_int_clr
Channel 1 Interrupt Clear register
R
Address@app_mhu_sender_app2com0 : 0x1b000034
Address@mot_mhu_sender_mot2app0 : 0x1b010034
Address@com_mhu_sender_com2app0 : 0x1b010034
Address@app_mhu_sender_app2com1 : 0x1b020034
Address@mot_mhu_sender_mot2app1 : 0x1b030034
Address@com_mhu_sender_com2app1 : 0x1b030034
Address@app_mhu_sender_app2mot0 : 0x1b040034
Address@mot_mhu_sender_mot2se0 : 0x1b050034
Address@com_mhu_sender_com2se0 : 0x1b050034
Address@app_mhu_sender_app2mot1 : 0x1b060034
Address@mot_mhu_sender_mot2se1 : 0x1b070034
Address@com_mhu_sender_com2se1 : 0x1b070034
Address@app_mhu_sender_app2se0 : 0x1b800034
Address@app_mhu_sender_app2se1 : 0x1b820034
Address@secenc_mhu_sender_se2app0 : 0x50003034
Address@secenc_mhu_sender_se2app1 : 0x50005034
Address@secenc_mhu_sender_se2com0 : 0x50010034
Address@secenc_mhu_sender_se2com1 : 0x50012034
Address@secenc_mhu_sender_se2mot0 : 0x50014034
Address@secenc_mhu_sender_se2mot1 : 0x50016034
Bits Name Description
31 - 1 -
 reserved
0 ch_clr
Clears the channel clear interrupt.
Writing 0b1 to this field clears the interrupt. Writing 0b0 to this field has no effect.
This field always reads as 0b0.


mhu_sender_ch1_int_en
Channel 1 Interrupt Enable register
R/W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b000038
Address@mot_mhu_sender_mot2app0 : 0x1b010038
Address@com_mhu_sender_com2app0 : 0x1b010038
Address@app_mhu_sender_app2com1 : 0x1b020038
Address@mot_mhu_sender_mot2app1 : 0x1b030038
Address@com_mhu_sender_com2app1 : 0x1b030038
Address@app_mhu_sender_app2mot0 : 0x1b040038
Address@mot_mhu_sender_mot2se0 : 0x1b050038
Address@com_mhu_sender_com2se0 : 0x1b050038
Address@app_mhu_sender_app2mot1 : 0x1b060038
Address@mot_mhu_sender_mot2se1 : 0x1b070038
Address@com_mhu_sender_com2se1 : 0x1b070038
Address@app_mhu_sender_app2se0 : 0x1b800038
Address@app_mhu_sender_app2se1 : 0x1b820038
Address@secenc_mhu_sender_se2app0 : 0x50003038
Address@secenc_mhu_sender_se2app1 : 0x50005038
Address@secenc_mhu_sender_se2com0 : 0x50010038
Address@secenc_mhu_sender_se2com1 : 0x50012038
Address@secenc_mhu_sender_se2mot0 : 0x50014038
Address@secenc_mhu_sender_se2mot1 : 0x50016038
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ch_clr
Enables and disables generation of the channel clear interrupt.
Writing 0b1 to this field enables generation of the interrupt.
Writing 0b0 to this field disables interrupt generation.


mhu_sender_mhu_cfg
Message Handling Unit Configuration register
R
Address@app_mhu_sender_app2com0 : 0x1b000f80
Address@mot_mhu_sender_mot2app0 : 0x1b010f80
Address@com_mhu_sender_com2app0 : 0x1b010f80
Address@app_mhu_sender_app2com1 : 0x1b020f80
Address@mot_mhu_sender_mot2app1 : 0x1b030f80
Address@com_mhu_sender_com2app1 : 0x1b030f80
Address@app_mhu_sender_app2mot0 : 0x1b040f80
Address@mot_mhu_sender_mot2se0 : 0x1b050f80
Address@com_mhu_sender_com2se0 : 0x1b050f80
Address@app_mhu_sender_app2mot1 : 0x1b060f80
Address@mot_mhu_sender_mot2se1 : 0x1b070f80
Address@com_mhu_sender_com2se1 : 0x1b070f80
Address@app_mhu_sender_app2se0 : 0x1b800f80
Address@app_mhu_sender_app2se1 : 0x1b820f80
Address@secenc_mhu_sender_se2app0 : 0x50003f80
Address@secenc_mhu_sender_se2app1 : 0x50005f80
Address@secenc_mhu_sender_se2com0 : 0x50010f80
Address@secenc_mhu_sender_se2com1 : 0x50012f80
Address@secenc_mhu_sender_se2mot0 : 0x50014f80
Address@secenc_mhu_sender_se2mot1 : 0x50016f80
Bits Name Description
31 - 7 -
 reserved
6 - 0 num_ch
Specifies the number of MHU channels that are implemented.
The value of the field indicates the number of channels, up to a maximum of 124 (0x7C).
The values 0x00, 0x7D, 0x7E, and 0x7F are reserved.


mhu_sender_resp_cfg
Response Configuration register
R/W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b000f84
Address@mot_mhu_sender_mot2app0 : 0x1b010f84
Address@com_mhu_sender_com2app0 : 0x1b010f84
Address@app_mhu_sender_app2com1 : 0x1b020f84
Address@mot_mhu_sender_mot2app1 : 0x1b030f84
Address@com_mhu_sender_com2app1 : 0x1b030f84
Address@app_mhu_sender_app2mot0 : 0x1b040f84
Address@mot_mhu_sender_mot2se0 : 0x1b050f84
Address@com_mhu_sender_com2se0 : 0x1b050f84
Address@app_mhu_sender_app2mot1 : 0x1b060f84
Address@mot_mhu_sender_mot2se1 : 0x1b070f84
Address@com_mhu_sender_com2se1 : 0x1b070f84
Address@app_mhu_sender_app2se0 : 0x1b800f84
Address@app_mhu_sender_app2se1 : 0x1b820f84
Address@secenc_mhu_sender_se2app0 : 0x50003f84
Address@secenc_mhu_sender_se2app1 : 0x50005f84
Address@secenc_mhu_sender_se2com0 : 0x50010f84
Address@secenc_mhu_sender_se2com1 : 0x50012f84
Address@secenc_mhu_sender_se2mot0 : 0x50014f84
Address@secenc_mhu_sender_se2mot1 : 0x50016f84
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
nr_resp
Specifies the response that is generated when the Sender attempts to access any channel window register while the access_ready.acc_rdy field is set to 0b0.
This setting indicates that the Receiver is not in a state in which it can accept a transfer.
When the Receiver is not ready, channel window register access attempts by the Sender are treated as RAZ/WI.
With the resp_cfg.nr_resp field set to 0b0, an error is not generated.
IF this field is set to 0b1, then an error is generated.


mhu_sender_access_request
Access Request register
R/W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b000f88
Address@mot_mhu_sender_mot2app0 : 0x1b010f88
Address@com_mhu_sender_com2app0 : 0x1b010f88
Address@app_mhu_sender_app2com1 : 0x1b020f88
Address@mot_mhu_sender_mot2app1 : 0x1b030f88
Address@com_mhu_sender_com2app1 : 0x1b030f88
Address@app_mhu_sender_app2mot0 : 0x1b040f88
Address@mot_mhu_sender_mot2se0 : 0x1b050f88
Address@com_mhu_sender_com2se0 : 0x1b050f88
Address@app_mhu_sender_app2mot1 : 0x1b060f88
Address@mot_mhu_sender_mot2se1 : 0x1b070f88
Address@com_mhu_sender_com2se1 : 0x1b070f88
Address@app_mhu_sender_app2se0 : 0x1b800f88
Address@app_mhu_sender_app2se1 : 0x1b820f88
Address@secenc_mhu_sender_se2app0 : 0x50003f88
Address@secenc_mhu_sender_se2app1 : 0x50005f88
Address@secenc_mhu_sender_se2com0 : 0x50010f88
Address@secenc_mhu_sender_se2com1 : 0x50012f88
Address@secenc_mhu_sender_se2mot0 : 0x50014f88
Address@secenc_mhu_sender_se2mot1 : 0x50016f88
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
acc_req
Requests that the Receiver prepares to accept a transfer.
- A setting of 0b0 for this field indicates that the Receiver does not need to prepare for a transfer.
- If this field is set to 0b1, then the Receiver is requested to prepare to accept a transfer.


mhu_sender_access_ready
Access Ready register
R
Address@app_mhu_sender_app2com0 : 0x1b000f8c
Address@mot_mhu_sender_mot2app0 : 0x1b010f8c
Address@com_mhu_sender_com2app0 : 0x1b010f8c
Address@app_mhu_sender_app2com1 : 0x1b020f8c
Address@mot_mhu_sender_mot2app1 : 0x1b030f8c
Address@com_mhu_sender_com2app1 : 0x1b030f8c
Address@app_mhu_sender_app2mot0 : 0x1b040f8c
Address@mot_mhu_sender_mot2se0 : 0x1b050f8c
Address@com_mhu_sender_com2se0 : 0x1b050f8c
Address@app_mhu_sender_app2mot1 : 0x1b060f8c
Address@mot_mhu_sender_mot2se1 : 0x1b070f8c
Address@com_mhu_sender_com2se1 : 0x1b070f8c
Address@app_mhu_sender_app2se0 : 0x1b800f8c
Address@app_mhu_sender_app2se1 : 0x1b820f8c
Address@secenc_mhu_sender_se2app0 : 0x50003f8c
Address@secenc_mhu_sender_se2app1 : 0x50005f8c
Address@secenc_mhu_sender_se2com0 : 0x50010f8c
Address@secenc_mhu_sender_se2com1 : 0x50012f8c
Address@secenc_mhu_sender_se2mot0 : 0x50014f8c
Address@secenc_mhu_sender_se2mot1 : 0x50016f8c
Bits Name Description
31 - 1 -
 reserved
0 acc_rdy
Specifies whether the Receiver is able to accept a transfer.
- A setting of 0b0 for this field indicates that the Receiver is not able to accept a transfer.
- If this field is set to 0b1, then the Receiver is able to accept a transfer.


mhu_sender_int_st
Interrupt Status register
R
Address@app_mhu_sender_app2com0 : 0x1b000f90
Address@mot_mhu_sender_mot2app0 : 0x1b010f90
Address@com_mhu_sender_com2app0 : 0x1b010f90
Address@app_mhu_sender_app2com1 : 0x1b020f90
Address@mot_mhu_sender_mot2app1 : 0x1b030f90
Address@com_mhu_sender_com2app1 : 0x1b030f90
Address@app_mhu_sender_app2mot0 : 0x1b040f90
Address@mot_mhu_sender_mot2se0 : 0x1b050f90
Address@com_mhu_sender_com2se0 : 0x1b050f90
Address@app_mhu_sender_app2mot1 : 0x1b060f90
Address@mot_mhu_sender_mot2se1 : 0x1b070f90
Address@com_mhu_sender_com2se1 : 0x1b070f90
Address@app_mhu_sender_app2se0 : 0x1b800f90
Address@app_mhu_sender_app2se1 : 0x1b820f90
Address@secenc_mhu_sender_se2app0 : 0x50003f90
Address@secenc_mhu_sender_se2app1 : 0x50005f90
Address@secenc_mhu_sender_se2com0 : 0x50010f90
Address@secenc_mhu_sender_se2com1 : 0x50012f90
Address@secenc_mhu_sender_se2mot0 : 0x50014f90
Address@secenc_mhu_sender_se2mot1 : 0x50016f90
Bits Name Description
31 - 3 -
 reserved
2 chcomb
Displays the status of the channel combined interrupt.
- A setting of 0b0 for this field indicates that an interrupt has not occurred on any channel.
- If this field is set to 0b1, then an interrupt has been generated on at least one channel.
There is no corresponding bit in the int_clr register. To clear the combined interrupt, software must clear the underlying interrupt.
1 r2nr
Displays the status of the ready to not ready interrupt.
- A setting of 0b0 for this field indicates that a ready to not ready interrupt has not occurred.
- If this field is set to 0b1, then a ready to not ready interrupt has been generated.
0 nr2r
Displays the status of the not ready to ready interrupt.
- A setting of 0b0 for this field indicates that a not ready to ready interrupt has not occurred.
- If this field is set to 0b1, then a not ready to ready interrupt has been generated.


mhu_sender_int_clr
Interrupt Clear register
W
0x00000000
Address@app_mhu_sender_app2com0 : 0x1b000f94
Address@mot_mhu_sender_mot2app0 : 0x1b010f94
Address@com_mhu_sender_com2app0 : 0x1b010f94
Address@app_mhu_sender_app2com1 : 0x1b020f94
Address@mot_mhu_sender_mot2app1 : 0x1b030f94
Address@com_mhu_sender_com2app1 : 0x1b030f94
Address@app_mhu_sender_app2mot0 : 0x1b040f94
Address@mot_mhu_sender_mot2se0 : 0x1b050f94
Address@com_mhu_sender_com2se0 : 0x1b050f94
Address@app_mhu_sender_app2mot1 : 0x1b060f94
Address@mot_mhu_sender_mot2se1 : 0x1b070f94
Address@com_mhu_sender_com2se1 : 0x1b070f94
Address@app_mhu_sender_app2se0 : 0x1b800f94
Address@app_mhu_sender_app2se1 : 0x1b820f94
Address@secenc_mhu_sender_se2app0 : 0x50003f94
Address@secenc_mhu_sender_se2app1 : 0x50005f94
Address@secenc_mhu_sender_se2com0 : 0x50010f94
Address@secenc_mhu_sender_se2com1 : 0x50012f94
Address@secenc_mhu_sender_se2mot0 : 0x50014f94
Address@secenc_mhu_sender_se2mot1 : 0x50016f94
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
r2nr
Clears the ready to not ready interrupt.
- Writing 0b1 to this field clears the ready to not ready interrupt.
- Writing 0b0 to this field has no effect.
0 "0"
nr2r
Clears the not ready to ready interrupt.
- Writing 0b1 to this field clears the not ready to ready interrupt.
- Writing 0b0 to this field has no effect.


mhu_sender_int_en
Interrupt Enable register
R/W
0x00000004
Address@app_mhu_sender_app2com0 : 0x1b000f98
Address@mot_mhu_sender_mot2app0 : 0x1b010f98
Address@com_mhu_sender_com2app0 : 0x1b010f98
Address@app_mhu_sender_app2com1 : 0x1b020f98
Address@mot_mhu_sender_mot2app1 : 0x1b030f98
Address@com_mhu_sender_com2app1 : 0x1b030f98
Address@app_mhu_sender_app2mot0 : 0x1b040f98
Address@mot_mhu_sender_mot2se0 : 0x1b050f98
Address@com_mhu_sender_com2se0 : 0x1b050f98
Address@app_mhu_sender_app2mot1 : 0x1b060f98
Address@mot_mhu_sender_mot2se1 : 0x1b070f98
Address@com_mhu_sender_com2se1 : 0x1b070f98
Address@app_mhu_sender_app2se0 : 0x1b800f98
Address@app_mhu_sender_app2se1 : 0x1b820f98
Address@secenc_mhu_sender_se2app0 : 0x50003f98
Address@secenc_mhu_sender_se2app1 : 0x50005f98
Address@secenc_mhu_sender_se2com0 : 0x50010f98
Address@secenc_mhu_sender_se2com1 : 0x50012f98
Address@secenc_mhu_sender_se2mot0 : 0x50014f98
Address@secenc_mhu_sender_se2mot1 : 0x50016f98
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "1"
chcomb
Enables and disables generation of the channel combined interrupt.
- Writing 0b1 to this field enables generation of the channel combined interrupt.
- Writing 0b0 to this field disables channel combined interrupt generation.
1 "0"
r2nr
Enables and disables generation of the ready to not ready interrupt.
- Writing 0b1 to this field enables generation of the ready to not ready interrupt.
- Writing 0b0 to this field disables ready to not ready interrupt generation.
0 "0"
nr2r
Enables and disables generation of the not ready to ready interrupt.
- Writing 0b1 to this field enables generation of the not ready to ready interrupt.
- Writing 0b0 to this field disables not ready to ready interrupt generation.


mhu_sender_chcomb_int_st0
Channel Combined Interrupt Status register 0
R
Address@app_mhu_sender_app2com0 : 0x1b000fa0
Address@mot_mhu_sender_mot2app0 : 0x1b010fa0
Address@com_mhu_sender_com2app0 : 0x1b010fa0
Address@app_mhu_sender_app2com1 : 0x1b020fa0
Address@mot_mhu_sender_mot2app1 : 0x1b030fa0
Address@com_mhu_sender_com2app1 : 0x1b030fa0
Address@app_mhu_sender_app2mot0 : 0x1b040fa0
Address@mot_mhu_sender_mot2se0 : 0x1b050fa0
Address@com_mhu_sender_com2se0 : 0x1b050fa0
Address@app_mhu_sender_app2mot1 : 0x1b060fa0
Address@mot_mhu_sender_mot2se1 : 0x1b070fa0
Address@com_mhu_sender_com2se1 : 0x1b070fa0
Address@app_mhu_sender_app2se0 : 0x1b800fa0
Address@app_mhu_sender_app2se1 : 0x1b820fa0
Address@secenc_mhu_sender_se2app0 : 0x50003fa0
Address@secenc_mhu_sender_se2app1 : 0x50005fa0
Address@secenc_mhu_sender_se2com0 : 0x50010fa0
Address@secenc_mhu_sender_se2com1 : 0x50012fa0
Address@secenc_mhu_sender_se2mot0 : 0x50014fa0
Address@secenc_mhu_sender_se2mot1 : 0x50016fa0
Bits Name Description
31 - 0 ch_int_st0
Display the status of channel interrupts 0-31.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the ch_int_stn registers of the Sender frame are set to 0b1 when the associated ch_int_st.ch_clr field is set to 0b1.


mhu_sender_chcomb_int_st1
Channel Combined Interrupt Status register 1
R
Address@app_mhu_sender_app2com0 : 0x1b000fa4
Address@mot_mhu_sender_mot2app0 : 0x1b010fa4
Address@com_mhu_sender_com2app0 : 0x1b010fa4
Address@app_mhu_sender_app2com1 : 0x1b020fa4
Address@mot_mhu_sender_mot2app1 : 0x1b030fa4
Address@com_mhu_sender_com2app1 : 0x1b030fa4
Address@app_mhu_sender_app2mot0 : 0x1b040fa4
Address@mot_mhu_sender_mot2se0 : 0x1b050fa4
Address@com_mhu_sender_com2se0 : 0x1b050fa4
Address@app_mhu_sender_app2mot1 : 0x1b060fa4
Address@mot_mhu_sender_mot2se1 : 0x1b070fa4
Address@com_mhu_sender_com2se1 : 0x1b070fa4
Address@app_mhu_sender_app2se0 : 0x1b800fa4
Address@app_mhu_sender_app2se1 : 0x1b820fa4
Address@secenc_mhu_sender_se2app0 : 0x50003fa4
Address@secenc_mhu_sender_se2app1 : 0x50005fa4
Address@secenc_mhu_sender_se2com0 : 0x50010fa4
Address@secenc_mhu_sender_se2com1 : 0x50012fa4
Address@secenc_mhu_sender_se2mot0 : 0x50014fa4
Address@secenc_mhu_sender_se2mot1 : 0x50016fa4
Bits Name Description
31 - 0 ch_int_st1
Display the status of channel interrupts 32-63.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the ch_int_stn registers of the Sender frame are set to 0b1 when the associated ch_int_st.ch_clr field is set to 0b1.


mhu_sender_chcomb_int_st2
Channel Combined Interrupt Status register 2
R
Address@app_mhu_sender_app2com0 : 0x1b000fa8
Address@mot_mhu_sender_mot2app0 : 0x1b010fa8
Address@com_mhu_sender_com2app0 : 0x1b010fa8
Address@app_mhu_sender_app2com1 : 0x1b020fa8
Address@mot_mhu_sender_mot2app1 : 0x1b030fa8
Address@com_mhu_sender_com2app1 : 0x1b030fa8
Address@app_mhu_sender_app2mot0 : 0x1b040fa8
Address@mot_mhu_sender_mot2se0 : 0x1b050fa8
Address@com_mhu_sender_com2se0 : 0x1b050fa8
Address@app_mhu_sender_app2mot1 : 0x1b060fa8
Address@mot_mhu_sender_mot2se1 : 0x1b070fa8
Address@com_mhu_sender_com2se1 : 0x1b070fa8
Address@app_mhu_sender_app2se0 : 0x1b800fa8
Address@app_mhu_sender_app2se1 : 0x1b820fa8
Address@secenc_mhu_sender_se2app0 : 0x50003fa8
Address@secenc_mhu_sender_se2app1 : 0x50005fa8
Address@secenc_mhu_sender_se2com0 : 0x50010fa8
Address@secenc_mhu_sender_se2com1 : 0x50012fa8
Address@secenc_mhu_sender_se2mot0 : 0x50014fa8
Address@secenc_mhu_sender_se2mot1 : 0x50016fa8
Bits Name Description
31 - 0 ch_int_st2
Display the status of channel interrupts 64-95.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the ch_int_stn registers of the Sender frame are set to 0b1 when the associated ch_int_st.ch_clr field is set to 0b1.


mhu_sender_chcomb_int_st3
Channel Combined Interrupt Status register 3
R
Address@app_mhu_sender_app2com0 : 0x1b000fac
Address@mot_mhu_sender_mot2app0 : 0x1b010fac
Address@com_mhu_sender_com2app0 : 0x1b010fac
Address@app_mhu_sender_app2com1 : 0x1b020fac
Address@mot_mhu_sender_mot2app1 : 0x1b030fac
Address@com_mhu_sender_com2app1 : 0x1b030fac
Address@app_mhu_sender_app2mot0 : 0x1b040fac
Address@mot_mhu_sender_mot2se0 : 0x1b050fac
Address@com_mhu_sender_com2se0 : 0x1b050fac
Address@app_mhu_sender_app2mot1 : 0x1b060fac
Address@mot_mhu_sender_mot2se1 : 0x1b070fac
Address@com_mhu_sender_com2se1 : 0x1b070fac
Address@app_mhu_sender_app2se0 : 0x1b800fac
Address@app_mhu_sender_app2se1 : 0x1b820fac
Address@secenc_mhu_sender_se2app0 : 0x50003fac
Address@secenc_mhu_sender_se2app1 : 0x50005fac
Address@secenc_mhu_sender_se2com0 : 0x50010fac
Address@secenc_mhu_sender_se2com1 : 0x50012fac
Address@secenc_mhu_sender_se2mot0 : 0x50014fac
Address@secenc_mhu_sender_se2mot1 : 0x50016fac
Bits Name Description
31 - 0 ch_int_st3
Display the status of channel interrupts 96-123.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
In the chcomb_int_st3 register, bits[31:28] are always Reserved and treated as RAZ/WI.
The fields within the ch_int_stn registers of the Sender frame are set to 0b1 when the associated ch_int_st.ch_clr field is set to 0b1.


mhu_sender_iidr
Implementer Identification Register
R
Address@app_mhu_sender_app2com0 : 0x1b000fc8
Address@mot_mhu_sender_mot2app0 : 0x1b010fc8
Address@com_mhu_sender_com2app0 : 0x1b010fc8
Address@app_mhu_sender_app2com1 : 0x1b020fc8
Address@mot_mhu_sender_mot2app1 : 0x1b030fc8
Address@com_mhu_sender_com2app1 : 0x1b030fc8
Address@app_mhu_sender_app2mot0 : 0x1b040fc8
Address@mot_mhu_sender_mot2se0 : 0x1b050fc8
Address@com_mhu_sender_com2se0 : 0x1b050fc8
Address@app_mhu_sender_app2mot1 : 0x1b060fc8
Address@mot_mhu_sender_mot2se1 : 0x1b070fc8
Address@com_mhu_sender_com2se1 : 0x1b070fc8
Address@app_mhu_sender_app2se0 : 0x1b800fc8
Address@app_mhu_sender_app2se1 : 0x1b820fc8
Address@secenc_mhu_sender_se2app0 : 0x50003fc8
Address@secenc_mhu_sender_se2app1 : 0x50005fc8
Address@secenc_mhu_sender_se2com0 : 0x50010fc8
Address@secenc_mhu_sender_se2com1 : 0x50012fc8
Address@secenc_mhu_sender_se2mot0 : 0x50014fc8
Address@secenc_mhu_sender_se2mot1 : 0x50016fc8
Bits Name Description
31 - 20 product_id
Specifies the MHU part identifier.
19 - 16 variant
Specifies the MHU major revision number.
15 - 12 revision
Specifies the MHU minor revision number.
11 - 0 implementer
Specifies the JEDEC JEP106 manufacturers identification code for Arm.
Bits[11:8] contain the JEP106 continuation code for the implementer
Bit[7] must always be 0
Bits[6:0] give the JEP106 identity code for the implementer


mhu_sender_aidr
Architecture Identification Register
R
Address@app_mhu_sender_app2com0 : 0x1b000fcc
Address@mot_mhu_sender_mot2app0 : 0x1b010fcc
Address@com_mhu_sender_com2app0 : 0x1b010fcc
Address@app_mhu_sender_app2com1 : 0x1b020fcc
Address@mot_mhu_sender_mot2app1 : 0x1b030fcc
Address@com_mhu_sender_com2app1 : 0x1b030fcc
Address@app_mhu_sender_app2mot0 : 0x1b040fcc
Address@mot_mhu_sender_mot2se0 : 0x1b050fcc
Address@com_mhu_sender_com2se0 : 0x1b050fcc
Address@app_mhu_sender_app2mot1 : 0x1b060fcc
Address@mot_mhu_sender_mot2se1 : 0x1b070fcc
Address@com_mhu_sender_com2se1 : 0x1b070fcc
Address@app_mhu_sender_app2se0 : 0x1b800fcc
Address@app_mhu_sender_app2se1 : 0x1b820fcc
Address@secenc_mhu_sender_se2app0 : 0x50003fcc
Address@secenc_mhu_sender_se2app1 : 0x50005fcc
Address@secenc_mhu_sender_se2com0 : 0x50010fcc
Address@secenc_mhu_sender_se2com1 : 0x50012fcc
Address@secenc_mhu_sender_se2mot0 : 0x50014fcc
Address@secenc_mhu_sender_se2mot1 : 0x50016fcc
Bits Name Description
31 - 8 -
 reserved
7 - 4 arch_major_rev
Specifies the MHU major architecture revision number.
- A value of 0x1 indicates that the MHU conforms to MHU architecture version 2.
- The setting 0x0 is Reserved.
When the arch_major_rev field is set to 0x0, the values in the arch_minor_rev field and iidr register are RAZ.
Software must determine in a platform-specific manner the MHU architecture version to which the component conforms.
3 - 0 arch_minor_rev
Specifies the MHU minor architecture revision number.
A value of 0x0 indicates that the architecture minor revision number is 0, while a setting of 0x1 specifies a minor revision number of 1.
All other values are reserved.


mhu_sender_pid4
Peripheral ID Register 4
R
Address@app_mhu_sender_app2com0 : 0x1b000fd0
Address@mot_mhu_sender_mot2app0 : 0x1b010fd0
Address@com_mhu_sender_com2app0 : 0x1b010fd0
Address@app_mhu_sender_app2com1 : 0x1b020fd0
Address@mot_mhu_sender_mot2app1 : 0x1b030fd0
Address@com_mhu_sender_com2app1 : 0x1b030fd0
Address@app_mhu_sender_app2mot0 : 0x1b040fd0
Address@mot_mhu_sender_mot2se0 : 0x1b050fd0
Address@com_mhu_sender_com2se0 : 0x1b050fd0
Address@app_mhu_sender_app2mot1 : 0x1b060fd0
Address@mot_mhu_sender_mot2se1 : 0x1b070fd0
Address@com_mhu_sender_com2se1 : 0x1b070fd0
Address@app_mhu_sender_app2se0 : 0x1b800fd0
Address@app_mhu_sender_app2se1 : 0x1b820fd0
Address@secenc_mhu_sender_se2app0 : 0x50003fd0
Address@secenc_mhu_sender_se2app1 : 0x50005fd0
Address@secenc_mhu_sender_se2com0 : 0x50010fd0
Address@secenc_mhu_sender_se2com1 : 0x50012fd0
Address@secenc_mhu_sender_se2mot0 : 0x50014fd0
Address@secenc_mhu_sender_se2mot1 : 0x50016fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


mhu_sender_pid5
Peripheral ID Register 5
R
Address@app_mhu_sender_app2com0 : 0x1b000fd4
Address@mot_mhu_sender_mot2app0 : 0x1b010fd4
Address@com_mhu_sender_com2app0 : 0x1b010fd4
Address@app_mhu_sender_app2com1 : 0x1b020fd4
Address@mot_mhu_sender_mot2app1 : 0x1b030fd4
Address@com_mhu_sender_com2app1 : 0x1b030fd4
Address@app_mhu_sender_app2mot0 : 0x1b040fd4
Address@mot_mhu_sender_mot2se0 : 0x1b050fd4
Address@com_mhu_sender_com2se0 : 0x1b050fd4
Address@app_mhu_sender_app2mot1 : 0x1b060fd4
Address@mot_mhu_sender_mot2se1 : 0x1b070fd4
Address@com_mhu_sender_com2se1 : 0x1b070fd4
Address@app_mhu_sender_app2se0 : 0x1b800fd4
Address@app_mhu_sender_app2se1 : 0x1b820fd4
Address@secenc_mhu_sender_se2app0 : 0x50003fd4
Address@secenc_mhu_sender_se2app1 : 0x50005fd4
Address@secenc_mhu_sender_se2com0 : 0x50010fd4
Address@secenc_mhu_sender_se2com1 : 0x50012fd4
Address@secenc_mhu_sender_se2mot0 : 0x50014fd4
Address@secenc_mhu_sender_se2mot1 : 0x50016fd4
Bits Name Description
31 - 0 mhu_sender_pid5


mhu_sender_pid6
Peripheral ID Register 6
R
Address@app_mhu_sender_app2com0 : 0x1b000fd8
Address@mot_mhu_sender_mot2app0 : 0x1b010fd8
Address@com_mhu_sender_com2app0 : 0x1b010fd8
Address@app_mhu_sender_app2com1 : 0x1b020fd8
Address@mot_mhu_sender_mot2app1 : 0x1b030fd8
Address@com_mhu_sender_com2app1 : 0x1b030fd8
Address@app_mhu_sender_app2mot0 : 0x1b040fd8
Address@mot_mhu_sender_mot2se0 : 0x1b050fd8
Address@com_mhu_sender_com2se0 : 0x1b050fd8
Address@app_mhu_sender_app2mot1 : 0x1b060fd8
Address@mot_mhu_sender_mot2se1 : 0x1b070fd8
Address@com_mhu_sender_com2se1 : 0x1b070fd8
Address@app_mhu_sender_app2se0 : 0x1b800fd8
Address@app_mhu_sender_app2se1 : 0x1b820fd8
Address@secenc_mhu_sender_se2app0 : 0x50003fd8
Address@secenc_mhu_sender_se2app1 : 0x50005fd8
Address@secenc_mhu_sender_se2com0 : 0x50010fd8
Address@secenc_mhu_sender_se2com1 : 0x50012fd8
Address@secenc_mhu_sender_se2mot0 : 0x50014fd8
Address@secenc_mhu_sender_se2mot1 : 0x50016fd8
Bits Name Description
31 - 0 mhu_sender_pid6


mhu_sender_pid7
Peripheral ID Register 7
R
Address@app_mhu_sender_app2com0 : 0x1b000fdc
Address@mot_mhu_sender_mot2app0 : 0x1b010fdc
Address@com_mhu_sender_com2app0 : 0x1b010fdc
Address@app_mhu_sender_app2com1 : 0x1b020fdc
Address@mot_mhu_sender_mot2app1 : 0x1b030fdc
Address@com_mhu_sender_com2app1 : 0x1b030fdc
Address@app_mhu_sender_app2mot0 : 0x1b040fdc
Address@mot_mhu_sender_mot2se0 : 0x1b050fdc
Address@com_mhu_sender_com2se0 : 0x1b050fdc
Address@app_mhu_sender_app2mot1 : 0x1b060fdc
Address@mot_mhu_sender_mot2se1 : 0x1b070fdc
Address@com_mhu_sender_com2se1 : 0x1b070fdc
Address@app_mhu_sender_app2se0 : 0x1b800fdc
Address@app_mhu_sender_app2se1 : 0x1b820fdc
Address@secenc_mhu_sender_se2app0 : 0x50003fdc
Address@secenc_mhu_sender_se2app1 : 0x50005fdc
Address@secenc_mhu_sender_se2com0 : 0x50010fdc
Address@secenc_mhu_sender_se2com1 : 0x50012fdc
Address@secenc_mhu_sender_se2mot0 : 0x50014fdc
Address@secenc_mhu_sender_se2mot1 : 0x50016fdc
Bits Name Description
31 - 0 mhu_sender_pid7


mhu_sender_pid0
Peripheral ID Register 0
R
Address@app_mhu_sender_app2com0 : 0x1b000fe0
Address@mot_mhu_sender_mot2app0 : 0x1b010fe0
Address@com_mhu_sender_com2app0 : 0x1b010fe0
Address@app_mhu_sender_app2com1 : 0x1b020fe0
Address@mot_mhu_sender_mot2app1 : 0x1b030fe0
Address@com_mhu_sender_com2app1 : 0x1b030fe0
Address@app_mhu_sender_app2mot0 : 0x1b040fe0
Address@mot_mhu_sender_mot2se0 : 0x1b050fe0
Address@com_mhu_sender_com2se0 : 0x1b050fe0
Address@app_mhu_sender_app2mot1 : 0x1b060fe0
Address@mot_mhu_sender_mot2se1 : 0x1b070fe0
Address@com_mhu_sender_com2se1 : 0x1b070fe0
Address@app_mhu_sender_app2se0 : 0x1b800fe0
Address@app_mhu_sender_app2se1 : 0x1b820fe0
Address@secenc_mhu_sender_se2app0 : 0x50003fe0
Address@secenc_mhu_sender_se2app1 : 0x50005fe0
Address@secenc_mhu_sender_se2com0 : 0x50010fe0
Address@secenc_mhu_sender_se2com1 : 0x50012fe0
Address@secenc_mhu_sender_se2mot0 : 0x50014fe0
Address@secenc_mhu_sender_se2mot1 : 0x50016fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


mhu_sender_pid1
Peripheral ID Register 1
R
Address@app_mhu_sender_app2com0 : 0x1b000fe4
Address@mot_mhu_sender_mot2app0 : 0x1b010fe4
Address@com_mhu_sender_com2app0 : 0x1b010fe4
Address@app_mhu_sender_app2com1 : 0x1b020fe4
Address@mot_mhu_sender_mot2app1 : 0x1b030fe4
Address@com_mhu_sender_com2app1 : 0x1b030fe4
Address@app_mhu_sender_app2mot0 : 0x1b040fe4
Address@mot_mhu_sender_mot2se0 : 0x1b050fe4
Address@com_mhu_sender_com2se0 : 0x1b050fe4
Address@app_mhu_sender_app2mot1 : 0x1b060fe4
Address@mot_mhu_sender_mot2se1 : 0x1b070fe4
Address@com_mhu_sender_com2se1 : 0x1b070fe4
Address@app_mhu_sender_app2se0 : 0x1b800fe4
Address@app_mhu_sender_app2se1 : 0x1b820fe4
Address@secenc_mhu_sender_se2app0 : 0x50003fe4
Address@secenc_mhu_sender_se2app1 : 0x50005fe4
Address@secenc_mhu_sender_se2com0 : 0x50010fe4
Address@secenc_mhu_sender_se2com1 : 0x50012fe4
Address@secenc_mhu_sender_se2mot0 : 0x50014fe4
Address@secenc_mhu_sender_se2mot1 : 0x50016fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


mhu_sender_pid2
Peripheral ID Register 2
R
Address@app_mhu_sender_app2com0 : 0x1b000fe8
Address@mot_mhu_sender_mot2app0 : 0x1b010fe8
Address@com_mhu_sender_com2app0 : 0x1b010fe8
Address@app_mhu_sender_app2com1 : 0x1b020fe8
Address@mot_mhu_sender_mot2app1 : 0x1b030fe8
Address@com_mhu_sender_com2app1 : 0x1b030fe8
Address@app_mhu_sender_app2mot0 : 0x1b040fe8
Address@mot_mhu_sender_mot2se0 : 0x1b050fe8
Address@com_mhu_sender_com2se0 : 0x1b050fe8
Address@app_mhu_sender_app2mot1 : 0x1b060fe8
Address@mot_mhu_sender_mot2se1 : 0x1b070fe8
Address@com_mhu_sender_com2se1 : 0x1b070fe8
Address@app_mhu_sender_app2se0 : 0x1b800fe8
Address@app_mhu_sender_app2se1 : 0x1b820fe8
Address@secenc_mhu_sender_se2app0 : 0x50003fe8
Address@secenc_mhu_sender_se2app1 : 0x50005fe8
Address@secenc_mhu_sender_se2com0 : 0x50010fe8
Address@secenc_mhu_sender_se2com1 : 0x50012fe8
Address@secenc_mhu_sender_se2mot0 : 0x50014fe8
Address@secenc_mhu_sender_se2mot1 : 0x50016fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


mhu_sender_pid3
Peripheral ID Register 3
R
Address@app_mhu_sender_app2com0 : 0x1b000fec
Address@mot_mhu_sender_mot2app0 : 0x1b010fec
Address@com_mhu_sender_com2app0 : 0x1b010fec
Address@app_mhu_sender_app2com1 : 0x1b020fec
Address@mot_mhu_sender_mot2app1 : 0x1b030fec
Address@com_mhu_sender_com2app1 : 0x1b030fec
Address@app_mhu_sender_app2mot0 : 0x1b040fec
Address@mot_mhu_sender_mot2se0 : 0x1b050fec
Address@com_mhu_sender_com2se0 : 0x1b050fec
Address@app_mhu_sender_app2mot1 : 0x1b060fec
Address@mot_mhu_sender_mot2se1 : 0x1b070fec
Address@com_mhu_sender_com2se1 : 0x1b070fec
Address@app_mhu_sender_app2se0 : 0x1b800fec
Address@app_mhu_sender_app2se1 : 0x1b820fec
Address@secenc_mhu_sender_se2app0 : 0x50003fec
Address@secenc_mhu_sender_se2app1 : 0x50005fec
Address@secenc_mhu_sender_se2com0 : 0x50010fec
Address@secenc_mhu_sender_se2com1 : 0x50012fec
Address@secenc_mhu_sender_se2mot0 : 0x50014fec
Address@secenc_mhu_sender_se2mot1 : 0x50016fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


mhu_sender_cid0
Component ID Register 0
R
Address@app_mhu_sender_app2com0 : 0x1b000ff0
Address@mot_mhu_sender_mot2app0 : 0x1b010ff0
Address@com_mhu_sender_com2app0 : 0x1b010ff0
Address@app_mhu_sender_app2com1 : 0x1b020ff0
Address@mot_mhu_sender_mot2app1 : 0x1b030ff0
Address@com_mhu_sender_com2app1 : 0x1b030ff0
Address@app_mhu_sender_app2mot0 : 0x1b040ff0
Address@mot_mhu_sender_mot2se0 : 0x1b050ff0
Address@com_mhu_sender_com2se0 : 0x1b050ff0
Address@app_mhu_sender_app2mot1 : 0x1b060ff0
Address@mot_mhu_sender_mot2se1 : 0x1b070ff0
Address@com_mhu_sender_com2se1 : 0x1b070ff0
Address@app_mhu_sender_app2se0 : 0x1b800ff0
Address@app_mhu_sender_app2se1 : 0x1b820ff0
Address@secenc_mhu_sender_se2app0 : 0x50003ff0
Address@secenc_mhu_sender_se2app1 : 0x50005ff0
Address@secenc_mhu_sender_se2com0 : 0x50010ff0
Address@secenc_mhu_sender_se2com1 : 0x50012ff0
Address@secenc_mhu_sender_se2mot0 : 0x50014ff0
Address@secenc_mhu_sender_se2mot1 : 0x50016ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


mhu_sender_cid1
Component ID Register 1
R
Address@app_mhu_sender_app2com0 : 0x1b000ff4
Address@mot_mhu_sender_mot2app0 : 0x1b010ff4
Address@com_mhu_sender_com2app0 : 0x1b010ff4
Address@app_mhu_sender_app2com1 : 0x1b020ff4
Address@mot_mhu_sender_mot2app1 : 0x1b030ff4
Address@com_mhu_sender_com2app1 : 0x1b030ff4
Address@app_mhu_sender_app2mot0 : 0x1b040ff4
Address@mot_mhu_sender_mot2se0 : 0x1b050ff4
Address@com_mhu_sender_com2se0 : 0x1b050ff4
Address@app_mhu_sender_app2mot1 : 0x1b060ff4
Address@mot_mhu_sender_mot2se1 : 0x1b070ff4
Address@com_mhu_sender_com2se1 : 0x1b070ff4
Address@app_mhu_sender_app2se0 : 0x1b800ff4
Address@app_mhu_sender_app2se1 : 0x1b820ff4
Address@secenc_mhu_sender_se2app0 : 0x50003ff4
Address@secenc_mhu_sender_se2app1 : 0x50005ff4
Address@secenc_mhu_sender_se2com0 : 0x50010ff4
Address@secenc_mhu_sender_se2com1 : 0x50012ff4
Address@secenc_mhu_sender_se2mot0 : 0x50014ff4
Address@secenc_mhu_sender_se2mot1 : 0x50016ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


mhu_sender_cid2
Component ID Register 2
R
Address@app_mhu_sender_app2com0 : 0x1b000ff8
Address@mot_mhu_sender_mot2app0 : 0x1b010ff8
Address@com_mhu_sender_com2app0 : 0x1b010ff8
Address@app_mhu_sender_app2com1 : 0x1b020ff8
Address@mot_mhu_sender_mot2app1 : 0x1b030ff8
Address@com_mhu_sender_com2app1 : 0x1b030ff8
Address@app_mhu_sender_app2mot0 : 0x1b040ff8
Address@mot_mhu_sender_mot2se0 : 0x1b050ff8
Address@com_mhu_sender_com2se0 : 0x1b050ff8
Address@app_mhu_sender_app2mot1 : 0x1b060ff8
Address@mot_mhu_sender_mot2se1 : 0x1b070ff8
Address@com_mhu_sender_com2se1 : 0x1b070ff8
Address@app_mhu_sender_app2se0 : 0x1b800ff8
Address@app_mhu_sender_app2se1 : 0x1b820ff8
Address@secenc_mhu_sender_se2app0 : 0x50003ff8
Address@secenc_mhu_sender_se2app1 : 0x50005ff8
Address@secenc_mhu_sender_se2com0 : 0x50010ff8
Address@secenc_mhu_sender_se2com1 : 0x50012ff8
Address@secenc_mhu_sender_se2mot0 : 0x50014ff8
Address@secenc_mhu_sender_se2mot1 : 0x50016ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


mhu_sender_cid3
Component ID Register 3
R
Address@app_mhu_sender_app2com0 : 0x1b000ffc
Address@mot_mhu_sender_mot2app0 : 0x1b010ffc
Address@com_mhu_sender_com2app0 : 0x1b010ffc
Address@app_mhu_sender_app2com1 : 0x1b020ffc
Address@mot_mhu_sender_mot2app1 : 0x1b030ffc
Address@com_mhu_sender_com2app1 : 0x1b030ffc
Address@app_mhu_sender_app2mot0 : 0x1b040ffc
Address@mot_mhu_sender_mot2se0 : 0x1b050ffc
Address@com_mhu_sender_com2se0 : 0x1b050ffc
Address@app_mhu_sender_app2mot1 : 0x1b060ffc
Address@mot_mhu_sender_mot2se1 : 0x1b070ffc
Address@com_mhu_sender_com2se1 : 0x1b070ffc
Address@app_mhu_sender_app2se0 : 0x1b800ffc
Address@app_mhu_sender_app2se1 : 0x1b820ffc
Address@secenc_mhu_sender_se2app0 : 0x50003ffc
Address@secenc_mhu_sender_se2app1 : 0x50005ffc
Address@secenc_mhu_sender_se2com0 : 0x50010ffc
Address@secenc_mhu_sender_se2com1 : 0x50012ffc
Address@secenc_mhu_sender_se2mot0 : 0x50014ffc
Address@secenc_mhu_sender_se2mot1 : 0x50016ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: mot_mhu_receiver_app2mot0, com_mhu_receiver_app2com0, app_mhu_receiver_com2app0, mot_mhu_receiver_app2mot1, com_mhu_receiver_app2com1, app_mhu_receiver_com2app1, mot_mhu_receiver_se2mot0, com_mhu_receiver_se2com0, app_mhu_receiver_mot2app0, mot_mhu_receiver_se2mot1, com_mhu_receiver_se2com1, app_mhu_receiver_mot2app1, app_mhu_receiver_se2app0, app_mhu_receiver_se2app1, secenc_mhu_receiver_app2se0, secenc_mhu_receiver_app2se1, secenc_mhu_receiver_com2se0, secenc_mhu_receiver_com2se1, secenc_mhu_receiver_mot2se0, secenc_mhu_receiver_mot2se1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R mhu_receiver_ch0_st
1 4 R mhu_receiver_ch0_st_msk
2 8 W mhu_receiver_ch0_clr
3 c -  reserved
4 10 R mhu_receiver_ch0_msk_st
5 14 W mhu_receiver_ch0_msk_set
6 18 W mhu_receiver_ch0_msk_clr
7 1c -  reserved
8 20 R mhu_receiver_ch1_st
9 24 R mhu_receiver_ch1_st_msk
a 28 W mhu_receiver_ch1_clr
b 2c -  reserved
c 30 R mhu_receiver_ch1_msk_st
d 34 W mhu_receiver_ch1_msk_set
e 38 W mhu_receiver_ch1_msk_clr
f-3df 3c-f7c -  reserved
3e0 f80 R mhu_receiver_mhu_cfg
3e1-3e3 f84-f8c -  reserved
3e4 f90 R mhu_receiver_int_st
3e5 f94 W mhu_receiver_int_clr
3e6 f98 R/W mhu_receiver_int_en
3e7 f9c -  reserved
3e8 fa0 R mhu_receiver_chcomb_int_st0
3e9 fa4 R mhu_receiver_chcomb_int_st1
3ea fa8 R mhu_receiver_chcomb_int_st2
3eb fac R mhu_receiver_chcomb_int_st3
3ec-3f1 fb0-fc4 -  reserved
3f2 fc8 R mhu_receiver_iidr
3f3 fcc R mhu_receiver_aidr
3f4 fd0 R mhu_receiver_pid4
3f5 fd4 R mhu_receiver_pid5
3f6 fd8 R mhu_receiver_pid6
3f7 fdc R mhu_receiver_pid7
3f8 fe0 R mhu_receiver_pid0
3f9 fe4 R mhu_receiver_pid1
3fa fe8 R mhu_receiver_pid2
3fb fec R mhu_receiver_pid3
3fc ff0 R mhu_receiver_cid0
3fd ff4 R mhu_receiver_cid1
3fe ff8 R mhu_receiver_cid2
3ff ffc R mhu_receiver_cid3

mhu_receiver_ch0_st
Channel 0 Status register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000000
Address@com_mhu_receiver_app2com0 : 0x1b000000
Address@app_mhu_receiver_com2app0 : 0x1b010000
Address@mot_mhu_receiver_app2mot1 : 0x1b020000
Address@com_mhu_receiver_app2com1 : 0x1b020000
Address@app_mhu_receiver_com2app1 : 0x1b030000
Address@mot_mhu_receiver_se2mot0 : 0x1b040000
Address@com_mhu_receiver_se2com0 : 0x1b040000
Address@app_mhu_receiver_mot2app0 : 0x1b050000
Address@mot_mhu_receiver_se2mot1 : 0x1b060000
Address@com_mhu_receiver_se2com1 : 0x1b060000
Address@app_mhu_receiver_mot2app1 : 0x1b070000
Address@app_mhu_receiver_se2app0 : 0x1b810000
Address@app_mhu_receiver_se2app1 : 0x1b830000
Address@secenc_mhu_receiver_app2se0 : 0x50004000
Address@secenc_mhu_receiver_app2se1 : 0x50006000
Address@secenc_mhu_receiver_com2se0 : 0x50011000
Address@secenc_mhu_receiver_com2se1 : 0x50013000
Address@secenc_mhu_receiver_mot2se0 : 0x50015000
Address@secenc_mhu_receiver_mot2se1 : 0x50017000
Bits Name Description
31 - 0 flag_vec
Display the status of channel flags.
Each bit can be used as an individual flag or bits can be grouped.
The way in which the register is used depends on the transport protocol that is employed.


mhu_receiver_ch0_st_msk
Channel 0 Status Masked register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000004
Address@com_mhu_receiver_app2com0 : 0x1b000004
Address@app_mhu_receiver_com2app0 : 0x1b010004
Address@mot_mhu_receiver_app2mot1 : 0x1b020004
Address@com_mhu_receiver_app2com1 : 0x1b020004
Address@app_mhu_receiver_com2app1 : 0x1b030004
Address@mot_mhu_receiver_se2mot0 : 0x1b040004
Address@com_mhu_receiver_se2com0 : 0x1b040004
Address@app_mhu_receiver_mot2app0 : 0x1b050004
Address@mot_mhu_receiver_se2mot1 : 0x1b060004
Address@com_mhu_receiver_se2com1 : 0x1b060004
Address@app_mhu_receiver_mot2app1 : 0x1b070004
Address@app_mhu_receiver_se2app0 : 0x1b810004
Address@app_mhu_receiver_se2app1 : 0x1b830004
Address@secenc_mhu_receiver_app2se0 : 0x50004004
Address@secenc_mhu_receiver_app2se1 : 0x50006004
Address@secenc_mhu_receiver_com2se0 : 0x50011004
Address@secenc_mhu_receiver_com2se1 : 0x50013004
Address@secenc_mhu_receiver_mot2se0 : 0x50015004
Address@secenc_mhu_receiver_mot2se1 : 0x50017004
Bits Name Description
31 - 0 flag_vec
Display the status of channel flags with the mask applied.
When this register is nonzero, the interrupt for the Channel is asserted.
The value in this register is equal to CH_ST and ~CH_MSK_ST, at the point at which the read occurs.


mhu_receiver_ch0_clr
Channel 0 Clear register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000008
Address@com_mhu_receiver_app2com0 : 0x1b000008
Address@app_mhu_receiver_com2app0 : 0x1b010008
Address@mot_mhu_receiver_app2mot1 : 0x1b020008
Address@com_mhu_receiver_app2com1 : 0x1b020008
Address@app_mhu_receiver_com2app1 : 0x1b030008
Address@mot_mhu_receiver_se2mot0 : 0x1b040008
Address@com_mhu_receiver_se2com0 : 0x1b040008
Address@app_mhu_receiver_mot2app0 : 0x1b050008
Address@mot_mhu_receiver_se2mot1 : 0x1b060008
Address@com_mhu_receiver_se2com1 : 0x1b060008
Address@app_mhu_receiver_mot2app1 : 0x1b070008
Address@app_mhu_receiver_se2app0 : 0x1b810008
Address@app_mhu_receiver_se2app1 : 0x1b830008
Address@secenc_mhu_receiver_app2se0 : 0x50004008
Address@secenc_mhu_receiver_app2se1 : 0x50006008
Address@secenc_mhu_receiver_com2se0 : 0x50011008
Address@secenc_mhu_receiver_com2se1 : 0x50013008
Address@secenc_mhu_receiver_mot2se0 : 0x50015008
Address@secenc_mhu_receiver_mot2se1 : 0x50017008
Bits Reset value Name Description
31 - 0 0x0
flag_clr_vec
Clear the channel flags.
Writing 0b1 to bits in this register clears the corresponding bits in the CH_ST and CH_ST_MSK registers.
Writing 0b0 to bits in this register has no effect. Each bit always reads as 0b0.


mhu_receiver_ch0_msk_st
Channel 0 Mask Status register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000010
Address@com_mhu_receiver_app2com0 : 0x1b000010
Address@app_mhu_receiver_com2app0 : 0x1b010010
Address@mot_mhu_receiver_app2mot1 : 0x1b020010
Address@com_mhu_receiver_app2com1 : 0x1b020010
Address@app_mhu_receiver_com2app1 : 0x1b030010
Address@mot_mhu_receiver_se2mot0 : 0x1b040010
Address@com_mhu_receiver_se2com0 : 0x1b040010
Address@app_mhu_receiver_mot2app0 : 0x1b050010
Address@mot_mhu_receiver_se2mot1 : 0x1b060010
Address@com_mhu_receiver_se2com1 : 0x1b060010
Address@app_mhu_receiver_mot2app1 : 0x1b070010
Address@app_mhu_receiver_se2app0 : 0x1b810010
Address@app_mhu_receiver_se2app1 : 0x1b830010
Address@secenc_mhu_receiver_app2se0 : 0x50004010
Address@secenc_mhu_receiver_app2se1 : 0x50006010
Address@secenc_mhu_receiver_com2se0 : 0x50011010
Address@secenc_mhu_receiver_com2se1 : 0x50013010
Address@secenc_mhu_receiver_mot2se0 : 0x50015010
Address@secenc_mhu_receiver_mot2se1 : 0x50017010
Bits Name Description
31 - 0 flag_msk_vec
Display the status of channel flag masks.
A channel mask bit that is set to 0b0 indicates that the corresponding flag bit is unmasked.
When a bit is unmasked, the equivalent bits in the CH_ST and CH_ST_MSK registers have the same value.
A channel mask bit that is set to 0b1 indicates that the corresponding flag bit is masked.
When a bit is masked, the equivalent bit in the CH_ST_MSK register always reads as 0b0.


mhu_receiver_ch0_msk_set
Channel 0 Mask Set register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000014
Address@com_mhu_receiver_app2com0 : 0x1b000014
Address@app_mhu_receiver_com2app0 : 0x1b010014
Address@mot_mhu_receiver_app2mot1 : 0x1b020014
Address@com_mhu_receiver_app2com1 : 0x1b020014
Address@app_mhu_receiver_com2app1 : 0x1b030014
Address@mot_mhu_receiver_se2mot0 : 0x1b040014
Address@com_mhu_receiver_se2com0 : 0x1b040014
Address@app_mhu_receiver_mot2app0 : 0x1b050014
Address@mot_mhu_receiver_se2mot1 : 0x1b060014
Address@com_mhu_receiver_se2com1 : 0x1b060014
Address@app_mhu_receiver_mot2app1 : 0x1b070014
Address@app_mhu_receiver_se2app0 : 0x1b810014
Address@app_mhu_receiver_se2app1 : 0x1b830014
Address@secenc_mhu_receiver_app2se0 : 0x50004014
Address@secenc_mhu_receiver_app2se1 : 0x50006014
Address@secenc_mhu_receiver_com2se0 : 0x50011014
Address@secenc_mhu_receiver_com2se1 : 0x50013014
Address@secenc_mhu_receiver_mot2se0 : 0x50015014
Address@secenc_mhu_receiver_mot2se1 : 0x50017014
Bits Reset value Name Description
31 - 0 0x0
flag_msk_set_vec
Set the channel flag masks.
Writing 0b1 to bits in this register sets the corresponding bits in the CH_MSK_ST register.
Writing 0b0 to bits in this register has no effect.
Each bit always reads as 0b0.


mhu_receiver_ch0_msk_clr
Channel 0 Mask Clear register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000018
Address@com_mhu_receiver_app2com0 : 0x1b000018
Address@app_mhu_receiver_com2app0 : 0x1b010018
Address@mot_mhu_receiver_app2mot1 : 0x1b020018
Address@com_mhu_receiver_app2com1 : 0x1b020018
Address@app_mhu_receiver_com2app1 : 0x1b030018
Address@mot_mhu_receiver_se2mot0 : 0x1b040018
Address@com_mhu_receiver_se2com0 : 0x1b040018
Address@app_mhu_receiver_mot2app0 : 0x1b050018
Address@mot_mhu_receiver_se2mot1 : 0x1b060018
Address@com_mhu_receiver_se2com1 : 0x1b060018
Address@app_mhu_receiver_mot2app1 : 0x1b070018
Address@app_mhu_receiver_se2app0 : 0x1b810018
Address@app_mhu_receiver_se2app1 : 0x1b830018
Address@secenc_mhu_receiver_app2se0 : 0x50004018
Address@secenc_mhu_receiver_app2se1 : 0x50006018
Address@secenc_mhu_receiver_com2se0 : 0x50011018
Address@secenc_mhu_receiver_com2se1 : 0x50013018
Address@secenc_mhu_receiver_mot2se0 : 0x50015018
Address@secenc_mhu_receiver_mot2se1 : 0x50017018
Bits Reset value Name Description
31 - 0 0x0
flag_msk_clr_vec
Clear the channel flag masks.
Writing 0b1 to bits in this register clears the corresponding bits in the CH_MSK_ST register.
Writing 0b0 to bits in this register has no effect.
Each bit always reads as 0b0.


mhu_receiver_ch1_st
Channel 1 Status register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000020
Address@com_mhu_receiver_app2com0 : 0x1b000020
Address@app_mhu_receiver_com2app0 : 0x1b010020
Address@mot_mhu_receiver_app2mot1 : 0x1b020020
Address@com_mhu_receiver_app2com1 : 0x1b020020
Address@app_mhu_receiver_com2app1 : 0x1b030020
Address@mot_mhu_receiver_se2mot0 : 0x1b040020
Address@com_mhu_receiver_se2com0 : 0x1b040020
Address@app_mhu_receiver_mot2app0 : 0x1b050020
Address@mot_mhu_receiver_se2mot1 : 0x1b060020
Address@com_mhu_receiver_se2com1 : 0x1b060020
Address@app_mhu_receiver_mot2app1 : 0x1b070020
Address@app_mhu_receiver_se2app0 : 0x1b810020
Address@app_mhu_receiver_se2app1 : 0x1b830020
Address@secenc_mhu_receiver_app2se0 : 0x50004020
Address@secenc_mhu_receiver_app2se1 : 0x50006020
Address@secenc_mhu_receiver_com2se0 : 0x50011020
Address@secenc_mhu_receiver_com2se1 : 0x50013020
Address@secenc_mhu_receiver_mot2se0 : 0x50015020
Address@secenc_mhu_receiver_mot2se1 : 0x50017020
Bits Name Description
31 - 0 flag_vec
Display the status of channel flags.
Each bit can be used as an individual flag or bits can be grouped.
The way in which the register is used depends on the transport protocol that is employed.


mhu_receiver_ch1_st_msk
Channel 1 Status Masked register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000024
Address@com_mhu_receiver_app2com0 : 0x1b000024
Address@app_mhu_receiver_com2app0 : 0x1b010024
Address@mot_mhu_receiver_app2mot1 : 0x1b020024
Address@com_mhu_receiver_app2com1 : 0x1b020024
Address@app_mhu_receiver_com2app1 : 0x1b030024
Address@mot_mhu_receiver_se2mot0 : 0x1b040024
Address@com_mhu_receiver_se2com0 : 0x1b040024
Address@app_mhu_receiver_mot2app0 : 0x1b050024
Address@mot_mhu_receiver_se2mot1 : 0x1b060024
Address@com_mhu_receiver_se2com1 : 0x1b060024
Address@app_mhu_receiver_mot2app1 : 0x1b070024
Address@app_mhu_receiver_se2app0 : 0x1b810024
Address@app_mhu_receiver_se2app1 : 0x1b830024
Address@secenc_mhu_receiver_app2se0 : 0x50004024
Address@secenc_mhu_receiver_app2se1 : 0x50006024
Address@secenc_mhu_receiver_com2se0 : 0x50011024
Address@secenc_mhu_receiver_com2se1 : 0x50013024
Address@secenc_mhu_receiver_mot2se0 : 0x50015024
Address@secenc_mhu_receiver_mot2se1 : 0x50017024
Bits Name Description
31 - 0 flag_vec
Display the status of channel flags with the mask applied.
When this register is nonzero, the interrupt for the Channel is asserted.
The value in this register is equal to CH_ST and ~CH_MSK_ST, at the point at which the read occurs.


mhu_receiver_ch1_clr
Channel 1 Clear register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000028
Address@com_mhu_receiver_app2com0 : 0x1b000028
Address@app_mhu_receiver_com2app0 : 0x1b010028
Address@mot_mhu_receiver_app2mot1 : 0x1b020028
Address@com_mhu_receiver_app2com1 : 0x1b020028
Address@app_mhu_receiver_com2app1 : 0x1b030028
Address@mot_mhu_receiver_se2mot0 : 0x1b040028
Address@com_mhu_receiver_se2com0 : 0x1b040028
Address@app_mhu_receiver_mot2app0 : 0x1b050028
Address@mot_mhu_receiver_se2mot1 : 0x1b060028
Address@com_mhu_receiver_se2com1 : 0x1b060028
Address@app_mhu_receiver_mot2app1 : 0x1b070028
Address@app_mhu_receiver_se2app0 : 0x1b810028
Address@app_mhu_receiver_se2app1 : 0x1b830028
Address@secenc_mhu_receiver_app2se0 : 0x50004028
Address@secenc_mhu_receiver_app2se1 : 0x50006028
Address@secenc_mhu_receiver_com2se0 : 0x50011028
Address@secenc_mhu_receiver_com2se1 : 0x50013028
Address@secenc_mhu_receiver_mot2se0 : 0x50015028
Address@secenc_mhu_receiver_mot2se1 : 0x50017028
Bits Reset value Name Description
31 - 0 0x0
flag_clr_vec
Clear the channel flags.
Writing 0b1 to bits in this register clears the corresponding bits in the CH_ST and CH_ST_MSK registers.
Writing 0b0 to bits in this register has no effect. Each bit always reads as 0b0.


mhu_receiver_ch1_msk_st
Channel 1 Mask Status register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000030
Address@com_mhu_receiver_app2com0 : 0x1b000030
Address@app_mhu_receiver_com2app0 : 0x1b010030
Address@mot_mhu_receiver_app2mot1 : 0x1b020030
Address@com_mhu_receiver_app2com1 : 0x1b020030
Address@app_mhu_receiver_com2app1 : 0x1b030030
Address@mot_mhu_receiver_se2mot0 : 0x1b040030
Address@com_mhu_receiver_se2com0 : 0x1b040030
Address@app_mhu_receiver_mot2app0 : 0x1b050030
Address@mot_mhu_receiver_se2mot1 : 0x1b060030
Address@com_mhu_receiver_se2com1 : 0x1b060030
Address@app_mhu_receiver_mot2app1 : 0x1b070030
Address@app_mhu_receiver_se2app0 : 0x1b810030
Address@app_mhu_receiver_se2app1 : 0x1b830030
Address@secenc_mhu_receiver_app2se0 : 0x50004030
Address@secenc_mhu_receiver_app2se1 : 0x50006030
Address@secenc_mhu_receiver_com2se0 : 0x50011030
Address@secenc_mhu_receiver_com2se1 : 0x50013030
Address@secenc_mhu_receiver_mot2se0 : 0x50015030
Address@secenc_mhu_receiver_mot2se1 : 0x50017030
Bits Name Description
31 - 0 flag_msk_vec
Display the status of channel flag masks.
A channel mask bit that is set to 0b0 indicates that the corresponding flag bit is unmasked.
When a bit is unmasked, the equivalent bits in the CH_ST and CH_ST_MSK registers have the same value.
A channel mask bit that is set to 0b1 indicates that the corresponding flag bit is masked.
When a bit is masked, the equivalent bit in the CH_ST_MSK register always reads as 0b0.


mhu_receiver_ch1_msk_set
Channel 1 Mask Set register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000034
Address@com_mhu_receiver_app2com0 : 0x1b000034
Address@app_mhu_receiver_com2app0 : 0x1b010034
Address@mot_mhu_receiver_app2mot1 : 0x1b020034
Address@com_mhu_receiver_app2com1 : 0x1b020034
Address@app_mhu_receiver_com2app1 : 0x1b030034
Address@mot_mhu_receiver_se2mot0 : 0x1b040034
Address@com_mhu_receiver_se2com0 : 0x1b040034
Address@app_mhu_receiver_mot2app0 : 0x1b050034
Address@mot_mhu_receiver_se2mot1 : 0x1b060034
Address@com_mhu_receiver_se2com1 : 0x1b060034
Address@app_mhu_receiver_mot2app1 : 0x1b070034
Address@app_mhu_receiver_se2app0 : 0x1b810034
Address@app_mhu_receiver_se2app1 : 0x1b830034
Address@secenc_mhu_receiver_app2se0 : 0x50004034
Address@secenc_mhu_receiver_app2se1 : 0x50006034
Address@secenc_mhu_receiver_com2se0 : 0x50011034
Address@secenc_mhu_receiver_com2se1 : 0x50013034
Address@secenc_mhu_receiver_mot2se0 : 0x50015034
Address@secenc_mhu_receiver_mot2se1 : 0x50017034
Bits Reset value Name Description
31 - 0 0x0
flag_msk_set_vec
Set the channel flag masks.
Writing 0b1 to bits in this register sets the corresponding bits in the CH_MSK_ST register.
Writing 0b0 to bits in this register has no effect.
Each bit always reads as 0b0.


mhu_receiver_ch1_msk_clr
Channel 1 Mask Clear register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000038
Address@com_mhu_receiver_app2com0 : 0x1b000038
Address@app_mhu_receiver_com2app0 : 0x1b010038
Address@mot_mhu_receiver_app2mot1 : 0x1b020038
Address@com_mhu_receiver_app2com1 : 0x1b020038
Address@app_mhu_receiver_com2app1 : 0x1b030038
Address@mot_mhu_receiver_se2mot0 : 0x1b040038
Address@com_mhu_receiver_se2com0 : 0x1b040038
Address@app_mhu_receiver_mot2app0 : 0x1b050038
Address@mot_mhu_receiver_se2mot1 : 0x1b060038
Address@com_mhu_receiver_se2com1 : 0x1b060038
Address@app_mhu_receiver_mot2app1 : 0x1b070038
Address@app_mhu_receiver_se2app0 : 0x1b810038
Address@app_mhu_receiver_se2app1 : 0x1b830038
Address@secenc_mhu_receiver_app2se0 : 0x50004038
Address@secenc_mhu_receiver_app2se1 : 0x50006038
Address@secenc_mhu_receiver_com2se0 : 0x50011038
Address@secenc_mhu_receiver_com2se1 : 0x50013038
Address@secenc_mhu_receiver_mot2se0 : 0x50015038
Address@secenc_mhu_receiver_mot2se1 : 0x50017038
Bits Reset value Name Description
31 - 0 0x0
flag_msk_clr_vec
Clear the channel flag masks.
Writing 0b1 to bits in this register clears the corresponding bits in the CH_MSK_ST register.
Writing 0b0 to bits in this register has no effect.
Each bit always reads as 0b0.


mhu_receiver_mhu_cfg
Message Handling Unit Configuration register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000f80
Address@com_mhu_receiver_app2com0 : 0x1b000f80
Address@app_mhu_receiver_com2app0 : 0x1b010f80
Address@mot_mhu_receiver_app2mot1 : 0x1b020f80
Address@com_mhu_receiver_app2com1 : 0x1b020f80
Address@app_mhu_receiver_com2app1 : 0x1b030f80
Address@mot_mhu_receiver_se2mot0 : 0x1b040f80
Address@com_mhu_receiver_se2com0 : 0x1b040f80
Address@app_mhu_receiver_mot2app0 : 0x1b050f80
Address@mot_mhu_receiver_se2mot1 : 0x1b060f80
Address@com_mhu_receiver_se2com1 : 0x1b060f80
Address@app_mhu_receiver_mot2app1 : 0x1b070f80
Address@app_mhu_receiver_se2app0 : 0x1b810f80
Address@app_mhu_receiver_se2app1 : 0x1b830f80
Address@secenc_mhu_receiver_app2se0 : 0x50004f80
Address@secenc_mhu_receiver_app2se1 : 0x50006f80
Address@secenc_mhu_receiver_com2se0 : 0x50011f80
Address@secenc_mhu_receiver_com2se1 : 0x50013f80
Address@secenc_mhu_receiver_mot2se0 : 0x50015f80
Address@secenc_mhu_receiver_mot2se1 : 0x50017f80
Bits Name Description
31 - 7 -
 reserved
6 - 0 num_ch
Specifies the number of MHU channels that are implemented.
The value of the field indicates the number of channels, up to a maximum of 124 (0x7C).
The values 0x00, 0x7D, 0x7E, and 0x7F are reserved.


mhu_receiver_int_st
Interrupt Status register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000f90
Address@com_mhu_receiver_app2com0 : 0x1b000f90
Address@app_mhu_receiver_com2app0 : 0x1b010f90
Address@mot_mhu_receiver_app2mot1 : 0x1b020f90
Address@com_mhu_receiver_app2com1 : 0x1b020f90
Address@app_mhu_receiver_com2app1 : 0x1b030f90
Address@mot_mhu_receiver_se2mot0 : 0x1b040f90
Address@com_mhu_receiver_se2com0 : 0x1b040f90
Address@app_mhu_receiver_mot2app0 : 0x1b050f90
Address@mot_mhu_receiver_se2mot1 : 0x1b060f90
Address@com_mhu_receiver_se2com1 : 0x1b060f90
Address@app_mhu_receiver_mot2app1 : 0x1b070f90
Address@app_mhu_receiver_se2app0 : 0x1b810f90
Address@app_mhu_receiver_se2app1 : 0x1b830f90
Address@secenc_mhu_receiver_app2se0 : 0x50004f90
Address@secenc_mhu_receiver_app2se1 : 0x50006f90
Address@secenc_mhu_receiver_com2se0 : 0x50011f90
Address@secenc_mhu_receiver_com2se1 : 0x50013f90
Address@secenc_mhu_receiver_mot2se0 : 0x50015f90
Address@secenc_mhu_receiver_mot2se1 : 0x50017f90
Bits Name Description
31 - 3 -
 reserved
2 chcomb
Displays the status of the channel combined interrupt.
- A setting of 0b0 for this field indicates that an interrupt has not occurred on any channel.
- If this field is set to 0b1, then an interrupt has been generated on at least one channel.
There is no corresponding bit in the INT_CLR register. To clear the combined interrupt, software must clear the underlying interrupt.
1 - 0 -
 reserved


mhu_receiver_int_clr
Interrupt Clear register
W
0x00000000
Address@mot_mhu_receiver_app2mot0 : 0x1b000f94
Address@com_mhu_receiver_app2com0 : 0x1b000f94
Address@app_mhu_receiver_com2app0 : 0x1b010f94
Address@mot_mhu_receiver_app2mot1 : 0x1b020f94
Address@com_mhu_receiver_app2com1 : 0x1b020f94
Address@app_mhu_receiver_com2app1 : 0x1b030f94
Address@mot_mhu_receiver_se2mot0 : 0x1b040f94
Address@com_mhu_receiver_se2com0 : 0x1b040f94
Address@app_mhu_receiver_mot2app0 : 0x1b050f94
Address@mot_mhu_receiver_se2mot1 : 0x1b060f94
Address@com_mhu_receiver_se2com1 : 0x1b060f94
Address@app_mhu_receiver_mot2app1 : 0x1b070f94
Address@app_mhu_receiver_se2app0 : 0x1b810f94
Address@app_mhu_receiver_se2app1 : 0x1b830f94
Address@secenc_mhu_receiver_app2se0 : 0x50004f94
Address@secenc_mhu_receiver_app2se1 : 0x50006f94
Address@secenc_mhu_receiver_com2se0 : 0x50011f94
Address@secenc_mhu_receiver_com2se1 : 0x50013f94
Address@secenc_mhu_receiver_mot2se0 : 0x50015f94
Address@secenc_mhu_receiver_mot2se1 : 0x50017f94
Bits Reset value Name Description
31 - 0 0
mhu_receiver_int_clr


mhu_receiver_int_en
Interrupt Enable register
R/W
0x00000004
Address@mot_mhu_receiver_app2mot0 : 0x1b000f98
Address@com_mhu_receiver_app2com0 : 0x1b000f98
Address@app_mhu_receiver_com2app0 : 0x1b010f98
Address@mot_mhu_receiver_app2mot1 : 0x1b020f98
Address@com_mhu_receiver_app2com1 : 0x1b020f98
Address@app_mhu_receiver_com2app1 : 0x1b030f98
Address@mot_mhu_receiver_se2mot0 : 0x1b040f98
Address@com_mhu_receiver_se2com0 : 0x1b040f98
Address@app_mhu_receiver_mot2app0 : 0x1b050f98
Address@mot_mhu_receiver_se2mot1 : 0x1b060f98
Address@com_mhu_receiver_se2com1 : 0x1b060f98
Address@app_mhu_receiver_mot2app1 : 0x1b070f98
Address@app_mhu_receiver_se2app0 : 0x1b810f98
Address@app_mhu_receiver_se2app1 : 0x1b830f98
Address@secenc_mhu_receiver_app2se0 : 0x50004f98
Address@secenc_mhu_receiver_app2se1 : 0x50006f98
Address@secenc_mhu_receiver_com2se0 : 0x50011f98
Address@secenc_mhu_receiver_com2se1 : 0x50013f98
Address@secenc_mhu_receiver_mot2se0 : 0x50015f98
Address@secenc_mhu_receiver_mot2se1 : 0x50017f98
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "1"
chcomb
Enables and disables generation of the channel combined interrupt.
- Writing 0b1 to this field enables generation of the channel combined interrupt.
- Writing 0b0 to this field disables channel combined interrupt generation.
1 - 0 0
-
 reserved


mhu_receiver_chcomb_int_st0
Channel Combined Interrupt Status register 0
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa0
Address@com_mhu_receiver_app2com0 : 0x1b000fa0
Address@app_mhu_receiver_com2app0 : 0x1b010fa0
Address@mot_mhu_receiver_app2mot1 : 0x1b020fa0
Address@com_mhu_receiver_app2com1 : 0x1b020fa0
Address@app_mhu_receiver_com2app1 : 0x1b030fa0
Address@mot_mhu_receiver_se2mot0 : 0x1b040fa0
Address@com_mhu_receiver_se2com0 : 0x1b040fa0
Address@app_mhu_receiver_mot2app0 : 0x1b050fa0
Address@mot_mhu_receiver_se2mot1 : 0x1b060fa0
Address@com_mhu_receiver_se2com1 : 0x1b060fa0
Address@app_mhu_receiver_mot2app1 : 0x1b070fa0
Address@app_mhu_receiver_se2app0 : 0x1b810fa0
Address@app_mhu_receiver_se2app1 : 0x1b830fa0
Address@secenc_mhu_receiver_app2se0 : 0x50004fa0
Address@secenc_mhu_receiver_app2se1 : 0x50006fa0
Address@secenc_mhu_receiver_com2se0 : 0x50011fa0
Address@secenc_mhu_receiver_com2se1 : 0x50013fa0
Address@secenc_mhu_receiver_mot2se0 : 0x50015fa0
Address@secenc_mhu_receiver_mot2se1 : 0x50017fa0
Bits Name Description
31 - 0 ch_int_st0
Display the status of channel interrupts 0-31.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the CH_INT_STn registers of the Sender frame are set to 0b1 when the associated CH_INT_ST.CH_CLR field is set to 0b1.


mhu_receiver_chcomb_int_st1
Channel Combined Interrupt Status register 1
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa4
Address@com_mhu_receiver_app2com0 : 0x1b000fa4
Address@app_mhu_receiver_com2app0 : 0x1b010fa4
Address@mot_mhu_receiver_app2mot1 : 0x1b020fa4
Address@com_mhu_receiver_app2com1 : 0x1b020fa4
Address@app_mhu_receiver_com2app1 : 0x1b030fa4
Address@mot_mhu_receiver_se2mot0 : 0x1b040fa4
Address@com_mhu_receiver_se2com0 : 0x1b040fa4
Address@app_mhu_receiver_mot2app0 : 0x1b050fa4
Address@mot_mhu_receiver_se2mot1 : 0x1b060fa4
Address@com_mhu_receiver_se2com1 : 0x1b060fa4
Address@app_mhu_receiver_mot2app1 : 0x1b070fa4
Address@app_mhu_receiver_se2app0 : 0x1b810fa4
Address@app_mhu_receiver_se2app1 : 0x1b830fa4
Address@secenc_mhu_receiver_app2se0 : 0x50004fa4
Address@secenc_mhu_receiver_app2se1 : 0x50006fa4
Address@secenc_mhu_receiver_com2se0 : 0x50011fa4
Address@secenc_mhu_receiver_com2se1 : 0x50013fa4
Address@secenc_mhu_receiver_mot2se0 : 0x50015fa4
Address@secenc_mhu_receiver_mot2se1 : 0x50017fa4
Bits Name Description
31 - 0 ch_int_st1
Display the status of channel interrupts 32-63.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the CH_INT_STn registers of the Sender frame are set to 0b1 when the associated CH_INT_ST.CH_CLR field is set to 0b1.


mhu_receiver_chcomb_int_st2
Channel Combined Interrupt Status register 2
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fa8
Address@com_mhu_receiver_app2com0 : 0x1b000fa8
Address@app_mhu_receiver_com2app0 : 0x1b010fa8
Address@mot_mhu_receiver_app2mot1 : 0x1b020fa8
Address@com_mhu_receiver_app2com1 : 0x1b020fa8
Address@app_mhu_receiver_com2app1 : 0x1b030fa8
Address@mot_mhu_receiver_se2mot0 : 0x1b040fa8
Address@com_mhu_receiver_se2com0 : 0x1b040fa8
Address@app_mhu_receiver_mot2app0 : 0x1b050fa8
Address@mot_mhu_receiver_se2mot1 : 0x1b060fa8
Address@com_mhu_receiver_se2com1 : 0x1b060fa8
Address@app_mhu_receiver_mot2app1 : 0x1b070fa8
Address@app_mhu_receiver_se2app0 : 0x1b810fa8
Address@app_mhu_receiver_se2app1 : 0x1b830fa8
Address@secenc_mhu_receiver_app2se0 : 0x50004fa8
Address@secenc_mhu_receiver_app2se1 : 0x50006fa8
Address@secenc_mhu_receiver_com2se0 : 0x50011fa8
Address@secenc_mhu_receiver_com2se1 : 0x50013fa8
Address@secenc_mhu_receiver_mot2se0 : 0x50015fa8
Address@secenc_mhu_receiver_mot2se1 : 0x50017fa8
Bits Name Description
31 - 0 ch_int_st2
Display the status of channel interrupts 64-95.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
The fields within the CH_INT_STn registers of the Sender frame are set to 0b1 when the associated CH_INT_ST.CH_CLR field is set to 0b1.


mhu_receiver_chcomb_int_st3
Channel Combined Interrupt Status register 3
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fac
Address@com_mhu_receiver_app2com0 : 0x1b000fac
Address@app_mhu_receiver_com2app0 : 0x1b010fac
Address@mot_mhu_receiver_app2mot1 : 0x1b020fac
Address@com_mhu_receiver_app2com1 : 0x1b020fac
Address@app_mhu_receiver_com2app1 : 0x1b030fac
Address@mot_mhu_receiver_se2mot0 : 0x1b040fac
Address@com_mhu_receiver_se2com0 : 0x1b040fac
Address@app_mhu_receiver_mot2app0 : 0x1b050fac
Address@mot_mhu_receiver_se2mot1 : 0x1b060fac
Address@com_mhu_receiver_se2com1 : 0x1b060fac
Address@app_mhu_receiver_mot2app1 : 0x1b070fac
Address@app_mhu_receiver_se2app0 : 0x1b810fac
Address@app_mhu_receiver_se2app1 : 0x1b830fac
Address@secenc_mhu_receiver_app2se0 : 0x50004fac
Address@secenc_mhu_receiver_app2se1 : 0x50006fac
Address@secenc_mhu_receiver_com2se0 : 0x50011fac
Address@secenc_mhu_receiver_com2se1 : 0x50013fac
Address@secenc_mhu_receiver_mot2se0 : 0x50015fac
Address@secenc_mhu_receiver_mot2se1 : 0x50017fac
Bits Name Description
31 - 0 ch_int_st3
Display the status of channel interrupts 96-123.
Each bit indicates whether there is a pending interrupt on the corresponding channel.
Where a channel is not implemented, the corresponding bit is Reserved and treated as RAZ/WI.
In the CHCOMB_INT_ST3 register, bits[31:28] are always Reserved and treated as RAZ/WI.
The fields within the CH_INT_STn registers of the Sender frame are set to 0b1 when the associated CH_INT_ST.CH_CLR field is set to 0b1.


mhu_receiver_iidr
Implementer Identification Register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fc8
Address@com_mhu_receiver_app2com0 : 0x1b000fc8
Address@app_mhu_receiver_com2app0 : 0x1b010fc8
Address@mot_mhu_receiver_app2mot1 : 0x1b020fc8
Address@com_mhu_receiver_app2com1 : 0x1b020fc8
Address@app_mhu_receiver_com2app1 : 0x1b030fc8
Address@mot_mhu_receiver_se2mot0 : 0x1b040fc8
Address@com_mhu_receiver_se2com0 : 0x1b040fc8
Address@app_mhu_receiver_mot2app0 : 0x1b050fc8
Address@mot_mhu_receiver_se2mot1 : 0x1b060fc8
Address@com_mhu_receiver_se2com1 : 0x1b060fc8
Address@app_mhu_receiver_mot2app1 : 0x1b070fc8
Address@app_mhu_receiver_se2app0 : 0x1b810fc8
Address@app_mhu_receiver_se2app1 : 0x1b830fc8
Address@secenc_mhu_receiver_app2se0 : 0x50004fc8
Address@secenc_mhu_receiver_app2se1 : 0x50006fc8
Address@secenc_mhu_receiver_com2se0 : 0x50011fc8
Address@secenc_mhu_receiver_com2se1 : 0x50013fc8
Address@secenc_mhu_receiver_mot2se0 : 0x50015fc8
Address@secenc_mhu_receiver_mot2se1 : 0x50017fc8
Bits Name Description
31 - 20 product_id
Specifies the MHU part identifier.
19 - 16 variant
Specifies the MHU major revision number.
15 - 12 revision
Specifies the MHU minor revision number.
11 - 0 implementer
Specifies the JEDEC JEP106 manufacturers identification code for Arm.
Bits[11:8] contain the JEP106 continuation code for the implementer
Bit[7] must always be 0
Bits[6:0] give the JEP106 identity code for the implementer


mhu_receiver_aidr
Architecture Identification Register
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fcc
Address@com_mhu_receiver_app2com0 : 0x1b000fcc
Address@app_mhu_receiver_com2app0 : 0x1b010fcc
Address@mot_mhu_receiver_app2mot1 : 0x1b020fcc
Address@com_mhu_receiver_app2com1 : 0x1b020fcc
Address@app_mhu_receiver_com2app1 : 0x1b030fcc
Address@mot_mhu_receiver_se2mot0 : 0x1b040fcc
Address@com_mhu_receiver_se2com0 : 0x1b040fcc
Address@app_mhu_receiver_mot2app0 : 0x1b050fcc
Address@mot_mhu_receiver_se2mot1 : 0x1b060fcc
Address@com_mhu_receiver_se2com1 : 0x1b060fcc
Address@app_mhu_receiver_mot2app1 : 0x1b070fcc
Address@app_mhu_receiver_se2app0 : 0x1b810fcc
Address@app_mhu_receiver_se2app1 : 0x1b830fcc
Address@secenc_mhu_receiver_app2se0 : 0x50004fcc
Address@secenc_mhu_receiver_app2se1 : 0x50006fcc
Address@secenc_mhu_receiver_com2se0 : 0x50011fcc
Address@secenc_mhu_receiver_com2se1 : 0x50013fcc
Address@secenc_mhu_receiver_mot2se0 : 0x50015fcc
Address@secenc_mhu_receiver_mot2se1 : 0x50017fcc
Bits Name Description
31 - 8 -
 reserved
7 - 4 arch_major_rev
Specifies the MHU major architecture revision number.
- A value of 0x1 indicates that the MHU conforms to MHU architecture version 2.
- The setting 0x0 is Reserved.
When the ARCH_MAJOR_REV field is set to 0x0, the values in the ARCH_MINOR_REV field and IIDR register are RAZ.
Software must determine in a platform-specific manner the MHU architecture version to which the component conforms.
3 - 0 arch_minor_rev
Specifies the MHU minor architecture revision number.
A value of 0x0 indicates that the architecture minor revision number is 0, while a setting of 0x1 specifies a minor revision number of 1.
All other values are reserved.


mhu_receiver_pid4
Peripheral ID Register 4
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd0
Address@com_mhu_receiver_app2com0 : 0x1b000fd0
Address@app_mhu_receiver_com2app0 : 0x1b010fd0
Address@mot_mhu_receiver_app2mot1 : 0x1b020fd0
Address@com_mhu_receiver_app2com1 : 0x1b020fd0
Address@app_mhu_receiver_com2app1 : 0x1b030fd0
Address@mot_mhu_receiver_se2mot0 : 0x1b040fd0
Address@com_mhu_receiver_se2com0 : 0x1b040fd0
Address@app_mhu_receiver_mot2app0 : 0x1b050fd0
Address@mot_mhu_receiver_se2mot1 : 0x1b060fd0
Address@com_mhu_receiver_se2com1 : 0x1b060fd0
Address@app_mhu_receiver_mot2app1 : 0x1b070fd0
Address@app_mhu_receiver_se2app0 : 0x1b810fd0
Address@app_mhu_receiver_se2app1 : 0x1b830fd0
Address@secenc_mhu_receiver_app2se0 : 0x50004fd0
Address@secenc_mhu_receiver_app2se1 : 0x50006fd0
Address@secenc_mhu_receiver_com2se0 : 0x50011fd0
Address@secenc_mhu_receiver_com2se1 : 0x50013fd0
Address@secenc_mhu_receiver_mot2se0 : 0x50015fd0
Address@secenc_mhu_receiver_mot2se1 : 0x50017fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


mhu_receiver_pid5
Peripheral ID Register 5
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd4
Address@com_mhu_receiver_app2com0 : 0x1b000fd4
Address@app_mhu_receiver_com2app0 : 0x1b010fd4
Address@mot_mhu_receiver_app2mot1 : 0x1b020fd4
Address@com_mhu_receiver_app2com1 : 0x1b020fd4
Address@app_mhu_receiver_com2app1 : 0x1b030fd4
Address@mot_mhu_receiver_se2mot0 : 0x1b040fd4
Address@com_mhu_receiver_se2com0 : 0x1b040fd4
Address@app_mhu_receiver_mot2app0 : 0x1b050fd4
Address@mot_mhu_receiver_se2mot1 : 0x1b060fd4
Address@com_mhu_receiver_se2com1 : 0x1b060fd4
Address@app_mhu_receiver_mot2app1 : 0x1b070fd4
Address@app_mhu_receiver_se2app0 : 0x1b810fd4
Address@app_mhu_receiver_se2app1 : 0x1b830fd4
Address@secenc_mhu_receiver_app2se0 : 0x50004fd4
Address@secenc_mhu_receiver_app2se1 : 0x50006fd4
Address@secenc_mhu_receiver_com2se0 : 0x50011fd4
Address@secenc_mhu_receiver_com2se1 : 0x50013fd4
Address@secenc_mhu_receiver_mot2se0 : 0x50015fd4
Address@secenc_mhu_receiver_mot2se1 : 0x50017fd4
Bits Name Description
31 - 0 mhu_receiver_pid5


mhu_receiver_pid6
Peripheral ID Register 6
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fd8
Address@com_mhu_receiver_app2com0 : 0x1b000fd8
Address@app_mhu_receiver_com2app0 : 0x1b010fd8
Address@mot_mhu_receiver_app2mot1 : 0x1b020fd8
Address@com_mhu_receiver_app2com1 : 0x1b020fd8
Address@app_mhu_receiver_com2app1 : 0x1b030fd8
Address@mot_mhu_receiver_se2mot0 : 0x1b040fd8
Address@com_mhu_receiver_se2com0 : 0x1b040fd8
Address@app_mhu_receiver_mot2app0 : 0x1b050fd8
Address@mot_mhu_receiver_se2mot1 : 0x1b060fd8
Address@com_mhu_receiver_se2com1 : 0x1b060fd8
Address@app_mhu_receiver_mot2app1 : 0x1b070fd8
Address@app_mhu_receiver_se2app0 : 0x1b810fd8
Address@app_mhu_receiver_se2app1 : 0x1b830fd8
Address@secenc_mhu_receiver_app2se0 : 0x50004fd8
Address@secenc_mhu_receiver_app2se1 : 0x50006fd8
Address@secenc_mhu_receiver_com2se0 : 0x50011fd8
Address@secenc_mhu_receiver_com2se1 : 0x50013fd8
Address@secenc_mhu_receiver_mot2se0 : 0x50015fd8
Address@secenc_mhu_receiver_mot2se1 : 0x50017fd8
Bits Name Description
31 - 0 mhu_receiver_pid6


mhu_receiver_pid7
Peripheral ID Register 7
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fdc
Address@com_mhu_receiver_app2com0 : 0x1b000fdc
Address@app_mhu_receiver_com2app0 : 0x1b010fdc
Address@mot_mhu_receiver_app2mot1 : 0x1b020fdc
Address@com_mhu_receiver_app2com1 : 0x1b020fdc
Address@app_mhu_receiver_com2app1 : 0x1b030fdc
Address@mot_mhu_receiver_se2mot0 : 0x1b040fdc
Address@com_mhu_receiver_se2com0 : 0x1b040fdc
Address@app_mhu_receiver_mot2app0 : 0x1b050fdc
Address@mot_mhu_receiver_se2mot1 : 0x1b060fdc
Address@com_mhu_receiver_se2com1 : 0x1b060fdc
Address@app_mhu_receiver_mot2app1 : 0x1b070fdc
Address@app_mhu_receiver_se2app0 : 0x1b810fdc
Address@app_mhu_receiver_se2app1 : 0x1b830fdc
Address@secenc_mhu_receiver_app2se0 : 0x50004fdc
Address@secenc_mhu_receiver_app2se1 : 0x50006fdc
Address@secenc_mhu_receiver_com2se0 : 0x50011fdc
Address@secenc_mhu_receiver_com2se1 : 0x50013fdc
Address@secenc_mhu_receiver_mot2se0 : 0x50015fdc
Address@secenc_mhu_receiver_mot2se1 : 0x50017fdc
Bits Name Description
31 - 0 mhu_receiver_pid7


mhu_receiver_pid0
Peripheral ID Register 0
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe0
Address@com_mhu_receiver_app2com0 : 0x1b000fe0
Address@app_mhu_receiver_com2app0 : 0x1b010fe0
Address@mot_mhu_receiver_app2mot1 : 0x1b020fe0
Address@com_mhu_receiver_app2com1 : 0x1b020fe0
Address@app_mhu_receiver_com2app1 : 0x1b030fe0
Address@mot_mhu_receiver_se2mot0 : 0x1b040fe0
Address@com_mhu_receiver_se2com0 : 0x1b040fe0
Address@app_mhu_receiver_mot2app0 : 0x1b050fe0
Address@mot_mhu_receiver_se2mot1 : 0x1b060fe0
Address@com_mhu_receiver_se2com1 : 0x1b060fe0
Address@app_mhu_receiver_mot2app1 : 0x1b070fe0
Address@app_mhu_receiver_se2app0 : 0x1b810fe0
Address@app_mhu_receiver_se2app1 : 0x1b830fe0
Address@secenc_mhu_receiver_app2se0 : 0x50004fe0
Address@secenc_mhu_receiver_app2se1 : 0x50006fe0
Address@secenc_mhu_receiver_com2se0 : 0x50011fe0
Address@secenc_mhu_receiver_com2se1 : 0x50013fe0
Address@secenc_mhu_receiver_mot2se0 : 0x50015fe0
Address@secenc_mhu_receiver_mot2se1 : 0x50017fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


mhu_receiver_pid1
Peripheral ID Register 1
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe4
Address@com_mhu_receiver_app2com0 : 0x1b000fe4
Address@app_mhu_receiver_com2app0 : 0x1b010fe4
Address@mot_mhu_receiver_app2mot1 : 0x1b020fe4
Address@com_mhu_receiver_app2com1 : 0x1b020fe4
Address@app_mhu_receiver_com2app1 : 0x1b030fe4
Address@mot_mhu_receiver_se2mot0 : 0x1b040fe4
Address@com_mhu_receiver_se2com0 : 0x1b040fe4
Address@app_mhu_receiver_mot2app0 : 0x1b050fe4
Address@mot_mhu_receiver_se2mot1 : 0x1b060fe4
Address@com_mhu_receiver_se2com1 : 0x1b060fe4
Address@app_mhu_receiver_mot2app1 : 0x1b070fe4
Address@app_mhu_receiver_se2app0 : 0x1b810fe4
Address@app_mhu_receiver_se2app1 : 0x1b830fe4
Address@secenc_mhu_receiver_app2se0 : 0x50004fe4
Address@secenc_mhu_receiver_app2se1 : 0x50006fe4
Address@secenc_mhu_receiver_com2se0 : 0x50011fe4
Address@secenc_mhu_receiver_com2se1 : 0x50013fe4
Address@secenc_mhu_receiver_mot2se0 : 0x50015fe4
Address@secenc_mhu_receiver_mot2se1 : 0x50017fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


mhu_receiver_pid2
Peripheral ID Register 2
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fe8
Address@com_mhu_receiver_app2com0 : 0x1b000fe8
Address@app_mhu_receiver_com2app0 : 0x1b010fe8
Address@mot_mhu_receiver_app2mot1 : 0x1b020fe8
Address@com_mhu_receiver_app2com1 : 0x1b020fe8
Address@app_mhu_receiver_com2app1 : 0x1b030fe8
Address@mot_mhu_receiver_se2mot0 : 0x1b040fe8
Address@com_mhu_receiver_se2com0 : 0x1b040fe8
Address@app_mhu_receiver_mot2app0 : 0x1b050fe8
Address@mot_mhu_receiver_se2mot1 : 0x1b060fe8
Address@com_mhu_receiver_se2com1 : 0x1b060fe8
Address@app_mhu_receiver_mot2app1 : 0x1b070fe8
Address@app_mhu_receiver_se2app0 : 0x1b810fe8
Address@app_mhu_receiver_se2app1 : 0x1b830fe8
Address@secenc_mhu_receiver_app2se0 : 0x50004fe8
Address@secenc_mhu_receiver_app2se1 : 0x50006fe8
Address@secenc_mhu_receiver_com2se0 : 0x50011fe8
Address@secenc_mhu_receiver_com2se1 : 0x50013fe8
Address@secenc_mhu_receiver_mot2se0 : 0x50015fe8
Address@secenc_mhu_receiver_mot2se1 : 0x50017fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


mhu_receiver_pid3
Peripheral ID Register 3
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000fec
Address@com_mhu_receiver_app2com0 : 0x1b000fec
Address@app_mhu_receiver_com2app0 : 0x1b010fec
Address@mot_mhu_receiver_app2mot1 : 0x1b020fec
Address@com_mhu_receiver_app2com1 : 0x1b020fec
Address@app_mhu_receiver_com2app1 : 0x1b030fec
Address@mot_mhu_receiver_se2mot0 : 0x1b040fec
Address@com_mhu_receiver_se2com0 : 0x1b040fec
Address@app_mhu_receiver_mot2app0 : 0x1b050fec
Address@mot_mhu_receiver_se2mot1 : 0x1b060fec
Address@com_mhu_receiver_se2com1 : 0x1b060fec
Address@app_mhu_receiver_mot2app1 : 0x1b070fec
Address@app_mhu_receiver_se2app0 : 0x1b810fec
Address@app_mhu_receiver_se2app1 : 0x1b830fec
Address@secenc_mhu_receiver_app2se0 : 0x50004fec
Address@secenc_mhu_receiver_app2se1 : 0x50006fec
Address@secenc_mhu_receiver_com2se0 : 0x50011fec
Address@secenc_mhu_receiver_com2se1 : 0x50013fec
Address@secenc_mhu_receiver_mot2se0 : 0x50015fec
Address@secenc_mhu_receiver_mot2se1 : 0x50017fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


mhu_receiver_cid0
Component ID Register 0
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff0
Address@com_mhu_receiver_app2com0 : 0x1b000ff0
Address@app_mhu_receiver_com2app0 : 0x1b010ff0
Address@mot_mhu_receiver_app2mot1 : 0x1b020ff0
Address@com_mhu_receiver_app2com1 : 0x1b020ff0
Address@app_mhu_receiver_com2app1 : 0x1b030ff0
Address@mot_mhu_receiver_se2mot0 : 0x1b040ff0
Address@com_mhu_receiver_se2com0 : 0x1b040ff0
Address@app_mhu_receiver_mot2app0 : 0x1b050ff0
Address@mot_mhu_receiver_se2mot1 : 0x1b060ff0
Address@com_mhu_receiver_se2com1 : 0x1b060ff0
Address@app_mhu_receiver_mot2app1 : 0x1b070ff0
Address@app_mhu_receiver_se2app0 : 0x1b810ff0
Address@app_mhu_receiver_se2app1 : 0x1b830ff0
Address@secenc_mhu_receiver_app2se0 : 0x50004ff0
Address@secenc_mhu_receiver_app2se1 : 0x50006ff0
Address@secenc_mhu_receiver_com2se0 : 0x50011ff0
Address@secenc_mhu_receiver_com2se1 : 0x50013ff0
Address@secenc_mhu_receiver_mot2se0 : 0x50015ff0
Address@secenc_mhu_receiver_mot2se1 : 0x50017ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


mhu_receiver_cid1
Component ID Register 1
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff4
Address@com_mhu_receiver_app2com0 : 0x1b000ff4
Address@app_mhu_receiver_com2app0 : 0x1b010ff4
Address@mot_mhu_receiver_app2mot1 : 0x1b020ff4
Address@com_mhu_receiver_app2com1 : 0x1b020ff4
Address@app_mhu_receiver_com2app1 : 0x1b030ff4
Address@mot_mhu_receiver_se2mot0 : 0x1b040ff4
Address@com_mhu_receiver_se2com0 : 0x1b040ff4
Address@app_mhu_receiver_mot2app0 : 0x1b050ff4
Address@mot_mhu_receiver_se2mot1 : 0x1b060ff4
Address@com_mhu_receiver_se2com1 : 0x1b060ff4
Address@app_mhu_receiver_mot2app1 : 0x1b070ff4
Address@app_mhu_receiver_se2app0 : 0x1b810ff4
Address@app_mhu_receiver_se2app1 : 0x1b830ff4
Address@secenc_mhu_receiver_app2se0 : 0x50004ff4
Address@secenc_mhu_receiver_app2se1 : 0x50006ff4
Address@secenc_mhu_receiver_com2se0 : 0x50011ff4
Address@secenc_mhu_receiver_com2se1 : 0x50013ff4
Address@secenc_mhu_receiver_mot2se0 : 0x50015ff4
Address@secenc_mhu_receiver_mot2se1 : 0x50017ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


mhu_receiver_cid2
Component ID Register 2
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000ff8
Address@com_mhu_receiver_app2com0 : 0x1b000ff8
Address@app_mhu_receiver_com2app0 : 0x1b010ff8
Address@mot_mhu_receiver_app2mot1 : 0x1b020ff8
Address@com_mhu_receiver_app2com1 : 0x1b020ff8
Address@app_mhu_receiver_com2app1 : 0x1b030ff8
Address@mot_mhu_receiver_se2mot0 : 0x1b040ff8
Address@com_mhu_receiver_se2com0 : 0x1b040ff8
Address@app_mhu_receiver_mot2app0 : 0x1b050ff8
Address@mot_mhu_receiver_se2mot1 : 0x1b060ff8
Address@com_mhu_receiver_se2com1 : 0x1b060ff8
Address@app_mhu_receiver_mot2app1 : 0x1b070ff8
Address@app_mhu_receiver_se2app0 : 0x1b810ff8
Address@app_mhu_receiver_se2app1 : 0x1b830ff8
Address@secenc_mhu_receiver_app2se0 : 0x50004ff8
Address@secenc_mhu_receiver_app2se1 : 0x50006ff8
Address@secenc_mhu_receiver_com2se0 : 0x50011ff8
Address@secenc_mhu_receiver_com2se1 : 0x50013ff8
Address@secenc_mhu_receiver_mot2se0 : 0x50015ff8
Address@secenc_mhu_receiver_mot2se1 : 0x50017ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


mhu_receiver_cid3
Component ID Register 3
R
Address@mot_mhu_receiver_app2mot0 : 0x1b000ffc
Address@com_mhu_receiver_app2com0 : 0x1b000ffc
Address@app_mhu_receiver_com2app0 : 0x1b010ffc
Address@mot_mhu_receiver_app2mot1 : 0x1b020ffc
Address@com_mhu_receiver_app2com1 : 0x1b020ffc
Address@app_mhu_receiver_com2app1 : 0x1b030ffc
Address@mot_mhu_receiver_se2mot0 : 0x1b040ffc
Address@com_mhu_receiver_se2com0 : 0x1b040ffc
Address@app_mhu_receiver_mot2app0 : 0x1b050ffc
Address@mot_mhu_receiver_se2mot1 : 0x1b060ffc
Address@com_mhu_receiver_se2com1 : 0x1b060ffc
Address@app_mhu_receiver_mot2app1 : 0x1b070ffc
Address@app_mhu_receiver_se2app0 : 0x1b810ffc
Address@app_mhu_receiver_se2app1 : 0x1b830ffc
Address@secenc_mhu_receiver_app2se0 : 0x50004ffc
Address@secenc_mhu_receiver_app2se1 : 0x50006ffc
Address@secenc_mhu_receiver_com2se0 : 0x50011ffc
Address@secenc_mhu_receiver_com2se1 : 0x50013ffc
Address@secenc_mhu_receiver_mot2se0 : 0x50015ffc
Address@secenc_mhu_receiver_mot2se1 : 0x50017ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: int_apbcom

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R apbcom_romentry0
1-33f 4-cfc -  reserved
340 d00 R apbcom_vidr
341 d04 -  reserved
342 d08 R apbcom_fidtxr
343 d0c R apbcom_fidrxr
344 d10 R/W apbcom_icsr
345-347 d14-d1c -  reserved
348 d20 R/W apbcom_dr
349-34a d24-d28 -  reserved
34b d2c R/W apbcom_sr0
34c d30 R/W apbcom_dbr
34d-34e d34-d38 -  reserved
34f d3c R/W apbcom_sr1
350-3be d40-ef8 -  reserved
3bf efc R apbcom_itstatus
3c0 f00 R/W apbcom_itctrl
3c1-3e7 f04-f9c -  reserved
3e8 fa0 R/W apbcom_claimset
3e9 fa4 R/W apbcom_claimclr
3ea fa8 R apbcom_devaff0
3eb fac R apbcom_devaff1
3ec fb0 R apbcom_lar
3ed fb4 R apbcom_lsr
3ee fb8 R apbcom_authstatus
3ef fbc R apbcom_devarch
3f0 fc0 R apbcom_devid2
3f1 fc4 R apbcom_devid1
3f2 fc8 R apbcom_devid
3f3 fcc R apbcom_devtype
3f4 fd0 R apbcom_pidr4
3f5 fd4 R apbcom_pidr5
3f6 fd8 R apbcom_pidr6
3f7 fdc R apbcom_pidr7
3f8 fe0 R apbcom_pidr0
3f9 fe4 R apbcom_pidr1
3fa fe8 R apbcom_pidr2
3fb fec R apbcom_pidr3
3fc ff0 R apbcom_cidr0
3fd ff4 R apbcom_cidr1
3fe ff8 R apbcom_cidr2
3ff ffc R apbcom_cidr3

apbcom_romentry0
Class 0x9 ROM Table entry
R
Address : 0x1b900000
Bits Name Description
31 - 22 -
 reserved
21 - 12 offset
ROM_ENTRY0[31:12]
Defined by the parameter ROM_ENTRY0. These are the upper bits of the relative address of the ROM table of the target system.
11 - 3 -
 reserved
2 poweridvalid
0: No standard power control
1 - 0 present
Indicates whether an entry is present at this location in the ROM Table.
This field can have one of the following values:
0b10: The ROM entry is not present, and this ROMENTRY is not the final entry in a ROM Table with fewer than the maximum number of entries.
This value is set when all debug is disabled on the authentication interface.
0b11: The ROM Entry is present. This value is set when any debug is allowed on the authentication interface.


apbcom_vidr
Version ID Register
R
Address : 0x1b900d00
Bits Name Description
31 - 8 -
 reserved
7 - 4 protversion
APBCOM Protocol version. The value of this field is:
0x0 .. APBCOM Protocol version 0 implemented
3 - 0 pmversion
APBCOM Programmers model version. The value of this field is:
0x0 .. APBCOM Programmers model version 0 implemented.


apbcom_fidtxr
Feature ID TxEngine Register
R
Address : 0x1b900d08
Bits Name Description
31 - 20 -
 reserved
19 - 16 txfd
TxEngine FIFO depth. The defined value of this field is:
0x0: TxEngine FIFO has a capacity of 1 byte.
15 - 11 -
 reserved
10 txsz32
TxEngine 32-bit write support. The defined value of this bit is:
0x1: TxEngine supports 32-bit wide writes.
9 txsz16
TxEngine 16-bit write support. The defined value of this bit is:
0x0: TxEngine does not support 16-bit wide writes.
8 txsz8
TxEngine 8-bit write support. The defined value of this bit is:
0x0: TxEngine does not support 8-bit wide writes.
7 - 4 txw
TxEngine Width. Indicates the implemented width of the TxEngine. The defined value of this field is:
0x1: 1-byte wide TxEngine. The upper bytes must be the NULL flag (0xAF).
        For example, to write 0x12 to the TxEngine, the APB write data is 0xAFAFAF12.
3 - 2 -
 reserved
1 txint
Indicates whether the TxEngine generates interrupts. The defined values of this bit are:
0x0: TxEngine interrupts not implemented.
0x1: TxEngine interrupts implemented.
0 txi
Indicates whether the TxEngine is implemented. The defined value of this bit is:
0x1: TxEngine implemented


apbcom_fidrxr
Feature ID RxEngine Register
R
Address : 0x1b900d0c
Bits Name Description
31 - 20 -
 reserved
19 - 16 rxfd
RxEngine FIFO depth. The defined value of this field is:
0x0: RxEngine FIFO has a capacity of 1 byte.
15 - 11 -
 reserved
10 rxsz32
RxEngine 32-bit read support. The defined value of this bit is:
0x1: RxEngine supports 32-bit wide reads.
9 rxsz16
RxEngine 16-bit read support. The defined value of this bit is:
0x0: RxEngine does not support 16-bit wide reads.
8 rxsz8
RxEngine 8-bit read support. The defined value of this bit is:
0x0: RxEngine does not support 8-bit wide reads.
7 - 2 -
 reserved
1 rxint
Indicates whether the RxEngine generates interrupts. The defined values of this bit are:
0x0: RxEngine interrupts not implemented.
0x1: RxEngine interrupts implemented.
0 rxi
Indicates whether the RxEngine is implemented. The defined value of this bit is:
0x1: RxEngine implemented


apbcom_icsr
Interrupt Control Status Register
R/W
0x00000000
Address : 0x1b900d10
Bits Reset value Name Description
31 "0"
rxfis
RxEngine FIFO interrupt status. The possible values of this bit are:
0x0 RxEngine FIFO interrupt has not occurred.
0x1 RxEngine FIFO interrupt has occurred.
This bit is RES0 in the External COM Port modules.
This bit is read/write-one-to-clear. This bit cannot be cleared while there is a triggering condition, such as rxfil = 1 and RxFIFO is full.
This bit resets to 0x0.
30 - 20 0
-
 reserved
19 - 16 "0000"
rxfil
RxEngine FIFO interrupt level select. The possible values of this field are:
0x0 RxEngine FIFO interrupts disabled.
0x1-0xF Generate RxEngine FIFO interrupt when the RxEngine FIFO is full. This occurs when the number of bytes stored reaches the value defined by fidrxr.rxfd.
This field is RES0 in the External COM Port modules.
This field is read/write.
This field resets to 0x1.
15 "0"
txfis
TxEngine FIFO interrupt status. The possible values of this bit are:
0x0 TxEngine FIFO interrupt has not occurred.
0x1 TxEngine FIFO interrupt has occurred.
This bit is RES0 in the External COM Port modules.
This bit is read/write-one-to-clear. This bit cannot be cleared while there is a triggering condition, such as txfil = 1 and TxFIFO is empty.
This bit resets to 0x0.
14 - 4 0
-
 reserved
3 - 0 "0000"
txfil
TxEngine FIFO interrupt level select. The possible values of this field are:
0x0 TxEngine FIFO interrupts disabled.
0x1-0xF Generate TxEngine FIFO interrupt when the TxEngine FIFO has less than the specified number of bytes remaining to process.
- Note -
If txfil is set to a value higher than 1, the IRQ will be continuously generated.

This field is RES0 in the external COM Port modules.
This field is read/write.
This field resets to 0x0.


apbcom_dr
Data Register
R/W
0x00000000
Address : 0x1b900d20
Bits Reset value Name Description
31 - 0 0x0
data
Data transfer. Only 32-bit accesses are supported to DR.
On writes:
- Transfers the lowest byte into the TxEngine FIFO for transmission.
- The upper bytes must be written with the NULL Flag byte value.
- The TxEngine ignores the NULL Flag byte value.
- If TxEngine FIFO is not empty and the byte to be transmitted to the TxEngine is not a NULL Flag byte, a TxEngine Overflow error occurs and sr.txoe is set to 1. The byte is discarded by the TxEngine.
- If sr.txoe or sr.txle is 1, then writes are ignored.
- Write accesses complete immediately.
On reads:
- Returns one byte from the RxEngine FIFO at the lowest byte.
- If the RxEngine FIFO is empty, the lowest byte returns the NULL Flag byte. The upper bytes always return the NULL Flag byte value of 0xAF.
- Read accesses complete immediately.


apbcom_sr0
Status Register
R/W
0x00000000
Address : 0x1b900d2c
Bits Reset value Name Description
31 "0"
pen
COM Port component enabled status. The defined values of this bit are:
0x0 Component is disabled.
       - Writes to DR and DBR are ignored.
       - Reads of DR and DBR behave as if the RxEngine FIFO is empty.
0x1 Component is enabled.
This bit is read-only.
Reading this bit returns the value of the CFG_PEN input on the External components and 0x1 on the Internal APBCOM.
30 "0"
rxle
RxEngine link error detected.
This bit is RES0 because no link error can occur in the SDC-600 RxEngine.
29 - 24 0
-
 reserved
23 - 16 "00000000"
rxf
RxEngine FIFO fill level. The possible values of this field are:
0x00 RxEngine has no data.
0x01 RxEngine has at least 1 byte available to read.
This field is read-only.
This field resets to 0x00.
15 "0"
trinprog
Transfer in progress. This bit is set when a transaction is aborted via DP_ABORT.
The possible values of this bit are:
0x0 No transaction in progress.
0x1 An input transaction has been aborted but the internal operation of that transaction, or a previous transaction, is still in progress.
This bit is RES0 in the External APBCOM for Integrated Cortex-M DAP and the Internal APBCOM components.
This bit resets to 0x0.
14 "0"
txle
TxEngine link error detected. The possible values of this bit are:
0x0 No link error detected.
0x1 A link error has been detected in the TxEngine.
This bit is set to 1 if:
- The link is lost during a data transfer because the remote Rx interface module is not operating.
 A LERR flag byte is inserted into the local Rx FIFO.
- One or more bytes written to the Tx FIFO are discarded because the link to the remote Rx interface module is not operating. A LERR flag byte is inserted into the local Rx FIFO.
This bit is read/write-one-to-clear.
This bit resets to 0x0.
13 "0"
txoe
TxEngine FIFO overflow. The possible values of this bit are:
0x0 No overflow logged.
0x1 At least one byte written to TxEngine could not be accepted and has been lost.
This bit is read/write-one-to-clear.
This bit resets to 0x0.
12 "0"
rrdis
Remote reboot requests disabled. The defined values of this bit are:
0x0 Remote Reboot requests enabled.
0x1 Remote Reboot requests disabled.
When this bit is 1, the TxEngine discards any LPH2RR Flag bytes written to the TxEngine.
This bit is read-only.
Reading this bit returns the value of the CFG_RRDIS input after synchronization in the External components and 0x1 in the Internal APBCOM.
11 - 8 0
-
 reserved
7 - 0 "00000000"
txs
TxEngine FIFO space. The defined values of this field are:
0x00 TxEngine has no space for new data.
0b1 TxEngine has at least 1 byte available.
This field resets to 0x01.
This field is read-only.


apbcom_dbr
Data Blocking Register
R/W
0x00000000
Address : 0x1b900d30
Bits Reset value Name Description
31 - 0 0x0
data
Data transfer. Only 32-bit access size is supported to DBR.
On writes:
- Transfers the lowest byte into the TxEngine FIFO for transmission.
- The upper bytes must be written with the NULL Flag byte value.
- The TxEngine ignores the NULL Flag byte value.
- If TxEngine FIFO is not empty and the byte to be transmitted to the TxEngine is not a NULL Flag byte, the write to the DBR stalls until the FIFO empties.
- If sr.txoe or sr.txle is 1, then writes are ignored.
- If sr.txle is 1, then writes are ignored and any outstanding write access is terminated with an OK response.
On reads:
- Returns one byte from the RxEngine FIFO at the lowest byte.
- If the RxEngine FIFO is empty, the lowest byte returns the NULL Flag byte.
The upper bytes always return the NULL Flag byte.
- Read accesses complete immediately.


apbcom_sr1
Status Register
R/W
0x00000000
Address : 0x1b900d3c
Bits Reset value Name Description
31 "0"
pen
COM Port component enabled status. The defined values of this bit are:
0x0 Component is disabled.
- Writes to DR and DBR are ignored.
- Reads of DR and DBR behave as if the RxEngine FIFO is empty.
0x1 Component is enabled.
This bit is read-only.
Reading this bit returns the value of the CFG_PEN input on the External components and 0x1 on the Internal APBCOM.
30 "0"
rxle
RxEngine link error detected.
This bit is RES0 because no link error can occur in the SDC-600 RxEngine.
29 - 24 0
-
 reserved
23 - 16 "00000000"
rxf
RxEngine FIFO fill level. The possible values of this field are:
0x00 RxEngine has no data.
0x01 RxEngine has at least 1 byte available to read.
This field is read-only.
This field resets to 0x00.
15 "0"
trinprog
Transfer in progress. This bit is set when a transaction is aborted via DP_ABORT.
The possible values of this bit are:
0x0 No transaction in progress.
0x1 An input transaction has been aborted but the internal operation of that transaction, or a previous transaction, is still in progress.
This bit is RES0 in the External APBCOM for Integrated Cortex-M DAP and the Internal APBCOM components.
This bit resets to 0x0.
14 "0"
txle
TxEngine link error detected. The possible values of this bit are:
0x0 No link error detected.
0x1 A link error has been detected in the TxEngine.
This bit is set to 1 if:
- The link is lost during a data transfer because the remote Rx interface module is not operating.
 A LERR flag byte is inserted into the local Rx FIFO.
- One or more bytes written to the Tx FIFO are discarded because the link to the remote Rx interface module is not operating. A LERR flag byte is inserted into the local Rx FIFO.
This bit is read/write-one-to-clear.
This bit resets to 0x0.
13 "0"
txoe
TxEngine FIFO overflow. The possible values of this bit are:
0x0 No overflow logged.
0x1 At least one byte written to TxEngine could not be accepted and has been lost.
This bit is read/write-one-to-clear.
This bit resets to 0x0.
12 "0"
rrdis
Remote reboot requests disabled. The defined values of this bit are:
0x0 Remote Reboot requests enabled.
0x1 Remote Reboot requests disabled.
When this bit is 1, the TxEngine discards any LPH2RR Flag bytes written to the TxEngine.
This bit is read-only.
Reading this bit returns the value of the CFG_RRDIS input after synchronization in the External components and 0x1 in the Internal APBCOM.
11 - 8 0
-
 reserved
7 - 0 "00000000"
txs
TxEngine FIFO space. The defined values of this field are:
0x00 TxEngine has no space for new data.
0b1 TxEngine has at least 1 byte available.
This field resets to 0x01.
This field is read-only.


apbcom_itstatus
Integration Mode Status Register
R
Address : 0x1b900efc
Bits Name Description
31 - 1 -
 reserved
0 dpabort
In integration testing mode, when itctrl.ime = 1, this bit latches to 1 on the rising edge of DP_ABORT.
The possible values of this bit are:
0x0 No rising edge of DP_ABORT has been detected.
0x1 Rising edge has been detected on DP_ABORT.
This bit is cleared on APB read from this register. If DP_ABORT rises in the same cycle when an APB read of the itstatus register is received, the APB read takes priority and the register is cleared as a result.
In mission mode, when itctrl.ime = 0, this register is RAZ/WI.
This bit resets to 0x0.


apbcom_itctrl
Integration Mode Control Register
R/W
0x00000000
Address : 0x1b900f00
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
ime
Integration Mode Enable. When set, the APBCOM enters integration mode, which allows integration testing to be performed.
The possible values of this bit are:
0x0 Functional mode.
0x1 Integration test mode.
This bit resets to 0x0.


apbcom_claimset
Claim Tag Set Register
R/W
0x00000000
Address : 0x1b900fa0
Bits Reset value Name Description
31 - 0 0
apbcom_claimset


apbcom_claimclr
Claim Tag Clear Register
R/W
0x00000000
Address : 0x1b900fa4
Bits Reset value Name Description
31 - 0 0
apbcom_claimclr


apbcom_devaff0
Device Affinity Register 0
R
Address : 0x1b900fa8
Bits Name Description
31 - 0 apbcom_devaff0


apbcom_devaff1
Device Affinity Register 1
R
Address : 0x1b900fac
Bits Name Description
31 - 0 apbcom_devaff1


apbcom_lar
Software Lock Access Register
R
Address : 0x1b900fb0
Bits Name Description
31 - 0 apbcom_lar


apbcom_lsr
Software Lock Status Register
R
Address : 0x1b900fb4
Bits Name Description
31 - 0 apbcom_lsr


apbcom_authstatus
Authentication Status Register
R
Address : 0x1b900fb8
Bits Name Description
31 - 0 apbcom_authstatus


apbcom_devarch
Device Architecture Register
R
Address : 0x1b900fbc
Bits Name Description
31 - 0 value



apbcom_devid2
Device Configuration Register 2
R
Address : 0x1b900fc0
Bits Name Description
31 - 0 value



apbcom_devid1
Device Configuration Register 1
R
Address : 0x1b900fc4
Bits Name Description
31 - 0 value



apbcom_devid
Device ID Register
R
Address : 0x1b900fc8
Bits Name Description
31 - 7 -
 reserved
6 cp
COM Port functionality present. The offset range 0xD00-0xD7C contains COM Port functionality.
Offset 0xD00 indicates the COM Port programmers model.
The value of this bit is:
0b1 COM Port functionality present.
5 prr
Powerup Request functionality included. The value of this bit is:
0b0 Powerup Request functionality not included.
4 sysmem
System memory present. Indicates whether system memory is present on the bus that connects to the ROM table.
The value of this bit is:
0b1 System memory is present on the bus that connects to the ROM table.
3 - 0 format
ROM format. The value of this field is:
0x0 32-bit format 0.


apbcom_devtype
Device Type Identifier Register
R
Address : 0x1b900fcc
Bits Name Description
31 - 0 value



apbcom_pidr4
Peripheral ID Register 4
R
Address : 0x1b900fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


apbcom_pidr5
Peripheral ID Register 5
R
Address : 0x1b900fd4
Bits Name Description
31 - 0 apbcom_pidr5


apbcom_pidr6
Peripheral ID Register 6
R
Address : 0x1b900fd8
Bits Name Description
31 - 0 apbcom_pidr6


apbcom_pidr7
Peripheral ID Register 7
R
Address : 0x1b900fdc
Bits Name Description
31 - 0 apbcom_pidr7


apbcom_pidr0
Peripheral ID Register 0
R
Address : 0x1b900fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


apbcom_pidr1
Peripheral ID Register 1
R
Address : 0x1b900fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


apbcom_pidr2
Peripheral ID Register 2
R
Address : 0x1b900fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


apbcom_pidr3
Peripheral ID Register 3
R
Address : 0x1b900fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


apbcom_cidr0
Component ID Register 0
R
Address : 0x1b900ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


apbcom_cidr1
Component ID Register 1
R
Address : 0x1b900ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


apbcom_cidr2
Component ID Register 2
R
Address : 0x1b900ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


apbcom_cidr3
Component ID Register 3
R
Address : 0x1b900ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: app_gic_distributor

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gic_distributor_gicd_ctlr
1 4 R gic_distributor_gicd_typer
2 8 R gic_distributor_gicd_iidr
3-1f c-7c -  reserved
20 80 R/W gic_distributor_gicd_igroupr0
21-2e 84-b8 -  reserved
2f bc R/W gic_distributor_gicd_igroupr15
30-3f c0-fc -  reserved
40 100 R/W gic_distributor_gicd_isenabler0
41-4e 104-138 -  reserved
4f 13c R/W gic_distributor_gicd_isenabler15
50-5f 140-17c -  reserved
60 180 R/W gic_distributor_gicd_icenabler0
61-6e 184-1b8 -  reserved
6f 1bc R/W gic_distributor_gicd_icenabler15
70-7f 1c0-1fc -  reserved
80 200 R/W gic_distributor_gicd_ispendr0
81-8e 204-238 -  reserved
8f 23c R/W gic_distributor_gicd_ispendr15
90-9f 240-27c -  reserved
a0 280 R/W gic_distributor_gicd_icpendr0
a1-ae 284-2b8 -  reserved
af 2bc R/W gic_distributor_gicd_icpendr15
b0-bf 2c0-2fc -  reserved
c0 300 R/W gic_distributor_gicd_isactiver0
c1-ce 304-338 -  reserved
cf 33c R/W gic_distributor_gicd_isactiver15
d0-df 340-37c -  reserved
e0 380 R/W gic_distributor_gicd_icactiver0
e1-ee 384-3b8 -  reserved
ef 3bc R/W gic_distributor_gicd_icactiver15
f0-ff 3c0-3fc -  reserved
100 400 R/W gic_distributor_gicd_ipriorityr0
101-17e 404-5f8 -  reserved
17f 5fc R/W gic_distributor_gicd_ipriorityr127
180-1ff 600-7fc -  reserved
200 800 R gic_distributor_gicd_itargetsr0
201-27e 804-9f8 -  reserved
27f 9fc R/W gic_distributor_gicd_itargetsr127
280-2ff a00-bfc -  reserved
300 c00 R gic_distributor_gicd_icfgr0
301-30e c04-c38 -  reserved
30f c3c R/W gic_distributor_gicd_icfgr15
310-33f c40-cfc -  reserved
340 d00 R gic_distributor_gicd_ppisr
341 d04 R gic_distributor_gicd_spisr0
342-34e d08-d38 -  reserved
34f d3c R gic_distributor_gicd_spisr14
350-3bf d40-efc -  reserved
3c0 f00 W gic_distributor_gicd_sgir
3c1-3c3 f04-f0c -  reserved
3c4 f10 R/W gic_distributor_gicd_cpendsgir0
3c5 f14 R/W gic_distributor_gicd_cpendsgir1
3c6 f18 R/W gic_distributor_gicd_cpendsgir2
3c7 f1c R/W gic_distributor_gicd_cpendsgir3
3c8 f20 R/W gic_distributor_gicd_spendsgir0
3c9 f24 R/W gic_distributor_gicd_spendsgir1
3ca f28 R/W gic_distributor_gicd_spendsgir2
3cb f2c R/W gic_distributor_gicd_spendsgir3
3cc-3f3 f30-fcc -  reserved
3f4 fd0 R gic_distributor_gicd_pidr4
3f5 fd4 R gic_distributor_gicd_pidr5
3f6 fd8 R gic_distributor_gicd_pidr6
3f7 fdc R gic_distributor_gicd_pidr7
3f8 fe0 R gic_distributor_gicd_pidr0
3f9 fe4 R gic_distributor_gicd_pidr1
3fa fe8 R gic_distributor_gicd_pidr2
3fb fec R gic_distributor_gicd_pidr3
3fc ff0 R gic_distributor_gicd_cidr0
3fd ff4 R gic_distributor_gicd_cidr1
3fe ff8 R gic_distributor_gicd_cidr2
3ff ffc R gic_distributor_gicd_cidr3

gic_distributor_gicd_ctlr
Distributor Control Register
R/W
0x00000000
Address : 0x1c010000
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_ctlr


gic_distributor_gicd_typer
Interrupt Controller Type Register
R
Address : 0x1c010004
Bits Name Description
31 - 16 -
 reserved
15 - 11 lspi
Lockable SPIs (LSPIs)
10 securityextn
1
9 - 8 -
 reserved
7 - 5 cpunumber
Has the value of (NUM_CPUS-1)
4 - 0 itlinesnumber
Has the value of NUM_SPIS/32
ITLinesNumber expresses that the GIC supports at most (ITLinesNumber+1)*32 interrupts,
that is, the potentially implemented interrupt IDs are 0 to ((ITLinesNumber+1)*32-1).
This information can then be used by software to restrict the range of interrupts that are accessed during interrupt discovery.
In the GIC-400, all interrupts are implemented except for the unused PPIs, IDs 16-24.


gic_distributor_gicd_iidr
Distributor Implementer Identification Register
R
Address : 0x1c010008
Bits Name Description
31 - 24 productid
Indicates the product ID: 0x02 .. GIC-400
23 - 20 -
 reserved
19 - 16 variant
Indicates the major revision or variant of the product: 0x0 .. variant number
15 - 12 revision
Indicates the minor revision of the product: 0x1 .. revision number
11 - 0 implementer
Indicates the implementer: 0x43B .. ARM


gic_distributor_gicd_igroupr0
Interrupt Group Register 0
R/W
0x00000000
Address : 0x1c010080
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_igroupr0


gic_distributor_gicd_igroupr15
Interrupt Group Register 15
R/W
0x00000000
Address : 0x1c0100bc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_igroupr15


gic_distributor_gicd_isenabler0
Interrupt Set-Enable Register 0
R/W
0x00000000
Address : 0x1c010100
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_isenabler0


gic_distributor_gicd_isenabler15
Interrupt Set-Enable Register 15
R/W
0x00000000
Address : 0x1c01013c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_isenabler15


gic_distributor_gicd_icenabler0
Interrupt Clear-Enable Register 0
R/W
0x00000000
Address : 0x1c010180
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icenabler0


gic_distributor_gicd_icenabler15
Interrupt Clear-Enable Register 15
R/W
0x00000000
Address : 0x1c0101bc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icenabler15


gic_distributor_gicd_ispendr0
Interrupt Set-Pending Register 0
R/W
0x00000000
Address : 0x1c010200
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_ispendr0


gic_distributor_gicd_ispendr15
Interrupt Set-Pending Register 15
R/W
0x00000000
Address : 0x1c01023c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_ispendr15


gic_distributor_gicd_icpendr0
Interrupt Clear-Pending Register 0
R/W
0x00000000
Address : 0x1c010280
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icpendr0


gic_distributor_gicd_icpendr15
Interrupt Clear-Pending Register 15
R/W
0x00000000
Address : 0x1c0102bc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icpendr15


gic_distributor_gicd_isactiver0
Interrupt Set-Active Register 0
R/W
0x00000000
Address : 0x1c010300
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_isactiver0


gic_distributor_gicd_isactiver15
Interrupt Set-Active Register 15
R/W
0x00000000
Address : 0x1c01033c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_isactiver15


gic_distributor_gicd_icactiver0
Interrupt Clear-Active Register 0
R/W
0x00000000
Address : 0x1c010380
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icactiver0


gic_distributor_gicd_icactiver15
Interrupt Clear-Active Register 15
R/W
0x00000000
Address : 0x1c0103bc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icactiver15


gic_distributor_gicd_ipriorityr0
Interrupt Priority Register 0
R/W
0x00000000
Address : 0x1c010400
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_ipriorityr0


gic_distributor_gicd_ipriorityr127
Interrupt Priority Register 127
R/W
0x00000000
Address : 0x1c0105fc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_ipriorityr127


gic_distributor_gicd_itargetsr0
Interrupt Processor Targets Register 0
R
Address : 0x1c010800
Bits Name Description
31 - 0 gic_distributor_gicd_itargetsr0


gic_distributor_gicd_itargetsr127
Interrupt Processor Targets Register 127
R/W
0x00000000
Address : 0x1c0109fc
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_itargetsr127


gic_distributor_gicd_icfgr0
Interrupt Configuration Register 0
R
Address : 0x1c010c00
Bits Name Description
31 - 0 gic_distributor_gicd_icfgr0


gic_distributor_gicd_icfgr15
Interrupt Configuration Register 15
R/W
0x00000000
Address : 0x1c010c3c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_icfgr15


gic_distributor_gicd_ppisr
Private Peripheral Interrupt Status Register
R
Address : 0x1c010d00
Bits Name Description
31 - 0 gic_distributor_gicd_ppisr


gic_distributor_gicd_spisr0
Shared Peripheral Interrupt Status Register 0
R
Address : 0x1c010d04
Bits Name Description
31 - 0 gic_distributor_gicd_spisr0


gic_distributor_gicd_spisr14
Shared Peripheral Interrupt Status Register 14
R
Address : 0x1c010d3c
Bits Name Description
31 - 0 gic_distributor_gicd_spisr14


gic_distributor_gicd_sgir
Software Generated Interrupt Register
W
0x00000000
Address : 0x1c010f00
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_sgir


gic_distributor_gicd_cpendsgir0
SGI Clear-Pending Registers 0
R/W
0x00000000
Address : 0x1c010f10
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_cpendsgir0


gic_distributor_gicd_cpendsgir1
SGI Clear-Pending Registers 1
R/W
0x00000000
Address : 0x1c010f14
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_cpendsgir1


gic_distributor_gicd_cpendsgir2
SGI Clear-Pending Registers 2
R/W
0x00000000
Address : 0x1c010f18
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_cpendsgir2


gic_distributor_gicd_cpendsgir3
SGI Clear-Pending Registers 3
R/W
0x00000000
Address : 0x1c010f1c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_cpendsgir3


gic_distributor_gicd_spendsgir0
SGI Set-Pending Registers 0
R/W
0x00000000
Address : 0x1c010f20
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_spendsgir0


gic_distributor_gicd_spendsgir1
SGI Set-Pending Registers 1
R/W
0x00000000
Address : 0x1c010f24
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_spendsgir1


gic_distributor_gicd_spendsgir2
SGI Set-Pending Registers 2
R/W
0x00000000
Address : 0x1c010f28
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_spendsgir2


gic_distributor_gicd_spendsgir3
SGI Set-Pending Registers 3
R/W
0x00000000
Address : 0x1c010f2c
Bits Reset value Name Description
31 - 0 0
gic_distributor_gicd_spendsgir3


gic_distributor_gicd_pidr4
Peripheral ID4 Register
R
Address : 0x1c010fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


gic_distributor_gicd_pidr5
Peripheral ID5 Register
R
Address : 0x1c010fd4
Bits Name Description
31 - 0 gic_distributor_gicd_pidr5


gic_distributor_gicd_pidr6
Peripheral ID6 Register
R
Address : 0x1c010fd8
Bits Name Description
31 - 0 gic_distributor_gicd_pidr6


gic_distributor_gicd_pidr7
Peripheral ID7 Register
R
Address : 0x1c010fdc
Bits Name Description
31 - 0 gic_distributor_gicd_pidr7


gic_distributor_gicd_pidr0
Peripheral ID0 Register
R
Address : 0x1c010fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


gic_distributor_gicd_pidr1
Peripheral ID1 Register
R
Address : 0x1c010fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


gic_distributor_gicd_pidr2
Peripheral ID2 Register
R
Address : 0x1c010fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


gic_distributor_gicd_pidr3
Peripheral ID3 Register
R
Address : 0x1c010fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


gic_distributor_gicd_cidr0
Component ID0 Register
R
Address : 0x1c010ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


gic_distributor_gicd_cidr1
Component ID1 Register
R
Address : 0x1c010ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


gic_distributor_gicd_cidr2
Component ID2 Register
R
Address : 0x1c010ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


gic_distributor_gicd_cidr3
Component ID3 Register
R
Address : 0x1c010ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: app_gic_cpu_interface

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gic_cpu_interface_gicc_ctlr
1 4 R/W gic_cpu_interface_gicc_pmr
2 8 R/W gic_cpu_interface_gicc_bpr
3 c R gic_cpu_interface_gicc_iar
4 10 W gic_cpu_interface_gicc_eoir
5 14 R gic_cpu_interface_gicc_rpr
6 18 R gic_cpu_interface_gicc_hppir
7 1c R/W gic_cpu_interface_gicc_abpr
8 20 R gic_cpu_interface_gicc_aiar
9 24 W gic_cpu_interface_gicc_aeoir
a 28 R gic_cpu_interface_gicc_ahppir
b-33 2c-cc -  reserved
34 d0 R/W gic_cpu_interface_gicc_apr0
35-37 d4-dc -  reserved
38 e0 R/W gic_cpu_interface_gicc_nsapr0
39-3e e4-f8 -  reserved
3f fc R gic_cpu_interface_gicc_iidr
40-3ff 100-ffc -  reserved

gic_cpu_interface_gicc_ctlr
CPU Interface Control Register
R/W
0x00000000
Address : 0x1c02f000
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_ctlr


gic_cpu_interface_gicc_pmr
Interrupt Priority Mask Register
R/W
0x00000000
Address : 0x1c02f004
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_pmr


gic_cpu_interface_gicc_bpr
Binary Point Register
R/W
0x00000000
Address : 0x1c02f008
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_bpr


gic_cpu_interface_gicc_iar
Interrupt Acknowledge Register
R
Address : 0x1c02f00c
Bits Name Description
31 - 0 gic_cpu_interface_gicc_iar


gic_cpu_interface_gicc_eoir
End Of Interrupt Register
W
0x00000000
Address : 0x1c02f010
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_eoir


gic_cpu_interface_gicc_rpr
Running Priority Register
R
Address : 0x1c02f014
Bits Name Description
31 - 0 gic_cpu_interface_gicc_rpr


gic_cpu_interface_gicc_hppir
Highest Priority Pending Interrupt Register
R
Address : 0x1c02f018
Bits Name Description
31 - 0 gic_cpu_interface_gicc_hppir


gic_cpu_interface_gicc_abpr
Aliased Binary Point Register
R/W
0x00000000
Address : 0x1c02f01c
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_abpr


gic_cpu_interface_gicc_aiar
Aliased Interrupt Acknowledge Register
R
Address : 0x1c02f020
Bits Name Description
31 - 0 gic_cpu_interface_gicc_aiar


gic_cpu_interface_gicc_aeoir
Aliased End of Interrupt Register
W
0x00000000
Address : 0x1c02f024
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_aeoir


gic_cpu_interface_gicc_ahppir
Aliased Highest Priority Pending Interrupt Register
R
Address : 0x1c02f028
Bits Name Description
31 - 0 gic_cpu_interface_gicc_ahppir


gic_cpu_interface_gicc_apr0
Active Priority Register
R/W
0x00000000
Address : 0x1c02f0d0
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_apr0


gic_cpu_interface_gicc_nsapr0
Non-Secure Active Priority Register
R/W
0x00000000
Address : 0x1c02f0e0
Bits Reset value Name Description
31 - 0 0
gic_cpu_interface_gicc_nsapr0


gic_cpu_interface_gicc_iidr
CPU Interface Identification Register
R
Address : 0x1c02f0fc
Bits Name Description
31 - 20 productid
Identifies the product ID: 0x020..GIC-400
19 - 16 arch_version
Identifies the architecture version of the GIC-400: 0x2..version 2.0
15 - 12 revision
Identifies the revision number for the CPU interface. For the GIC-400: 0x1..revision r0p1
11 - 0 implementer
Contains the JEP106 code of the company that implemented the CPU interface. 0x43B..ARM



Base Address Area: app_gic_virt_interface_ctrl, app_gic_virt_interface_ctrl_alias

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gic_virt_interface_ctrl_gich_hcr
1 4 R gic_virt_interface_ctrl_gich_vtr
2 8 R/W gic_virt_interface_ctrl_gich_vmcr
3 c -  reserved
4 10 R gic_virt_interface_ctrl_gich_misr
5-7 14-1c -  reserved
8 20 R gic_virt_interface_ctrl_gich_eisr0
9-b 24-2c -  reserved
c 30 R gic_virt_interface_ctrl_gich_elsr0
d-3b 34-ec -  reserved
3c f0 R/W gic_virt_interface_ctrl_gich_apr0
3d-3f f4-fc -  reserved
40 100 R/W gic_virt_interface_ctrl_gich_lr0
41 104 R/W gic_virt_interface_ctrl_gich_lr1
42 108 R/W gic_virt_interface_ctrl_gich_lr2
43 10c R/W gic_virt_interface_ctrl_gich_lr3
44-3ff 110-ffc -  reserved

gic_virt_interface_ctrl_gich_hcr
Hypervisor Control Register
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f000
Address@app_gic_virt_interface_ctrl_alias : 0x1c050000
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_hcr


gic_virt_interface_ctrl_gich_vtr
VGIC Type Register
R
Address@app_gic_virt_interface_ctrl : 0x1c04f004
Address@app_gic_virt_interface_ctrl_alias : 0x1c050004
Bits Name Description
31 - 29 pribits
Indicates the number of priority bits implemented, minus one: 0x4 .. 5 bits of priority and 32 priority levels.
28 - 26 prebits
Indicates the number of preemption bits implemented, minus one: 0x4 .. 5 bits of preemption and 32 preemption levels
25 - 6 -
 reserved
5 - 0 listregs
Indicates the number of implemented List Registers, minus one: 0x3 .. 4 List registers.


gic_virt_interface_ctrl_gich_vmcr
Virtual Machine Control Register
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f008
Address@app_gic_virt_interface_ctrl_alias : 0x1c050008
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_vmcr


gic_virt_interface_ctrl_gich_misr
Maintenance Interrupt Status Register
R
Address@app_gic_virt_interface_ctrl : 0x1c04f010
Address@app_gic_virt_interface_ctrl_alias : 0x1c050010
Bits Name Description
31 - 0 gic_virt_interface_ctrl_gich_misr


gic_virt_interface_ctrl_gich_eisr0
End of Interrupt Status Register
R
Address@app_gic_virt_interface_ctrl : 0x1c04f020
Address@app_gic_virt_interface_ctrl_alias : 0x1c050020
Bits Name Description
31 - 0 gic_virt_interface_ctrl_gich_eisr0


gic_virt_interface_ctrl_gich_elsr0
Empty List Register Status Register
R
Address@app_gic_virt_interface_ctrl : 0x1c04f030
Address@app_gic_virt_interface_ctrl_alias : 0x1c050030
Bits Name Description
31 - 0 gic_virt_interface_ctrl_gich_elsr0


gic_virt_interface_ctrl_gich_apr0
Active Priority Register
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f0f0
Address@app_gic_virt_interface_ctrl_alias : 0x1c0500f0
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_apr0


gic_virt_interface_ctrl_gich_lr0
List Register 0
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f100
Address@app_gic_virt_interface_ctrl_alias : 0x1c050100
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_lr0


gic_virt_interface_ctrl_gich_lr1
List Register 1
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f104
Address@app_gic_virt_interface_ctrl_alias : 0x1c050104
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_lr1


gic_virt_interface_ctrl_gich_lr2
List Register 2
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f108
Address@app_gic_virt_interface_ctrl_alias : 0x1c050108
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_lr2


gic_virt_interface_ctrl_gich_lr3
List Register 3
R/W
0x00000000
Address@app_gic_virt_interface_ctrl : 0x1c04f10c
Address@app_gic_virt_interface_ctrl_alias : 0x1c05010c
Bits Reset value Name Description
31 - 0 0
gic_virt_interface_ctrl_gich_lr3



Base Address Area: app_gic_virt_cpu_interface

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gic_virt_cpu_interface_gicv_ctlr
1 4 R/W gic_virt_cpu_interface_gicv_pmr
2 8 R/W gic_virt_cpu_interface_gicv_bpr
3 c R gic_virt_cpu_interface_gicv_iar
4 10 W gic_virt_cpu_interface_gicv_eoir
5 14 R gic_virt_cpu_interface_gicv_rpr
6 18 R gic_virt_cpu_interface_gicv_hppir
7 1c R/W gic_virt_cpu_interface_gicv_abpr
8 20 R gic_virt_cpu_interface_gicv_aiar
9 24 W gic_virt_cpu_interface_gicv_aeoir
a 28 R gic_virt_cpu_interface_gicv_ahppir
b-33 2c-cc -  reserved
34 d0 R/W gic_virt_cpu_interface_gicv_apr0
35-3e d4-f8 -  reserved
3f fc R gic_virt_cpu_interface_gicv_iidr
40-3ff 100-ffc -  reserved

gic_virt_cpu_interface_gicv_ctlr
Virtual Machine Control Register
R/W
0x00000000
Address : 0x1c06f000
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_ctlr


gic_virt_cpu_interface_gicv_pmr
VM Priority Mask Register
R/W
0x00000000
Address : 0x1c06f004
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_pmr


gic_virt_cpu_interface_gicv_bpr
VM Binary Point Register
R/W
0x00000000
Address : 0x1c06f008
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_bpr


gic_virt_cpu_interface_gicv_iar
VM Interrupt Acknowledge Register
R
Address : 0x1c06f00c
Bits Name Description
31 - 0 gic_virt_cpu_interface_gicv_iar


gic_virt_cpu_interface_gicv_eoir
VM End of Interrupt Register
W
0x00000000
Address : 0x1c06f010
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_eoir


gic_virt_cpu_interface_gicv_rpr
VM Running Priority Register
R
Address : 0x1c06f014
Bits Name Description
31 - 0 gic_virt_cpu_interface_gicv_rpr


gic_virt_cpu_interface_gicv_hppir
VM Highest Priority Pending Interrupt Register
R
Address : 0x1c06f018
Bits Name Description
31 - 0 gic_virt_cpu_interface_gicv_hppir


gic_virt_cpu_interface_gicv_abpr
VM Aliased Binary Point Register
R/W
0x00000000
Address : 0x1c06f01c
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_abpr


gic_virt_cpu_interface_gicv_aiar
VM Aliased Interrupt Acknowledge Register
R
Address : 0x1c06f020
Bits Name Description
31 - 0 gic_virt_cpu_interface_gicv_aiar


gic_virt_cpu_interface_gicv_aeoir
VM Aliased End of Interrupt Register
W
0x00000000
Address : 0x1c06f024
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_aeoir


gic_virt_cpu_interface_gicv_ahppir
VM Aliased Highest Priority Pending Interrupt Register
R
Address : 0x1c06f028
Bits Name Description
31 - 0 gic_virt_cpu_interface_gicv_ahppir


gic_virt_cpu_interface_gicv_apr0
VM Active Priority Register
R/W
0x00000000
Address : 0x1c06f0d0
Bits Reset value Name Description
31 - 0 0
gic_virt_cpu_interface_gicv_apr0


gic_virt_cpu_interface_gicv_iidr
VM CPU Interface Identification Register
R
Address : 0x1c06f0fc
Bits Name Description
31 - 20 productid
Identifies the product ID: 0x020..GIC-400
19 - 16 arch_version
Identifies the architecture version of the GIC-400: 0x2..version 2.0
15 - 12 revision
Identifies the revision number for the CPU interface. For the GIC-400: 0x1..revision r0p1
11 - 0 implementer
Contains the JEP106 code of the company that implemented the CPU interface. 0x43B..ARM



Base Address Area: app_main_nic_gpv

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 W main_nic_gpv_remap
1 4 -  reserved
2 8 W main_nic_gpv_security0
3-40 c-100 -  reserved
41 104 W main_nic_gpv_security63
42-7f3 108-1fcc -  reserved
7f4 1fd0 R main_nic_gpv_pidr4
7f5 1fd4 R main_nic_gpv_pidr5
7f6 1fd8 R main_nic_gpv_pidr6
7f7 1fdc R main_nic_gpv_pidr7
7f8 1fe0 R main_nic_gpv_pidr0
7f9 1fe4 R main_nic_gpv_pidr1
7fa 1fe8 R main_nic_gpv_pidr2
7fb 1fec R main_nic_gpv_pidr3
7fc 1ff0 R main_nic_gpv_cidr0
7fd 1ff4 R main_nic_gpv_cidr1
7fe 1ff8 R main_nic_gpv_cidr2
7ff 1ffc R main_nic_gpv_cidr3
800-3ffff 2000-ffffc -  reserved

main_nic_gpv_remap
Remap register. Up to eight remap bits are supported
W
0x00000000
Address : 0x1e000000
Bits Reset value Name Description
31 - 0 0
main_nic_gpv_remap


main_nic_gpv_security0
Slave 0 security setting
W
0x00000000
Address : 0x1e000008
Bits Reset value Name Description
31 - 0 0
main_nic_gpv_security0


main_nic_gpv_security63
Slave 63 security setting
W
0x00000000
Address : 0x1e000104
Bits Reset value Name Description
31 - 0 0
main_nic_gpv_security63


main_nic_gpv_pidr4
Peripheral ID4
R
Address : 0x1e001fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


main_nic_gpv_pidr5
Peripheral ID5
R
Address : 0x1e001fd4
Bits Name Description
31 - 0 main_nic_gpv_pidr5


main_nic_gpv_pidr6
Peripheral ID6
R
Address : 0x1e001fd8
Bits Name Description
31 - 0 main_nic_gpv_pidr6


main_nic_gpv_pidr7
Peripheral ID7
R
Address : 0x1e001fdc
Bits Name Description
31 - 0 main_nic_gpv_pidr7


main_nic_gpv_pidr0
Peripheral ID0
R
Address : 0x1e001fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


main_nic_gpv_pidr1
Peripheral ID1
R
Address : 0x1e001fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


main_nic_gpv_pidr2
Peripheral ID2
R
Address : 0x1e001fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


main_nic_gpv_pidr3
Peripheral ID3
R
Address : 0x1e001fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


main_nic_gpv_cidr0
Component ID0
R
Address : 0x1e001ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


main_nic_gpv_cidr1
Component ID1
R
Address : 0x1e001ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


main_nic_gpv_cidr2
Component ID2
R
Address : 0x1e001ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


main_nic_gpv_cidr3
Component ID3
Component ID Register 3
R
Address : 0x1e001ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: secenc_cryptocell

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-203 0-80c -  reserved
204 810 R/W cryptocell_misc_aes_clk_enable
205 814 -  reserved
206 818 R/W cryptocell_misc_hash_clk_enable
207 81c R/W cryptocell_misc_pka_clk_enable
208 820 R/W cryptocell_misc_dma_clk_enable
209 824 R cryptocell_misc_clk_status
20a-215 828-854 -  reserved
216 858 R/W cryptocell_misc_chacha_clk_enable
217-29d 85c-a74 -  reserved
29e a78 R/W cryptocell_host_core_clk_gating_enable
29f-77f a7c-1dfc -  reserved
780 1e00 R/W cryptocell_host_dcu_en0
781 1e04 R/W cryptocell_host_dcu_en1
782 1e08 R/W cryptocell_host_dcu_en2
783 1e0c R/W cryptocell_host_dcu_en3
784 1e10 R/W cryptocell_host_dcu_lock0
785 1e14 R/W cryptocell_host_dcu_lock1
786 1e18 R/W cryptocell_host_dcu_lock2
787 1e1c R/W cryptocell_host_dcu_lock3
788-7c0 1e20-1f00 -  reserved
7c1 1f04 R cryptocell_aib_fuse_prog_completed
7c2 1f08 R cryptocell_nvm_debug_status
7c3 1f0c R cryptocell_lcs_is_valid
7c4 1f10 R cryptocell_nvm_is_idle
7c5 1f14 R cryptocell_lcs_reg
7c6 1f18 W cryptocell_host_shadow_kdr_reg
7c7 1f1c W cryptocell_host_shadow_kcp_reg
7c8 1f20 W cryptocell_host_shadow_kce_reg
7c9 1f24 W cryptocell_host_shadow_kpicv_reg
7ca 1f28 W cryptocell_host_shadow_kceicv_reg
7cb 1f2c R cryptocell_otp_addr_width_def
7cc-7ff 1f30-1ffc -  reserved
800 2000 R/W cryptocell_nvm_base
801-ffe 2004-3ff8 -  reserved
fff 3ffc - cryptocell_nvm_end

cryptocell_misc_aes_clk_enable
AES clock enable register
R/W
0x00000000
Address : 0x2f000810
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Enable the AES clock.


cryptocell_misc_hash_clk_enable
HASH clock enable register
R/W
0x00000000
Address : 0x2f000818
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Enable the HASH clock.


cryptocell_misc_pka_clk_enable
PKA clock enable register
R/W
0x00000000
Address : 0x2f00081c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Enable the PKA clock.


cryptocell_misc_dma_clk_enable
DMA clock enable register
R/W
0x00000000
Address : 0x2f000820
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Enable the DMA clock.


cryptocell_misc_clk_status
Clock status register
R
Address : 0x2f000824
Bits Name Description
31 - 9 -
 reserved
8 dma_clk_status

7 chacha_clk_status

6 - 4 -
 reserved
3 pka_clk_status

2 hash_clk_status

1 -
 reserved
0 aes_clk_status



cryptocell_misc_chacha_clk_enable
CHACHA clock enable register
R/W
0x00000000
Address : 0x2f000858
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
Enable the CHACHA clock.


cryptocell_host_core_clk_gating_enable
Clock gating enable register
This register enables the core clk gating by masking/enabling the cc_idle_state output signal.
R/W
0x00000000
Address : 0x2f000a78
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
host_core_clk_gating_enable
Enable the core clk gating.


cryptocell_host_dcu_en0
Debug Control Unit enable register 0
DCU[31:0]
R/W
0x00000000
Address : 0x2f001e00
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_en0


cryptocell_host_dcu_en1
Debug Control Unit enable register 1
DCU[63:32]
R/W
0x00000000
Address : 0x2f001e04
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_en1


cryptocell_host_dcu_en2
Debug Control Unit enable register 2
DCU[95:64]
R/W
0x00000000
Address : 0x2f001e08
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_en2


cryptocell_host_dcu_en3
Debug Control Unit enable register 3
DCU[128:96]
R/W
0x00000000
Address : 0x2f001e0c
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_en3


cryptocell_host_dcu_lock0
Debug Control Unit lock register 0
Writing 1 locks the corresponding DCU_EN[31:0] bit.
R/W
0x00000000
Address : 0x2f001e10
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_lock0


cryptocell_host_dcu_lock1
Debug Control Unit lock register 1
Writing 1 locks the corresponding DCU_EN[63:32] bit.
R/W
0x00000000
Address : 0x2f001e14
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_lock1


cryptocell_host_dcu_lock2
Debug Control Unit lock register 2
Writing 1 locks the corresponding DCU_EN[95:64] bit.
R/W
0x00000000
Address : 0x2f001e18
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_lock2


cryptocell_host_dcu_lock3
Debug Control Unit lock register 3
Writing 1 locks the corresponding DCU_EN[128:96] bit.
R/W
0x00000000
Address : 0x2f001e1c
Bits Reset value Name Description
31 - 0 0
cryptocell_host_dcu_lock3


cryptocell_aib_fuse_prog_completed
Fuse programming completion status
R
Address : 0x2f001f04
Bits Name Description
31 - 1 -
 reserved
0 aib_fuse_prog_completed
Fuse programming operation has been completed.


cryptocell_nvm_debug_status
AIB debug status register
R
Address : 0x2f001f08
Bits Name Description
31 - 4 -
 reserved
3 - 1 nvm_sm
Main NVM FSM
0 -
 reserved


cryptocell_lcs_is_valid
LCS valid status
R
Address : 0x2f001f0c
Bits Name Description
31 - 1 -
 reserved
0 lcs_is_valid_reg
LCS is valid


cryptocell_nvm_is_idle
NVM manager idle status
R
Address : 0x2f001f10
Bits Name Description
31 - 1 -
 reserved
0 nvm_is_idle_reg
NVM is idle


cryptocell_lcs_reg
LCS state register and number of zeros error indication
R
Address : 0x2f001f14
Bits Name Description
31 - 13 -
 reserved
12 error_kceicv_zero_cnt
Indication that the number of zeros in the loaded KCEICV is not equal to the value set in the manufacture flag.
11 error_kpicv_zero_cnt
Indication that the number of zeros in the loaded KPICV is not equal to the value set in the manufacture flag.
10 error_kce_zero_cnt
Indication that the number of zeros in the loaded KCE is not equal to the value set in the OEM flag.
9 error_prov_zero_cnt
Indication that the number of zeros in the loaded KCP is not equal to the value set in the OEM flag.
8 error_kdr_zero_cnt
Indication that the number of zeros in the loaded KDR is not equal to the value set in the manufacture flag.
7 - 3 -
 reserved
2 - 0 lcs_reg
LCS value
3'b000: CM
3'b001: DM
3'b101: SE
3'b111: RMA


cryptocell_host_shadow_kdr_reg
W
0x00000000
Address : 0x2f001f18
Bits Reset value Name Description
31 - 0 0
cryptocell_host_shadow_kdr_reg


cryptocell_host_shadow_kcp_reg
W
0x00000000
Address : 0x2f001f1c
Bits Reset value Name Description
31 - 0 0
cryptocell_host_shadow_kcp_reg


cryptocell_host_shadow_kce_reg
W
0x00000000
Address : 0x2f001f20
Bits Reset value Name Description
31 - 0 0
cryptocell_host_shadow_kce_reg


cryptocell_host_shadow_kpicv_reg
W
0x00000000
Address : 0x2f001f24
Bits Reset value Name Description
31 - 0 0
cryptocell_host_shadow_kpicv_reg


cryptocell_host_shadow_kceicv_reg
W
0x00000000
Address : 0x2f001f28
Bits Reset value Name Description
31 - 0 0
cryptocell_host_shadow_kceicv_reg


cryptocell_otp_addr_width_def
R
Address : 0x2f001f2c
Bits Name Description
31 - 0 cryptocell_otp_addr_width_def


cryptocell_nvm_base
NVM direct access start address
Area size: 8kB
R/W
0x00000000
Address : 0x2f002000
Bits Reset value Name Description
31 - 0 0
cryptocell_nvm_base


cryptocell_nvm_end

Address : 0x2f003ffc
Bits Name Description
31 - 0 cryptocell_nvm_end



Base Address Area: secenc_cryptocell_otp_ctrl, secenc_otp_ctrl0, secenc_otp_ctrl1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W otp_ctrl_cfg
1 4 R otp_ctrl_status
2 8 R/W otp_ctrl_timings_power0
3 c R/W otp_ctrl_timings_power1
4 10 R/W otp_ctrl_timings_power2
5 14 R/W otp_ctrl_timings_power3
6 18 R/W otp_ctrl_timings_read0
7 1c R/W otp_ctrl_timings_read1
8 20 R/W otp_ctrl_timings_read2
9 24 R/W otp_ctrl_timings_program0
a 28 R/W otp_ctrl_timings_program1
b 2c R/W otp_ctrl_timings_program2
c 30 R/W otp_ctrl_timings_program3
d-3f 34-fc -  reserved

otp_ctrl_cfg
OTP controller config register
R/W
0x00000000
Address@secenc_cryptocell_otp_ctrl : 0x2f004000
Address@secenc_otp_ctrl0 : 0x5001c000
Address@secenc_otp_ctrl1 : 0x5001d000
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
disable_auto_standby
Disable automatic transition to standby and deep standby when idle.
2 "0"
disable_pprog_multi_writes
Disable multiple 32bit writes during a single PPROG cycle.
1 "0"
disable_skip_unprog
Disable skipping of unprogrammed bits during writes to the OTP.
0 "0"
disable_rmw
Disable read-modify-write sequence for write requests.
Note: If disabled it must be ensured only newly-programmed bits are set in the write data. The controller will not ensure it in this mode. If wrongly used, the OTP may take damage when cells are programmed too often.


otp_ctrl_status
OTP controller status register
R
Address@secenc_cryptocell_otp_ctrl : 0x2f004004
Address@secenc_otp_ctrl0 : 0x5001c004
Address@secenc_otp_ctrl1 : 0x5001d004
Bits Name Description
31 - 8 -
 reserved
7 - 2 ip_fsm_state
State of the IP control FSM. Used for debugging only.
1 disable_auto_standby_until_first_access
The OTP controller will disable automatic switch to standby states until the first access (read or write) has been detected. This allows immidiate access of the OTP after statup even if the first access is likely to happen after the access and standby timeouts.
Note: This is not configurable, but an implementation time setting.
0 auto_leave_standby_after_reset
The OTP controller will leave standby states and enter read mode in selected state. This allows immidiate access of the OTP after statup.
Note: This is not configurable, but an implementation time setting.


otp_ctrl_timings_power0
Power timing parameter register 0
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x000000c8
Address@secenc_cryptocell_otp_ctrl : 0x2f004008
Address@secenc_otp_ctrl0 : 0x5001c008
Address@secenc_otp_ctrl1 : 0x5001d008
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0000"
t_penh
Power enable hold time, min: 0ns
15 - 10 0
-
 reserved
9 - 0 0xc8
t_pens
Power enable setup time, min: 1us


otp_ctrl_timings_power1
Power timing parameter register 1
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x00020190
Address@secenc_cryptocell_otp_ctrl : 0x2f00400c
Address@secenc_otp_ctrl0 : 0x5001c00c
Address@secenc_otp_ctrl1 : 0x5001d00c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0010"
t_ash
Active mode to deep standby hold time, min: 10ns
It is also used for ptrim 0 -> pdstb 0, i.e. entering standby from active mode.
15 - 10 0
-
 reserved
9 - 0 0x190
t_sas
Deep standby to active mode setup time, min: 2us


otp_ctrl_timings_power2
Power timing parameter register 2
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x00002710
Address@secenc_cryptocell_otp_ctrl : 0x2f004010
Address@secenc_otp_ctrl0 : 0x5001c010
Address@secenc_otp_ctrl1 : 0x5001d010
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x2710
t_tas
Repair mode setup time, min: 50us
It is also used for pdstb 1 -> ptrim 1


otp_ctrl_timings_power3
Power timing parameter register 3
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x4e1f031f
Address@secenc_cryptocell_otp_ctrl : 0x2f004014
Address@secenc_otp_ctrl0 : 0x5001c014
Address@secenc_otp_ctrl1 : 0x5001d014
Bits Reset value Name Description
31 - 16 0x4e1f
auto_standby_inactivity_cycles
Number of clock cycles before OTP will be transitioned from read idle to standby state
It must be at least t_tah = 10ns to make sure control pins are idle at least this time before setting ptrim = 0 in enter standby state.
15 - 12 0
-
 reserved
11 - 0 0x31f
auto_deep_standby_inactivity_cycles
Number of clock cycles before IP will transitioned from standby to deep standby state


otp_ctrl_timings_read0
Read timing parameter register 0
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x000207d0
Address@secenc_cryptocell_otp_ctrl : 0x2f004018
Address@secenc_otp_ctrl0 : 0x5001c018
Address@secenc_otp_ctrl1 : 0x5001d018
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0010"
t_as
Address setup time, min: 10ns
15 - 12 0
-
 reserved
11 - 0 0x7d0
t_cs
IP enable time, min: 10us


otp_ctrl_timings_read1
Read timing parameter register 1
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x00000155
Address@secenc_cryptocell_otp_ctrl : 0x2f00401c
Address@secenc_otp_ctrl0 : 0x5001c01c
Address@secenc_otp_ctrl1 : 0x5001d01c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00001"
t_dout_sample_pre_kl_end
dout sample point in number of half-cycles before pclk low-phase end (t_kh + t_kl - t_cd), t_cd min: 50ns
Note: This value is the desired value as is (not minus one).
7 - 4 "0101"
t_kl
Clock pulse low time, min: 20ns
3 - 0 "0101"
t_kh
Clock pulse high time, min: 20ns
But: t_cyc = 50ns (t_kh+t_kl) and t_cd = 50ns (access time) with t_oh = 0.1ns (output hold) -> do t_cyc = 60ns really


otp_ctrl_timings_read2
Read timing parameter register 2
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x000927bf
Address@secenc_cryptocell_otp_ctrl : 0x2f004020
Address@secenc_otp_ctrl0 : 0x5001c020
Address@secenc_otp_ctrl1 : 0x5001d020
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 0 0x927bf
read_selected_inactivity_cycles
Number of clock cycles before OTP will be transitioned from read selected to read idle state


otp_ctrl_timings_program0
Program timing parameter register 0
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x000307d0
Address@secenc_cryptocell_otp_ctrl : 0x2f004024
Address@secenc_otp_ctrl0 : 0x5001c024
Address@secenc_otp_ctrl1 : 0x5001d024
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 16 "0011"
t_asp
Program address setup time, min: 10ns, must be > t_dsp (min: 1ns)
Note: This value is the desired value as is (not minus one).
15 - 12 0
-
 reserved
11 - 0 0x7d0
t_csp
IP enable time in program, min: 10us, max: 100us


otp_ctrl_timings_program1
Program timing parameter register 1
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x03e807d0
Address@secenc_cryptocell_otp_ctrl : 0x2f004028
Address@secenc_otp_ctrl0 : 0x5001c028
Address@secenc_otp_ctrl1 : 0x5001d028
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 16 0x3e8
t_ppr
Program mode recovery time, min: 5 us, max: 100us
15 - 12 0
-
 reserved
11 - 0 0x7d0
t_pps
Program mode setup time min: 10us, max: 20us


otp_ctrl_timings_program2
Program timing parameter register 2
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x00c807d0
Address@secenc_cryptocell_otp_ctrl : 0x2f00402c
Address@secenc_otp_ctrl0 : 0x5001c02c
Address@secenc_otp_ctrl1 : 0x5001d02c
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 - 16 0xc8
t_pwi
Program pulse interval time, min: 1us, max: 5us
15 - 12 0
-
 reserved
11 - 0 0x7d0
t_pw
Program pulse width time, min: 10us, max: 15us


otp_ctrl_timings_program3
Program timing parameter register 3
Note: Programmed values must be desired value minus one.
Note: Default values are for OTP macros in 200 MHz clock domain (secenc_cryptocell_nvm) and are different for 100 MHz clock domain instances (secenc_otp0, secenc_otp1).
R/W
0x00000320
Address@secenc_cryptocell_otp_ctrl : 0x2f004030
Address@secenc_otp_ctrl0 : 0x5001c030
Address@secenc_otp_ctrl1 : 0x5001d030
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x320
t_pph_minus_pwi
Program mode hold time [minus Program pulse interval time], t_pph min: 5us, max 20us
It must not exceed t_pwi_max - t_pwi because this time may be used to wait for additonal write requests!



Base Address Area: secenc_ram

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W secenc_ram_base
1-1fffe 4-7fff8 -  reserved
1ffff 7fffc R/W secenc_ram_end

secenc_ram_base
SecEnc internal SRAM start address
Area size: 512kB
R/W
0x00000000
Address : 0x30000000
Bits Reset value Name Description
31 - 0 0
secenc_ram_base


secenc_ram_end
SecEnc internal SRAM end address
R/W
0x00000000
Address : 0x3007fffc
Bits Reset value Name Description
31 - 0 0
secenc_ram_end



Base Address Area: sqi, app_sqi0, app_sqi1, mot_sqi0, mot_sqi1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sqi_cr0
1 4 R/W sqi_cr1
2 8 R/W sqi_dr
3 c R sqi_sr
4 10 R/W sqi_tcr
5 14 R/W sqi_irq_mask
6 18 R sqi_irq_raw
7 1c R sqi_irq_masked
8 20 R/W sqi_irq_clear
9 24 R/W sqi_dmacr
a 28 R/W sqi_pio_out
b 2c -  reserved
c 30 R/W sqi_pio_oe
d 34 R sqi_pio_in
e 38 R/W sqi_sqirom_cfg
f 3c -  reserved

sqi_cr0
SQI control register 0
This register is compatible to netX50 and netX10 SPI module. However, there are some additional settings possible. SQI module
provides only master functionality, hence slave settings are omitted. Compatible mode for netx100 is not supported by SQI module.
R/W
0x00080007
Address@sqi : 0x40010000
Address@app_sqi0 : 0x40080480
Address@app_sqi1 : 0x400804c0
Address@mot_sqi0 : 0x49200480
Address@mot_sqi1 : 0x492004c0
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 "0"
filter_in
Receive-data is sampled every 10ns (100MHz system clock). If this bit is set, the
stored receive value will be the result of a majority decision of the three sampling points
around a sck clock edge (if two or more '1's were sampled, a '1' will be stored, else a '0' will
be stored).
Input filtering should be used for sck_muladd<=0x200 (i.e. below 12.5MHz). For higher frequencies
stable signal phases are too short for filtering.
26 - 24 0
-
 reserved
23 - 22 "00"
sio_cfg
SQI IO configuration. Default is all additional SQI-IOs (SIO2,3) are in PIO input mode.
Coding
 00: only SIO2,3 are controllable as PIOs (2-bit SPI or Standard Motorola SPI),
 01: all SQP IOs are used for transfers (4-bit SPI/SQI).
 10: reserved
 11: all SQI IOs are controllable as PIOs
21 - 20 0
-
 reserved
19 - 8 0x800
sck_muladd
Serial clock rate multiply add value for sck generation.
sck-frequency: f_sck = (sck_muladd * 100)/4096 [MHz].
Programmed value of sck_muladd must be <= 0x800.
Default value 0x800 equals 50MHz clock rate.
Note:
   If sck_muladd is set to zero, transfer will freeze.
Note:
   SQIROM (XiP) serial clock rate must be programmed in 'sqi_sqirom_cfg' register.
7 "0"
sck_phase
Serial clock phase
1: sample data at second clock edge, data is generated half a clock phase before sampling
0: sample data at first clock edge, data is generated half a clock phase before sampling
Note:
    sck_phase value equals bit 0 of SPI mode value (mode = (sck_pol, sck_phase)).
6 "0"
sck_pol
Serial clock polarity
0: idle: clock is low, first edge is rising
1: idle: clock is high, first edge is falling
Note:
    sck_pol value equals bit 1 of SPI mode value (mode = (sck_pol, sck_phase)).
5 - 4 0
-
 reserved
3 - 0 "0111"
datasize
Data size select for standard Motorola SPI mode.
This bit field is unused in 2- and 4-bit SPI modes (i.e. datasize fixed to 8 bit).
(transfer size = datasize + 1 bits)
0000...0010: reserved
0011: 4 bit
0100: 5 bit
...
0111:  8 bit
...
1111: 16 bit


sqi_cr1
SQI control register 1
This register is compatible to netX50 and netX10 SPI module. However, there are some additional settings possible. SQI module
provides only master functionality, hence slave settings are omitted.
R/W
0x08080000
Address@sqi : 0x40010004
Address@app_sqi0 : 0x40080484
Address@app_sqi1 : 0x400804c4
Address@mot_sqi0 : 0x49200484
Address@mot_sqi1 : 0x492004c4
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 "0"
rx_fifo_clr
Writing "1" to this bit will clear the receive FIFO.
This bit will be reset automatically by hardware. It is always '0' on read.
27 - 24 "1000"
rx_fifo_wm
Receive FIFO watermark for IRQ generation.
If receive FIFO watermark IRQ is enabled ('RXIM' bit is set in 'sqi_irq_mask' register),
transfers will be stopped when receive FIFO runs full. Transfers will be continued after
receive data is read from receive FIFO. This is done to avoid receive FIFO overruns.
If receive FIFO watermark IRQ is disabled ('RXIM' bit is not set in 'sqi_irq_mask' register),
transfers will not be stopped when receive FIFO runs full. In this case receive FIFO
overrun could occur. This is compatible to netX50 behaviour and allows writing data in
full duplex mode without reading receive FIFO.
23 - 21 0
-
 reserved
20 "0"
tx_fifo_clr
Writing "1" to this bit will clear the transmit FIFO.
This bit will be reset automatically by hardware. It is always '0' on read.
19 - 16 "1000"
tx_fifo_wm
Transmit FIFO watermark for IRQ generation
15 - 13 0
-
 reserved
12 "0"
spi_trans_ctrl
Transfer Control for standard Motorola SPI (default: disabled)
This bit is only used for standard Motorola SPI (register 'sqi_tcr' 'mode'-bits)
in full- and half-duplex modes.
If this bit is set, SPI transfer then is controlled by 'start_transfer' and 'transfer_size'
of register 'sqi_tcr'.
If this bit is not set (default), SPI transfers start immediately after transfer data was written to
TX FIFO (this is SPI module compatible). Settings of 'start_transfer' and 'transfer_size'
of register 'sqi_tcr' then remain unaffected and are ignored.
If this bit is set and SPI is used in receive mode (full duplex or half duplex receive
mode set by bit field 'duplex' in register 'sqi_tcr'), transfers will be stopped when
receive FIFO runs full. Transfers will be continued after receive data is read from
receive FIFO. This is done to avoid receive FIFO overruns.
11 "0"
fss_static
SQI static chip-select
0: chip-select will be generated automatically at data frame begin/end according to fss and datasize
1: chip-select will be set statically according to 'fss' bits (see below).
If fss is set to static mode, fss must be toggled manually after each data frame in Motorola SPI mode when
sck_phase is 0 for spec compatibility!
Note:
   This bit is only used in Standard Motorola SPI mode. For SQI modes, chip-select is never generated automatically.
10 - 8 "000"
fss
Frame slave select (up to 3 devices can be assigned directly,
up to 8 devices can be assigned if an external de-multiplexer is used).
This signal is active low, so the bits will be inverted before output to the SQI pins.
7 - 2 0
-
 reserved
1 "0"
sqi_en
SQI enable.
0: interface disabled
1: interface enabled
Note:
   Standard SQI/SPI function is not available if SQIROM/XiP function is selected by
   'enable' bit of 'sqi_sqirom_cfg' register (see description of 'sqi_sqirom_cfg' register).
0 0
-
 reserved


sqi_dr
SQI data register (DR)
Read access: received data word is delivered from receive FIFO.
Write access: send data word is written to send FIFO.
Both, receive and transmit FIFO have a depth of 16 words (standard SPI mode). In SQI mode both FIFOs are combined, so 64 bytes are
available.
R/W
0x00000000
Address@sqi : 0x40010008
Address@app_sqi0 : 0x40080488
Address@app_sqi1 : 0x400804c8
Address@mot_sqi0 : 0x49200488
Address@mot_sqi1 : 0x492004c8
Bits Reset value Name Description
31 - 0 0x0
data
Transmit data, must be right aligned on writing.
In Standard SPI mode only bits according to sqi_cr0.datasize are being transferred.
In SQI mode data must be written in full DWords (i.e. software needs to collect four bytes prior to writing).
Unused bytes won't be transferred and may be padded at will (number of transfered bytes depends on sqi_tcr.transfer_size).
Receive data will always be right aligned; unused bits will be "0".


sqi_sr
Read only SQI status register
Shows the current status of the SQI interface.
R
Address@sqi : 0x4001000c
Address@app_sqi0 : 0x4008048c
Address@app_sqi1 : 0x400804cc
Address@mot_sqi0 : 0x4920048c
Address@mot_sqi1 : 0x492004cc
Bits Name Description
31 rx_fifo_err_undr
Receive FIFO underrun error occurred, unexpected data has been read.
This status flag is cleared by clearing RX FIFO ('sqi_cr1' register).
30 rx_fifo_err_ovfl
Receive FIFO overflow error occurred, data is lost.
This status flag is cleared by clearing RX FIFO ('sqi_cr1' register).
29 -
 reserved
28 - 24 rx_fifo_level
Receive FIFO level (number of received words to read out from FIFO).
23 tx_fifo_err_undr
Transmit FIFO underrun error occurred, unexpected data has been sent.
This status flag is cleared by clearing TX FIFO ('sqi_cr1' register).
22 tx_fifo_err_ovfl
Transmit FIFO overflow error occurred, data is lost.
This status flag is cleared by clearing TX FIFO ('sqi_cr1' register).
21 -
 reserved
20 - 16 tx_fifo_level
Transmit FIFO level (number of words to transmit are left in FIFO).
15 sqirom_disabled_err
Access to SQIROM area detected while SQIROM was disabled.
To enable SQIROM functionality set 'enable' bit in 'sqi_sqirom_cfg' register.
This bit can be used to determine the reason for 'sqirom_error' IRQ assertion.
This status flag is only cleared by writing a '1' here.
14 sqirom_write_err
Write access to SQIROM area detected.
SQIROM area is read only.
This bit can be used to determine the reason for 'sqirom_error' IRQ assertion.
This status flag is only cleared by writing a '1' here.
13 sqirom_timeout_err
Timeout during SQIROM area read detected.
A timeout results from a fix level on netX serial clock IO. Check IO
multiplexing configuration and ensure that serial clock output is not externally clamped.
This bit can be used to determine the reason for 'sqirom_error' IRQ assertion.
This status flag is only cleared by writing a '1' here.
SQIROM function must be disabled and enabled again to reset module internal state
machines after this bit has ben set (register 'sqirom_cfg', reset and set again 'enable' bit).
12 - 5 -
 reserved
4 busy
Device is busy (1 if data is currently transmitted/received or the transmit FIFO is not empty).
3 rx_fifo_full
Receive FIFO is full (1 if full).
2 rx_fifo_not_empty
Receive FIFO is not empty (0 if empty).
1 tx_fifo_not_full
Transmit FIFO is not full (0 if full).
0 tx_fifo_empty
Transmit FIFO is empty (1 if empty).


sqi_tcr
SQI transfer control
(module address offset 0x10 is reserved in netX10/50 SPI module. No compatibility problems by using this address for new register).
This register must not be changed while a transfer is running ('busy' bit in register 'sqi_sr' is '1') to avoid corrupted transfers causing hardware damage.
R/W
0x1c000000
Address@sqi : 0x40010010
Address@app_sqi0 : 0x40080490
Address@app_sqi1 : 0x400804d0
Address@mot_sqi0 : 0x49200490
Address@mot_sqi1 : 0x492004d0
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 "0"
ms_byte_first
Most significant byte first
2- and 4-bit mode: Writing "1" to this bit will use most significant byte first in DWords (big endian).
Default is little endian representation.
In Standard Motorola SPI mode this bit is ignored.
Endianess of a transferred 32-bit word can be controlled by this bit. Default 0 is little endianess.
28 "1"
ms_bit_first
Most significant bit first
2- and 4-bit mode: Writing "1" to this bit will transfer most significant bit first (default).
In Standard Motorola SPI mode this bit is ignored.
27 - 26 "11"
duplex
Transfer type selection (default is '11' for standard SPI compatibility).
00:
dummy
Generates 'transfer_size' + 1 serial clock periods. No change of RX and TX FIFOs.
Data lines (standard Motorola SPI mode: SPI_MOSI) are controlled by 'tx_oe' and 'tx_out'.
01:


half-duplex receive
Receives 'transfer_size' + 1 words.
In 2-bit and 4-bit mode TX-FIFO will be cleared and is not available during receive.
In standard SPI mode SPI_MOSI is controlled by 'tx_oe' and 'tx_out'. There is no need to
fill the TX-FIFO with dummy TX-data to receive RX-data. TX FIFOs are not changed and are always available.
10:

half-duplex transmit
Transmits 'transfer_size' + 1 words.
In 2-bit and 4-bit mode RX-FIFO will be cleared and is not available during transmit.
In standard SPI mode SPI_MISO input is ignored. RX-FIFO is available and remains unchanged.
11:
full-duplex (Standard Motorola SPI mode only, reserved in 2-bit and 4-bit modes)
This is full-duplex standard Motorola SPI mode always transmitting and receiving data. Transmit data
is taken from TX-FIFO, receive data is stored in RX-FIFO.
Note:
   If '11' is set in 2-bit or 4-bit mode, this is treated as 'receive' (like '01' setting).
Note:
   If there was a FIFO error (overflow, underrun) before changing to '01' or '10'
   the FIFO error status bits in register 'sqi_sr' are not cleared by half-duplex modes FIFO clearing.
25 - 24 "00"
mode
SPI/SQI mode selection
00: Standard Motorola SPI mode.
01: 2-bit SPI mode
10: 4-bit SPI mode
11: reserved
23 "0"
start_transfer
Transfer start signal
Writing a "1" starts the transfer of transfer_size bytes.
Also starts transfer of dummy cycles.
This bit will be reset automatically by hardware and is always '0' on read. It
is only writable after a transfer sequence is finished or if the transfer sequence is
terminated by a FIFO clear.
Note:
   A transfer sequence is finished completely when 'busy' bit in 'sqi_sr' register is not set.
Note:
   For standard Motorola SPI mode, this function can be controlled by 'spi_trans_ctrl' bit in
   'sqi_cr1' register (for SPI module compatibility).
22 "0"
tx_oe
Output driver enable in dummy or standard SPI receive-only mode
Writing a "1" enables the output drivers of the data pins in dummy mode.
21 "0"
tx_out
Output level in dummy or standard SPI receive-only mode.
This bit selects the output level when the output driver is enabled in dummy mode.
20 - 19 0
-
 reserved
18 - 0 0x0
transfer_size
Number of bytes within the current SQI transaction (transfer_size+1).
Program (actual number of bytes - 1) in SQI modes or (number of dummy clock cycles - 1)
Example:
   0x00000: one byte / dummy cycle
   ...
   0x7ffff: 512k bytes / dummy cycles
This bit field counts down during transfer with each transferred word/byte or dummy cycle. It
is only writable after a transfer sequence is finished  or if the transfer sequence is
terminated by a FIFO clear. Hence, it is writable but can also be changed by hardware.
A running transfer sequence can be terminated by FIFO clearing (register 'sqi_cr1').
This may be necessary if a read sequence has to be terminated.
Example:
   A half duplex write transfer of 128k bytes was programmed but there is not enough
   write data. To terminate this write sequence, clear TX FIFO. If there is an external
   transfer running at the moment of clearing the FIFO, this transfer will not be broken
   and finished with the last bit to be transferred.
Note:
   A transfer sequence is finished completely when 'busy' bit in 'sqi_sr' register is not set.


sqi_irq_mask
SQI interrupt mask register:
IRQ mask is an AND-mask: only raw interrupts with mask bit set can generate a module IRQ to CPU.

Note: The functionality of this register is similar to the corresponding SPI register spi_imsc.
      However in contrast to this register, setting bits in spi_imsc does also clear the corresponding raw interrupts.

For detailed IRQ behaviour and function view 'sqi_irq_raw' register.
R/W
0x00000000
Address@sqi : 0x40010014
Address@app_sqi0 : 0x40080494
Address@app_sqi1 : 0x400804d4
Address@mot_sqi0 : 0x49200494
Address@mot_sqi1 : 0x492004d4
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
sqirom_error
SQIROM error interrupt mask
7 "0"
trans_end
Transfer end interrupt mask
6 "0"
txeim
Transmit FIFO empty interrupt mask (for netx100/500 compliance)
5 "0"
rxfim
Receive FIFO full interrupt mask (for netx100/500 compliance)
4 "0"
rxneim
Receive FIFO not empty interrupt mask (for netx100/500 compliance)
3 "0"
TXIM
Transmit FIFO interrupt mask
2 "0"
RXIM
Receive FIFO interrupt mask
1 "0"
RTIM
Receive timeout interrupt mask
0 "0"
RORIM
Receive FIFO overrun interrupt mask


sqi_irq_raw
SQI interrupt state before masking register (raw interrupt).
Writing a "1" to a bit clears this interrupt.
Note:
   IRQ flags can also be cleared by using 'sqi_irq_clear' for SPI module compatibility.
R
Address@sqi : 0x40010018
Address@app_sqi0 : 0x40080498
Address@app_sqi1 : 0x400804d8
Address@mot_sqi0 : 0x49200498
Address@mot_sqi1 : 0x492004d8
Bits Name Description
31 - 9 -
 reserved
8 sqirom_error
Unmaksed SQIROM error interrupt state
1:

SQIROM access error detected.
This IRQ is asserted when an error occurs on a SQIROM access. Detailed error information
is provided by SQIROM error bits in register 'sqi_sr'.
For error handling both, this IRQ bit and bits in register 'sqi_sr' must be cleared.
0: no SQIROM error detected.
7 trans_end
Unmasked transfer end interrupt state (related to bit 'busy' of 'sqi_sr' register)
1: transfer finished. Bit 'busy' of 'sqi_sr' register has become inactive.
0: transfer finished not finished. Bit 'busy' of 'sqi_sr' register is active.
6 txeris
Unmasked transmit FIFO empty interrupt state (for netx100/500 compliance)
1: transmit FIFO is empty
0: transmit FIFO is not empty
5 rxfris
Unmasked receive FIFO full interrupt state (for netx100/500 compliance)
1: receive FIFO is full
0: receive FIFO is not full
4 rxneris
Unmasked receive FIFO not empty interrupt state (for netx100/500 compliance)
1: receive FIFO is not empty
0: receive FIFO is empty
3 TXRIS
Unmasked transmit FIFO interrupt state
1: transmit FIFO level is below sqi_cr1.tx_fifo_wm
0: transmit FIFO equals or is higher than sqi_cr1.tx_fifo_wm
2 RXRIS
Unmasked receive FIFO interrupt state
1: receive FIFO is higher than sqi_cr1.rx_fifo_wm
0: receive FIFO is equals or is below sqi_cr1.rx_fifo_wm
Note:
    View description of register 'sqi_cr1' for bits 'spi_trans_ctrl' and 'rx_fifo_wm'
    for receive FIFO behaviour before programming this IRQ.
1 RTRIS
Unmasked receive timeout interrupt state
Timeout period is 32 serial clock periods (depending on adr_sqi_cr0.sck_muladd)
1: receive FIFO is not empty and has not been read out during the timeout period
0: receive FIFO is empty or read during the last timeout period
0 RORRIS
Unmasked receive FIFO overrun interrupt state
1: receive FIFO overrun error occurred
0: no receive FIFO overrun error occurred


sqi_irq_masked
SQI masked interrupt status register
For detailed IRQ behaviour and function view 'sqi_irq_raw' register.
R
Address@sqi : 0x4001001c
Address@app_sqi0 : 0x4008049c
Address@app_sqi1 : 0x400804dc
Address@mot_sqi0 : 0x4920049c
Address@mot_sqi1 : 0x492004dc
Bits Name Description
31 - 9 -
 reserved
8 sqirom_error
Masked SQIROM error interrupt state
7 trans_end
Masked transfer end interrupt state
6 txemis
Masked transmit FIFO empty interrupt state (for netx100/500 compliance)
5 rxfmis
Masked receive FIFO full interrupt state (for netx100/500 compliance)
4 rxnemis
Masked receive FIFO not empty interrupt state (for netx100/500 compliance)
3 TXMIS
Masked transmit FIFO interrupt state
2 RXMIS
Masked receive FIFO interrupt state
1 RTMIS
Masked receive timeout interrupt state
0 RORMIS
Masked receive FIFO overrun interrupt state


sqi_irq_clear
SQI interrupt clear register (for compatibility to netX10/50 SPI module).
This register is always '0' on read.
Note:
   IRQ flags can also be cleared by writing 'sqi_irq_raw' register.
R/W
0x00000000
Address@sqi : 0x40010020
Address@app_sqi0 : 0x400804a0
Address@app_sqi1 : 0x400804e0
Address@mot_sqi0 : 0x492004a0
Address@mot_sqi1 : 0x492004e0
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
sqirom_error
Clear SQIROM error interrupt
7 "0"
trans_end
Clear transfer end interrupt
6 "0"
txeic
Clear transmit FIFO empty interrupt (for netx100/500 compliance)
5 "0"
rxfic
Clear receive FIFO full interrupt (for netx100/500 compliance)
4 "0"
rxneic
Clear receive FIFO not empty interrupt (for netx100/500 compliance)
3 "0"
TXIC
Clear transmit FIFO interrupt
2 "0"
RXIC
Clear receive FIFO interrupt
1 "0"
RTIC
Clear receive FIFO overrun interrupt
0 "0"
RORIC
Clear receive FIFO overrun interrupt


sqi_dmacr
SQI DMA control register
Only normal transfer requests will be generated by this module (i.e. no last requests will be issued). In consequence
only DMAC controlled transfers can be used (no peripheral controlled mode).
R/W
0x00000000
Address@sqi : 0x40010024
Address@app_sqi0 : 0x400804a4
Address@app_sqi1 : 0x400804e4
Address@mot_sqi0 : 0x492004a4
Address@mot_sqi1 : 0x492004e4
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
tx_dma_en
Enable DMA for SQI-transmit data
A request will be generated if TX-FIFO is not full and sqi_cr1.sqi_en (module enable) is set.
Burst request to the DMAC will be done if at least 4 words are writable to the TX-FIFO (set DMA-burst-size to 4)
If this bit is reset or the module is disabled, DMA request will also be reset.
Note: set adr_dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA module
0 "0"
rx_dma_en
Enable DMA for SQI-receive data
A request will be generated if RX-FIFO is not empty and sqi_cr1.sqi_en (module enable) is set.
Burst request to the DMAC will be done if the RX-FIFO contains at least 4 words (set DMA-burst-size to 4)
If this bit is reset or the module is disabled, DMA request will also be reset.
Note: set adr_dmac_chctrl.SBSize = 1 (i.e. burst size: 4) in the DMA module


sqi_pio_out
SQI PIO output level control register
IO PIO mode is controlable by 'sqi_cr0' register bits 'sio_cfg'.
PIO input signal states are never filtered ('sqi_cr0' bit 'filter_in')
Note:
   SQI module must be enabled by register 'sqi_cr0' bit 'sqi_en' for SQI IOs driving in PIO mode.
R/W
0x0000000e
Address@sqi : 0x40010028
Address@app_sqi0 : 0x400804a8
Address@app_sqi1 : 0x400804e8
Address@mot_sqi0 : 0x492004a8
Address@mot_sqi1 : 0x492004e8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
sio3
SIO3 output state
6 "0"
sio2
SIO2 output state
5 "0"
miso
MISO/SIO1 output state
4 "0"
mosi
MOSI/SIO0 output state
3 - 1 "111"
csn
Chip-select/FSS output state {CS2, CS1, CS0}
0 "0"
sclk
Serial SPI clock output state.


sqi_pio_oe
SQI PIO output enable control register
IO PIO mode is controlable by 'sqi_cr0' register bits 'sio_cfg'.
Note:
   SQI module must be enabled by register 'sqi_cr0' bit 'sqi_en' for SQI IOs driving in PIO mode.
R/W
0x00000000
Address@sqi : 0x40010030
Address@app_sqi0 : 0x400804b0
Address@app_sqi1 : 0x400804f0
Address@mot_sqi0 : 0x492004b0
Address@mot_sqi1 : 0x492004f0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
sio3
SIO3 output enable
6 "0"
sio2
SIO2 output enable
5 "0"
miso
MISO/SIO1 output enable
4 "0"
mosi
MOSI/SIO0 output enable
3 - 1 "000"
csn
Chip-select/FSS output enable {CS2, CS1, CS0}
0 "0"
sclk
Serial SPI clock output enable


sqi_pio_in
SQI PIO input status register
IO PIO mode is controllable by 'sqi_cr0' register bits 'sio_cfg'.
R
Address@sqi : 0x40010034
Address@app_sqi0 : 0x400804b4
Address@app_sqi1 : 0x400804f4
Address@mot_sqi0 : 0x492004b4
Address@mot_sqi1 : 0x492004f4
Bits Name Description
31 - 8 -
 reserved
7 sio3
SIO3 input state
6 sio2
SIO2 input state
5 miso
MISO/SIO1 input state
4 mosi
MOSI/SIO0 input state
3 - 1 csn
Chip-select/FSS  input state {CS2, CS1, CS0}
0 sclk
Serial SPI clock input state


sqi_sqirom_cfg
SQIROM mode configuration
Configuration register for the SQIROM mode.
This mode supports the 'eXecute in Place' (XiP) feature of SQI flash chips. The position of the command byte and the address nibbles as well as
the the number of address nibbles and dummy cycles can be configured with this register. It is also possible to change the clock divider
to support a wide range of frequencies for the serial clock output.
Note: Before enabling this mode, the SQI flash chip needs to be in 4 bit command mode, otherwise the module is not able to fetch data
from the flash.
Note: When enabled, the SQI module is completely blocked, i.e. other SQI or SPI transactions are not possible.
Note: The chip-select signal of the flash must be connected to sqi_cs0.
Note: SQIROM transfers can be generated in SPI mode 0 or mode 3. This can be selected by in the sqi_cr0 register. Mode 1 and 2 must
not be selected for SQIROM usage.
R/W
0x18020004
Address@sqi : 0x40010038
Address@app_sqi0 : 0x400804b8
Address@app_sqi1 : 0x400804f8
Address@mot_sqi0 : 0x492004b8
Address@mot_sqi1 : 0x492004f8
Bits Reset value Name Description
31 - 24 "00011000"
clk_div_val
Internal 2 GHz clock will be divided by (clk_div_val+1) for sqirom_clk generation
Default setting '24' is 2GHz DIV 25 == 80 MHz. Maximum allowed serial clock rate is 133 MHz (clk_div_val programmed to '14').
Serial clock period (t_sck) will be (clk_div_val+1)*0.5ns. Clock high and low phase will be generated symmetrically.
Note: Programming '0' will freeze sqirom_clk. Values of 1-14 aren't allowed, either.
23 - 22 0
-
 reserved
21 - 20 "00"
t_csh
Minimum SQI chips-select-high (idle) time: (t_csh+1) * t_sck (according to clk_div_val).
Programmable values are 0 to 3.
Change this parameter if used SQI device requires minimum chips-select-high times
exceeding 1 serial clock period. Required timing must be taken from used SQI device datasheet.
Note:
   Serial clock will not toggle when device is not selected. Hence only chip-select-active
   timing has to be considered.
19 - 16 "0010"
dummy_cycles
Selects the number of dummy cycles before data will be sampled from the SQI chip.
0000 : 0 cycles
0001 : 1 cycle
0010 : 2 cycles (default)
...
1111 : 15 cycles
15 - 8 "00000000"
cmd_byte
This byte is transferred to the SQI chip as the command sequence.
The address-command order can be controlled by the 'addr_before_cmd' bit.
7 0
-
 reserved
6 - 4 "000"
addr_bits
Number of address bits used to generate the address for the SQI chip. This depends
on the size of the SQI chip.
000 : 20 bits (1MByte/8MBit device) (default)
001 : 21 bits (2MByte/16MBit device)
010 : 22 bits (4MByte/32MBit device)
011 : 23 bits (8MByte/64MBit device)
100 : 24 bits (16MByte/128MBit device)
101 : 25 bits (32MByte/256MBit device)
110 : 26 bits (64MByte/512MBit device)
111 : 27 bits (128MByte/1GBit device)
3 - 2 "01"
addr_nibbles
Number of nibbles to transfer as the address to the SQI chip.
This depends on the command format of the SQI chip.
The address-command order can be controlled by the 'addr_before_cmd' bit.
Most significant address bits will be transmitted in the first address nibble.
Least significant address bits will be transmitted in the last address nibble.
00 : 5 nibbles
01 : 6 nibbles (default)
10 : 7 nibbles
11 : 8 nibbles
1 "0"
addr_before_cmd
When set to '1' the address nibbles will be transferred before the command byte.
Otherwise the command is transferred first.
0 "0"
enable
Enables the SQIROM mode of the SQI module. The SQI chip needs to be initialized to
accept 4 bit read-command before activating the SQIROM mode.
Note:
   This bit is also used to switch between SQIROM/XiP and standard SQI/SPI function.
   If this bit is set, standard SQI/SPI function is not available. SQIROM/XiP function
   does not depend on programmed value of 'sqi_en' bit in 'sqi_cr1' register.
   If multiplexmatrix provides SQI functionality, this is only available in
   standard SQI/SPI but not for SQIROM/XiP usage. SQIROM/XiP function is only
   provided on dedicated non-multiplexmatrix SQI IOs but not as multiplexmatrix function
   even if standard SQI is provided there.



Base Address Area: global_asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W global_asic_ctrl_netx_version
1 4 R/W global_asic_ctrl_netx_unique_id0
2 8 R/W global_asic_ctrl_netx_unique_id1
3 c R/W global_asic_ctrl_netx_unique_id2
4 10 R/W global_asic_ctrl_only_por
5 14 R global_asic_ctrl_system_status
6 18 R/W global_asic_ctrl_rst_out_cfg
7 1c R/W global_asic_ctrl_io_voltage_cfg
8 20 R/W global_asic_ctrl_app_mmio_io_cfg0
9 24 R/W global_asic_ctrl_app_mmio_io_cfg1
a 28 R/W global_asic_ctrl_app_mmio_io_cfg2
b 2c R/W global_asic_ctrl_app_mmio_io_cfg3
c 30 R/W global_asic_ctrl_app_mmio_io_cfg4
d 34 R/W global_asic_ctrl_app_pio_io_cfg
e 38 R/W global_asic_ctrl_app_eth_io_cfg
f 3c R/W global_asic_ctrl_app_biss_io_cfg
10 40 R/W global_asic_ctrl_app_endat_io_cfg
11 44 R/W global_asic_ctrl_app_peri_io_cfg
12 48 R/W global_asic_ctrl_app_misc_io_cfg
13 4c -  reserved
14 50 R/W global_asic_ctrl_com_mmio_io_cfg
15 54 R/W global_asic_ctrl_com_sgmii_io_cfg
16 58 R/W global_asic_ctrl_com_rgmii_io_cfg
17 5c R/W global_asic_ctrl_com_mii0_io_cfg
18 60 R/W global_asic_ctrl_com_mii1_io_cfg
19 64 R/W global_asic_ctrl_com_rmii_io_cfg
1a 68 R/W global_asic_ctrl_com_gxc_io_cfg0
1b 6c R/W global_asic_ctrl_com_gxc_io_cfg1
1c 70 R/W global_asic_ctrl_com_misc_io_cfg
1d 74 R/W global_asic_ctrl_com_peri_io_cfg
1e 78 R/W global_asic_ctrl_com_canfd_io_cfg
1f 7c R/W global_asic_ctrl_mot_mmio_io_cfg0
20 80 R/W global_asic_ctrl_mot_mmio_io_cfg1
21 84 R/W global_asic_ctrl_mot_mmio_io_cfg2
22 88 R/W global_asic_ctrl_mot_mmio_io_cfg3
23 8c R/W global_asic_ctrl_mot_pio_io_cfg
24 90 R/W global_asic_ctrl_mot_sdm_io_cfg
25 94 R/W global_asic_ctrl_mot_biss_io_cfg
26 98 R/W global_asic_ctrl_mot_endat_io_cfg
27 9c R/W global_asic_ctrl_dbg_io_cfg
28 a0 R/W global_asic_ctrl_ioextender_io_cfg
29 a4 R/W global_asic_ctrl_global_peri_io_cfg
2a a8 R/W global_asic_ctrl_hif_io_cfg0
2b ac R/W global_asic_ctrl_hif_io_cfg1
2c b0 R/W global_asic_ctrl_hif_io_cfg2
2d b4 R/W global_asic_ctrl_hif_io_cfg3
2e b8 R/W global_asic_ctrl_pcie_dbg_io_cfg
2f bc R/W global_asic_ctrl_pcie_isolation
30 c0 R/W global_asic_ctrl_irq_raw
31 c4 R/W global_asic_ctrl_irq_masked
32 c8 R/W global_asic_ctrl_irq_mask_set
33 cc R/W global_asic_ctrl_irq_mask_rst
34 d0 R/W global_asic_ctrl_sdio_pad_cfg
35-ff d4-3fc -  reserved

global_asic_ctrl_netx_version
(netx_version)
netX Revision Register:
This register contains information about netX hardware and bootloader revision.
TBD, not yet: This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
0x00000011
Address : 0x40030000
Bits Reset value Name Description
31 - 0 0x11
netx_version
netX revision number:
Hardware reset values of netX version register is:
0x01: netx100, netx500
0x01: netx50
0x02: netx5_mpw
0x41: netx5
0x50: netx10
0x05: netx56
0x06: reserved
0x07: netx6
0x08: netx4000_relaxed
0x09: reserved
0x0a: netx4000
0x0b: reserved
0x0c: netxtiny_mpw
0x0d: netxtiny
0x0e: netiol_mpw
0x0f: netiol
0x10: netxxl_mpw0
0x11: netx22xx_mpw
Further netX revisions should increment (next: 0x12).
This register is changed to Hilscher netX bootloader revision by ROM-code:
Hardware reset values should differ from Hilscher values!
netX50 revision number starts with "B" (0x42).
0x41: netx500
0x42: netx50
0x42: netx100
0x41: netx5
0x42: netx10
0x42: netx56


global_asic_ctrl_netx_unique_id0
netX unique ID register 0
TBD, not yet: This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
0x00000000
Address : 0x40030004
Bits Reset value Name Description
31 - 0 0x0
id
netX unique ID part 0


global_asic_ctrl_netx_unique_id1
netX unique ID register 1
TBD, not yet: This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
0x00000000
Address : 0x40030008
Bits Reset value Name Description
31 - 0 0x0
id
netX unique ID part 1


global_asic_ctrl_netx_unique_id2
netX unique ID register 2
TBD, not yet: This register is lockable by asic_ctrl_com.netx_lock-lock_id_regs.
R/W
0x00000000
Address : 0x4003000c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
id
netX unique ID part 2


global_asic_ctrl_only_por
Firmware Status register:
This register is not Reset by SW resets, only PORn will reset this register. TBD
R/W
0x00000000
Address : 0x40030010
Bits Reset value Name Description
31 - 0 0x0
data
netX Firmware status


global_asic_ctrl_system_status
netX System Status Register.
This register provides information of netX system events and status.
R
Address : 0x40030014
Bits Name Description
31 - 2 -
 reserved
1 top_dftenable
Sampled TESTMODE input & SSE710 DFTENABLE signals for production test purpose
0 testmode
Sampled TESTMODE input for production test purpose


global_asic_ctrl_rst_out_cfg
(NETX_RESET_CTRL)
Reset Control Register
R/W
0x00000000
Address : 0x40030018
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 -
rst_out_n_in_ro
Status of reset pin (RST_OUT_N). This bit is a read only status and indicates the reset state.
26 "0"
EN_RES_REQ_OUT
This bit enables the driving of the programmable reset output RST_OUT_N.
When this bit is not set RST_OUT_N will be in high impedance state.
For all resets this bit is cleared. The external level of the RST_OUT_N output during the reset
must be realized by an external pull up or down resistor (when RST_OUT_N function is desired).
25 "0"
RES_REQ_OUT
Software reset for external devices: This bit controls the level of the RST_OUT_N output
for normal operation. For all resets this bit is cleared, however driving of RST_OUT_N
is also disabled (view EN_RES_REQ_OUT bit).
24 - 0 0
-
 reserved


global_asic_ctrl_io_voltage_cfg
Voltage select configuration register (password protected).
There are 4 programmable IO power groups for netx22xx (see column "PwrGrp" in pinning table, or comments at pad_ctrl registers).
By default all programmable power groups are configured for 3.3V usage. If a power group is supplied with 1.8V it must be switched to
the 1.8V mode before it can be used.
Attention: It will cause permanent damage to the IOs if a power group is supplied with 3.3V but the related bit of this config
           register is programmed to 1.8V!
Note: It will not cause damage if a power group is supplied with 1.8V but configured to 3.3V. However this won't work correctly.
Note: Power switching is not supported: An IO power group must be constantly either supplied with 3.3V or with 1.8V. E.g. it is not
possible to supply a power group at startup with 3.3V and to switch later to 1.8V.
R/W
0x00000000
Address : 0x4003001c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xf1c8 must be written here to validate a write access to this register.
15 - 4 0
-
 reserved
3 "0"
pwr_grp5_v18
Voltage select for IOs of programmable power group 5 (0: 3.3V, 1: 1.8V)
2 "0"
pwr_grp4_v18
Voltage select for IOs of programmable power group 4 (0: 3.3V, 1: 1.8V)
Note: Power group 4 are the SDIO IOs. The SDIO itself offers the possibility to
      program the IOs to 1.8 or 3.3V. However programming this in the IP is always ignored
      by the IOs. The IO voltage selection is only done by this bit here.
1 "0"
pwr_grp3_v18
Voltage select for IOs of programmable power group 3 (0: 3.3V, 1: 1.8V)
0 "0"
pwr_grp2_v18
Voltage select for IOs of programmable power group 2 (0: 3.3V, 1: 1.8V)


global_asic_ctrl_app_mmio_io_cfg0
IO config for APP MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030020
Bits Reset value Name Description
31 - 16 0x0
sel_app_mmio0_15_wm
Write mask of sel_app_mmio0_15
15 - 0 0x0
sel_app_mmio0_15
MUX-select for APP MMIO 0 - 15


global_asic_ctrl_app_mmio_io_cfg1
IO config for APP MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030024
Bits Reset value Name Description
31 - 16 0x0
sel_app_mmio16_31_wm
Write mask of sel_app_mmio16_31
15 - 0 0x0
sel_app_mmio16_31
MUX-select for APP MMIO 16 - 31


global_asic_ctrl_app_mmio_io_cfg2
IO config for APP MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030028
Bits Reset value Name Description
31 - 16 0x0
sel_app_mmio32_47_wm
Write mask of sel_app_mmio32_47
15 - 0 0x0
sel_app_mmio32_47
MUX-select for APP MMIO 32 - 47


global_asic_ctrl_app_mmio_io_cfg3
IO config for APP MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003002c
Bits Reset value Name Description
31 - 16 0x0
sel_app_mmio48_63_wm
Write mask of sel_app_mmio48_63
15 - 0 0x0
sel_app_mmio48_63
MUX-select for APP MMIO 48 - 63


global_asic_ctrl_app_mmio_io_cfg4
IO config for APP MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030030
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 16 0x0
sel_app_mmio64_75_wm
Write mask of sel_app_mmio64_75
15 - 12 0
-
 reserved
11 - 0 0x0
sel_app_mmio64_75
MUX-select for APP MMIO 64 - 75


global_asic_ctrl_app_pio_io_cfg
IO config for APP PIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030034
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 16 0x0
sel_app_pio_wm
Write mask of sel_app_pio
15 - 11 0
-
 reserved
10 - 0 0x0
sel_app_pio
MUX-select for APP PIO 0 - 10. Note: APP PIO 7 - 10 can only be used as inputs on SGMII IOs.


global_asic_ctrl_app_eth_io_cfg
IO config for APP Ethernet Phy
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030038
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sel_app_sgmii_fx_sd_wm
Write mask of sel_app_sgmii_fx_sd
20 "0"
sel_app_mdio_rgmii_wm
Write mask of sel_app_mdio_rgmii
19 "0"
sel_app_mdio_sgmii_wm
Write mask of sel_app_mdio_sgmii
18 "0"
sel_app_mdc_wm
Write mask of sel_app_mdc
17 "0"
sel_app_rgmii_1_wm
Write mask of sel_app_rgmii_1
16 "0"
sel_app_rgmii_0_wm
Write mask of sel_app_rgmii_0
15 - 6 0
-
 reserved
5 "0"
sel_app_sgmii_fx_sd
MUX-select for APP SGMII, fx_sd signal
4 "0"
sel_app_mdio_rgmii
MUX-select for APP MDIO at position for use with RGMII
3 "0"
sel_app_mdio_sgmii
MUX-select for APP MDIO at position for use with SGMII
2 "0"
sel_app_mdc
MUX-select for APP MDC
1 "0"
sel_app_rgmii_1
MUX-select for APP RGMII group 1 (TX)
0 "0"
sel_app_rgmii_0
MUX-select for APP RGMII group 0 (RX)


global_asic_ctrl_app_biss_io_cfg
IO config for APP BiSS
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003003c
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
sel_app_biss1_mo_b_wm
Write mask of sel_app_biss1_mo_b
23 "0"
sel_app_biss1_mo_a_wm
Write mask of sel_app_biss1_mo_a
22 "0"
sel_app_biss1_b_wm
Write mask of sel_app_biss1_b
21 "0"
sel_app_biss1_a_wm
Write mask of sel_app_biss1_a
20 "0"
sel_app_biss1_wm
Write mask of sel_app_biss1
19 "0"
sel_app_biss0_mo_b_wm
Write mask of sel_app_biss0_mo_b
18 "0"
sel_app_biss0_mo_a_wm
Write mask of sel_app_biss0_mo_a
17 "0"
sel_app_biss0_b_wm
Write mask of sel_app_biss0_b
16 "0"
sel_app_biss0_a_wm
Write mask of sel_app_biss0_a
15 - 9 0
-
 reserved
8 "0"
sel_app_biss1_mo_b
MUX-select for APP BiSS 1 MO signal, position (b)
7 "0"
sel_app_biss1_mo_a
MUX-select for APP BiSS 1 MO signal, position (a)
6 "0"
sel_app_biss1_b
MUX-select for APP BiSS 1, position (b)
5 "0"
sel_app_biss1_a
MUX-select for APP BiSS 1, position (a)
4 "0"
sel_app_biss1
MUX-select for APP BiSS 1, default position
3 "0"
sel_app_biss0_mo_b
MUX-select for APP BiSS 0 MO signal, position (b)
2 "0"
sel_app_biss0_mo_a
MUX-select for APP BiSS 0 MO signal, position (a)
1 "0"
sel_app_biss0_b
MUX-select for APP BiSS 0, position (b)
0 "0"
sel_app_biss0_a
MUX-select for APP BiSS 0, position (a)


global_asic_ctrl_app_endat_io_cfg
IO config for APP EnDat
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030040
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
sel_app_endat1_devel_b_wm
Write mask of sel_app_endat1_devel_b
24 "0"
sel_app_endat1_devel_a_wm
Write mask of sel_app_endat1_devel_a
23 "0"
sel_app_endat1_b_wm
Write mask of sel_app_endat1_b
22 "0"
sel_app_endat1_a_wm
Write mask of sel_app_endat1_a
21 "0"
sel_app_endat1_wm
Write mask of sel_app_endat1
20 "0"
sel_app_endat0_devel_b_wm
Write mask of sel_app_endat0_devel_b
19 "0"
sel_app_endat0_devel_a_wm
Write mask of sel_app_endat0_devel_a
18 "0"
sel_app_endat0_devel_wm
Write mask of sel_app_endat0_devel
17 "0"
sel_app_endat0_b_wm
Write mask of sel_app_endat0_b
16 "0"
sel_app_endat0_a_wm
Write mask of sel_app_endat0_a
15 - 10 0
-
 reserved
9 "0"
sel_app_endat1_devel_b
MUX-select for APP EnDat 1 development signals, position (b)
8 "0"
sel_app_endat1_devel_a
MUX-select for APP EnDat 1 development signals, position (a)
7 "0"
sel_app_endat1_b
MUX-select for APP EnDat 1, position (b)
6 "0"
sel_app_endat1_a
MUX-select for APP EnDat 1, position (a)
5 "0"
sel_app_endat1
MUX-select for APP EnDat 1, default position
4 "0"
sel_app_endat0_devel_b
MUX-select for APP EnDat 0 development signals, position (b)
3 "0"
sel_app_endat0_devel_a
MUX-select for APP EnDat 0 development signals, position (a)
2 "0"
sel_app_endat0_devel
MUX-select for APP EnDat 0 development signals, default position
1 "0"
sel_app_endat0_b
MUX-select for APP EnDat 0, position (b)
0 "0"
sel_app_endat0_a
MUX-select for APP EnDat 0, position (a)


global_asic_ctrl_app_peri_io_cfg
IO config for APP peripherals
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030044
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
sel_app_xspi_rst_n_wm
Write mask of sel_app_xspi_rst_n
22 "0"
sel_app_xspi_int_wm
Write mask of sel_app_xspi_int
21 "0"
sel_app_xspi_cs1_wm
Write mask of sel_app_xspi_cs1
20 "0"
sel_app_xspi_wm
Write mask of sel_app_xspi
19 "0"
sel_app_canfd1_a_wm
Write mask of sel_app_canfd1_a
18 "0"
sel_app_canfd1_wm
Write mask of sel_app_canfd1
17 "0"
sel_app_canfd0_a_wm
Write mask of sel_app_canfd0_a
16 "0"
sel_app_canfd0_wm
Write mask of sel_app_canfd0
15 - 8 0
-
 reserved
7 "0"
sel_app_xspi_rst_n
MUX-select for APP xSPI RST_N signal
6 "0"
sel_app_xspi_int
MUX-select for APP xSPI INT signal
5 "0"
sel_app_xspi_cs1
MUX-select for APP xSPI CS1 signal
4 "0"
sel_app_xspi
MUX-select for APP xSPI
3 "0"
sel_app_canfd1_a
MUX-select for APP CAN-FD 1, position (a)
2 "0"
sel_app_canfd1
MUX-select for APP CAN-FD 1, default position
1 "0"
sel_app_canfd0_a
MUX-select for APP CAN-FD 0, position (a)
0 "0"
sel_app_canfd0
MUX-select for APP CAN-FD 0, default position


global_asic_ctrl_app_misc_io_cfg
IO config for APP
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030048
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
sel_app_phy_rst_out_n_cs1_wm
Write mask of sel_app_phy_rst_out_n_cs1
16 "0"
sel_app_phy_rst_out_n_int_wm
Write mask of sel_app_phy_rst_out_n_int
15 - 2 0
-
 reserved
1 "0"
sel_app_phy_rst_out_n_cs1
MUX-select for APP_PHY_RST_OUT_N, position com_xspi_cs1
0 "0"
sel_app_phy_rst_out_n_int
MUX-select for APP_PHY_RST_OUT_N, position com_xspi_int


global_asic_ctrl_com_mmio_io_cfg
IO config for COM MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030050
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000000"
sel_com_mmio_wm
Write mask of sel_com_mmio
15 - 8 0
-
 reserved
7 - 0 "00000000"
sel_com_mmio
MUX-select for COM MMIO 0 - 7


global_asic_ctrl_com_sgmii_io_cfg
IO config for COM SGMIIs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030054
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
sel_com_sgmii1_fx_sd_wm
Write mask of sel_com_sgmii1_fx_sd
22 "0"
sel_com_sgmii1_3_wm
Write mask of sel_com_sgmii1_3
21 "0"
sel_com_sgmii1_2_wm
Write mask of sel_com_sgmii1_2
20 "0"
sel_com_sgmii1_1_wm
Write mask of sel_com_sgmii1_1
19 "0"
sel_com_sgmii0_fx_sd_wm
Write mask of sel_com_sgmii0_fx_sd
18 "0"
sel_com_sgmii0_3_wm
Write mask of sel_com_sgmii0_3
17 "0"
sel_com_sgmii0_2_wm
Write mask of sel_com_sgmii0_2
16 "0"
sel_com_sgmii0_1_wm
Write mask of sel_com_sgmii0_1
15 - 8 0
-
 reserved
7 "0"
sel_com_sgmii1_fx_sd
MUX-select for COM SGMII 1, fx_sd signal
6 "0"
sel_com_sgmii1_3
MUX-select for COM SGMII 1, signal group 3
5 "0"
sel_com_sgmii1_2
MUX-select for COM SGMII 1, signal group 2
4 "0"
sel_com_sgmii1_1
MUX-select for COM SGMII 1, signal group 1
3 "0"
sel_com_sgmii0_fx_sd
MUX-select for COM SGMII 0, fx_sd signal
2 "0"
sel_com_sgmii0_3
MUX-select for COM SGMII 0, signal group 3
1 "0"
sel_com_sgmii0_2
MUX-select for COM SGMII 0, signal group 2
0 "0"
sel_com_sgmii0_1
MUX-select for COM SGMII 0, signal group 1


global_asic_ctrl_com_rgmii_io_cfg
IO config for COM RGMIIs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030058
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 "0"
sel_com_rgmii1_txc_out_p1ns_wm
Write mask of sel_com_rgmii1_txc_out_p1ns
28 "0"
sel_com_rgmii1_4_wm
Write mask of sel_com_rgmii1_4
27 "0"
sel_com_rgmii1_3_wm
Write mask of sel_com_rgmii1_3
26 "0"
sel_com_rgmii1_2_wm
Write mask of sel_com_rgmii1_2
25 "0"
sel_com_rgmii1_1_wm
Write mask of sel_com_rgmii1_1
24 "0"
sel_com_rgmii1_0_wm
Write mask of sel_com_rgmii1_0
23 - 22 0
-
 reserved
21 "0"
sel_com_rgmii0_txc_out_p1ns_wm
Write mask of sel_com_rgmii0_txc_out_p1ns
20 "0"
sel_com_rgmii0_4_wm
Write mask of sel_com_rgmii0_4
19 "0"
sel_com_rgmii0_3_wm
Write mask of sel_com_rgmii0_3
18 "0"
sel_com_rgmii0_2_wm
Write mask of sel_com_rgmii0_2
17 "0"
sel_com_rgmii0_1_wm
Write mask of sel_com_rgmii0_1
16 "0"
sel_com_rgmii0_0_wm
Write mask of sel_com_rgmii0_0
15 - 14 0
-
 reserved
13 "0"
sel_com_rgmii1_txc_out_p1ns
Select 1ns additional delay on com_rgmii1_txc
12 "0"
sel_com_rgmii1_4
MUX-select for COM RGMII 1, signal group 4
11 "0"
sel_com_rgmii1_3
MUX-select for COM RGMII 1, signal group 3
10 "0"
sel_com_rgmii1_2
MUX-select for COM RGMII 1, signal group 2
9 "0"
sel_com_rgmii1_1
MUX-select for COM RGMII 1, signal group 1
8 "0"
sel_com_rgmii1_0
MUX-select for COM RGMII 1, signal group 0
7 - 6 0
-
 reserved
5 "0"
sel_com_rgmii0_txc_out_p1ns
Select 1ns additional delay on com_rgmii0_txc
4 "0"
sel_com_rgmii0_4
MUX-select for COM RGMII 0, signal group 4
3 "0"
sel_com_rgmii0_3
MUX-select for COM RGMII 0, signal group 3
2 "0"
sel_com_rgmii0_2
MUX-select for COM RGMII 0, signal group 2
1 "0"
sel_com_rgmii0_1
MUX-select for COM RGMII 0, signal group 1
0 "0"
sel_com_rgmii0_0
MUX-select for COM RGMII 0, signal group 0


global_asic_ctrl_com_mii0_io_cfg
IO config for COM MII0
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003005c
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
sel_com_mii0_9_wm
Write mask of sel_com_mii0_9
24 "0"
sel_com_mii0_8_wm
Write mask of sel_com_mii0_8
23 "0"
sel_com_mii0_7_wm
Write mask of sel_com_mii0_7
22 "0"
sel_com_mii0_6_wm
Write mask of sel_com_mii0_6
21 "0"
sel_com_mii0_5_wm
Write mask of sel_com_mii0_5
20 "0"
sel_com_mii0_4_wm
Write mask of sel_com_mii0_4
19 "0"
sel_com_mii0_3_wm
Write mask of sel_com_mii0_3
18 "0"
sel_com_mii0_2_wm
Write mask of sel_com_mii0_2
17 "0"
sel_com_mii0_1_wm
Write mask of sel_com_mii0_1
16 "0"
sel_com_mii0_0_wm
Write mask of sel_com_mii0_0
15 - 10 0
-
 reserved
9 "0"
sel_com_mii0_9
MUX-select for COM MII 0, signal group 9 (TXSFD)
8 "0"
sel_com_mii0_8
MUX-select for COM MII 0, signal group 8 (RXSFD_B)
7 "0"
sel_com_mii0_7
MUX-select for COM MII 0, signal group 7 (RXSFD_A)
6 "0"
sel_com_mii0_6
MUX-select for COM MII 0, signal group 6 (LINK)
5 "0"
sel_com_mii0_5
MUX-select for COM MII 0, signal group 5 (CRS)
4 "0"
sel_com_mii0_4
MUX-select for COM MII 0, signal group 4 (COL)
3 "0"
sel_com_mii0_3
MUX-select for COM MII 0, signal group 3 (TXCLK_B)
2 "0"
sel_com_mii0_2
MUX-select for COM MII 0, signal group 2 (TXCLK_A)
1 "0"
sel_com_mii0_1
MUX-select for COM MII 0, signal group 1 (TX)
0 "0"
sel_com_mii0_0
MUX-select for COM MII 0, signal group 0 (RX)


global_asic_ctrl_com_mii1_io_cfg
IO config for COM MII1
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030060
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
sel_com_mii1_9_wm
Write mask of sel_com_mii1_9
24 "0"
sel_com_mii1_8_wm
Write mask of sel_com_mii1_8
23 "0"
sel_com_mii1_7_wm
Write mask of sel_com_mii1_7
22 "0"
sel_com_mii1_6_wm
Write mask of sel_com_mii1_6
21 "0"
sel_com_mii1_5_wm
Write mask of sel_com_mii1_5
20 "0"
sel_com_mii1_4_wm
Write mask of sel_com_mii1_4
19 "0"
sel_com_mii1_3_wm
Write mask of sel_com_mii1_3
18 "0"
sel_com_mii1_2_wm
Write mask of sel_com_mii1_2
17 "0"
sel_com_mii1_1_wm
Write mask of sel_com_mii1_1
16 "0"
sel_com_mii1_0_wm
Write mask of sel_com_mii1_0
15 - 10 0
-
 reserved
9 "0"
sel_com_mii1_9
MUX-select for COM MII 1, signal group 9 (TXSFD)
8 "0"
sel_com_mii1_8
MUX-select for COM MII 1, signal group 8 (RXSFD_B)
7 "0"
sel_com_mii1_7
MUX-select for COM MII 1, signal group 7 (RXSFD_A)
6 "0"
sel_com_mii1_6
MUX-select for COM MII 1, signal group 6 (LINK)
5 "0"
sel_com_mii1_5
MUX-select for COM MII 1, signal group 5 (CRS)
4 "0"
sel_com_mii1_4
MUX-select for COM MII 1, signal group 4 (COL)
3 "0"
sel_com_mii1_3
MUX-select for COM MII 1, signal group 3 (TXCLK_B)
2 "0"
sel_com_mii1_2
MUX-select for COM MII 1, signal group 2 (TXCLK_A)
1 "0"
sel_com_mii1_1
MUX-select for COM MII 1, signal group 1 (TX)
0 "0"
sel_com_mii1_0
MUX-select for COM MII 1, signal group 0 (RX)


global_asic_ctrl_com_rmii_io_cfg
IO config for COM RMIIs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030064
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 "0"
sel_com_rmii1_5_wm
Write mask of sel_com_rmii1_5
28 "0"
sel_com_rmii1_4_wm
Write mask of sel_com_rmii1_4
27 "0"
sel_com_rmii1_3_wm
Write mask of sel_com_rmii1_3
26 "0"
sel_com_rmii1_2_wm
Write mask of sel_com_rmii1_2
25 "0"
sel_com_rmii1_1_wm
Write mask of sel_com_rmii1_1
24 "0"
sel_com_rmii1_0_wm
Write mask of sel_com_rmii1_0
23 - 22 0
-
 reserved
21 "0"
sel_com_rmii0_5_wm
Write mask of sel_com_rmii0_5
20 "0"
sel_com_rmii0_4_wm
Write mask of sel_com_rmii0_4
19 "0"
sel_com_rmii0_3_wm
Write mask of sel_com_rmii0_3
18 "0"
sel_com_rmii0_2_wm
Write mask of sel_com_rmii0_2
17 "0"
sel_com_rmii0_1_wm
Write mask of sel_com_rmii0_1
16 "0"
sel_com_rmii0_0_wm
Write mask of sel_com_rmii0_0
15 - 14 0
-
 reserved
13 "0"
sel_com_rmii1_5
MUX-select for COM RMII 1, signal group 5
12 "0"
sel_com_rmii1_4
MUX-select for COM RMII 1, signal group 4
11 "0"
sel_com_rmii1_3
MUX-select for COM RMII 1, signal group 3
10 "0"
sel_com_rmii1_2
MUX-select for COM RMII 1, signal group 2
9 "0"
sel_com_rmii1_1
MUX-select for COM RMII 1, signal group 1
8 "0"
sel_com_rmii1_0
MUX-select for COM RMII 1, signal group 0
7 - 6 0
-
 reserved
5 "0"
sel_com_rmii0_5
MUX-select for COM RMII 0, signal group 5
4 "0"
sel_com_rmii0_4
MUX-select for COM RMII 0, signal group 4
3 "0"
sel_com_rmii0_3
MUX-select for COM RMII 0, signal group 3
2 "0"
sel_com_rmii0_2
MUX-select for COM RMII 0, signal group 2
1 "0"
sel_com_rmii0_1
MUX-select for COM RMII 0, signal group 1
0 "0"
sel_com_rmii0_0
MUX-select for COM RMII 0, signal group 0


global_asic_ctrl_com_gxc_io_cfg0
IO config0 for COM GXC
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030068
Bits Reset value Name Description
31 - 28 "0000"
sel_com_xc1_gpio_wm
Write mask of sel_com_xc1_gpio
27 - 24 "0000"
sel_com_xc0_b_gpio_wm
Write mask of sel_com_xc0_b_gpio
23 - 20 "0000"
sel_com_xc0_gpio_wm
Write mask of sel_com_xc0_gpio
19 "0"
sel_com_gxc_sample1_wm
Write mask of sel_com_gxc_sample1
18 "0"
sel_com_gxc_sample0_wm
Write mask of sel_com_gxc_sample0
17 "0"
sel_com_gxc_trigger1_wm
Write mask of sel_com_gxc_trigger1
16 "0"
sel_com_gxc_trigger0_wm
Write mask of sel_com_gxc_trigger0
15 - 12 "0000"
sel_com_xc1_gpio
MUX-select for COM XC1 GPIO 0 - 3
11 - 8 "0000"
sel_com_xc0_b_gpio
MUX-select for COM XC0 GPIO 0 - 3, position b
7 - 4 "0000"
sel_com_xc0_gpio
MUX-select for COM XC0 GPIO 0 - 3
3 "0"
sel_com_gxc_sample1
MUX-select for COM GXC sample 1
2 "0"
sel_com_gxc_sample0
MUX-select for COM GXC sample 0
1 "0"
sel_com_gxc_trigger1
MUX-select for COM GXC trigger 1
0 "0"
sel_com_gxc_trigger0
MUX-select for COM GXC trigger 0


global_asic_ctrl_com_gxc_io_cfg1
IO config1 for COM GXC
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003006c
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 "0"
sel_com_miim_wm
Write mask of sel_com_miim
15 - 1 0
-
 reserved
0 "0"
sel_com_miim
MUX-select for COM_MDC and COM_MDIO (Media Independent Interface Management)


global_asic_ctrl_com_misc_io_cfg
IO config for COM
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030070
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
sel_com_phy_rst_out_n_cs1_wm
Write mask of sel_com_phy_rst_out_n_cs1
19 "0"
sel_com_phy_rst_out_n_int_wm
Write mask of sel_com_phy_rst_out_n_int
18 "0"
clk50out_oe_wm
Write mask of clk50out_oe
17 "0"
sel_clk50out_wm
Write mask of sel_clk50out
16 "0"
clk25out_oe_wm
Write mask of clk25out_oe
15 - 5 0
-
 reserved
4 "0"
sel_com_phy_rst_out_n_cs1
MUX-select for COM_PHY_RST_OUT_N, position com_xspi_cs1
3 "0"
sel_com_phy_rst_out_n_int
MUX-select for COM_PHY_RST_OUT_N, position com_xspi_int
2 "0"
clk50out_oe
Drive enable for CLK50OUT
1 "0"
sel_clk50out
MUX-select for CLK50OUT
0 "0"
clk25out_oe
Drive enable for CLK25OUT


global_asic_ctrl_com_peri_io_cfg
IO config for COM peripherals
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030074
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
sel_com_iol_spi_cs0_wm
Write mask of sel_com_iol_spi_cs0
23 "0"
sel_com_iol_spi_wm
Write mask of sel_com_iol_spi
22 "0"
sel_com_xspi_rst_n_wm
Write mask of sel_com_xspi_rst_n
21 "0"
sel_com_xspi_int_wm
Write mask of sel_com_xspi_int
20 "0"
sel_com_xspi_cs1_wm
Write mask of sel_com_xspi_cs1
19 "0"
sel_com_xspi_wm
Write mask of sel_com_xspi
18 "0"
sel_com_uart0_wm
Write mask of sel_com_uart0
17 "0"
sel_com_spi1_wm
Write mask of sel_com_spi1
16 "0"
sel_com_spi0_wm
Write mask of sel_com_spi0
15 - 9 0
-
 reserved
8 "0"
sel_com_iol_spi_cs0
MUX-select for COM IOL SPI CS 0
7 "0"
sel_com_iol_spi
MUX-select for COM IOL SPI
6 "0"
sel_com_xspi_rst_n
MUX-select for COM xSPI RST_N signal
5 "0"
sel_com_xspi_int
MUX-select for COM xSPI INT signal
4 "0"
sel_com_xspi_cs1
MUX-select for COM xSPI CS1 signal
3 "0"
sel_com_xspi
MUX-select for COM xSPI
2 "0"
sel_com_uart0
MUX-select for COM UART 0
1 "0"
sel_com_spi1
MUX-select for COM SPI 1
0 "0"
sel_com_spi0
MUX-select for COM SPI 0


global_asic_ctrl_com_canfd_io_cfg
IO config for COM CAN-FDs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030078
Bits Reset value Name Description
31 - 23 0
-
 reserved
22 "0"
sel_com_canfd1_pg2_wm
Write mask of sel_com_canfd1_pg2
21 "0"
sel_com_canfd1_pg0_wm
Write mask of sel_com_canfd1_pg0
20 "0"
sel_com_canfd1_wm
Write mask of sel_com_canfd1
19 0
-
 reserved
18 "0"
sel_com_canfd0_pg2_wm
Write mask of sel_com_canfd0_pg2
17 "0"
sel_com_canfd0_pg0_wm
Write mask of sel_com_canfd0_pg0
16 "0"
sel_com_canfd0_wm
Write mask of sel_com_canfd0
15 - 7 0
-
 reserved
6 "0"
sel_com_canfd1_pg2
MUX-select for COM CAN-FD 1, position (pg2)
5 "0"
sel_com_canfd1_pg0
MUX-select for COM CAN-FD 1, position (pg0)
4 "0"
sel_com_canfd1
MUX-select for COM CAN-FD 1, default position
3 0
-
 reserved
2 "0"
sel_com_canfd0_pg2
MUX-select for COM CAN-FD 0, position (pg2)
1 "0"
sel_com_canfd0_pg0
MUX-select for COM CAN-FD 0, position (pg0)
0 "0"
sel_com_canfd0
MUX-select for COM CAN-FD 0, default position


global_asic_ctrl_mot_mmio_io_cfg0
IO config for MOT MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003007c
Bits Reset value Name Description
31 - 16 0x0
sel_mot_mmio0_15_wm
Write mask of sel_mot_mmio0_15
15 - 0 0x0
sel_mot_mmio0_15
MUX-select for MOT MMIO 0 - 15


global_asic_ctrl_mot_mmio_io_cfg1
IO config for MOT MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030080
Bits Reset value Name Description
31 - 16 0x0
sel_mot_mmio16_31_wm
Write mask of sel_mot_mmio16_31
15 - 0 0x0
sel_mot_mmio16_31
MUX-select for MOT MMIO 16 - 31


global_asic_ctrl_mot_mmio_io_cfg2
IO config for MOT MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030084
Bits Reset value Name Description
31 - 16 0x0
sel_mot_mmio32_47_wm
Write mask of sel_mot_mmio32_47
15 - 0 0x0
sel_mot_mmio32_47
MUX-select for MOT MMIO 32 - 47


global_asic_ctrl_mot_mmio_io_cfg3
IO config for MOT MMIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030088
Bits Reset value Name Description
31 0
-
 reserved
30 - 16 0x0
sel_mot_mmio48_62_wm
Write mask of sel_mot_mmio48_62
15 0
-
 reserved
14 - 0 0x0
sel_mot_mmio48_62
MUX-select for MOT MMIO 48 - 62


global_asic_ctrl_mot_pio_io_cfg
IO config for MOT PIOs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003008c
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 - 16 0x0
sel_mot_pio_wm
Write mask of sel_mot_pio
15 - 11 0
-
 reserved
10 - 0 0x0
sel_mot_pio
MUX-select for MOT PIO 0 - 10. Note: APP PIO 7 - 10 can only be used as inputs on SGMII IOs.


global_asic_ctrl_mot_sdm_io_cfg
IO config for MOT SDMs
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030090
Bits Reset value Name Description
31 - 23 0
-
 reserved
22 "0"
sel_sdm2_d2_wm
Write mask of sel_sdm2_d2
21 "0"
sel_sdm2_d1_wm
Write mask of sel_sdm2_d1
20 "0"
sel_sdm2_wm
Write mask of sel_sdm2
19 "0"
sel_sdm1_d1_wm
Write mask of sel_sdm1_d1
18 "0"
sel_sdm1_wm
Write mask of sel_sdm1
17 "0"
sel_sdm0_d1_wm
Write mask of sel_sdm0_d1
16 "0"
sel_sdm0_wm
Write mask of sel_sdm0
15 - 7 0
-
 reserved
6 "0"
sel_sdm2_d2
MUX-select for MOT SDM 2, D2 signal
5 "0"
sel_sdm2_d1
MUX-select for MOT SDM 2, D1 signal
4 "0"
sel_sdm2
MUX-select for MOT SDM 2
3 "0"
sel_sdm1_d1
MUX-select for MOT SDM 1, D1 signal
2 "0"
sel_sdm1
MUX-select for MOT SDM 1
1 "0"
sel_sdm0_d1
MUX-select for MOT SDM 0, D1 signal
0 "0"
sel_sdm0
MUX-select for MOT SDM 0


global_asic_ctrl_mot_biss_io_cfg
IO config for MOT BiSS
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030094
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
sel_mot_biss1_mo_b_wm
Write mask of sel_mot_biss1_mo_b
23 "0"
sel_mot_biss1_mo_a_wm
Write mask of sel_mot_biss1_mo_a
22 "0"
sel_mot_biss1_b_wm
Write mask of sel_mot_biss1_b
21 "0"
sel_mot_biss1_a_wm
Write mask of sel_mot_biss1_a
20 "0"
sel_mot_biss1_wm
Write mask of sel_mot_biss1
19 "0"
sel_mot_biss0_mo_b_wm
Write mask of sel_mot_biss0_mo_b
18 "0"
sel_mot_biss0_mo_a_wm
Write mask of sel_mot_biss0_mo_a
17 "0"
sel_mot_biss0_b_wm
Write mask of sel_mot_biss0_b
16 "0"
sel_mot_biss0_a_wm
Write mask of sel_mot_biss0_a
15 - 9 0
-
 reserved
8 "0"
sel_mot_biss1_mo_b
MUX-select for MOT BiSS 1 MO signal, position (b)
7 "0"
sel_mot_biss1_mo_a
MUX-select for MOT BiSS 1 MO signal, position (a)
6 "0"
sel_mot_biss1_b
MUX-select for MOT BiSS 1, position (b)
5 "0"
sel_mot_biss1_a
MUX-select for MOT BiSS 1, position (a)
4 "0"
sel_mot_biss1
MUX-select for MOT BiSS 1, default position
3 "0"
sel_mot_biss0_mo_b
MUX-select for MOT BiSS 0 MO signal, position (b)
2 "0"
sel_mot_biss0_mo_a
MUX-select for MOT BiSS 0 MO signal, position (a)
1 "0"
sel_mot_biss0_b
MUX-select for MOT BiSS 0, position (b)
0 "0"
sel_mot_biss0_a
MUX-select for MOT BiSS 0, position (a)


global_asic_ctrl_mot_endat_io_cfg
IO config for MOT EnDat
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x40030098
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
sel_mot_endat1_devel_b_wm
Write mask of sel_mot_endat1_devel_b
24 "0"
sel_mot_endat1_devel_a_wm
Write mask of sel_mot_endat1_devel_a
23 "0"
sel_mot_endat1_b_wm
Write mask of sel_mot_endat1_b
22 "0"
sel_mot_endat1_a_wm
Write mask of sel_mot_endat1_a
21 "0"
sel_mot_endat1_wm
Write mask of sel_mot_endat1
20 "0"
sel_mot_endat0_devel_b_wm
Write mask of sel_mot_endat0_devel_b
19 "0"
sel_mot_endat0_devel_a_wm
Write mask of sel_mot_endat0_devel_a
18 "0"
sel_mot_endat0_devel_wm
Write mask of sel_mot_endat0_devel
17 "0"
sel_mot_endat0_b_wm
Write mask of sel_mot_endat0_b
16 "0"
sel_mot_endat0_a_wm
Write mask of sel_mot_endat0_a
15 - 10 0
-
 reserved
9 "0"
sel_mot_endat1_devel_b
MUX-select for MOT EnDat 1 development signals, position (b)
8 "0"
sel_mot_endat1_devel_a
MUX-select for MOT EnDat 1 development signals, position (a)
7 "0"
sel_mot_endat1_b
MUX-select for MOT EnDat 1, position (b)
6 "0"
sel_mot_endat1_a
MUX-select for MOT EnDat 1, position (a)
5 "0"
sel_mot_endat1
MUX-select for MOT EnDat 1, default position
4 "0"
sel_mot_endat0_devel_b
MUX-select for MOT EnDat 0 development signals, position (b)
3 "0"
sel_mot_endat0_devel_a
MUX-select for MOT EnDat 0 development signals, position (a)
2 "0"
sel_mot_endat0_devel
MUX-select for MOT EnDat 0 development signals, default position
1 "0"
sel_mot_endat0_b
MUX-select for MOT EnDat 0, position (b)
0 "0"
sel_mot_endat0_a
MUX-select for MOT EnDat 0, position (a)


global_asic_ctrl_dbg_io_cfg
IO config for software debug functions
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x4003009c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
sel_dbg_trace_ctl_wm
Write mask of sel_dbg_trace_ctl
18 - 16 "000"
sel_dbg_trace_cfg_wm
Write mask of sel_dbg_trace_cfg
15 - 4 0
-
 reserved
3 "0"
sel_dbg_trace_ctl
MUX-select for dbg_trace_ctl signal
2 - 0 "000"
sel_dbg_trace_cfg
Select pins for CoreSight tracing
000: Disable trace:                          sel_trace = 0, sel_trace_d[15:4] = 000000000000, sel_trace_b_d[15:4] = 000000000000
001: Trace with 4 data line:                 sel_trace = 1, sel_trace_d[15:4] = 000000000000, sel_trace_b_d[15:4] = 000000000000
010: Trace with 8 data lines:                sel_trace = 1, sel_trace_d[15:4] = 000000001111, sel_trace_b_d[15:4] = 000000000000
011: Trace with 12 data lines:               sel_trace = 1, sel_trace_d[15:4] = 000011111111, sel_trace_b_d[15:4] = 000000000000
100: Trace with 16 data lines:               sel_trace = 1, sel_trace_d[15:4] = 111111111111, sel_trace_b_d[15:4] = 000000000000
101: Trace with 8 data lines. position (b):  sel_trace = 1, sel_trace_d[15:4] = 000000000000, sel_trace_b_d[15:4] = 000000001111
110: Trace with 12 data lines, position (b): sel_trace = 1, sel_trace_d[15:4] = 000000000000, sel_trace_b_d[15:0] = 000011111111
111: Trace with 16 data lines, position (b): sel_trace = 1, sel_trace_d[15:4] = 000000000000, sel_trace_b_d[15:0] = 111111111111


global_asic_ctrl_ioextender_io_cfg
IO config for IO extender
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300a0
Bits Reset value Name Description
31 0
-
 reserved
30 - 16 0x0
sel_ioe_io_wm
Write mask of sel_ioe_io
15 0
-
 reserved
14 - 0 0x0
sel_ioe_io
MUX-select for IO extender I/O 0 - 14 on dedicated pins


global_asic_ctrl_global_peri_io_cfg
IO config for global peripherals
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300a4
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 16 "00"
sel_sqi_cs_wm
Write mask of sel_sqi_cs
15 - 2 0
-
 reserved
1 - 0 "00"
sel_sqi_cs
MUX-select for SQI CS1/2 signal
sel_sqi_cs[0]: enables select for sqi_cs1n
sel_sqi_cs[1]: enables select for sqi_cs2n


global_asic_ctrl_hif_io_cfg0
IO config for HIF
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300a8
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
sel_hif_b_sirq_wm
Write mask of sel_hif_b_sirq
25 "0"
sel_hif_sirq_wm
Write mask of sel_hif_sirq
24 "0"
sel_hif_dirq_wm
Write mask of sel_hif_dirq
23 "0"
sel_hif_wrhn_wm
Write mask of sel_hif_wrhn
22 "0"
sel_hif_bhe_wm
Write mask of sel_hif_bhe
21 "0"
sel_hif_ale_wm
Write mask of sel_hif_ale
20 "0"
sel_hif_rdy_wm
Write mask of sel_hif_rdy
19 "0"
sel_hif_b_d16_wm
Write mask of sel_hif_b_d16
18 "0"
sel_hif_a_d16_wm
Write mask of sel_hif_a_d16
17 "0"
sel_hif_d16_wm
Write mask of sel_hif_d16
16 "0"
sel_hif_wm
Write mask of sel_hif
15 - 11 0
-
 reserved
10 "0"
sel_hif_b_sirq
MUX-select for HIF SIRQ signal, position (b)
9 "0"
sel_hif_sirq
MUX-select for HIF SIRQ signal, default position
8 "0"
sel_hif_dirq
MUX-select for HIF DIRQ signal, default position
7 "0"
sel_hif_wrhn
MUX-select for HIF WRHN signal
6 "0"
sel_hif_bhe
MUX-select for HIF BHE signal
5 "0"
sel_hif_ale
MUX-select for HIF ALE signal
4 "0"
sel_hif_rdy
MUX-select for HIF RDY signal
3 "0"
sel_hif_b_d16
MUX-select for HIF 16 bit databus (mutually exclusive with sel_hif_a_d16)
2 "0"
sel_hif_a_d16
MUX-select for HIF 16 bit databus (mutually exclusive with sel_hif_b_d16)
1 "0"
sel_hif_d16
MUX-select for HIF 16 bit databus (you must also select either sel_hif_a_d16 or sel_hif_b_d16 for some data lines)
0 "0"
sel_hif
MUX-select for HIF common signals


global_asic_ctrl_hif_io_cfg1
IO config for HIF
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300ac
Bits Reset value Name Description
31 - 16 0x0
sel_hif_a0_15_wm
Write mask of sel_hif_a0_15
15 - 0 0x0
sel_hif_a0_15
MUX-select for HIF address 0 - 15 signals


global_asic_ctrl_hif_io_cfg2
IO config for HIF
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300b0
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 16 "00"
sel_hif_a16_17_wm
Write mask of sel_hif_a16_17
15 - 2 0
-
 reserved
1 - 0 "00"
sel_hif_a16_17
MUX-select for HIF address 16 - 17 signals


global_asic_ctrl_hif_io_cfg3
IO config for HIF
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300b4
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 - 16 0x0
sel_hif_b_a9_17_wm
Write mask of sel_hif_b_a9_17
15 - 9 0
-
 reserved
8 - 0 0x0
sel_hif_b_a9_17
MUX-select for HIF address 9 - 17 signals, position (b)
Note: The signals hif_a14, hif_a15 and hif_a16 can only be used as inputs for position (b). I.e. when the
      related bits are set here they cannot be used as outputs in PIO mode. This is because the LVDS IOs
      they are located on do not provide output functionality.


global_asic_ctrl_pcie_dbg_io_cfg
IO config for PCIe debug functions
This register is a write mask register, i.e. lower 16 bits are only writeable, if corresponding upper bits are set.
R/W
0x00000000
Address : 0x400300b8
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 "0"
test_sel_pcie_link0_dbg_wm
Write mask of test_sel_pcie_link0_dbg
15 - 1 0
-
 reserved
0 "0"
test_sel_pcie_link0_dbg
Testmode MUX-select


global_asic_ctrl_pcie_isolation
Register for PCIE AXI port isolation
R/W
0x00000000
Address : 0x400300bc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
axi_app_mst_isolated_ro
1: interface 'app_mst' was successfully isolated
0: interface 'app_mst' is currently not isolated
17 -
axi_com_mst_isolated_ro
1: interface 'com_mst' was successfully isolated
0: interface 'com_mst' is currently not isolated
16 -
axi_slv_isolated_ro
1: interface 'axi_slv' was successfully isolated
0: interface 'axi_slv' is currently not isolated
15 - 3 0
-
 reserved
2 "0"
axi_app_mst_isolate
1: Request interface 'app_mst' to be isolated, preventing any further AXI transactions
0: Disable isolation on interface 'app_mst'
1 "0"
axi_com_mst_isolate
1: Request interface 'com_mst' to be isolated, preventing any further AXI transactions
0: Disable isolation on interface 'com_mst'
0 "0"
axi_slv_isolate
1: Request interface 'axi_slv' to be isolated, preventing any further AXI transactions
0: Disable isolation on interface 'axi_slv'


global_asic_ctrl_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x400300c0
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
com_gic_ecc_fatal
Event: COM CA32 GIC fatal ECC error occured.


global_asic_ctrl_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_global_asic_ctrl_irq_raw).
R/W
0x00000000
Address : 0x400300c4
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
com_gic_ecc_fatal
Event: COM CA32 GIC fatal ECC error occured.


global_asic_ctrl_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_global_asic_ctrl_irq_raw
R/W
0x00000000
Address : 0x400300c8
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
com_gic_ecc_fatal
Event: COM CA32 GIC fatal ECC error occured.


global_asic_ctrl_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 1 when no IRQ is set:
  0 : irq-com_gic_ecc_fatal
  1 : no active IRQ
R/W
0x00000000
Address : 0x400300cc
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
com_gic_ecc_fatal
Event: COM CA32 GIC fatal ECC error occured.


global_asic_ctrl_sdio_pad_cfg
SDIO pad configuration register
R/W
0x00000000
Address : 0x400300d0
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sel_ip_ie_ctrl
Input-enable select of the SDIO IOs.
0 :
The input-enables of the SDIO IOs are controlled by the PAD_CTRL module.
Use this when the SDIO IP is not used or when other functions than SDIO are multiplexed
on the SDIO IOs
1 : The input-enables of the SDIO IOs are controlled by the SDIO IP and the settings from the PAD_CTRL.
module are ignored. Use this when the SDIO IP is used.
0 "0"
sel_ip_drvss
Drive strength select of the SDIO IOs.
0 :
Use the drive-strength settings of the PAD_CTRL module for each SDIO IO individually and ignore
the setting of the SDIO IP register SRS15.DSS. This is recommended when the SDIO IP is not used
or other functions than SDIO are multiplexed on the SDIO IOs
1 : Use the drive-strength settings of the PAD_CTRL module for all SDIO IOs in common and take care
of the setting of the SDIO IP register SRS15.DSS. This is recommended when the SDIO IP is used.
Basically the drive strength of the SDIO IOs must be programmed by the appropriate
registers in the PAD_CTRL module regardless whether the IOs are used for SDIO IP or not.
For SDIO the IP provides an additional setup possibility which can be activated by this bit here:
In register SRS15 of the SDOO IP the drive strength can be selected according to the Modes A to D
which are defined in the SDIO specification. This is realized by the following remapping of the DS
settings of the SDIO IO of PAD_CTRL:
The DS settings of SDIO DAT0-3 IOs are used to define the drive strength of all SDIO IOs when the
sel_ip_drvss bit is set:
   Adr_pad_ctrl_sdio_dat0.DS[2:0] define SDIO Drive Type B (SDIO register SRS15.DSS programmed to 00, i.e. Mode B, default)
   Adr_pad_ctrl_sdio_dat1.DS[2:0] define SDIO Drive Type A (SDIO register SRS15.DSS programmed to 01, i.e. Mode A)
   Adr_pad_ctrl_sdio_dat2.DS[2:0] define SDIO Drive Type C (SDIO register SRS15.DSS programmed to 10, i.e. Mode C)
   Adr_pad_ctrl_sdio_dat3.DS[2:0] define SDIO Drive Type D (SDIO register SRS15.DSS programmed to 11, i.e. Mode D)
 Note: For the clock feedback inside the netX22XX package (SDIO_LPBK_DQS_O->SDIO_LPBK_DQS_I) always the DS values
       of the PAD_CTRL registers Adr_pad_ctrl_sdio_lpbk_dqs_o and Adr_pad_ctrl_sdio_lpbk_dqs_i are taken because it
       might be necessary to set up the DS of these signals differently as they don't have loads outside the package
 For details see:
 - SDIO IP documentation SRS15 register
 - SDIO specification "Physical layer, section Driver Strength
   (e.g. "Part 1 Physical Layer Specification Ver.9.00 Final 20220210.pdf", section 6.7, P.326)



Base Address Area: global_pad_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pad_ctrl_dpm0_spi_mosi
1 4 R/W pad_ctrl_dpm0_spi_miso
2 8 R/W pad_ctrl_dpm0_spi_clk
3 c R/W pad_ctrl_dpm0_spi_sio3
4 10 R/W pad_ctrl_dpm0_spi_sio2
5 14 R/W pad_ctrl_dpm0_spi_csn
6 18 R/W pad_ctrl_dpm0_spi_dirq
7 1c R/W pad_ctrl_dpm1_spi_mosi
8 20 R/W pad_ctrl_dpm1_spi_miso
9 24 R/W pad_ctrl_dpm1_spi_clk
a 28 R/W pad_ctrl_dpm1_spi_sio3
b 2c R/W pad_ctrl_dpm1_spi_sio2
c 30 R/W pad_ctrl_dpm1_spi_csn
d 34 R/W pad_ctrl_dpm1_spi_dirq
e 38 R/W pad_ctrl_com_rgmii0_rxd3
f 3c R/W pad_ctrl_com_gm0_in0
10 40 R/W pad_ctrl_com_rgmii0_rxc
11 44 R/W pad_ctrl_com_rgmii0_rxd0
12 48 R/W pad_ctrl_com_rgmii0_rxctl
13 4c R/W pad_ctrl_com_mdio
14 50 R/W pad_ctrl_com_gm0_in3
15 54 R/W pad_ctrl_com_rgmii0_txctl
16 58 R/W pad_ctrl_com_rgmii0_txc
17 5c R/W pad_ctrl_com_gm1_in0
18 60 R/W pad_ctrl_com_rgmii0_txd1
19 64 R/W pad_ctrl_com_rgmii0_txd0
1a 68 R/W pad_ctrl_com_rgmii0_txd2
1b 6c R/W pad_ctrl_com_rgmii0_txd3
1c 70 R/W pad_ctrl_com_rgmii1_rxd3
1d 74 R/W pad_ctrl_com_gm1_in3
1e 78 R/W pad_ctrl_com_mdc
1f 7c R/W pad_ctrl_com_rgmii1_rxc
20 80 R/W pad_ctrl_com_rgmii1_rxd0
21 84 R/W pad_ctrl_com_rgmii1_rxctl
22 88 R/W pad_ctrl_com_rgmii1_txctl
23 8c R/W pad_ctrl_com_rgmii1_txc
24 90 R/W pad_ctrl_com_rgmii1_txd1
25 94 R/W pad_ctrl_com_rgmii1_txd0
26 98 R/W pad_ctrl_com_rgmii1_txd2
27 9c R/W pad_ctrl_clk25out
28 a0 R/W pad_ctrl_com_rgmii1_txd3
29 a4 R/W pad_ctrl_com_xspi_csn1
2a a8 R/W pad_ctrl_com_xspi_csn0
2b ac R/W pad_ctrl_com_xspi_int
2c b0 R/W pad_ctrl_com_xspi_clk
2d b4 R/W pad_ctrl_com_xspi_rwds
2e b8 R/W pad_ctrl_com_xspi_dq1
2f bc R/W pad_ctrl_com_xspi_dq6
30 c0 R/W pad_ctrl_com_xspi_dq7
31 c4 R/W pad_ctrl_com_xspi_dq0
32 c8 R/W pad_ctrl_com_xspi_dq5
33 cc R/W pad_ctrl_com_xspi_dq4
34 d0 R/W pad_ctrl_com_xspi_dq2
35 d4 R/W pad_ctrl_com_xspi_dq3
36 d8 R/W pad_ctrl_sqi_sio2
37 dc R/W pad_ctrl_sqi_miso_sio1
38 e0 R/W pad_ctrl_sqi_clk
39 e4 R/W pad_ctrl_sqi_mosi_sio0
3a e8 R/W pad_ctrl_sqi_sio3
3b ec R/W pad_ctrl_sqi_cs0n
3c f0 R/W pad_ctrl_app_mdc
3d f4 R/W pad_ctrl_app_mdio
3e f8 R/W pad_ctrl_dbg_trace_clk
3f fc R/W pad_ctrl_dbg_trace_d0
40 100 R/W pad_ctrl_dbg_trace_d1
41 104 R/W pad_ctrl_dbg_trace_d2
42 108 R/W pad_ctrl_dbg_trace_d3
43 10c R/W pad_ctrl_com_io3
44 110 R/W pad_ctrl_com_io1
45 114 R/W pad_ctrl_com_io2
46 118 R/W pad_ctrl_com_io0
47 11c R/W pad_ctrl_xspi_csn1
48 120 R/W pad_ctrl_xspi_csn0
49 124 R/W pad_ctrl_xspi_int
4a 128 R/W pad_ctrl_xspi_rwds
4b 12c R/W pad_ctrl_xspi_clk
4c 130 R/W pad_ctrl_xspi_dq1
4d 134 R/W pad_ctrl_xspi_dq7
4e 138 R/W pad_ctrl_xspi_dq6
4f 13c R/W pad_ctrl_xspi_dq0
50 140 R/W pad_ctrl_xspi_dq5
51 144 R/W pad_ctrl_xspi_dq2
52 148 R/W pad_ctrl_xspi_dq3
53 14c R/W pad_ctrl_xspi_dq4
54 150 R/W pad_ctrl_com_io5
55 154 R/W pad_ctrl_com_io4
56 158 R/W pad_ctrl_ioe_strb
57 15c R/W pad_ctrl_ioe_sck_nrdy
58 160 R/W pad_ctrl_com_io6
59 164 R/W pad_ctrl_ioe_miso
5a 168 R/W pad_ctrl_ioe_mosi_nrun
5b 16c R/W pad_ctrl_rst_out_n
5c 170 R/W pad_ctrl_com_io7
5d 174 R/W pad_ctrl_uart_tx
5e 178 R/W pad_ctrl_uart_rx
5f 17c R/W pad_ctrl_app_mmio0
60 180 R/W pad_ctrl_app_mmio2
61 184 R/W pad_ctrl_app_mmio1
62 188 R/W pad_ctrl_app_mmio5
63 18c R/W pad_ctrl_app_mmio6
64 190 R/W pad_ctrl_app_mmio7
65 194 R/W pad_ctrl_app_mmio3
66 198 R/W pad_ctrl_app_mmio4
67 19c R/W pad_ctrl_app_mmio8
68 1a0 R/W pad_ctrl_app_mmio9
69 1a4 R/W pad_ctrl_app_mmio10
6a 1a8 R/W pad_ctrl_app_mmio12
6b 1ac R/W pad_ctrl_app_mmio11
6c 1b0 R/W pad_ctrl_app_mmio13
6d 1b4 R/W pad_ctrl_app_mmio15
6e 1b8 R/W pad_ctrl_app_mmio14
6f-7f 1bc-1fc -  reserved
80 200 R/W pad_ctrl_com_rgmii0_rxd1
81 204 R/W pad_ctrl_com_rgmii0_rxd2
82 208 R/W pad_ctrl_com_gm0_in1
83 20c R/W pad_ctrl_com_gm0_in2
84 210 R/W pad_ctrl_com_rgmii1_rxd1
85 214 R/W pad_ctrl_com_rgmii1_rxd2
86 218 R/W pad_ctrl_com_gm1_in1
87 21c R/W pad_ctrl_com_gm1_in2
88 220 R/W pad_ctrl_app_sgmii_rx_p
89 224 R/W pad_ctrl_app_sgmii_rx_n
8a 228 R/W pad_ctrl_app_sgmii_tx_p
8b 22c R/W pad_ctrl_app_sgmii_tx_n
8c-8f 230-23c -  reserved
90 240 R/W pad_ctrl_sdio_clk
91 244 R/W pad_ctrl_sdio_cmd
92 248 R/W pad_ctrl_sdio_dat0
93 24c R/W pad_ctrl_sdio_dat1
94 250 R/W pad_ctrl_sdio_dat2
95 254 R/W pad_ctrl_sdio_dat3
96 258 R/W pad_ctrl_sdio_ds
97 25c R/W pad_ctrl_sdio_lpbk_dqs_o
98 260 R/W pad_ctrl_sdio_lpbk_dqs_i
99-ff 264-3fc -  reserved

pad_ctrl_dpm0_spi_mosi
Pad configuration register of port DPM0_SPI_MOSI (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030400
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd348 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_miso
Pad configuration register of port DPM0_SPI_MISO (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030404
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x72d8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_clk
Pad configuration register of port DPM0_SPI_CLK (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030408
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x942b must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_sio3
Pad configuration register of port DPM0_SPI_SIO3 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003040c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd90d must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_sio2
Pad configuration register of port DPM0_SPI_SIO2 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030410
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa59a must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_csn
Pad configuration register of port DPM0_SPI_CSN (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030414
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xefc6 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm0_spi_dirq
Pad configuration register of port DPM0_SPI_DIRQ (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030418
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x88b1 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_mosi
Pad configuration register of port DPM1_SPI_MOSI (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003041c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb808 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_miso
Pad configuration register of port DPM1_SPI_MISO (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030420
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x1998 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_clk
Pad configuration register of port DPM1_SPI_CLK (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030424
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa85b must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_sio3
Pad configuration register of port DPM1_SPI_SIO3 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030428
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb24d must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_sio2
Pad configuration register of port DPM1_SPI_SIO2 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003042c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xceda must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_csn
Pad configuration register of port DPM1_SPI_CSN (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030430
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd3b6 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_dpm1_spi_dirq
Pad configuration register of port DPM1_SPI_DIRQ (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030434
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe3f1 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_rxd3
Pad configuration register of port COM_RGMII0_RXD3 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030438
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x623d must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_gm0_in0
Pad configuration register of port COM_GM0_IN0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003043c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xbcb9 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_rxc
Pad configuration register of port COM_RGMII0_RXC (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030440
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x3bd2 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_rxd0
Pad configuration register of port COM_RGMII0_RXD0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030444
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x4548 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_rxctl
Pad configuration register of port COM_RGMII0_RXCTL (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030448
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x865e must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_mdio
Pad configuration register of port COM_MDIO (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003044c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xbd56 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_gm0_in3
Pad configuration register of port COM_GM0_IN3 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030450
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x8321 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txctl
Pad configuration register of port COM_RGMII0_TXCTL (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030454
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa928 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txc
Pad configuration register of port COM_RGMII0_TXC (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030458
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2312 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_gm1_in0
Pad configuration register of port COM_GM1_IN0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003045c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xab88 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txd1
Pad configuration register of port COM_RGMII0_TXD1 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030460
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe94f must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txd0
Pad configuration register of port COM_RGMII0_TXD0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030464
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb9a must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txd2
Pad configuration register of port COM_RGMII0_TXD2 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030468
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xce3a must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_txd3
Pad configuration register of port COM_RGMII0_TXD3 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003046c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2cef must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_rxd3
Pad configuration register of port COM_RGMII1_RXD3 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030470
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x37a1 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_gm1_in3
Pad configuration register of port COM_GM1_IN3 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030474
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x9410 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_mdc
Pad configuration register of port COM_MDC (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030478
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa600 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_rxc
Pad configuration register of port COM_RGMII1_RXC (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x4003047c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xf6a5 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_rxd0
Pad configuration register of port COM_RGMII1_RXD0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030480
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x10d4 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_rxctl
Pad configuration register of port COM_RGMII1_RXCTL (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030484
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x910b must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txctl
Pad configuration register of port COM_RGMII1_TXCTL (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030488
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xbe7d must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txc
Pad configuration register of port COM_RGMII1_TXC (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003048c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xee65 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txd1
Pad configuration register of port COM_RGMII1_TXD1 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030490
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xbcd3 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txd0
Pad configuration register of port COM_RGMII1_TXD0 (password protected).
Pad type: PRWDWUWHWSWDGE_H_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030494
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5e06 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txd2
Pad configuration register of port COM_RGMII1_TXD2 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030498
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x9ba6 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_clk25out
Pad configuration register of port CLK25OUT (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
Note:
   The default states are already applied during reset.
R/W
0x00001050
Address : 0x4003049c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x84ba must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_rgmii1_txd3
Pad configuration register of port COM_RGMII1_TXD3 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x400304a0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x7973 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_csn1
Pad configuration register of port COM_XSPI_CSN1 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304a4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa389 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_csn0
Pad configuration register of port COM_XSPI_CSN0 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304a8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xdf1e must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_int
Pad configuration register of port COM_XSPI_INT (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400304ac
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2c89 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_clk
Pad configuration register of port COM_XSPI_CLK (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304b0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x24c3 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_rwds
Pad configuration register of port COM_XSPI_RWDS (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304b4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x54fa must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq1
Pad configuration register of port COM_XSPI_DQ1 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304b8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xa77d must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq6
Pad configuration register of port COM_XSPI_DQ6 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304bc
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x9632 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq7
Pad configuration register of port COM_XSPI_DQ7 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304c0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x4646 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq0
Pad configuration register of port COM_XSPI_DQ0 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304c4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x7709 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq5
Pad configuration register of port COM_XSPI_DQ5 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304c8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe6af must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq4
Pad configuration register of port COM_XSPI_DQ4 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304cc
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x36db must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq2
Pad configuration register of port COM_XSPI_DQ2 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304d0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd7e0 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_xspi_dq3
Pad configuration register of port COM_XSPI_DQ3 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304d4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x794 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_sio2
Pad configuration register of port SQI_SIO2 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304d8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xda5b must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_miso_sio1
Pad configuration register of port SQI_MISO_SIO1 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304dc
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x3ce3 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_clk
Pad configuration register of port SQI_CLK (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304e0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x85f9 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_mosi_sio0
Pad configuration register of port SQI_MOSI_SIO0 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304e4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2ae1 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_sio3
Pad configuration register of port SQI_SIO3 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304e8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xda9e must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_sqi_cs0n
Pad configuration register of port SQI_CS0N (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x400304ec
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe378 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select (pull-up/down pad, up by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_app_mdc
Pad configuration register of port APP_MDC (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400304f0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xaa37 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_app_mdio
Pad configuration register of port APP_MDIO (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400304f4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x8548 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_dbg_trace_clk
Pad configuration register of port DBG_TRACE_CLK (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x400304f8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc307 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_dbg_trace_d0
Pad configuration register of port DBG_TRACE_D0 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x400304fc
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc44b must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_dbg_trace_d1
Pad configuration register of port DBG_TRACE_D1 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030500
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x143f must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_dbg_trace_d2
Pad configuration register of port DBG_TRACE_D2 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030504
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x64a2 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_dbg_trace_d3
Pad configuration register of port DBG_TRACE_D3 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030508
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb4d6 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_io3
Pad configuration register of port COM_IO3 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x4003050c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x106f must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_io1
Pad configuration register of port COM_IO1 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030510
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x91bf must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_io2
Pad configuration register of port COM_IO2 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030514
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5087 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_com_io0
Pad configuration register of port COM_IO0 (password protected).
Pad type: PRWDWUWHWSWDGE_V_G
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030518
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd157 must be written here to validate a write access to this register.
15 - 14 0
-
 reserved
13 "0"
he
hold last value of tristate IO instead of floating away (off by default)
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select (pull-up/down pad, down by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 - 2 0
-
 reserved
1 - 0 "00"
ds
driving strength (low by default)


pad_ctrl_xspi_csn1
Pad configuration register of port XSPI_CSN1 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003051c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x32cf must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_csn0
Pad configuration register of port XSPI_CSN0 (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030520
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x3beb must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_int
Pad configuration register of port XSPI_INT (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030524
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xce94 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_rwds
Pad configuration register of port XSPI_RWDS (password protected).
Pad type: PRWHSWCDGSD_V
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030528
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb098 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_clk
Pad configuration register of port XSPI_CLK (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003052c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc1e2 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq1
Pad configuration register of port XSPI_DQ1 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030530
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xeaf6 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq7
Pad configuration register of port XSPI_DQ7 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030534
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe869 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq6
Pad configuration register of port XSPI_DQ6 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030538
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe8ac must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq0
Pad configuration register of port XSPI_DQ0 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003053c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xea33 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq5
Pad configuration register of port XSPI_DQ5 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030540
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe9e2 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq2
Pad configuration register of port XSPI_DQ2 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030544
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xebb8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq3
Pad configuration register of port XSPI_DQ3 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030548
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xeb7d must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_xspi_dq4
Pad configuration register of port XSPI_DQ4 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003054c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe927 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_io5
Pad configuration register of port COM_IO5 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001040
Address : 0x40030550
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x921c must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "0"
pe
pull enable (pull-up/down pad, disabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_io4
Pad configuration register of port COM_IO4 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030554
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd2f4 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_ioe_strb
Pad configuration register of port IOE_STRB (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030558
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x8d81 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_ioe_sck_nrdy
Pad configuration register of port IOE_SCK_NRDY (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x4003055c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x97dc must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_io6
Pad configuration register of port COM_IO6 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030560
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5324 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_ioe_miso
Pad configuration register of port IOE_MISO (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030564
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x8d04 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_ioe_mosi_nrun
Pad configuration register of port IOE_MOSI_NRUN (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030568
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc2c2 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_rst_out_n
Pad configuration register of port RST_OUT_N (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003056c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x6dd must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_io7
Pad configuration register of port COM_IO7 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030570
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x13cc must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_uart_tx
Pad configuration register of port UART_TX (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030574
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe9fb must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_uart_rx
Pad configuration register of port UART_RX (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001070
Address : 0x40030578
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xeedf must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio0
Pad configuration register of port APP_MMIO0 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003057c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe7d9 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio2
Pad configuration register of port APP_MMIO2 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030580
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xf191 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio1
Pad configuration register of port APP_MMIO1 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030584
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xeefd must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio5
Pad configuration register of port APP_MMIO5 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030588
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc36d must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio6
Pad configuration register of port APP_MMIO6 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003058c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xdc01 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio7
Pad configuration register of port APP_MMIO7 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030590
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd525 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio3
Pad configuration register of port APP_MMIO3 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030594
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xf8b5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio4
Pad configuration register of port APP_MMIO4 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x40030598
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xca49 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio8
Pad configuration register of port APP_MMIO8 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x4003059c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xbcd1 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio9
Pad configuration register of port APP_MMIO9 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305a0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xb5f5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio10
Pad configuration register of port APP_MMIO10 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305a4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xd33e must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio12
Pad configuration register of port APP_MMIO12 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305a8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5957 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio11
Pad configuration register of port APP_MMIO11 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305ac
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x960e must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio13
Pad configuration register of port APP_MMIO13 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305b0
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x1c67 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio15
Pad configuration register of port APP_MMIO15 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305b4
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x82cd must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_app_mmio14
Pad configuration register of port APP_MMIO14 (password protected).
Pad type: PRWHSWCDGSD_H
For more details refer to description of register pad_ctrl_clk25out.
R/W
0x00001050
Address : 0x400305b8
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xc7fd must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "0"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, disabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_com_rgmii0_rxd1
Pad configuration register of port COM_RGMII0_RXD1 (password protected).
Pad type: sgmii0_rx_p (SGMII RX LVDS P-type)
R/W
0x00001000
Address : 0x40030600
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x1ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_rgmii0_rxd2
Pad configuration register of port COM_RGMII0_RXD2 (password protected).
Pad type: sgmii0_rx_n (SGMII RX LVDS N-type)
R/W
0x00001000
Address : 0x40030604
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x1cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_gm0_in1
Pad configuration register of port COM_GM0_IN1 (password protected).
Pad type: sgmii0_tx_n (SGMII TX LVDS N-type)
R/W
0x00001000
Address : 0x40030608
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_gm0_in2
Pad configuration register of port COM_GM0_IN2 (password protected).
Pad type: sgmii0_tx_p (SGMII TX LVDS P-type)
R/W
0x00001000
Address : 0x4003060c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x2cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_rgmii1_rxd1
Pad configuration register of port COM_RGMII1_RXD1 (password protected).
Pad type: sgmii0_rx_p (SGMII RX LVDS P-type)
R/W
0x00001000
Address : 0x40030610
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x3ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_rgmii1_rxd2
Pad configuration register of port COM_RGMII1_RXD2 (password protected).
Pad type: sgmii0_rx_n (SGMII RX LVDS N-type)
R/W
0x00001000
Address : 0x40030614
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x3cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_gm1_in1
Pad configuration register of port COM_GM1_IN1 (password protected).
Pad type: sgmii0_tx_n (SGMII TX LVDS N-type)
R/W
0x00001000
Address : 0x40030618
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x4ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_com_gm1_in2
Pad configuration register of port COM_GM1_IN2 (password protected).
Pad type: sgmii0_tx_p (SGMII TX LVDS P-type)
R/W
0x00001000
Address : 0x4003061c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x4cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_app_sgmii_rx_p
Pad configuration register of port APP_SGMII_RX_P (password protected).
Pad type: sgmii0_rx_p (SGMII RX LVDS P-type)
R/W
0x00001000
Address : 0x40030620
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_app_sgmii_rx_n
Pad configuration register of port APP_SGMII_RX_N (password protected).
Pad type: sgmii0_rx_n (SGMII RX LVDS N-type)
R/W
0x00001000
Address : 0x40030624
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x5cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_app_sgmii_tx_p
Pad configuration register of port APP_SGMII_TX_P (password protected).
Pad type: sgmii0_tx_n (SGMII TX LVDS P-type)
R/W
0x00001000
Address : 0x40030628
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x6ac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_app_sgmii_tx_n
Pad configuration register of port APP_SGMII_TX_N (password protected).
Pad type: sgmii0_tx_p (SGMII TX LVDS N-type)
R/W
0x00001000
Address : 0x4003062c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x6cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 10 0
-
 reserved
9 - 8 "00"
st
schmitt trigger (off by default)
7 - 0 0
-
 reserved


pad_ctrl_sdio_clk
Pad configuration register of port SDIO_CLK (password protected).
Pad type: PRWHSWCDGSD_V
Note:
   The default states are already applied during reset.
R/W
0x00001070
Address : 0x40030640
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xfac8 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_cmd
Pad configuration register of port SDIO_CMD (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x40030644
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x7cb5 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_dat0
Pad configuration register of port SDIO_DAT0 (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x40030648
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x98ff must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_dat1
Pad configuration register of port SDIO_DAT1 (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x4003064c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xe468 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_dat2
Pad configuration register of port SDIO_DAT2 (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x40030650
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x61d3 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_dat3
Pad configuration register of port SDIO_DAT3 (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x40030654
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0x1d44 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_ds
Pad configuration register of port SDIO_DS (password protected).
Pad type: PRWHSWCDGSD_V
R/W
0x00001070
Address : 0x40030658
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xcecb must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_lpbk_dqs_o
Pad configuration register of port SDIO_LPBK_DQS_O (password protected).
Pad type: PRWHSWCDGSD_V
Note: This is a package internal signal.
R/W
0x00001070
Address : 0x4003065c
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xacec must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)


pad_ctrl_sdio_lpbk_dqs_i
Pad configuration register of port SDIO_LPBK_DQS_I (password protected).
Pad type: PRWHSWCDGSD_V
Note: This is a package internal signal.
R/W
0x00001070
Address : 0x40030660
Bits Reset value Name Description
31 - 16 0x0
pw
Password: pw=0xdd54 must be written here to validate a write access to this register.
15 - 13 0
-
 reserved
12 "1"
ie
input enable (enabled by default)
11 - 9 0
-
 reserved
8 "0"
st
schmitt trigger (off by default)
7 0
-
 reserved
6 "1"
sl
slew rate control (on by default)
5 "1"
ps
pull select: 1: pull-up, 0: down if pull is enabled by pe, enabled by default)
4 "1"
pe
pull enable (pull-up/down pad, enabled by default)
3 0
-
 reserved
2 - 0 "000"
ds
driving strength (low by default)



Base Address Area: global_ioextender_mux_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ioextender_ioe_o0_sel
1 4 R/W ioextender_ioe_o1_sel
2 8 R/W ioextender_ioe_o2_sel
3 c R/W ioextender_ioe_o3_sel
4 10 R/W ioextender_ioe_o4_sel
5 14 R/W ioextender_ioe_o5_sel
6 18 R/W ioextender_ioe_o6_sel
7 1c R/W ioextender_ioe_o7_sel
8 20 R/W ioextender_ioe_o8_sel
9 24 R/W ioextender_ioe_o9_sel
a 28 R/W ioextender_ioe_o10_sel
b 2c R/W ioextender_ioe_o11_sel
c 30 R/W ioextender_ioe_o12_sel
d 34 R/W ioextender_ioe_o13_sel
e 38 R/W ioextender_ioe_o14_sel
f 3c R/W ioextender_ioe_o15_sel
10 40 R/W ioextender_ioe_o16_sel
11 44 R/W ioextender_ioe_o17_sel
12 48 R/W ioextender_ioe_o18_sel
13 4c R/W ioextender_ioe_o19_sel
14 50 R/W ioextender_ioe_o20_sel
15 54 R/W ioextender_ioe_o21_sel
16 58 R/W ioextender_ioe_o22_sel
17 5c R/W ioextender_ioe_o23_sel
18 60 R/W ioextender_ioe_o24_sel
19 64 R/W ioextender_ioe_o25_sel
1a 68 R/W ioextender_ioe_o26_sel
1b 6c R/W ioextender_ioe_o27_sel
1c 70 R/W ioextender_ioe_o28_sel
1d 74 R/W ioextender_ioe_o29_sel
1e 78 R/W ioextender_ioe_o30_sel
1f 7c R/W ioextender_ioe_o31_sel
20 80 R/W ioextender_ioe_o32_sel
21 84 R/W ioextender_ioe_o33_sel
22 88 R/W ioextender_ioe_o34_sel
23 8c R/W ioextender_ioe_o35_sel
24 90 R/W ioextender_ioe_o36_sel
25 94 R/W ioextender_ioe_o37_sel
26 98 R/W ioextender_ioe_o38_sel
27 9c R/W ioextender_ioe_o39_sel
28 a0 R/W ioextender_ioe_o40_sel
29 a4 R/W ioextender_ioe_o41_sel
2a a8 R/W ioextender_ioe_o42_sel
2b ac R/W ioextender_ioe_o43_sel
2c b0 R/W ioextender_ioe_o44_sel
2d b4 R/W ioextender_ioe_o45_sel
2e b8 R/W ioextender_ioe_o46_sel
2f bc R/W ioextender_ioe_o47_sel
30 c0 R/W ioextender_ioe_o48_sel
31 c4 R/W ioextender_ioe_o49_sel
32 c8 R/W ioextender_ioe_o50_sel
33 cc R/W ioextender_ioe_o51_sel
34 d0 R/W ioextender_ioe_o52_sel
35 d4 R/W ioextender_ioe_o53_sel
36 d8 R/W ioextender_ioe_o54_sel
37 dc R/W ioextender_ioe_o55_sel
38 e0 R/W ioextender_ioe_o56_sel
39 e4 R/W ioextender_ioe_o57_sel
3a e8 R/W ioextender_ioe_o58_sel
3b ec R/W ioextender_ioe_o59_sel
3c f0 R/W ioextender_ioe_o60_sel
3d f4 R/W ioextender_ioe_o61_sel
3e f8 R/W ioextender_ioe_o62_sel
3f fc R/W ioextender_ioe_o63_sel
40 100 R/W ioextender_ioe_mosi_dc_oe_sel
41 104 R/W ioextender_ioe_mosi_dc_o_sel
42 108 R/W ioextender_ioe_sck_dc_oe_sel
43 10c R/W ioextender_ioe_sck_dc_o_sel
44-7f 110-1fc -  reserved
80 200 R/W ioextender_app_mdio_in_sel
81 204 R/W ioextender_com_mdio_in_sel
82 208 R/W ioextender_mot_pio_in0_sel
83 20c R/W ioextender_mot_pio_in1_sel
84 210 R/W ioextender_mot_pio_in2_sel
85 214 R/W ioextender_mot_pio_in3_sel
86 218 R/W ioextender_mot_pio_in4_sel
87 21c R/W ioextender_mot_pio_in5_sel
88 220 R/W ioextender_mot_pio_in6_sel
89 224 R/W ioextender_mot_pio_in7_sel
8a 228 R/W ioextender_mot_pio_in8_sel
8b 22c R/W ioextender_mot_pio_in9_sel
8c 230 R/W ioextender_mot_pio_in10_sel
8d 234 R/W ioextender_mot_pio_in11_sel
8e 238 R/W ioextender_mot_pio_in12_sel
8f 23c R/W ioextender_mot_pio_in13_sel
90 240 R/W ioextender_mot_pio_in14_sel
91 244 R/W ioextender_mot_pio_in15_sel
92 248 R/W ioextender_app_pio_in0_sel
93 24c R/W ioextender_app_pio_in1_sel
94 250 R/W ioextender_app_pio_in2_sel
95 254 R/W ioextender_app_pio_in3_sel
96 258 R/W ioextender_app_pio_in4_sel
97 25c R/W ioextender_app_pio_in5_sel
98 260 R/W ioextender_app_pio_in6_sel
99 264 R/W ioextender_app_pio_in7_sel
9a 268 R/W ioextender_app_pio_in8_sel
9b 26c R/W ioextender_app_pio_in9_sel
9c 270 R/W ioextender_app_pio_in10_sel
9d 274 R/W ioextender_app_pio_in11_sel
9e 278 R/W ioextender_app_pio_in12_sel
9f 27c R/W ioextender_app_pio_in13_sel
a0 280 R/W ioextender_app_pio_in14_sel
a1 284 R/W ioextender_app_pio_in15_sel
a2 288 R/W ioextender_com_pio_in0_sel
a3 28c R/W ioextender_com_pio_in1_sel
a4 290 R/W ioextender_com_pio_in2_sel
a5 294 R/W ioextender_com_pio_in3_sel
a6 298 R/W ioextender_com_pio_in4_sel
a7 29c R/W ioextender_com_pio_in5_sel
a8 2a0 R/W ioextender_com_pio_in6_sel
a9 2a4 R/W ioextender_com_pio_in7_sel
aa 2a8 R/W ioextender_com_pio_in8_sel
ab 2ac R/W ioextender_com_pio_in9_sel
ac 2b0 R/W ioextender_com_pio_in10_sel
ad 2b4 R/W ioextender_com_pio_in11_sel
ae 2b8 R/W ioextender_com_pio_in12_sel
af 2bc R/W ioextender_com_pio_in13_sel
b0 2c0 R/W ioextender_com_pio_in14_sel
b1 2c4 R/W ioextender_com_pio_in15_sel
b2 2c8 R/W ioextender_run_n_in_sel
b3 2cc R/W ioextender_rdy_n_in_sel
b4-ff 2d0-3fc -  reserved

ioextender_ioe_o0_sel
Selects the source for ioe_o0
R/W
0x00000000
Address : 0x40030800
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

sel determines the output of the multiplexer as follows:
 0     : not_selected
 4.. 1 : mot_blink_out[3:0]
20.. 5 : mot_pio_out[15:0]
21     : app_mdio_oe
22     : app_mdio_out
23     : app_mdc_out
27..24 : app_blink_out[3:0]
43..28 : app_pio_out[15:0]
44     : xspi_rst_n_out
45     : com_xspi_rst_n_out
46     : com_phy_rst_out_n_out
47     : com_mdio_oe
48     : com_mdio_out
49     : com_mdc_out
53..50 : gxc_phy1_led_out[3:0]
57..54 : gxc_phy0_led_out[3:0]
61..58 : com_blink_out[3:0]
77..62 : com_pio_out[15:0]
78     : run_n_oe
79     : run_n_out
80     : rdy_n_oe
81     : rdy_n_out


ioextender_ioe_o1_sel
Selects the source for ioe_o1
R/W
0x00000000
Address : 0x40030804
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o2_sel
Selects the source for ioe_o2
R/W
0x00000000
Address : 0x40030808
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o3_sel
Selects the source for ioe_o3
R/W
0x00000000
Address : 0x4003080c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o4_sel
Selects the source for ioe_o4
R/W
0x00000000
Address : 0x40030810
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o5_sel
Selects the source for ioe_o5
R/W
0x00000000
Address : 0x40030814
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o6_sel
Selects the source for ioe_o6
R/W
0x00000000
Address : 0x40030818
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o7_sel
Selects the source for ioe_o7
R/W
0x00000000
Address : 0x4003081c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o8_sel
Selects the source for ioe_o8
R/W
0x00000000
Address : 0x40030820
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o9_sel
Selects the source for ioe_o9
R/W
0x00000000
Address : 0x40030824
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o10_sel
Selects the source for ioe_o10
R/W
0x00000000
Address : 0x40030828
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o11_sel
Selects the source for ioe_o11
R/W
0x00000000
Address : 0x4003082c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o12_sel
Selects the source for ioe_o12
R/W
0x00000000
Address : 0x40030830
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o13_sel
Selects the source for ioe_o13
R/W
0x00000000
Address : 0x40030834
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o14_sel
Selects the source for ioe_o14
R/W
0x00000000
Address : 0x40030838
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o15_sel
Selects the source for ioe_o15
R/W
0x00000000
Address : 0x4003083c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o16_sel
Selects the source for ioe_o16
R/W
0x00000000
Address : 0x40030840
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o17_sel
Selects the source for ioe_o17
R/W
0x00000000
Address : 0x40030844
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o18_sel
Selects the source for ioe_o18
R/W
0x00000000
Address : 0x40030848
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o19_sel
Selects the source for ioe_o19
R/W
0x00000000
Address : 0x4003084c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o20_sel
Selects the source for ioe_o20
R/W
0x00000000
Address : 0x40030850
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o21_sel
Selects the source for ioe_o21
R/W
0x00000000
Address : 0x40030854
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o22_sel
Selects the source for ioe_o22
R/W
0x00000000
Address : 0x40030858
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o23_sel
Selects the source for ioe_o23
R/W
0x00000000
Address : 0x4003085c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o24_sel
Selects the source for ioe_o24
R/W
0x00000000
Address : 0x40030860
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o25_sel
Selects the source for ioe_o25
R/W
0x00000000
Address : 0x40030864
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o26_sel
Selects the source for ioe_o26
R/W
0x00000000
Address : 0x40030868
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o27_sel
Selects the source for ioe_o27
R/W
0x00000000
Address : 0x4003086c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o28_sel
Selects the source for ioe_o28
R/W
0x00000000
Address : 0x40030870
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o29_sel
Selects the source for ioe_o29
R/W
0x00000000
Address : 0x40030874
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o30_sel
Selects the source for ioe_o30
R/W
0x00000000
Address : 0x40030878
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o31_sel
Selects the source for ioe_o31
R/W
0x00000000
Address : 0x4003087c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o32_sel
Selects the source for ioe_o32
R/W
0x00000000
Address : 0x40030880
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o33_sel
Selects the source for ioe_o33
R/W
0x00000000
Address : 0x40030884
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o34_sel
Selects the source for ioe_o34
R/W
0x00000000
Address : 0x40030888
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o35_sel
Selects the source for ioe_o35
R/W
0x00000000
Address : 0x4003088c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o36_sel
Selects the source for ioe_o36
R/W
0x00000000
Address : 0x40030890
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o37_sel
Selects the source for ioe_o37
R/W
0x00000000
Address : 0x40030894
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o38_sel
Selects the source for ioe_o38
R/W
0x00000000
Address : 0x40030898
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o39_sel
Selects the source for ioe_o39
R/W
0x00000000
Address : 0x4003089c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o40_sel
Selects the source for ioe_o40
R/W
0x00000000
Address : 0x400308a0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o41_sel
Selects the source for ioe_o41
R/W
0x00000000
Address : 0x400308a4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o42_sel
Selects the source for ioe_o42
R/W
0x00000000
Address : 0x400308a8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o43_sel
Selects the source for ioe_o43
R/W
0x00000000
Address : 0x400308ac
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o44_sel
Selects the source for ioe_o44
R/W
0x00000000
Address : 0x400308b0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o45_sel
Selects the source for ioe_o45
R/W
0x00000000
Address : 0x400308b4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o46_sel
Selects the source for ioe_o46
R/W
0x00000000
Address : 0x400308b8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o47_sel
Selects the source for ioe_o47
R/W
0x00000000
Address : 0x400308bc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o48_sel
Selects the source for ioe_o48
R/W
0x00000000
Address : 0x400308c0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o49_sel
Selects the source for ioe_o49
R/W
0x00000000
Address : 0x400308c4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o50_sel
Selects the source for ioe_o50
R/W
0x00000000
Address : 0x400308c8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o51_sel
Selects the source for ioe_o51
R/W
0x00000000
Address : 0x400308cc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o52_sel
Selects the source for ioe_o52
R/W
0x00000000
Address : 0x400308d0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o53_sel
Selects the source for ioe_o53
R/W
0x00000000
Address : 0x400308d4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o54_sel
Selects the source for ioe_o54
R/W
0x00000000
Address : 0x400308d8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o55_sel
Selects the source for ioe_o55
R/W
0x00000000
Address : 0x400308dc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o56_sel
Selects the source for ioe_o56
R/W
0x00000000
Address : 0x400308e0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o57_sel
Selects the source for ioe_o57
R/W
0x00000000
Address : 0x400308e4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o58_sel
Selects the source for ioe_o58
R/W
0x00000000
Address : 0x400308e8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o59_sel
Selects the source for ioe_o59
R/W
0x00000000
Address : 0x400308ec
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o60_sel
Selects the source for ioe_o60
R/W
0x00000000
Address : 0x400308f0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o61_sel
Selects the source for ioe_o61
R/W
0x00000000
Address : 0x400308f4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o62_sel
Selects the source for ioe_o62
R/W
0x00000000
Address : 0x400308f8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_o63_sel
Selects the source for ioe_o63
R/W
0x00000000
Address : 0x400308fc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_ioe_o0_sel.


ioextender_ioe_mosi_dc_oe_sel
Selects the source for ioe_mosi_dc_oe
R/W
0x0000004e
Address : 0x40030900
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1001110"
sel

same as adr_ioextender_ioe_o0_sel.
Default signal is run_n_oe


ioextender_ioe_mosi_dc_o_sel
Selects the source for ioe_mosi_dc_o
R/W
0x0000004f
Address : 0x40030904
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1001111"
sel

same as adr_ioextender_ioe_o0_sel.
Default signal is run_n_out


ioextender_ioe_sck_dc_oe_sel
Selects the source for ioe_sck_dc_oe
R/W
0x00000050
Address : 0x40030908
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1010000"
sel

same as adr_ioextender_ioe_o0_sel.
Default signal is rdy_n_oe


ioextender_ioe_sck_dc_o_sel
Selects the source for ioe_sck_dc_o
R/W
0x00000051
Address : 0x4003090c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1010001"
sel

same as adr_ioextender_ioe_o0_sel.
Default signal is rdy_n_out


ioextender_app_mdio_in_sel
Selects the source for app_mdio_in
R/W
0x00000000
Address : 0x40030a00
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

sel determines the output of the multiplexer as follows:
 0     : not_selected
 1     : ioe_tgl
65.. 2 : ioe_i[63:0]
66     : ioe_mosi_dc_i
67     : ioe_sck_dc_i


ioextender_com_mdio_in_sel
Selects the source for com_mdio_in
R/W
0x00000000
Address : 0x40030a04
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in0_sel
Selects the source for mot_pio_in0
R/W
0x00000001
Address : 0x40030a08
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000001"
sel

same as adr_ioextender_app_mdio_in_sel.
Default signal is ioe_tgl


ioextender_mot_pio_in1_sel
Selects the source for mot_pio_in1
R/W
0x00000000
Address : 0x40030a0c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in2_sel
Selects the source for mot_pio_in2
R/W
0x00000000
Address : 0x40030a10
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in3_sel
Selects the source for mot_pio_in3
R/W
0x00000000
Address : 0x40030a14
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in4_sel
Selects the source for mot_pio_in4
R/W
0x00000000
Address : 0x40030a18
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in5_sel
Selects the source for mot_pio_in5
R/W
0x00000000
Address : 0x40030a1c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in6_sel
Selects the source for mot_pio_in6
R/W
0x00000000
Address : 0x40030a20
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in7_sel
Selects the source for mot_pio_in7
R/W
0x00000000
Address : 0x40030a24
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in8_sel
Selects the source for mot_pio_in8
R/W
0x00000000
Address : 0x40030a28
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in9_sel
Selects the source for mot_pio_in9
R/W
0x00000000
Address : 0x40030a2c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in10_sel
Selects the source for mot_pio_in10
R/W
0x00000000
Address : 0x40030a30
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in11_sel
Selects the source for mot_pio_in11
R/W
0x00000000
Address : 0x40030a34
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in12_sel
Selects the source for mot_pio_in12
R/W
0x00000000
Address : 0x40030a38
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in13_sel
Selects the source for mot_pio_in13
R/W
0x00000000
Address : 0x40030a3c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in14_sel
Selects the source for mot_pio_in14
R/W
0x00000000
Address : 0x40030a40
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_mot_pio_in15_sel
Selects the source for mot_pio_in15
R/W
0x00000000
Address : 0x40030a44
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in0_sel
Selects the source for app_pio_in0
R/W
0x00000001
Address : 0x40030a48
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000001"
sel

same as adr_ioextender_app_mdio_in_sel.
Default signal is ioe_tgl


ioextender_app_pio_in1_sel
Selects the source for app_pio_in1
R/W
0x00000000
Address : 0x40030a4c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in2_sel
Selects the source for app_pio_in2
R/W
0x00000000
Address : 0x40030a50
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in3_sel
Selects the source for app_pio_in3
R/W
0x00000000
Address : 0x40030a54
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in4_sel
Selects the source for app_pio_in4
R/W
0x00000000
Address : 0x40030a58
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in5_sel
Selects the source for app_pio_in5
R/W
0x00000000
Address : 0x40030a5c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in6_sel
Selects the source for app_pio_in6
R/W
0x00000000
Address : 0x40030a60
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in7_sel
Selects the source for app_pio_in7
R/W
0x00000000
Address : 0x40030a64
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in8_sel
Selects the source for app_pio_in8
R/W
0x00000000
Address : 0x40030a68
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in9_sel
Selects the source for app_pio_in9
R/W
0x00000000
Address : 0x40030a6c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in10_sel
Selects the source for app_pio_in10
R/W
0x00000000
Address : 0x40030a70
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in11_sel
Selects the source for app_pio_in11
R/W
0x00000000
Address : 0x40030a74
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in12_sel
Selects the source for app_pio_in12
R/W
0x00000000
Address : 0x40030a78
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in13_sel
Selects the source for app_pio_in13
R/W
0x00000000
Address : 0x40030a7c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in14_sel
Selects the source for app_pio_in14
R/W
0x00000000
Address : 0x40030a80
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_app_pio_in15_sel
Selects the source for app_pio_in15
R/W
0x00000000
Address : 0x40030a84
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in0_sel
Selects the source for com_pio_in0
R/W
0x00000001
Address : 0x40030a88
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000001"
sel

same as adr_ioextender_app_mdio_in_sel.
Default signal is ioe_tgl


ioextender_com_pio_in1_sel
Selects the source for com_pio_in1
R/W
0x00000000
Address : 0x40030a8c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in2_sel
Selects the source for com_pio_in2
R/W
0x00000000
Address : 0x40030a90
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in3_sel
Selects the source for com_pio_in3
R/W
0x00000000
Address : 0x40030a94
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in4_sel
Selects the source for com_pio_in4
R/W
0x00000000
Address : 0x40030a98
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in5_sel
Selects the source for com_pio_in5
R/W
0x00000000
Address : 0x40030a9c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in6_sel
Selects the source for com_pio_in6
R/W
0x00000000
Address : 0x40030aa0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in7_sel
Selects the source for com_pio_in7
R/W
0x00000000
Address : 0x40030aa4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in8_sel
Selects the source for com_pio_in8
R/W
0x00000000
Address : 0x40030aa8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in9_sel
Selects the source for com_pio_in9
R/W
0x00000000
Address : 0x40030aac
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in10_sel
Selects the source for com_pio_in10
R/W
0x00000000
Address : 0x40030ab0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in11_sel
Selects the source for com_pio_in11
R/W
0x00000000
Address : 0x40030ab4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in12_sel
Selects the source for com_pio_in12
R/W
0x00000000
Address : 0x40030ab8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in13_sel
Selects the source for com_pio_in13
R/W
0x00000000
Address : 0x40030abc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in14_sel
Selects the source for com_pio_in14
R/W
0x00000000
Address : 0x40030ac0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_com_pio_in15_sel
Selects the source for com_pio_in15
R/W
0x00000000
Address : 0x40030ac4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "0000000"
sel

same as adr_ioextender_app_mdio_in_sel.


ioextender_run_n_in_sel
Selects the source for run_n_in
R/W
0x00000042
Address : 0x40030ac8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1000010"
sel

same as adr_ioextender_app_mdio_in_sel.
Default signal is ioe_mosi_dc_i


ioextender_rdy_n_in_sel
Selects the source for rdy_n_in
R/W
0x00000043
Address : 0x40030acc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
inv
1: invert multiplexer output
6 - 0 "1000011"
sel

same as adr_ioextender_app_mdio_in_sel.
Default signal is ioe_sck_dc_i



Base Address Area: global_ioextender

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W ioextender_cfg_sck0
1 4 R/W ioextender_cfg_sck1
2 8 R/W ioextender_cfg_sck2
3 c R/W ioextender_cfg_sck3
4 10 R/W ioextender_cfg_p0_len
5 14 R/W ioextender_cfg_p8_len
6 18 R/W ioextender_cfg_frame
7 1c R/W ioextender_cfg_ioe_io_dir
8 20 R/W ioextender_cmd
9 24 R ioextender_state
a 28 R/W ioextender_dc_i_tgl
b 2c R/W ioextender_i0
c 30 R/W ioextender_i1
d 34 R ioextender_dc_o
e 38 R ioextender_o0
f 3c R ioextender_o1
10 40 R ioextender_pad_in
11 44 R/W ioextender_pad_out
12-3f 48-fc -  reserved

ioextender_cfg_sck0
All CFG_* registers may only be changed when CMD.en=0.
R/W
0x00040004
Address : 0x40030c00
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 16 0x4
miso_sample
0..(2*half_period-1): value of sck_phase_dly (i.e. one clock cycle after sck_phase) when the sampled MISO input is sampled. For external shift registers shifting on the rising edge the optimum value is half_period (i.e. the clock cycle before the rising edge is applied).
See bit timing diagram for details.
15 - 12 0
-
 reserved
11 - 0 0x4
half_period
1..MAX length of a SCK half period in clock cycles
sck_phase will run from (2*half_period-1) to 0.


ioextender_cfg_sck1
R/W
0x00050005
Address : 0x40030c04
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 16 0x5
miso_sample

15 - 12 0
-
 reserved
11 - 0 0x5
half_period



ioextender_cfg_sck2
R/W
0x00060006
Address : 0x40030c08
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 16 0x6
miso_sample

15 - 12 0
-
 reserved
11 - 0 0x6
half_period



ioextender_cfg_sck3
R/W
0x00070007
Address : 0x40030c0c
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 16 0x7
miso_sample

15 - 12 0
-
 reserved
11 - 0 0x7
half_period



ioextender_cfg_p0_len
R/W
0x00000000
Address : 0x40030c10
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 0 0x0
val
0: phase 0 is disabled
1..MAX length of P0 in clk cycles


ioextender_cfg_p8_len
R/W
0x00005adf
Address : 0x40030c14
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 0 0x5adf
val
0: phase 8 is disabled
1..MAX length of phase 8 in SCK cycles
(0x5ADF = 23263 <=> 0.3% = (64+6) / (64+6+23263)


ioextender_cfg_frame
R/W
0x0103c1bf
Address : 0x40030c18
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 - 18 "1000000"
n_len
1..64: number of bits transferred during phase p4
17 "1"
sck_middle
value of SCK in the middle of the SCK period during phase p4
16 - 9 "11100000"
sck_start
value of SCK at the beginning of the SCK period for p0..p7 (value for p0 is not used, value for p8 is determined by dc_o_sck)
(0xE0 = "11100000")
8 - 0 0x1bf
s
value of STRB for phase p0..p8:
STRB = s[STATE.phase]
(0xBF = "10111111")


ioextender_cfg_ioe_io_dir
Selects if the shift register or the IOE_IO pads are used for IO.
R/W
0x00000000
Address : 0x40030c1c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
Controls the direction of the IOE_IO pads.
val[N]=0 <=> corresponding bit of the O register is output simultaneously on on IOE_IO[N] and the shift register. IOE_IO[N] is configured as output (oe=1).
val[N]=1: corresponding bit of the I register is fed by IOE_IO[N], while the corresponding value of the shift register is ignored. IOE_IO[N] is configured as input (oe=0).
Note: To use a IOE_IO pad the main multiplexer must also be configured.


ioextender_cmd
R/W
0x00000000
Address : 0x40030c20
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
en
0: ioe disabled
external pins controlled by PAD_O register.
STATE set to default (reset) values.
1: ioe frame generation running. Frame generation controls external pins.


ioextender_state
R
Address : 0x40030c24
Bits Name Description
31 - 12 -
 reserved
11 - 10 hp
N= 0..3 currently using CFG_SCK_HP
9 - 4 n
0..(CFG_FRAME.n_len-1): number of bit currently transmitted (value is valid only during p4)
3 - 0 phase
0:idle
1..9:p0..p8


ioextender_dc_i_tgl
The bits in this register can also be set by SW, but are overwritten by the frame generator at the end of p6 when CMD.en=1.
R/W
0x00000000
Address : 0x40030c28
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ioe_tgl
value of ioe_tgl signal send to external subsystem. This bit is inverted by the frame generator at the end of p6. At the same clock cycle the I* outputs of the ioe module are updated.
When the DC_I_TGL (and I*) registers are updated by SW, it is the responsibility of the SW to toggle DC_I_TGL.ioe.tgl to signal the update.
1 "0"
mosi
same as sck field for mosi_dc_i / MOSI pin.
0 "0"
sck
sck_dc_i signal to subsystem INPUT / sampled from SCK pin at the end of phase p0 (if p0 is enabled).


ioextender_i0
The bits in this register can also be set by SW, but are overwritten by the frame generator at the end of p6 when CMD.en=1.
R/W
0x00000000
Address : 0x40030c2c
Bits Reset value Name Description
31 - 0 0x0
val
incoming values from shift registers or ioe_io pins (depending on CFG_IOE_IO_DIR) sent to ioe_i outputs.


ioextender_i1
The bits in this register can also be set by SW, but are overwritten by the frame generator at the end of p6 when CMD.en=1.
R/W
0x00000000
Address : 0x40030c30
Bits Reset value Name Description
31 - 0 0x0
val
incoming values from shift registers or ioe_io pins (depending on CFG_IOE_IO_DIR) sent to ioe_i outputs.


ioextender_dc_o
R
Address : 0x40030c34
Bits Name Description
31 - 4 -
 reserved
3 mosi_oe
value of miso_dc_oe module input signal.
Ignored for p8.
Applied to MOSI pin when CMD.en=0 and PAD_OUT.sel_sck_mosi=0.
2 sck_oe
value of sck_dc_oe module input signal.
Ignored for p8.
Applied to SCK pin when CMD.en=0 and PAD_OUT.sel_sck_mosi=0.
1 mosi
value of mosi_dc_o module input signal.
Applied to MOSI pin during p8.
0 sck
value of sck_dc_o module input signal.
Applied to SCK pin during p8.


ioextender_o0
R
Address : 0x40030c38
Bits Name Description
31 - 0 val
values to be output by shift registers and IOE_IO pins.
Sampled at the end of p3.


ioextender_o1
R
Address : 0x40030c3c
Bits Name Description
31 - 0 val
values to be output by shift registers and IOE_IO pins.
Sampled at the end of p3.


ioextender_pad_in
Current value output to the pad cell. Always valid.
R
Address : 0x40030c40
Bits Name Description
31 - 4 -
 reserved
3 miso

2 mosi

1 sck

0 strb



ioextender_pad_out
Manual control register of pad cells. Values applied to pad cells when CMD.en=0.
R/W
0x00000000
Address : 0x40030c44
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
sel_sck_mosi
when CMD.en=0: SCK and MISO pads are controlled by
0: module inputs: ioe_sck/oe & mosi_dc_o/oe
1: this register: PAD_OUT.sck/miso/_oe
7 "0"
miso_oe

6 "0"
mosi_oe

5 "0"
sck_oe

4 "0"
strb_oe

3 "0"
miso

2 "0"
mosi

1 "0"
sck

0 "0"
strb




Base Address Area: crg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W crg_clock_enable
1 4 R crg_clock_status
2-3 8-c -  reserved
4 10 R crg_reset_status
5 14 R/W crg_reset_ctrl_pcie
6-7 18-1c -  reserved
8 20 R/W crg_clk500_div
9 24 R/W crg_clk166_dpm_div
a 28 R/W crg_sse_syspll_div
b 2c R/W crg_sse_cpupll_div
c 30 R/W crg_clk200_div
d 34 R/W crg_clk100_div
e 38 R/W crg_clk80_div
f 3c R/W crg_clk250_div
10 40 R/W crg_clk200_sdio_div
11 44 R/W crg_clk200_gem_gxl_div
12-17 48-5c -  reserved
18 60 R/W crg_tpiu
19-1f 64-7c -  reserved
20 80 R/W crg_sys_pll_cfg
21 84 R crg_all_pll_status
22 88 R/W crg_ext_bypass_set
23 8c R/W crg_ext_bypass_clr
24 90 R crg_irq_status
25 94 R/W crg_irq_clr
26-3f 98-fc -  reserved

crg_clock_enable
Clock enable register
IMPORTANT: Do not enable all clocks at once, do it step by step. Otherwise high inrush currents
could cause unstable behaviour and the system might crash.
R/W
0x00000000
Address : 0x40030d00
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
run_clk400_pcie
run_clk400_pcie (AXI clock of PCIE area)
14 "0"
run_clk200_gem_gxl
run_clk200_gem_gxl
13 "0"
run_clk200_sdio
run_clk200_sdio
12 "0"
run_clk250_iol
run_clk250_iol
11 "0"
run_clk80_canfd_app
run_clk80_canfd_app
10 "0"
run_clk80_canfd_com
run_clk80_canfd_com
9 "0"
run_clk100_mot
run_clk100_mot
8 "0"
run_clk200_mot
run_clk200_mot
7 "0"
run_clk166_dpm
run_clk166_dpm
6 "0"
run_clk500_app_hsgmii
run_clk500_app_hsgmii
5 "0"
run_clk500_com_hsgmii1
run_clk500_com_hsgmii1
4 "0"
run_clk500_com_hsgmii0
run_clk500_com_hsgmii0
3 "0"
run_clk500_ada
run_clk500_ada
2 "0"
run_clk500_cada_rx
run_clk500_cada_rx
1 "0"
run_clk500_cada_tx
run_clk500_cada_tx
0 "0"
run_clk500_gxc
run_clk500_gxc


crg_clock_status
Clock status register
Status for license masked clock enable signals
The bits represent the status of the clock_enable_run signals after being masked by the corresponding SCB license bits.
TBD: PCIe lic clock enable masking
R
Address : 0x40030d04
Bits Name Description
31 - 15 -
 reserved
14 run_clk200_gem_gxl
run_clk200_gem_gxl status
13 run_clk200_sdio
run_clk200_sdio status
12 -
 reserved
11 run_clk80_canfd_app
run_clk80_canfd_app status
10 - 0 -
 reserved


crg_reset_status
Reset status register
Change note: This register has no function in netx22xx_mpw and will be removed.
R
Address : 0x40030d10
Bits Name Description
31 - 3 -
 reserved
2 wdg1_tbd
Reset was initiated by WDG1
1 rst_in_n
Reset was initiated by RST_IN_N input
0 por
Reset was initiated by POR_N input


crg_reset_ctrl_pcie
Reset control register for PCIe
The PCIe area can be excluded from certain resets e.g. to keep the PCIe connection to a host alive
while a firmware reset is done on the netX.
By default all resets masks of this register allow to reset PCIe. To exclude certain resets
program the allow bit to 0.
This register is only reset by an external power-on-reset (recieved by input POR_N low)
Note: The reset from the POR_N input will always reset the PCIe IP.
R/W
0x0000001f
Address : 0x40030d14
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "1"
allow_pcie_warm_nres_req
allow reset request from PCIe to reset PCIe
3 "1"
allow_systop_warmresetn
allow SSE systop_warmresetn to reset PCIe
2 "1"
allow_aontop_warmresetn
allow SSE aontop_warmresetn to reset PCIe
1 "1"
allow_aontop_poresetn
allow SSE aontop_poresetn to reset PCIe
0 "1"
allow_rst_in_n
allow input rst_in_n to reset PCIe


crg_clk500_div
CRG divider setting for 500MHz COM clock domains (for divider crg_main_clock_div_clk500com)
and the Host-interface (HIF/DPM) clock.
Note: The Host-interface (HIF/DPM) clock has a 2nd stage divider from the clk500. See register clk166_dpm_div.
R/W
0x00000003
Address : 0x40030d20
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 - 0 "011"
div_val
Divides the PLL output by (div_val+1) to generate the clk500 domains
By default the PLL runs with 2GHz. Hence the default value 3 will generate
2GHz DIV 4 == 500MHz on the clk500 domains (COM system: CA32-COM, GXC_SYS, CADAs, ADA).
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 500MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk166_dpm_div
CRG divider setting for 166/100MHz the Host-interface (HIF/DPM) clock (for divider hsoc_clock_div_ahbl_cdc_imsc_idpm_sys).
Note: The divider related to this configuration register is a 2nd stage divider. The first stage is programmed by
      the clk500_div register
Important: No AHB access must run between the clk166 and clk500 when you change the value of this register. Otherwise
           the system may crash completely. It is strongly recommendet to disable the clk166_dpm by the bit clock_enable_run_clk166_dpm
           before the value of this register is changed.
R/W
0x00000002
Address : 0x40030d24
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 - 0 "010"
div_val
Divides the crg_main_clock_div_clk500com output by (div_val+1) to generate the clk166_dpm domain
for the HIF/DPM modules.
By default the crg_main_clock_div_clk500com generates 500MHz. Hence the default value 2 will generate
500MHz DIV 3 == 166MHz on the clk166_dpm domain..
This divider does only work with odd division. Hence only even values must be programmed. odd values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
Recommended values are for a 500MHz clk500:
  2        166MHz clk166_dpm (default)
  4        100MHz clk166_dpm (reduced performance but less critical IO timing)
  others   reserved/not recommended
It is forbidden to program values that lead to frequencies above 166MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_sse_syspll_div
CRG divider setting for the SYSPLL domain of the SSE (for divider crg_main_clock_div_sse_syspll).
Note: Further clocks are derived from the SYSPLL clock of the SSE inside the SSE.
      Please see for details in the SSE documentation.
R/W
0x00000004
Address : 0x40030d28
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0100"
div_val
Divides the PLL output by (div_val+1) to generate the SYSPLL domain of the SSE
By default the PLL runs with 2GHz. Hence the default value 4 will generate
2GHz DIV 5 == 400MHz on the SYSPLL domain of the SSE.
This divider does only work with odd division. Hence only even values must be programmed. odd values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
To save dynamic power a slower frequency could be programmed here. However this will
lead to reduced performance.
It is forbidden to program values that lead to frequencies above 400MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_sse_cpupll_div
CRG divider setting for the CPUPLL domain of the SSE (for divider crg_main_clock_div_sse_cpupll).
Note: Further clocks are derived from the CPUPLL clock of the SSE inside the SSE.
      Please see for details in the SSE documentation.
R/W
0x00000003
Address : 0x40030d2c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0011"
div_val
Divides the PLL output by (div_val+1) to generate the CPUPLL domain of the SSE
By default the PLL runs with 2GHz. Hence the default value 3 will generate
2GHz DIV 4 == 500MHz on the CPUPLL domain of the SSE.
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
To save dynamic power a slower frequency could be programmed here. However this will
lead to reduced performance.
It is forbidden to program values that lead to frequencies above 500MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.
Note: You can switch the CA32 APP to the syspll clock in the SSE configuration registers. This
      allows the CA32 APP running on even divided frequencies of 2GHz (for the PLL default).


crg_clk200_div
CRG divider setting for 200MHz clock domains (for divider crg_main_clock_div_200aon_rcg) and
for the 100MHz peripheral clock domains.
Note: The peripheral clocks have a 2nd stage clock divider. See register clk100_div.
R/W
0x00000009
Address : 0x40030d30
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001001"
div_val
Divides the PLL output by (div_val+1) to generate the clk200 domains
By default the PLL runs with 2GHz. Hence the default value 9 will generate
2GHz DIV 10 == 200MHz on the clk200 domains (MOT system).
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 200MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk100_div
CRG divider setting for for the 100MHz peripheral clock domains (for divider hsoc_clock_div_ahbl_cdc_imsc_clk100).
Note: The divider related to this configuration register is a 2nd stage divider. The first stage is programmed by
      the clk200_div register
R/W
0x00000001
Address : 0x40030d34
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "01"
div_val
Divides the crg_main_clock_div_200aon_rcg output by (div_val+1) to generate the clk100 domains
for the peripheral modules.
By default the crg_main_clock_div_200aon_rcg generates 200MHz. Hence the default value 1 will generate
200MHz DIV 2 == 100MHz on the clk100 domains (IO peripherals which do not have own clock dividers).
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting in a way that generates another clock than 100MHz.
It is forbidden to program values that lead to frequencies above 100MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk80_div
CRG divider setting for 80MHz CANFD clock domains (for divider crg_main_clock_div_80aon_rcg)..
R/W
0x00000018
Address : 0x40030d38
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "011000"
div_val
Divides the PLL output by (div_val+1) to generate the clk80 CANFD domains
By default the PLL runs with 2GHz. Hence the default value 24 will generate
2GHz DIV 25 == 80MHz on the clk80 domains (CANFD modules).
This divider does only work with odd division. Hence only even values must be programmed. odd values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 80MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk250_div
CRG divider setting for 250MHz IOL clock domains (for divider crg_main_clock_div_250_rcg)..
R/W
0x00000007
Address : 0x40030d3c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0111"
div_val
Divides the PLL output by (div_val+1) to generate the clk250 IOL domains
By default the PLL runs with 2GHz. Hence the default value 24 will generate
2GHz DIV 8 == 250MHz on the clk250 domains (IOL modules).
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 250MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk200_sdio_div
CRG divider setting for 200MHz SDIO clock domains (for divider crg_main_clock_div_200_sdio_rcg)..
R/W
0x00000009
Address : 0x40030d40
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "01001"
div_val
Divides the PLL output by (div_val+1) to generate the clk200 SDIO domains (SDIO phy_clk)
By default the PLL runs with 2GHz. Hence the default value 9 will generate
2GHz DIV 10 == 200MHz on the clk200_sdio domains (SDIO modules).
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 200MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_clk200_gem_gxl_div
CRG divider setting for 200MHz GEM_GXL (GMAC) clock domains (for divider crg_main_clock_div_200_gem_gxl_rcg)..
R/W
0x00000009
Address : 0x40030d44
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "01001"
div_val
Divides the PLL output by (div_val+1) to generate the clk200_gem_gxl domains (system busses)
By default the PLL runs with 2GHz. Hence the default value 9 will generate
2GHz DIV 10 == 200MHz on the clk200_gem_gxl domains.
This divider does only work with even division. Hence only odd values must be programmed. even values are
reserved and could lead to unpredictable behaviour (0 for bypass is OK but reserved for PLL bypass mode).
It is not recommended to change this setting.
It is forbidden to program values that lead to frequencies above 200MHz. The system
will show unpredictable behaviour and could even get damaged if you do so.


crg_tpiu
CRG trace clock divider setting  TBD: is the CRG cfg reg area the right location for the traceclk divider?
Note:
  The trace clock is derived from the SSE debug clock which runs at 200MHz by default (SYS PLL div 4) but which
  could be programmed to other frequencies. The frequencies shown below refer to a 200MHz debug clock and must be
  re-calculated if the debug clock frequency is changed to a value unequal 200MHz.
Note: The divider was changed from NETXXL MPW:
  MPW: bypass or 2^N div (1, 2, 4, 8, 16), default 200MHz (in the MPW description 400MHz is documented but that refers to
a 400MHz debug clock, which is not the default. Also for the MPW the debug clock default is 200MHz.
  netx22xx: bypass or DIV (2*N) (1, 2, 4, 6.. 30), default: 0 (200MHz). Programming even values (2, 4, 6, ..30) is forbidden.
Note: There is an additional DIV2 for the external DBG_TRACE_CLK signal in the SSE. So the clock rate at the
      DBG_TRACE_CLK output will be half of the frequency programmed in this register.
R/W
0x00000000
Address : 0x40030d60
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
traceclk_div
Trace Port Interface Unit (TPIU) Clock divider (DIV traceclk_div+1) divider.
The clock rate at the DBG_TRACE_CLK output will be half of this (see note above).
0  : no division - 200MHz (for 200MHz SSE debug clock, default)
1  : divide by 2 - 100MHz
2  : reserved
3  : divide by 4 - 50MHz
4  : reserved
5  : divide by 6 - 33.33MHz
6  : reserved
:
15 : divide by 16 - 12.5MHz
:
31 : divide by 32 - 6.25MHz


crg_sys_pll_cfg
CRG SYS_PLL divider values: Default is 2GHz for a 25MHz crystal on FOUTVCO
Note: The FOUTVCO of the PLL which bypasses the post-dividers is used. Due to this the
post dividers cannot be configured.
Note: The PLL must be in power-down mode (pd=1) when the PLL divider settings are changed.
Note: The PLL must not be driven to more than 2GHz in functional mode as the implementation
is limited to that.
R/W
0x00005001
Address : 0x40030d80
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
pd
Global power down
23 - 20 0
-
 reserved
19 - 8 0x50
fbdiv
Feedback Divide Value
7 - 6 0
-
 reserved
5 - 0 "000001"
refdiv
Reference Clock Divide Value (1-63)


crg_all_pll_status
Shows the lock and ext_bypass (former overrule) indicators of all implemented PLLs in a single register.
R
Address : 0x40030d84
Bits Name Description
31 - 9 -
 reserved
8 sys_pll_ext_bypass_stat
PLL output has been bypassed due to an lock loss event or on request
7 - 1 -
 reserved
0 sys_pll_lock_stat
SYS PLL locked


crg_ext_bypass_set
CRG PLL ext_bypass set - force clocks being fed from REFCLK (again) as the PLL lock was lost.
Enabling the ext_bypass here will also assert the unlock IRQ to test this.
The hardware will automatically reset all bits in this register.
R/W
0x00000000
Address : 0x40030d88
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
sys_pll
SYS PLL ext_bypass set


crg_ext_bypass_clr
CRG PLL ext_bypass clear - ext_bypass is set by HW when PLL lost its lock
or if set by the 'ext_bypass_set' register. In this case the PLLs are
bypassed with REFCLK.
The hardware will automatically reset all bits in this register.
R/W
0x00000000
Address : 0x40030d8c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
sys_pll
SYS PLL  ext_bypass clear


crg_irq_status
CRG lock-loss PLL IRQ status. If a PLL lost its lock the ext_bypass is acivated by hardware.
The system will still run but the the slower REFCLK is used instead of the clocks generated by the PLL.
R
Address : 0x40030d90
Bits Name Description
31 - 1 -
 reserved
0 sys_pll_lock_loss
Status of the SYS PLL lock-loss IRQ


crg_irq_clr
CRG lock-loss PLL IRQ clear
The hardware will automatically reset all bits in this register.
R/W
0x00000000
Address : 0x40030d94
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
sys_pll_lock_loss
Clear the SYS PLL lock-loss IRQ



Base Address Area: com_asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W com_asic_ctrl_only_por
1 4 R com_asic_ctrl_rstsyn
2-3 8-c -  reserved
4 10 R/W com_asic_ctrl_netx_status
5 14 R/W com_asic_ctrl_rdy_run_cfg
6 18 R/W com_asic_ctrl_rst_out_cfg
7-3f 1c-fc -  reserved

com_asic_ctrl_only_por
Firmware Status register:
This register is not Reset by SW resets, only PORn will reset this register.
R/W
0x00000000
Address : 0x40040000
Bits Reset value Name Description
31 - 0 0x0
data
netX Firmware status


com_asic_ctrl_rstsyn
COM Reset Syndrome Status register
R
Address : 0x40040004
Bits Name Description
31 - 5 -
 reserved
4 ext
Indicates the last reset of the COM system was caused by a request to reset this system.
3 host
Indicates the last reset of the COM system was caused by an APP system reset request.
2 res
Unused by current SSE710 release. Always read back 0.
1 nsrst
Indicates that the last reset of the COM system was caused by either:
- nSRST pin being asserted.
- DP ROM CSYSRSTREQ being asserted.
0 por
Indicates that the last reset of the COM system was caused by one of the following:
- POR_N pin being asserted.
- DP CDBGRSTREQ being asserted.
- SoC Watchdog reset request.
- Secure Enclave Watchdog reset request.
- SOC_RST_CTRL.RST_REQ bit set to 1.
- Secure Enclave software reset request.


com_asic_ctrl_netx_status
(adr_netx_status)
netX Legacy System Status Configuration Register.
This Register was implemented in Hilscher HIF module originally.
From Hilscher Program Reference Guide: The general status of a netX based system is usually indicated by the System LED, which can either
consist of a dual LED or two single LEDs.

Access to this register is not protected by any locking or access protection algorithm.

IMPORTANT: netX50/100/500 Change Note:
   The netX50/100/500 SYS_STA register was byte accessible. This changed: This register is only 32bit accessible.
   In netx50/100/500, write access to bits 0..15 of SYS_STA register can generate an IRQ to external host CPU.
   As the register now is 32bit accessible only, this is changed to whole register access. I.e. any write
   access to this register will generate an host IRQ if enabled. To change the upper 16 bits of this register without
   host IRQ generation, use register rdy_run_cfg.

Note:
   Changing bits here will also change rdy_run_cfg register bits.

Note:
   Bits 0..3 and 8..15 are read-only-mirrored to DPM/Host Status register dpm_sys_sta (DPM_HOST_SYS_STAT) (Area DPM).
   Read-only bits 4..7 can be programmed by DPM/Host Status register dpm_sys_sta (DPM_HOST_SYS_STAT) (Area DPM).
R/W
0x00030000
Address : 0x40040010
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
RUN_DRV
Driver enable for RUN LED. Enables output driver when set.
24 "0"
RDY_DRV
Driver enable for RDY LED. Enables output driver when set.
23 - 20 0
-
 reserved
19 "0"
RUN_POL
Output polarity RUN LED; outsig = RUN exor RUN_POL.
18 "0"
RDY_POL
Output polarity RDY LED; outsig = RDY exor RDY_POL.
17 "1"
RUN_IN
Physical input signal level at RUN pin (read-only).
16 "1"
RDY_IN
Physical input signal level at RDY pin (read-only).
15 - 2 0
-
 reserved
1 "0"
RUN
Signal Level of the RUN LED output.
Note:
   This bit is read-only-mirrored to DPM/Host Status register
   dpm_sys_sta (DPM_HOST_SYS_STAT) (Area DPM). Changing this bit can produce
   a IRQ to host CPU.
0 "0"
RDY
Signal level of the RDY LED output.
Note:
   This bit is read-only-mirrored to DPM/Host Status register
   dpm_sys_sta (DPM_HOST_SYS_STAT) (Area DPM). Changing this bit can produce
   a IRQ to host CPU.


com_asic_ctrl_rdy_run_cfg
(adr_rdy_run_cfg)
netX Legacy RDY/RUN IO System Status Configuration Register.
RDY/RUN signal programming was implemented in Hilscher HIF module originally.
From Hilscher Program Reference Guide: The general status of a netX based system is usually indicated by the System LED, which can either
consist of a dual LED or two single LEDs.

Access to this register is not protected by any locking or access protection algorithm.

Note:
   Use this register to change the upper 16 bits of sys_sta (SYS_STA) register witout
   host IRQ generation. For further information see sys_sta register description. Changing bits here
   will also change sys_sta register bits, however no host IRQ will be generated.
R/W
0x00030000
Address : 0x40040014
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
RUN_DRV
Driver enable for RUN LED. Enables output driver when set.
24 "0"
RDY_DRV
Driver enable for RDY LED. Enables output driver when set.
23 - 20 0
-
 reserved
19 "0"
RUN_POL
Output polarity RUN LED; outsig = RUN exor RUN_POL.
18 "0"
RDY_POL
Output polarity RDY LED; outsig = RDY exor RDY_POL.
17 "1"
RUN_IN
Physical input signal level at RUN pin (read-only).
16 "1"
RDY_IN
Physical input signal level at RDY pin (read-only).
15 - 2 0
-
 reserved
1 "0"
RUN
Signal Level of the RUN LED output.
0 "0"
RDY
Signal level of the RDY LED output.


com_asic_ctrl_rst_out_cfg
COM Reset Control Register
R/W
0x00000000
Address : 0x40040018
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 -
com_phy_rst_out_n_in_ro
Status of reset pin (com_phy_rst_out_n). This bit is a read only status and indicates the reset state.
26 "0"
EN_RES_REQ_com_phy_rst_out_n
This bit enables the driving of the programmable reset output com_phy_rst_out_n.
When this bit is not set com_phy_rst_out_n will be in high impedance state.
For all resets this bit is cleared. The external level of the com_phy_rst_out_n output during the reset
must be realized by an external pull up or down resistor (when com_phy_rst_out_n function is desired).
25 "0"
RES_REQ_com_phy_rst_out_n
Software reset for external devices: This bit controls the level of the com_phy_rst_out_n output
for normal operation. For all resets this bit is cleared, however driving of com_phy_rst_out_n
is also disabled (view EN_RES_REQ_com_phy_rst_out_n bit).
24 - 0 0
-
 reserved



Base Address Area: com_mmio_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W com_mmio0_cfg
1 4 R/W com_mmio1_cfg
2 8 R/W com_mmio2_cfg
3 c R/W com_mmio3_cfg
4 10 R/W com_mmio4_cfg
5 14 R/W com_mmio5_cfg
6 18 R/W com_mmio6_cfg
7 1c R/W com_mmio7_cfg
8 20 R/W com_mmio_pio_out_line_cfg0
9 24 R/W com_mmio_pio_out_line_set_cfg0
a 28 R/W com_mmio_pio_out_line_reset_cfg0
b 2c R/W com_mmio_pio_oe_line_cfg0
c 30 R/W com_mmio_pio_oe_line_set_cfg0
d 34 R/W com_mmio_pio_oe_line_reset_cfg0
e 38 R com_mmio_in_line_status0
f 3c R com_mmio_is_pio_status0

com_mmio0_cfg
Multiplexmatrix Configuration Register for COM_MMIO0
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040100
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO0, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO0, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO0, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO0 signal selection (default: PIO mode, access-key-protected).
value  netX internal function (core connection)  signal type  functional group
0x00  PIO mode  use line registers  PIO function
0x01  com_spi0_clk  bidirectional  SPI of COM
0x02  com_spi0_miso  bidirectional  SPI of COM
0x03  com_spi0_mosi  bidirectional  SPI of COM
0x04  com_spi0_cs0n  bidirectional  SPI of COM
0x05  com_spi1_clk  bidirectional  SPI of COM
0x06  com_spi1_miso  bidirectional  SPI of COM
0x07  com_spi1_mosi  bidirectional  SPI of COM
0x08  com_spi1_cs0n  bidirectional  SPI of COM
0x09  com_i2c0_scl  bidirectional  I2C of COM
0x0a  com_i2c0_sda  bidirectional  I2C of COM
0x0b  com_i2c1_scl  bidirectional  I2C of COM
0x0c  com_i2c1_sda  bidirectional  I2C of COM
0x0d  com_uart0_tx  tristatable output  UART of COM
0x0e  com_uart0_rx  input  UART of COM
0x0f  com_uart0_rtsn  tristatable output  UART of COM
0x10  com_uart0_ctsn  input  UART of COM
0x11  com_uart1_tx  tristatable output  UART of COM
0x12  com_uart1_rx  input  UART of COM
0x13  com_uart1_rtsn  tristatable output  UART of COM
0x14  com_uart1_ctsn  input  UART of COM
0x15  com_iol_clkref  always driven output  IOL clock reference
0x16  com_iol_spi_cs1n  bidirectional  IOL SPI interface
0x17  com_iol_spi_cs2n  bidirectional  IOL SPI interface
0x18  com_mii0_txer  tristatable output  MII additional signals
0x19  com_mii1_txer  tristatable output  MII additional signals
0x1a  com_gpio0  bidirectional  GPIO
0x1b  com_gpio1  bidirectional  GPIO
0x1c  com_gpio2  bidirectional  GPIO
0x1d  com_gpio3  bidirectional  GPIO
0x1e  com_gxc_sample_global0  input  Trigger/Latch global
0x1f  com_gxc_sample_global1  input  Trigger/Latch global
0x20  com_gxc_trigger_global0  tristatable output  Trigger/Latch global
0x21  com_gxc_trigger_global1  tristatable output  Trigger/Latch global
0x22  com_wdg_active  always driven output  Watchdog of COM active signal
..  reserved    


com_mmio1_cfg
Multiplexmatrix Configuration Register for COM_MMIO1
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040104
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO1, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO1, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO1, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO1 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio2_cfg
Multiplexmatrix Configuration Register for COM_MMIO2
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040108
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO2, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO2, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO2, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO2 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio3_cfg
Multiplexmatrix Configuration Register for COM_MMIO3
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x4004010c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO3, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO3, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO3, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO3 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio4_cfg
Multiplexmatrix Configuration Register for COM_MMIO4
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040110
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO4, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO4, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO4, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO4 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio5_cfg
Multiplexmatrix Configuration Register for COM_MMIO5
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040114
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO5, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO5, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO5, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO5 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio6_cfg
Multiplexmatrix Configuration Register for COM_MMIO6
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x40040118
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO6, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO6, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO6, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO6 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio7_cfg
Multiplexmatrix Configuration Register for COM_MMIO7
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any COM_MMIO will be assigned to 0.
If one core-connection is mapped to more than one COM_MMIO, the core-input-state will be these ored COM_MMIO-states.
R/W
0x00000000
Address : 0x4004011c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of COM_MMIO7, could also be read from 'com_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of COM_MMIO7, could also be programmd by 'com_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of COM_MMIO7, could also be programmd by com_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'com_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
com_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
com_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
com_mmio_sel
COM_MMIO7 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_com_mmio0_cfg


com_mmio_pio_out_line_cfg0
COM_MMIO PIO line output level register of COM_MMIO0 to COM_MMIO7.
Changing bits here will change 'pio_out' bit of related com_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40040120
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Output state if related COM_MMIO is in PIO mode.
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.


com_mmio_pio_out_line_set_cfg0
COM_MMIO PIO line output level set register of COM_MMIO0 to COM_MMIO7.
This register is for setting single COM_MMIO PIOs to high level with a single access. In contrast to using the 'com_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'com_mmio*_cfg' register and also activate
the related bits in the 'com_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'com_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40040124
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Write '1's to set the related COM_MMIO output to high level (when it is in PIO mode and output is enabled).
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.
For read the current value of the programmed output states is returned (i.e. the value of com_mmio_pio_out_line_cfg0).


com_mmio_pio_out_line_reset_cfg0
COM_MMIO PIO line output level reset register of COM_MMIO0 to COM_MMIO7.
This register is for deactivating single COM_MMIO PIOs with a single access. In contrast to using the 'com_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'com_mmio*_cfg' register and also clear
the related bits in the 'com_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'com_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40040128
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Write '1's to set the related COM_MMIO output to low level (when it is in PIO mode and output is enabled).
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.
For read the current value of the programmed output states is returned (i.e. the value of com_mmio_pio_out_line_cfg0).


com_mmio_pio_oe_line_cfg0
COM_MMIO PIO line output enable register of COM_MMIO0 to COM_MMIO7.
Changing bits here will change 'pio_oe' bit of related com_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4004012c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Output enable if related COM_MMIO is in PIO mode.
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.


com_mmio_pio_oe_line_set_cfg0
COM_MMIO PIO line output enable set register of COM_MMIO0 to COM_MMIO7.
This register is for activating single COM_MMIO PIOs with a single access. In contrast to using the 'com_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'com_mmio*_cfg' register and also activate
the related bits in the 'com_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'com_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40040130
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Write '1's to activate the related COM_MMIO output enable (when it is in PIO mode).
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.
For read the current value of the programmed output enables is returned (i.e. the value of com_mmio_pio_oe_line_cfg0).


com_mmio_pio_oe_line_reset_cfg0
COM_MMIO PIO line output enable reset register of COM_MMIO0 to COM_MMIO7.
This register is for deactivating single COM_MMIO PIOs with a single access. In contrast to using the 'com_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'com_mmio*_cfg' register and also clear
the related bits in the 'com_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'com_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40040134
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
line
Write '1's to clear the related COM_MMIO output enable (when it is in PIO mode).
If related COM_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls COM_MMIO0, bit 1 controls COM_MMIO1, ... bit 7 controlls COM_MMIO7.
For read the current value of the programmed output enables is returned (i.e. the value of com_mmio_pio_oe_line_cfg0).


com_mmio_in_line_status0
COM_MMIO input line register of COM_MMIO0 to COM_MMIO7.
R
Address : 0x40040138
Bits Name Description
31 - 8 -
 reserved
7 - 0 line
sampled COM_MMIO input state.
Does not depend whether COM_MMIO is in PIO mode or not.
Bit 0 monitors COM_MMIO0, Bit 1 monitors COM_MMIO1, ... bit 7 monitors COM_MMIO7.


com_mmio_is_pio_status0
COM_MMIO mode line register of COM_MMIO0 to COM_MMIO7.
Note: PIO Mode can be enabled or disabled in com_mmio_cfg registers.
R
Address : 0x4004013c
Bits Name Description
31 - 8 -
 reserved
7 - 0 line
Bit 0 shows status of COM_MMIO0, Bit 1 shows status of  COM_MMIO1, ... bit 7 shows COM_MMIO7.
If the COM_MMIO is the standard function of the netX IO (i.e. the netX pin name is COM_MMIO*), the bit of the
related COM_MMIO shows whether the COM_MMIO is in PIO mode or not.
If the COM_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than COM_MMIO*), a PIO function is not
available by the COM_MMIO function. In this case the bit of the related COM_MMIO shows whether the COM_MMIO function is selected or not.
 The related COM_MMIO is a standar d-   Val ue   Status
 function COM_MMIO (netX COM_MMIO*  port)  
               yes    0  The related COM_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related COM_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The COM_MMIO function of the netX IO is selected and assigned to a COM_MMIO core functionality.
               no    1  The COM_MMIO function of the related netX IO is not selected.

Note: When the COM_MMIO function is selected it could be possible that also another IO multiplex function is
      activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
      in global IO multiplexing and could deselect the COM_MMIO function.



Base Address Area: app_asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W app_asic_ctrl_only_por
1 4 R/W app_asic_ctrl_rst_out_cfg
2-3f 8-fc -  reserved

app_asic_ctrl_only_por
Firmware Status register:
This register is not Reset by SW resets, only PORn will reset this register.
R/W
0x00000000
Address : 0x40050000
Bits Reset value Name Description
31 - 0 0x0
data
netX Firmware status


app_asic_ctrl_rst_out_cfg
APP Reset Control Register
R/W
0x00000000
Address : 0x40050004
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 -
app_phy_rst_out_n_in_ro
Status of reset pin (app_phy_rst_out_n). This bit is a read only status and indicates the reset state.
26 "0"
EN_RES_REQ_app_phy_rst_out_n
This bit enables the driving of the programmable reset output app_phy_rst_out_n.
When this bit is not set app_phy_rst_out_n will be in high impedance state.
For all resets this bit is cleared. The external level of the app_phy_rst_out_n output during the reset
must be realized by an external pull up or down resistor (when app_phy_rst_out_n function is desired).
25 "0"
RES_REQ_app_phy_rst_out_n
Software reset for external devices: This bit controls the level of the app_phy_rst_out_n output
for normal operation. For all resets this bit is cleared, however driving of app_phy_rst_out_n
is also disabled (view EN_RES_REQ_app_phy_rst_out_n bit).
24 - 0 0
-
 reserved



Base Address Area: app_mmio_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W app_mmio0_cfg
1 4 R/W app_mmio1_cfg
2 8 R/W app_mmio2_cfg
3 c R/W app_mmio3_cfg
4 10 R/W app_mmio4_cfg
5 14 R/W app_mmio5_cfg
6 18 R/W app_mmio6_cfg
7 1c R/W app_mmio7_cfg
8 20 R/W app_mmio8_cfg
9 24 R/W app_mmio9_cfg
a 28 R/W app_mmio10_cfg
b 2c R/W app_mmio11_cfg
c 30 R/W app_mmio12_cfg
d 34 R/W app_mmio13_cfg
e 38 R/W app_mmio14_cfg
f 3c R/W app_mmio15_cfg
10 40 R/W app_mmio16_cfg
11 44 R/W app_mmio17_cfg
12 48 R/W app_mmio18_cfg
13 4c R/W app_mmio19_cfg
14 50 R/W app_mmio20_cfg
15 54 R/W app_mmio21_cfg
16 58 R/W app_mmio22_cfg
17 5c R/W app_mmio23_cfg
18 60 R/W app_mmio24_cfg
19 64 R/W app_mmio25_cfg
1a 68 R/W app_mmio26_cfg
1b 6c R/W app_mmio27_cfg
1c 70 R/W app_mmio28_cfg
1d 74 R/W app_mmio29_cfg
1e 78 R/W app_mmio30_cfg
1f 7c R/W app_mmio31_cfg
20 80 R/W app_mmio32_cfg
21 84 R/W app_mmio33_cfg
22 88 R/W app_mmio34_cfg
23 8c R/W app_mmio35_cfg
24 90 R/W app_mmio36_cfg
25 94 R/W app_mmio37_cfg
26 98 R/W app_mmio38_cfg
27 9c R/W app_mmio39_cfg
28 a0 R/W app_mmio40_cfg
29 a4 R/W app_mmio41_cfg
2a a8 R/W app_mmio42_cfg
2b ac R/W app_mmio43_cfg
2c b0 R/W app_mmio44_cfg
2d b4 R/W app_mmio45_cfg
2e b8 R/W app_mmio46_cfg
2f bc R/W app_mmio47_cfg
30 c0 R/W app_mmio48_cfg
31 c4 R/W app_mmio49_cfg
32 c8 R/W app_mmio50_cfg
33 cc R/W app_mmio51_cfg
34 d0 R/W app_mmio52_cfg
35 d4 R/W app_mmio53_cfg
36 d8 R/W app_mmio54_cfg
37 dc R/W app_mmio55_cfg
38 e0 R/W app_mmio56_cfg
39 e4 R/W app_mmio57_cfg
3a e8 R/W app_mmio58_cfg
3b ec R/W app_mmio59_cfg
3c f0 R/W app_mmio60_cfg
3d f4 R/W app_mmio61_cfg
3e f8 R/W app_mmio62_cfg
3f fc R/W app_mmio63_cfg
40 100 R/W app_mmio64_cfg
41 104 R/W app_mmio65_cfg
42 108 R/W app_mmio66_cfg
43 10c R/W app_mmio67_cfg
44 110 R/W app_mmio68_cfg
45 114 R/W app_mmio69_cfg
46 118 R/W app_mmio70_cfg
47 11c R/W app_mmio71_cfg
48 120 R/W app_mmio72_cfg
49 124 R/W app_mmio73_cfg
4a 128 R/W app_mmio74_cfg
4b 12c R/W app_mmio75_cfg
4c 130 R/W app_mmio_pio_out_line_cfg0
4d 134 R/W app_mmio_pio_out_line_cfg1
4e 138 R/W app_mmio_pio_out_line_cfg2
4f 13c R/W app_mmio_pio_out_line_set_cfg0
50 140 R/W app_mmio_pio_out_line_set_cfg1
51 144 R/W app_mmio_pio_out_line_set_cfg2
52 148 R/W app_mmio_pio_out_line_reset_cfg0
53 14c R/W app_mmio_pio_out_line_reset_cfg1
54 150 R/W app_mmio_pio_out_line_reset_cfg2
55 154 R/W app_mmio_pio_oe_line_cfg0
56 158 R/W app_mmio_pio_oe_line_cfg1
57 15c R/W app_mmio_pio_oe_line_cfg2
58 160 R/W app_mmio_pio_oe_line_set_cfg0
59 164 R/W app_mmio_pio_oe_line_set_cfg1
5a 168 R/W app_mmio_pio_oe_line_set_cfg2
5b 16c R/W app_mmio_pio_oe_line_reset_cfg0
5c 170 R/W app_mmio_pio_oe_line_reset_cfg1
5d 174 R/W app_mmio_pio_oe_line_reset_cfg2
5e 178 R app_mmio_in_line_status0
5f 17c R app_mmio_in_line_status1
60 180 R app_mmio_in_line_status2
61 184 R app_mmio_is_pio_status0
62 188 R app_mmio_is_pio_status1
63 18c R app_mmio_is_pio_status2
64-7f 190-1fc -  reserved

app_mmio0_cfg
Multiplexmatrix Configuration Register for APP_MMIO0
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050200
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO0, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO0, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO0, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO0 signal selection (default: PIO mode, access-key-protected).
value  netX internal function (core connection)  signal type  functional group
0x00  PIO mode  use line registers  PIO function
0x01  app_i2c0_scl  bidirectional  I2C of HPERI
0x02  app_i2c0_sda  bidirectional  I2C of HPERI
0x03  app_i2c1_scl  bidirectional  I2C of HPERI
0x04  app_i2c1_sda  bidirectional  I2C of HPERI
0x05  app_spi0_mosi  bidirectional  SPI of HPERI
0x06  app_spi0_miso  bidirectional  SPI of HPERI
0x07  app_spi0_clk  bidirectional  SPI of HPERI
0x08  app_spi0_cs0n  bidirectional  SPI of HPERI
0x09  app_spi0_cs1n  bidirectional  SPI of HPERI
0x0a  app_spi0_cs2n  bidirectional  SPI of HPERI
0x0b  app_spi1_mosi  bidirectional  SPI of HPERI
0x0c  app_spi1_miso  bidirectional  SPI of HPERI
0x0d  app_spi1_clk  bidirectional  SPI of HPERI
0x0e  app_spi1_cs0n  bidirectional  SPI of HPERI
0x0f  app_spi1_cs1n  bidirectional  SPI of HPERI
0x10  app_spi1_cs2n  bidirectional  SPI of HPERI
0x11  app_uart0_tx  tristatable output  UART of HPERI (HSOC IP)
0x12  app_uart0_rx  input  UART of HPERI (HSOC IP)
0x13  app_uart0_rtsn  tristatable output  UART of HPERI (HSOC IP)
0x14  app_uart0_ctsn  input  UART of HPERI (HSOC IP)
0x15  app_uart1_tx  tristatable output  UART of HPERI (HSOC IP)
0x16  app_uart1_rx  input  UART of HPERI (HSOC IP)
0x17  app_uart1_rtsn  tristatable output  UART of HPERI (HSOC IP)
0x18  app_uart1_ctsn  input  UART of HPERI (HSOC IP)
0x19  app_gpio0  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1a  app_gpio1  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1b  app_gpio2  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1c  app_gpio3  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1d  app_gpio4  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1e  app_gpio5  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x1f  app_gpio6  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x20  app_gpio7  bidirectional  GPIO of HPERI (Timer/PWM/Blink etc)
0x21  app_sqi0_mosi  bidirectional  SQI of HPERI
0x22  app_sqi0_miso  bidirectional  SQI of HPERI
0x23  app_sqi0_sio2  bidirectional  SQI of HPERI
0x24  app_sqi0_sio3  bidirectional  SQI of HPERI
0x25  app_sqi0_clk  bidirectional  SQI of HPERI
0x26  app_sqi0_cs0n  bidirectional  SQI of HPERI
0x27  app_sqi0_cs1n  bidirectional  SQI of HPERI
0x28  app_sqi0_cs2n  bidirectional  SQI of HPERI
0x29  app_sqi1_mosi  bidirectional  SQI of HPERI
0x2a  app_sqi1_miso  bidirectional  SQI of HPERI
0x2b  app_sqi1_sio2  bidirectional  SQI of HPERI
0x2c  app_sqi1_sio3  bidirectional  SQI of HPERI
0x2d  app_sqi1_clk  bidirectional  SQI of HPERI
0x2e  app_sqi1_cs0n  bidirectional  SQI of HPERI
0x2f  app_sqi1_cs1n  bidirectional  SQI of HPERI
0x30  app_sqi1_cs2n  bidirectional  SQI of HPERI
0x31  cor_uart0_tx  always driven output  UART of APP (Corstone IP)
0x32  cor_uart0_rx  input  UART of APP (Corstone IP)
0x33  cor_uart0_rtsn  always driven output  UART of APP (Corstone IP)
0x34  cor_uart0_ctsn  input  UART of APP (Corstone IP)
0x35  cor_uart1_tx  always driven output  UART of APP (Corstone IP)
0x36  cor_uart1_rx  input  UART of APP (Corstone IP)
0x37  cor_uart1_rtsn  always driven output  UART of APP (Corstone IP)
0x38  cor_uart1_ctsn  input  UART of APP (Corstone IP)
0x39  sdio_cd  input  SDIO of APP (card detect)
0x3a  sdio_wp  input  SDIO of APP (write protect inverted)
0x3b  sdio_rstn  always driven output  SDIO of APP (device reset active low)
0x3c  sdio_dat2_pu_pd  always driven output  SDIO of APP (DAT2 pullup/pulldown)
0x3d  sdio_bus_voltage_enable  always driven output  SDIO of APP (Bus voltage enable / IP mem_ctrl_1)
..  reserved    


app_mmio1_cfg
Multiplexmatrix Configuration Register for APP_MMIO1
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050204
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO1, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO1, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO1, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO1 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio2_cfg
Multiplexmatrix Configuration Register for APP_MMIO2
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050208
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO2, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO2, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO2, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO2 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio3_cfg
Multiplexmatrix Configuration Register for APP_MMIO3
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005020c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO3, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO3, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO3, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO3 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio4_cfg
Multiplexmatrix Configuration Register for APP_MMIO4
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050210
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO4, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO4, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO4, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO4 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio5_cfg
Multiplexmatrix Configuration Register for APP_MMIO5
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050214
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO5, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO5, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO5, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO5 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio6_cfg
Multiplexmatrix Configuration Register for APP_MMIO6
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050218
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO6, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO6, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO6, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO6 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio7_cfg
Multiplexmatrix Configuration Register for APP_MMIO7
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005021c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO7, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO7, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO7, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO7 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio8_cfg
Multiplexmatrix Configuration Register for APP_MMIO8
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050220
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO8, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO8, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO8, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO8 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio9_cfg
Multiplexmatrix Configuration Register for APP_MMIO9
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050224
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO9, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO9, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO9, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO9 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio10_cfg
Multiplexmatrix Configuration Register for APP_MMIO10
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050228
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO10, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO10, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO10, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO10 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio11_cfg
Multiplexmatrix Configuration Register for APP_MMIO11
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005022c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO11, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO11, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO11, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO11 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio12_cfg
Multiplexmatrix Configuration Register for APP_MMIO12
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050230
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO12, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO12, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO12, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO12 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio13_cfg
Multiplexmatrix Configuration Register for APP_MMIO13
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050234
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO13, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO13, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO13, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO13 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio14_cfg
Multiplexmatrix Configuration Register for APP_MMIO14
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050238
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO14, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO14, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO14, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO14 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio15_cfg
Multiplexmatrix Configuration Register for APP_MMIO15
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005023c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO15, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO15, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO15, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO15 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio16_cfg
Multiplexmatrix Configuration Register for APP_MMIO16
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050240
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO16, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO16, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO16, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO16 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio17_cfg
Multiplexmatrix Configuration Register for APP_MMIO17
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050244
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO17, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO17, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO17, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO17 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio18_cfg
Multiplexmatrix Configuration Register for APP_MMIO18
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050248
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO18, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO18, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO18, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO18 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio19_cfg
Multiplexmatrix Configuration Register for APP_MMIO19
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005024c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO19, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO19, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO19, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO19 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio20_cfg
Multiplexmatrix Configuration Register for APP_MMIO20
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050250
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO20, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO20, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO20, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO20 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio21_cfg
Multiplexmatrix Configuration Register for APP_MMIO21
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050254
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO21, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO21, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO21, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO21 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio22_cfg
Multiplexmatrix Configuration Register for APP_MMIO22
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050258
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO22, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO22, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO22, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO22 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio23_cfg
Multiplexmatrix Configuration Register for APP_MMIO23
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005025c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO23, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO23, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO23, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO23 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio24_cfg
Multiplexmatrix Configuration Register for APP_MMIO24
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050260
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO24, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO24, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO24, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO24 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio25_cfg
Multiplexmatrix Configuration Register for APP_MMIO25
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050264
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO25, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO25, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO25, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO25 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio26_cfg
Multiplexmatrix Configuration Register for APP_MMIO26
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050268
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO26, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO26, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO26, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO26 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio27_cfg
Multiplexmatrix Configuration Register for APP_MMIO27
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005026c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO27, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO27, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO27, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO27 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio28_cfg
Multiplexmatrix Configuration Register for APP_MMIO28
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050270
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO28, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO28, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO28, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO28 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio29_cfg
Multiplexmatrix Configuration Register for APP_MMIO29
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050274
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO29, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO29, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO29, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO29 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio30_cfg
Multiplexmatrix Configuration Register for APP_MMIO30
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050278
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO30, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO30, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO30, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO30 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio31_cfg
Multiplexmatrix Configuration Register for APP_MMIO31
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005027c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO31, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO31, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO31, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO31 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio32_cfg
Multiplexmatrix Configuration Register for APP_MMIO32
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050280
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO32, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO32, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO32, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO32 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio33_cfg
Multiplexmatrix Configuration Register for APP_MMIO33
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050284
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO33, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO33, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO33, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO33 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio34_cfg
Multiplexmatrix Configuration Register for APP_MMIO34
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050288
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO34, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO34, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO34, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO34 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio35_cfg
Multiplexmatrix Configuration Register for APP_MMIO35
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005028c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO35, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO35, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO35, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO35 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio36_cfg
Multiplexmatrix Configuration Register for APP_MMIO36
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050290
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO36, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO36, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO36, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO36 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio37_cfg
Multiplexmatrix Configuration Register for APP_MMIO37
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000032
Address : 0x40050294
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO37, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO37, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO37, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "110010"
app_mmio_sel
APP_MMIO37 signal selection (default: cor_uart0_rx of UART of APP (Corstone IP), access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio38_cfg
Multiplexmatrix Configuration Register for APP_MMIO38
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000031
Address : 0x40050298
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO38, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO38, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO38, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "110001"
app_mmio_sel
APP_MMIO38 signal selection (default: cor_uart0_tx of UART of APP (Corstone IP), access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio39_cfg
Multiplexmatrix Configuration Register for APP_MMIO39
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005029c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO39, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO39, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO39, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO39 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio40_cfg
Multiplexmatrix Configuration Register for APP_MMIO40
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502a0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO40, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO40, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO40, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO40 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio41_cfg
Multiplexmatrix Configuration Register for APP_MMIO41
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502a4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO41, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO41, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO41, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO41 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio42_cfg
Multiplexmatrix Configuration Register for APP_MMIO42
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502a8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO42, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO42, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO42, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO42 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio43_cfg
Multiplexmatrix Configuration Register for APP_MMIO43
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502ac
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO43, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO43, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO43, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO43 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio44_cfg
Multiplexmatrix Configuration Register for APP_MMIO44
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502b0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO44, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO44, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO44, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO44 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio45_cfg
Multiplexmatrix Configuration Register for APP_MMIO45
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502b4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO45, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO45, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO45, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO45 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio46_cfg
Multiplexmatrix Configuration Register for APP_MMIO46
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502b8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO46, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO46, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO46, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO46 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio47_cfg
Multiplexmatrix Configuration Register for APP_MMIO47
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502bc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO47, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO47, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO47, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO47 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio48_cfg
Multiplexmatrix Configuration Register for APP_MMIO48
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502c0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO48, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO48, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO48, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO48 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio49_cfg
Multiplexmatrix Configuration Register for APP_MMIO49
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502c4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO49, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO49, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO49, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO49 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio50_cfg
Multiplexmatrix Configuration Register for APP_MMIO50
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502c8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO50, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO50, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO50, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO50 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio51_cfg
Multiplexmatrix Configuration Register for APP_MMIO51
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502cc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO51, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO51, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO51, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO51 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio52_cfg
Multiplexmatrix Configuration Register for APP_MMIO52
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502d0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO52, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO52, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO52, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO52 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio53_cfg
Multiplexmatrix Configuration Register for APP_MMIO53
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502d4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO53, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO53, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO53, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO53 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio54_cfg
Multiplexmatrix Configuration Register for APP_MMIO54
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502d8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO54, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO54, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO54, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO54 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio55_cfg
Multiplexmatrix Configuration Register for APP_MMIO55
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502dc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO55, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO55, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO55, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO55 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio56_cfg
Multiplexmatrix Configuration Register for APP_MMIO56
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502e0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO56, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO56, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO56, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO56 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio57_cfg
Multiplexmatrix Configuration Register for APP_MMIO57
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502e4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO57, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO57, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO57, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO57 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio58_cfg
Multiplexmatrix Configuration Register for APP_MMIO58
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502e8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO58, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO58, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO58, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO58 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio59_cfg
Multiplexmatrix Configuration Register for APP_MMIO59
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502ec
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO59, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO59, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO59, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO59 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio60_cfg
Multiplexmatrix Configuration Register for APP_MMIO60
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502f0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO60, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO60, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO60, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO60 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio61_cfg
Multiplexmatrix Configuration Register for APP_MMIO61
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502f4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO61, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO61, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO61, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO61 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio62_cfg
Multiplexmatrix Configuration Register for APP_MMIO62
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502f8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO62, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO62, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO62, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO62 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio63_cfg
Multiplexmatrix Configuration Register for APP_MMIO63
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x400502fc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO63, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO63, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO63, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO63 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio64_cfg
Multiplexmatrix Configuration Register for APP_MMIO64
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050300
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO64, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO64, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO64, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO64 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio65_cfg
Multiplexmatrix Configuration Register for APP_MMIO65
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050304
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO65, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO65, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO65, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO65 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio66_cfg
Multiplexmatrix Configuration Register for APP_MMIO66
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050308
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO66, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO66, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO66, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO66 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio67_cfg
Multiplexmatrix Configuration Register for APP_MMIO67
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005030c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO67, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO67, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO67, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO67 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio68_cfg
Multiplexmatrix Configuration Register for APP_MMIO68
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050310
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO68, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO68, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO68, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO68 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio69_cfg
Multiplexmatrix Configuration Register for APP_MMIO69
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050314
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO69, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO69, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO69, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO69 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio70_cfg
Multiplexmatrix Configuration Register for APP_MMIO70
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050318
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO70, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO70, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO70, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO70 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio71_cfg
Multiplexmatrix Configuration Register for APP_MMIO71
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005031c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO71, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO71, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO71, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO71 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio72_cfg
Multiplexmatrix Configuration Register for APP_MMIO72
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050320
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO72, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO72, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO72, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO72 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio73_cfg
Multiplexmatrix Configuration Register for APP_MMIO73
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050324
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO73, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO73, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO73, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO73 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio74_cfg
Multiplexmatrix Configuration Register for APP_MMIO74
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x40050328
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO74, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO74, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO74, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO74 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio75_cfg
Multiplexmatrix Configuration Register for APP_MMIO75
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any APP_MMIO will be assigned to 0.
If one core-connection is mapped to more than one APP_MMIO, the core-input-state will be these ored APP_MMIO-states.
R/W
0x00000000
Address : 0x4005032c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of APP_MMIO75, could also be read from 'app_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of APP_MMIO75, could also be programmd by 'app_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of APP_MMIO75, could also be programmd by app_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'app_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
app_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
app_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 6 0
-
 reserved
5 - 0 "000000"
app_mmio_sel
APP_MMIO75 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_app_mmio0_cfg


app_mmio_pio_out_line_cfg0
APP_MMIO PIO line output level register of APP_MMIO0 to APP_MMIO31.
Changing bits here will change 'pio_out' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050330
Bits Reset value Name Description
31 - 0 0x0
line
Output state if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.


app_mmio_pio_out_line_cfg1
APP_MMIO PIO line output level register of APP_MMIO32 to APP_MMIO63.
Changing bits here will change 'pio_out' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050334
Bits Reset value Name Description
31 - 0 0x0
line
Output state if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.


app_mmio_pio_out_line_cfg2
APP_MMIO PIO line output level register of APP_MMIO64 to APP_MMIO75.
Changing bits here will change 'pio_out' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050338
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Output state if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.


app_mmio_pio_out_line_set_cfg0
APP_MMIO PIO line output level set register of APP_MMIO0 to APP_MMIO31.
This register is for setting single APP_MMIO PIOs to high level with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4005033c
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related APP_MMIO output to high level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg0).


app_mmio_pio_out_line_set_cfg1
APP_MMIO PIO line output level set register of APP_MMIO32 to APP_MMIO63.
This register is for setting single APP_MMIO PIOs to high level with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_out_line_cfg1' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050340
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related APP_MMIO output to high level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg1).


app_mmio_pio_out_line_set_cfg2
APP_MMIO PIO line output level set register of APP_MMIO64 to APP_MMIO75.
This register is for setting single APP_MMIO PIOs to high level with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg2' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_out_line_cfg2' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg2' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050344
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Write '1's to set the related APP_MMIO output to high level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg2).


app_mmio_pio_out_line_reset_cfg0
APP_MMIO PIO line output level reset register of APP_MMIO0 to APP_MMIO31.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050348
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related APP_MMIO output to low level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg0).


app_mmio_pio_out_line_reset_cfg1
APP_MMIO PIO line output level reset register of APP_MMIO32 to APP_MMIO63.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_out_line_cfg1' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4005034c
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related APP_MMIO output to low level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg1).


app_mmio_pio_out_line_reset_cfg2
APP_MMIO PIO line output level reset register of APP_MMIO64 to APP_MMIO75.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_out_line_cfg2' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_out_line_cfg2' register.
For read this register returns the same value as the 'app_mmio_pio_out_line_cfg2' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050350
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Write '1's to set the related APP_MMIO output to low level (when it is in PIO mode and output is enabled).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.
For read the current value of the programmed output states is returned (i.e. the value of app_mmio_pio_out_line_cfg2).


app_mmio_pio_oe_line_cfg0
APP_MMIO PIO line output enable register of APP_MMIO0 to APP_MMIO31.
Changing bits here will change 'pio_oe' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050354
Bits Reset value Name Description
31 - 0 0x0
line
Output enable if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.


app_mmio_pio_oe_line_cfg1
APP_MMIO PIO line output enable register of APP_MMIO32 to APP_MMIO63.
Changing bits here will change 'pio_oe' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050358
Bits Reset value Name Description
31 - 0 0x0
line
Output enable if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.


app_mmio_pio_oe_line_cfg2
APP_MMIO PIO line output enable register of APP_MMIO64 to APP_MMIO75.
Changing bits here will change 'pio_oe' bit of related app_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4005035c
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Output enable if related APP_MMIO is in PIO mode.
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.


app_mmio_pio_oe_line_set_cfg0
APP_MMIO PIO line output enable set register of APP_MMIO0 to APP_MMIO31.
This register is for activating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050360
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to activate the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg0).


app_mmio_pio_oe_line_set_cfg1
APP_MMIO PIO line output enable set register of APP_MMIO32 to APP_MMIO63.
This register is for activating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_oe_line_cfg1' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050364
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to activate the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg1).


app_mmio_pio_oe_line_set_cfg2
APP_MMIO PIO line output enable set register of APP_MMIO64 to APP_MMIO75.
This register is for activating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg2' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'app_mmio*_cfg' register and also activate
the related bits in the 'app_mmio_pio_oe_line_cfg2' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg2' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050368
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Write '1's to activate the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg2).


app_mmio_pio_oe_line_reset_cfg0
APP_MMIO PIO line output enable reset register of APP_MMIO0 to APP_MMIO31.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4005036c
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to clear the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO0, bit 1 controls APP_MMIO1, ... bit 31 controlls APP_MMIO31.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg0).


app_mmio_pio_oe_line_reset_cfg1
APP_MMIO PIO line output enable reset register of APP_MMIO32 to APP_MMIO63.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_oe_line_cfg1' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050370
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to clear the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO32, bit 1 controls APP_MMIO33, ... bit 31 controlls APP_MMIO63.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg1).


app_mmio_pio_oe_line_reset_cfg2
APP_MMIO PIO line output enable reset register of APP_MMIO64 to APP_MMIO75.
This register is for deactivating single APP_MMIO PIOs with a single access. In contrast to using the 'app_mmio_pio_oe_line_cfg2' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'app_mmio*_cfg' register and also clear
the related bits in the 'app_mmio_pio_oe_line_cfg2' register.
For read this register returns the same value as the 'app_mmio_pio_oe_line_cfg2' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40050374
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 0 0x0
line
Write '1's to clear the related APP_MMIO output enable (when it is in PIO mode).
If related APP_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls APP_MMIO64, bit 1 controls APP_MMIO65, ... bit 11 controlls APP_MMIO75.
For read the current value of the programmed output enables is returned (i.e. the value of app_mmio_pio_oe_line_cfg2).


app_mmio_in_line_status0
APP_MMIO input line register of APP_MMIO0 to APP_MMIO31.
R
Address : 0x40050378
Bits Name Description
31 - 0 line
sampled APP_MMIO input state.
Does not depend whether APP_MMIO is in PIO mode or not.
Bit 0 monitors APP_MMIO0, Bit 1 monitors APP_MMIO1, ... bit 31 monitors APP_MMIO31.


app_mmio_in_line_status1
APP_MMIO input line register of APP_MMIO32 to APP_MMIO63.
R
Address : 0x4005037c
Bits Name Description
31 - 0 line
sampled APP_MMIO input state.
Does not depend whether APP_MMIO is in PIO mode or not.
Bit 0 monitors APP_MMIO32, Bit 1 monitors APP_MMIO33, ... bit 31 monitors APP_MMIO63.


app_mmio_in_line_status2
APP_MMIO input line register of APP_MMIO64 to APP_MMIO75.
R
Address : 0x40050380
Bits Name Description
31 - 12 -
 reserved
11 - 0 line
sampled APP_MMIO input state.
Does not depend whether APP_MMIO is in PIO mode or not.
Bit 0 monitors APP_MMIO64, Bit 1 monitors APP_MMIO65, ... bit 11 monitors APP_MMIO75.


app_mmio_is_pio_status0
APP_MMIO mode line register of APP_MMIO0 to APP_MMIO31.
Note: PIO Mode can be enabled or disabled in app_mmio_cfg registers.
R
Address : 0x40050384
Bits Name Description
31 - 0 line
Bit 0 shows status of APP_MMIO0, Bit 1 shows status of  APP_MMIO1, ... bit 31 shows APP_MMIO31.
If the APP_MMIO is the standard function of the netX IO (i.e. the netX pin name is APP_MMIO*), the bit of the
related APP_MMIO shows whether the APP_MMIO is in PIO mode or not.
If the APP_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than APP_MMIO*), a PIO function is not
available by the APP_MMIO function. In this case the bit of the related APP_MMIO shows whether the APP_MMIO function is selected or not.
 The related APP_MMIO is a standar d-   Val ue   Status
 function APP_MMIO (netX APP_MMIO*  port)  
               yes    0  The related APP_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related APP_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The APP_MMIO function of the netX IO is selected and assigned to a APP_MMIO core functionality.
               no    1  The APP_MMIO function of the related netX IO is not selected.

Note: When the APP_MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the APP_MMIO function.


app_mmio_is_pio_status1
APP_MMIO mode line register of APP_MMIO32 to APP_MMIO63.
Note: PIO Mode can be enabled or disabled in app_mmio_cfg registers.
R
Address : 0x40050388
Bits Name Description
31 - 0 line
Bit 0 shows status of APP_MMIO32, Bit 1 shows status of  APP_MMIO33, ... bit 31 shows APP_MMIO63.
If the APP_MMIO is the standard function of the netX IO (i.e. the netX pin name is APP_MMIO*), the bit of the
related APP_MMIO shows whether the APP_MMIO is in PIO mode or not.
If the APP_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than APP_MMIO*), a PIO function is not
available by the APP_MMIO function. In this case the bit of the related APP_MMIO shows whether the APP_MMIO function is selected or not.
 The related APP_MMIO is a standar d-   Val ue   Status
 function APP_MMIO (netX APP_MMIO*  port)  
               yes    0  The related APP_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related APP_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The APP_MMIO function of the netX IO is selected and assigned to a APP_MMIO core functionality.
               no    1  The APP_MMIO function of the related netX IO is not selected.

Note: When the APP_MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the APP_MMIO function.


app_mmio_is_pio_status2
APP_MMIO mode line register of APP_MMIO64 to APP_MMIO75.
Note: PIO Mode can be enabled or disabled in app_mmio_cfg registers.
R
Address : 0x4005038c
Bits Name Description
31 - 12 -
 reserved
11 - 0 line
Bit 0 shows status of APP_MMIO64, Bit 1 shows status of  APP_MMIO65, ... bit 11 shows APP_MMIO75.
If the APP_MMIO is the standard function of the netX IO (i.e. the netX pin name is APP_MMIO*), the bit of the
related APP_MMIO shows whether the APP_MMIO is in PIO mode or not.
If the APP_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than APP_MMIO*), a PIO function is not
available by the APP_MMIO function. In this case the bit of the related APP_MMIO shows whether the APP_MMIO function is selected or not.
 The related APP_MMIO is a standar d-   Val ue   Status
 function APP_MMIO (netX APP_MMIO*  port)  
               yes    0  The related APP_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related APP_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The APP_MMIO function of the netX IO is selected and assigned to a APP_MMIO core functionality.
               no    1  The APP_MMIO function of the related netX IO is not selected.

Note: When the APP_MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the APP_MMIO function.



Base Address Area: mot_asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R mot_asic_ctrl_rstsyn
1-3f 4-fc -  reserved

mot_asic_ctrl_rstsyn
MOT Reset Syndrome Status register
R
Address : 0x40060000
Bits Name Description
31 - 5 -
 reserved
4 ext
Indicates the last reset of the MOT system was caused by a request to reset this system.
3 host
Indicates the last reset of the MOT system was caused by an APP system reset request.
2 res
Unused by current SSE710 release. Always read back 0.
1 nsrst
Indicates that the last reset of the MOT system was caused by either:
- nSRST pin being asserted.
- DP ROM CSYSRSTREQ being asserted.
0 por
Indicates that the last reset of the MOT system was caused by one of the following:
- POR_N pin being asserted.
- DP CDBGRSTREQ being asserted.
- SoC Watchdog reset request.
- Secure Enclave Watchdog reset request.
- SOC_RST_CTRL.RST_REQ bit set to 1.
- Secure Enclave software reset request.



Base Address Area: mot_mmio_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_mmio0_cfg
1 4 R/W mot_mmio1_cfg
2 8 R/W mot_mmio2_cfg
3 c R/W mot_mmio3_cfg
4 10 R/W mot_mmio4_cfg
5 14 R/W mot_mmio5_cfg
6 18 R/W mot_mmio6_cfg
7 1c R/W mot_mmio7_cfg
8 20 R/W mot_mmio8_cfg
9 24 R/W mot_mmio9_cfg
a 28 R/W mot_mmio10_cfg
b 2c R/W mot_mmio11_cfg
c 30 R/W mot_mmio12_cfg
d 34 R/W mot_mmio13_cfg
e 38 R/W mot_mmio14_cfg
f 3c R/W mot_mmio15_cfg
10 40 R/W mot_mmio16_cfg
11 44 R/W mot_mmio17_cfg
12 48 R/W mot_mmio18_cfg
13 4c R/W mot_mmio19_cfg
14 50 R/W mot_mmio20_cfg
15 54 R/W mot_mmio21_cfg
16 58 R/W mot_mmio22_cfg
17 5c R/W mot_mmio23_cfg
18 60 R/W mot_mmio24_cfg
19 64 R/W mot_mmio25_cfg
1a 68 R/W mot_mmio26_cfg
1b 6c R/W mot_mmio27_cfg
1c 70 R/W mot_mmio28_cfg
1d 74 R/W mot_mmio29_cfg
1e 78 R/W mot_mmio30_cfg
1f 7c R/W mot_mmio31_cfg
20 80 R/W mot_mmio32_cfg
21 84 R/W mot_mmio33_cfg
22 88 R/W mot_mmio34_cfg
23 8c R/W mot_mmio35_cfg
24 90 R/W mot_mmio36_cfg
25 94 R/W mot_mmio37_cfg
26 98 R/W mot_mmio38_cfg
27 9c R/W mot_mmio39_cfg
28 a0 R/W mot_mmio40_cfg
29 a4 R/W mot_mmio41_cfg
2a a8 R/W mot_mmio42_cfg
2b ac R/W mot_mmio43_cfg
2c b0 R/W mot_mmio44_cfg
2d b4 R/W mot_mmio45_cfg
2e b8 R/W mot_mmio46_cfg
2f bc R/W mot_mmio47_cfg
30 c0 R/W mot_mmio48_cfg
31 c4 R/W mot_mmio49_cfg
32 c8 R/W mot_mmio50_cfg
33 cc R/W mot_mmio51_cfg
34 d0 R/W mot_mmio52_cfg
35 d4 R/W mot_mmio53_cfg
36 d8 R/W mot_mmio54_cfg
37 dc R/W mot_mmio55_cfg
38 e0 R/W mot_mmio56_cfg
39 e4 R/W mot_mmio57_cfg
3a e8 R/W mot_mmio58_cfg
3b ec R/W mot_mmio59_cfg
3c f0 R/W mot_mmio60_cfg
3d f4 R/W mot_mmio61_cfg
3e f8 R/W mot_mmio62_cfg
3f fc R/W mot_mmio_pio_out_line_cfg0
40 100 R/W mot_mmio_pio_out_line_cfg1
41 104 R/W mot_mmio_pio_out_line_set_cfg0
42 108 R/W mot_mmio_pio_out_line_set_cfg1
43 10c R/W mot_mmio_pio_out_line_reset_cfg0
44 110 R/W mot_mmio_pio_out_line_reset_cfg1
45 114 R/W mot_mmio_pio_oe_line_cfg0
46 118 R/W mot_mmio_pio_oe_line_cfg1
47 11c R/W mot_mmio_pio_oe_line_set_cfg0
48 120 R/W mot_mmio_pio_oe_line_set_cfg1
49 124 R/W mot_mmio_pio_oe_line_reset_cfg0
4a 128 R/W mot_mmio_pio_oe_line_reset_cfg1
4b 12c R mot_mmio_in_line_status0
4c 130 R mot_mmio_in_line_status1
4d 134 R mot_mmio_is_pio_status0
4e 138 R mot_mmio_is_pio_status1
4f-7f 13c-1fc -  reserved

mot_mmio0_cfg
Multiplexmatrix Configuration Register for MOT_MMIO0
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060200
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO0, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO0, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO0, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO0 signal selection (default: PIO mode, access-key-protected).
value  netX internal function (core connection)  signal type  functional group
0x00  PIO mode  use line registers  PIO function
0x01  mot_i2c0_scl  bidirectional  I2C of MOT
0x02  mot_i2c0_sda  bidirectional  I2C of MOT
0x03  mot_i2c1_scl  bidirectional  I2C of MOT
0x04  mot_i2c1_sda  bidirectional  I2C of MOT
0x05  mot_spi0_mosi  bidirectional  SPI of MOT
0x06  mot_spi0_miso  bidirectional  SPI of MOT
0x07  mot_spi0_clk  bidirectional  SPI of MOT
0x08  mot_spi0_cs0n  bidirectional  SPI of MOT
0x09  mot_spi0_cs1n  bidirectional  SPI of MOT
0x0a  mot_spi0_cs2n  bidirectional  SPI of MOT
0x0b  mot_spi1_mosi  bidirectional  SPI of MOT
0x0c  mot_spi1_miso  bidirectional  SPI of MOT
0x0d  mot_spi1_clk  bidirectional  SPI of MOT
0x0e  mot_spi1_cs0n  bidirectional  SPI of MOT
0x0f  mot_spi1_cs1n  bidirectional  SPI of MOT
0x10  mot_spi1_cs2n  bidirectional  SPI of MOT
0x11  mot_uart0_tx  tristatable output  UART of MOT (HSOC IP)
0x12  mot_uart0_rx  input  UART of MOT (HSOC IP)
0x13  mot_uart0_rtsn  tristatable output  UART of MOT (HSOC IP)
0x14  mot_uart0_ctsn  input  UART of MOT (HSOC IP)
0x15  mot_uart1_tx  tristatable output  UART of MOT (HSOC IP)
0x16  mot_uart1_rx  input  UART of MOT (HSOC IP)
0x17  mot_uart1_rtsn  tristatable output  UART of MOT (HSOC IP)
0x18  mot_uart1_ctsn  input  UART of MOT (HSOC IP)
0x19  mot_gpio0  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1a  mot_gpio1  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1b  mot_gpio2  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1c  mot_gpio3  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1d  mot_gpio4  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1e  mot_gpio5  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x1f  mot_gpio6  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x20  mot_gpio7  bidirectional  GPIO of MOT (Timer/PWM/Blink etc)
0x21  mot_sqi0_mosi  bidirectional  SQI of MOT
0x22  mot_sqi0_miso  bidirectional  SQI of MOT
0x23  mot_sqi0_sio2  bidirectional  SQI of MOT
0x24  mot_sqi0_sio3  bidirectional  SQI of MOT
0x25  mot_sqi0_clk  bidirectional  SQI of MOT
0x26  mot_sqi0_cs0n  bidirectional  SQI of MOT
0x27  mot_sqi0_cs1n  bidirectional  SQI of MOT
0x28  mot_sqi0_cs2n  bidirectional  SQI of MOT
0x29  mot_sqi1_mosi  bidirectional  SQI of MOT
0x2a  mot_sqi1_miso  bidirectional  SQI of MOT
0x2b  mot_sqi1_sio2  bidirectional  SQI of MOT
0x2c  mot_sqi1_sio3  bidirectional  SQI of MOT
0x2d  mot_sqi1_clk  bidirectional  SQI of MOT
0x2e  mot_sqi1_cs0n  bidirectional  SQI of MOT
0x2f  mot_sqi1_cs1n  bidirectional  SQI of MOT
0x30  mot_sqi1_cs2n  bidirectional  SQI of MOT
0x31  mpwm_pwm0  always driven output  MPWM
0x32  mpwm_pwm1  always driven output  MPWM
0x33  mpwm_pwm2  always driven output  MPWM
0x34  mpwm_pwm3  always driven output  MPWM
0x35  mpwm_pwm4  always driven output  MPWM
0x36  mpwm_pwm5  always driven output  MPWM
0x37  mpwm_brake  always driven output  MPWM
0x38  mpwm_fail  input  MPWM
0x39  menc0_a  input  MENC
0x3a  menc0_b  input  MENC
0x3b  menc0_n  input  MENC
0x3c  menc1_a  input  MENC
0x3d  menc1_b  input  MENC
0x3e  menc1_n  input  MENC
0x3f  menc_mp0  input  MENC
0x40  menc_mp1  input  MENC
0x41  singen_sin  always driven output  SINGEN
0x42  singen_demod  always driven output  SINGEN
0x43  sdmf0_sdm_clk  always driven output  SDMF0
0x44  sdmf0_sdm_d0  input  SDMF0
0x45  sdmf0_sdm_d1  input  SDMF0
0x46  sdmf1_sdm_clk  always driven output  SDMF1
0x47  sdmf1_sdm_d0  input  SDMF1
0x48  sdmf1_sdm_d1  input  SDMF1
0x49  sdmf2_sdm_clk  always driven output  SDMF2
0x4a  sdmf2_sdm_d0  input  SDMF2
0x4b  sdmf2_sdm_d1  input  SDMF2
0x4c  sdmf2_sdm_d2  input  SDMF2
..  reserved    


mot_mmio1_cfg
Multiplexmatrix Configuration Register for MOT_MMIO1
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060204
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO1, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO1, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO1, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO1 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio2_cfg
Multiplexmatrix Configuration Register for MOT_MMIO2
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060208
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO2, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO2, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO2, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO2 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio3_cfg
Multiplexmatrix Configuration Register for MOT_MMIO3
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006020c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO3, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO3, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO3, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO3 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio4_cfg
Multiplexmatrix Configuration Register for MOT_MMIO4
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060210
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO4, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO4, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO4, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO4 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio5_cfg
Multiplexmatrix Configuration Register for MOT_MMIO5
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060214
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO5, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO5, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO5, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO5 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio6_cfg
Multiplexmatrix Configuration Register for MOT_MMIO6
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060218
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO6, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO6, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO6, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO6 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio7_cfg
Multiplexmatrix Configuration Register for MOT_MMIO7
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006021c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO7, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO7, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO7, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO7 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio8_cfg
Multiplexmatrix Configuration Register for MOT_MMIO8
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060220
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO8, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO8, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO8, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO8 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio9_cfg
Multiplexmatrix Configuration Register for MOT_MMIO9
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060224
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO9, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO9, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO9, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO9 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio10_cfg
Multiplexmatrix Configuration Register for MOT_MMIO10
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060228
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO10, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO10, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO10, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO10 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio11_cfg
Multiplexmatrix Configuration Register for MOT_MMIO11
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006022c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO11, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO11, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO11, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO11 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio12_cfg
Multiplexmatrix Configuration Register for MOT_MMIO12
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060230
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO12, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO12, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO12, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO12 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio13_cfg
Multiplexmatrix Configuration Register for MOT_MMIO13
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060234
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO13, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO13, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO13, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO13 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio14_cfg
Multiplexmatrix Configuration Register for MOT_MMIO14
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060238
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO14, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO14, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO14, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO14 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio15_cfg
Multiplexmatrix Configuration Register for MOT_MMIO15
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006023c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO15, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO15, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO15, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO15 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio16_cfg
Multiplexmatrix Configuration Register for MOT_MMIO16
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060240
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO16, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO16, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO16, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO16 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio17_cfg
Multiplexmatrix Configuration Register for MOT_MMIO17
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060244
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO17, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO17, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO17, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO17 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio18_cfg
Multiplexmatrix Configuration Register for MOT_MMIO18
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060248
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO18, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO18, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO18, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO18 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio19_cfg
Multiplexmatrix Configuration Register for MOT_MMIO19
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006024c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO19, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO19, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO19, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO19 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio20_cfg
Multiplexmatrix Configuration Register for MOT_MMIO20
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060250
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO20, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO20, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO20, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO20 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio21_cfg
Multiplexmatrix Configuration Register for MOT_MMIO21
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060254
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO21, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO21, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO21, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO21 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio22_cfg
Multiplexmatrix Configuration Register for MOT_MMIO22
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060258
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO22, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO22, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO22, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO22 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio23_cfg
Multiplexmatrix Configuration Register for MOT_MMIO23
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006025c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO23, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO23, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO23, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO23 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio24_cfg
Multiplexmatrix Configuration Register for MOT_MMIO24
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060260
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO24, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO24, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO24, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO24 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio25_cfg
Multiplexmatrix Configuration Register for MOT_MMIO25
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060264
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO25, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO25, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO25, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO25 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio26_cfg
Multiplexmatrix Configuration Register for MOT_MMIO26
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060268
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO26, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO26, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO26, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO26 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio27_cfg
Multiplexmatrix Configuration Register for MOT_MMIO27
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006026c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO27, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO27, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO27, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO27 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio28_cfg
Multiplexmatrix Configuration Register for MOT_MMIO28
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060270
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO28, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO28, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO28, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO28 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio29_cfg
Multiplexmatrix Configuration Register for MOT_MMIO29
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060274
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO29, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO29, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO29, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO29 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio30_cfg
Multiplexmatrix Configuration Register for MOT_MMIO30
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060278
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO30, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO30, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO30, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO30 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio31_cfg
Multiplexmatrix Configuration Register for MOT_MMIO31
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006027c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO31, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO31, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO31, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO31 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio32_cfg
Multiplexmatrix Configuration Register for MOT_MMIO32
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060280
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO32, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO32, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO32, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO32 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio33_cfg
Multiplexmatrix Configuration Register for MOT_MMIO33
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060284
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO33, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO33, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO33, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO33 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio34_cfg
Multiplexmatrix Configuration Register for MOT_MMIO34
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060288
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO34, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO34, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO34, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO34 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio35_cfg
Multiplexmatrix Configuration Register for MOT_MMIO35
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006028c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO35, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO35, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO35, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO35 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio36_cfg
Multiplexmatrix Configuration Register for MOT_MMIO36
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060290
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO36, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO36, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO36, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO36 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio37_cfg
Multiplexmatrix Configuration Register for MOT_MMIO37
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060294
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO37, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO37, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO37, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO37 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio38_cfg
Multiplexmatrix Configuration Register for MOT_MMIO38
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x40060298
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO38, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO38, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO38, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO38 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio39_cfg
Multiplexmatrix Configuration Register for MOT_MMIO39
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x4006029c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO39, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO39, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO39, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO39 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio40_cfg
Multiplexmatrix Configuration Register for MOT_MMIO40
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602a0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO40, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO40, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO40, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO40 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio41_cfg
Multiplexmatrix Configuration Register for MOT_MMIO41
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602a4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO41, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO41, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO41, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO41 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio42_cfg
Multiplexmatrix Configuration Register for MOT_MMIO42
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602a8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO42, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO42, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO42, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO42 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio43_cfg
Multiplexmatrix Configuration Register for MOT_MMIO43
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602ac
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO43, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO43, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO43, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO43 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio44_cfg
Multiplexmatrix Configuration Register for MOT_MMIO44
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602b0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO44, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO44, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO44, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO44 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio45_cfg
Multiplexmatrix Configuration Register for MOT_MMIO45
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602b4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO45, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO45, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO45, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO45 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio46_cfg
Multiplexmatrix Configuration Register for MOT_MMIO46
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602b8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO46, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO46, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO46, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO46 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio47_cfg
Multiplexmatrix Configuration Register for MOT_MMIO47
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602bc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO47, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO47, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO47, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO47 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio48_cfg
Multiplexmatrix Configuration Register for MOT_MMIO48
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602c0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO48, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO48, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO48, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO48 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio49_cfg
Multiplexmatrix Configuration Register for MOT_MMIO49
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602c4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO49, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO49, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO49, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO49 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio50_cfg
Multiplexmatrix Configuration Register for MOT_MMIO50
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602c8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO50, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO50, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO50, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO50 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio51_cfg
Multiplexmatrix Configuration Register for MOT_MMIO51
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602cc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO51, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO51, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO51, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO51 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio52_cfg
Multiplexmatrix Configuration Register for MOT_MMIO52
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602d0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO52, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO52, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO52, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO52 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio53_cfg
Multiplexmatrix Configuration Register for MOT_MMIO53
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602d4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO53, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO53, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO53, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO53 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio54_cfg
Multiplexmatrix Configuration Register for MOT_MMIO54
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602d8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO54, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO54, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO54, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO54 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio55_cfg
Multiplexmatrix Configuration Register for MOT_MMIO55
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602dc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO55, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO55, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO55, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO55 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio56_cfg
Multiplexmatrix Configuration Register for MOT_MMIO56
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602e0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO56, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO56, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO56, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO56 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio57_cfg
Multiplexmatrix Configuration Register for MOT_MMIO57
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602e4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO57, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO57, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO57, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO57 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio58_cfg
Multiplexmatrix Configuration Register for MOT_MMIO58
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602e8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO58, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO58, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO58, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO58 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio59_cfg
Multiplexmatrix Configuration Register for MOT_MMIO59
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602ec
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO59, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO59, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO59, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO59 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio60_cfg
Multiplexmatrix Configuration Register for MOT_MMIO60
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602f0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO60, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO60, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO60, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO60 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio61_cfg
Multiplexmatrix Configuration Register for MOT_MMIO61
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602f4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO61, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO61, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO61, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO61 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio62_cfg
Multiplexmatrix Configuration Register for MOT_MMIO62
-------------------------------
Some bits of this register is protected by the netX access-key mechanism; changing this register is only possible by the following sequence:
1.: read out access-key from asic_ctrl_access_key register
2.: write back access-key to asic_ctrl_access_key register
3.: write desired value to this register
-------------------------------
Core-inputs not mapped to any MOT_MMIO will be assigned to 0.
If one core-connection is mapped to more than one MOT_MMIO, the core-input-state will be these ored MOT_MMIO-states.
R/W
0x00000000
Address : 0x400602f8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 -
status_in_ro
current input status of MOT_MMIO62, could also be read from 'mot_mmio_in_line_status' register
17 "0"
pio_out
PIO mode output drive level of MOT_MMIO62, could also be programmd by 'mot_mmio_pio_out_line_cfg' register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_out_line_cfg register'.
16 "0"
pio_oe
PIO mode output enable of MOT_MMIO62, could also be programmd by mot_mmio_pio_oe_line_cfg register (not protected)
Changing this bit will also change according bit in 'mot_mmio_pio_oe_line_cfg register'.
15 - 11 0
-
 reserved
10 "0"
mot_mmio_in_inv
1: invert input signal; 0: keep original signal polarity (access-key-protected)
9 "0"
mot_mmio_out_inv
1: invert output signal; 0: keep original signal polarity (access-key-protected)
8 - 7 0
-
 reserved
6 - 0 "0000000"
mot_mmio_sel
MOT_MMIO62 signal selection (default: PIO mode, access-key-protected).
For select coding view descrition at adr_mot_mmio0_cfg


mot_mmio_pio_out_line_cfg0
MOT_MMIO PIO line output level register of MOT_MMIO0 to MOT_MMIO31.
Changing bits here will change 'pio_out' bit of related mot_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x400602fc
Bits Reset value Name Description
31 - 0 0x0
line
Output state if related MOT_MMIO is in PIO mode.
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.


mot_mmio_pio_out_line_cfg1
MOT_MMIO PIO line output level register of MOT_MMIO32 to MOT_MMIO62.
Changing bits here will change 'pio_out' bit of related mot_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060300
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Output state if related MOT_MMIO is in PIO mode.
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.


mot_mmio_pio_out_line_set_cfg0
MOT_MMIO PIO line output level set register of MOT_MMIO0 to MOT_MMIO31.
This register is for setting single MOT_MMIO PIOs to high level with a single access. In contrast to using the 'mot_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'mot_mmio*_cfg' register and also activate
the related bits in the 'mot_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'mot_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060304
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related MOT_MMIO output to high level (when it is in PIO mode and output is enabled).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.
For read the current value of the programmed output states is returned (i.e. the value of mot_mmio_pio_out_line_cfg0).


mot_mmio_pio_out_line_set_cfg1
MOT_MMIO PIO line output level set register of MOT_MMIO32 to MOT_MMIO62.
This register is for setting single MOT_MMIO PIOs to high level with a single access. In contrast to using the 'mot_mmio_pio_out_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_out' bit of related 'mot_mmio*_cfg' register and also activate
the related bits in the 'mot_mmio_pio_out_line_cfg1' register.
For read this register returns the same value as the 'mot_mmio_pio_out_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060308
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Write '1's to set the related MOT_MMIO output to high level (when it is in PIO mode and output is enabled).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.
For read the current value of the programmed output states is returned (i.e. the value of mot_mmio_pio_out_line_cfg1).


mot_mmio_pio_out_line_reset_cfg0
MOT_MMIO PIO line output level reset register of MOT_MMIO0 to MOT_MMIO31.
This register is for deactivating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_out_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'mot_mmio*_cfg' register and also clear
the related bits in the 'mot_mmio_pio_out_line_cfg0' register.
For read this register returns the same value as the 'mot_mmio_pio_out_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4006030c
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to set the related MOT_MMIO output to low level (when it is in PIO mode and output is enabled).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.
For read the current value of the programmed output states is returned (i.e. the value of mot_mmio_pio_out_line_cfg0).


mot_mmio_pio_out_line_reset_cfg1
MOT_MMIO PIO line output level reset register of MOT_MMIO32 to MOT_MMIO62.
This register is for deactivating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_out_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_out' bit of related 'mot_mmio*_cfg' register and also clear
the related bits in the 'mot_mmio_pio_out_line_cfg1' register.
For read this register returns the same value as the 'mot_mmio_pio_out_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060310
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Write '1's to set the related MOT_MMIO output to low level (when it is in PIO mode and output is enabled).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.
For read the current value of the programmed output states is returned (i.e. the value of mot_mmio_pio_out_line_cfg1).


mot_mmio_pio_oe_line_cfg0
MOT_MMIO PIO line output enable register of MOT_MMIO0 to MOT_MMIO31.
Changing bits here will change 'pio_oe' bit of related mot_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060314
Bits Reset value Name Description
31 - 0 0x0
line
Output enable if related MOT_MMIO is in PIO mode.
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.


mot_mmio_pio_oe_line_cfg1
MOT_MMIO PIO line output enable register of MOT_MMIO32 to MOT_MMIO62.
Changing bits here will change 'pio_oe' bit of related mot_mmio*_cfg register. Changes there will change related bit inside this register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060318
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Output enable if related MOT_MMIO is in PIO mode.
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.


mot_mmio_pio_oe_line_set_cfg0
MOT_MMIO PIO line output enable set register of MOT_MMIO0 to MOT_MMIO31.
This register is for activating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'mot_mmio*_cfg' register and also activate
the related bits in the 'mot_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'mot_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x4006031c
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to activate the related MOT_MMIO output enable (when it is in PIO mode).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.
For read the current value of the programmed output enables is returned (i.e. the value of mot_mmio_pio_oe_line_cfg0).


mot_mmio_pio_oe_line_set_cfg1
MOT_MMIO PIO line output enable set register of MOT_MMIO32 to MOT_MMIO62.
This register is for activating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_oe_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will activate the 'pio_oe' bit of related 'mot_mmio*_cfg' register and also activate
the related bits in the 'mot_mmio_pio_oe_line_cfg1' register.
For read this register returns the same value as the 'mot_mmio_pio_oe_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060320
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Write '1's to activate the related MOT_MMIO output enable (when it is in PIO mode).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.
For read the current value of the programmed output enables is returned (i.e. the value of mot_mmio_pio_oe_line_cfg1).


mot_mmio_pio_oe_line_reset_cfg0
MOT_MMIO PIO line output enable reset register of MOT_MMIO0 to MOT_MMIO31.
This register is for deactivating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_oe_line_cfg0' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'mot_mmio*_cfg' register and also clear
the related bits in the 'mot_mmio_pio_oe_line_cfg0' register.
For read this register returns the same value as the 'mot_mmio_pio_oe_line_cfg0' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060324
Bits Reset value Name Description
31 - 0 0x0
line
Write '1's to clear the related MOT_MMIO output enable (when it is in PIO mode).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO0, bit 1 controls MOT_MMIO1, ... bit 31 controlls MOT_MMIO31.
For read the current value of the programmed output enables is returned (i.e. the value of mot_mmio_pio_oe_line_cfg0).


mot_mmio_pio_oe_line_reset_cfg1
MOT_MMIO PIO line output enable reset register of MOT_MMIO32 to MOT_MMIO62.
This register is for deactivating single MOT_MMIO PIOs with a single access. In contrast to using the 'mot_mmio_pio_oe_line_cfg1' register
no read-modify-write sequence (which could be interrupted) is required.
Writing '1's here will clear the 'pio_oe' bit of related 'mot_mmio*_cfg' register and also clear
the related bits in the 'mot_mmio_pio_oe_line_cfg1' register.
For read this register returns the same value as the 'mot_mmio_pio_oe_line_cfg1' register.
Note: This register is not protected by netX access-key algorithm.
R/W
0x00000000
Address : 0x40060328
Bits Reset value Name Description
31 0
-
 reserved
30 - 0 0x0
line
Write '1's to clear the related MOT_MMIO output enable (when it is in PIO mode).
If related MOT_MMIO is not in PIO mode, programmed setting is ignored.
Bit 0 controls MOT_MMIO32, bit 1 controls MOT_MMIO33, ... bit 30 controlls MOT_MMIO62.
For read the current value of the programmed output enables is returned (i.e. the value of mot_mmio_pio_oe_line_cfg1).


mot_mmio_in_line_status0
MOT_MMIO input line register of MOT_MMIO0 to MOT_MMIO31.
R
Address : 0x4006032c
Bits Name Description
31 - 0 line
sampled MOT_MMIO input state.
Does not depend whether MOT_MMIO is in PIO mode or not.
Bit 0 monitors MOT_MMIO0, Bit 1 monitors MOT_MMIO1, ... bit 31 monitors MOT_MMIO31.


mot_mmio_in_line_status1
MOT_MMIO input line register of MOT_MMIO32 to MOT_MMIO62.
R
Address : 0x40060330
Bits Name Description
31 -
 reserved
30 - 0 line
sampled MOT_MMIO input state.
Does not depend whether MOT_MMIO is in PIO mode or not.
Bit 0 monitors MOT_MMIO32, Bit 1 monitors MOT_MMIO33, ... bit 30 monitors MOT_MMIO62.


mot_mmio_is_pio_status0
MOT_MMIO mode line register of MOT_MMIO0 to MOT_MMIO31.
Note: PIO Mode can be enabled or disabled in mot_mmio_cfg registers.
R
Address : 0x40060334
Bits Name Description
31 - 0 line
Bit 0 shows status of MOT_MMIO0, Bit 1 shows status of  MOT_MMIO1, ... bit 31 shows MOT_MMIO31.
If the MOT_MMIO is the standard function of the netX IO (i.e. the netX pin name is MOT_MMIO*), the bit of the
related MOT_MMIO shows whether the MOT_MMIO is in PIO mode or not.
If the MOT_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than MOT_MMIO*), a PIO function is not
available by the MOT_MMIO function. In this case the bit of the related MOT_MMIO shows whether the MOT_MMIO function is selected or not.
 The related MOT_MMIO is a standar d-   Val ue   Status
 function MOT_MMIO (netX MOT_MMIO*  port)  
               yes    0  The related MOT_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related MOT_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The MOT_MMIO function of the netX IO is selected and assigned to a MOT_MMIO core functionality.
               no    1  The MOT_MMIO function of the related netX IO is not selected.

Note: When the MOT_MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the MOT_MMIO function.


mot_mmio_is_pio_status1
MOT_MMIO mode line register of MOT_MMIO32 to MOT_MMIO62.
Note: PIO Mode can be enabled or disabled in mot_mmio_cfg registers.
R
Address : 0x40060338
Bits Name Description
31 -
 reserved
30 - 0 line
Bit 0 shows status of MOT_MMIO32, Bit 1 shows status of  MOT_MMIO33, ... bit 30 shows MOT_MMIO62.
If the MOT_MMIO is the standard function of the netX IO (i.e. the netX pin name is MOT_MMIO*), the bit of the
related MOT_MMIO shows whether the MOT_MMIO is in PIO mode or not.
If the MOT_MMIO is a multiplex function of a netX IO (i.e. the netX pin name is another than MOT_MMIO*), a PIO function is not
available by the MOT_MMIO function. In this case the bit of the related MOT_MMIO shows whether the MOT_MMIO function is selected or not.
 The related MOT_MMIO is a standar d-   Val ue   Status
 function MOT_MMIO (netX MOT_MMIO*  port)  
               yes    0  The related MOT_MMIO is not in PIO mode (is assigned to core functionality).
               yes    1  The related MOT_MMIO is in PIO mode (is not assigned to core functionality).
               no    0  The MOT_MMIO function of the netX IO is selected and assigned to a MOT_MMIO core functionality.
               no    1  The MOT_MMIO function of the related netX IO is not selected.

Note: When the MOT_MMIO function is selected it could be possible that also another IO multiplex function is
   activated (e.g. by global IO-configuration registers 'io_config'). This function could have higher priority
   in global IO multiplexing and could deselect the MOT_MMIO function.



Base Address Area: secenc_asic_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W secenc_asic_ctrl_protect_com_intram0_0
1 4 R/W secenc_asic_ctrl_protect_com_intram0_1
2 8 R/W secenc_asic_ctrl_protect_com_intram2_0
3 c R/W secenc_asic_ctrl_protect_com_intram2_1
4-3f 10-fc -  reserved

secenc_asic_ctrl_protect_com_intram0_0
Enable secure-only accesses for 16kB regions in the com_intram0, lower 32 regions
Non-secure accesses in a secure_only region will result in an error response on the AXI bus
R/W
0x00000000
Address : 0x40070000
Bits Reset value Name Description
31 - 0 0x0
secure_only
bit N corresponds to region N (ascending)
e.g. bit 1 marks region from addr 0x04000 to 0x08000 as secure-only


secenc_asic_ctrl_protect_com_intram0_1
Enable secure-only accesses for 16kB regions in the com_intram0, upper 32 regions
Non-secure accesses in a secure_only region will result in an error response on the AXI bus
R/W
0x00000000
Address : 0x40070004
Bits Reset value Name Description
31 - 0 0x0
secure_only
bit N corresponds to region N+32 (ascending)
e.g. bit 1 marks region from addr 0x84000 to 0x88000 as secure-only


secenc_asic_ctrl_protect_com_intram2_0
Enable secure-only accesses for 16kB regions in the com_intram2, lower 32 regions
Non-secure accesses in a secure_only region will result in an error response on the AXI bus
R/W
0x00000000
Address : 0x40070008
Bits Reset value Name Description
31 - 0 0x0
secure_only
bit N corresponds to region N (ascending)
e.g. bit 1 marks region from addr 0x04000 to 0x08000 as secure-only


secenc_asic_ctrl_protect_com_intram2_1
Enable secure-only accesses for 16kB regions in the com_intram2, upper 32 regions
Non-secure accesses in a secure_only region will result in an error response on the AXI bus
R/W
0x00000000
Address : 0x4007000c
Bits Reset value Name Description
31 - 0 0x0
secure_only
bit N corresponds to region N+32 (ascending)
e.g. bit 1 marks region from addr 0x84000 to 0x88000 as secure-only



Base Address Area: app_biss0, app_biss1, mot_biss0, mot_biss1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W biss_scdata0_0
1 4 R/W biss_scdata0_1
2 8 R/W biss_scdata1_0
3 c R/W biss_scdata1_1
4 10 R/W biss_scdata2_0
5 14 R/W biss_scdata2_1
6 18 R/W biss_scdata3_0
7 1c R/W biss_scdata3_1
8 20 R/W biss_scdata4_0
9 24 R/W biss_scdata4_1
a 28 R/W biss_scdata5_0
b 2c R/W biss_scdata5_1
c 30 R/W biss_scdata6_0
d 34 R/W biss_scdata6_1
e 38 R/W biss_scdata7_0
f 3c R/W biss_scdata7_1
10-1f 40-7c -  reserved
20 80 R/W biss_rdata0
21 84 R/W biss_rdata1
22 88 R/W biss_rdata2
23 8c R/W biss_rdata3
24 90 R/W biss_rdata4
25 94 R/W biss_rdata5
26 98 R/W biss_rdata6
27 9c R/W biss_rdata7
28 a0 R/W biss_rdata8
29 a4 R/W biss_rdata9
2a a8 R/W biss_rdata10
2b ac R/W biss_rdata11
2c b0 R/W biss_rdata12
2d b4 R/W biss_rdata13
2e b8 R/W biss_rdata14
2f bc R/W biss_rdata15
30 c0 R/W biss_sc0
31 c4 R/W biss_sc1
32 c8 R/W biss_sc2
33 cc R/W biss_sc3
34 d0 R/W biss_sc4
35 d4 R/W biss_sc5
36 d8 R/W biss_sc6
37 dc R/W biss_sc7
38 e0 R/W biss_ccc0
39 e4 R/W biss_ccc1_mc0
3a e8 R/W biss_mc1
3b ec R/W biss_cc_sl
3c f0 R biss_status0
3d f4 R/W biss_ir
3e f8 R biss_status1
3f fc -  reserved

biss_scdata0_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080000
Address@app_biss1 : 0x40080100
Address@mot_biss0 : 0x49200000
Address@mot_biss1 : 0x49200100
Bits Reset value Name Description
31 - 0 0x0
SCDATA0_0
Slave0 (SCD)single cycle data[31:0]


biss_scdata0_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080004
Address@app_biss1 : 0x40080104
Address@mot_biss0 : 0x49200004
Address@mot_biss1 : 0x49200104
Bits Reset value Name Description
31 - 0 0x0
SCDATA0_1
Slave0 (SCD)single cycle data[63:32]


biss_scdata1_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080008
Address@app_biss1 : 0x40080108
Address@mot_biss0 : 0x49200008
Address@mot_biss1 : 0x49200108
Bits Reset value Name Description
31 - 0 0x0
SCDATA1_0
Slave1 (SCD)single cycle data[31:0]


biss_scdata1_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x4008000c
Address@app_biss1 : 0x4008010c
Address@mot_biss0 : 0x4920000c
Address@mot_biss1 : 0x4920010c
Bits Reset value Name Description
31 - 0 0x0
SCDATA1_1
Slave1 (SCD)single cycle data[63:32]


biss_scdata2_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080010
Address@app_biss1 : 0x40080110
Address@mot_biss0 : 0x49200010
Address@mot_biss1 : 0x49200110
Bits Reset value Name Description
31 - 0 0x0
SCDATA2_0
Slave2 (SCD)single cycle data[31:0]


biss_scdata2_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080014
Address@app_biss1 : 0x40080114
Address@mot_biss0 : 0x49200014
Address@mot_biss1 : 0x49200114
Bits Reset value Name Description
31 - 0 0x0
SCDATA2_1
Slave2 (SCD)single cycle data[63:32]


biss_scdata3_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080018
Address@app_biss1 : 0x40080118
Address@mot_biss0 : 0x49200018
Address@mot_biss1 : 0x49200118
Bits Reset value Name Description
31 - 0 0x0
SCDATA3_0
Slave3 (SCD)single cycle data[31:0]


biss_scdata3_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x4008001c
Address@app_biss1 : 0x4008011c
Address@mot_biss0 : 0x4920001c
Address@mot_biss1 : 0x4920011c
Bits Reset value Name Description
31 - 0 0x0
SCDATA3_1
Slave3 (SCD)single cycle data[63:32]


biss_scdata4_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080020
Address@app_biss1 : 0x40080120
Address@mot_biss0 : 0x49200020
Address@mot_biss1 : 0x49200120
Bits Reset value Name Description
31 - 0 0x0
SCDATA4_0
Slave4 (SCD)single cycle data[31:0]


biss_scdata4_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080024
Address@app_biss1 : 0x40080124
Address@mot_biss0 : 0x49200024
Address@mot_biss1 : 0x49200124
Bits Reset value Name Description
31 - 0 0x0
SCDATA4_1
Slave4 (SCD)single cycle data[63:32]


biss_scdata5_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080028
Address@app_biss1 : 0x40080128
Address@mot_biss0 : 0x49200028
Address@mot_biss1 : 0x49200128
Bits Reset value Name Description
31 - 0 0x0
SCDATA5_0
Slave5 (SCD)single cycle data[31:0]


biss_scdata5_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x4008002c
Address@app_biss1 : 0x4008012c
Address@mot_biss0 : 0x4920002c
Address@mot_biss1 : 0x4920012c
Bits Reset value Name Description
31 - 0 0x0
SCDATA5_1
Slave5 (SCD)single cycle data[63:32]


biss_scdata6_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080030
Address@app_biss1 : 0x40080130
Address@mot_biss0 : 0x49200030
Address@mot_biss1 : 0x49200130
Bits Reset value Name Description
31 - 0 0x0
SCDATA6_0
Slave6 (SCD)single cycle data[31:0]


biss_scdata6_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080034
Address@app_biss1 : 0x40080134
Address@mot_biss0 : 0x49200034
Address@mot_biss1 : 0x49200134
Bits Reset value Name Description
31 - 0 0x0
SCDATA6_1
Slave6 (SCD)single cycle data[63:32]


biss_scdata7_0
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x40080038
Address@app_biss1 : 0x40080138
Address@mot_biss0 : 0x49200038
Address@mot_biss1 : 0x49200138
Bits Reset value Name Description
31 - 0 0x0
SCDATA7_0
Slave0 (SCD)single cycle data[31:0]


biss_scdata7_1
Sensor and Actuator Data
R/W
0x00000000
Address@app_biss0 : 0x4008003c
Address@app_biss1 : 0x4008013c
Address@mot_biss0 : 0x4920003c
Address@mot_biss1 : 0x4920013c
Bits Reset value Name Description
31 - 0 0x0
SCDATA7_1
Slave7 (SCD)single cycle data[63:32]


biss_rdata0
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080080
Address@app_biss1 : 0x40080180
Address@mot_biss0 : 0x49200080
Address@mot_biss1 : 0x49200180
Bits Reset value Name Description
31 - 0 0x0
RDATA0
- Using register access in control communication
  RDATA0: register data DWord0
- Using command/instructions in control communication
  IDS: ID-Select, command/instruction addressing combinable


biss_rdata1
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080084
Address@app_biss1 : 0x40080184
Address@mot_biss0 : 0x49200084
Address@mot_biss1 : 0x49200184
Bits Reset value Name Description
31 - 0 0x0
RDATA1
register data DWord1


biss_rdata2
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080088
Address@app_biss1 : 0x40080188
Address@mot_biss0 : 0x49200088
Address@mot_biss1 : 0x49200188
Bits Reset value Name Description
31 - 0 0x0
RDATA2
register data DWord2


biss_rdata3
Register Data
R/W
0x00000000
Address@app_biss0 : 0x4008008c
Address@app_biss1 : 0x4008018c
Address@mot_biss0 : 0x4920008c
Address@mot_biss1 : 0x4920018c
Bits Reset value Name Description
31 - 0 0x0
RDATA3
register data DWord3


biss_rdata4
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080090
Address@app_biss1 : 0x40080190
Address@mot_biss0 : 0x49200090
Address@mot_biss1 : 0x49200190
Bits Reset value Name Description
31 - 0 0x0
RDATA4
register data DWord4


biss_rdata5
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080094
Address@app_biss1 : 0x40080194
Address@mot_biss0 : 0x49200094
Address@mot_biss1 : 0x49200194
Bits Reset value Name Description
31 - 0 0x0
RDATA5
register data DWord5


biss_rdata6
Register Data
R/W
0x00000000
Address@app_biss0 : 0x40080098
Address@app_biss1 : 0x40080198
Address@mot_biss0 : 0x49200098
Address@mot_biss1 : 0x49200198
Bits Reset value Name Description
31 - 0 0x0
RDATA6
register data DWord6


biss_rdata7
Register Data
R/W
0x00000000
Address@app_biss0 : 0x4008009c
Address@app_biss1 : 0x4008019c
Address@mot_biss0 : 0x4920009c
Address@mot_biss1 : 0x4920019c
Bits Reset value Name Description
31 - 0 0x0
RDATA7
register data DWord7


biss_rdata8
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800a0
Address@app_biss1 : 0x400801a0
Address@mot_biss0 : 0x492000a0
Address@mot_biss1 : 0x492001a0
Bits Reset value Name Description
31 - 0 0x0
RDATA8
register data DWord8


biss_rdata9
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800a4
Address@app_biss1 : 0x400801a4
Address@mot_biss0 : 0x492000a4
Address@mot_biss1 : 0x492001a4
Bits Reset value Name Description
31 - 0 0x0
RDATA9
register data DWord9


biss_rdata10
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800a8
Address@app_biss1 : 0x400801a8
Address@mot_biss0 : 0x492000a8
Address@mot_biss1 : 0x492001a8
Bits Reset value Name Description
31 - 0 0x0
RDATA10
register data DWord10


biss_rdata11
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800ac
Address@app_biss1 : 0x400801ac
Address@mot_biss0 : 0x492000ac
Address@mot_biss1 : 0x492001ac
Bits Reset value Name Description
31 - 0 0x0
RDATA11
register data DWord11


biss_rdata12
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800b0
Address@app_biss1 : 0x400801b0
Address@mot_biss0 : 0x492000b0
Address@mot_biss1 : 0x492001b0
Bits Reset value Name Description
31 - 0 0x0
RDATA12
register data DWord12


biss_rdata13
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800b4
Address@app_biss1 : 0x400801b4
Address@mot_biss0 : 0x492000b4
Address@mot_biss1 : 0x492001b4
Bits Reset value Name Description
31 - 0 0x0
RDATA13
register data DWord13


biss_rdata14
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800b8
Address@app_biss1 : 0x400801b8
Address@mot_biss0 : 0x492000b8
Address@mot_biss1 : 0x492001b8
Bits Reset value Name Description
31 - 0 0x0
RDATA14
register data DWord14


biss_rdata15
Register Data
R/W
0x00000000
Address@app_biss0 : 0x400800bc
Address@app_biss1 : 0x400801bc
Address@mot_biss0 : 0x492000bc
Address@mot_biss1 : 0x492001bc
Bits Reset value Name Description
31 - 0 0x0
RDATA15
register data DWord15


biss_sc0
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800c0
Address@app_biss1 : 0x400801c0
Address@mot_biss0 : 0x492000c0
Address@mot_biss1 : 0x492001c0
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART0
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS0
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY0
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP0
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD0
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN0
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc1
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800c4
Address@app_biss1 : 0x400801c4
Address@mot_biss0 : 0x492000c4
Address@mot_biss1 : 0x492001c4
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART1
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS1
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY1
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP1
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD1
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN1
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc2
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800c8
Address@app_biss1 : 0x400801c8
Address@mot_biss0 : 0x492000c8
Address@mot_biss1 : 0x492001c8
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART2
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS2
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY2
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP2
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD2
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN2
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc3
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800cc
Address@app_biss1 : 0x400801cc
Address@mot_biss0 : 0x492000cc
Address@mot_biss1 : 0x492001cc
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART3
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS3
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY3
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP3
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD3
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN3
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc4
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800d0
Address@app_biss1 : 0x400801d0
Address@mot_biss0 : 0x492000d0
Address@mot_biss1 : 0x492001d0
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART4
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS4
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY4
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP4
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD4
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN4
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc5
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800d4
Address@app_biss1 : 0x400801d4
Address@mot_biss0 : 0x492000d4
Address@mot_biss1 : 0x492001d4
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART5
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS5
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY5
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP5
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD5
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN5
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc6
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800d8
Address@app_biss1 : 0x400801d8
Address@mot_biss0 : 0x492000d8
Address@mot_biss1 : 0x492001d8
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART6
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS6
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY6
- SELCRCx == 0 ( SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP6
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSCD6
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN6
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_sc7
Slave Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800dc
Address@app_biss1 : 0x400801dc
Address@mot_biss0 : 0x492000dc
Address@mot_biss1 : 0x492001dc
Bits Reset value Name Description
31 - 16 0x0
SCRCSTART7
Start value for polynomial SCD CRC calculation
15 "0"
SELCRCS7
Selection between polynomial or length for SCD CRC polynomial
0: CRC bit length in SCRCLENx (see SCRCPOLYx) apply dedicated CRC polynomials
1: CRC polynomial(7:1) in SCRCPOLYx. SELCRCSx = 1 not applicable with CRC polynomial SCRCPOLYx(7:0) = 0x00
14 - 8 "0000000"
SCRCPOLY7
- SELCRCx == 0 (SCRCLENx: polynomial selection by length for SCD CRC check)
   0: CRC for single cycle data not present, CRC verification deactivated. SELCRCSx = 0b0
   3: CRC polynomial = 0x0b
   4: CRC polynomial = 0x13
   5: CRC polynomial = 0x25
   6: CRC polynomial = 0x43
   7: CRC polynomial = 0x89
   8: CRC polynomial = 0x12f
  16: CRC polynomial = 0x190d9
  ..: other CRC length are not permitted with SELCRCSx = 0
- SELCRCx == 1 (SCRCPOLYx: polynomial for SCD CRC check)
  0x00       : CRC polynomial 0x00 not applicable with SELCRCSx = 1
  0x01.. 0x7f: CRC polynomial for single cycle data = SCRCPOLYx(7:1) + 0x01
7 "0"
LSTOP7
- BISS mode(LSTOPx = Actuator stop bit control)
  0: no leading STOP bit on single cycle actuator data
  1: leading STOP bit on single cycle actuator data
- SSI mode(GRAYSx = Enable SCD gray to binary conversion)
  0: SSI single cycle data binary coded
  1: SSI single cycle data gray coded
6 "0"
ENSC7
Enable single cycle data
0: single cycle data not available
1: single cycle data available
5 - 0 "000000"
SCDLEN7
Single cycle data length
0 : single cycle data length = 1
1 : single cycle data length = 2
... single cycle data length = SCDLENx + 1
62: single cycle data length = 63
63: single cycle data length = 64


biss_ccc0
Register Communication Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800e0
Address@app_biss1 : 0x400801e0
Address@mot_biss0 : 0x492000e0
Address@mot_biss1 : 0x492001e0
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 24 "000000"
REGNUM
Register data count
0x00       : register count = 1
0x01 ..0x3f: register count = REGNUM(5:0)+1
23 "0"
WNR
Register access read/write selector
0: read register data
1: write register data
22 - 16 "0000000"
REGADR
Register access start address 0x00 .. 0x7f
15 - 0 0
-
 reserved


biss_ccc1_mc0
Register Communication Configuration / Master Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800e4
Address@app_biss1 : 0x400801e4
Address@mot_biss0 : 0x492000e4
Address@mot_biss1 : 0x492001e4
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
NOCRC
CRC for SCD not to be stored in RAM
0: CRC of SCD is stored RAM (only applicable with active CRC verification and CRC polynome > 0)
1: CRC of SCD not to be stored in RAM
24 "0"
SINGLEBANK
Use of only one RAM bank for SCD
0: two RAM banks are used for SCD
1: one RAM bank is used for SCD
23 - 21 "000"
FREQR
Frequency division register communication BiSS B
0 .. 7: freqSens/(2*(FREQ(7:5)+1))
0: FreqSens/2
1: FreqSens/4
2: FreqSens/8
3: FreqSens/16
4: FreqSens/32
5: FreqSens/64
6: FreqSens/128
7: FreqSens/256
20 - 16 "00000"
FREQS
Frequency division
0x00: fCLK/2
0x01: fCLK/4
0x02: fCLK/6
0x03: fCLK/8
...
0x09: fCLK/20
...
0x0d: fCLK/28
0x0e: fCLK/30
0x0f: fCLK/32
0x10: not permitted
0x11: fCLK/40
0x12: fCLK/60
0x13: fCLK/80
...
0x1d: fCLK/280
0x1e: fCLK/300
0x1f: fCLK/320
15 "0"
CTS
Register transmission or instruction selector
0: command/instruction communication
1: register communication
14 "0"
REGVERS
BiSS model A/B or C selector
- Using register access in control communication
  0: register communication BiSS A/B
  1: register communication BiSS C
- Using command/instructions in control communication
  0: not applicable with command/instruction communication
  1: command communication BiSS C
13 - 12 "00"
CMD
- Using register access in control communication
  SLAVEID[2:1]: slave selector bit2_1
- Using command/instructions in control communication
  Command of access slave     # default 0x00
  0x00 .. 0x03: command/instruction 0b00 .. 0b11
11 "0"
IDA_TEST
- Using register access in control communication
  SLAVEID[0]: slave selector bit0
- Using command/instructions in control communication
  IDA_TEST: command/instruction execution control
  0: the slaves feedback (IDA) is tested before execution (EX bit after IDA)
  1: immediate execution
10 0
-
 reserved
9 "0"
EN_MO
Enable output at MOx for actuator data or delayed start bit
0: MO forced to low
1: Parameterized processing time by master on MO signal active (length: MO_BUSY)
8 "0"
HOLDCDM
Hold CDM(control data master)
0: clock line high at end of cycle
1: clock line constant with CDM bit until start of next cycle
7 - 2 0
-
 reserved
1 - 0 "00"
CHSEL
Channel selector
0: channel 1 used for control communication, channel 2 not used
1: channel 1 used for control communication, channel 2 not used
2: channel 2 used for control communication, channel 1 not used. Note: Channel 2 is not available with IC-MB4 TSSOP24
3: channel 1,2 used for control communication. Note: Channel 2 is not available with IC-MB4 TSSOP24


biss_mc1
Master Configuration
R/W
0x00000000
Address@app_biss0 : 0x400800e8
Address@app_biss1 : 0x400801e8
Address@mot_biss0 : 0x492000e8
Address@mot_biss1 : 0x492001e8
Bits Reset value Name Description
31 - 24 "00000000"
VERSION
Device identifier
0x83: iC-MB3
0x84: iC-MB4
.. 0xff
23 - 16 "00000000"
REVISION
Revision
0x10: Z(first revision)
0x11: Z1
0x12: Y
.. 0xff
15 - 8 "00000000"
MO_BUSY
Delay of start bit at output MOx
0x00 .. 0xff: count of MA clocks as the parameterized processing time by master on MO signal
Premise: EN_MO = 1
7 - 0 "00000000"
FREQAGS
AutoGetSens Frequency division
0x00.. 0x7b: fCLK/(20*(FREQAGS(6:0)+1))
0x7c       : AGSMIN( the master automatically restarts the next cycle after the prior was finished. AGSMIN is the fastest SCD rate with complete SCD cycles. )
0x7d.. 0x7f: AGSINFINITE( the master does not automatically restart the next cycle after the prior one was finished. AGSINFINITE requires a trigger event to start the next SCD cycle. )
0x80.. 0xff: fCLK/(625*(FREQAGS(6:0)+1))


biss_cc_sl
Channel Configuration
R/W
0x00000001
Address@app_biss0 : 0x400800ec
Address@app_biss1 : 0x400801ec
Address@mot_biss0 : 0x492000ec
Address@mot_biss1 : 0x492001ec
Bits Reset value Name Description
31 - 24 "00000000"
ACTnSENS
Sensor or actuator data selector
0x00: all slaves are sensors
0x01: slave 0 is actuator
0x02: slave 1 is actuator
0x04: slave 2 is actuator
0x08: slave 3 is actuator
0x10: slave 4 is actuator
0x20: slave 5 is actuator
0x40: slave 6 is actuator
0x80: slave 7 is actuator
0xff: all slaves are actuators
23 - 12 0
-
 reserved
11 - 10 "00"
CFGCH2
Channel 2 configuration
0x00: BiSS B
0x01: BiSS C
0x02: SSI
0x03: channel is not used
9 - 8 "00"
CFGCH1
Channel 1 configuration
0x00: BiSS B
0x01: BiSS C
0x02: SSI
0x03: channel is not used
7 - 5 0
-
 reserved
4 "0"
SLAVELOC5
Slave location
0: slaves 4-7 are connected to channel 1
1: slaves 4-7 are connected to channel 2(only available with iC-MB4 QFN28)
3 - 0 "0001"
cc_sl_reserved1



biss_status0
Status Information
R
Address@app_biss0 : 0x400800f0
Address@app_biss1 : 0x400801f0
Address@mot_biss0 : 0x492000f0
Address@mot_biss1 : 0x492001f0
Bits Name Description
31 CDMTIMEOUT
CDM(Control Data Master) timeout reached
0: CDMTIMEOUT not reached
1: CDMTIMEOUT reached
30 CDSSEL
CDS(Control Data Slave) bit from the selected channel
29 - 24 REGBYTES
Number of valid register data transmission in case of error
0x00       : after transfer: no register communication error
0x01 . 0x3f: after transfer: number of successfully transferred registers before register communication error
23 SVALID7
SCDATA7 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
22 -
 reserved
21 SVALID6
SCDATA6 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
20 -
 reserved
19 SVALID5
SCDATA5 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
18 -
 reserved
17 SVALID4
SCDATA4 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
16 -
 reserved
15 SVALID3
SCDATA3 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
14 -
 reserved
13 SVALID2
SCDATA2 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
12 -
 reserved
11 SVALID1
SCDATA1 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
10 -
 reserved
9 SVALID0
SCDATA0 validity indication
0: SCD invalid
1: SCD valid
The SVALIDx bit indicates the validity of each slaves SCD CRC verification. A prior set SVALIDx bit can be reset by writing 0 into the register.
8 -
 reserved
7 nERR
Transmission error (error at NER pin)
0: error
1: no error
It is possible to connect other components to pin NER which can also generate an error message; this can then be read out via this bit.
6 nAGSERR
AGS error
0: AGS(Automatic Get Sensor data) watchdog error
1: no AGS watchdog error
An AGS watchdog error is set during the automatic transmission of sensor data if no new cycle could be initiated; bit AGS in the command register is reset and the automatic request of sensor data aborted.
5 nDELAYERR
Missing start bit during register communication
0: delay error
1: no delay error
4 nSCDERR
Error in single cycle data transmission
0: error in last single cycle data transmission
1: no error in last single cycle data transmission
3 nREGERR
Error in register data transmission
0: error in last register data transmission
1: no error in last register data transmission
2 REGEND
Register data transmission completed
0: no valid register data available
1: register data transmission completed
1 status0_reserved1
reserved
0 EOT
Data transmission completed
0: data transmission active
1: data transmission finished


biss_ir
Instruction Register
R/W
0x00000000
Address@app_biss0 : 0x400800f4
Address@app_biss1 : 0x400801f4
Address@mot_biss0 : 0x492000f4
Address@mot_biss1 : 0x492001f4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
MAVO
Not selected MA line control level
0: low definition of unselected(CHSEL) MA clock lines
1: high definition of unselected(CHSEL) MA clock lines
14 "0"
MAFO
Not selected MA line control selection
0: controlling unselected(CHSEL) MA clock line: using MA signal
1: controlling unselected(CHSEL) MA clock line: using MAVS level
13 "0"
MAVS
Selected MA line control level
0: low definition of selected(CHSEL) MA clock lines
1: high definition of selected(CHSEL) MA clock lines
12 "0"
MAFS
Selected MA line control selection
0: controlling selected/CHSEL) MA clock line: using MA signal
1: controlling selected(CHSEL) MA clock line: using MAVS level
11 - 10 "00"
CFGIF
Configure physical interface
0x00: TTL
0x01: CMOS
0x02: RS422
0x03: LVDS
9 "0"
ENTEST
Enable test interface
0: device in normal operation mode
1: device in test mode
8 "0"
CLKENI
Enable internal clock
0: the master clock is generated by an external clock oscillator
1: the master clock is generated by the basic clock of the internal 20MHz oscillator
7 "0"
BREAK
Data transmission interrupt
0: no change
1:
abort data transmission
nSCDERR, nREGERR, nDELAYERR, nAGSERR = 1,
REGEND = 0
All current actions can be aborted using the BREAK command so that a defined state can be resumed if one of the sensors proves faulty, for example.
BREAK= 1 aborts the active data transmission and all status information will be reset.
6 "0"
HOLDBANK
RAM bank control
0: no bank switching lock permitted
1: bank switching lock permitted
During the readout of more than one sensor data register by the controller it is possible that the RAM banks in the master could be swapped over once a sensor data transmission is completed.
So that the controller only reads related values bit HOLDBANK should be set at the start of the readout and reset at the end; this suppresses the RAM swap.
With the start of a new sensor data cycle previous values are then overwritten by the new sensor data.
5 "0"
SWBANK
Switch RAM banks
0: RAM banks are not switched
1: RAM banks are switched
4 "0"
INIT
Start INIT sequence
0: no changes on the data channel
1: initialize data channel
3 - 1 "000"
INSTR
SCD control instruction
0b010       : CDM = 0
0b001       : CDM = 1
0b100, 0b110: register communication
              condition: CDMTIMEOUT = 1
0b111       : register communication(reduced protocol)
              condition: CDMTIMEOUT = 1
The transmission of sensor data can be triggered via INSTR. With INSTR=0b010 the ccle finishes with a CDM=0.
With INSTR= 0b001 the cycle finishes with a CDM=1. A BiSS C register access to a slave can be operated by INSTR=0b100.
A reduced protocol for a shorter BiSS C register access to a slave can be operated by INST=0b111.
0 "0"
AGS
AutoGetSens(Automatic Get Sensordata)
0: no automatic data transmission
1: - start of data transmission after TIMEOUTSENS
     condition: FREQAGS = AGSMIN
   - start of data transmission triggered by pin
     condition: FREQAGS = AGSINFINITE
   - start of data transmission after timeout
With AGS = 0 the master starts the data transmission after finishing writing the instruction register(rising edge of NWR).
A nAGSERR error will be generated if the SL line is low, TIMEOUTSENS has not exceeded. If an AGS bit has been set sensor data is read in
cyclically according to the cycle frequency set in FREQAGS.


biss_status1
Status Information
R
Address@app_biss0 : 0x400800f8
Address@app_biss1 : 0x400801f8
Address@mot_biss0 : 0x492000f8
Address@mot_biss1 : 0x492001f8
Bits Name Description
31 - 25 -
 reserved
24 SWBANKFAILS
Bank switching status
0: bank switching(SCD) successful
1: bank switching(SCD) not successful
23 - 2 -
 reserved
1 CDS1
CDS bit of channel 1
0: CDS = 0
1: CDS = 1
0 SL1
Current SL line level of channel 1
0: SL line level low
1: SL line level high



Base Address Area: app_biss_ctrl0, app_biss_ctrl1, mot_biss_ctrl0, mot_biss_ctrl1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W biss_ctrl_trigger_cfg
1 4 R/W biss_ctrl_trigger
2 8 R/W biss_ctrl_irq_raw
3 c R biss_ctrl_irq_masked
4 10 R/W biss_ctrl_irq_msk_set
5 14 R/W biss_ctrl_irq_msk_reset
6-7 18-1c -  reserved

biss_ctrl_trigger_cfg
BiSS trigger configuration
R/W
0x00000000
Address@app_biss_ctrl0 : 0x40080200
Address@app_biss_ctrl1 : 0x40080220
Address@mot_biss_ctrl0 : 0x49200200
Address@mot_biss_ctrl1 : 0x49200220
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
sel
Trigger source select
This bit field configures which event is connected to the GETSENS signal of the BiSS core. A rising edge of the selected event will generate an event to the core.
Value trigger event
0 none
1 manual
2 gxc_trigger_out0
3 gxc_trigger_out0 (inverted)
4 gxc_trigger_out1
5 gxc_trigger_out1 (inverted)
6 gxc_sample_in0
7 gxc_sample_in0 (inverted)
8 gxc_sample_in1
9 gxc_sample_in1 (inverted)
10 gxc_trigger_global_out0
11 gxc_trigger_global_out0 (inverted)
12 gxc_trigger_global_out1
13 gxc_trigger_global_out1 (inverted)
14 gxc_sample_global_in0
15 gxc_sample_global_in0 (inverted)
16 gxc_sample_global_in1
17 gxc_sample_global_in1 (inverted)
18 app_gpio_counter_zero0
19 app_gpio_counter_zero1
20 app_gpio_counter_zero2
21 app_gpio_counter_zero3
22 app_gpio_counter_zero4
23 app_gpio_counter_zero5
24 app_gpio_counter_zero6
25 app_gpio_counter_zero7
26-31 reserved


biss_ctrl_trigger
BiSS trigger
R/W
0x00000000
Address@app_biss_ctrl0 : 0x40080204
Address@app_biss_ctrl1 : 0x40080224
Address@mot_biss_ctrl0 : 0x49200204
Address@mot_biss_ctrl1 : 0x49200224
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
manual
Manual trigger.
Writing '1' to this bit will trigger the BiSS core immediately in case the trigger_cfg.sel bit field is set to manual mode and the BiSS core is setup for external triggering by the GETSENS signal.


biss_ctrl_irq_raw
BiSS raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@app_biss_ctrl0 : 0x40080208
Address@app_biss_ctrl1 : 0x40080228
Address@mot_biss_ctrl0 : 0x49200208
Address@mot_biss_ctrl1 : 0x49200228
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
err
Error signal from the BiSS core. Only a falling edge on the NER signal will set the interrupt.
0 "0"
eot
End-Of-Transmission signal from the BiSS core. Only a rising edge on the EOT signal will set the interrupt.


biss_ctrl_irq_masked
BiSS masked IRQ:
Shows status of masked IRQs.
R
Address@app_biss_ctrl0 : 0x4008020c
Address@app_biss_ctrl1 : 0x4008022c
Address@mot_biss_ctrl0 : 0x4920020c
Address@mot_biss_ctrl1 : 0x4920022c
Bits Name Description
31 - 2 -
 reserved
1 err
Error signal from the BiSS core.
0 eot
End-Of-Transmission signal from the BiSS core.


biss_ctrl_irq_msk_set
BiSS IRQ mask set:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to mtgy_irq_raw.
R/W
0x00000000
Address@app_biss_ctrl0 : 0x40080210
Address@app_biss_ctrl1 : 0x40080230
Address@mot_biss_ctrl0 : 0x49200210
Address@mot_biss_ctrl1 : 0x49200230
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
err
Error signal from the BiSS core.
0 "0"
eot
End-Of-Transmission signal from the BiSS core.


biss_ctrl_irq_msk_reset
BiSS IRQ mask reset:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address@app_biss_ctrl0 : 0x40080214
Address@app_biss_ctrl1 : 0x40080234
Address@mot_biss_ctrl0 : 0x49200214
Address@mot_biss_ctrl1 : 0x49200234
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
err
Error signal from the BiSS core.
0 "0"
eot
End-Of-Transmission signal from the BiSS core.



Base Address Area: app_endat0, app_endat1, mot_endat0, mot_endat1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W endat_send
1 4 R endat_receive1_0
2 8 R endat_receive1_1
3 c R endat_receive2
4 10 R endat_receive3
5 14 R/W endat_conf1
6 18 R/W endat_conf2
7 1c R/W endat_conf3
8 20 R/W endat_stat
9 24 R/W endat_int
a 28 R endat_test1
b 2c R/W endat_test2
c 30 R endat_receive4_0
d 34 R endat_receive4_1
e 38 W endat_sw_strobe
f 3c R endat_id

endat_send
Send register
The send register contains data to be transmitted to the EnDat encoder.
Mode command
MRS code/address/port address (depends on the mode command)
Parameters/instructions (depends on the mode command)
R/W
0x07000000
Address@app_endat0 : 0x40080240
Address@app_endat1 : 0x40080280
Address@mot_endat0 : 0x49200240
Address@mot_endat1 : 0x49200280
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 24 "000111"
byte4
Mode bits M[5:0]
23 - 16 "00000000"
byte3
MRS code / Address / Port address A[7:0]
15 - 8 "00000000"
byte2
Parameters / Instructions D[15:0]
7 - 0 "00000000"
byte1
Parameters / Instructions D[7:0]


endat_receive1_0
Receive register 1
Depending on the transmitted type 2.1 mode command, receive register 1 contains different data.
With EnDat type 2.2 mode commands and with SSI, the position value is always entered into receive-Reg 1.
R
Address@app_endat0 : 0x40080244
Address@app_endat1 : 0x40080284
Address@mot_endat0 : 0x49200244
Address@mot_endat1 : 0x49200284
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive1_1
Receive register 1
R
Address@app_endat0 : 0x40080248
Address@app_endat1 : 0x40080288
Address@mot_endat0 : 0x49200248
Address@mot_endat1 : 0x49200288
Bits Name Description
31 - 24 -
 reserved
23 - 16 byte7
...
15 - 8 byte6
...
7 - 0 byte5
...


endat_receive2
Receive register 2
If a type 2.2 mode command was sent, receive register 2 will contain the contents of additional information 2 and its CRC.
This data is to be interpreted in accordance with the EnDat Interface Description.
In SSI protocol mode with double-word transmission, the redundant position value is stored here (right-aligned).
R
Address@app_endat0 : 0x4008024c
Address@app_endat1 : 0x4008028c
Address@mot_endat0 : 0x4920024c
Address@mot_endat1 : 0x4920028c
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive3
Receive register 3
If a type 2.2 mode command was sent, receive register 3 will contain the contents of additional information 1 and its CRC.
This data is to be interpreted in accordance with the EnDat Interface Description.
R
Address@app_endat0 : 0x40080250
Address@app_endat1 : 0x40080290
Address@mot_endat0 : 0x49200250
Address@mot_endat1 : 0x49200290
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_conf1
Configuration register 1
R/W
0x00000df0
Address@app_endat0 : 0x40080254
Address@app_endat1 : 0x40080294
Address@mot_endat0 : 0x49200254
Address@mot_endat1 : 0x49200294
Bits Reset value Name Description
31 - 30 "00"
endat_ssi
These two bits set either the EnDat (0x2) or the SSI (0x1) transmission mode.
Values 0x0 and 0x3 are not permitted.
Note: For debugging purposes, this function may also be used to perform an internal status
engine software reset without clearing of the other internal registers.
29 "0"
ic_reset
Setting of this bit has the effect that the entire interface component is reset to its initial state.
IC reset inactive = 0
IC reset active = 1
28 - 26 "000"
f_sys
The system frequency actually used must be selected here.
64/48/32/50/100 MHz = 000/010/100/101/110
25 0
-
 reserved
24 "0"
delay_comp
Delay compensation.
This bit switches propagation delay compensation on.
When this bit is set, propagation time measurement is performed with the next data transmission to the EnDat encoder.
The interface component determines the cable propagation time and saves this in conf_reg1.
This value is used to determine propagation delay compensation.
To measure the propagation time again, the delay compensation bit must be reset and set again.
For 16-bit access it must be considered that the measured cable propagation time value is overwritten with 00/h.
Delay compensation off = 0
Delay compensation on = 1
In SSI mode, this bit is always on:
Delay compensation off = 0 (SSI mode)
23 - 16 "00000000"
cable_prop_time
The cable propagation time determined by the interface component is stored here.
(The application may change this value.
If that is the case the status registers propagation time measurement (LZM) bit will automatically be reset).
The binary value has a step width of one system clock.
At a system clock of 64 MHz, this corresponds to a setting range from 0 us to 3.98 us in steps of 15.6 ns.
The basic setting is 00 hex
15 "0"
auto_reset
Autom. reset (automatic reset). If this bit is set, resetting of the status register and error register is performed automatically
Autom. reset = 0 Resetting of the above-mentioned registers must be
                 performed by the application.
Autom. reset = 1 Resetting of the above-mentioned registers is done automatically.
                 However, this resetting only occurs in the next EnDat transmission with the start of data reception.
For safety applications: autom. reset = 0
14 "0"
reset_window
The set bit allows resetting of the status and error register only within a defined time period.
Reset window = 0 Resetting of the registers mentioned above can be performed
                 anytime (i.e. without considering malfunctions).
Reset Window = 1 Resetting of the registers mentioned above must be performed within
                 a defined time period for acceptance by the protocol engine.
For safety applications: reset window = 1
13 - 8 "001101"
data_word_len
Here the data word length is set binary with 6 bits for EnDat or SSI.
The permissible setting range for EnDat is from 8 bits to 48 bits.
The permissible setting range for SSI is from 8 bits to 48 bits.
Data word length = 0 bits = 00 1000
:
Data word length = 13 bits = 00 1101
:
Data word length = 48 bits = 11 0000
Note: The Data word length has to set to 40/d bit while using mode command "encoder transmit test values".
Note: In SSI mode the additionally required clock cycle for the parity bit is generated automatically by the circuit.
7 - 4 "1111"
f_tclk
Setting (4 bit) of transmission rate for EnDat and SSI from 100 kHz to 1 MHz (SSI) or 16 MHz (EnDat).
Transmission frequency = 100kHz   = 1111
Transmission frequency = 200kHz   = 1110
Transmission frequency = 1MHz     = 1101
Transmission frequency = 2MHz     = 1100
Transmission frequency = 4.16MHz  = 1011
Transmission frequency = 8.33MHz  = 0110
Transmission frequency = 16.67MHz = 0000..0011
3 0
-
 reserved
2 "0"
endat_cont_clk_mode
This bit is used to select the EnDat continuous clock mode.
Continuous clock off = 0
Continuous clock on = 1
1 "0"
uncond_transfer
This bit defines the unconditional data transfer to receive registers 1, 2, 3, 4 on completion of a data transmission process,
despite a flag being set in the status register.
Data transfer according to flag set in the status register = 0
Data transfer despite the flag in the status register = 1
For safety applications uncond_transfer = 1 must be set.
0 "0"
hw_strobe
1: Enables external /STR signal as strobe signal


endat_conf2
Configuration register 2
R/W
0x00040000
Address@app_endat0 : 0x40080258
Address@app_endat1 : 0x40080298
Address@mot_endat0 : 0x49200258
Address@mot_endat1 : 0x49200298
Bits Reset value Name Description
31 - 24 "00000000"
hw_strobe_delay
Here the application can enter a value for the HW strobe delay. The binary value has a step width of one system clock.
 Setting 00 = Off, 3..255=3..255 system clock cycles
The values 1, 2 are not permissible. At a system clock of 64 MHz, this corresponds to a value range from 46.88 ns to 3.98 us in steps of 15.6 ns.
23 0
-
 reserved
22 "0"
rtm
Activates the recovery time measurement that is then performed after each EnDat transmission with the mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2).
RTM=0 Recovery time measurement is deactivated (default setting after reset)
RTM=1 Recovery time measurement is activated
21 - 19 "000"
filter
The digital filter for the Data_RC data input can be adjusted in eight steps (3 bits) as shown in the table below.
The filter setting value corresponds to system clock cycles.
Setting 000 = Off
Setting 001 = 3
Setting 010 = 4
Setting 011 = 5
Setting 100 = 6
Setting 101 = 10
Setting 110 = 20
Setting 111 = 40
Setting             000     001     010     011     100     101     110     111
Note on the application:
The filter must be set according to the transmission rate of the serial interface to the encoder.
Example: fTCLK = 1 MHz (corresponds to 64 system clock cycles with CLK = 64 MHz)
For the filter, 1/10 of the fTCLK must be set. That means 6 system clock cycles leads to setting: 100
18 - 16 "100"
t_st
This time is to be set in accordance with EnDat specification.
The set time has an accuracy of 0.1 us.
Setting 000 = 0.5 * TCLK
Setting 001 = 0.5 us
Setting 010 = 1 us
Setting 011 = 1.5 us
Setting 100 = 2 us
Setting 101 = 4 us
Setting 110 = 8 us
Setting 111 = 10 us
15 - 8 "00000000"
watchdog
256 different watchdog time values can be set.
In the default setting 00 hex or 80 hex the watchdog is off.
7 - 0 "00000000"
timer_for_sampling_rate
256 different sampling rates can be set.
In the default setting 00 hex or 80 hex the timer is off.


endat_conf3
Configuration register 3
R/W
0x000000cc
Address@app_endat0 : 0x4008025c
Address@app_endat1 : 0x4008029c
Address@mot_endat0 : 0x4920025c
Address@mot_endat1 : 0x4920029c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
speed
(optional) This bit allows selection of the register width for velocity.
64-bit = 0
32-Bit = 1
14 - 9 0
-
 reserved
8 "0"
dw
This bit allows a double-word query to be selected with SSI transmission.
Double-word query off = 0
Double word query on  = 1
7 - 3 "11001"
singleturn_res
Here the number of steps per revolution is set to binary with 5 bits.
This setting is only required for the fir tree format.
Singleturn resolution = 13 bits = 0 1101
2 "1"
gray_to_binary
In SSI transmission mode, Gray code values can be converted here to binary code values.
Gray-to-binary conversion inactive = 0
Gray-to-binary conversion inactive = 1
1 "0"
format
Here the transmission format for SSI transmission is selected.
Fir tree: 0
Serial, right-aligned = 1
0 "0"
parity
Here the parity check for SSI transmission is selected.
Parity off = 0
Parity on  = 1


endat_stat
Status register
The status bits are created by the sequencing controller of the interface component, as required.
Status information remains set until it is reset by the application.
The application can selectively reset status information with a write command.
This occurs by writing 1 to the selected bits. In the event of concurrent access, the internal sequencing controller has priority.
This ensures that status information is not 'lost'.
The status bits (15:11) are only valid when additional information 1 or 2 has been received.
Note on the application:
The status register should be read after each data transmission. It provides information about validity of the data contained in the receive registers.
The status bits must be reset in order that the internal sequencing controller can recognize a renewed setting of the status bits.
Note: Each bit (except for LZM, LZK, Ready for Strobe) can trigger an interrupt (output: INT1).
Masking is performed with the interrupt mask register.
If a bit that has been set (and thus has triggered an interrupt) is reset, the INT1 output changes from low to three-state if no other bit has triggered an interrupt.
R/W
0x40000400
Address@app_endat0 : 0x40080260
Address@app_endat1 : 0x400802a0
Address@mot_endat0 : 0x49200260
Address@mot_endat1 : 0x492002a0
Bits Reset value Name Description
31 "0"
ready
If the ready bit is set, the status register is completely updated. All checks have been performed.
Data transmission is not yet completed, however, meaning that the EnDat protocol automation machine is not yet ready again.
No Ready = 0
Ready    = 1
30 "1"
ready_for_strobe
This bit reports that data transmission has ended and that the EnDat protocol automation machine is ready for the next transmission.
The time values Recovery time 1 (tm) and Recovery time 2 (tR) as specified in the EnDat specification are completed.
No Ready = 0
Ready    = 1
This bit cannot be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines.
The bit cannot cause an interrupt.
29 "0"
speed_ready
(optional). This bit reports that a new velocity value has been calculated.
No new velocity value calculated = 0
New velocity value calculated    = 1
28 "0"
rtm_stop
This bit indicates the end of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2)
27 "0"
rtm_start
This bit indicates the beginning of the recovery time, if conf2(22)=1 during EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2)
26 - 24 0
-
 reserved
23 "0"
prop_time_measurement
(LZM). This bit reports that propagation time measurement was successfully completed.
Condition: propagation delay compensation LZK in conf_reg1 is set.
If the value for propagation delay compensation in configuration register 1 is corrected by the application, this bit will automatically be reset.
LZM incomplete = 0
LZM complete   = 1
22 "0"
delay_comp
(LZK). This bit reports if propagation delay compensation is active.
If propagation delay compensation in configuration register 1 is switched off, this bit and propagation time measurement will automatically be reset.
LZK inactive = 0
LZK active   = 1
Neither the LZM nor the LZK bit can be reset by writing a 1 to the respective bit as this is a status display of the current conditions of internal automation engines.
Neither of the two bits can cause an interrupt.
21 - 19 0
-
 reserved
18 "0"
f_type3
Type II error (transmission layer) triggers F type III. Error recognition occurs in the EnDat master.
The error did not occur = 0
The error occurred      = 1
17 "0"
watchdog
Reports triggering of the watchdog.
Condition: watchdog in conf_reg2 is set.
Watchdog not triggered = 0
Watchdog triggered     = 1
16 "0"
spike
Reports that a Spike was detected at the data input port.
Condition: filter in conf_reg1 is set.
No spike       = 0
Spike occurred = 1
15 "0"
wrn
Contains the WRN status bit as transmitted in the EnDat protocol.
WRN = 0
WRN = 1
14 "0"
rm
Contains the RM status bit as transmitted in the EnDat protocol.
RM = 0
RM = 1
13 "0"
busy
Contains the Busy status bit as transmitted in the EnDat protocol.
Busy = 0
Busy = 1
12 "0"
crc_zi2
During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI2).
CRC check of ZI2 okay   = 0
CRC check of ZI2 faulty = 1
11 "0"
crc_zi1
During EnDat transmissions, this bit indicates the result of the CRC checking of additional information (ZI1).
CRC check of ZI2 okay   = 0
CRC check of ZI2 faulty = 1
10 "1"
error2
Contains the /Error 2 status bit from the EnDat protocol (only with EnDat2.2 commands).
/Error2 occurred      = 0
/Error2 did not occur = 1
9 "0"
receive3_reg
This status flag indicates that the data in Receive-Reg3 has been updated.
It must be cleared after Receive-Reg3 has been read to allow the interface component to rewrite data.
Receive-Reg3 not updated = 0
Receive-Reg3 updated     = 1
8 "0"
receive2_reg
This status flag indicates that the data in Receive-Reg 2 (3) has been updated.
It must be cleared after Receive-Reg2 (3) has been read to allow the interface component to rewrite data.
Receive-Reg2 (3) not updated = 0
Receive-Reg2 (3) updated     = 1
7 "0"
ir7
This bit indicates the state of input pin /IR7.
Input /IR7 is at high level = 0
Input /IR7 is at low level  = 1
6 "0"
ir6
This bit indicates an H/L edge at input pin /IR6.
No H/L edge transition at input /IR6 = 0
H/L edge transition has occurred at input /IR6R6 = 1
5 "0"
mrs_adr
The occurrence of an addressing or acknowledgement error is shown here as described in the EnDat Interface specification.
The errors (F type I / II) are special cases of MRS/address errors, i.e. they are a sub-quantity of these.
Accordingly, whenever a type I or type II error is identified, the MRS/Adr bit is set.
For example, if an MRS/address bit is recognized incorrectly due to a disturbance, only the MRS/Adr status bit will be set, not the F TYP I/II bits.
No acknowledgement or addressing error has occurred = 0
An acknowledgement or addressing error has occurred = 1
4 "0"
f_type2
Shows type II error handling in accordance with the EnDat specification at Annex A2.
A type II error did not occur = 0
A type II error occurred = 1
3 "0"
f_type1
Shows type I error handling in accordance with the EnDat specification at Annex A2.
A type I error did not occur = 0
A type I error occurred      = 1
2 "0"
crcpw_parity
This bit has two meanings.
With EnDat transmission it represents the result of the CRC check of the received value (position value, parameter or test value).
With SSI transmission it shows the result of the parity check. Condition: parity check in conf-Reg1 is switched on.
CRC check or parity check okay = 0
CRC and parity check faulty    = 1
1 "0"
error1
The status bit error1 from the EnDat protocol is entered here.
Error1 did not occur = 0
Error1 occurred = 1
0 "0"
receive1_reg
This status flag indicates that the data in Receive-Reg 1 has been updated.
It must be cleared after Receive-Reg1 has been read to allow the interface component to rewrite data there.
Receive-Reg1 not updated = 0
Receive-Reg1 updated     = 1
Note: This flag is ignored if the uncond_transfer bit is enabled in conf-Reg 1.


endat_int
Interrupt mask
The interrupt mask register is for the masking of the status registers interrupt sources.
All bits shown in the status register (except for LZM, LZK, Ready for Strobe) can generate an interrupt.
The bit assignments of the interrupt mask register are identical to those of the status register.
An interrupt is allowed by setting the corresponding bit to 1.
The INT output changes from three-state to low.
R/W
0x00000000
Address@app_endat0 : 0x40080264
Address@app_endat1 : 0x400802a4
Address@mot_endat0 : 0x49200264
Address@mot_endat1 : 0x492002a4
Bits Reset value Name Description
31 "0"
ready
...
30 0
-
 reserved
29 "0"
speed_ready
...
28 - 19 0
-
 reserved
18 "0"
f_type3
...
17 "0"
watchdog
...
16 "0"
spike
...
15 "0"
wrn
...
14 "0"
RM
...
13 "0"
busy
...
12 "0"
crc_zi2
...
11 "0"
crc_zi1
...
10 "0"
error2
...
9 "0"
receive3_reg
...
8 "0"
receive2_reg
...
7 "0"
ir7
...
6 "0"
ir6
...
5 "0"
mrs_adr
...
4 "0"
f_type2
...
3 "0"
f_type1
...
2 "0"
crcpw_parity
...
1 "0"
error1
...
0 "0"
receive1_reg
...


endat_test1
Test register 1
R
Address@app_endat0 : 0x40080268
Address@app_endat1 : 0x400802a8
Address@mot_endat0 : 0x49200268
Address@mot_endat1 : 0x492002a8
Bits Name Description
31 - 10 ic_test_values
...
9 - 4 enDat_automation_engine
...
3 -
 reserved
2 - 1 status_zi
Allows testing of the IC-internal automation machine.
IC sends no clocks for additional information = 00
IC sends clocks for one unit of additional information 1 = 01
IC sends clocks for one unit of additional information 2 = 10
IC sends clocks for two units of additional information (1+2) = 11
0 dl_high
For control of the EnDat automation machine.


endat_test2
Test register 2
R/W
0x00000000
Address@app_endat0 : 0x4008026c
Address@app_endat1 : 0x400802ac
Address@mot_endat0 : 0x4920026c
Address@mot_endat1 : 0x492002ac
Bits Reset value Name Description
31 - 16 0x0
ic_test_data
RTM value - Counter value of the recovery time measurement if conf2(22)=1.
Updated after the completion of the recovery time tm measurement during the EnDat transmission with mode command 1-1 "Encoder transmit position value and selection of memory area" with MRS code 0x43 (selection of 2nd word of position value 2).
With conf2(22)=0, data for the recovery time measurement tm are not valid. Writing to the test register sets the internal counter of the recovery time measurement to the value of the "write data" (31:16) - Init word or start value of the recovery time measurement. The value of the internal measuring counter is incremented with the system frequency during the time tm, and the carry is discarded.
15 - 14 "00"
sel_test_mux3
(For testing at IC manufacturing site, internal resources can be read via test register 3)
Write value test register 3        = 00 (Content written to test register 3 via the I/O port.)
Test values counter TM measurement = 01 TM_High_Err & TM_low_Err & F_TM & TM_CT2 &TM_CT1
Limit values for TM measurement    = 10 C_WT_HIGH & C_WT_LOW & C_HIGH & C_LOW
Test values internal OEM Reg       = 11 (only available in customer-specific versions)
13 - 12 "00"
sel_test_mux2
(For testing at IC manufacturing site, internal resources can be read via test register 4)
Test_Mode_Divider = 0:
  Selection of test multiplexer 2:
    Test value Pos1b (Pos1 - Off2)      = 00
    Test value Pos1c (Pos1 DIV nsrPos1) = 01
    Test value Pos1d (Pos1 MOD srM)     = 10
    Test value Pos2                     = 11
    Test_Mode_Divider                   = 1
  Selection of test multiplexer 2:
    Test value quotient (divider)  = 00
    Test value remainder (divider) = 01
11 "0"
test_mode_divider
(For testing at IC manufacturing site, internal resources can be read via test register 4)
Standard operating mode = 0
Test mode active = 1
10 - 8 "000"
selection_add_info
The number of required additional information units (ZI) can also be selected manually(alternatively to implemented ZI automation resources)
Automated resources active = 0 00
IC sends clocks for one unit of additional information 1      = 0 01
IC sends clocks for one unit of additional information 2      = 0 10
IC sends clocks for two units of additional information (1+2) = 0 11
IC sends no clocks for additional information                 = 1 xx
7 "0"
ic_test_mode
The IC can be switched to a special test mode, allowing the testing of internal modules
Standard application mode = 0
Special test mode         = 1
6 0
-
 reserved
5 - 4 "00"
sel_test_mux
(for testing at IC manufacturing site, internal resources can be read)
Standard operating mode = 00
Central pre-dividers    = 01
Start bit counter       = 10
Delay counter and register, additional information bit = 11
3 "0"
test_receive_reg
Standard operating mode        = TST receive_reg = 0
Test mode for receive register = TST receive_reg = 1
By writing to the address of the receive registers, the content of test register 2 (bits (31:16) is transferred them.
It is not possible to directly write to a receive register via the parallel port.
2 "0"
selection_tst_out
For testing, the TST_OUT_PIN pin is assigned as follows:
Internal (delayed by synchronization) DATA_RC_INT = 0
This signal is the signal that belongs to data strobe pulse.
1 - 0 0
-
 reserved


endat_receive4_0
Receive register 4
Receive register 4 contains position value 2 (Pos2), which is put together from the additional information 1 of Cycles 2, 3 and 4.
Test function: with the test register 2 bits (13:12), internal test values can be read
R
Address@app_endat0 : 0x40080270
Address@app_endat1 : 0x400802b0
Address@mot_endat0 : 0x49200270
Address@mot_endat1 : 0x492002b0
Bits Name Description
31 - 24 byte4
...
23 - 16 byte3
...
15 - 8 byte2
...
7 - 0 byte1
...


endat_receive4_1
Receive register 4
R
Address@app_endat0 : 0x40080274
Address@app_endat1 : 0x400802b4
Address@mot_endat0 : 0x49200274
Address@mot_endat1 : 0x492002b4
Bits Name Description
31 - 16 -
 reserved
15 - 8 byte6
...
7 - 0 byte5
...


endat_sw_strobe
SW strobe
W
0x00000000
Address@app_endat0 : 0x40080278
Address@app_endat1 : 0x400802b8
Address@mot_endat0 : 0x49200278
Address@mot_endat1 : 0x492002b8
Bits Reset value Name Description
31 - 0 0x0
sw_strobe
Writing this register will in each case cause the first H/L transition of the TCLK transmission clock signal.


endat_id
Identification register
The soft-macro specification (ID) is stored here. This information is helpful for automated configuration by higher-level user software.
E22: Designates the latest EnDat 2.2 protocol generation
6: MAZeT-internal designation (E6)
xxxx: Consecutive version number (this document is valid for all versions as of xx13.)
R
Address@app_endat0 : 0x4008027c
Address@app_endat1 : 0x400802bc
Address@mot_endat0 : 0x4920027c
Address@mot_endat1 : 0x492002bc
Bits Name Description
31 - 0 id
...



Base Address Area: app_endat_ctrl0, app_endat_ctrl1, mot_endat_ctrl0, mot_endat_ctrl1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W endat_ctrl_trigger_cfg
1 4 R/W endat_ctrl_trigger
2 8 R/W endat_ctrl_strobe_cfg
3 c -  reserved

endat_ctrl_trigger_cfg
EnDat trigger configuration
R/W
0x00000000
Address@app_endat_ctrl0 : 0x400802c0
Address@app_endat_ctrl1 : 0x400802d0
Address@mot_endat_ctrl0 : 0x492002c0
Address@mot_endat_ctrl1 : 0x492002d0
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
sel
Trigger source select
This bit field configures which event is connected to the strobe signal of the EnDat core. A rising edge of the selected event will generate an event to the core according to the configuration in the strobe_cfg register.
Note: When ntimer or n_si are selected, they are routed directly to the EnDat core (i.e. they are not connected to the pulse former).
Value trigger event
0 none
1 manual
2 gxc_trigger_out0
3 gxc_trigger_out0 (inverted)
4 gxc_trigger_out1
5 gxc_trigger_out1 (inverted)
6 gxc_sample_in0
7 gxc_sample_in0 (inverted)
8 gxc_sample_in1
9 gxc_sample_in1 (inverted)
10 gxc_trigger_global_out0
11 gxc_trigger_global_out0 (inverted)
12 gxc_trigger_global_out1
13 gxc_trigger_global_out1 (inverted)
14 gxc_sample_global_in0
15 gxc_sample_global_in0 (inverted)
16 gxc_sample_global_in1
17 gxc_sample_global_in1 (inverted)
18 app_gpio_counter_zero0
19 app_gpio_counter_zero1
20 app_gpio_counter_zero2
21 app_gpio_counter_zero3
22 app_gpio_counter_zero4
23 app_gpio_counter_zero5
24 app_gpio_counter_zero6
25 app_gpio_counter_zero7
26 ntimer signal of other EnDat instance
27 n_si signal of other EnDat instance
28-31 reserved


endat_ctrl_trigger
EnDat trigger
R/W
0x00000000
Address@app_endat_ctrl0 : 0x400802c4
Address@app_endat_ctrl1 : 0x400802d4
Address@mot_endat_ctrl0 : 0x492002c4
Address@mot_endat_ctrl1 : 0x492002d4
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
manual
Manual trigger.
Writing '1' to this bit will trigger the EnDat core immediately in case the trigger_cfg.sel bit field is set to manual mode and the EnDat core is setup for external triggering by the strobe signal.


endat_ctrl_strobe_cfg
EnDat strobe pulse form configuration
R/W
0x00000303
Address@app_endat_ctrl0 : 0x400802c8
Address@app_endat_ctrl1 : 0x400802d8
Address@mot_endat_ctrl0 : 0x492002c8
Address@mot_endat_ctrl1 : 0x492002d8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000011"
high_len
Length of the high phase (i.e. inactive phase) of the strobe signal
The high phase will be the programmed value + 1 clock cycle.
Note: EnDat spec requires the high phase to be at least 4 clock cycles long, therefore 0 - 2 are illegal settings.
Note: There is no other requirement on the high phase. This bit field is for debug and test only and should be kept at its default setting.
7 - 0 "00000011"
low_len
Length of the low phase (i.e. active phase) of the strobe signal
The low phase will be the programmed value + 1 clock cycle.
Note: EnDat spec requires the low phase to be at least 4 clock cycles long, therefore 0 - 2 are illegal settings.
Note: If a strobe delay is configured in the EnDat core, the minimum length is strobe delay + 1 (i.e. program low_len = strobe delay).



Base Address Area: app_gpio, mot_gpio

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gpio_app_cfg0
1 4 R/W gpio_app_cfg1
2 8 R/W gpio_app_cfg2
3 c R/W gpio_app_cfg3
4 10 R/W gpio_app_cfg4
5 14 R/W gpio_app_cfg5
6 18 R/W gpio_app_cfg6
7 1c R/W gpio_app_cfg7
8 20 R/W gpio_app_tc0
9 24 R/W gpio_app_tc1
a 28 R/W gpio_app_tc2
b 2c R/W gpio_app_tc3
c 30 R/W gpio_app_tc4
d 34 R/W gpio_app_tc5
e 38 R/W gpio_app_tc6
f 3c R/W gpio_app_tc7
10 40 R/W gpio_app_counter0_ctrl
11 44 R/W gpio_app_counter1_ctrl
12 48 R/W gpio_app_counter2_ctrl
13 4c R/W gpio_app_counter3_ctrl
14 50 R/W gpio_app_counter4_ctrl
15 54 R/W gpio_app_counter5_ctrl
16 58 R/W gpio_app_counter6_ctrl
17 5c R/W gpio_app_counter7_ctrl
18 60 R/W gpio_app_counter0_max
19 64 R/W gpio_app_counter1_max
1a 68 R/W gpio_app_counter2_max
1b 6c R/W gpio_app_counter3_max
1c 70 R/W gpio_app_counter4_max
1d 74 R/W gpio_app_counter5_max
1e 78 R/W gpio_app_counter6_max
1f 7c R/W gpio_app_counter7_max
20 80 R/W gpio_app_counter0_cnt
21 84 R/W gpio_app_counter1_cnt
22 88 R/W gpio_app_counter2_cnt
23 8c R/W gpio_app_counter3_cnt
24 90 R/W gpio_app_counter4_cnt
25 94 R/W gpio_app_counter5_cnt
26 98 R/W gpio_app_counter6_cnt
27 9c R/W gpio_app_counter7_cnt
28 a0 R/W gpio_app_line
29 a4 R gpio_app_in
2a a8 R/W gpio_app_irq_raw
2b ac R gpio_app_irq_masked
2c b0 R/W gpio_app_irq_mask_set
2d b4 R/W gpio_app_irq_mask_rst
2e b8 R/W gpio_app_cnt_irq_raw
2f bc R gpio_app_cnt_irq_masked
30 c0 R/W gpio_app_cnt_irq_mask_set
31 c4 R/W gpio_app_cnt_irq_mask_rst
32-3f c8-fc -  reserved

gpio_app_cfg0
GPIO_APP pin 0 config register:
R/W
0x00000000
Address@app_gpio : 0x40080500
Address@mot_gpio : 0x49200500
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
Run blink sequence only once (blink mode only)
13 - 9 "00000"
blink_len
Length of blink sequence minus 1 (blink mode only)
 00000: use bit 0 of gpio_app_tc
 00001: use bits 0..1 of gpio_app_tc
 00010: use bits 0..2 of gpio_app_tc
...
 11111: use bits 0..31 of gpio_app_tc
8 - 5 "0000"
count_ref
counter reference
 0000: counter 0
 0001: counter 1
 0010: counter 2
 0011: counter 3
 0100: counter 4
 0101: counter 5
 0110: counter 6
 0111: counter 7
 1111: sys_time (global system time)
4 "0"
inv
1: invert input/output value
0: do not invert input/output
3 - 0 "0000"
mode
defines the gp input or output mode - depends on io_cfg
Input modes:
 0000: read mode
 0001: capture continued at rising edge (allows gpio_app_irq on each capture)
 0010: capture once at rising edge (reset gpio_app_irq to capture again)
 0011: capture once at high level (reset gpio_app_irq to capture again)
Output modes:
 0100: set to 0
 0101: set to 1
 0110: set to gpio_app_line[0]
 0111: pwm mode, direct threshold update (might cause hazards on output)
 1000: blink mode
Multi pin modes:
 1111: pwm2-mode with threshold update at counter=0 from gpio_app_tc[n+1] register (hazard-free)


gpio_app_cfg1
GPIO_APP pin 1 config register:
R/W
0x00000000
Address@app_gpio : 0x40080504
Address@mot_gpio : 0x49200504
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg2
GPIO_APP pin 2 config register:
R/W
0x00000000
Address@app_gpio : 0x40080508
Address@mot_gpio : 0x49200508
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg3
GPIO_APP pin 3 config register:
R/W
0x00000000
Address@app_gpio : 0x4008050c
Address@mot_gpio : 0x4920050c
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg4
GPIO_APP pin 4 config register:
R/W
0x00000000
Address@app_gpio : 0x40080510
Address@mot_gpio : 0x49200510
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg5
GPIO_APP pin 5 config register:
R/W
0x00000000
Address@app_gpio : 0x40080514
Address@mot_gpio : 0x49200514
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg6
GPIO_APP pin 6 config register:
R/W
0x00000000
Address@app_gpio : 0x40080518
Address@mot_gpio : 0x49200518
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_cfg7
GPIO_APP pin 7 config register:
R/W
0x00000000
Address@app_gpio : 0x4008051c
Address@mot_gpio : 0x4920051c
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
blink_once
analog to gpio_app_cfg0
13 - 9 "00000"
blink_len
analog to gpio_app_cfg0
8 - 5 "0000"
count_ref
analog to gpio_app_cfg0
4 "0"
inv
analog to gpio_app_cfg0
3 - 0 "0000"
mode
analog to gpio_app_cfg0


gpio_app_tc0
GPIO_APP pin 0 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080520
Address@mot_gpio : 0x49200520
Bits Reset value Name Description
31 - 0 0x0
val
 Threshold/Capture register:
 PWM mode (threshold):



The counter threshold value equals the number of inactive clock cycles per period (cycles with pwm=0).
Therefore it is interpreted differently in symmetrical and asymmetrical counter mode:
Asymmetrical mode (sawtooth): pwm = (counter >= gpio_app_tc)
Symmetrical mode (triangle) : Counter is compared with gpio_app_tc[31:1], gpio_app_tc[0] extends the inactive phase
by 1 clock cycle only while counting up. This allows running a 10 ns resolution even in symmetrical mode.

 Capture mode (capture register)
  In the capture mode, this register holds the captured counter value.

 Blink mode (blink sequence)
  In the blink mode, this register holds the blinking sequence starting from bit 0.


gpio_app_tc1
GPIO_APP pin 1 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080524
Address@mot_gpio : 0x49200524
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc2
GPIO_APP pin 2 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080528
Address@mot_gpio : 0x49200528
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc3
GPIO_APP pin 3 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x4008052c
Address@mot_gpio : 0x4920052c
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc4
GPIO_APP pin 4 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080530
Address@mot_gpio : 0x49200530
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc5
GPIO_APP pin 5 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080534
Address@mot_gpio : 0x49200534
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc6
GPIO_APP pin 6 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x40080538
Address@mot_gpio : 0x49200538
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_tc7
GPIO_APP pin 7 threshold or capture register:
R/W
0x00000000
Address@app_gpio : 0x4008053c
Address@mot_gpio : 0x4920053c
Bits Reset value Name Description
31 - 0 0x0
val
analog to gpio_app_tc0


gpio_app_counter0_ctrl
GPIO_APP counter0 control register:
R/W
0x00000000
Address@app_gpio : 0x40080540
Address@mot_gpio : 0x49200540
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
gpio reference (0 - 7)
6 - 5 "00"
event_act
Define action of selected external event (dependent on sel_event, gpio_ref)
00: count every clock cycle, ignore external events
01: count only external events (edge or level according to bit sel_event)
10: enable watchdog mode of counter (external event will be reset without IRQ, overflow generates IRQ).
11: enable automatic run mode (external event sets run bit, used for DC-DC PWM in combination with bit once=1)
4 "0"
once
1: count once (reset run bit after 1 period)
0: count continuously
3 "0"
sel_event
select external event
0: high level, invert gpio in register gpio_app_cfg to select low level
1: pos. edge, invert gpio in register gpio_app_cfg to select neg. edge
2 "0"
irq_en
1: enable interrupt request on sel_event
0: disable interrupt request
1 "0"
sym_nasym
1: symmetric mode (triangle)
0: asymmetric mode (sawtooth)
0 "0"
run
1: start counter, counter is running
0: stop counter


gpio_app_counter1_ctrl
GPIO_APP counter1 control register:
R/W
0x00000000
Address@app_gpio : 0x40080544
Address@mot_gpio : 0x49200544
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter2_ctrl
GPIO_APP counter2 control register:
R/W
0x00000000
Address@app_gpio : 0x40080548
Address@mot_gpio : 0x49200548
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter3_ctrl
GPIO_APP counter3 control register:
R/W
0x00000000
Address@app_gpio : 0x4008054c
Address@mot_gpio : 0x4920054c
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter4_ctrl
GPIO_APP counter4 control register:
R/W
0x00000000
Address@app_gpio : 0x40080550
Address@mot_gpio : 0x49200550
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter5_ctrl
GPIO_APP counter5 control register:
R/W
0x00000000
Address@app_gpio : 0x40080554
Address@mot_gpio : 0x49200554
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter6_ctrl
GPIO_APP counter6 control register:
R/W
0x00000000
Address@app_gpio : 0x40080558
Address@mot_gpio : 0x49200558
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter7_ctrl
GPIO_APP counter7 control register:
R/W
0x00000000
Address@app_gpio : 0x4008055c
Address@mot_gpio : 0x4920055c
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 - 7 "000"
gpio_ref
analog to gpio_app_counter0_ctrl
6 - 5 "00"
event_act
analog to gpio_app_counter0_ctrl
4 "0"
once
analog to gpio_app_counter0_ctrl
3 "0"
sel_event
analog to gpio_app_counter0_ctrl
2 "0"
irq_en
analog to gpio_app_counter0_ctrl
1 "0"
sym_nasym
analog to gpio_app_counter0_ctrl
0 "0"
run
analog to gpio_app_counter0_ctrl


gpio_app_counter0_max
GPIO_APP counter0 max value:
R/W
0x00000000
Address@app_gpio : 0x40080560
Address@mot_gpio : 0x49200560
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter1_max
GPIO_APP counter1 max value:
R/W
0x00000000
Address@app_gpio : 0x40080564
Address@mot_gpio : 0x49200564
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter2_max
GPIO_APP counter2 max value:
R/W
0x00000000
Address@app_gpio : 0x40080568
Address@mot_gpio : 0x49200568
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter3_max
GPIO_APP counter3 max value:
R/W
0x00000000
Address@app_gpio : 0x4008056c
Address@mot_gpio : 0x4920056c
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter4_max
GPIO_APP counter4 max value:
R/W
0x00000000
Address@app_gpio : 0x40080570
Address@mot_gpio : 0x49200570
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter5_max
GPIO_APP counter5 max value:
R/W
0x00000000
Address@app_gpio : 0x40080574
Address@mot_gpio : 0x49200574
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter6_max
GPIO_APP counter6 max value:
R/W
0x00000000
Address@app_gpio : 0x40080578
Address@mot_gpio : 0x49200578
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter7_max
GPIO_APP counter7 max value:
R/W
0x00000000
Address@app_gpio : 0x4008057c
Address@mot_gpio : 0x4920057c
Bits Reset value Name Description
31 - 0 0x0
val
Asymmetric mode: Counting period in cc + 1
Symmetric mode: Counting period in cc


gpio_app_counter0_cnt
GPIO_APP counter0 current value:
R/W
0x00000000
Address@app_gpio : 0x40080580
Address@mot_gpio : 0x49200580
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter1_cnt
GPIO_APP counter1 current value:
R/W
0x00000000
Address@app_gpio : 0x40080584
Address@mot_gpio : 0x49200584
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter2_cnt
GPIO_APP counter2 current value:
R/W
0x00000000
Address@app_gpio : 0x40080588
Address@mot_gpio : 0x49200588
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter3_cnt
GPIO_APP counter3 current value:
R/W
0x00000000
Address@app_gpio : 0x4008058c
Address@mot_gpio : 0x4920058c
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter4_cnt
GPIO_APP counter4 current value:
R/W
0x00000000
Address@app_gpio : 0x40080590
Address@mot_gpio : 0x49200590
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter5_cnt
GPIO_APP counter5 current value:
R/W
0x00000000
Address@app_gpio : 0x40080594
Address@mot_gpio : 0x49200594
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter6_cnt
GPIO_APP counter6 current value:
R/W
0x00000000
Address@app_gpio : 0x40080598
Address@mot_gpio : 0x49200598
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_counter7_cnt
GPIO_APP counter7 current value:
R/W
0x00000000
Address@app_gpio : 0x4008059c
Address@mot_gpio : 0x4920059c
Bits Reset value Name Description
31 - 0 0x0
val
current counter value


gpio_app_line
GPIO_APP line register
R/W
0x00000000
Address@app_gpio : 0x400805a0
Address@mot_gpio : 0x492005a0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
val
gpio_app output values


gpio_app_in
GPIO_APP latched inputs register:
R
Address@app_gpio : 0x400805a4
Address@mot_gpio : 0x492005a4
Bits Name Description
31 - 8 -
 reserved
7 - 0 val
gpio_app input values


gpio_app_irq_raw
GPIO_APP raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@app_gpio : 0x400805a8
Address@mot_gpio : 0x492005a8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_masked
GPIO_APP masked IRQ register:
R
Address@app_gpio : 0x400805ac
Address@mot_gpio : 0x492005ac
Bits Name Description
31 - 8 -
 reserved
7 gpio_app7
Interrupt bit for GPIO_APP7
6 gpio_app6
Interrupt bit for GPIO_APP6
5 gpio_app5
Interrupt bit for GPIO_APP5
4 gpio_app4
Interrupt bit for GPIO_APP4
3 gpio_app3
Interrupt bit for GPIO_APP3
2 gpio_app2
Interrupt bit for GPIO_APP2
1 gpio_app1
Interrupt bit for GPIO_APP1
0 gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_mask_set
GPIO_APP interrupt mask set:
Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to gpio_app_irq_raw.
R/W
0x00000000
Address@app_gpio : 0x400805b0
Address@mot_gpio : 0x492005b0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_irq_mask_rst
GPIO_APP interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
0x00000000
Address@app_gpio : 0x400805b4
Address@mot_gpio : 0x492005b4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
gpio_app7
Interrupt bit for GPIO_APP7
6 "0"
gpio_app6
Interrupt bit for GPIO_APP6
5 "0"
gpio_app5
Interrupt bit for GPIO_APP5
4 "0"
gpio_app4
Interrupt bit for GPIO_APP4
3 "0"
gpio_app3
Interrupt bit for GPIO_APP3
2 "0"
gpio_app2
Interrupt bit for GPIO_APP2
1 "0"
gpio_app1
Interrupt bit for GPIO_APP1
0 "0"
gpio_app0
Interrupt bit for GPIO_APP0


gpio_app_cnt_irq_raw
Counter raw IRQ register:
Read access shows the status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the corresponding IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@app_gpio : 0x400805b8
Address@mot_gpio : 0x492005b8
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
cnt7
Interrupt bit for counter7
6 "0"
cnt6
Interrupt bit for counter6
5 "0"
cnt5
Interrupt bit for counter5
4 "0"
cnt4
Interrupt bit for counter4
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_masked
Counter masked IRQ register:
Read access shows the status of the masked IRQs (cnt_irq_raw AND cnt_irq_mask).
R
Address@app_gpio : 0x400805bc
Address@mot_gpio : 0x492005bc
Bits Name Description
31 - 8 -
 reserved
7 cnt7
Interrupt bit for counter7
6 cnt6
Interrupt bit for counter6
5 cnt5
Interrupt bit for counter5
4 cnt4
Interrupt bit for counter4
3 cnt3
Interrupt bit for counter3
2 cnt2
Interrupt bit for counter2
1 cnt1
Interrupt bit for counter1
0 cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_mask_set
Counter interrupt mask set:
Since different software tasks might change its bits, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets the interrupt mask bit (enables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
Note: Before activating the interrupt mask, delete old pending interrupts by writing the same value to cnt_irq_raw.
R/W
0x00000000
Address@app_gpio : 0x400805c0
Address@mot_gpio : 0x492005c0
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
cnt7
Interrupt bit for counter7
6 "0"
cnt6
Interrupt bit for counter6
5 "0"
cnt5
Interrupt bit for counter5
4 "0"
cnt4
Interrupt bit for counter4
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0


gpio_app_cnt_irq_mask_rst
Counter interrupt mask reset:
This reset mask serves to disable the interrupt requests for the corresponding interrupt sources.
Write access with '1' resets the interrupt mask bit (disables the interrupt request for the corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows the current interrupt mask.
R/W
0x00000000
Address@app_gpio : 0x400805c4
Address@mot_gpio : 0x492005c4
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
cnt7
Interrupt bit for counter7
6 "0"
cnt6
Interrupt bit for counter6
5 "0"
cnt5
Interrupt bit for counter5
4 "0"
cnt4
Interrupt bit for counter4
3 "0"
cnt3
Interrupt bit for counter3
2 "0"
cnt2
Interrupt bit for counter2
1 "0"
cnt1
Interrupt bit for counter1
0 "0"
cnt0
Interrupt bit for counter0



Base Address Area: app_trigger_irq, app_trigger_irq_global, mot_trigger_irq, mot_trigger_irq_global

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W trigger_irq_cfg
1 4 R/W trigger_irq_irq_raw
2 8 R/W trigger_irq_irq_masked
3 c R/W trigger_irq_irq_mask_set
4 10 R/W trigger_irq_irq_mask_rst
5-7 14-1c -  reserved

trigger_irq_cfg
Trigger IRQ configuration register.
R/W
0x00000000
Address@app_trigger_irq : 0x40080760
Address@app_trigger_irq_global : 0x40080780
Address@mot_trigger_irq : 0x49200760
Address@mot_trigger_irq_global : 0x49200780
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 - 0 "00"
trigger_out_polarity
Polarity of trigger_out signals for edge detection.
0: Use pos-edge on trigger_out signals to trigger an IRQ.
1: Use neg-edge on trigger_out signals to trigger an IRQ.
Note: Changing the polarity will trigger an IRQ in the raw register (and when the mask is set also the IRQ signal to the CPU) due to the edge detection logic.


trigger_irq_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@app_trigger_irq : 0x40080764
Address@app_trigger_irq_global : 0x40080784
Address@mot_trigger_irq : 0x49200764
Address@mot_trigger_irq_global : 0x49200784
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
trigger_out_edge1
Event: Edge detected on trigger_out[1]
0 "0"
trigger_out_edge0
Event: Edge detected on trigger_out[0]


trigger_irq_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_trigger_irq_irq_raw).
R/W
0x00000000
Address@app_trigger_irq : 0x40080768
Address@app_trigger_irq_global : 0x40080788
Address@mot_trigger_irq : 0x49200768
Address@mot_trigger_irq_global : 0x49200788
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
trigger_out_edge1
Event: Edge detected on trigger_out[1]
0 "0"
trigger_out_edge0
Event: Edge detected on trigger_out[0]


trigger_irq_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_trigger_irq_irq_raw
R/W
0x00000000
Address@app_trigger_irq : 0x4008076c
Address@app_trigger_irq_global : 0x4008078c
Address@mot_trigger_irq : 0x4920076c
Address@mot_trigger_irq_global : 0x4920078c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
trigger_out_edge1
Event: Edge detected on trigger_out[1]
0 "0"
trigger_out_edge0
Event: Edge detected on trigger_out[0]


trigger_irq_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 2 when no IRQ is set:
  0 : irq-trigger_out_edge0
  1 : irq-trigger_out_edge1
  2 : no active IRQ
R/W
0x00000000
Address@app_trigger_irq : 0x40080770
Address@app_trigger_irq_global : 0x40080790
Address@mot_trigger_irq : 0x49200770
Address@mot_trigger_irq_global : 0x49200790
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
trigger_out_edge1
Event: Edge detected on trigger_out[1]
0 "0"
trigger_out_edge0
Event: Edge detected on trigger_out[0]



Base Address Area: app_dmac0_dmac_ch0, app_dmac0_dmac_ch1, app_dmac0_dmac_ch2, app_dmac0_dmac_ch3, app_dmac1_dmac_ch0, app_dmac1_dmac_ch1, app_dmac1_dmac_ch2, app_dmac1_dmac_ch3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W dmac_chsrc_ad
1 4 R/W dmac_chdest_ad
2 8 R/W dmac_chlink
3 c R/W dmac_chctrl
4 10 R/W dmac_chcfg
5-7 14-1c -  reserved

dmac_chsrc_ad
channel source address registers
R/W
0x00000000
Address@app_dmac0_dmac_ch0 : 0x40081100
Address@app_dmac0_dmac_ch1 : 0x40081120
Address@app_dmac0_dmac_ch2 : 0x40081140
Address@app_dmac0_dmac_ch3 : 0x40081160
Address@app_dmac1_dmac_ch0 : 0x40082100
Address@app_dmac1_dmac_ch1 : 0x40082120
Address@app_dmac1_dmac_ch2 : 0x40082140
Address@app_dmac1_dmac_ch3 : 0x40082160
Bits Reset value Name Description
31 - 0 0x0
DMACCHSRCADDR
DMA source address


dmac_chdest_ad
channel destination address registers
R/W
0x00000000
Address@app_dmac0_dmac_ch0 : 0x40081104
Address@app_dmac0_dmac_ch1 : 0x40081124
Address@app_dmac0_dmac_ch2 : 0x40081144
Address@app_dmac0_dmac_ch3 : 0x40081164
Address@app_dmac1_dmac_ch0 : 0x40082104
Address@app_dmac1_dmac_ch1 : 0x40082124
Address@app_dmac1_dmac_ch2 : 0x40082144
Address@app_dmac1_dmac_ch3 : 0x40082164
Bits Reset value Name Description
31 - 0 0x0
DMACCHDESTADDR
DMA destination address


dmac_chlink
channel linked list item register
R/W
0x00000000
Address@app_dmac0_dmac_ch0 : 0x40081108
Address@app_dmac0_dmac_ch1 : 0x40081128
Address@app_dmac0_dmac_ch2 : 0x40081148
Address@app_dmac0_dmac_ch3 : 0x40081168
Address@app_dmac1_dmac_ch0 : 0x40082108
Address@app_dmac1_dmac_ch1 : 0x40082128
Address@app_dmac1_dmac_ch2 : 0x40082148
Address@app_dmac1_dmac_ch3 : 0x40082168
Bits Reset value Name Description
31 - 2 0x0
LLIADDR
Linked list item. Bits [31:2] of the address for the next LLI. Address bits [1:0] are 0.
1 - 0 0
-
 reserved


dmac_chctrl
channel control registers
R/W
0x00000000
Address@app_dmac0_dmac_ch0 : 0x4008110c
Address@app_dmac0_dmac_ch1 : 0x4008112c
Address@app_dmac0_dmac_ch2 : 0x4008114c
Address@app_dmac0_dmac_ch3 : 0x4008116c
Address@app_dmac1_dmac_ch0 : 0x4008210c
Address@app_dmac1_dmac_ch1 : 0x4008212c
Address@app_dmac1_dmac_ch2 : 0x4008214c
Address@app_dmac1_dmac_ch3 : 0x4008216c
Bits Reset value Name Description
31 "0"
I
Terminal count interrupt enable bit. It controls whether the current LLI is expected to trigger the terminal count interrupt.
30 - 28 "000"
Prot
Protection.
27 "0"
DI
Destination increment. When set the destination address is incremented after each transfer.
26 "0"
SI
Source increment. When set the source address is incremented after each transfer.
25 0
-
 reserved
24 "0"
ARM_EQ
Set equal behaviour to arm implementation
This bit should always be set to 1 (default of 0 is from historical reasons).
This bit changes 2 behavioural details:
1. ARM_EQ=1: ignore single requests in DMA-controlled Memory-to-Peripheral accesses.
   ARM_EQ=0: handle single requests like burst requests (in this case DBSize should be 1 access).
   Note: In DMA-controlled Memory-to-Peripheral mode only burst request signals are allowed.
         The behaviour of single requests (from peripheral to DMAC) is not defined.
         Modules generating single requests anyways might use ARM_EQ=0 in combination with DBSize=000.
2. ARM_EQ=1: Always read 0 from TransferSize in this register.
   ARM_EQ=0: Read some internal value for debug purposes
23 - 21 "000"
DWidth
Destination transfer width:
The source and destination widths can be different from each other.
The hardware automatically packs and unpacks the data as required.
_________________________
bit_value      data_width
-------------------------
 000             8 bit
 001            16 bit
 010            32 bit
=========================
20 - 18 "000"
SWidth
Source transfer width:
The source and destination widths can be different from each other.
The hardware automatically packs and unpacks the data as required.
_________________________
bit_value      data_width
-------------------------
 000             8 bit
 001            16 bit
 010            32 bit
=========================
17 - 15 "000"
DBSize
Destination burst size:
Indicates the number of transfers which make up a destination burst transfer request.
This value must be set to the burst size of the destination peripheral, or if the destination is memory, to the memory boundary size.
The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the destination peripheral.
The burst size is not related to the AHB HBURST signal.
Note: If flow controller is DMAC and destination is a peripheral, only bursts are transferred to the peripheral (DMACxSREQ is ignored if set by peripheral).
      The source burst size has no such limitation.
________________________________
bit_value    burst_transfer_size
--------------------------------
 000         1
 001         4
 010         8
 011         16
 100         32
 101         64
 110         128
 111         256
================================
14 - 12 "000"
SBSize
Source burst size:
Indicates the number of transfers which make up a source burst.
This value must be set to the burst size of the source peripheral, or if the source is memory, to the memory boundary size.
The burst size is the amount of data that is transferred when the DMACxBREQ signal goes active in the source peripheral.
The burst size is not related to the AHB HBURST signal.
________________________________
bit_value    burst_transfer_size
--------------------------------
 000         1
 001         4
 010         8
 011         16
 100         32
 101         64
 110         128
 111         256
================================
11 - 0 0x0
TransferSize
Transfer size:
For writes, this field indicates the number of (Source width) transfers to perform when the DMAC is the flow controller.
For reads, the transfer size indicates the number of transfers completed on the destination bus.
Reading the register when the channel is active does not give useful information,
as by the time that the software has processed the value read,
the channel might have progressed.
It is intended to be used only when a channel is enabled and then disabled.
If the DMAC controller is not the flow controller the transfer size should be set to 0.


dmac_chcfg
channel configuration registers
R/W
0x00000000
Address@app_dmac0_dmac_ch0 : 0x40081110
Address@app_dmac0_dmac_ch1 : 0x40081130
Address@app_dmac0_dmac_ch2 : 0x40081150
Address@app_dmac0_dmac_ch3 : 0x40081170
Address@app_dmac1_dmac_ch0 : 0x40082110
Address@app_dmac1_dmac_ch1 : 0x40082130
Address@app_dmac1_dmac_ch2 : 0x40082150
Address@app_dmac1_dmac_ch3 : 0x40082170
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 "0"
H
Halt: 0 = allow DMA requests 1 = ignore further source DMA requests. The contents of the channels FIFO are drained.
This value can be used with the Active and Channel Enable bits to cleanly disable a DMA channel.
17 "0"
A
Active: 0 = there is no data in the FIFO of the channel 1 = the FIFO of the channel has data. (ro)
This value can be used with the Halt and Channel Enable bits to cleanly disable a DMA channel.
16 "0"
L
Lock. When set this bit enables locked transfers.
15 "0"
ITC
Terminal count interrupt mask. When cleared this bit masks out the terminal count interrupt of the relevant channel.
14 "0"
IE
Interrupt error mask. When cleared this bit masks out the error interrupt of the relevant channel.
13 - 11 "000"
FlowCntrl
Flow control and transfer type. This value is used to indicate the flow controller and transfer type.
The flow controller can be the DMAC, the source peripheral, or the destination peripheral.
The transfer type can be either memory-to-memory, memory-to-peripheral, peripheral-to-memory, or peripheral-to-peripheral.
_______________________________________________________________________
bit_value     transfer_type                                  controller
-----------------------------------------------------------------------
000           Memory-to-memory                               DMAC
001           Memory-to-peripheral                           DMAC
010           Peripheral-to-memorys                          DMAC
011           Source peripheral-to-destination peripheral    DMAC (not supported in netX system)
100           Source peripheral-to-destination peripheral    Destination peripheral (not supported in netX system)
101           Memory-to-peripheral                           Peripheral
110           Peripheral-to-memory                           Peripheral
111           Source peripheral-to-destination peripheral    Source peripheral (not supported in netX system)
========================================================================
Note: Peripheral-to-peripheral transfers are configurable, but not supported in the netX system. Don't use these
three modes.
10 0
-
 reserved
9 - 6 "0000"
DestPeripheral
Destination peripheral. This value selects the DMA destination request peripheral.
This field is ignored if the destination of the transfer is to memory.
For mapping of peripheral to value see 'SrcPeripheral' bit-field in this register.
5 0
-
 reserved
4 - 1 "0000"
SrcPeripheral
Source peripheral. This value selects the DMA source request peripheral.
This field is ignored if the source of the transfer is from memory.
value  peripheral
0  app_uart0_rx
1  app_uart0_tx
2  app_uart1_rx
3  app_uart1_tx
4  app_spi0_rx
5  app_spi0_tx
6  app_spi1_rx
7  app_spi1_tx
8  app_sqi0_rx
9  app_sqi0_tx
10  app_sqi1_rx
11  app_sqi1_tx
12  reserved
13  reserved
14  reserved
15  reserved
0 "0"
E
Channel enable. Reading this bit indicates whether a channel is currently enabled or disabled: 0 = channel disabled 1 = channel enabled.
The Channel Enable bit status can also be found by reading the DMACEnbldChns register.
A channel is enabled by setting this bit. Before enabling a single channel the DMA controller must be enabled globally by setting the DMACENABLE bit in the dmac_config register.
Enabling a channel while the controller is disabled leads to undefined behaviour. A channel can be disabled by clearing the Enable bit.
This causes the current AHB transfer (if one is in progress) to complete and the channel is then disabled.
Any data in the channels FIFO is lost.
Restarting the channel by simply setting the Channel Enable bit has unpredictable effects and the channel must be fully re-initialized.
The channel is also disabled, and Channel Enable bit cleared, when the last LLI is reached or if a channel error is encountered.
If a channel has to be disabled without losing data in a channels FIFO the Halt bit must be set so that further DMA requests are ignored.
The Active bit must then be polled until it reaches 0, indicating that there is no data left in the channels FIFO.
Finally the Channel Enable bit can be cleared.



Base Address Area: dmac_reg, app_dmac0_dmac_reg, app_dmac1_dmac_reg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R dmac_int_status
1 4 R dmac_inttc_status
2 8 W dmac_inttc_clear
3 c R dmac_interr_status
4 10 W dmac_interr_clear
5 14 R dmac_rawinttc_status
6 18 R dmac_rawinterr_status
7 1c R dmac_enabled_channel
8 20 R/W dmac_softb_req
9 24 R/W dmac_softs_req
a 28 R/W dmac_softlb_req
b 2c R/W dmac_softls_req
c 30 R/W dmac_config
d 34 R/W dmac_sync
e-1ff 38-7fc -  reserved

dmac_int_status
interrupt status register
R
Address@dmac_reg : 0x40081800
Address@app_dmac0_dmac_reg : 0x40081800
Address@app_dmac1_dmac_reg : 0x40082800
Bits Name Description
31 - 4 -
 reserved
3 DMACINT_ch3
Status of DMA channel 3 - interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINT_ch2
Status of DMA channel 2 - interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINT_ch1
Status of DMA channel 1 - interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINT_ch0
Status of DMA channel 0 - interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_inttc_status
interrupt terminal count status register
R
Address@dmac_reg : 0x40081804
Address@app_dmac0_dmac_reg : 0x40081804
Address@app_dmac1_dmac_reg : 0x40082804
Bits Name Description
31 - 4 -
 reserved
3 DMACINTTC_ch3
Status of DMA channel 3 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINTTC_ch2
Status of DMA channel 2 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINTTC_ch1
Status of DMA channel 1 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINTTC_ch0
Status of DMA channel 0 - terminal count interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_inttc_clear
interrupt terminal count clear register
W
0x00000000
Address@dmac_reg : 0x40081808
Address@app_dmac0_dmac_reg : 0x40081808
Address@app_dmac1_dmac_reg : 0x40082808
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
DMACINTTCCLR_ch3
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 3 ,1'b0 have no effect.
2 "0"
DMACINTTCCLR_ch2
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 2 ,1'b0 have no effect.
1 "0"
DMACINTTCCLR_ch1
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 1 ,1'b0 have no effect.
0 "0"
DMACINTTCCLR_ch0
Writing a 1'b1 Bit clears the terminal count interrupt of the specific channel 0 ,1'b0 have no effect.


dmac_interr_status
interrupt error status register
R
Address@dmac_reg : 0x4008180c
Address@app_dmac0_dmac_reg : 0x4008180c
Address@app_dmac1_dmac_reg : 0x4008280c
Bits Name Description
31 - 4 -
 reserved
3 DMACINTERR_ch3
Status of DMA channel 3 - error interrupt after masking. 1'b1 indicates an active interrupt request.
2 DMACINTERR_ch2
Status of DMA channel 2 - error interrupt after masking. 1'b1 indicates an active interrupt request.
1 DMACINTERR_ch1
Status of DMA channel 1 - error interrupt after masking. 1'b1 indicates an active interrupt request.
0 DMACINTERR_ch0
Status of DMA channel 0 - error interrupt after masking. 1'b1 indicates an active interrupt request.


dmac_interr_clear
interrupt error clear register
W
0x00000000
Address@dmac_reg : 0x40081810
Address@app_dmac0_dmac_reg : 0x40081810
Address@app_dmac1_dmac_reg : 0x40082810
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
DMACINTERRCLR_ch3
Writing a 1'b1 Bit clears the error interrupt of the specific channel 3 ,1'b0 have no effect.
2 "0"
DMACINTERRCLR_ch2
Writing a 1'b1 Bit clears the error interrupt of the specific channel 2 ,1'b0 have no effect.
1 "0"
DMACINTERRCLR_ch1
Writing a 1'b1 Bit clears the error interrupt of the specific channel 1 ,1'b0 have no effect.
0 "0"
DMACINTERRCLR_ch0
Writing a 1'b1 Bit clears the error interrupt of the specific channel 0 ,1'b0 have no effect.


dmac_rawinttc_status
raw interrupt terminal count status register
R
Address@dmac_reg : 0x40081814
Address@app_dmac0_dmac_reg : 0x40081814
Address@app_dmac1_dmac_reg : 0x40082814
Bits Name Description
31 - 4 -
 reserved
3 DMACRAWINTTC_ch3
Status of DMA channel 3 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
2 DMACRAWINTTC_ch2
Status of DMA channel 2 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
1 DMACRAWINTTC_ch1
Status of DMA channel 1 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.
0 DMACRAWINTTC_ch0
Status of DMA channel 0 - terminal count interrupt prior to masking. 1'b1 indicates an active interrupt request.


dmac_rawinterr_status
raw interrupt error status register
R
Address@dmac_reg : 0x40081818
Address@app_dmac0_dmac_reg : 0x40081818
Address@app_dmac1_dmac_reg : 0x40082818
Bits Name Description
31 - 4 -
 reserved
3 DMACRAWINTERR_ch3
Status of DMA channel 3 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
2 DMACRAWINTERR_ch2
Status of DMA channel 2 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
1 DMACRAWINTERR_ch1
Status of DMA channel 1 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.
0 DMACRAWINTERR_ch0
Status of DMA channel 0 - error interrupt prior to masking. 1'b1 indicates an active interrupt request.


dmac_enabled_channel
channel enable register
R
Address@dmac_reg : 0x4008181c
Address@app_dmac0_dmac_reg : 0x4008181c
Address@app_dmac1_dmac_reg : 0x4008281c
Bits Name Description
31 - 4 -
 reserved
3 DMACENABLEDCHNS_ch3
Status DMA channel 3 enable
2 DMACENABLEDCHNS_ch2
Status DMA channel 2 enable
1 DMACENABLEDCHNS_ch1
Status DMA channel 1 enable
0 DMACENABLEDCHNS_ch0
Status DMA channel 0 enable


dmac_softb_req
software burst request register
R/W
0x00000000
Address@dmac_reg : 0x40081820
Address@app_dmac0_dmac_reg : 0x40081820
Address@app_dmac1_dmac_reg : 0x40082820
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
DMACSoftBReq
Software burst request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA burst transfers.


dmac_softs_req
software single request register
R/W
0x00000000
Address@dmac_reg : 0x40081824
Address@app_dmac0_dmac_reg : 0x40081824
Address@app_dmac1_dmac_reg : 0x40082824
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
DMACSoftSReq
Software single request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA single transfers.


dmac_softlb_req
software last burst request register
R/W
0x00000000
Address@dmac_reg : 0x40081828
Address@app_dmac0_dmac_reg : 0x40081828
Address@app_dmac1_dmac_reg : 0x40082828
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
DMACSoftLBReq
Software last burst request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA last burst transfers.


dmac_softls_req
software last single request register
R/W
0x00000000
Address@dmac_reg : 0x4008182c
Address@app_dmac0_dmac_reg : 0x4008182c
Address@app_dmac1_dmac_reg : 0x4008282c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
DMACSoftLSReq
Software last single request. A DMA request can be generated for each source by writing a 1'b1 to the corresponding register bit.
Reading the register indicates which sources are requesting DMA last single transfers.


dmac_config
configuration register
R/W
0x00000000
Address@dmac_reg : 0x40081830
Address@app_dmac0_dmac_reg : 0x40081830
Address@app_dmac1_dmac_reg : 0x40082830
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
DMACENABLE
DMAC enable: 0 = disabled 1 = enabled. This bit is reset to 0. Disabling the DMAC reduces power consumption.


dmac_sync
sync register
DMA synchronization logic for DMA request signals enabled or disabled
A 1'b0 bit indicates that the synchronization logic for
the DMACBREQ[15:0], DMACSREQ[15:0], DMACLBREQ[15:0], and DMACLSREQ[15:0] request signals is enabled.
A HIGH bit indicates that the synchronization logic is disabled.
Note: Within the netX system all peripherals and the DMAC are running in the same clock-domain. Therefore,
it is recommended to disable the synchronisation for all channels (i.e. write 0xffff). This results in a
performance gain.
R/W
0x00000000
Address@dmac_reg : 0x40081834
Address@app_dmac0_dmac_reg : 0x40081834
Address@app_dmac1_dmac_reg : 0x40082834
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
DIS_SYNC
Disable sync register peripheral requests.



Base Address Area: gem_gxl_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_gem_gxl_top_0_mbist_power0
1 4 R/W gen_ram_ctrl_gem_gxl_top_0_mbist_power1
2 8 R/W gen_ram_ctrl_gem_gxl_top_0_mbist_power2
3 c R/W gen_ram_ctrl_gem_gxl_top_0_mbist_power3
4-1ff 10-7fc -  reserved
200 800 R/W gen_ram_ctrl_gem_gxl_top_0_ecc0
201-27f 804-9fc -  reserved
280 a00 R gen_ram_ctrl_gem_gxl_top_0_ecc_status_corr0
281-2ff a04-bfc -  reserved
300 c00 R gen_ram_ctrl_gem_gxl_top_0_ecc_status_noncorr0
301-37f c04-dfc -  reserved
380 e00 R/W gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_gem_gxl_top_0_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_gem_gxl_top_0_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_gem_gxl_top_0_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_gem_gxl_top_0_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_gem_gxl_top_0_mbist_power0
MBIST/power control and status register
For memory gem_gxl_emac_rxspram_i (2048x128 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x400c8000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gem_gxl_top_0_mbist_power1
MBIST/power control and status register
For memory gem_gxl_emac_txspram_i (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x400c8004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gem_gxl_top_0_mbist_power2
MBIST/power control and status register
For memory gem_gxl_rxspram_i (2048x128 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x400c8008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gem_gxl_top_0_mbist_power3
MBIST/power control and status register
For memory gem_gxl_txspram_i (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x400c800c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_gem_gxl_top_0_ecc0
ECC control and status register
Dummy register, no ECC RAMs in the design.
R/W
0x00000000
Address : 0x400c8800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_gem_gxl_top_0_ecc_status_corr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address : 0x400c8a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gem_gxl_top_0_ecc_status_noncorr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address : 0x400c8c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x400c8e00
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gem_gxl_top_0_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0).
R/W
0x00000000
Address : 0x400c8e40
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gem_gxl_top_0_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_gem_gxl_top_0_irq_raw_reg0
R/W
0x00000000
Address : 0x400c8e80
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gem_gxl_top_0_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 6 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_0_err_ecc_correctable
  2 : irq_reg0-mem_0_mbist_or_init_finished
  3 : irq_reg0-mem_1_mbist_or_init_finished
  4 : irq_reg0-mem_2_mbist_or_init_finished
  5 : irq_reg0-mem_3_mbist_or_init_finished
  6 : no active IRQ
R/W
0x00000000
Address : 0x400c8ec0
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_gem_gxl_top_0_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x400c8efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: mot_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_7_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_7_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_7_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_7_mbist_power3
4-1ff 10-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_7_ecc0
201-27f 804-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_7_ecc_status_corr0
281-2ff a04-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_7_ecc_status_noncorr0
301-37f c04-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_7_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_7_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_7_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_7_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_7_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_7_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.mot_i.mot_ahbl_bus_logic_i.intram0_mot_i.gen_ram_hsoc_i (16384x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x48044000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_7_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.mot_i.mot_ahbl_bus_logic_i.intram1_mot_i.gen_ram_hsoc_i (16384x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x48044004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_7_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.mot_i.mot_ahbl_bus_logic_i.intram2_mot_i.gen_ram_hsoc_i (16384x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x48044008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_7_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.mot_i.mot_ahbl_bus_logic_i.intram3_mot_i.gen_ram_hsoc_i (16384x32 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x4804400c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_7_ecc0
ECC control and status register
Dummy register, no ECC RAMs in the design.
R/W
0x00000000
Address : 0x48044800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_7_ecc_status_corr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address : 0x48044a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_7_ecc_status_noncorr0
ECC status register
Dummy register, no ECC RAMs in the design.
R
Address : 0x48044c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_7_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x48044e00
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_7_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_7_irq_raw_reg0).
R/W
0x00000000
Address : 0x48044e40
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_7_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_7_irq_raw_reg0
R/W
0x00000000
Address : 0x48044e80
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_7_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 6 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_0_err_ecc_correctable
  2 : irq_reg0-mem_0_mbist_or_init_finished
  3 : irq_reg0-mem_1_mbist_or_init_finished
  4 : irq_reg0-mem_2_mbist_or_init_finished
  5 : irq_reg0-mem_3_mbist_or_init_finished
  6 : no active IRQ
R/W
0x00000000
Address : 0x48044ec0
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_7_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x48044efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: mot_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_ctrl_cfg
1 4 R/W mot_ctrl_singen_sync
2 8 R/W mot_ctrl_sdmf0_sync
3 c R/W mot_ctrl_sdmf1_sync
4 10 R/W mot_ctrl_sdmf2_sync
5 14 R/W mot_ctrl_cpu0_boot_addr
6 18 R/W mot_ctrl_cpu0_mtvec_addr
7 1c R/W mot_ctrl_cpu0_dm_halt_addr
8 20 R/W mot_ctrl_cpu0_dm_exception_addr
9 24 R/W mot_ctrl_cpu1_boot_addr
a 28 R/W mot_ctrl_cpu1_mtvec_addr
b 2c R/W mot_ctrl_cpu1_dm_halt_addr
c 30 R/W mot_ctrl_cpu1_dm_exception_addr
d 34 R/W mot_ctrl_cpu_ctrl
e 38 R mot_ctrl_cpu_status
f 3c -  reserved

mot_ctrl_cfg
Configurations for the sources of MENC encoder signals and
MPWM error condition input (mpwm_eci)
R/W
0x00000001
Address : 0x49000000
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
enc1_src
0: enc1_* source is external input
1: enc1_a source is sdmf1_wc0
enc1_b source is sdmf1_wc1
4 "0"
enc0_src
Select source for encoder signals enc0_a and
enc0_b (enc0_n source is always external input)
0: enc0_* source is external input
1: enc0_a source is sdmf0_wc0
enc0_b source is sdmf0_wc1
3 - 0 "0001"
eci_src
Set bits to 1 to enable individual source signals
for MPWM error condition input. Enabled source
signals are OR'ed to generate mpwm_eci.
0: mpwm_fail_in (external input)
1: sdmf0_eco
2: sdmf1_eco
3: sdmf2_eco


mot_ctrl_singen_sync
Configuration for the singen hardware sync strobe.
R/W
0x0001ffff
Address : 0x49000004
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 - 0 0x1ffff
src
sync strobe condition to reset singen output
0x0...0x0FFFF: sync at (ECNT == val)
0x10000: posedge of xc_trigger[0]
0x10001: posedge of xc_trigger[1]
0x10002: negedge of xc_trigger[0]
0x10003: negedge of xc_trigger[1]
0x10004: posedge of xc_sample[0]
0x10005: posedge of xc_sample[1]
0x10006: negedge of xc_sample[0]
0x10007: negedge of xc_sample[1]
0x10008...0x1FFFF: hardware sync disabled


mot_ctrl_sdmf0_sync
Configuration for the sdmf0 hardware sync strobe source
R/W
0x0001ffff
Address : 0x49000008
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 - 0 0x1ffff
src
sync strobe condition to start sum/record
0x0...0x0FFFF: sync at (ECNT == val)
0x1...0x1FFFF: hardware sync disabled


mot_ctrl_sdmf1_sync
Configuration for the sdmf1 hardware sync strobe source
R/W
0x0001ffff
Address : 0x4900000c
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 - 0 0x1ffff
src
sync strobe condition to start sum/record
0x0...0x0FFFF: sync at (ECNT == val)
0x1...0x1FFFF: hardware sync disabled


mot_ctrl_sdmf2_sync
Configuration for the sdmf2 hardware sync strobe source
R/W
0x0001ffff
Address : 0x49000010
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 - 0 0x1ffff
src
sync strobe condition to start sum/record
0x0...0x0FFFF: sync at (ECNT == val)
0x1FFFF: hardware disabled


mot_ctrl_cpu0_boot_addr
Boot address for CPU0. First program counter after reset = addr.
Must be half-word aligned. Do not change while CPU0 instruction
fetch is enabled.
R/W
0x00000000
Address : 0x49000014
Bits Reset value Name Description
31 - 1 0x0
val
boot address value
0 0
-
 reserved


mot_ctrl_cpu0_mtvec_addr
mtvec address for CPU0. Initial value for the address part of Machine
Trap-Vector Base Address (mtvec), 256-byte aligned. Do not
change while CPU0 instruction fetch is enabled.
R/W
0x00000000
Address : 0x49000018
Bits Reset value Name Description
31 - 8 0x0
val
mtvec address value
7 - 0 0
-
 reserved


mot_ctrl_cpu0_dm_halt_addr
Address to jump to for CPU0 when entering Debug Mode
Must be word-aligned. Do not change while CPU0 instruction
fetch is enabled.
R/W
0x00000000
Address : 0x4900001c
Bits Reset value Name Description
31 - 2 0x0
val
dm_halt address value
1 - 0 0
-
 reserved


mot_ctrl_cpu0_dm_exception_addr
Word-aligned address to jump to for CPU0 when an exception occurs
when executing code during Debug Mode. Do not change while CPU1
instruction fetch is enabled.
R/W
0x00000000
Address : 0x49000020
Bits Reset value Name Description
31 - 2 0x0
val
dm_exception address value
1 - 0 0
-
 reserved


mot_ctrl_cpu1_boot_addr
Halfword-aligned Boot address for CPU1. First program counter after reset = addr.
Must be half-word aligned. Do not change while CPU1 instruction
fetch is enabled.
R/W
0x00000000
Address : 0x49000024
Bits Reset value Name Description
31 - 1 0x0
val
boot address value
0 0
-
 reserved


mot_ctrl_cpu1_mtvec_addr
mtvec address for CPU1. Initial value for the address part of Machine
Trap-Vector Base Address (mtvec), 256-byte aligned. Do not
change while CPU1 instruction fetch is enabled.
R/W
0x00000000
Address : 0x49000028
Bits Reset value Name Description
31 - 8 0x0
val
mtvec address value
7 - 0 0
-
 reserved


mot_ctrl_cpu1_dm_halt_addr
Address to jump to for CPU1 when entering Debug Mode
Must be word-aligned. Do not change while CPU1 instruction
fetch is enabled.
R/W
0x00000000
Address : 0x4900002c
Bits Reset value Name Description
31 - 2 0x0
val
dm_halt address value
1 - 0 0
-
 reserved


mot_ctrl_cpu1_dm_exception_addr
Word-aligned address to jump to for CPU1 when an exception occurs
when executing code during Debug Mode. Do not change while CPU1
instruction fetch is enabled.
R/W
0x00000000
Address : 0x49000030
Bits Reset value Name Description
31 - 2 0x0
val
dm_exception address value
1 - 0 0
-
 reserved


mot_ctrl_cpu_ctrl
control CPU0/CPU1 reset and instruction fetch.
R/W
0x00000000
Address : 0x49000034
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
cpu1_enif
" "
2 "0"
cpu1_nres
" "
1 "0"
cpu0_enif
Set to 1 to enable CPU0 instruction fetch by
asserting input signal fetch_enable_i.
The first instruction fetch after reset de-
assertion will not happen as long as this signal
is 0. fetch_enable_i needs to be set to 1 for at
least one cycle while not in reset to enable
fetching. Once fetching has been enabled the value
fetch_enable_i is ignored.
0 "0"
cpu0_nres
CPU0 is held in reset while this field
has a value of 0. Write 1 to leave reset.


mot_ctrl_cpu_status
Status of CPU0/CPU1. For details on sleeping see
https://cv32e40p.readthedocs.io/en/latest/sleep/
R
Address : 0x49000038
Bits Name Description
31 - 2 -
 reserved
1 cpu1_sleeping
1: CPU1 is sleeping
0 cpu0_sleeping
1: CPU0 is sleeping



Base Address Area: singen

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W singen_cfg
1 4 R/W singen_demod_cfg
2 8 W singen_cmd
3 c R/W singen_inc
4 10 R/W singen_acc
5 14 R/W singen_phase
6 18 R singen_phase_acc_rs
7 1c R/W singen_dac

singen_cfg
R/W
0x00000000
Address : 0x49000040
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 - 8 "00000"
sdm_div
divider for the SDM modulator: fmod = fsys / (2 + sdm_div)
7 - 4 "0000"
ampli_coeff
unsigned amplitude scale
3 "0"
ampli_en
1: sinus table output is scaled by ampli_coeff
2 0
-
 reserved
1 "0"
sync_en
1: sync input enabled.
Sync will restart sinus (set PHASE to 0 and ACC to 0) and capture the current PHASE and ACC in PHASE_ACC_RS
0 "0"
en
1: enable sinus generator and modulator


singen_demod_cfg
R/W
0x00000000
Address : 0x49000044
Bits Reset value Name Description
31 - 15 0
-
 reserved
14 "0"
val

13 - 7 "0000000"
phase_high

6 - 0 "0000000"
phase_low
if phase_low <= PHASE < phase_high then demod_out = val else demod_out = ~val
PHASE is constantly monitored, i.e. demod_out is also correctly updated when a sync occurs.
Note that this allows the definition of a demodulation window wrapping over the PHASE.


singen_cmd
W
0x00000000
Address : 0x49000048
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
sync
1: trigger a sync


singen_inc
R/W
0x00000000
Address : 0x4900004c
Bits Reset value Name Description
31 - 0 0x0
val
speed of the generated sinus


singen_acc
R/W
0x00000000
Address : 0x49000050
Bits Reset value Name Description
31 - 0 0x0
val
When CFG.en=1: ACC = ACC + INC in every clock cycle.


singen_phase
R/W
0x00000000
Address : 0x49000054
Bits Reset value Name Description
31 - 7 0
-
 reserved
6 - 0 "0000000"
val
phase of the sinus. Full range corresponds to 0..2PI. Incremented every time ACC overflows.


singen_phase_acc_rs
Captures the PHASE and ACC register when a SYNC pulse occurs.
R
Address : 0x49000058
Bits Name Description
31 - 7 acc
ACC[31:7] at the last sync
6 - 0 phase
PHASE at the last sync


singen_dac
R/W
0x00000000
Address : 0x4900005c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
val
input value of the SDM modulator. Updated by HW at every change of PHASE. To control the SDM modulator output by software set INC to 0.



Base Address Area: sdmf0, sdmf1, sdmf2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sdmf_cfg
1 4 R/W sdmf_bq_cfg_0
2 8 R/W sdmf_bq_cfg_1
3 c R/W sdmf_bq_cfg_2
4 10 R/W sdmf_bq_cfg_3
5 14 R/W sdmf_wc_cfg
6 18 R/W sdmf_wc_thr_0
7 1c R/W sdmf_wc_thr_1
8 20 R/W sdmf_wc_thr_2
9 24 R/W sdmf_wc_thr_3
a 28 R/W sdmf_sr_cfg
b 2c R/W sdmf_dma_acc_lo
c 30 R/W sdmf_dma_acc_hi
d 34 R/W sdmf_s_cfg
e 38 R/W sdmf_r_cfg
f 3c R/W sdmf_sadr_ws
10 40 R/W sdmf_radr_ws
11 44 W sdmf_cmd
12 48 R/W sdmf_en
13 4c R sdmf_cic_0
14 50 R sdmf_cic_1
15 54 R sdmf_cic_2
16 58 R sdmf_cic_3
17 5c R sdmf_bq0_0
18 60 R sdmf_bq0_1
19 64 R sdmf_bq0_2
1a 68 R sdmf_bq0_3
1b 6c R sdmf_bq1_0
1c 70 R sdmf_bq1_1
1d 74 R sdmf_bq1_2
1e 78 R sdmf_bq1_3
1f 7c R sdmf_bq2_0
20 80 R sdmf_bq2_1
21 84 R sdmf_bq2_2
22 88 R sdmf_bq2_3
23 8c R sdmf_wc
24 90 R sdmf_sadr
25 94 R sdmf_radr
26 98 R sdmf_dtime_now
27 9c R sdmf_dtime
28 a0 R sdmf_sum_0
29 a4 R sdmf_sum_1
2a a8 R sdmf_sum_2
2b ac R sdmf_sum_3
2c b0 R/W sdmf_irq_raw
2d b4 R/W sdmf_irq_masked
2e b8 R/W sdmf_irq_mask_set
2f bc R/W sdmf_irq_mask_rst
30 c0 R/W sdmf_ch_bq_sel
31 c4 R/W sdmf_bq0_cfg
32 c8 R/W sdmf_bq1_cfg
33 cc R/W sdmf_bq2_cfg
34 d0 R/W sdmf_bq0_gain_cfg
35 d4 R/W sdmf_bq1_gain_cfg
36 d8 R/W sdmf_bq2_gain_cfg
37-3f dc-fc -  reserved

sdmf_cfg
Static configuration for SDM clock generator and CIC filter. May only be changed when EN.sdm_clk_en=0 or EN.cic_bq_en=0, respectively.
R/W
0x00000000
Address@sdmf0 : 0x49000100
Address@sdmf1 : 0x49000200
Address@sdmf2 : 0x49000300
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 - 24 "00000"
cic_shift
0..21: CIC output shifted by this value and then saturated to 22 bits
23 - 20 "0000"
cic_dr
2..15: decimation rate of the CIC filter.
19 - 17 "000"
cic_order
1..4: order of the CIC filter.
16 - 9 "00000000"
ssphase
sphase when sdm_d is sampled.
8 "0"
rf_sel
0: sample sdm_d with rising clk_fr
1: sample sdm_d with falling clk_fr
7 - 0 "00000000"
sdm_clk_period
period of the generated sdm_clk in clk_fe cycles.


sdmf_bq_cfg_0
Configurations for the biquad filters. BQ_CFG_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000104
Address@sdmf1 : 0x49000204
Address@sdmf2 : 0x49000304
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 12 "000000"
bq2

11 - 6 "000000"
bq1

5 - 0 "000000"
bq0
bq0 configuration number


sdmf_bq_cfg_1
Configurations for the biquad filters. BQ_CFG_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000108
Address@sdmf1 : 0x49000208
Address@sdmf2 : 0x49000308
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 12 "000000"
bq2

11 - 6 "000000"
bq1

5 - 0 "000000"
bq0
bq0 configuration number


sdmf_bq_cfg_2
Configurations for the biquad filters. BQ_CFG_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x4900010c
Address@sdmf1 : 0x4900020c
Address@sdmf2 : 0x4900030c
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 12 "000000"
bq2

11 - 6 "000000"
bq1

5 - 0 "000000"
bq0
bq0 configuration number


sdmf_bq_cfg_3
Configurations for the biquad filters. BQ_CFG_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000110
Address@sdmf1 : 0x49000210
Address@sdmf2 : 0x49000310
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 12 "000000"
bq2

11 - 6 "000000"
bq1

5 - 0 "000000"
bq0
bq0 configuration number


sdmf_wc_cfg
Window comparator and error condition output configurations.
R/W
0x00000000
Address@sdmf0 : 0x49000114
Address@sdmf1 : 0x49000214
Address@sdmf2 : 0x49000314
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 "0"
eco_lt_3

18 "0"
eco_gt_3

17 "0"
winv_3

16 - 15 "00"
wsrc_3

14 "0"
eco_lt_2

13 "0"
eco_gt_2

12 "0"
winv_2

11 - 10 "00"
wsrc_2

9 "0"
eco_lt_1

8 "0"
eco_gt_1

7 "0"
winv_1

6 - 5 "00"
wsrc_1

4 "0"
eco_lt_0
1: eco is asserted when BQ is smaller than lower threshold
3 "0"
eco_gt_0
1: eco is asserted when BQ exceeds upper threshold
2 "0"
winv_0
1: invert window comparator output
1 - 0 "00"
wsrc_0
0..2: Window comparator uses output of BQ?


sdmf_wc_thr_0
Window comparator thresholds. WC_THR_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000118
Address@sdmf1 : 0x49000218
Address@sdmf2 : 0x49000318
Bits Reset value Name Description
31 - 16 0x0
ht
window comparator high threshold
15 - 0 0x0
lt
window comparator low threshold


sdmf_wc_thr_1
Window comparator thresholds. WC_THR_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x4900011c
Address@sdmf1 : 0x4900021c
Address@sdmf2 : 0x4900031c
Bits Reset value Name Description
31 - 16 0x0
ht
window comparator high threshold
15 - 0 0x0
lt
window comparator low threshold


sdmf_wc_thr_2
Window comparator thresholds. WC_THR_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000120
Address@sdmf1 : 0x49000220
Address@sdmf2 : 0x49000320
Bits Reset value Name Description
31 - 16 0x0
ht
window comparator high threshold
15 - 0 0x0
lt
window comparator low threshold


sdmf_wc_thr_3
Window comparator thresholds. WC_THR_N corresponds to sdm_d[N].
R/W
0x00000000
Address@sdmf0 : 0x49000124
Address@sdmf1 : 0x49000224
Address@sdmf2 : 0x49000324
Bits Reset value Name Description
31 - 16 0x0
ht
window comparator high threshold
15 - 0 0x0
lt
window comparator low threshold


sdmf_sr_cfg
Static configuration for summing and recording of samples.
R/W
0x00000000
Address@sdmf0 : 0x49000128
Address@sdmf1 : 0x49000228
Address@sdmf2 : 0x49000328
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 14 "00000000"
rskip
0: record every sample
1: record every 2nd sample
2: record every 3rd sample
...
13 - 12 "00"
bq_init
0: biquad filter is not initalized
1: biquad filter is initalized with 0
2: biquad filter is initalized with result of CIC filter
11 - 7 "00000"
cic_skip
0..MAX: number of CIC samples to skip until biquad is initalized
6 "0"
cic_init
1: CIC filter is cleared at start of sum/record
5 "0"
r32
0: record 16 bit samples
1: record 32 bit samples
4 - 2 "000"
sr_no
1..4 : numbers of SDM channel to sum and record
1 - 0 "00"
sr_src
0..2 : SUM and record use output of BQ?


sdmf_dma_acc_lo
Static configuration for memory access boundaries when summing and recording
R/W
0x00000000
Address@sdmf0 : 0x4900012c
Address@sdmf1 : 0x4900022c
Address@sdmf2 : 0x4900032c
Bits Reset value Name Description
31 - 4 0x0
val
lower boundary for DMA access control, 16 byte precision (writes outside range provided by DMA_ACC_LO and DMA_ACC_HI are discarded and assert IRQ_RAW.dma_accviol_evt)
3 - 0 0
-
 reserved


sdmf_dma_acc_hi
Static configuration for memory access boundaries when summing and recording
R/W
0x00000000
Address@sdmf0 : 0x49000130
Address@sdmf1 : 0x49000230
Address@sdmf2 : 0x49000330
Bits Reset value Name Description
31 - 4 0x0
val
upper boundary for DMA access control, 16 byte precision (see DMA_ACC_LO).
3 - 0 0
-
 reserved


sdmf_s_cfg
Static configuration common for summing of samples.
R/W
0x00000000
Address@sdmf0 : 0x49000134
Address@sdmf1 : 0x49000234
Address@sdmf2 : 0x49000334
Bits Reset value Name Description
31 - 16 0x0
sno
number of samples to sum.
15 - 0 0x0
soffset
number of samples to skip before summing


sdmf_r_cfg
Static configuration common for recording of samples.
R/W
0x00000000
Address@sdmf0 : 0x49000138
Address@sdmf1 : 0x49000238
Address@sdmf2 : 0x49000338
Bits Reset value Name Description
31 - 16 0x0
rno
number of samples to record. Must be even, LSB is ignored.
15 - 0 0x0
roffset
number of samples to skip before recording.


sdmf_sadr_ws
Transferred to SADR when a sync occurs.
R/W
0x00000000
Address@sdmf0 : 0x4900013c
Address@sdmf1 : 0x4900023c
Address@sdmf2 : 0x4900033c
Bits Reset value Name Description
31 - 2 0x0
adr
" "
1 0
-
 reserved
0 "0"
sen
see SADR


sdmf_radr_ws
Transfered to RADR when a sync occurs.
R/W
0x00000000
Address@sdmf0 : 0x49000140
Address@sdmf1 : 0x49000240
Address@sdmf2 : 0x49000340
Bits Reset value Name Description
31 - 2 0x0
adr
" "
1 0
-
 reserved
0 "0"
ren
see RADR


sdmf_cmd
W
0x00000000
Address@sdmf0 : 0x49000144
Address@sdmf1 : 0x49000244
Address@sdmf2 : 0x49000344
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 14 "00"
wc_3
" "
13 - 12 "00"
wc_2
" "
11 - 10 "00"
wc_1
" "
9 - 8 "00"
wc_0
0: NOP
1: set state of window comparator to 0
2: set state of window comparator to 1
7 - 6 "00"
bq2
" "
5 - 4 "00"
bq1
" "
3 - 2 "00"
bq0
0: NOP
1: init with 0
2: init with CIC output
1 "0"
cic_clr
0: NOP
1: clear CIC filter
0 "0"
sync
0: NOP
1: cause sync pulse


sdmf_en
R/W
0x00000000
Address@sdmf0 : 0x49000148
Address@sdmf1 : 0x49000248
Address@sdmf2 : 0x49000348
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sr_en
0: sum and record FSM is idle
1: enable summing, recording and dma operations
1 "0"
cic_bq_en
1: enable CIC and biquad filters
0 "0"
sdm_clk_en
1: enable sdm_clk generation


sdmf_cic_0
R
Address@sdmf0 : 0x4900014c
Address@sdmf1 : 0x4900024c
Address@sdmf2 : 0x4900034c
Bits Name Description
31 - 0 val
CIC output, sign extended to 32 bits


sdmf_cic_1
R
Address@sdmf0 : 0x49000150
Address@sdmf1 : 0x49000250
Address@sdmf2 : 0x49000350
Bits Name Description
31 - 0 val
CIC output, sign extended to 32 bits


sdmf_cic_2
R
Address@sdmf0 : 0x49000154
Address@sdmf1 : 0x49000254
Address@sdmf2 : 0x49000354
Bits Name Description
31 - 0 val
CIC output, sign extended to 32 bits


sdmf_cic_3
R
Address@sdmf0 : 0x49000158
Address@sdmf1 : 0x49000258
Address@sdmf2 : 0x49000358
Bits Name Description
31 - 0 val
CIC output, sign extended to 32 bits


sdmf_bq0_0
R
Address@sdmf0 : 0x4900015c
Address@sdmf1 : 0x4900025c
Address@sdmf2 : 0x4900035c
Bits Name Description
31 - 0 val
BQ0 output, signed


sdmf_bq0_1
R
Address@sdmf0 : 0x49000160
Address@sdmf1 : 0x49000260
Address@sdmf2 : 0x49000360
Bits Name Description
31 - 0 val
BQ0 output, signed


sdmf_bq0_2
R
Address@sdmf0 : 0x49000164
Address@sdmf1 : 0x49000264
Address@sdmf2 : 0x49000364
Bits Name Description
31 - 0 val
BQ0 output, signed


sdmf_bq0_3
R
Address@sdmf0 : 0x49000168
Address@sdmf1 : 0x49000268
Address@sdmf2 : 0x49000368
Bits Name Description
31 - 0 val
BQ0 output, signed


sdmf_bq1_0
R
Address@sdmf0 : 0x4900016c
Address@sdmf1 : 0x4900026c
Address@sdmf2 : 0x4900036c
Bits Name Description
31 - 0 val
BQ1 output, signed


sdmf_bq1_1
R
Address@sdmf0 : 0x49000170
Address@sdmf1 : 0x49000270
Address@sdmf2 : 0x49000370
Bits Name Description
31 - 0 val
BQ1 output, signed


sdmf_bq1_2
R
Address@sdmf0 : 0x49000174
Address@sdmf1 : 0x49000274
Address@sdmf2 : 0x49000374
Bits Name Description
31 - 0 val
BQ1 output, signed


sdmf_bq1_3
R
Address@sdmf0 : 0x49000178
Address@sdmf1 : 0x49000278
Address@sdmf2 : 0x49000378
Bits Name Description
31 - 0 val
BQ1 output, signed


sdmf_bq2_0
R
Address@sdmf0 : 0x4900017c
Address@sdmf1 : 0x4900027c
Address@sdmf2 : 0x4900037c
Bits Name Description
31 - 0 val
BQ2 output signed


sdmf_bq2_1
R
Address@sdmf0 : 0x49000180
Address@sdmf1 : 0x49000280
Address@sdmf2 : 0x49000380
Bits Name Description
31 - 0 val
BQ2 output signed


sdmf_bq2_2
R
Address@sdmf0 : 0x49000184
Address@sdmf1 : 0x49000284
Address@sdmf2 : 0x49000384
Bits Name Description
31 - 0 val
BQ2 output signed


sdmf_bq2_3
R
Address@sdmf0 : 0x49000188
Address@sdmf1 : 0x49000288
Address@sdmf2 : 0x49000388
Bits Name Description
31 - 0 val
BQ2 output signed


sdmf_wc
Status of window comparators and combined error condition output.
R
Address@sdmf0 : 0x4900018c
Address@sdmf1 : 0x4900028c
Address@sdmf2 : 0x4900038c
Bits Name Description
31 - 13 -
 reserved
12 eco

11 wc_3

10 lt_3

9 gt_3

8 wc_2

7 lt_2

6 gt_2

5 wc_1

4 lt_1

3 gt_1

2 wc_0
state of window comparator
1 lt_0
1 : BQ[CFG.wc_src] _0 < WC_CFG_0.lt
0 gt_0
1 : BQ[CFG.wc_src] _0 > WC_CFG_0.ht


sdmf_sadr
R
Address@sdmf0 : 0x49000190
Address@sdmf1 : 0x49000290
Address@sdmf2 : 0x49000390
Bits Name Description
31 - 2 adr
Start address for storage of dtime and sum. Incremented by HW during recording.
1 -
 reserved
0 sen
1: writing of DTIME and SUM_? enabled


sdmf_radr
R
Address@sdmf0 : 0x49000194
Address@sdmf1 : 0x49000294
Address@sdmf2 : 0x49000394
Bits Name Description
31 - 2 adr
Start address for recording samples. Incremented by HW during recording.
1 -
 reserved
0 ren
1: recording enabled


sdmf_dtime_now
R
Address@sdmf0 : 0x49000198
Address@sdmf1 : 0x49000298
Address@sdmf2 : 0x49000398
Bits Name Description
31 - 0 val
free running incrementing counter, cleared when the first sample to be summed arrives


sdmf_dtime
R
Address@sdmf0 : 0x4900019c
Address@sdmf1 : 0x4900029c
Address@sdmf2 : 0x4900039c
Bits Name Description
31 - 0 val
value of DTIME_NOW when the first sample to be summed became available


sdmf_sum_0
R
Address@sdmf0 : 0x490001a0
Address@sdmf1 : 0x490002a0
Address@sdmf2 : 0x490003a0
Bits Name Description
31 - 0 val
current sum, signed


sdmf_sum_1
R
Address@sdmf0 : 0x490001a4
Address@sdmf1 : 0x490002a4
Address@sdmf2 : 0x490003a4
Bits Name Description
31 - 0 val
current sum, signed


sdmf_sum_2
R
Address@sdmf0 : 0x490001a8
Address@sdmf1 : 0x490002a8
Address@sdmf2 : 0x490003a8
Bits Name Description
31 - 0 val
current sum, signed


sdmf_sum_3
R
Address@sdmf0 : 0x490001ac
Address@sdmf1 : 0x490002ac
Address@sdmf2 : 0x490003ac
Bits Name Description
31 - 0 val
current sum, signed


sdmf_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@sdmf0 : 0x490001b0
Address@sdmf1 : 0x490002b0
Address@sdmf2 : 0x490003b0
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 -
eco
STATUS: error condition outoput (same as module output)
12 -
wc_3
STATUS: output of window comparator 3 (same as module output)
11 -
wc_2
STATUS: output of window comparator 2 (same as module output)
10 -
wc_1
STATUS: output of window comparator 1 (same as module output)
9 -
wc_0
STATUS: output of window comparator 0 (same as module output)
8 "0"
rdma_accviol_evt
EVENT : attempted to write to illegal memory address (constrained by DMA_ACC_LO and DMA_ACC_HI)
7 "0"
rdma_err_evt
EVENT : some samples could not be recorded (have been dropped)
6 "0"
rdone_evt
EVENT : all recorded samples have been written via AHBL
5 "0"
sdone_evt
EVENT : DTIME and SUM have been written via AHBL
4 "0"
snew_evt
EVENT : SUM_? registers have been updated
3 "0"
fil_done_evt
EVENT : BQ*_? registers have been updated
2 -
radr_ws_empty
STATUS: register RADR_WS is empty (transfered to RADR) and can be written
1 -
sadr_ws_empty
STATUS: register SADR_WS is empty (transfered to SADR) and can be written
0 -
sr_idle
STATUS: 1: summing / recording FSM is idle and can accept a new sync command


sdmf_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sdmf_irq_raw).
R/W
0x00000000
Address@sdmf0 : 0x490001b4
Address@sdmf1 : 0x490002b4
Address@sdmf2 : 0x490003b4
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
eco
STATUS: error condition outoput (same as module output)
12 "0"
wc_3
STATUS: output of window comparator 3 (same as module output)
11 "0"
wc_2
STATUS: output of window comparator 2 (same as module output)
10 "0"
wc_1
STATUS: output of window comparator 1 (same as module output)
9 "0"
wc_0
STATUS: output of window comparator 0 (same as module output)
8 "0"
rdma_accviol_evt
EVENT : attempted to write to illegal memory address (constrained by DMA_ACC_LO and DMA_ACC_HI)
7 "0"
rdma_err_evt
EVENT : some samples could not be recorded (have been dropped)
6 "0"
rdone_evt
EVENT : all recorded samples have been written via AHBL
5 "0"
sdone_evt
EVENT : DTIME and SUM have been written via AHBL
4 "0"
snew_evt
EVENT : SUM_? registers have been updated
3 "0"
fil_done_evt
EVENT : BQ*_? registers have been updated
2 "0"
radr_ws_empty
STATUS: register RADR_WS is empty (transfered to RADR) and can be written
1 "0"
sadr_ws_empty
STATUS: register SADR_WS is empty (transfered to SADR) and can be written
0 "0"
sr_idle
STATUS: 1: summing / recording FSM is idle and can accept a new sync command


sdmf_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sdmf_irq_raw
R/W
0x00000000
Address@sdmf0 : 0x490001b8
Address@sdmf1 : 0x490002b8
Address@sdmf2 : 0x490003b8
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
eco
STATUS: error condition outoput (same as module output)
12 "0"
wc_3
STATUS: output of window comparator 3 (same as module output)
11 "0"
wc_2
STATUS: output of window comparator 2 (same as module output)
10 "0"
wc_1
STATUS: output of window comparator 1 (same as module output)
9 "0"
wc_0
STATUS: output of window comparator 0 (same as module output)
8 "0"
rdma_accviol_evt
EVENT : attempted to write to illegal memory address (constrained by DMA_ACC_LO and DMA_ACC_HI)
7 "0"
rdma_err_evt
EVENT : some samples could not be recorded (have been dropped)
6 "0"
rdone_evt
EVENT : all recorded samples have been written via AHBL
5 "0"
sdone_evt
EVENT : DTIME and SUM have been written via AHBL
4 "0"
snew_evt
EVENT : SUM_? registers have been updated
3 "0"
fil_done_evt
EVENT : BQ*_? registers have been updated
2 "0"
radr_ws_empty
STATUS: register RADR_WS is empty (transfered to RADR) and can be written
1 "0"
sadr_ws_empty
STATUS: register SADR_WS is empty (transfered to SADR) and can be written
0 "0"
sr_idle
STATUS: 1: summing / recording FSM is idle and can accept a new sync command


sdmf_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 14 when no IRQ is set:
  0  : irq-sr_idle
  1  : irq-sadr_ws_empty
  2  : irq-radr_ws_empty
  3  : irq-fil_done_evt
  4  : irq-snew_evt
  5  : irq-sdone_evt
  6  : irq-rdone_evt
  7  : irq-rdma_err_evt
  8  : irq-rdma_accviol_evt
  9  : irq-wc_0
  10 : irq-wc_1
  11 : irq-wc_2
  12 : irq-wc_3
  13 : irq-eco
  14 : no active IRQ
R/W
0x00000000
Address@sdmf0 : 0x490001bc
Address@sdmf1 : 0x490002bc
Address@sdmf2 : 0x490003bc
Bits Reset value Name Description
31 - 14 0
-
 reserved
13 "0"
eco
STATUS: error condition outoput (same as module output)
12 "0"
wc_3
STATUS: output of window comparator 3 (same as module output)
11 "0"
wc_2
STATUS: output of window comparator 2 (same as module output)
10 "0"
wc_1
STATUS: output of window comparator 1 (same as module output)
9 "0"
wc_0
STATUS: output of window comparator 0 (same as module output)
8 "0"
rdma_accviol_evt
EVENT : attempted to write to illegal memory address (constrained by DMA_ACC_LO and DMA_ACC_HI)
7 "0"
rdma_err_evt
EVENT : some samples could not be recorded (have been dropped)
6 "0"
rdone_evt
EVENT : all recorded samples have been written via AHBL
5 "0"
sdone_evt
EVENT : DTIME and SUM have been written via AHBL
4 "0"
snew_evt
EVENT : SUM_? registers have been updated
3 "0"
fil_done_evt
EVENT : BQ*_? registers have been updated
2 "0"
radr_ws_empty
STATUS: register RADR_WS is empty (transfered to RADR) and can be written
1 "0"
sadr_ws_empty
STATUS: register SADR_WS is empty (transfered to SADR) and can be written
0 "0"
sr_idle
STATUS: 1: summing / recording FSM is idle and can accept a new sync command


sdmf_ch_bq_sel
CONFIDENTIAL. HIDDEN.
R/W
0x00000000
Address@sdmf0 : 0x490001c0
Address@sdmf1 : 0x490002c0
Address@sdmf2 : 0x490003c0
Bits Reset value Name Description
31 - 2 0x0
guard
Writing 0x2701B1BA while the module input signal bq_visible is set enables reading and writing to BQ*_CFG registers below.Writing any other value or deasserting bq_visible will disable it.Reading returns 1 when reads / writes are allowed and 0 otherwise.After system reset writes are not allowed.
1 - 0 "00"
sel
0..N select register bank BQ*_CFG for sdm[sel]


sdmf_bq0_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.
R/W
0x00000000
Address@sdmf0 : 0x490001c4
Address@sdmf1 : 0x490002c4
Address@sdmf2 : 0x490003c4
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 25 "00000"
init_exp
gain exponent
24 - 20 "00000"
init_mant
gain mantissa
19 - 15 "00000"
c2_exp
exponent
14 - 10 "00000"
c2_mant
unsigned mantissa
9 - 5 "00000"
c1_exp
exponent
4 - 0 "00000"
c1_mant
unsigned mantissa


sdmf_bq1_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.
R/W
0x00000000
Address@sdmf0 : 0x490001c8
Address@sdmf1 : 0x490002c8
Address@sdmf2 : 0x490003c8
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 25 "00000"
init_exp
gain exponent
24 - 20 "00000"
init_mant
gain mantissa
19 - 15 "00000"
c2_exp
exponent
14 - 10 "00000"
c2_mant
unsigned mantissa
9 - 5 "00000"
c1_exp
exponent
4 - 0 "00000"
c1_mant
unsigned mantissa


sdmf_bq2_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.
R/W
0x00000000
Address@sdmf0 : 0x490001cc
Address@sdmf1 : 0x490002cc
Address@sdmf2 : 0x490003cc
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 25 "00000"
init_exp
gain exponent
24 - 20 "00000"
init_mant
gain mantissa
19 - 15 "00000"
c2_exp
exponent
14 - 10 "00000"
c2_mant
unsigned mantissa
9 - 5 "00000"
c1_exp
exponent
4 - 0 "00000"
c1_mant
unsigned mantissa


sdmf_bq0_gain_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.

R/W
0x00000000
Address@sdmf0 : 0x490001d0
Address@sdmf1 : 0x490002d0
Address@sdmf2 : 0x490003d0
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
out_scale



sdmf_bq1_gain_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.

R/W
0x00000000
Address@sdmf0 : 0x490001d4
Address@sdmf1 : 0x490002d4
Address@sdmf2 : 0x490003d4
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
out_scale



sdmf_bq2_gain_cfg
CONFIDENTIAL. HIDDEN (see CH_BQ_SEL). Free configuration for the biquad filters. BQ0_N corresponds to sdm_d[N]. Hidden register. Written when the corresponding BQ_CFG_? register is written.

R/W
0x00000000
Address@sdmf0 : 0x490001d8
Address@sdmf1 : 0x490002d8
Address@sdmf2 : 0x490003d8
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 - 0 "00000"
out_scale




Base Address Area: mpwm

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mpwm_cfg
1 4 R/W mpwm_cnt_max
2 8 R/W mpwm_cnt_ps_max
3 c R/W mpwm_dt
4 10 R/W mpwm_ocfg
5 14 R/W mpwm_cnt_max_s
6 18 R/W mpwm_dt_s
7 1c R mpwm_status
8 20 W mpwm_cmd
9 24 R mpwm_cnt
a 28 R mpwm_ecnt
b 2c R mpwm_cnt_rs
c 30 R mpwm_cnt_ps
d 34 R mpwm_evt_cnt
e 38 R/W mpwm_bc_s
f 3c R/W mpwm_bc
10-3f 40-fc -  reserved
40 100 R/W mpwm_ch0_cmp0_s
41 104 R/W mpwm_ch0_cmp1_s
42 108 R/W mpwm_ch0_cmp0
43 10c R/W mpwm_ch0_cmp1
44 110 R/W mpwm_ch0_muxin_s
45 114 R/W mpwm_ch0_muxin
46-47 118-11c -  reserved
48 120 R/W mpwm_ch1_cmp0_s
49 124 R/W mpwm_ch1_cmp1_s
4a 128 R/W mpwm_ch1_cmp0
4b 12c R/W mpwm_ch1_cmp1
4c 130 R/W mpwm_ch1_muxin_s
4d 134 R/W mpwm_ch1_muxin
4e-4f 138-13c -  reserved
50 140 R/W mpwm_ch2_cmp0_s
51 144 R/W mpwm_ch2_cmp1_s
52 148 R/W mpwm_ch2_cmp0
53 14c R/W mpwm_ch2_cmp1
54 150 R/W mpwm_ch2_muxin_s
55 154 R/W mpwm_ch2_muxin
56-57 158-15c -  reserved
58 160 R/W mpwm_ch3_cmp0_s
59 164 R/W mpwm_ch3_cmp1_s
5a 168 R/W mpwm_ch3_cmp0
5b 16c R/W mpwm_ch3_cmp1
5c 170 R/W mpwm_ch3_muxin_s
5d 174 R/W mpwm_ch3_muxin
5e-5f 178-17c -  reserved
60 180 R/W mpwm_ch4_cmp0_s
61 184 R/W mpwm_ch4_cmp1_s
62 188 R/W mpwm_ch4_cmp0
63 18c R/W mpwm_ch4_cmp1
64 190 R/W mpwm_ch4_muxin_s
65 194 R/W mpwm_ch4_muxin
66-67 198-19c -  reserved
68 1a0 R/W mpwm_ch5_cmp0_s
69 1a4 R/W mpwm_ch5_cmp1_s
6a 1a8 R/W mpwm_ch5_cmp0
6b 1ac R/W mpwm_ch5_cmp1
6c 1b0 R/W mpwm_ch5_muxin_s
6d 1b4 R/W mpwm_ch5_muxin
6e-6f 1b8-1bc -  reserved
70 1c0 R/W mpwm_irq_raw
71 1c4 R mpwm_irq_masked
72 1c8 R/W mpwm_irq_msk_set
73 1cc R/W mpwm_irq_msk_reset
74 1d0 R mpwm_irq_no
75-7f 1d4-1fc -  reserved

mpwm_cfg
Config register:
General config bits for the MPWM module.
R/W
0x00000800
Address : 0x49000400
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 - 16 "00000000"
eci_fil_thresh
ECI filter threshold:
Threshold value for the error condition input integral filter.
15 - 11 "00001"
evt_cnt_top
evt_cnt_top
Used to specify the maximum value of EVT_CNT. When EVT_CNT is zero and a begin of period )BOP) event occurs, an event counter zero (ECZ) event is emitted and EVT_CNT is reset to evt_cnt_top. If an begin of period event occurs and EVT_CNT is not zero, EVT_CNT is decremented. This mechanism can be used as an event prescaler to reduce the number of period interrupts from the MPWM module. Examples: If evt_cnt_top is zero, ECZ events and BOP events will coincide. If evt_cnt_top is one, ECZ events will appear every other period (half the frequency of BOP events). If evt_cnt_top is two, ECZ events will appear every third period (one third the frequency of BOP events).
10 "0"
sce_src_mop
sce_src_mop
1=emit shadow copy event on middle of PWM period bit
9 "0"
sce_src_bop
sce_src_bop
1=emit shadow copy event on beginning of PWM period
8 "0"
sce_src_ecz
sce_src_ecz
1=emit shadow copy event when event counter reaches zero
7 "0"
eci_ks_en
eci_ks_en
Set 1 to enable synchronous error condition input (eci) kill switch. The synchronous eci kill switch is a flip flop that is set once eci is active. The eci kill switch can only be reset through MPWM_ECI_CMD. When the eci kill switch is set, all PWM module outputs are disabled.
6 "0"
eci_gate_en
eci_gate_en
Set 1 to gate all pwm outputs with the integral filtered error control input. This means that the outputs will be disabled asynchronously whenever eci is active.
5 "0"
eci_inv
eci_inv
This bit controls the polarity of the error condition input (eci). Set 0 for active high eci, 1 for active low eci.
4 "0"
sync_in_pol
Polarity of sync signal from trigger_latch unit
0: Sync on rising edge
1: Sync on falling edge
3 "0"
sync_in_restart
Restart at sync signal from trigger_latch unit
0: Restart counter only by restart command.
1: Restart counter at sync signal or by restart command.
2 "0"
cnt_en_rs
cnt_en_rs
When this bit is one and sync_in is active, save the value of MPWM_CNT to the MPWM_CNT_RS (rs = read sync) register.
1 - 0 "00"
cnt_mode
Counter mode:
00: sawtooth
01: triangle
10: inv sawtooth
11: inv triangle


mpwm_cnt_max
Counter top register:
This is the maximum / top value for the PWM counter. In inverse sawtooth mode, MPWM_CNT will be loaded with MPWM_CNT_MAX after reaching zero or when restarting the counter. In sawtooth mode, MPWM_CNT will be reset to zero after reaching MPWM_CNT_MAX. In inverse sawtooth mode, MPWM_CNT will be set to MPWM_CNT_MAX when restarting the counter, and when it reaches MPWM_CNT_MAX while counting up, it will change to counting down. In inverse sawtooth mode, when MPWM_CNT reaches MPWM_CNT_MAX while counting up, it will change to counting down. In either sawtooth mode, the most significant bit must be zero. This is necessary to ensure a valid MPWM_ECNT. The CNT_MAX register must be at least 1 for correct operation of the counter.
R/W
0x00000000
Address : 0x49000404
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
Counter top value


mpwm_cnt_ps_max
Counter prescaler max value register:
The values of this register determines how often MPWM_CNT and the counters in the dead time generators will be updated. When setting MPWM_CNT_PS_MAX to n, MPWM_CNT will be updated every n + 1 system clock cycles. This register can be used to slow down operation of the counter.
R/W
0x00000000
Address : 0x49000408
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
val
Counter prescaler max value


mpwm_dt
Dead time register:
This is the number of dead (LS and HS off) cycles (prescaled by MPWM_CNT_PS) that the dead time generator inserts when the direct PWM signal changes from zero to one (rise_val) and from one to zero (fall_val). Set to zero for no dead cycles.
R/W
0x00000000
Address : 0x4900040c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
fall_val
Dead time cycles at falling edge of PWM signal
7 - 0 "00000000"
rise_val
Dead time cycles at rising edge of PWM signal


mpwm_ocfg
Output section config register:
Output select, enable, invert and edge detect values.
R/W
0x00000000
Address : 0x49000410
Bits Reset value Name Description
31 0
-
 reserved
30 "0"
oedpol5
Channel 5 edge detector polarity (0 = detect positive edge, 1 = detect negative edge)
29 "0"
oedpol4
Channel 4 edge detector polarity
28 "0"
oedpol3
Channel 3 edge detector polarity
27 "0"
oedpol2
Channel 2 edge detector polarity
26 "0"
oedpol1
Channel 1 edge detector polarity
25 "0"
oedpol0
Channel 0 edge detector polarity
24 "0"
oeden5
Channel 5 edge detector enable
23 "0"
oeden4
Channel 4 edge detector enable
22 "0"
oeden3
Channel 3 edge detector enable
21 "0"
oeden2
Channel 2 edge detector enable
20 "0"
oeden1
Channel 1 edge detector enable
19 "0"
oeden0
Channel 0 edge detector enable
18 "0"
oinv5
Output 5 invert
17 "0"
oinv4
Output 4 invert
16 "0"
oinv3
Output 3 invert
15 "0"
oinv2
Output 2 invert
14 "0"
oinv1
Output 1 invert
13 "0"
oinv0
Output 0 invert (see output section diagram)
12 "0"
oe5
Output 5 enable
11 "0"
oe4
Output 4 enable
10 "0"
oe3
Output 3 enable
9 "0"
oe2
Output 2 enable
8 "0"
oe1
Output 1 enable
7 "0"
oe0
Output 0 enable (see output section diagram)
6 0
-
 reserved
5 "0"
osel5
Output 5 selector:
0: compare channel 5 direct PWM output
1: dead time generator channel 2 LS
4 "0"
osel4
Output 4 selector:
0: compare channel 4 direct PWM output
1: dead time generator channel 2 HS
3 "0"
osel3
Output 3 selector:
0: compare channel 3 direct PWM output
1: dead time generator channel 1 LS
2 "0"
osel2
Output 2 selector:
0: compare channel 2 direct PWM output
1: dead time generator channel 1 HS
1 "0"
osel1
Output 1 selector:
0: compare channel 1 direct PWM output
1: dead time generator channel 0 LS
0 "0"
osel0
Output 0 selector:
0: compare channel 0 direct PWM output
1: dead time generator channel 0 HS


mpwm_cnt_max_s
Counter top shadow register:
Shadow register for MPWM_CNT_TOP. After writing this register, an internal flag is set. If the internal flag is set, at the next occurence of a shadow copy event cnt_top will be overwritten by MPWM_CNT_MAX_S and the internal flag will be reset.
R/W
0x00000000
Address : 0x49000414
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
Counter top shadow value


mpwm_dt_s
Dead time shadow register:
Shadow register for MPWM_DT register.
R/W
0x00000000
Address : 0x49000418
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 8 "00000000"
fall_val
Dead time shadow value for falling edge of PWM signal
7 - 0 "00000000"
rise_val
Dead time shadow value for rising edge of PWM signal


mpwm_status
Status register:
This register can be read to obtain information about the current status of the MPWM module.
R
Address : 0x4900041c
Bits Name Description
31 - 4 -
 reserved
3 cnt_half
count half:
0: counter is in first half period of triangle mode or inverted triangle mode or counter is in sawtooth or inverse sawtooth mode.
1: counter is in second half period of triangle mode or inverted triangle mode
2 cnt_updown
count updown
0: counter is counting down
1: counter is counting up
1 eci_val_unfil
Error Condition Input unfiltered:
Read the current value of the error condition input before the digital integral filter. This bit is corrected for polarity, which means it reads zero for inactive, one for active.
0 running
MPWM is running


mpwm_cmd
Command register:
W
0x00000000
Address : 0x49000420
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
eci_ks_rst
ECI kill switch reset:
Command register to reset the eci kill switch.
4 "0"
evt_cnt_rst
Event Counter Reset
3 "0"
sce_emit
Copy shadow registers to corresponding registers
2 "0"
restart
Restart:
Write 1 to this bit to reset MPWM_CNT and MPWM_CNT_PS and start counter operation. MPWM_CNT_PS is reset to MPWM_CNT_PS_MAX. In triangle and sawtooth mode, MPWM_CNT is reset to 0. In inverse triangle and inverse sawtooth mode, MPWM_CNT is reset to MPWM_CNT_MAX. If the restart and the stop bit are written as 1 in the same access, the MPWM_CNT and MPWM_CNT_PS registers will be reset but the counter will remain stopped.
1 "0"
stop
Stop:
Write 1 to this bit to stop counter operation and prescaler operation.
0 "0"
start
Start:
Write 1 to start counter operation and prescaler operation. This does not reset the counter state. If the counter operating before, it will resume operation from where it was stopped.


mpwm_cnt
Counter:
Global counter. Used for all the comparisons that then generate the PWM signals. See counter behaviour diagram.
R
Address : 0x49000424
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
value


mpwm_ecnt
Extended counter:
Counter extended by one bit to distinguish between counting up and down. See counter behaviour diagram. The content of this register is also exposed to the outside of this module to allow other system components to synchronize themselves to the MPWM counter.
R
Address : 0x49000428
Bits Name Description
31 - 16 -
 reserved
15 - 0 val
value


mpwm_cnt_rs
Counter save register:
When CFG.cnt_en_rs (rs = read sync) is set, this register is used to save the value of the MPWM_CNT and MPWM_CNT_PS register every time that sync_in becomes active.
R
Address : 0x4900042c
Bits Name Description
31 - 24 -
 reserved
23 - 16 ps_val
saved value of the MPWM_CNT_PS register
15 - 0 cnt_val
saved value of the MPWM_CNT register


mpwm_cnt_ps
Counter prescaler register:
Internal counter that is responsible for determining, in which clock cycles cnt will be incremented / decremented. MPWM_CNT_PS is reloaded with MPWM_CNT_PS_MAX when it reaches zero. In every clock cycle, in which MPWM_CNT_PS is zero, cnt will be incremented / decremented.
R
Address : 0x49000430
Bits Name Description
31 - 8 -
 reserved
7 - 0 val
value


mpwm_evt_cnt
Event counter register:
This counter counts down whenever a full PWM period is finished. When MPWM_EVT_CNT reaches zero, a event counter zero event is emitted and MPWM_EVT_CNT is reset to MPWM_EVT_CNT_TOP.
R
Address : 0x49000434
Bits Name Description
31 - 5 -
 reserved
4 - 0 val
Current counter value


mpwm_bc_s
Brake chopper shadow register:
Shadow register for the brake chopper output
R/W
0x00000000
Address : 0x49000438
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
val
value


mpwm_bc
Brake chopper register:
The brake chopper output signal is determined by the value of this register.
R/W
0x00000000
Address : 0x4900043c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
val
value


mpwm_ch0_cmp0_s
Channel 0 compare value 0 shadow register:
Compare value 0 shadow register for channel 0.
R/W
0x00000000
Address : 0x49000500
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch0_cmp1_s
Channel 0 compare value 1 shadow register:
Compare value 1 shadow register for channel 0.
R/W
0x00000000
Address : 0x49000504
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch0_cmp0
Channel 0 compare value 0 register:
Compare value 0 for channel 0.
R/W
0x00000000
Address : 0x49000508
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch0_cmp1
Channel 0 compare value 1 register:
Compare value 1 for channel 0.
R/W
0x00000000
Address : 0x4900050c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch0_muxin_s
Channel 0 multiplexer input shadow register:
Shadow register for channel 0 multiplexer input register.
R/W
0x00000000
Address : 0x49000510
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch0_muxin
Channel 0 multiplexer input register:
This register is central in determining the direct PWM output value of channel 0. When (CNT  < CHX_CMP0) and (CNT  < CHX_CMP1), then the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is BeLow both compare values). When (CNT >= CHX_CMP0) and (CNT >= CHX_CMP1), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is ABove both compare values). If neither is the case, CNT is BeTween CHX_CMP0 and CHX_CMP1 and the direct PWM output signal is equal to CHX_MUXIN.bt.
R/W
0x00000000
Address : 0x49000514
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch1_cmp0_s
Channel 1 compare value 0 shadow register:
Compare value 0 shadow register for channel 1.
R/W
0x00000000
Address : 0x49000520
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch1_cmp1_s
Channel 1 compare value 1 shadow register:
Compare value 1 shadow register for channel 1.
R/W
0x00000000
Address : 0x49000524
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch1_cmp0
Channel 1 compare value 0 register:
Compare value 0 for channel 1.
R/W
0x00000000
Address : 0x49000528
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch1_cmp1
Channel 1 compare value 1 register:
Compare value 1 for channel 1.
R/W
0x00000000
Address : 0x4900052c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch1_muxin_s
Channel 1 multiplexer input shadow register:
Shadow register for channel 1 multiplexer input register.
R/W
0x00000000
Address : 0x49000530
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch1_muxin
Channel 1 multiplexer input register:
This register is central in determining the direct PWM output value of channel 1. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
0x00000000
Address : 0x49000534
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch2_cmp0_s
Channel 2 compare value 0 shadow register:
Compare value 0 shadow register for channel 2.
R/W
0x00000000
Address : 0x49000540
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch2_cmp1_s
Channel 2 compare value 1 shadow register:
Compare value 1 shadow register for channel 2.
R/W
0x00000000
Address : 0x49000544
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch2_cmp0
Channel 2 compare value 0 register:
Compare value 0 for channel 2.
R/W
0x00000000
Address : 0x49000548
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch2_cmp1
Channel 2 compare value 1 register:
Compare value 1 for channel 2.
R/W
0x00000000
Address : 0x4900054c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch2_muxin_s
Channel 2 multiplexer input shadow register:
Shadow register for channel 2 multiplexer input register.
R/W
0x00000000
Address : 0x49000550
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch2_muxin
Channel 2 multiplexer input register:
This register is central in determining the direct PWM output value of channel 2. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
0x00000000
Address : 0x49000554
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch3_cmp0_s
Channel 3 compare value 0 shadow register:
Compare value 0 shadow register for channel 3.
R/W
0x00000000
Address : 0x49000560
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch3_cmp1_s
Channel 3 compare value 1 shadow register:
Compare value 1 shadow register for channel 3.
R/W
0x00000000
Address : 0x49000564
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch3_cmp0
Channel 3 compare value 0 register:
Compare value 0 for channel 3.
R/W
0x00000000
Address : 0x49000568
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch3_cmp1
Channel 3 compare value 1 register:
Compare value 1 for channel 3.
R/W
0x00000000
Address : 0x4900056c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch3_muxin_s
Channel 3 multiplexer input shadow register:
Shadow register for channel 3 multiplexer input register.
R/W
0x00000000
Address : 0x49000570
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch3_muxin
Channel 3 multiplexer input register:
This register is central in determining the direct PWM output value of channel 3. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
0x00000000
Address : 0x49000574
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch4_cmp0_s
Channel 4 compare value 0 shadow register:
Compare value 0 shadow register for channel 4.
R/W
0x00000000
Address : 0x49000580
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch4_cmp1_s
Channel 4 compare value 1 shadow register:
Compare value 1 shadow register for channel 4.
R/W
0x00000000
Address : 0x49000584
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch4_cmp0
Channel 4 compare value 0 register:
Compare value 0 for channel 4.
R/W
0x00000000
Address : 0x49000588
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch4_cmp1
Channel 4 compare value 1 register:
Compare value 1 for channel 4.
R/W
0x00000000
Address : 0x4900058c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch4_muxin_s
Channel 4 multiplexer input shadow register:
Shadow register for channel 4 multiplexer input register.
R/W
0x00000000
Address : 0x49000590
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch4_muxin
Channel 4 multiplexer input register:
This register is central in determining the direct PWM output value of channel 4. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
0x00000000
Address : 0x49000594
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch5_cmp0_s
Channel 5 compare value 0 shadow register:
Compare value 0 shadow register for channel 5.
R/W
0x00000000
Address : 0x490005a0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch5_cmp1_s
Channel 5 compare value 1 shadow register:
Compare value 1 shadow register for channel 5.
R/W
0x00000000
Address : 0x490005a4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch5_cmp0
Channel 5 compare value 0 register:
Compare value 0 for channel 5.
R/W
0x00000000
Address : 0x490005a8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch5_cmp1
Channel 5 compare value 1 register:
Compare value 1 for channel 5.
R/W
0x00000000
Address : 0x490005ac
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
val
value


mpwm_ch5_muxin_s
Channel 5 multiplexer input shadow register:
Shadow register for channel 5 multiplexer input register.
R/W
0x00000000
Address : 0x490005b0
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_ch5_muxin
Channel 5 multiplexer input register:
This register is central in determining the direct PWM output value of channel 5. When (CHX_CMP0 $>=$ CNT) and (CHX_CMP1 $>=$ CNT), the direct PWM output signal is equal to CHX_MUXIN.bl (counter value is below both compare values). When (CHX_CMP0 $>=$ CNT) xor (CHX_CMP1 $>=$ CNT) is true, then the direct PWM output signal is equal to CHX_MUXIN.bt (counter value is between both compare values). When not (CHX_CMP0 $>=$ CNT) and not (CHX_CMP1 $>=$ CNT), then the direct PWM output signal is equal to CHX_MUXIN.ab (counter value is above both compare values).
R/W
0x00000000
Address : 0x490005b4
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ab
above
1 "0"
bt
between
0 "0"
bl
below


mpwm_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs. IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source).
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x490005c0
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 5 "000000"
oede
event: output section edge detector
4 -
eci_ks_state
status: error condition kill switch state bit
3 -
eci_val
status: eci_val
error condition input value bit after filter
2 "0"
mop
event: middle of PWM period bit
1 "0"
bop
event: beginning of PWM period bit
0 "0"
ecz
event: evt_counter reached zero bit


mpwm_irq_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
Address : 0x490005c4
Bits Name Description
31 - 11 -
 reserved
10 - 5 oede
event: output section edge detector
4 eci_ks_state
status: error condition kill switch state bit
3 eci_val
status: eci_val
error condition input value bit after filter
2 mop
event: middle of PWM period bit
1 bop
event: beginning of PWM period bit
0 ecz
event: evt_counter reached zero bit


mpwm_irq_msk_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_mpwm_irq_raw.
R/W
0x00000000
Address : 0x490005c8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 5 "000000"
oede
event: output section edge detector
4 "0"
eci_ks_state
status: error condition kill switch state bit
3 "0"
eci_val
status: eci_val
error condition input value bit after filter
2 "0"
mop
event: middle of PWM period bit
1 "0"
bop
event: beginning of PWM period bit
0 "0"
ecz
event: evt_counter reached zero bit


mpwm_irq_msk_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access is undefined
R/W
0x00000000
Address : 0x490005cc
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 5 "000000"
oede
event: output section edge detector
4 "0"
eci_ks_state
status: error condition kill switch state bit
3 "0"
eci_val
status: eci_val
error condition input value bit after filter
2 "0"
mop
event: middle of PWM period bit
1 "0"
bop
event: beginning of PWM period bit
0 "0"
ecz
event: evt_counter reached zero bit


mpwm_irq_no
IRQ number:
This shows the bit number of the lowest active bit in IRQ_MASKED or MAX+1 when no bit is set.
R
Address : 0x490005d0
Bits Name Description
31 - 4 -
 reserved
3 - 0 val
lowest active IRQ number



Base Address Area: menc

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W menc_config
1 4 R/W menc_enc0_position
2 8 R/W menc_enc1_position
3 c R/W menc_capture_now
4 10 R/W menc_capture0_config
5 14 R menc_capture0_val
6 18 R menc_capture0_ta
7 1c R menc_capture0_te
8 20 R/W menc_capture1_config
9 24 R menc_capture1_val
a 28 R menc_capture1_ta
b 2c R menc_capture1_te
c 30 R/W menc_capture2_config
d 34 R menc_capture2_val
e 38 R menc_capture2_ta
f 3c R menc_capture2_te
10 40 R/W menc_capture3_config
11 44 R menc_capture3_val
12 48 R menc_capture3_ta
13 4c R menc_capture3_te
14 50 R/W menc_status
15 54 R menc_irq_masked
16 58 R/W menc_irq_msk_set
17 5c R/W menc_irq_msk_reset
18-1f 60-7c -  reserved

menc_config
Encoder configuration register
R/W
0x00000000
Address : 0x49000600
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 25 "000"
mp1_filter_sample_rate
Filter sample rate for mp1 signal:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
24 "0"
mp1_en
mp1 enable:
0: Disable interrupts based on mp1 signal.
23 - 20 0
-
 reserved
19 - 17 "000"
mp0_filter_sample_rate
Filter sample rate for mp0 signal:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
16 "0"
mp0_en
mp0 enable:
0: Disable interrupts based on mp0 signal.
15 - 13 0
-
 reserved
12 "0"
enc1_count_dir
Encoder1 count direction:
0: standard
1: inverted
11 - 9 "000"
enc1_filter_sample_rate
Encoder1 filter sample rate:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
8 "0"
enc1_en
Encoder1 enable:
0: Disable interrupts based on encoder1 signals.
7 - 5 0
-
 reserved
4 "0"
enc0_count_dir
Encoder0 count direction:
0: standard
1: inverted
3 - 1 "000"
enc0_filter_sample_rate
Encoder0 filter sample rate:
0: none   -  Filter is disabled.
1: 10 ns  -  pulses < 10ns  will be blocked,
pulses > 20ns will pass.
2: 20 ns  -  pulses < 20ns  will be blocked,
pulses > 40ns will pass.
3: 50 ns  -  pulses < 50ns  will be blocked,
pulses > 100ns will pass.
4: 100 ns -  pulses < 100ns will be blocked,
pulses > 200ns will pass.
5: 200 ns -  pulses < 200ns will be blocked,
pulses > 400ns will pass.
6: 500 ns -  pulses < 500ns will be blocked,
pulses > 1us will pass.
7: 1 us   -  pulses < 1us   will be blocked,
pulses > 2us will pass.
0 "0"
enc0_en
Encoder0 enable:
0: Disable interrupts based on encoder0 signals.


menc_enc0_position
Position of encoder 0
R/W
0x00000000
Address : 0x49000604
Bits Reset value Name Description
31 - 0 0x0
val
Actual position of encoder 0.
This register is writable but can also be changed by hardware.


menc_enc1_position
Position of encoder 1
R/W
0x00000000
Address : 0x49000608
Bits Reset value Name Description
31 - 0 0x0
val
Actual position of encoder 1.
This register is writable but can also be changed by hardware.


menc_capture_now
Capture now register:
This register allows activating the capture event by software for all 4 capture units.
R/W
0x00000000
Address : 0x4900060c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
cap3_now
Capture menc_capture3 now (by SW).
Capture by writing 1 to this register, reset automatically.
2 "0"
cap2_now
Capture menc_capture2 now (by SW).
Capture by writing 1 to this register, reset automatically.
1 "0"
cap1_now
Capture menc_capture1 now (by SW).
Capture by writing 1 to this register, reset automatically.
0 "0"
cap0_now
Capture menc_capture0 now (by SW).
Capture by writing 1 to this register, reset automatically.


menc_capture0_config
Capture unit 0 configuration register
R/W
0x0001ffff
Address : 0x49000610
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
src
Capture source (what to capture):
0: system time ns (independent of src_nr)
1: position channel 0/1
2: Ta of channel 0/1
3: Te of channel 0/1
4: Ta+Te of channel 0/1
5: period in clock cycles (independent of src_nr)
16 - 0 0x1ffff
trigger
Capture start signal:
0x0...0x0FFFF: start at (ECNT == trigger)
0x10000: positive edge of enc0_n
0x10001: negative edge of enc0_n
0x10002: positive edge of enc1_n
0x10003: positive edge of enc1_n
0x10004: any edge of enc0_a or enc0_b
0x10005: any edge of enc1_a or enc0_b
0x10006: positive edge of mp0
0x10007: negative edge of mp0
0x10008: positive edge of mp1
0x10009: negative edge of mp1
0x1000a: GPIO_APP_COUNTER0 = 0
0x1000b: GPIO_APP_COUNTER1 = 0
0x1000c: GPIO_APP_COUNTER2 = 0
0x1000d: positive edge of xc_trigger[0]
0x1000e: positive edge of xc_trigger[1]
0x1000f: negative edge of xc_trigger[0]
0x10010: negative edge of xc_trigger[1]
0x10011: positive edge of xc_sample[0]
0x10012: positive edge of xc_sample[1]
0x10013: negative edge of xc_sample[0]
0x10014: negative edge of xc_sample[1]
0x1FFFF: off (no automatic capture, only capture_now)


menc_capture0_val
Capture unit 0 captured value
R
Address : 0x49000614
Bits Name Description
31 - 0 val
Captured value


menc_capture0_ta
Capture unit 0 Ta:
This register is only used for debug purposes.
R
Address : 0x49000618
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture0_te
Capture unit 0 Te
This register is only used for debug purposes.
R
Address : 0x4900061c
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture1_config
Capture unit 1 configuration register
R/W
0x0001ffff
Address : 0x49000620
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
trigger
Capture start signal:
s. capture0_config-trigger


menc_capture1_val
Capture unit 1 captured value
R
Address : 0x49000624
Bits Name Description
31 - 0 val
Captured value


menc_capture1_ta
Capture unit 1 Ta:
This register is only used for debug purposes.
R
Address : 0x49000628
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture1_te
Capture unit 1 Te
This register is only used for debug purposes.
R
Address : 0x4900062c
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture2_config
Capture unit 2 configuration register
R/W
0x0001ffff
Address : 0x49000630
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
trigger
Capture start signal:
s. capture0_config-trigger


menc_capture2_val
Capture unit 2 captured value
R
Address : 0x49000634
Bits Name Description
31 - 0 val
Captured value


menc_capture2_ta
Capture unit 2 Ta:
This register is only used for debug purposes.
R
Address : 0x49000638
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture2_te
Capture unit 2 Te
This register is only used for debug purposes.
R
Address : 0x4900063c
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_capture3_config
Capture unit 3 configuration register
R/W
0x0001ffff
Address : 0x49000640
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
conce
Capture once:
0: continuous capture: each event overwrites old capture register
1: capture once: capture only, if menc_status.cap0 = 0
20 "0"
src_nr
Capture source channel:
0: encoder/channel 0
1: encoder/channel 1
19 - 17 "000"
src
Capture source (what to capture):
s. capture0_config-src
16 - 0 0x1ffff
trigger
Capture start signal:
s. capture0_config-trigger


menc_capture3_val
Capture unit 3 captured value
R
Address : 0x49000644
Bits Name Description
31 - 0 val
Captured value


menc_capture3_ta
Capture unit 3 Ta:
This register is only used for debug purposes.
R
Address : 0x49000648
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Ta:
Time before first encoder pulse in period.


menc_capture3_te
Capture unit 3 Te
This register is only used for debug purposes.
R
Address : 0x4900064c
Bits Name Description
31 - 20 -
 reserved
19 - 0 val
Actual Te:
Time after last encoder pulse in period.


menc_status
Position and capture status:
This register includes all raw IRQs and encoder direction.
To reset an IRQ, write 1 to appropriate bit (except enc?_dir_ro).
R/W
0x00000000
Address : 0x49000650
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
mp1
Rising edge at Measurement Point 1
24 "0"
mp0
Rising edge at Measurement Point 0
23 - 20 0
-
 reserved
19 "0"
cap3
Captured register 3
18 "0"
cap2
Captured register 2
17 "0"
cap1
Captured register 1
16 "0"
cap0
Captured register 0
15 -
enc1_dir_ro
Encoder1 direction (read only)
14 - 13 0
-
 reserved
12 "0"
enc1_n
Rising edge at input enc1_n.
11 "0"
enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 -
enc0_dir_ro
Encoder0 direction (read only)
6 - 5 0
-
 reserved
4 "0"
enc0_n
Rising edge at input enc0_n.
3 "0"
enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_masked
Masked IRQ register:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
Address : 0x49000654
Bits Name Description
31 - 26 -
 reserved
25 mp1
Rising edge at Measurement Point 1
24 mp0
Rising edge at Measurement Point 0
23 - 20 -
 reserved
19 cap3
Captured register 3
18 cap2
Captured register 2
17 cap1
Captured register 1
16 cap0
Captured register 0
15 - 13 -
 reserved
12 enc1_n
Rising edge at input enc1_n.
11 enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 enc1_ovfl_neg
Encoder1 overflow negative
9 enc1_ovfl_pos
Encoder1 overflow positive
8 enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 -
 reserved
4 enc0_n
Rising edge at input enc0_n.
3 enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 enc0_ovfl_neg
Encoder0 overflow negative
1 enc0_ovfl_pos
Encoder0 overflow positive
0 enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_msk_set
IRQ mask enable:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_menc_status
R/W
0x00000000
Address : 0x49000658
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
mp1
Rising edge at Measurement Point 1
24 "0"
mp0
Rising edge at Measurement Point 0
23 - 20 0
-
 reserved
19 "0"
cap3
Captured register 3
18 "0"
cap2
Captured register 2
17 "0"
cap1
Captured register 1
16 "0"
cap0
Captured register 0
15 - 13 0
-
 reserved
12 "0"
enc1_n
Rising edge at input enc1_n.
11 "0"
enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 0
-
 reserved
4 "0"
enc0_n
Rising edge at input enc0_n.
3 "0"
enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)


menc_irq_msk_reset
IRQ mask disable:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0x4900065c
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
mp1
Rising edge at Measurement Point 1
24 "0"
mp0
Rising edge at Measurement Point 0
23 - 20 0
-
 reserved
19 "0"
cap3
Captured register 3
18 "0"
cap2
Captured register 2
17 "0"
cap1
Captured register 1
16 "0"
cap0
Captured register 0
15 - 13 0
-
 reserved
12 "0"
enc1_n
Rising edge at input enc1_n.
11 "0"
enc1_phase_error
Phase error at encoder 1:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
10 "0"
enc1_ovfl_neg
Encoder1 overflow negative
9 "0"
enc1_ovfl_pos
Encoder1 overflow positive
8 "0"
enc1_edge
Edge at Encoder 1 occurred (rising or falling of enc1_a or enc1_b)
7 - 5 0
-
 reserved
4 "0"
enc0_n
Rising edge at input enc0_n.
3 "0"
enc0_phase_error
Phase error at encoder 0:
Encoder inputs changed 2 phases in 1 cycle, which leads to unknown position.
2 "0"
enc0_ovfl_neg
Encoder0 overflow negative
1 "0"
enc0_ovfl_pos
Encoder0 overflow positive
0 "0"
enc0_edge
Edge at Encoder 0 occurred (rising or falling of enc0_a or enc0_b)



Base Address Area: madc

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W madc_cfg
1 4 R/W madc_adc0_static_cfg
2 8 R/W madc_adc1_static_cfg
3 c R/W madc_adc2_static_cfg
4 10 R/W madc_adc3_static_cfg
5 14 R/W madc_start
6 18 R/W madc_deadtime01_delay
7 1c R/W madc_deadtime23_delay
8 20 R/W madc_deadtime45_delay
9 24 R/W madc_cal_vref_config
a 28 R/W madc_cal_iref_config
b-f 2c-3c -  reserved

madc_cfg
Config bits for the MADC common module.
R/W
0x00000002
Address : 0x49000680
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000010"
adcclk_period
Max value of global ADC synchronization counter:
ADCs running at same adcclk might interfere. Therefore the ADCs should be able to run in different clk-phases.
Adcclk generation will be done within the ADC sequencers. This value is used to configure a global counter for clock phase reference. It's value should be the same or an natural numbered multiple of the value configured in ADC sequencers.


madc_adc0_static_cfg
Static configuration signals
R/W
0x000006f0
Address : 0x49000684
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 9 "011"
ibtune_cmp
Comparator bias current tuning
8 - 6 "011"
ibtune_ref
Reference OTA bias current tuning
5 - 4 "11"
bw_tune
Bandwidth tuning, trade settling vs noise
3 "0"
inv_clko
Output clock invert (invert phase)
2 "0"
buffer_enable
 alias din_refout_pd_0v9 (inverted)
1 "0"
reset_n
Low active reset of ADC0 and ADC1 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
enable
enable/disable
1: Enable ADC
0: Disable ADC


madc_adc1_static_cfg
Static configuration signals
R/W
0x000006f0
Address : 0x49000688
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 9 "011"
ibtune_cmp
Comparator bias current tuning
8 - 6 "011"
ibtune_ref
Reference OTA bias current tuning
5 - 4 "11"
bw_tune
Bandwidth tuning, trade settling vs noise
3 "0"
inv_clko
Output clock invert (invert phase)
2 "0"
buffer_enable
 alias din_refout_pd_0v9 (inverted)
1 "0"
reset_n
Low active reset of ADC0 and ADC1 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
enable
enable/disable
1: Enable ADC
0: Disable ADC


madc_adc2_static_cfg
Static configuration signals
R/W
0x000006f0
Address : 0x4900068c
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 9 "011"
ibtune_cmp
Comparator bias current tuning
8 - 6 "011"
ibtune_ref
Reference OTA bias current tuning
5 - 4 "11"
bw_tune
Bandwidth tuning, trade settling vs noise
3 "0"
inv_clko
Output clock invert (invert phase)
2 "0"
buffer_enable
 alias din_refout_pd_0v9 (inverted)
1 "0"
reset_n
Low active reset of ADC0 and ADC1 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
enable
enable/disable
1: Enable ADC
0: Disable ADC


madc_adc3_static_cfg
Static configuration signals
R/W
0x000006f0
Address : 0x49000690
Bits Reset value Name Description
31 - 12 0
-
 reserved
11 - 9 "011"
ibtune_cmp
Comparator bias current tuning
8 - 6 "011"
ibtune_ref
Reference OTA bias current tuning
5 - 4 "11"
bw_tune
Bandwidth tuning, trade settling vs noise
3 "0"
inv_clko
Output clock invert (invert phase)
2 "0"
buffer_enable
 alias din_refout_pd_0v9 (inverted)
1 "0"
reset_n
Low active reset of ADC0 and ADC1 and their state machines:
1: Soft-Reset is inactive.
0: Soft-Reset is active.
A reset can be applied at any time during a currently running conversion cycle. There are no constraints on reset length.
0 "0"
enable
enable/disable
1: Enable ADC
0: Disable ADC


madc_start
ADC start register:
This register allows to start all ADCs in parallel. All further configuration is done within the ADC sequencers. Also ADCs can be started from their sequencers address range.
This register is writable but can also be changed by hardware (reset).
R/W
0x00000000
Address : 0x49000694
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
start_adc3
Start ADC3:
2 "0"
start_adc2
Start ADC2:
1 "0"
start_adc1
Start ADC1:
0 "0"
start_adc0
Start ADC0:
Setting this bit to 1 starts ADC control state machine for ADC0.
It will reset automatically after sampling phase.
If it is reset, it can be set for next conversion.
If start_adc0 and start_adc1 are set, the next conversion will be started
after both ADCs are finished. Otherwise the next conversion will start
directly after current conversion of ADC0 is finished.


madc_deadtime01_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time EVenT from PWM module and trigger.
In case of 2nd DTEVT within delay time, the second DTEVT will be lost.
R/W
0x000a000a
Address : 0x49000698
Bits Reset value Name Description
31 - 16 0xa
dt1
delay for DTEVT[1]
15 - 0 0xa
dt0
delay for DTEVT[0]


madc_deadtime23_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time Event from PWM module and trigger.
In case of 2nd Dead Time Event within delay time, the second DTEVT will be lost.
R/W
0x000a000a
Address : 0x4900069c
Bits Reset value Name Description
31 - 16 0xa
dt3
delay for DTEVT[3]
15 - 0 0xa
dt2
delay for DTEVT[2]


madc_deadtime45_delay
Dead time delay:
Delay in steps of system clock (10ns) between Dead Time Event from PWM module and trigger.
In case of 2nd Dead Time Event within delay time, the second DTEVT will be lost.
R/W
0x000a000a
Address : 0x490006a0
Bits Reset value Name Description
31 - 16 0xa
dt5
delay for DTEVT[5]
15 - 0 0xa
dt4
delay for DTEVT[4]


madc_cal_vref_config
Configuration of calibration reference:
R/W
0x80808080
Address : 0x490006a4
Bits Reset value Name Description
31 - 24 "10000000"
dual_adc1_cal_vref_tc

23 - 16 "10000000"
dual_adc1_cal_vref

15 - 8 "10000000"
dual_adc0_cal_vref_tc

7 - 0 "10000000"
dual_adc0_cal_vref



madc_cal_iref_config
Configuration of calibration current reference:
R/W
0x00000210
Address : 0x490006a8
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 - 5 "010000"
dual_adc1_cal_iref

4 - 0 "10000"
dual_adc0_cal_iref




Base Address Area: madc_seq0, madc_seq1, madc_seq2, madc_seq3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W madc_seq_cfg
1 4 R/W madc_seq_tracking_time_mux0
2 8 R/W madc_seq_tracking_time_mux1
3 c R/W madc_seq_tracking_time_mux2
4 10 R/W madc_seq_tracking_time_mux3
5 14 R/W madc_seq_tracking_time_mux4
6 18 R/W madc_seq_tracking_time_mux5
7 1c R/W madc_seq_tracking_time_mux6
8 20 R/W madc_seq_tracking_time_mux7
9 24 R/W madc_seq_ms_en
a 28 R/W madc_seq_ms_baseadr
b 2c R/W madc_seq_m0
c 30 R/W madc_seq_m1
d 34 R/W madc_seq_m2
e 38 R/W madc_seq_m3
f 3c R/W madc_seq_m4
10 40 R/W madc_seq_m5
11 44 R/W madc_seq_m6
12 48 R/W madc_seq_m7
13 4c R/W madc_seq_cmd
14 50 R madc_seq_status
15 54 R madc_seq_result_current
16 58 R madc_seq_result_last
17 5c R/W madc_seq_debug
18-1b 60-6c -  reserved
1c 70 R/W madc_seq_irq_raw
1d 74 R madc_seq_irq_masked
1e 78 R/W madc_seq_irq_mask_set
1f 7c R/W madc_seq_irq_mask_reset
20-3f 80-fc -  reserved

madc_seq_cfg
ADC static configuration
R/W
0x0000ff01
Address@madc_seq0 : 0x49000700
Address@madc_seq1 : 0x49000800
Address@madc_seq2 : 0x49000900
Address@madc_seq3 : 0x49000a00
Bits Reset value Name Description
31 - 23 0
-
 reserved
22 - 20 "000"
adc_mode
din_mode_0v9[0]= 0b:
    status bit is enabled if set to 1b
din_mode_0v9[1]= 0b:
    if 2 clk periods sampling is desired, set it to 1b
    dint_mode[1] should only changed while din_rst_0v9==1'b1. The model will not change the
    number of sampling clocks otherwise, behaviour for the pysical ADC is undefined for changes
    outside the reset state.
din_mode_0v9[2]= 0b:
    set it to 1b din_mode_0v9[2]= 0b, to increase Vref (internal and external) by +10% set it to 1b. Please note,
    the use of this setting is outside of the ADC specification. Not feasible if vdd1v8<1.8V.
19 "0"
dma_disable
Disable DMA
1: DMA is disabled, results are not written to memory, only the current result will be visible in madc_seq_result_current.
0: DMA is enabled, results are written to memory as defined in madc_seq_ms_adr and madc_seq_m*-adr_offset.
18 "0"
dma_32bit_adr
The DMA engine only uses 32bit addresses and DWord access.
This mode wastes memory but speeds up the DMA access by not running read-modify-write cycles.
17 "0"
reseved

16 "0"
adcclk_sync
0: The rising edges of adcclk are generated independently of the other ADCs.
1: Use adc_clock_phase for defined clock phases in relation to other ADC sequencers
15 - 8 "11111111"
adcclk_phase
Generation of the rising edge of the adcclk is delayed until the global clk_phase counter matches this value.
NOTE: The rising edge of the adcclk ending the first sample period of a triggered measurement is NEVER delayed.
7 - 0 "00000001"
adcclk_period
Duration of an adcclk period in clk100 cycles-1
For odd values the high phase of adcclk is one system clock cycle longer than the low phase.


madc_seq_tracking_time_mux0
ADC sample extension for input channel 0
Length of 2nd adcclk in steps of 10ns system clock(~ delay of 3rd adcclk edge).
The capacitor inside ADC needs time to be charged depending on the driving strength of the external signal. For 12 bit precision, a settling to time of 9 tau should be ensured.
tau can be calculated by tau = 9 * (ADC_MUX_RSER + Rext) * ADC_MUX_CIN, with Rext being additional resistance from devices external to the SOC.
The setting of tt_add also depends on the setting of madc_seq_cfg.adcclk_period and can be calculate by the following formula:
tt_add = ceil( tau/10ns - madc_seq_cfg.adcclk_period ) - 2
Set tt_add=4 if calculated value is smaller 4.
Note: madc_seq_cfg.adcclk_period and madc_seq_tracking_time_mux[x].tt_add will count down to 0 meaning that the any value set in the registers is increased by 1. To compensate this the tt_add formula includes a '-2'.
Note: ADC_MUX_RSET and ADC_MUX_CIN are defined in the electrical parameters.
Note: Exact values for ADC_MUX_RSET and ADC_MUX_CIN will vary for each ADC-Input and are TBD. For rough estimation use ADC_MUX_RSET = 390Ohm+20% and ADC_MUX_CIN = 4,5pF+20%
The total ADC cycle time results in:
tcycle = 14 * adcclk_period + clock_sync_delay (max 1 adcclk_period) + tt_add * 10ns.
R/W
0x00000004
Address@madc_seq0 : 0x49000704
Address@madc_seq1 : 0x49000804
Address@madc_seq2 : 0x49000904
Address@madc_seq3 : 0x49000a04
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux1
ADC sample extension for input channel 1
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x49000708
Address@madc_seq1 : 0x49000808
Address@madc_seq2 : 0x49000908
Address@madc_seq3 : 0x49000a08
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux2
ADC sample extension for input channel 2
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x4900070c
Address@madc_seq1 : 0x4900080c
Address@madc_seq2 : 0x4900090c
Address@madc_seq3 : 0x49000a0c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux3
ADC sample extension for input channel 3
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x49000710
Address@madc_seq1 : 0x49000810
Address@madc_seq2 : 0x49000910
Address@madc_seq3 : 0x49000a10
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux4
ADC sample extension for input channel 4
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x49000714
Address@madc_seq1 : 0x49000814
Address@madc_seq2 : 0x49000914
Address@madc_seq3 : 0x49000a14
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux5
ADC sample extension for input channel 5
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x49000718
Address@madc_seq1 : 0x49000818
Address@madc_seq2 : 0x49000918
Address@madc_seq3 : 0x49000a18
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux6
ADC sample extension for input channel 6
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x4900071c
Address@madc_seq1 : 0x4900081c
Address@madc_seq2 : 0x4900091c
Address@madc_seq3 : 0x49000a1c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_tracking_time_mux7
ADC sample extension for input channel 7
s. madc_seq_tracking_time_mux0 for details.
R/W
0x00000004
Address@madc_seq0 : 0x49000720
Address@madc_seq1 : 0x49000820
Address@madc_seq2 : 0x49000920
Address@madc_seq3 : 0x49000a20
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000100"
tt_add
Tracking time addon


madc_seq_ms_en
Enable measurement configurations:
Terminology:
A measurement sequence consists of upto 8 measurements.
A measurement consists of up to 8 samples.
A sample needs at least 14 adcclk cycles (+ tracking time addon).
This register enables the measurements belonging to a measurement sequence (up to 8).
With the start of a measurement sequence (s. madc_seq_cmd) all sequence configuration registers (ms_en, ms_adr, m0..m7) are copied to shadow registers that can no longer be changed until the measurement sequence is finished. All further write accesses to these registers will be valid
for the subsequent measurement sequence.
The software must ensure, that a set of configuration data for one sequence is completely written before starting the next sequence.
R/W
0x00000000
Address@madc_seq0 : 0x49000724
Address@madc_seq1 : 0x49000824
Address@madc_seq2 : 0x49000924
Address@madc_seq3 : 0x49000a24
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
m7
1: Enable measurement defined by madc_seq_m7 for the current measurement sequence
6 "0"
m6
1: Enable measurement defined by madc_seq_m6 for the current measurement sequence
5 "0"
m5
1: Enable measurement defined by madc_seq_m5 for the current measurement sequence
4 "0"
m4
1: Enable measurement defined by madc_seq_m4 for the current measurement sequence
3 "0"
m3
1: Enable measurement defined by madc_seq_m3 for the current measurement sequence
2 "0"
m2
1: Enable measurement defined by madc_seq_m2 for the current measurement sequence
1 "0"
m1
1: Enable measurement defined by madc_seq_m1 for the current measurement sequence
0 "0"
m0
1: Enable measurement defined by madc_seq_m0 for the current measurement sequence


madc_seq_ms_baseadr
Base address for writing the measurement results.
R/W
0x00000000
Address@madc_seq0 : 0x49000728
Address@madc_seq1 : 0x49000828
Address@madc_seq2 : 0x49000928
Address@madc_seq3 : 0x49000a28
Bits Reset value Name Description
31 - 1 0x0
adr
word (16 bit) aligned address, LSB is ignored
In case of madc_seq_cfg-dma_32bit_adr=1, bit 1 will be ignored.
0 0
-
 reserved


madc_seq_m0
Measurement 0 configuration:
A measurement performs (oversample+1) ADC conversions, summing up the results.
Every ADC conversion starts with two adcclk periods followed by a sampling phase extension with a minimal duration selected by sext_sel.
The sampling phase of the first ADC conversion of the measurement ends when the trigger condition is fulfilled.
All subsequent conversions of the measurement do not wait for any trigger condition.
The sum consisting of (oversample+1) ADC conversions is written as a 16 bit word to the memory location (byte address) ms_adr + 2*adr_offset.
During the measurement the input multiplexer setting (channel selection) is changed to the value mux.
Depending on the timing selected by mux_time_sel the channel setting becomes effective for this or the next measurement.
R/W
0x0001ffff
Address@madc_seq0 : 0x4900072c
Address@madc_seq1 : 0x4900082c
Address@madc_seq2 : 0x4900092c
Address@madc_seq3 : 0x49000a2c
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
In case of madc_seq_cfg-dma_32bit_adr=1, this value will be interpreted as 32-bit address.
22 - 20 "000"
mux
Input channel multiplexer setting
The input multiplexer will always be set 1 system clock (10ns) before SOF.
It will be reset after sampling to ensure a not-connected phase at the one-hot-coded multiplexer switches.
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
i.e. 0:sum 1 samples, 1:sum 2 samples, ...
16 - 0 0x1ffff
trigger
Trigger condition for measurement
0x0...0x0FFFF: condition (ECNT == trigger)
0x10000...0x10005: delayed DTEVT[0..5]==1
0x10006: GPIO_APP_COUNTER0 = 0
0x10007: GPIO_APP_COUNTER1 = 0
0x10008: GPIO_APP_COUNTER2 = 0
0x10009: posedge of xc_trigger[0]
0x1000a: posedge of xc_trigger[1]
0x1000b: negedge of xc_trigger[0]
0x1000c: negedge of xc_trigger[1]
0x1000d: posedge of xc_sample[0]
0x1000e: posedge of xc_sample[1]
0x1000f: negedge of xc_sample[0]
0x10010: negedge of xc_sample[1]
0x1FFFF: no trigger, measurement executes immediately after end of sampling phase
Note: Ensure that the time between SOC and trigger event does not exceed ADC_MAXTRACK (10ms).


madc_seq_m1
Measurement 1 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000730
Address@madc_seq1 : 0x49000830
Address@madc_seq2 : 0x49000930
Address@madc_seq3 : 0x49000a30
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m2
Measurement 2 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000734
Address@madc_seq1 : 0x49000834
Address@madc_seq2 : 0x49000934
Address@madc_seq3 : 0x49000a34
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m3
Measurement 3 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000738
Address@madc_seq1 : 0x49000838
Address@madc_seq2 : 0x49000938
Address@madc_seq3 : 0x49000a38
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m4
Measurement 4 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x4900073c
Address@madc_seq1 : 0x4900083c
Address@madc_seq2 : 0x4900093c
Address@madc_seq3 : 0x49000a3c
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m5
Measurement 5 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000740
Address@madc_seq1 : 0x49000840
Address@madc_seq2 : 0x49000940
Address@madc_seq3 : 0x49000a40
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m6
Measurement 6 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000744
Address@madc_seq1 : 0x49000844
Address@madc_seq2 : 0x49000944
Address@madc_seq3 : 0x49000a44
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_m7
Measurement 7 configuration:
s. madc_seq_m0 for details
R/W
0x0001ffff
Address@madc_seq0 : 0x49000748
Address@madc_seq1 : 0x49000848
Address@madc_seq2 : 0x49000948
Address@madc_seq3 : 0x49000a48
Bits Reset value Name Description
31 - 28 0
-
 reserved
27 - 23 "00000"
adr_offset
Address offset specified in 16 bit words where the sum will be stored
22 - 20 "000"
mux
Input channel multiplexer setting
19 - 17 "000"
oversample
Number of samples minus one to sum for this measurement
16 - 0 0x1ffff
trigger
Trigger condition for measurement


madc_seq_cmd
Command Register:
Run or abort processing the measurement sequence.
This register is writable but can also be changed by hardware (reset).
R/W
0x00000000
Address@madc_seq0 : 0x4900074c
Address@madc_seq1 : 0x4900084c
Address@madc_seq2 : 0x4900094c
Address@madc_seq3 : 0x49000a4c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
debug
Debug mode:
0: ADC is controlled by measurement sequencer
1: ADC is directly controlled by madc_seq_debug register.
2 "0"
reset
Reset this ADC-sequencer:
In comparision to madc_adc01_static_cfg-adc01_reset_n, which resets a pair of ADC channels (e.g. ADC0 and ADC1), this bit only resets this single ADC-sequencer. The analog part of ADC will not be reset, but all registers of the controller (including result registers, which will not be reset in case of run=stop).
1 "0"
continuous
Continuous mode:
0: run starts single conversion. All measurements enabled in madc_m_en are executed once.
1: start continuous conversion. All measurments enabled are executed repeatedly until stopped by resetting the run bit.
0 "0"
run
Run bit:
This bit can be set here or at madc_start to start all ADCs simultaneously.
This bit can be reset here or automatically by hardware, when measurement sequence is finished.
1 : start measurement sequence.
0 : stop measurement sequence. Any conversion in progress is aborted and ADC returns to idle state with adcclk=0 and adc_soc=0.


madc_seq_status
Status of the current measurement sequence in progress
R
Address@madc_seq0 : 0x49000750
Address@madc_seq1 : 0x49000850
Address@madc_seq2 : 0x49000950
Address@madc_seq3 : 0x49000a50
Bits Name Description
31 - 9 -
 reserved
8 - 4 adc_half_clock_cycle
0..30: current adcclk half clock cycle, 0 when adc is idle
3 - 0 m_nr
Number of measurement configuration:
0..7: currently active measurement configuration, 8 when the ADC is idle


madc_seq_result_current
Result register of current measurement
R
Address@madc_seq0 : 0x49000754
Address@madc_seq1 : 0x49000854
Address@madc_seq2 : 0x49000954
Address@madc_seq3 : 0x49000a54
Bits Name Description
31 valid
result in register is finally calculated (val shows intermediate values in case of oversample>0)
30 - 19 -
 reserved
18 - 16 mnr
number of measurement configuration
15 - 0 val
result of measurement


madc_seq_result_last
Result register of last measurement
R
Address@madc_seq0 : 0x49000758
Address@madc_seq1 : 0x49000858
Address@madc_seq2 : 0x49000958
Address@madc_seq3 : 0x49000a58
Bits Name Description
31 valid
result in register is finally calculated (val shows intermediate values in case of oversample>0)
30 - 19 -
 reserved
18 - 16 mnr
number of measurement configuration
15 - 0 val
result of measurement


madc_seq_debug
Debug Mode register:
If cmd-debug is enabled, this register directly controls inputs of both ADCs.
Output data of both ADCs will still be at data0 and data1.
In debug mode, a software reset (cfg-reset_n) will not influence these values (only directly signal ADC_NRES).
R/W
0x00000000
Address@madc_seq0 : 0x4900075c
Address@madc_seq1 : 0x4900085c
Address@madc_seq2 : 0x4900095c
Address@madc_seq3 : 0x49000a5c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
adc_set_mux3
ADC_SET_MUX3 signal
4 "0"
adc_set_mux2
ADC_SET_MUX2 signal
3 "0"
adc_set_mux1
ADC_SET_MUX1 signal
2 "0"
adc_set_mux0
ADC_SET_MUX0 signal
1 "0"
adc_res
ADC_res signal
0 "0"
adc_clk
ADC is sampling data.


madc_seq_irq_raw
Raw IRQ:
Read access shows status of unmasked IRQs.
IRQs are set automatically and reset by writing to this register:
Write access with '1' resets the appropriate IRQ (if event irq, reset status irqs at their source).
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@madc_seq0 : 0x49000770
Address@madc_seq1 : 0x49000870
Address@madc_seq2 : 0x49000970
Address@madc_seq3 : 0x49000a70
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
dma_hresp
AHBL hresp signal received
9 "0"
dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
seq_cmpl
measurement sequence completed
7 "0"
m7_cmpl
event: measurement 7 completed
6 "0"
m6_cmpl
event: measurement 6 completed
5 "0"
m5_cmpl
event: measurement 5 completed
4 "0"
m4_cmpl
event: measurement 4 completed
3 "0"
m3_cmpl
event: measurement 3 completed
2 "0"
m2_cmpl
event: measurement 2 completed
1 "0"
m1_cmpl
event: measurement 1 completed
0 "0"
m0_cmpl
event: measurement 0 completed


madc_seq_irq_masked
Masked IRQ:
Shows status of masked IRQs (as connected to ARM/xPIC).
R
Address@madc_seq0 : 0x49000774
Address@madc_seq1 : 0x49000874
Address@madc_seq2 : 0x49000974
Address@madc_seq3 : 0x49000a74
Bits Name Description
31 - 11 -
 reserved
10 dma_hresp
AHBL hresp signal received
9 dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 seq_cmpl
measurement sequence completed
7 m7_cmpl
event: measurement 7 completed
6 m6_cmpl
event: measurement 6 completed
5 m5_cmpl
event: measurement 5 completed
4 m4_cmpl
event: measurement 4 completed
3 m3_cmpl
event: measurement 3 completed
2 m2_cmpl
event: measurement 2 completed
1 m1_cmpl
event: measurement 1 completed
0 m0_cmpl
event: measurement 0 completed


madc_seq_irq_mask_set
IRQ enable mask:
The IRQ mask enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by set and reset masks:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Attention: Before activating interrupt mask, delete old pending interrupts by writing the same value to adr_mpwm_irq_raw.
R/W
0x00000000
Address@madc_seq0 : 0x49000778
Address@madc_seq1 : 0x49000878
Address@madc_seq2 : 0x49000978
Address@madc_seq3 : 0x49000a78
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
dma_hresp
AHBL hresp signal received
9 "0"
dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
seq_cmpl
measurement sequence completed
7 "0"
m7_cmpl
event: measurement 7 completed
6 "0"
m6_cmpl
event: measurement 6 completed
5 "0"
m5_cmpl
event: measurement 5 completed
4 "0"
m4_cmpl
event: measurement 4 completed
3 "0"
m3_cmpl
event: measurement 3 completed
2 "0"
m2_cmpl
event: measurement 2 completed
1 "0"
m1_cmpl
event: measurement 1 completed
0 "0"
m0_cmpl
event: measurement 0 completed


madc_seq_irq_mask_reset
IRQ disable mask:
This is the corresponding reset mask to disable interrupt requests for corresponding interrupt sources:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows bit number of the lowest active bit in IRQ_MASKED or MAX+1 when no bit is set.
R/W
0x00000000
Address@madc_seq0 : 0x4900077c
Address@madc_seq1 : 0x4900087c
Address@madc_seq2 : 0x4900097c
Address@madc_seq3 : 0x49000a7c
Bits Reset value Name Description
31 - 11 0
-
 reserved
10 "0"
dma_hresp
AHBL hresp signal received
9 "0"
dma_overrun
AHBL write buffer overrun
result not written due to AHBL busy
8 "0"
seq_cmpl
measurement sequence completed
7 "0"
m7_cmpl
event: measurement 7 completed
6 "0"
m6_cmpl
event: measurement 6 completed
5 "0"
m5_cmpl
event: measurement 5 completed
4 "0"
m4_cmpl
event: measurement 4 completed
3 "0"
m3_cmpl
event: measurement 3 completed
2 "0"
m2_cmpl
event: measurement 2 completed
1 "0"
m1_cmpl
event: measurement 1 completed
0 "0"
m0_cmpl
event: measurement 0 completed



Base Address Area: mot_irq_router_cpu0_motion_exp_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_motion_exp_0_irq_raw
1 4 R/W mot_irq_router_cpu0_motion_exp_0_irq_masked
2 8 R/W mot_irq_router_cpu0_motion_exp_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_motion_exp_0_irq_mask_rst

mot_irq_router_cpu0_motion_exp_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210000
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu0_motion_exp_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_motion_exp_0_irq_raw).
R/W
0x00000000
Address : 0x49210004
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu0_motion_exp_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_motion_exp_0_irq_raw
R/W
0x00000000
Address : 0x49210008
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu0_motion_exp_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 22 when no IRQ is set:
  0  : motion_exp_0_irq-madc_seq_0
  1  : motion_exp_0_irq-madc_seq_1
  2  : motion_exp_0_irq-madc_seq_2
  3  : motion_exp_0_irq-madc_seq_3
  4  : motion_exp_0_irq-sdfm_0
  5  : motion_exp_0_irq-sdfm_1
  6  : motion_exp_0_irq-sdfm_2
  7  : motion_exp_0_irq-menc_enc_0
  8  : motion_exp_0_irq-menc_enc_1
  9  : motion_exp_0_irq-biss_0
  10 : motion_exp_0_irq-biss_1
  11 : motion_exp_0_irq-endat_0
  12 : motion_exp_0_irq-endat_1
  13 : motion_exp_0_irq-trigger_irq_0
  14 : motion_exp_0_irq-trigger_irq_1
  15 : motion_exp_0_irq-trigger_irq_global_0
  16 : motion_exp_0_irq-trigger_irq_global_1
  17 : motion_exp_0_irq-mpwm_0
  18 : motion_exp_0_irq-menc_cap_mp_0
  19 : motion_exp_0_irq-menc_err_0
  20 : motion_exp_0_irq-sync_timer_0
  21 : motion_exp_0_irq-sync_timer_global_0
  22 : no active IRQ
R/W
0x00000000
Address : 0x4921000c
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]



Base Address Area: mot_irq_router_cpu0_sync_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_sync_0_irq_raw
1 4 R/W mot_irq_router_cpu0_sync_0_irq_masked
2 8 R/W mot_irq_router_cpu0_sync_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_sync_0_irq_mask_rst

mot_irq_router_cpu0_sync_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210010
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu0_sync_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_sync_0_irq_raw).
R/W
0x00000000
Address : 0x49210014
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu0_sync_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_sync_0_irq_raw
R/W
0x00000000
Address : 0x49210018
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu0_sync_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 2 when no IRQ is set:
  0 : sync_0_irq-sync_timer_0
  1 : sync_0_irq-sync_timer_global_0
  2 : no active IRQ
R/W
0x00000000
Address : 0x4921001c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]



Base Address Area: mot_irq_router_cpu0_mpwm_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_mpwm_0_irq_raw
1 4 R/W mot_irq_router_cpu0_mpwm_0_irq_masked
2 8 R/W mot_irq_router_cpu0_mpwm_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_mpwm_0_irq_mask_rst

mot_irq_router_cpu0_mpwm_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210020
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu0_mpwm_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_mpwm_0_irq_raw).
R/W
0x00000000
Address : 0x49210024
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu0_mpwm_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_mpwm_0_irq_raw
R/W
0x00000000
Address : 0x49210028
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu0_mpwm_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 1 when no IRQ is set:
  0 : mpwm_0_irq-mpwm_0
  1 : no active IRQ
R/W
0x00000000
Address : 0x4921002c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]



Base Address Area: mot_irq_router_cpu0_adc_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_adc_0_irq_raw
1 4 R/W mot_irq_router_cpu0_adc_0_irq_masked
2 8 R/W mot_irq_router_cpu0_adc_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_adc_0_irq_mask_rst

mot_irq_router_cpu0_adc_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210030
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu0_adc_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_adc_0_irq_raw).
R/W
0x00000000
Address : 0x49210034
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu0_adc_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_adc_0_irq_raw
R/W
0x00000000
Address : 0x49210038
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu0_adc_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : adc_0_irq-madc_seq_0
  1 : adc_0_irq-madc_seq_1
  2 : adc_0_irq-sdfm_0
  3 : adc_0_irq-sdfm_1
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921003c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]



Base Address Area: mot_irq_router_cpu0_adc_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_adc_1_irq_raw
1 4 R/W mot_irq_router_cpu0_adc_1_irq_masked
2 8 R/W mot_irq_router_cpu0_adc_1_irq_mask_set
3 c R/W mot_irq_router_cpu0_adc_1_irq_mask_rst

mot_irq_router_cpu0_adc_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210040
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu0_adc_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_adc_1_irq_raw).
R/W
0x00000000
Address : 0x49210044
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu0_adc_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_adc_1_irq_raw
R/W
0x00000000
Address : 0x49210048
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu0_adc_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 3 when no IRQ is set:
  0 : adc_1_irq-madc_seq_2
  1 : adc_1_irq-madc_seq_3
  2 : adc_1_irq-sdfm_2
  3 : no active IRQ
R/W
0x00000000
Address : 0x4921004c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]



Base Address Area: mot_irq_router_cpu0_enc_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_enc_0_irq_raw
1 4 R/W mot_irq_router_cpu0_enc_0_irq_masked
2 8 R/W mot_irq_router_cpu0_enc_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_enc_0_irq_mask_rst

mot_irq_router_cpu0_enc_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210050
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu0_enc_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_enc_0_irq_raw).
R/W
0x00000000
Address : 0x49210054
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu0_enc_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_enc_0_irq_raw
R/W
0x00000000
Address : 0x49210058
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu0_enc_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : enc_0_irq-menc_enc_0
  1 : enc_0_irq-menc_cap_mp_0
  2 : enc_0_irq-biss_0
  3 : enc_0_irq-endat_0
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921005c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]



Base Address Area: mot_irq_router_cpu0_enc_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_enc_1_irq_raw
1 4 R/W mot_irq_router_cpu0_enc_1_irq_masked
2 8 R/W mot_irq_router_cpu0_enc_1_irq_mask_set
3 c R/W mot_irq_router_cpu0_enc_1_irq_mask_rst

mot_irq_router_cpu0_enc_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210060
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu0_enc_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_enc_1_irq_raw).
R/W
0x00000000
Address : 0x49210064
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu0_enc_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_enc_1_irq_raw
R/W
0x00000000
Address : 0x49210068
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu0_enc_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : enc_1_irq-menc_enc_1
  1 : enc_1_irq-menc_cap_mp_0
  2 : enc_1_irq-biss_1
  3 : enc_1_irq-endat_1
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921006c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]



Base Address Area: mot_irq_router_cpu0_com_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_com_0_irq_raw
1 4 R/W mot_irq_router_cpu0_com_0_irq_masked
2 8 R/W mot_irq_router_cpu0_com_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_com_0_irq_mask_rst

mot_irq_router_cpu0_com_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210070
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu0_com_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_com_0_irq_raw).
R/W
0x00000000
Address : 0x49210074
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu0_com_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_com_0_irq_raw
R/W
0x00000000
Address : 0x49210078
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu0_com_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_0_irq-mhu_0
  1  : com_0_irq-mhu_1
  2  : com_0_irq-mhu_2
  3  : com_0_irq-mhu_3
  4  : com_0_irq-mhu_4
  5  : com_0_irq-mhu_5
  6  : com_0_irq-mhu_6
  7  : com_0_irq-mhu_7
  8  : com_0_irq-sms_0
  9  : com_0_irq-sms_1
  10 : com_0_irq-sms_2
  11 : com_0_irq-sms_3
  12 : com_0_irq-hsc_0
  13 : com_0_irq-hsc_1
  14 : com_0_irq-hsc_2
  15 : com_0_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921007c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]



Base Address Area: mot_irq_router_cpu0_com_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_com_1_irq_raw
1 4 R/W mot_irq_router_cpu0_com_1_irq_masked
2 8 R/W mot_irq_router_cpu0_com_1_irq_mask_set
3 c R/W mot_irq_router_cpu0_com_1_irq_mask_rst

mot_irq_router_cpu0_com_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210080
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu0_com_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_com_1_irq_raw).
R/W
0x00000000
Address : 0x49210084
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu0_com_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_com_1_irq_raw
R/W
0x00000000
Address : 0x49210088
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu0_com_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_1_irq-mhu_0
  1  : com_1_irq-mhu_1
  2  : com_1_irq-mhu_2
  3  : com_1_irq-mhu_3
  4  : com_1_irq-mhu_4
  5  : com_1_irq-mhu_5
  6  : com_1_irq-mhu_6
  7  : com_1_irq-mhu_7
  8  : com_1_irq-sms_0
  9  : com_1_irq-sms_1
  10 : com_1_irq-sms_2
  11 : com_1_irq-sms_3
  12 : com_1_irq-hsc_0
  13 : com_1_irq-hsc_1
  14 : com_1_irq-hsc_2
  15 : com_1_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921008c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]



Base Address Area: mot_irq_router_cpu0_com_2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_com_2_irq_raw
1 4 R/W mot_irq_router_cpu0_com_2_irq_masked
2 8 R/W mot_irq_router_cpu0_com_2_irq_mask_set
3 c R/W mot_irq_router_cpu0_com_2_irq_mask_rst

mot_irq_router_cpu0_com_2_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210090
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu0_com_2_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_com_2_irq_raw).
R/W
0x00000000
Address : 0x49210094
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu0_com_2_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_com_2_irq_raw
R/W
0x00000000
Address : 0x49210098
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu0_com_2_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_2_irq-mhu_0
  1  : com_2_irq-mhu_1
  2  : com_2_irq-mhu_2
  3  : com_2_irq-mhu_3
  4  : com_2_irq-mhu_4
  5  : com_2_irq-mhu_5
  6  : com_2_irq-mhu_6
  7  : com_2_irq-mhu_7
  8  : com_2_irq-sms_0
  9  : com_2_irq-sms_1
  10 : com_2_irq-sms_2
  11 : com_2_irq-sms_3
  12 : com_2_irq-hsc_0
  13 : com_2_irq-hsc_1
  14 : com_2_irq-hsc_2
  15 : com_2_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921009c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]



Base Address Area: mot_irq_router_cpu0_com_3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_com_3_irq_raw
1 4 R/W mot_irq_router_cpu0_com_3_irq_masked
2 8 R/W mot_irq_router_cpu0_com_3_irq_mask_set
3 c R/W mot_irq_router_cpu0_com_3_irq_mask_rst

mot_irq_router_cpu0_com_3_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492100a0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu0_com_3_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_com_3_irq_raw).
R/W
0x00000000
Address : 0x492100a4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu0_com_3_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_com_3_irq_raw
R/W
0x00000000
Address : 0x492100a8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu0_com_3_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_3_irq-mhu_0
  1  : com_3_irq-mhu_1
  2  : com_3_irq-mhu_2
  3  : com_3_irq-mhu_3
  4  : com_3_irq-mhu_4
  5  : com_3_irq-mhu_5
  6  : com_3_irq-mhu_6
  7  : com_3_irq-mhu_7
  8  : com_3_irq-sms_0
  9  : com_3_irq-sms_1
  10 : com_3_irq-sms_2
  11 : com_3_irq-sms_3
  12 : com_3_irq-hsc_0
  13 : com_3_irq-hsc_1
  14 : com_3_irq-hsc_2
  15 : com_3_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x492100ac
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]



Base Address Area: mot_irq_router_cpu0_peri_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_peri_0_0_irq_raw
1 4 R/W mot_irq_router_cpu0_peri_0_1_irq_raw
2 8 R/W mot_irq_router_cpu0_peri_0_0_irq_masked
3 c R/W mot_irq_router_cpu0_peri_0_1_irq_masked
4 10 R/W mot_irq_router_cpu0_peri_0_0_irq_mask_set
5 14 R/W mot_irq_router_cpu0_peri_0_1_irq_mask_set
6 18 R/W mot_irq_router_cpu0_peri_0_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu0_peri_0_1_irq_mask_rst

mot_irq_router_cpu0_peri_0_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492100c0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492100c4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_0_0_irq_raw).
R/W
0x00000000
Address : 0x492100c8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_0_1_irq_raw).
R/W
0x00000000
Address : 0x492100cc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_0_0_irq_raw
R/W
0x00000000
Address : 0x492100d0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_0_1_irq_raw
R/W
0x00000000
Address : 0x492100d4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_0_0_irq-gpio_0
  1  : peri_0_0_irq-gpio_1
  2  : peri_0_0_irq-gpio_2
  3  : peri_0_0_irq-gpio_3
  4  : peri_0_0_irq-gpio_4
  5  : peri_0_0_irq-gpio_5
  6  : peri_0_0_irq-gpio_6
  7  : peri_0_0_irq-gpio_7
  8  : peri_0_0_irq-gpio_8
  9  : peri_0_0_irq-gpio_9
  10 : peri_0_0_irq-gpio_10
  11 : peri_0_0_irq-gpio_11
  12 : peri_0_0_irq-gpio_12
  13 : peri_0_0_irq-gpio_13
  14 : peri_0_0_irq-gpio_14
  15 : peri_0_0_irq-gpio_15
  16 : peri_0_0_irq-timer0_0
  17 : peri_0_0_irq-timer0_1
  18 : peri_0_0_irq-timer0_2
  19 : peri_0_0_irq-timer0_3
  20 : peri_0_0_irq-timer1_0
  21 : peri_0_0_irq-timer1_1
  22 : peri_0_0_irq-timer1_2
  23 : peri_0_0_irq-timer1_3
  24 : peri_0_0_irq-uart_0
  25 : peri_0_0_irq-uart_1
  26 : peri_0_0_irq-i2c_0
  27 : peri_0_0_irq-i2c_1
  28 : peri_0_0_irq-spi_0
  29 : peri_0_0_irq-spi_1
  30 : peri_0_0_irq-sqi_0
  31 : peri_0_0_irq-sqi_1
  32 : peri_0_1_irq-wdg0_0
  33 : peri_0_1_irq-wdg0_1
  34 : peri_0_1_irq-wdg1_0
  35 : peri_0_1_irq-wdg1_1
  36 : peri_0_1_irq-pio_0
  37 : peri_0_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492100d8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu0_peri_0_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_0_0_irq-gpio_0
  1  : peri_0_0_irq-gpio_1
  2  : peri_0_0_irq-gpio_2
  3  : peri_0_0_irq-gpio_3
  4  : peri_0_0_irq-gpio_4
  5  : peri_0_0_irq-gpio_5
  6  : peri_0_0_irq-gpio_6
  7  : peri_0_0_irq-gpio_7
  8  : peri_0_0_irq-gpio_8
  9  : peri_0_0_irq-gpio_9
  10 : peri_0_0_irq-gpio_10
  11 : peri_0_0_irq-gpio_11
  12 : peri_0_0_irq-gpio_12
  13 : peri_0_0_irq-gpio_13
  14 : peri_0_0_irq-gpio_14
  15 : peri_0_0_irq-gpio_15
  16 : peri_0_0_irq-timer0_0
  17 : peri_0_0_irq-timer0_1
  18 : peri_0_0_irq-timer0_2
  19 : peri_0_0_irq-timer0_3
  20 : peri_0_0_irq-timer1_0
  21 : peri_0_0_irq-timer1_1
  22 : peri_0_0_irq-timer1_2
  23 : peri_0_0_irq-timer1_3
  24 : peri_0_0_irq-uart_0
  25 : peri_0_0_irq-uart_1
  26 : peri_0_0_irq-i2c_0
  27 : peri_0_0_irq-i2c_1
  28 : peri_0_0_irq-spi_0
  29 : peri_0_0_irq-spi_1
  30 : peri_0_0_irq-sqi_0
  31 : peri_0_0_irq-sqi_1
  32 : peri_0_1_irq-wdg0_0
  33 : peri_0_1_irq-wdg0_1
  34 : peri_0_1_irq-wdg1_0
  35 : peri_0_1_irq-wdg1_1
  36 : peri_0_1_irq-pio_0
  37 : peri_0_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492100dc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]



Base Address Area: mot_irq_router_cpu0_peri_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_peri_1_0_irq_raw
1 4 R/W mot_irq_router_cpu0_peri_1_1_irq_raw
2 8 R/W mot_irq_router_cpu0_peri_1_0_irq_masked
3 c R/W mot_irq_router_cpu0_peri_1_1_irq_masked
4 10 R/W mot_irq_router_cpu0_peri_1_0_irq_mask_set
5 14 R/W mot_irq_router_cpu0_peri_1_1_irq_mask_set
6 18 R/W mot_irq_router_cpu0_peri_1_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu0_peri_1_1_irq_mask_rst

mot_irq_router_cpu0_peri_1_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492100e0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492100e4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_1_0_irq_raw).
R/W
0x00000000
Address : 0x492100e8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_1_1_irq_raw).
R/W
0x00000000
Address : 0x492100ec
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_1_0_irq_raw
R/W
0x00000000
Address : 0x492100f0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_1_1_irq_raw
R/W
0x00000000
Address : 0x492100f4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_1_0_irq-gpio_0
  1  : peri_1_0_irq-gpio_1
  2  : peri_1_0_irq-gpio_2
  3  : peri_1_0_irq-gpio_3
  4  : peri_1_0_irq-gpio_4
  5  : peri_1_0_irq-gpio_5
  6  : peri_1_0_irq-gpio_6
  7  : peri_1_0_irq-gpio_7
  8  : peri_1_0_irq-gpio_8
  9  : peri_1_0_irq-gpio_9
  10 : peri_1_0_irq-gpio_10
  11 : peri_1_0_irq-gpio_11
  12 : peri_1_0_irq-gpio_12
  13 : peri_1_0_irq-gpio_13
  14 : peri_1_0_irq-gpio_14
  15 : peri_1_0_irq-gpio_15
  16 : peri_1_0_irq-timer0_0
  17 : peri_1_0_irq-timer0_1
  18 : peri_1_0_irq-timer0_2
  19 : peri_1_0_irq-timer0_3
  20 : peri_1_0_irq-timer1_0
  21 : peri_1_0_irq-timer1_1
  22 : peri_1_0_irq-timer1_2
  23 : peri_1_0_irq-timer1_3
  24 : peri_1_0_irq-uart_0
  25 : peri_1_0_irq-uart_1
  26 : peri_1_0_irq-i2c_0
  27 : peri_1_0_irq-i2c_1
  28 : peri_1_0_irq-spi_0
  29 : peri_1_0_irq-spi_1
  30 : peri_1_0_irq-sqi_0
  31 : peri_1_0_irq-sqi_1
  32 : peri_1_1_irq-wdg0_0
  33 : peri_1_1_irq-wdg0_1
  34 : peri_1_1_irq-wdg1_0
  35 : peri_1_1_irq-wdg1_1
  36 : peri_1_1_irq-pio_0
  37 : peri_1_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492100f8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu0_peri_1_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_1_0_irq-gpio_0
  1  : peri_1_0_irq-gpio_1
  2  : peri_1_0_irq-gpio_2
  3  : peri_1_0_irq-gpio_3
  4  : peri_1_0_irq-gpio_4
  5  : peri_1_0_irq-gpio_5
  6  : peri_1_0_irq-gpio_6
  7  : peri_1_0_irq-gpio_7
  8  : peri_1_0_irq-gpio_8
  9  : peri_1_0_irq-gpio_9
  10 : peri_1_0_irq-gpio_10
  11 : peri_1_0_irq-gpio_11
  12 : peri_1_0_irq-gpio_12
  13 : peri_1_0_irq-gpio_13
  14 : peri_1_0_irq-gpio_14
  15 : peri_1_0_irq-gpio_15
  16 : peri_1_0_irq-timer0_0
  17 : peri_1_0_irq-timer0_1
  18 : peri_1_0_irq-timer0_2
  19 : peri_1_0_irq-timer0_3
  20 : peri_1_0_irq-timer1_0
  21 : peri_1_0_irq-timer1_1
  22 : peri_1_0_irq-timer1_2
  23 : peri_1_0_irq-timer1_3
  24 : peri_1_0_irq-uart_0
  25 : peri_1_0_irq-uart_1
  26 : peri_1_0_irq-i2c_0
  27 : peri_1_0_irq-i2c_1
  28 : peri_1_0_irq-spi_0
  29 : peri_1_0_irq-spi_1
  30 : peri_1_0_irq-sqi_0
  31 : peri_1_0_irq-sqi_1
  32 : peri_1_1_irq-wdg0_0
  33 : peri_1_1_irq-wdg0_1
  34 : peri_1_1_irq-wdg1_0
  35 : peri_1_1_irq-wdg1_1
  36 : peri_1_1_irq-pio_0
  37 : peri_1_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492100fc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]



Base Address Area: mot_irq_router_cpu0_peri_2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_peri_2_0_irq_raw
1 4 R/W mot_irq_router_cpu0_peri_2_1_irq_raw
2 8 R/W mot_irq_router_cpu0_peri_2_0_irq_masked
3 c R/W mot_irq_router_cpu0_peri_2_1_irq_masked
4 10 R/W mot_irq_router_cpu0_peri_2_0_irq_mask_set
5 14 R/W mot_irq_router_cpu0_peri_2_1_irq_mask_set
6 18 R/W mot_irq_router_cpu0_peri_2_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu0_peri_2_1_irq_mask_rst

mot_irq_router_cpu0_peri_2_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210100
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210104
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_2_0_irq_raw).
R/W
0x00000000
Address : 0x49210108
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_2_1_irq_raw).
R/W
0x00000000
Address : 0x4921010c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_2_0_irq_raw
R/W
0x00000000
Address : 0x49210110
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_2_1_irq_raw
R/W
0x00000000
Address : 0x49210114
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_2_0_irq-gpio_0
  1  : peri_2_0_irq-gpio_1
  2  : peri_2_0_irq-gpio_2
  3  : peri_2_0_irq-gpio_3
  4  : peri_2_0_irq-gpio_4
  5  : peri_2_0_irq-gpio_5
  6  : peri_2_0_irq-gpio_6
  7  : peri_2_0_irq-gpio_7
  8  : peri_2_0_irq-gpio_8
  9  : peri_2_0_irq-gpio_9
  10 : peri_2_0_irq-gpio_10
  11 : peri_2_0_irq-gpio_11
  12 : peri_2_0_irq-gpio_12
  13 : peri_2_0_irq-gpio_13
  14 : peri_2_0_irq-gpio_14
  15 : peri_2_0_irq-gpio_15
  16 : peri_2_0_irq-timer0_0
  17 : peri_2_0_irq-timer0_1
  18 : peri_2_0_irq-timer0_2
  19 : peri_2_0_irq-timer0_3
  20 : peri_2_0_irq-timer1_0
  21 : peri_2_0_irq-timer1_1
  22 : peri_2_0_irq-timer1_2
  23 : peri_2_0_irq-timer1_3
  24 : peri_2_0_irq-uart_0
  25 : peri_2_0_irq-uart_1
  26 : peri_2_0_irq-i2c_0
  27 : peri_2_0_irq-i2c_1
  28 : peri_2_0_irq-spi_0
  29 : peri_2_0_irq-spi_1
  30 : peri_2_0_irq-sqi_0
  31 : peri_2_0_irq-sqi_1
  32 : peri_2_1_irq-wdg0_0
  33 : peri_2_1_irq-wdg0_1
  34 : peri_2_1_irq-wdg1_0
  35 : peri_2_1_irq-wdg1_1
  36 : peri_2_1_irq-pio_0
  37 : peri_2_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x49210118
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu0_peri_2_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_2_0_irq-gpio_0
  1  : peri_2_0_irq-gpio_1
  2  : peri_2_0_irq-gpio_2
  3  : peri_2_0_irq-gpio_3
  4  : peri_2_0_irq-gpio_4
  5  : peri_2_0_irq-gpio_5
  6  : peri_2_0_irq-gpio_6
  7  : peri_2_0_irq-gpio_7
  8  : peri_2_0_irq-gpio_8
  9  : peri_2_0_irq-gpio_9
  10 : peri_2_0_irq-gpio_10
  11 : peri_2_0_irq-gpio_11
  12 : peri_2_0_irq-gpio_12
  13 : peri_2_0_irq-gpio_13
  14 : peri_2_0_irq-gpio_14
  15 : peri_2_0_irq-gpio_15
  16 : peri_2_0_irq-timer0_0
  17 : peri_2_0_irq-timer0_1
  18 : peri_2_0_irq-timer0_2
  19 : peri_2_0_irq-timer0_3
  20 : peri_2_0_irq-timer1_0
  21 : peri_2_0_irq-timer1_1
  22 : peri_2_0_irq-timer1_2
  23 : peri_2_0_irq-timer1_3
  24 : peri_2_0_irq-uart_0
  25 : peri_2_0_irq-uart_1
  26 : peri_2_0_irq-i2c_0
  27 : peri_2_0_irq-i2c_1
  28 : peri_2_0_irq-spi_0
  29 : peri_2_0_irq-spi_1
  30 : peri_2_0_irq-sqi_0
  31 : peri_2_0_irq-sqi_1
  32 : peri_2_1_irq-wdg0_0
  33 : peri_2_1_irq-wdg0_1
  34 : peri_2_1_irq-wdg1_0
  35 : peri_2_1_irq-wdg1_1
  36 : peri_2_1_irq-pio_0
  37 : peri_2_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x4921011c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]



Base Address Area: mot_irq_router_cpu0_peri_3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_peri_3_0_irq_raw
1 4 R/W mot_irq_router_cpu0_peri_3_1_irq_raw
2 8 R/W mot_irq_router_cpu0_peri_3_0_irq_masked
3 c R/W mot_irq_router_cpu0_peri_3_1_irq_masked
4 10 R/W mot_irq_router_cpu0_peri_3_0_irq_mask_set
5 14 R/W mot_irq_router_cpu0_peri_3_1_irq_mask_set
6 18 R/W mot_irq_router_cpu0_peri_3_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu0_peri_3_1_irq_mask_rst

mot_irq_router_cpu0_peri_3_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210120
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210124
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_3_0_irq_raw).
R/W
0x00000000
Address : 0x49210128
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_peri_3_1_irq_raw).
R/W
0x00000000
Address : 0x4921012c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_3_0_irq_raw
R/W
0x00000000
Address : 0x49210130
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_peri_3_1_irq_raw
R/W
0x00000000
Address : 0x49210134
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_3_0_irq-gpio_0
  1  : peri_3_0_irq-gpio_1
  2  : peri_3_0_irq-gpio_2
  3  : peri_3_0_irq-gpio_3
  4  : peri_3_0_irq-gpio_4
  5  : peri_3_0_irq-gpio_5
  6  : peri_3_0_irq-gpio_6
  7  : peri_3_0_irq-gpio_7
  8  : peri_3_0_irq-gpio_8
  9  : peri_3_0_irq-gpio_9
  10 : peri_3_0_irq-gpio_10
  11 : peri_3_0_irq-gpio_11
  12 : peri_3_0_irq-gpio_12
  13 : peri_3_0_irq-gpio_13
  14 : peri_3_0_irq-gpio_14
  15 : peri_3_0_irq-gpio_15
  16 : peri_3_0_irq-timer0_0
  17 : peri_3_0_irq-timer0_1
  18 : peri_3_0_irq-timer0_2
  19 : peri_3_0_irq-timer0_3
  20 : peri_3_0_irq-timer1_0
  21 : peri_3_0_irq-timer1_1
  22 : peri_3_0_irq-timer1_2
  23 : peri_3_0_irq-timer1_3
  24 : peri_3_0_irq-uart_0
  25 : peri_3_0_irq-uart_1
  26 : peri_3_0_irq-i2c_0
  27 : peri_3_0_irq-i2c_1
  28 : peri_3_0_irq-spi_0
  29 : peri_3_0_irq-spi_1
  30 : peri_3_0_irq-sqi_0
  31 : peri_3_0_irq-sqi_1
  32 : peri_3_1_irq-wdg0_0
  33 : peri_3_1_irq-wdg0_1
  34 : peri_3_1_irq-wdg1_0
  35 : peri_3_1_irq-wdg1_1
  36 : peri_3_1_irq-pio_0
  37 : peri_3_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x49210138
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu0_peri_3_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_3_0_irq-gpio_0
  1  : peri_3_0_irq-gpio_1
  2  : peri_3_0_irq-gpio_2
  3  : peri_3_0_irq-gpio_3
  4  : peri_3_0_irq-gpio_4
  5  : peri_3_0_irq-gpio_5
  6  : peri_3_0_irq-gpio_6
  7  : peri_3_0_irq-gpio_7
  8  : peri_3_0_irq-gpio_8
  9  : peri_3_0_irq-gpio_9
  10 : peri_3_0_irq-gpio_10
  11 : peri_3_0_irq-gpio_11
  12 : peri_3_0_irq-gpio_12
  13 : peri_3_0_irq-gpio_13
  14 : peri_3_0_irq-gpio_14
  15 : peri_3_0_irq-gpio_15
  16 : peri_3_0_irq-timer0_0
  17 : peri_3_0_irq-timer0_1
  18 : peri_3_0_irq-timer0_2
  19 : peri_3_0_irq-timer0_3
  20 : peri_3_0_irq-timer1_0
  21 : peri_3_0_irq-timer1_1
  22 : peri_3_0_irq-timer1_2
  23 : peri_3_0_irq-timer1_3
  24 : peri_3_0_irq-uart_0
  25 : peri_3_0_irq-uart_1
  26 : peri_3_0_irq-i2c_0
  27 : peri_3_0_irq-i2c_1
  28 : peri_3_0_irq-spi_0
  29 : peri_3_0_irq-spi_1
  30 : peri_3_0_irq-sqi_0
  31 : peri_3_0_irq-sqi_1
  32 : peri_3_1_irq-wdg0_0
  33 : peri_3_1_irq-wdg0_1
  34 : peri_3_1_irq-wdg1_0
  35 : peri_3_1_irq-wdg1_1
  36 : peri_3_1_irq-pio_0
  37 : peri_3_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x4921013c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]



Base Address Area: mot_irq_router_cpu0_shdint_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu0_shdint_0_irq_raw
1 4 R/W mot_irq_router_cpu0_shdint_0_irq_masked
2 8 R/W mot_irq_router_cpu0_shdint_0_irq_mask_set
3 c R/W mot_irq_router_cpu0_shdint_0_irq_mask_rst

mot_irq_router_cpu0_shdint_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49210140
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu0_shdint_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu0_shdint_0_irq_raw).
R/W
0x00000000
Address : 0x49210144
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu0_shdint_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu0_shdint_0_irq_raw
R/W
0x00000000
Address : 0x49210148
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu0_shdint_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 24 when no IRQ is set:
  0  : shdint_0_irq-shdint_0
  1  : shdint_0_irq-shdint_1
  2  : shdint_0_irq-shdint_2
  3  : shdint_0_irq-shdint_3
  4  : shdint_0_irq-shdint_4
  5  : shdint_0_irq-shdint_5
  6  : shdint_0_irq-shdint_6
  7  : shdint_0_irq-shdint_7
  8  : shdint_0_irq-shdint_8
  9  : shdint_0_irq-shdint_9
  10 : shdint_0_irq-shdint_10
  11 : shdint_0_irq-shdint_11
  12 : shdint_0_irq-shdint_12
  13 : shdint_0_irq-shdint_13
  14 : shdint_0_irq-shdint_14
  15 : shdint_0_irq-shdint_15
  16 : shdint_0_irq-shdint_16
  17 : shdint_0_irq-shdint_17
  18 : shdint_0_irq-shdint_18
  19 : shdint_0_irq-shdint_19
  20 : shdint_0_irq-shdint_20
  21 : shdint_0_irq-shdint_21
  22 : shdint_0_irq-shdint_22
  23 : shdint_0_irq-shdint_23
  24 : no active IRQ
R/W
0x00000000
Address : 0x4921014c
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]



Base Address Area: mot_irq_router_cpu1_motion_exp_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_motion_exp_0_irq_raw
1 4 R/W mot_irq_router_cpu1_motion_exp_0_irq_masked
2 8 R/W mot_irq_router_cpu1_motion_exp_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_motion_exp_0_irq_mask_rst

mot_irq_router_cpu1_motion_exp_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211000
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu1_motion_exp_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_motion_exp_0_irq_raw).
R/W
0x00000000
Address : 0x49211004
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu1_motion_exp_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_motion_exp_0_irq_raw
R/W
0x00000000
Address : 0x49211008
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]


mot_irq_router_cpu1_motion_exp_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 22 when no IRQ is set:
  0  : motion_exp_0_irq-madc_seq_0
  1  : motion_exp_0_irq-madc_seq_1
  2  : motion_exp_0_irq-madc_seq_2
  3  : motion_exp_0_irq-madc_seq_3
  4  : motion_exp_0_irq-sdfm_0
  5  : motion_exp_0_irq-sdfm_1
  6  : motion_exp_0_irq-sdfm_2
  7  : motion_exp_0_irq-menc_enc_0
  8  : motion_exp_0_irq-menc_enc_1
  9  : motion_exp_0_irq-biss_0
  10 : motion_exp_0_irq-biss_1
  11 : motion_exp_0_irq-endat_0
  12 : motion_exp_0_irq-endat_1
  13 : motion_exp_0_irq-trigger_irq_0
  14 : motion_exp_0_irq-trigger_irq_1
  15 : motion_exp_0_irq-trigger_irq_global_0
  16 : motion_exp_0_irq-trigger_irq_global_1
  17 : motion_exp_0_irq-mpwm_0
  18 : motion_exp_0_irq-menc_cap_mp_0
  19 : motion_exp_0_irq-menc_err_0
  20 : motion_exp_0_irq-sync_timer_0
  21 : motion_exp_0_irq-sync_timer_global_0
  22 : no active IRQ
R/W
0x00000000
Address : 0x4921100c
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ motion_exp[0]
20 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ motion_exp[0]
19 "0"
menc_err_0
Event - menc_err[0] contribution to IRQ motion_exp[0]
18 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ motion_exp[0]
17 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ motion_exp[0]
16 "0"
trigger_irq_global_1
Event - trigger_irq_global[1] contribution to IRQ motion_exp[0]
15 "0"
trigger_irq_global_0
Event - trigger_irq_global[0] contribution to IRQ motion_exp[0]
14 "0"
trigger_irq_1
Event - trigger_irq[1] contribution to IRQ motion_exp[0]
13 "0"
trigger_irq_0
Event - trigger_irq[0] contribution to IRQ motion_exp[0]
12 "0"
endat_1
Event - endat[1] contribution to IRQ motion_exp[0]
11 "0"
endat_0
Event - endat[0] contribution to IRQ motion_exp[0]
10 "0"
biss_1
Event - biss[1] contribution to IRQ motion_exp[0]
9 "0"
biss_0
Event - biss[0] contribution to IRQ motion_exp[0]
8 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ motion_exp[0]
7 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ motion_exp[0]
6 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ motion_exp[0]
5 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ motion_exp[0]
4 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ motion_exp[0]
3 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ motion_exp[0]
2 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ motion_exp[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ motion_exp[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ motion_exp[0]



Base Address Area: mot_irq_router_cpu1_sync_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_sync_0_irq_raw
1 4 R/W mot_irq_router_cpu1_sync_0_irq_masked
2 8 R/W mot_irq_router_cpu1_sync_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_sync_0_irq_mask_rst

mot_irq_router_cpu1_sync_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211010
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu1_sync_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_sync_0_irq_raw).
R/W
0x00000000
Address : 0x49211014
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu1_sync_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_sync_0_irq_raw
R/W
0x00000000
Address : 0x49211018
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]


mot_irq_router_cpu1_sync_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 2 when no IRQ is set:
  0 : sync_0_irq-sync_timer_0
  1 : sync_0_irq-sync_timer_global_0
  2 : no active IRQ
R/W
0x00000000
Address : 0x4921101c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
sync_timer_global_0
Event - sync_timer_global[0] contribution to IRQ sync[0]
0 "0"
sync_timer_0
Event - sync_timer[0] contribution to IRQ sync[0]



Base Address Area: mot_irq_router_cpu1_mpwm_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_mpwm_0_irq_raw
1 4 R/W mot_irq_router_cpu1_mpwm_0_irq_masked
2 8 R/W mot_irq_router_cpu1_mpwm_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_mpwm_0_irq_mask_rst

mot_irq_router_cpu1_mpwm_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211020
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu1_mpwm_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_mpwm_0_irq_raw).
R/W
0x00000000
Address : 0x49211024
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu1_mpwm_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_mpwm_0_irq_raw
R/W
0x00000000
Address : 0x49211028
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]


mot_irq_router_cpu1_mpwm_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 1 when no IRQ is set:
  0 : mpwm_0_irq-mpwm_0
  1 : no active IRQ
R/W
0x00000000
Address : 0x4921102c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
mpwm_0
Event - mpwm[0] contribution to IRQ mpwm[0]



Base Address Area: mot_irq_router_cpu1_adc_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_adc_0_irq_raw
1 4 R/W mot_irq_router_cpu1_adc_0_irq_masked
2 8 R/W mot_irq_router_cpu1_adc_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_adc_0_irq_mask_rst

mot_irq_router_cpu1_adc_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211030
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu1_adc_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_adc_0_irq_raw).
R/W
0x00000000
Address : 0x49211034
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu1_adc_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_adc_0_irq_raw
R/W
0x00000000
Address : 0x49211038
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]


mot_irq_router_cpu1_adc_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : adc_0_irq-madc_seq_0
  1 : adc_0_irq-madc_seq_1
  2 : adc_0_irq-sdfm_0
  3 : adc_0_irq-sdfm_1
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921103c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
sdfm_1
Event - sdfm[1] contribution to IRQ adc[0]
2 "0"
sdfm_0
Event - sdfm[0] contribution to IRQ adc[0]
1 "0"
madc_seq_1
Event - madc_seq[1] contribution to IRQ adc[0]
0 "0"
madc_seq_0
Event - madc_seq[0] contribution to IRQ adc[0]



Base Address Area: mot_irq_router_cpu1_adc_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_adc_1_irq_raw
1 4 R/W mot_irq_router_cpu1_adc_1_irq_masked
2 8 R/W mot_irq_router_cpu1_adc_1_irq_mask_set
3 c R/W mot_irq_router_cpu1_adc_1_irq_mask_rst

mot_irq_router_cpu1_adc_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211040
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu1_adc_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_adc_1_irq_raw).
R/W
0x00000000
Address : 0x49211044
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu1_adc_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_adc_1_irq_raw
R/W
0x00000000
Address : 0x49211048
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]


mot_irq_router_cpu1_adc_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 3 when no IRQ is set:
  0 : adc_1_irq-madc_seq_2
  1 : adc_1_irq-madc_seq_3
  2 : adc_1_irq-sdfm_2
  3 : no active IRQ
R/W
0x00000000
Address : 0x4921104c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
sdfm_2
Event - sdfm[2] contribution to IRQ adc[1]
1 "0"
madc_seq_3
Event - madc_seq[3] contribution to IRQ adc[1]
0 "0"
madc_seq_2
Event - madc_seq[2] contribution to IRQ adc[1]



Base Address Area: mot_irq_router_cpu1_enc_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_enc_0_irq_raw
1 4 R/W mot_irq_router_cpu1_enc_0_irq_masked
2 8 R/W mot_irq_router_cpu1_enc_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_enc_0_irq_mask_rst

mot_irq_router_cpu1_enc_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211050
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu1_enc_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_enc_0_irq_raw).
R/W
0x00000000
Address : 0x49211054
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu1_enc_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_enc_0_irq_raw
R/W
0x00000000
Address : 0x49211058
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]


mot_irq_router_cpu1_enc_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : enc_0_irq-menc_enc_0
  1 : enc_0_irq-menc_cap_mp_0
  2 : enc_0_irq-biss_0
  3 : enc_0_irq-endat_0
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921105c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_0
Event - endat[0] contribution to IRQ enc[0]
2 "0"
biss_0
Event - biss[0] contribution to IRQ enc[0]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[0]
0 "0"
menc_enc_0
Event - menc_enc[0] contribution to IRQ enc[0]



Base Address Area: mot_irq_router_cpu1_enc_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_enc_1_irq_raw
1 4 R/W mot_irq_router_cpu1_enc_1_irq_masked
2 8 R/W mot_irq_router_cpu1_enc_1_irq_mask_set
3 c R/W mot_irq_router_cpu1_enc_1_irq_mask_rst

mot_irq_router_cpu1_enc_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211060
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu1_enc_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_enc_1_irq_raw).
R/W
0x00000000
Address : 0x49211064
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu1_enc_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_enc_1_irq_raw
R/W
0x00000000
Address : 0x49211068
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]


mot_irq_router_cpu1_enc_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 4 when no IRQ is set:
  0 : enc_1_irq-menc_enc_1
  1 : enc_1_irq-menc_cap_mp_0
  2 : enc_1_irq-biss_1
  3 : enc_1_irq-endat_1
  4 : no active IRQ
R/W
0x00000000
Address : 0x4921106c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
endat_1
Event - endat[1] contribution to IRQ enc[1]
2 "0"
biss_1
Event - biss[1] contribution to IRQ enc[1]
1 "0"
menc_cap_mp_0
Event - menc_cap_mp[0] contribution to IRQ enc[1]
0 "0"
menc_enc_1
Event - menc_enc[1] contribution to IRQ enc[1]



Base Address Area: mot_irq_router_cpu1_com_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_com_0_irq_raw
1 4 R/W mot_irq_router_cpu1_com_0_irq_masked
2 8 R/W mot_irq_router_cpu1_com_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_com_0_irq_mask_rst

mot_irq_router_cpu1_com_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211070
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu1_com_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_com_0_irq_raw).
R/W
0x00000000
Address : 0x49211074
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu1_com_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_com_0_irq_raw
R/W
0x00000000
Address : 0x49211078
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]


mot_irq_router_cpu1_com_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_0_irq-mhu_0
  1  : com_0_irq-mhu_1
  2  : com_0_irq-mhu_2
  3  : com_0_irq-mhu_3
  4  : com_0_irq-mhu_4
  5  : com_0_irq-mhu_5
  6  : com_0_irq-mhu_6
  7  : com_0_irq-mhu_7
  8  : com_0_irq-sms_0
  9  : com_0_irq-sms_1
  10 : com_0_irq-sms_2
  11 : com_0_irq-sms_3
  12 : com_0_irq-hsc_0
  13 : com_0_irq-hsc_1
  14 : com_0_irq-hsc_2
  15 : com_0_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921107c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[0]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[0]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[0]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[0]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[0]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[0]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[0]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[0]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[0]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[0]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[0]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[0]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[0]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[0]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[0]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[0]



Base Address Area: mot_irq_router_cpu1_com_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_com_1_irq_raw
1 4 R/W mot_irq_router_cpu1_com_1_irq_masked
2 8 R/W mot_irq_router_cpu1_com_1_irq_mask_set
3 c R/W mot_irq_router_cpu1_com_1_irq_mask_rst

mot_irq_router_cpu1_com_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211080
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu1_com_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_com_1_irq_raw).
R/W
0x00000000
Address : 0x49211084
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu1_com_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_com_1_irq_raw
R/W
0x00000000
Address : 0x49211088
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]


mot_irq_router_cpu1_com_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_1_irq-mhu_0
  1  : com_1_irq-mhu_1
  2  : com_1_irq-mhu_2
  3  : com_1_irq-mhu_3
  4  : com_1_irq-mhu_4
  5  : com_1_irq-mhu_5
  6  : com_1_irq-mhu_6
  7  : com_1_irq-mhu_7
  8  : com_1_irq-sms_0
  9  : com_1_irq-sms_1
  10 : com_1_irq-sms_2
  11 : com_1_irq-sms_3
  12 : com_1_irq-hsc_0
  13 : com_1_irq-hsc_1
  14 : com_1_irq-hsc_2
  15 : com_1_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921108c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[1]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[1]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[1]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[1]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[1]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[1]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[1]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[1]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[1]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[1]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[1]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[1]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[1]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[1]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[1]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[1]



Base Address Area: mot_irq_router_cpu1_com_2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_com_2_irq_raw
1 4 R/W mot_irq_router_cpu1_com_2_irq_masked
2 8 R/W mot_irq_router_cpu1_com_2_irq_mask_set
3 c R/W mot_irq_router_cpu1_com_2_irq_mask_rst

mot_irq_router_cpu1_com_2_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211090
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu1_com_2_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_com_2_irq_raw).
R/W
0x00000000
Address : 0x49211094
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu1_com_2_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_com_2_irq_raw
R/W
0x00000000
Address : 0x49211098
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]


mot_irq_router_cpu1_com_2_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_2_irq-mhu_0
  1  : com_2_irq-mhu_1
  2  : com_2_irq-mhu_2
  3  : com_2_irq-mhu_3
  4  : com_2_irq-mhu_4
  5  : com_2_irq-mhu_5
  6  : com_2_irq-mhu_6
  7  : com_2_irq-mhu_7
  8  : com_2_irq-sms_0
  9  : com_2_irq-sms_1
  10 : com_2_irq-sms_2
  11 : com_2_irq-sms_3
  12 : com_2_irq-hsc_0
  13 : com_2_irq-hsc_1
  14 : com_2_irq-hsc_2
  15 : com_2_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x4921109c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[2]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[2]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[2]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[2]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[2]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[2]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[2]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[2]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[2]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[2]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[2]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[2]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[2]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[2]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[2]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[2]



Base Address Area: mot_irq_router_cpu1_com_3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_com_3_irq_raw
1 4 R/W mot_irq_router_cpu1_com_3_irq_masked
2 8 R/W mot_irq_router_cpu1_com_3_irq_mask_set
3 c R/W mot_irq_router_cpu1_com_3_irq_mask_rst

mot_irq_router_cpu1_com_3_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492110a0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu1_com_3_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_com_3_irq_raw).
R/W
0x00000000
Address : 0x492110a4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu1_com_3_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_com_3_irq_raw
R/W
0x00000000
Address : 0x492110a8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]


mot_irq_router_cpu1_com_3_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 16 when no IRQ is set:
  0  : com_3_irq-mhu_0
  1  : com_3_irq-mhu_1
  2  : com_3_irq-mhu_2
  3  : com_3_irq-mhu_3
  4  : com_3_irq-mhu_4
  5  : com_3_irq-mhu_5
  6  : com_3_irq-mhu_6
  7  : com_3_irq-mhu_7
  8  : com_3_irq-sms_0
  9  : com_3_irq-sms_1
  10 : com_3_irq-sms_2
  11 : com_3_irq-sms_3
  12 : com_3_irq-hsc_0
  13 : com_3_irq-hsc_1
  14 : com_3_irq-hsc_2
  15 : com_3_irq-hsc_3
  16 : no active IRQ
R/W
0x00000000
Address : 0x492110ac
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hsc_3
Event - hsc[3] contribution to IRQ com[3]
14 "0"
hsc_2
Event - hsc[2] contribution to IRQ com[3]
13 "0"
hsc_1
Event - hsc[1] contribution to IRQ com[3]
12 "0"
hsc_0
Event - hsc[0] contribution to IRQ com[3]
11 "0"
sms_3
Event - sms[3] contribution to IRQ com[3]
10 "0"
sms_2
Event - sms[2] contribution to IRQ com[3]
9 "0"
sms_1
Event - sms[1] contribution to IRQ com[3]
8 "0"
sms_0
Event - sms[0] contribution to IRQ com[3]
7 "0"
mhu_7
Event - mhu[7] contribution to IRQ com[3]
6 "0"
mhu_6
Event - mhu[6] contribution to IRQ com[3]
5 "0"
mhu_5
Event - mhu[5] contribution to IRQ com[3]
4 "0"
mhu_4
Event - mhu[4] contribution to IRQ com[3]
3 "0"
mhu_3
Event - mhu[3] contribution to IRQ com[3]
2 "0"
mhu_2
Event - mhu[2] contribution to IRQ com[3]
1 "0"
mhu_1
Event - mhu[1] contribution to IRQ com[3]
0 "0"
mhu_0
Event - mhu[0] contribution to IRQ com[3]



Base Address Area: mot_irq_router_cpu1_peri_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_peri_0_0_irq_raw
1 4 R/W mot_irq_router_cpu1_peri_0_1_irq_raw
2 8 R/W mot_irq_router_cpu1_peri_0_0_irq_masked
3 c R/W mot_irq_router_cpu1_peri_0_1_irq_masked
4 10 R/W mot_irq_router_cpu1_peri_0_0_irq_mask_set
5 14 R/W mot_irq_router_cpu1_peri_0_1_irq_mask_set
6 18 R/W mot_irq_router_cpu1_peri_0_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu1_peri_0_1_irq_mask_rst

mot_irq_router_cpu1_peri_0_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492110c0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492110c4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_0_0_irq_raw).
R/W
0x00000000
Address : 0x492110c8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_0_1_irq_raw).
R/W
0x00000000
Address : 0x492110cc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_0_0_irq_raw
R/W
0x00000000
Address : 0x492110d0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_0_1_irq_raw
R/W
0x00000000
Address : 0x492110d4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_0_0_irq-gpio_0
  1  : peri_0_0_irq-gpio_1
  2  : peri_0_0_irq-gpio_2
  3  : peri_0_0_irq-gpio_3
  4  : peri_0_0_irq-gpio_4
  5  : peri_0_0_irq-gpio_5
  6  : peri_0_0_irq-gpio_6
  7  : peri_0_0_irq-gpio_7
  8  : peri_0_0_irq-gpio_8
  9  : peri_0_0_irq-gpio_9
  10 : peri_0_0_irq-gpio_10
  11 : peri_0_0_irq-gpio_11
  12 : peri_0_0_irq-gpio_12
  13 : peri_0_0_irq-gpio_13
  14 : peri_0_0_irq-gpio_14
  15 : peri_0_0_irq-gpio_15
  16 : peri_0_0_irq-timer0_0
  17 : peri_0_0_irq-timer0_1
  18 : peri_0_0_irq-timer0_2
  19 : peri_0_0_irq-timer0_3
  20 : peri_0_0_irq-timer1_0
  21 : peri_0_0_irq-timer1_1
  22 : peri_0_0_irq-timer1_2
  23 : peri_0_0_irq-timer1_3
  24 : peri_0_0_irq-uart_0
  25 : peri_0_0_irq-uart_1
  26 : peri_0_0_irq-i2c_0
  27 : peri_0_0_irq-i2c_1
  28 : peri_0_0_irq-spi_0
  29 : peri_0_0_irq-spi_1
  30 : peri_0_0_irq-sqi_0
  31 : peri_0_0_irq-sqi_1
  32 : peri_0_1_irq-wdg0_0
  33 : peri_0_1_irq-wdg0_1
  34 : peri_0_1_irq-wdg1_0
  35 : peri_0_1_irq-wdg1_1
  36 : peri_0_1_irq-pio_0
  37 : peri_0_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492110d8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[0]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[0]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[0]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[0]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[0]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[0]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[0]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[0]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[0]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[0]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[0]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[0]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[0]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[0]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[0]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[0]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[0]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[0]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[0]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[0]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[0]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[0]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[0]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[0]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[0]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[0]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[0]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[0]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[0]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[0]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[0]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[0]


mot_irq_router_cpu1_peri_0_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_0_0_irq-gpio_0
  1  : peri_0_0_irq-gpio_1
  2  : peri_0_0_irq-gpio_2
  3  : peri_0_0_irq-gpio_3
  4  : peri_0_0_irq-gpio_4
  5  : peri_0_0_irq-gpio_5
  6  : peri_0_0_irq-gpio_6
  7  : peri_0_0_irq-gpio_7
  8  : peri_0_0_irq-gpio_8
  9  : peri_0_0_irq-gpio_9
  10 : peri_0_0_irq-gpio_10
  11 : peri_0_0_irq-gpio_11
  12 : peri_0_0_irq-gpio_12
  13 : peri_0_0_irq-gpio_13
  14 : peri_0_0_irq-gpio_14
  15 : peri_0_0_irq-gpio_15
  16 : peri_0_0_irq-timer0_0
  17 : peri_0_0_irq-timer0_1
  18 : peri_0_0_irq-timer0_2
  19 : peri_0_0_irq-timer0_3
  20 : peri_0_0_irq-timer1_0
  21 : peri_0_0_irq-timer1_1
  22 : peri_0_0_irq-timer1_2
  23 : peri_0_0_irq-timer1_3
  24 : peri_0_0_irq-uart_0
  25 : peri_0_0_irq-uart_1
  26 : peri_0_0_irq-i2c_0
  27 : peri_0_0_irq-i2c_1
  28 : peri_0_0_irq-spi_0
  29 : peri_0_0_irq-spi_1
  30 : peri_0_0_irq-sqi_0
  31 : peri_0_0_irq-sqi_1
  32 : peri_0_1_irq-wdg0_0
  33 : peri_0_1_irq-wdg0_1
  34 : peri_0_1_irq-wdg1_0
  35 : peri_0_1_irq-wdg1_1
  36 : peri_0_1_irq-pio_0
  37 : peri_0_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492110dc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[0]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[0]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[0]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[0]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[0]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[0]



Base Address Area: mot_irq_router_cpu1_peri_1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_peri_1_0_irq_raw
1 4 R/W mot_irq_router_cpu1_peri_1_1_irq_raw
2 8 R/W mot_irq_router_cpu1_peri_1_0_irq_masked
3 c R/W mot_irq_router_cpu1_peri_1_1_irq_masked
4 10 R/W mot_irq_router_cpu1_peri_1_0_irq_mask_set
5 14 R/W mot_irq_router_cpu1_peri_1_1_irq_mask_set
6 18 R/W mot_irq_router_cpu1_peri_1_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu1_peri_1_1_irq_mask_rst

mot_irq_router_cpu1_peri_1_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492110e0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x492110e4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_1_0_irq_raw).
R/W
0x00000000
Address : 0x492110e8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_1_1_irq_raw).
R/W
0x00000000
Address : 0x492110ec
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_1_0_irq_raw
R/W
0x00000000
Address : 0x492110f0
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_1_1_irq_raw
R/W
0x00000000
Address : 0x492110f4
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_1_0_irq-gpio_0
  1  : peri_1_0_irq-gpio_1
  2  : peri_1_0_irq-gpio_2
  3  : peri_1_0_irq-gpio_3
  4  : peri_1_0_irq-gpio_4
  5  : peri_1_0_irq-gpio_5
  6  : peri_1_0_irq-gpio_6
  7  : peri_1_0_irq-gpio_7
  8  : peri_1_0_irq-gpio_8
  9  : peri_1_0_irq-gpio_9
  10 : peri_1_0_irq-gpio_10
  11 : peri_1_0_irq-gpio_11
  12 : peri_1_0_irq-gpio_12
  13 : peri_1_0_irq-gpio_13
  14 : peri_1_0_irq-gpio_14
  15 : peri_1_0_irq-gpio_15
  16 : peri_1_0_irq-timer0_0
  17 : peri_1_0_irq-timer0_1
  18 : peri_1_0_irq-timer0_2
  19 : peri_1_0_irq-timer0_3
  20 : peri_1_0_irq-timer1_0
  21 : peri_1_0_irq-timer1_1
  22 : peri_1_0_irq-timer1_2
  23 : peri_1_0_irq-timer1_3
  24 : peri_1_0_irq-uart_0
  25 : peri_1_0_irq-uart_1
  26 : peri_1_0_irq-i2c_0
  27 : peri_1_0_irq-i2c_1
  28 : peri_1_0_irq-spi_0
  29 : peri_1_0_irq-spi_1
  30 : peri_1_0_irq-sqi_0
  31 : peri_1_0_irq-sqi_1
  32 : peri_1_1_irq-wdg0_0
  33 : peri_1_1_irq-wdg0_1
  34 : peri_1_1_irq-wdg1_0
  35 : peri_1_1_irq-wdg1_1
  36 : peri_1_1_irq-pio_0
  37 : peri_1_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492110f8
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[1]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[1]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[1]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[1]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[1]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[1]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[1]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[1]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[1]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[1]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[1]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[1]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[1]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[1]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[1]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[1]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[1]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[1]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[1]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[1]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[1]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[1]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[1]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[1]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[1]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[1]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[1]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[1]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[1]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[1]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[1]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[1]


mot_irq_router_cpu1_peri_1_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_1_0_irq-gpio_0
  1  : peri_1_0_irq-gpio_1
  2  : peri_1_0_irq-gpio_2
  3  : peri_1_0_irq-gpio_3
  4  : peri_1_0_irq-gpio_4
  5  : peri_1_0_irq-gpio_5
  6  : peri_1_0_irq-gpio_6
  7  : peri_1_0_irq-gpio_7
  8  : peri_1_0_irq-gpio_8
  9  : peri_1_0_irq-gpio_9
  10 : peri_1_0_irq-gpio_10
  11 : peri_1_0_irq-gpio_11
  12 : peri_1_0_irq-gpio_12
  13 : peri_1_0_irq-gpio_13
  14 : peri_1_0_irq-gpio_14
  15 : peri_1_0_irq-gpio_15
  16 : peri_1_0_irq-timer0_0
  17 : peri_1_0_irq-timer0_1
  18 : peri_1_0_irq-timer0_2
  19 : peri_1_0_irq-timer0_3
  20 : peri_1_0_irq-timer1_0
  21 : peri_1_0_irq-timer1_1
  22 : peri_1_0_irq-timer1_2
  23 : peri_1_0_irq-timer1_3
  24 : peri_1_0_irq-uart_0
  25 : peri_1_0_irq-uart_1
  26 : peri_1_0_irq-i2c_0
  27 : peri_1_0_irq-i2c_1
  28 : peri_1_0_irq-spi_0
  29 : peri_1_0_irq-spi_1
  30 : peri_1_0_irq-sqi_0
  31 : peri_1_0_irq-sqi_1
  32 : peri_1_1_irq-wdg0_0
  33 : peri_1_1_irq-wdg0_1
  34 : peri_1_1_irq-wdg1_0
  35 : peri_1_1_irq-wdg1_1
  36 : peri_1_1_irq-pio_0
  37 : peri_1_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x492110fc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[1]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[1]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[1]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[1]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[1]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[1]



Base Address Area: mot_irq_router_cpu1_peri_2

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_peri_2_0_irq_raw
1 4 R/W mot_irq_router_cpu1_peri_2_1_irq_raw
2 8 R/W mot_irq_router_cpu1_peri_2_0_irq_masked
3 c R/W mot_irq_router_cpu1_peri_2_1_irq_masked
4 10 R/W mot_irq_router_cpu1_peri_2_0_irq_mask_set
5 14 R/W mot_irq_router_cpu1_peri_2_1_irq_mask_set
6 18 R/W mot_irq_router_cpu1_peri_2_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu1_peri_2_1_irq_mask_rst

mot_irq_router_cpu1_peri_2_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211100
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211104
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_2_0_irq_raw).
R/W
0x00000000
Address : 0x49211108
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_2_1_irq_raw).
R/W
0x00000000
Address : 0x4921110c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_2_0_irq_raw
R/W
0x00000000
Address : 0x49211110
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_2_1_irq_raw
R/W
0x00000000
Address : 0x49211114
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_2_0_irq-gpio_0
  1  : peri_2_0_irq-gpio_1
  2  : peri_2_0_irq-gpio_2
  3  : peri_2_0_irq-gpio_3
  4  : peri_2_0_irq-gpio_4
  5  : peri_2_0_irq-gpio_5
  6  : peri_2_0_irq-gpio_6
  7  : peri_2_0_irq-gpio_7
  8  : peri_2_0_irq-gpio_8
  9  : peri_2_0_irq-gpio_9
  10 : peri_2_0_irq-gpio_10
  11 : peri_2_0_irq-gpio_11
  12 : peri_2_0_irq-gpio_12
  13 : peri_2_0_irq-gpio_13
  14 : peri_2_0_irq-gpio_14
  15 : peri_2_0_irq-gpio_15
  16 : peri_2_0_irq-timer0_0
  17 : peri_2_0_irq-timer0_1
  18 : peri_2_0_irq-timer0_2
  19 : peri_2_0_irq-timer0_3
  20 : peri_2_0_irq-timer1_0
  21 : peri_2_0_irq-timer1_1
  22 : peri_2_0_irq-timer1_2
  23 : peri_2_0_irq-timer1_3
  24 : peri_2_0_irq-uart_0
  25 : peri_2_0_irq-uart_1
  26 : peri_2_0_irq-i2c_0
  27 : peri_2_0_irq-i2c_1
  28 : peri_2_0_irq-spi_0
  29 : peri_2_0_irq-spi_1
  30 : peri_2_0_irq-sqi_0
  31 : peri_2_0_irq-sqi_1
  32 : peri_2_1_irq-wdg0_0
  33 : peri_2_1_irq-wdg0_1
  34 : peri_2_1_irq-wdg1_0
  35 : peri_2_1_irq-wdg1_1
  36 : peri_2_1_irq-pio_0
  37 : peri_2_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x49211118
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[2]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[2]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[2]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[2]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[2]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[2]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[2]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[2]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[2]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[2]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[2]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[2]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[2]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[2]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[2]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[2]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[2]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[2]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[2]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[2]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[2]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[2]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[2]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[2]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[2]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[2]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[2]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[2]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[2]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[2]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[2]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[2]


mot_irq_router_cpu1_peri_2_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_2_0_irq-gpio_0
  1  : peri_2_0_irq-gpio_1
  2  : peri_2_0_irq-gpio_2
  3  : peri_2_0_irq-gpio_3
  4  : peri_2_0_irq-gpio_4
  5  : peri_2_0_irq-gpio_5
  6  : peri_2_0_irq-gpio_6
  7  : peri_2_0_irq-gpio_7
  8  : peri_2_0_irq-gpio_8
  9  : peri_2_0_irq-gpio_9
  10 : peri_2_0_irq-gpio_10
  11 : peri_2_0_irq-gpio_11
  12 : peri_2_0_irq-gpio_12
  13 : peri_2_0_irq-gpio_13
  14 : peri_2_0_irq-gpio_14
  15 : peri_2_0_irq-gpio_15
  16 : peri_2_0_irq-timer0_0
  17 : peri_2_0_irq-timer0_1
  18 : peri_2_0_irq-timer0_2
  19 : peri_2_0_irq-timer0_3
  20 : peri_2_0_irq-timer1_0
  21 : peri_2_0_irq-timer1_1
  22 : peri_2_0_irq-timer1_2
  23 : peri_2_0_irq-timer1_3
  24 : peri_2_0_irq-uart_0
  25 : peri_2_0_irq-uart_1
  26 : peri_2_0_irq-i2c_0
  27 : peri_2_0_irq-i2c_1
  28 : peri_2_0_irq-spi_0
  29 : peri_2_0_irq-spi_1
  30 : peri_2_0_irq-sqi_0
  31 : peri_2_0_irq-sqi_1
  32 : peri_2_1_irq-wdg0_0
  33 : peri_2_1_irq-wdg0_1
  34 : peri_2_1_irq-wdg1_0
  35 : peri_2_1_irq-wdg1_1
  36 : peri_2_1_irq-pio_0
  37 : peri_2_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x4921111c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[2]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[2]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[2]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[2]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[2]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[2]



Base Address Area: mot_irq_router_cpu1_peri_3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_peri_3_0_irq_raw
1 4 R/W mot_irq_router_cpu1_peri_3_1_irq_raw
2 8 R/W mot_irq_router_cpu1_peri_3_0_irq_masked
3 c R/W mot_irq_router_cpu1_peri_3_1_irq_masked
4 10 R/W mot_irq_router_cpu1_peri_3_0_irq_mask_set
5 14 R/W mot_irq_router_cpu1_peri_3_1_irq_mask_set
6 18 R/W mot_irq_router_cpu1_peri_3_0_irq_mask_rst
7 1c R/W mot_irq_router_cpu1_peri_3_1_irq_mask_rst

mot_irq_router_cpu1_peri_3_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211120
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_1_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211124
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_3_0_irq_raw).
R/W
0x00000000
Address : 0x49211128
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_1_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_peri_3_1_irq_raw).
R/W
0x00000000
Address : 0x4921112c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_3_0_irq_raw
R/W
0x00000000
Address : 0x49211130
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_1_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_peri_3_1_irq_raw
R/W
0x00000000
Address : 0x49211134
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_3_0_irq-gpio_0
  1  : peri_3_0_irq-gpio_1
  2  : peri_3_0_irq-gpio_2
  3  : peri_3_0_irq-gpio_3
  4  : peri_3_0_irq-gpio_4
  5  : peri_3_0_irq-gpio_5
  6  : peri_3_0_irq-gpio_6
  7  : peri_3_0_irq-gpio_7
  8  : peri_3_0_irq-gpio_8
  9  : peri_3_0_irq-gpio_9
  10 : peri_3_0_irq-gpio_10
  11 : peri_3_0_irq-gpio_11
  12 : peri_3_0_irq-gpio_12
  13 : peri_3_0_irq-gpio_13
  14 : peri_3_0_irq-gpio_14
  15 : peri_3_0_irq-gpio_15
  16 : peri_3_0_irq-timer0_0
  17 : peri_3_0_irq-timer0_1
  18 : peri_3_0_irq-timer0_2
  19 : peri_3_0_irq-timer0_3
  20 : peri_3_0_irq-timer1_0
  21 : peri_3_0_irq-timer1_1
  22 : peri_3_0_irq-timer1_2
  23 : peri_3_0_irq-timer1_3
  24 : peri_3_0_irq-uart_0
  25 : peri_3_0_irq-uart_1
  26 : peri_3_0_irq-i2c_0
  27 : peri_3_0_irq-i2c_1
  28 : peri_3_0_irq-spi_0
  29 : peri_3_0_irq-spi_1
  30 : peri_3_0_irq-sqi_0
  31 : peri_3_0_irq-sqi_1
  32 : peri_3_1_irq-wdg0_0
  33 : peri_3_1_irq-wdg0_1
  34 : peri_3_1_irq-wdg1_0
  35 : peri_3_1_irq-wdg1_1
  36 : peri_3_1_irq-pio_0
  37 : peri_3_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x49211138
Bits Reset value Name Description
31 "0"
sqi_1
Event - sqi[1] contribution to IRQ peri[3]
30 "0"
sqi_0
Event - sqi[0] contribution to IRQ peri[3]
29 "0"
spi_1
Event - spi[1] contribution to IRQ peri[3]
28 "0"
spi_0
Event - spi[0] contribution to IRQ peri[3]
27 "0"
i2c_1
Event - i2c[1] contribution to IRQ peri[3]
26 "0"
i2c_0
Event - i2c[0] contribution to IRQ peri[3]
25 "0"
uart_1
Event - uart[1] contribution to IRQ peri[3]
24 "0"
uart_0
Event - uart[0] contribution to IRQ peri[3]
23 "0"
timer1_3
Event - timer1[3] contribution to IRQ peri[3]
22 "0"
timer1_2
Event - timer1[2] contribution to IRQ peri[3]
21 "0"
timer1_1
Event - timer1[1] contribution to IRQ peri[3]
20 "0"
timer1_0
Event - timer1[0] contribution to IRQ peri[3]
19 "0"
timer0_3
Event - timer0[3] contribution to IRQ peri[3]
18 "0"
timer0_2
Event - timer0[2] contribution to IRQ peri[3]
17 "0"
timer0_1
Event - timer0[1] contribution to IRQ peri[3]
16 "0"
timer0_0
Event - timer0[0] contribution to IRQ peri[3]
15 "0"
gpio_15
Event - gpio[15] contribution to IRQ peri[3]
14 "0"
gpio_14
Event - gpio[14] contribution to IRQ peri[3]
13 "0"
gpio_13
Event - gpio[13] contribution to IRQ peri[3]
12 "0"
gpio_12
Event - gpio[12] contribution to IRQ peri[3]
11 "0"
gpio_11
Event - gpio[11] contribution to IRQ peri[3]
10 "0"
gpio_10
Event - gpio[10] contribution to IRQ peri[3]
9 "0"
gpio_9
Event - gpio[9] contribution to IRQ peri[3]
8 "0"
gpio_8
Event - gpio[8] contribution to IRQ peri[3]
7 "0"
gpio_7
Event - gpio[7] contribution to IRQ peri[3]
6 "0"
gpio_6
Event - gpio[6] contribution to IRQ peri[3]
5 "0"
gpio_5
Event - gpio[5] contribution to IRQ peri[3]
4 "0"
gpio_4
Event - gpio[4] contribution to IRQ peri[3]
3 "0"
gpio_3
Event - gpio[3] contribution to IRQ peri[3]
2 "0"
gpio_2
Event - gpio[2] contribution to IRQ peri[3]
1 "0"
gpio_1
Event - gpio[1] contribution to IRQ peri[3]
0 "0"
gpio_0
Event - gpio[0] contribution to IRQ peri[3]


mot_irq_router_cpu1_peri_3_1_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 38 when no IRQ is set:
  0  : peri_3_0_irq-gpio_0
  1  : peri_3_0_irq-gpio_1
  2  : peri_3_0_irq-gpio_2
  3  : peri_3_0_irq-gpio_3
  4  : peri_3_0_irq-gpio_4
  5  : peri_3_0_irq-gpio_5
  6  : peri_3_0_irq-gpio_6
  7  : peri_3_0_irq-gpio_7
  8  : peri_3_0_irq-gpio_8
  9  : peri_3_0_irq-gpio_9
  10 : peri_3_0_irq-gpio_10
  11 : peri_3_0_irq-gpio_11
  12 : peri_3_0_irq-gpio_12
  13 : peri_3_0_irq-gpio_13
  14 : peri_3_0_irq-gpio_14
  15 : peri_3_0_irq-gpio_15
  16 : peri_3_0_irq-timer0_0
  17 : peri_3_0_irq-timer0_1
  18 : peri_3_0_irq-timer0_2
  19 : peri_3_0_irq-timer0_3
  20 : peri_3_0_irq-timer1_0
  21 : peri_3_0_irq-timer1_1
  22 : peri_3_0_irq-timer1_2
  23 : peri_3_0_irq-timer1_3
  24 : peri_3_0_irq-uart_0
  25 : peri_3_0_irq-uart_1
  26 : peri_3_0_irq-i2c_0
  27 : peri_3_0_irq-i2c_1
  28 : peri_3_0_irq-spi_0
  29 : peri_3_0_irq-spi_1
  30 : peri_3_0_irq-sqi_0
  31 : peri_3_0_irq-sqi_1
  32 : peri_3_1_irq-wdg0_0
  33 : peri_3_1_irq-wdg0_1
  34 : peri_3_1_irq-wdg1_0
  35 : peri_3_1_irq-wdg1_1
  36 : peri_3_1_irq-pio_0
  37 : peri_3_1_irq-ram_ctrl_0
  38 : no active IRQ
R/W
0x00000000
Address : 0x4921113c
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
ram_ctrl_0
Event - ram_ctrl[0] contribution to IRQ peri[3]
4 "0"
pio_0
Event - pio[0] contribution to IRQ peri[3]
3 "0"
wdg1_1
Event - wdg1[1] contribution to IRQ peri[3]
2 "0"
wdg1_0
Event - wdg1[0] contribution to IRQ peri[3]
1 "0"
wdg0_1
Event - wdg0[1] contribution to IRQ peri[3]
0 "0"
wdg0_0
Event - wdg0[0] contribution to IRQ peri[3]



Base Address Area: mot_irq_router_cpu1_shdint_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W mot_irq_router_cpu1_shdint_0_irq_raw
1 4 R/W mot_irq_router_cpu1_shdint_0_irq_masked
2 8 R/W mot_irq_router_cpu1_shdint_0_irq_mask_set
3 c R/W mot_irq_router_cpu1_shdint_0_irq_mask_rst

mot_irq_router_cpu1_shdint_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x49211140
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu1_shdint_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_mot_irq_router_cpu1_shdint_0_irq_raw).
R/W
0x00000000
Address : 0x49211144
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu1_shdint_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_mot_irq_router_cpu1_shdint_0_irq_raw
R/W
0x00000000
Address : 0x49211148
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]


mot_irq_router_cpu1_shdint_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 24 when no IRQ is set:
  0  : shdint_0_irq-shdint_0
  1  : shdint_0_irq-shdint_1
  2  : shdint_0_irq-shdint_2
  3  : shdint_0_irq-shdint_3
  4  : shdint_0_irq-shdint_4
  5  : shdint_0_irq-shdint_5
  6  : shdint_0_irq-shdint_6
  7  : shdint_0_irq-shdint_7
  8  : shdint_0_irq-shdint_8
  9  : shdint_0_irq-shdint_9
  10 : shdint_0_irq-shdint_10
  11 : shdint_0_irq-shdint_11
  12 : shdint_0_irq-shdint_12
  13 : shdint_0_irq-shdint_13
  14 : shdint_0_irq-shdint_14
  15 : shdint_0_irq-shdint_15
  16 : shdint_0_irq-shdint_16
  17 : shdint_0_irq-shdint_17
  18 : shdint_0_irq-shdint_18
  19 : shdint_0_irq-shdint_19
  20 : shdint_0_irq-shdint_20
  21 : shdint_0_irq-shdint_21
  22 : shdint_0_irq-shdint_22
  23 : shdint_0_irq-shdint_23
  24 : no active IRQ
R/W
0x00000000
Address : 0x4921114c
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
shdint_23
Event - shdint[23] contribution to IRQ shdint[0]
22 "0"
shdint_22
Event - shdint[22] contribution to IRQ shdint[0]
21 "0"
shdint_21
Event - shdint[21] contribution to IRQ shdint[0]
20 "0"
shdint_20
Event - shdint[20] contribution to IRQ shdint[0]
19 "0"
shdint_19
Event - shdint[19] contribution to IRQ shdint[0]
18 "0"
shdint_18
Event - shdint[18] contribution to IRQ shdint[0]
17 "0"
shdint_17
Event - shdint[17] contribution to IRQ shdint[0]
16 "0"
shdint_16
Event - shdint[16] contribution to IRQ shdint[0]
15 "0"
shdint_15
Event - shdint[15] contribution to IRQ shdint[0]
14 "0"
shdint_14
Event - shdint[14] contribution to IRQ shdint[0]
13 "0"
shdint_13
Event - shdint[13] contribution to IRQ shdint[0]
12 "0"
shdint_12
Event - shdint[12] contribution to IRQ shdint[0]
11 "0"
shdint_11
Event - shdint[11] contribution to IRQ shdint[0]
10 "0"
shdint_10
Event - shdint[10] contribution to IRQ shdint[0]
9 "0"
shdint_9
Event - shdint[9] contribution to IRQ shdint[0]
8 "0"
shdint_8
Event - shdint[8] contribution to IRQ shdint[0]
7 "0"
shdint_7
Event - shdint[7] contribution to IRQ shdint[0]
6 "0"
shdint_6
Event - shdint[6] contribution to IRQ shdint[0]
5 "0"
shdint_5
Event - shdint[5] contribution to IRQ shdint[0]
4 "0"
shdint_4
Event - shdint[4] contribution to IRQ shdint[0]
3 "0"
shdint_3
Event - shdint[3] contribution to IRQ shdint[0]
2 "0"
shdint_2
Event - shdint[2] contribution to IRQ shdint[0]
1 "0"
shdint_1
Event - shdint[1] contribution to IRQ shdint[0]
0 "0"
shdint_0
Event - shdint[0] contribution to IRQ shdint[0]



Base Address Area: secenc_timer0, secenc_timer1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cmsdk_timer_ctrl
1 4 R/W cmsdk_timer_value
2 8 R/W cmsdk_timer_reload
3 c R/W cmsdk_timer_int
4-3f3 10-fcc -  reserved
3f4 fd0 R cmsdk_timer_pid4
3f5 fd4 R cmsdk_timer_pid5
3f6 fd8 R cmsdk_timer_pid6
3f7 fdc R cmsdk_timer_pid7
3f8 fe0 R cmsdk_timer_pid0
3f9 fe4 R cmsdk_timer_pid1
3fa fe8 R cmsdk_timer_pid2
3fb fec R cmsdk_timer_pid3
3fc ff0 R cmsdk_timer_cid0
3fd ff4 R cmsdk_timer_cid1
3fe ff8 R cmsdk_timer_cid2
3ff ffc R cmsdk_timer_cid3

cmsdk_timer_ctrl
Timer control register
R/W
0x00000000
Address@secenc_timer0 : 0x50000000
Address@secenc_timer1 : 0x50001000
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
timer_interrupt_enable
Timer interrupt enable
2 "0"
select_external_input_as_clock
Select external input as clock
1 "0"
select_external_input_as_enable
Select external input as enable
0 "0"
enable
Timer enable


cmsdk_timer_value
Timer value register
R/W
0x00000000
Address@secenc_timer0 : 0x50000004
Address@secenc_timer1 : 0x50001004
Bits Reset value Name Description
31 - 0 0x0
value
Current value


cmsdk_timer_reload
Timer reload register
R/W
0x00000000
Address@secenc_timer0 : 0x50000008
Address@secenc_timer1 : 0x50001008
Bits Reset value Name Description
31 - 0 0x0
reload
Reload value. A write to this register sets the current value after it reaches 0.


cmsdk_timer_int
Timer INTSTATUS/INTCLEAR register
R/W
0x00000000
Address@secenc_timer0 : 0x5000000c
Address@secenc_timer1 : 0x5000100c
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
stat_clr
Timer interrupt. Write one to clear.


cmsdk_timer_pid4
Peripheral ID Register 4
R
Address@secenc_timer0 : 0x50000fd0
Address@secenc_timer1 : 0x50001fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 block_count
Number of 4KB occupied by the block.
3 - 0 jep106_c_code
JEP Continuation


cmsdk_timer_pid5
Peripheral ID Register 5
R
Address@secenc_timer0 : 0x50000fd4
Address@secenc_timer1 : 0x50001fd4
Bits Name Description
31 - 0 cmsdk_timer_pid5


cmsdk_timer_pid6
Peripheral ID Register 6
R
Address@secenc_timer0 : 0x50000fd8
Address@secenc_timer1 : 0x50001fd8
Bits Name Description
31 - 0 cmsdk_timer_pid6


cmsdk_timer_pid7
Peripheral ID Register 7
R
Address@secenc_timer0 : 0x50000fdc
Address@secenc_timer1 : 0x50001fdc
Bits Name Description
31 - 0 cmsdk_timer_pid7


cmsdk_timer_pid0
Peripheral ID Register 0
R
Address@secenc_timer0 : 0x50000fe0
Address@secenc_timer1 : 0x50001fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cmsdk_timer_pid1
Peripheral ID Register 1
R
Address@secenc_timer0 : 0x50000fe4
Address@secenc_timer1 : 0x50001fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 jep106_id_3_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cmsdk_timer_pid2
Peripheral ID Register 2
R
Address@secenc_timer0 : 0x50000fe8
Address@secenc_timer1 : 0x50001fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec_used
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 jep106_id_6_4
Bits [6:4] of JEP 106 Identity


cmsdk_timer_pid3
Peripheral ID Register 3
R
Address@secenc_timer0 : 0x50000fec
Address@secenc_timer1 : 0x50001fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 eco_rev_num
Minor revision number of the block
3 - 0 cmod
Customer modification number


cmsdk_timer_cid0
Component ID Register 0
R
Address@secenc_timer0 : 0x50000ff0
Address@secenc_timer1 : 0x50001ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cmsdk_timer_cid1
Component ID Register 1
R
Address@secenc_timer0 : 0x50000ff4
Address@secenc_timer1 : 0x50001ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cmsdk_timer_cid2
Component ID Register 2
R
Address@secenc_timer0 : 0x50000ff8
Address@secenc_timer1 : 0x50001ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cmsdk_timer_cid3
Component ID Register 3
R
Address@secenc_timer0 : 0x50000ffc
Address@secenc_timer1 : 0x50001ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: secenc_otp0, secenc_otp1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W secenc_otp_base
1-7fe 4-1ff8 -  reserved
7ff 1ffc R/W secenc_otp_end

secenc_otp_base
SecEnc OTP start address
Area size: 8kB
R/W
0x00000000
Address@secenc_otp0 : 0x50018000
Address@secenc_otp1 : 0x5001a000
Bits Reset value Name Description
31 - 0 0
secenc_otp_base


secenc_otp_end
SecEnc OTP end address
R/W
0x00000000
Address@secenc_otp0 : 0x50019ffc
Address@secenc_otp1 : 0x5001bffc
Bits Reset value Name Description
31 - 0 0
secenc_otp_end



Base Address Area: secenc_asic_ctrl_sse

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R secenc_asic_ctrl_sse_system_status
1-3ff 4-ffc -  reserved

secenc_asic_ctrl_sse_system_status
SecEnc System Status Register
This register provides information of netX system events and status.
R
Address : 0x5001e000
Bits Name Description
31 - 2 -
 reserved
1 top_dftenable
Sampled TESTMODE input & SSE710 DFTENABLE signals for production test purpose
0 testmode
Sampled TESTMODE input for production test purpose



Base Address Area: secenc_hash

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 W hash_din
1 4 R/W hash_cfg
2 8 W hash_ctrl
3 c R hash_stat
4 10 -  reserved
5 14 R/W hash_irq_raw
6 18 R/W hash_irq_masked
7 1c R/W hash_irq_mask_set
8 20 R/W hash_irq_mask_rst
9 24 R hash_dout0
a 28 R hash_dout1
b 2c R hash_dout2
c 30 R hash_dout3
d 34 R hash_dout4
e 38 R hash_dout5
f 3c R hash_dout6
10 40 R hash_dout7
11 44 R hash_dout8
12 48 R hash_dout9
13 4c R hash_dout10
14 50 R hash_dout11
15 54 R hash_dout12
16 58 R hash_dout13
17 5c R hash_dout14
18 60 R hash_dout15
19 64 R/W hash_hmac_key0
1a 68 R/W hash_hmac_key1
1b 6c R/W hash_hmac_key2
1c 70 R/W hash_hmac_key3
1d 74 R/W hash_hmac_key4
1e 78 R/W hash_hmac_key5
1f 7c R/W hash_hmac_key6
20 80 R/W hash_hmac_key7
21 84 R/W hash_hmac_key8
22 88 R/W hash_hmac_key9
23 8c R/W hash_hmac_key10
24 90 R/W hash_hmac_key11
25 94 R/W hash_hmac_key12
26 98 R/W hash_hmac_key13
27 9c R/W hash_hmac_key14
28 a0 R/W hash_hmac_key15
29-3f a4-fc -  reserved

hash_din
Hash FIFO input:
Unlike all other registers, this address can be written with DWord(32 Bit), Word(16 Bit) or Byte acccss.
The FIFO controller will automatically collect data and start HASH-calculation,
if enough data (complete DWords) are collected.
W
0x00000000
Address : 0x5001f000
Bits Reset value Name Description
31 - 0 0x0
val
data bits


hash_cfg
Hash config register:
R/W
0x00000000
Address : 0x5001f004
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
hmac_en
Enable HMAC processing
4 "0"
reset
Reset of HASH engines:
1: reset internal registers, use this to start calculation of new hash
0: start calculation as soon as enough data in FIFO buffer
After writing '1', this bit will automatically be reset.
3 - 1 "000"
mode
Hash core mode
101: MD5
100: SHA2-512
011: SHA2-384
010: SHA2-256
001: SHA2-224
000: SHA1-160
Note: When changing the mode, a reset must be performed to correctly initialize the SHA/MD5 core. This can be done by setting the 'reset' bit together with the new mode or in a second access after setting the mode.
0 "0"
enable
Global enable signal
This bit and the mode bit field control the clock enable to the algorithm cores for power-saving purposes. Be sure to keep enabled as long as operations are outstanding (e.g. also for soft-reset).


hash_ctrl
Hash control register:
W
0x00000000
Address : 0x5001f008
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
hmac_finish
Signal to finish first round of HMAC and start final round
After writing '1', this bit will automatically be reset.
0 "0"
trigger_padding
Signal to pad the input data as soon as the fifo is depleted.
After writing '1', this bit will automatically be reset.


hash_stat
Hash status register:
R
Address : 0x5001f00c
Bits Name Description
31 - 9 -
 reserved
8 - 0 fifo_fill
Fill level of FIFO in bytes (0..256)


hash_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x5001f014
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_hash_irq_raw).
R/W
0x00000000
Address : 0x5001f018
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
R/W
0x00000000
Address : 0x5001f01c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 3 when no IRQ is set:
  0 : irq-hash_ready
  1 : irq-fifo_underrun
  2 : irq-fifo_overflow
  3 : no active IRQ
R/W
0x00000000
Address : 0x5001f020
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
fifo_overflow
input buffer was overflown, set hash_cfg-reset=1 to reset this bit
1 "0"
fifo_underrun
input buffer was underrun, set hash_cfg-reset=1 to reset this bit
0 "0"
hash_ready
Hash core has finished calculation and hash value inside the registers crypt_hash[15:0] is valid


hash_dout0
Hash value0 register
R
Address : 0x5001f024
Bits Name Description
31 - 0 val
data bits 31..0


hash_dout1
Hash value1 register
R
Address : 0x5001f028
Bits Name Description
31 - 0 val
data bits 63..32


hash_dout2
Hash value2 register
R
Address : 0x5001f02c
Bits Name Description
31 - 0 val
data bits 95..64


hash_dout3
Hash value3 register
R
Address : 0x5001f030
Bits Name Description
31 - 0 val
data bits 127..96


hash_dout4
Hash value4 register
R
Address : 0x5001f034
Bits Name Description
31 - 0 val
data bits 159..128


hash_dout5
Hash value5 register
R
Address : 0x5001f038
Bits Name Description
31 - 0 val
data bits 191..160


hash_dout6
Hash value6 register
R
Address : 0x5001f03c
Bits Name Description
31 - 0 val
data bits 223..192


hash_dout7
Hash value7 register
R
Address : 0x5001f040
Bits Name Description
31 - 0 val
data bits 255..224


hash_dout8
Hash value8 register
R
Address : 0x5001f044
Bits Name Description
31 - 0 val
data bits 287..256


hash_dout9
Hash value9 register
R
Address : 0x5001f048
Bits Name Description
31 - 0 val
data bits 319..288


hash_dout10
Hash value10 register
R
Address : 0x5001f04c
Bits Name Description
31 - 0 val
data bits 351..320


hash_dout11
Hash value11 register
R
Address : 0x5001f050
Bits Name Description
31 - 0 val
data bits 383..352


hash_dout12
Hash value12 register
R
Address : 0x5001f054
Bits Name Description
31 - 0 val
data bits 415..384


hash_dout13
Hash value13 register
R
Address : 0x5001f058
Bits Name Description
31 - 0 val
data bits 447..416


hash_dout14
Hash value14 register
R
Address : 0x5001f05c
Bits Name Description
31 - 0 val
data bits 479..448


hash_dout15
Hash value15 register
R
Address : 0x5001f060
Bits Name Description
31 - 0 val
data bits 511..480


hash_hmac_key0
HMAC Key0 register
R/W
0x00000000
Address : 0x5001f064
Bits Reset value Name Description
31 - 0 0x0
val
data bits 31..0


hash_hmac_key1
HMAC Key1 register
R/W
0x00000000
Address : 0x5001f068
Bits Reset value Name Description
31 - 0 0x0
val
data bits 63..32


hash_hmac_key2
HMAC Key2 register
R/W
0x00000000
Address : 0x5001f06c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 95..64


hash_hmac_key3
HMAC Key3 register
R/W
0x00000000
Address : 0x5001f070
Bits Reset value Name Description
31 - 0 0x0
val
data bits 127..96


hash_hmac_key4
HMAC Key4 register
R/W
0x00000000
Address : 0x5001f074
Bits Reset value Name Description
31 - 0 0x0
val
data bits 159..128


hash_hmac_key5
HMAC Key5 register
R/W
0x00000000
Address : 0x5001f078
Bits Reset value Name Description
31 - 0 0x0
val
data bits 191..160


hash_hmac_key6
HMAC Key6 register
R/W
0x00000000
Address : 0x5001f07c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 223..192


hash_hmac_key7
HMAC Key7 register
R/W
0x00000000
Address : 0x5001f080
Bits Reset value Name Description
31 - 0 0x0
val
data bits 255..224


hash_hmac_key8
HMAC Key8 register
R/W
0x00000000
Address : 0x5001f084
Bits Reset value Name Description
31 - 0 0x0
val
data bits 287..256


hash_hmac_key9
HMAC Key9 register
R/W
0x00000000
Address : 0x5001f088
Bits Reset value Name Description
31 - 0 0x0
val
data bits 319..288


hash_hmac_key10
HMAC Key10 register
R/W
0x00000000
Address : 0x5001f08c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 351..320


hash_hmac_key11
HMAC Key11 register
R/W
0x00000000
Address : 0x5001f090
Bits Reset value Name Description
31 - 0 0x0
val
data bits 383..352


hash_hmac_key12
HMAC Key12 register
R/W
0x00000000
Address : 0x5001f094
Bits Reset value Name Description
31 - 0 0x0
val
data bits 415..384


hash_hmac_key13
HMAC Key13 register
R/W
0x00000000
Address : 0x5001f098
Bits Reset value Name Description
31 - 0 0x0
val
data bits 447..416


hash_hmac_key14
HMAC Key14 register
R/W
0x00000000
Address : 0x5001f09c
Bits Reset value Name Description
31 - 0 0x0
val
data bits 479..448


hash_hmac_key15
HMAC Key15 register
R/W
0x00000000
Address : 0x5001f0a0
Bits Reset value Name Description
31 - 0 0x0
val
data bits 511..480



Base Address Area: secenc_sys2jtag

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sys2jtag_cfg
1 4 W sys2jtag_cmd_data
2 8 R sys2jtag_status_data
3 c R sys2jtag_status
4 10 R sys2jtag_chain_status
5 14 R/W sys2jtag_chain_cfg
6 18 R sys2jtag_handshake_rx
7 1c R/W sys2jtag_handshake_tx

sys2jtag_cfg
Configuration register
R/W
0x00000000
Address : 0x50020000
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 - 1 "00"
speed
JTAG TCK speed
Value Speed
2'b00 sysclk / 4
2'b01 sysclk / 8
2'b10 sysclk / 16
2'b11 sysclk / 32
0 "0"
enable
Global enable


sys2jtag_cmd_data
Command and send data register
W
0x00000000
Address : 0x50020004
Bits Reset value Name Description
31 - 24 "00000000"
cmd
Command
New commands are only accepted when the JTAG sequence generator is IDLE.
The command conding is as follows:
cmd[7:6] Operation
2'b00

Shift
cmd[6]: Reserved
cmd[5]: TMS state of last bit
cmd[4:0]: Length (bits - 1); allowed range: 0-23
2'b01




Statemove
cmd[6]: Reserved
cmd[5:0]: TMS sequence index
The index of an n-bit TMS sequence is determined by the following formula:
index = offset[n] + (binary representation of TMS sequence)
with offset[1] = 0, offset[2] = 2, offset[3] = 6, offset[4] = 14, offset[5] = 30.
Note: Index 0x3e (TMS sequence 6'b001111) has been added as a special shortcut for the statemove from "PAUSE-DR" to "SHIFT-IR". The movement can also be generated by sending indices 0x2d and 0x0 consecutively. Index 0x3f is reserved.
2'b10
Reset
cmd[6:1]: Reserved
cmd[0]: New state on nTRST signal
2'b11
Direct pin control
cmd[6:4]: Reserved
cmd[3:0]: Length (bits - 1); allowed range: 0-11

Note: Commands with invalid lengths will be silently dropped.
Only the "shift" and "direct pin control" commands use the data field in this register as well as the data field in the "status_data" register.
23 - 0 0x0
data
Transmit data (TDI) associated to given command


sys2jtag_status_data
Status and receive data register
R
Address : 0x50020008
Bits Name Description
31 idle
JTAG sequence generator is IDLE and accepts new commands
30 - 27 tap_state
Current JTAG TAP state
The state coding is according to the example TAP controller implementation of the IEEE1149.1-1990 standard:
Value TAP state
4'b1111 TEST-LOGIC-RESET
4'b1100 RUN-TEST/IDLE
4'b0111 SELECT-DR-SCAN
4'b0110 CAPTURE-DR
4'b0010 SHIFT-DR
4'b0001 EXIT1-DR
4'b0011 PAUSE-DR
4'b0000 EXIT2-DR
4'b0101 UPDATE-DR
4'b0100 SELECT-IR-SCAN
4'b1110 CAPTURE-IR
4'b1010 SHIFT-IR
4'b1001 EXIT1-IR
4'b1011 PAUSE-IR
4'b1000 EXIT2-IR
4'b1101 UPDATE-IR
26 - 24 -
 reserved
23 - 0 data
Received data (TDO) from previous command
Data is only valid when idle == 1.


sys2jtag_status
Status register
R
Address : 0x5002000c
Bits Name Description
31 idle
JTAG sequence generator is IDLE and accepts new commands
30 - 27 tap_state
Current JTAG TAP state
The state coding is according to the example TAP controller implementation of the IEEE1149.1-1990 standard:
Value TAP state
4'b1111 TEST-LOGIC-RESET
4'b1100 RUN-TEST/IDLE
4'b0111 SELECT-DR-SCAN
4'b0110 CAPTURE-DR
4'b0010 SHIFT-DR
4'b0001 EXIT1-DR
4'b0011 PAUSE-DR
4'b0000 EXIT2-DR
4'b0101 UPDATE-DR
4'b0100 SELECT-IR-SCAN
4'b1110 CAPTURE-IR
4'b1010 SHIFT-IR
4'b1001 EXIT1-IR
4'b1011 PAUSE-IR
4'b1000 EXIT2-IR
4'b1101 UPDATE-IR
26 - 0 -
 reserved


sys2jtag_chain_status
JTAG chain status register
This register represents the status of the JTAG chain as it is currently configured by the DFT TAP.
R
Address : 0x50020010
Bits Name Description
31 - 2 -
 reserved
1 sel_sys2jtag
DFT TAP selected the JTAG signals from SYS2JTAG to reach the
TAP chain. SYS2JTAG can only operate if both, sel_sys2jtag and
en_sys2jtag, are set to '1' by the DFT TAP.
0 en_sys2jtag
DFT TAP enabled routing of the JTAG signals from SYS2JTAG.
If this bit is 0 the JTAG signals from SYS2JTAG are clamped into
the inactive state.


sys2jtag_chain_cfg
JTAG chain configuration register
If SYS2JTAG is able to use the JTAG chain (see 'sys2jtag_chain_status' register), this register configures which TAPs are put into the JTAG chain.
R/W
0x00000000
Address : 0x50020014
Bits Reset value Name Description
31 - 0 0x0
tap_active
Configuration of TAPs to put into the chain.
Each bit represents a single TAP within the chain.


sys2jtag_handshake_rx
Handshake receive register
This register can be used to handshake with the DFT TAP instance in the system.
R
Address : 0x50020018
Bits Name Description
31 - 8 -
 reserved
7 - 0 val
This is the value written by the DFT TAP.


sys2jtag_handshake_tx
Handshake transmit register
This register can be used to handshake with another TAP controller instance in the system.
R/W
0x00000000
Address : 0x5002001c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
val
This value is readable by DFT TAP.



Base Address Area: secenc_sys_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R secenc_sys_ctrl_se_rst_syn
1 4 R/W secenc_sys_ctrl_se_rst_msk
2 8 R/W secenc_sys_ctrl_se_pwr_ctrl
3-4 c-10 -  reserved
5 14 R/W secenc_sys_ctrl_se_gp0
6 18 R/W secenc_sys_ctrl_se_gp1
7 1c R/W secenc_sys_ctrl_se_gp2
8 20 R/W secenc_sys_ctrl_se_gp3
9-b 24-2c -  reserved
c 30 R/W secenc_sys_ctrl_se_clk_div
d-3d 34-f4 -  reserved
3e f8 R secenc_sys_ctrl_se_bld_cfg
3f-3f3 fc-fcc -  reserved
3f4 fd0 R secenc_sys_ctrl_pid4
3f5 fd4 R secenc_sys_ctrl_pid5
3f6 fd8 R secenc_sys_ctrl_pid6
3f7 fdc R secenc_sys_ctrl_pid7
3f8 fe0 R secenc_sys_ctrl_pid0
3f9 fe4 R secenc_sys_ctrl_pid1
3fa fe8 R secenc_sys_ctrl_pid2
3fb fec R secenc_sys_ctrl_pid3
3fc ff0 R secenc_sys_ctrl_cid0
3fd ff4 R secenc_sys_ctrl_cid1
3fe ff8 R secenc_sys_ctrl_cid2
3ff ffc R secenc_sys_ctrl_cid3

secenc_sys_ctrl_se_rst_syn
Secure Enclave Reset Syndrome
R
Address : 0x50080000
Bits Name Description
31 - 3 -
 reserved
2 ca_err
Indicates the last reset of the Secure Enclave was caused by an error of the Crypto Accelerator or not.
0b0: Last reset of the Secure Enclave was not caused by an error of the Crypto Accelerator.
0b1: Last reset of the Secure Enclave was caused by an error of the Crypto Accelerator.
1 wd_reset
Indicates that the last reset cause of the SecEnc caused by the SecEnc watchdog.
0 sw_reset
Indicates that the last reset cause of the SecEnc was caused by the Secure Enclave software reset request.


secenc_sys_ctrl_se_rst_msk
Secure Enclave Reset Mask
R/W
0x00000000
Address : 0x50080004
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
ca_err_msk
Controls whether an error of the Crypto Accelerator generates an IPoR:
0b0: An error of the Crypto Accelerator generates an IPoR.
0b1: An error of the Crypto Accelerator does not generate an IPoR.
Software must only change the value of this field when there is no error of the Crypto Accelerator outstanding, otherwise it is UNPREDICTABLE whether an IPoR is generated or not.
1 - 0 0
-
 reserved


secenc_sys_ctrl_se_pwr_ctrl
Secure Enclave Power Control
R/W
0x00000000
Address : 0x50080008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
pwr_gate_en
SECENCTOP can enter OFF or MEM_RET:
0b0: SECENCTOP must remain in ON.
0b1: SECENCTOP can enter OFF or MEM_RET next time the Secure Enclave is idle.


secenc_sys_ctrl_se_gp0
Secure Enclave General Purpose 0
R/W
0x00000000
Address : 0x50080014
Bits Reset value Name Description
31 - 0 0x0
gp
General-purpose data register


secenc_sys_ctrl_se_gp1
Secure Enclave General Purpose 1
R/W
0x00000000
Address : 0x50080018
Bits Reset value Name Description
31 - 0 0x0
gp
General-purpose data register


secenc_sys_ctrl_se_gp2
Secure Enclave General Purpose 2
R/W
0x00000000
Address : 0x5008001c
Bits Reset value Name Description
31 - 0 0x0
gp
General-purpose data register


secenc_sys_ctrl_se_gp3
Secure Enclave General Purpose 3
R/W
0x00000000
Address : 0x50080020
Bits Reset value Name Description
31 - 0 0x0
gp
General-purpose data register


secenc_sys_ctrl_se_clk_div
Secure Enclave Clock Divider Control register
R/W
0x00000001
Address : 0x50080030
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur
Current value of integer divider applied to SECENCCLK:
0x00: Divide by 1, 0x01: Divide by 2, ..., 0x1F: Divide by 32
15 - 5 0
-
 reserved
4 - 0 "00001"
clk_divider
Controls the clock divider ratio:
0: 1:1 ratio between SECENCDIVCLK clock and SECENCCLK clock
1: 1:2 ratio between SECENCDIVCLK and SECENCCLK
2 - 31: Reserved


secenc_sys_ctrl_se_bld_cfg
Secure Enclave Build Configuration register
R
Address : 0x500800f8
Bits Name Description
31 - 16 ram_size
Secure Enclave RAM size.
The value of this field is the size of the Secure Enclave RAM in KB.
A value of 0x00 is Reserved.
For example, a value of 0x40 indicates a RAM of 64KB whilst a value of 0x80 indicates a RAM of 128KB.
15 - 0 rom_size
Secure Enclave ROM size.
The value of this field is the size of the Secure Enclave ROM in KB.
A value of 0x00 is Reserved.
For example, a value of 0x20 indicates a ROM of 32KB whilst a value of 0x40 indicates a ROM of 64KB.


secenc_sys_ctrl_pid4
Peripheral ID Register 4
R
Address : 0x50080fd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


secenc_sys_ctrl_pid5
Peripheral ID Register 5
R
Address : 0x50080fd4
Bits Name Description
31 - 0 secenc_sys_ctrl_pid5


secenc_sys_ctrl_pid6
Peripheral ID Register 6
R
Address : 0x50080fd8
Bits Name Description
31 - 0 secenc_sys_ctrl_pid6


secenc_sys_ctrl_pid7
Peripheral ID Register 7
R
Address : 0x50080fdc
Bits Name Description
31 - 0 secenc_sys_ctrl_pid7


secenc_sys_ctrl_pid0
Peripheral ID Register 0
R
Address : 0x50080fe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


secenc_sys_ctrl_pid1
Peripheral ID Register 1
R
Address : 0x50080fe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


secenc_sys_ctrl_pid2
Peripheral ID Register 2
R
Address : 0x50080fe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


secenc_sys_ctrl_pid3
Peripheral ID Register 3
R
Address : 0x50080fec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision of the block
3 - 0 cmod
Customer modification field


secenc_sys_ctrl_cid0
Component ID Register 0
R
Address : 0x50080ff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


secenc_sys_ctrl_cid1
Component ID Register 1
R
Address : 0x50080ff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


secenc_sys_ctrl_cid2
Component ID Register 2
R
Address : 0x50080ff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


secenc_sys_ctrl_cid3
Component ID Register 3
R
Address : 0x50080ffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: secenc_watchdog, secenc_soc_watchdog

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W cmsdk_wdog_wdogload
1 4 R cmsdk_wdog_wdogvalue
2 8 R/W cmsdk_wdog_wdogcontrol
3 c W cmsdk_wdog_wdogintclr
4 10 R cmsdk_wdog_wdogris
5 14 R cmsdk_wdog_wdogmis
6-2ff 18-bfc -  reserved
300 c00 R/W cmsdk_wdog_wdoglock
301-3bf c04-efc -  reserved
3c0 f00 R/W cmsdk_wdog_wdogitcr
3c1 f04 W cmsdk_wdog_wdogitor
3c2-3f3 f08-fcc -  reserved
3f4 fd0 R cmsdk_wdog_pid4
3f5 fd4 R cmsdk_wdog_pid5
3f6 fd8 R cmsdk_wdog_pid6
3f7 fdc R cmsdk_wdog_pid7
3f8 fe0 R cmsdk_wdog_pid0
3f9 fe4 R cmsdk_wdog_pid1
3fa fe8 R cmsdk_wdog_pid2
3fb fec R cmsdk_wdog_pid3
3fc ff0 R cmsdk_wdog_cid0
3fd ff4 R cmsdk_wdog_cid1
3fe ff8 R cmsdk_wdog_cid2
3ff ffc R cmsdk_wdog_cid3

cmsdk_wdog_wdogload
Watchdog Load register
R/W
0x00000000
Address@secenc_watchdog : 0x50081000
Address@secenc_soc_watchdog : 0x5008f000
Bits Reset value Name Description
31 - 0 0x0
value
The register contains the value from which the counter is to decrement.
When this register is written to, the count is immediately restarted from the new value.
The minimum valid value is 1.


cmsdk_wdog_wdogvalue
Watchdog Value register
R
Address@secenc_watchdog : 0x50081004
Address@secenc_soc_watchdog : 0x5008f004
Bits Name Description
31 - 0 value
The register gives the current value of the decrementing counter.


cmsdk_wdog_wdogcontrol
Watchdog Control register
R/W
0x00000000
Address@secenc_watchdog : 0x50081008
Address@secenc_soc_watchdog : 0x5008f008
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
resen
Enable watchdog reset output, WDOGRES. Acts as a mask for the reset output.
Set to 1 to enable the reset, or to 0 to disable the reset.
0 "0"
inten
Enable the interrupt event, WDOGINT.
Set to 1 to enable the counter and the interrupt, or to 0 to disable the counter and interrupt.
Reloads the counter from the value in WDOGLOAD when the interrupt is enabled, after previously being disabled.


cmsdk_wdog_wdogintclr
Watchdog Interrupt register
W
0x00000000
Address@secenc_watchdog : 0x5008100c
Address@secenc_soc_watchdog : 0x5008f00c
Bits Reset value Name Description
31 - 0 0x0
value
A write of any value to the register clears the watchdog interrupt, and reloads the counter from the value in load register.


cmsdk_wdog_wdogris
Watchdog Raw Interrupt Status register
R
Address@secenc_watchdog : 0x50081010
Address@secenc_soc_watchdog : 0x5008f010
Bits Name Description
31 - 1 -
 reserved
0 stat
Raw interrupt status from the counter.


cmsdk_wdog_wdogmis
Watchdog Interrupt Status register
R
Address@secenc_watchdog : 0x50081014
Address@secenc_soc_watchdog : 0x5008f014
Bits Name Description
31 - 1 -
 reserved
0 stat
Enabled interrupt status from the counter.


cmsdk_wdog_wdoglock
Watchdog Lock register
R/W
0x00000000
Address@secenc_watchdog : 0x50081c00
Address@secenc_soc_watchdog : 0x5008fc00
Bits Reset value Name Description
31 - 1 0x0
write_value
Enable register writes
Enable write access to all other registers by writing 0x1ACCE551.
Disable write access by writing any other value.
0 "0"
write_enable
Register write enable status
0: Write access to all other registers is enabled. This is the default.
1: Write access to all other registers is disabled.


cmsdk_wdog_wdogitcr
Watchdog Integration Test Control register
R/W
0x00000000
Address@secenc_watchdog : 0x50081f00
Address@secenc_soc_watchdog : 0x5008ff00
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
enable
When set to 1, places the watchdog into integration test mode.


cmsdk_wdog_wdogitor
Watchdog Integration Test Output Set register
W
0x00000000
Address@secenc_watchdog : 0x50081f04
Address@secenc_soc_watchdog : 0x5008ff04
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
wdogint_value
Value output on WDOGINT when in integration test mode.
0 "0"
wdogres_value
Value output on WDOGRES when in integration test mode.


cmsdk_wdog_pid4
Peripheral ID Register 4
R
Address@secenc_watchdog : 0x50081fd0
Address@secenc_soc_watchdog : 0x5008ffd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 block_count
Number of 4KB occupied by the block.
3 - 0 jep106_c_code
JEP Continuation


cmsdk_wdog_pid5
Peripheral ID Register 5
R
Address@secenc_watchdog : 0x50081fd4
Address@secenc_soc_watchdog : 0x5008ffd4
Bits Name Description
31 - 0 cmsdk_wdog_pid5


cmsdk_wdog_pid6
Peripheral ID Register 6
R
Address@secenc_watchdog : 0x50081fd8
Address@secenc_soc_watchdog : 0x5008ffd8
Bits Name Description
31 - 0 cmsdk_wdog_pid6


cmsdk_wdog_pid7
Peripheral ID Register 7
R
Address@secenc_watchdog : 0x50081fdc
Address@secenc_soc_watchdog : 0x5008ffdc
Bits Name Description
31 - 0 cmsdk_wdog_pid7


cmsdk_wdog_pid0
Peripheral ID Register 0
R
Address@secenc_watchdog : 0x50081fe0
Address@secenc_soc_watchdog : 0x5008ffe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


cmsdk_wdog_pid1
Peripheral ID Register 1
R
Address@secenc_watchdog : 0x50081fe4
Address@secenc_soc_watchdog : 0x5008ffe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 jep106_id_3_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


cmsdk_wdog_pid2
Peripheral ID Register 2
R
Address@secenc_watchdog : 0x50081fe8
Address@secenc_soc_watchdog : 0x5008ffe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec_used
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 jep106_id_6_4
Bits [6:4] of JEP 106 Identity


cmsdk_wdog_pid3
Peripheral ID Register 3
R
Address@secenc_watchdog : 0x50081fec
Address@secenc_soc_watchdog : 0x5008ffec
Bits Name Description
31 - 8 -
 reserved
7 - 4 eco_rev_num
Minor revision number of the block
3 - 0 cmod
Customer modification number


cmsdk_wdog_cid0
Component ID Register 0
R
Address@secenc_watchdog : 0x50081ff0
Address@secenc_soc_watchdog : 0x5008fff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


cmsdk_wdog_cid1
Component ID Register 1
R
Address@secenc_watchdog : 0x50081ff4
Address@secenc_soc_watchdog : 0x5008fff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


cmsdk_wdog_cid2
Component ID Register 2
R
Address@secenc_watchdog : 0x50081ff8
Address@secenc_soc_watchdog : 0x5008fff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


cmsdk_wdog_cid3
Component ID Register 3
R
Address@secenc_watchdog : 0x50081ffc
Address@secenc_soc_watchdog : 0x5008fffc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: secenc_base_sys_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W secenc_base_sys_ctrl_host_sys_rst_ctrl
1 4 R secenc_base_sys_ctrl_host_sys_rst_st
2 8 R/W secenc_base_sys_ctrl_soc_rst_ctrl
3 c R secenc_base_sys_ctrl_soc_rst_syn
4 10 R secenc_base_sys_ctrl_int_col_st0
5 14 R secenc_base_sys_ctrl_int_col_st1
6 18 R secenc_base_sys_ctrl_int_col_st2
7 1c R secenc_base_sys_ctrl_int_col_st3
8 20 R/W secenc_base_sys_ctrl_int_col_msk0
9 24 R/W secenc_base_sys_ctrl_int_col_msk1
a 28 R/W secenc_base_sys_ctrl_int_col_msk2
b 2c R/W secenc_base_sys_ctrl_int_col_msk3
c-ff 30-3fc -  reserved
100 400 R/W secenc_base_sys_ctrl_bsys_pwr_req
101 404 R secenc_base_sys_ctrl_bsys_pwr_st
102-1ff 408-7fc -  reserved
200 800 R/W secenc_base_sys_ctrl_clk_ctrl
201 804 R/W secenc_base_sys_ctrl_clk_div
202-27f 808-9fc -  reserved
280 a00 R secenc_base_sys_ctrl_clkforce_st
281 a04 W secenc_base_sys_ctrl_clkforce_set
282 a08 W secenc_base_sys_ctrl_clkforce_clr
283 a0c -  reserved
284 a10 R secenc_base_sys_ctrl_pll_st
285-3f3 a14-fcc -  reserved
3f4 fd0 R secenc_base_sys_ctrl_pid4
3f5 fd4 R secenc_base_sys_ctrl_pid5
3f6 fd8 R secenc_base_sys_ctrl_pid6
3f7 fdc R secenc_base_sys_ctrl_pid7
3f8 fe0 R secenc_base_sys_ctrl_pid0
3f9 fe4 R secenc_base_sys_ctrl_pid1
3fa fe8 R secenc_base_sys_ctrl_pid2
3fb fec R secenc_base_sys_ctrl_pid3
3fc ff0 R secenc_base_sys_ctrl_cid0
3fd ff4 R secenc_base_sys_ctrl_cid1
3fe ff8 R secenc_base_sys_ctrl_cid2
3ff ffc R secenc_base_sys_ctrl_cid3

secenc_base_sys_ctrl_host_sys_rst_ctrl
SecEnc Host System Reset Control register
R/W
0x00000001
Address : 0x5008e000
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for Host System. 0b0: No reset requested, 0b1: Reset requested
0 "1"
cpuwait
CPU wait control.


secenc_base_sys_ctrl_host_sys_rst_st
SecEnc Host System Reset Status register
R
Address : 0x5008e004
Bits Name Description
31 - 3 -
 reserved
2 - 1 rst_ack
Status of reset request
Possible field values are:
00: No reset requested.
01: Reset request unable to complete.
10: Reset request complete.
11: Reserved.
0 -
 reserved


secenc_base_sys_ctrl_soc_rst_ctrl
SecEnc SoC Reset Control register
R/W
0x00000000
Address : 0x5008e008
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
rst_req
Reset request for SoC. 0b0: No reset requested, 0b1: Reset requested
0 0
-
 reserved


secenc_base_sys_ctrl_soc_rst_syn
SecEnc SoC Reset Syndrome register
R
Address : 0x5008e00c
Bits Name Description
31 sec_enc
Indicates the source of the last reset is captured in the se_rst_syn register in the secenc_sys_ctrl area.
30 - 4 -
 reserved
3 soc_wdog
Indicates the last reset of the SoC was caused by the SoC watchdog.
2 -
 reserved
1 nsrst
Indicates that the last reset of the SoC was caused by either:
- nSRST pin being asserted.
- DP ROM CSYSRSTREQ being asserted.
0 por
Indicates that the last reset of the SoC was caused by either:
- POR_N pin being asserted.
- DP CDBGRSTREQ being asserted.
- SOC_RST_CTRL.RST_REQ bit set to 1.


secenc_base_sys_ctrl_int_col_st0
SecEnc Base system Interrupt Collator Status 0 register
R
Address : 0x5008e010
Bits Name Description
31 - 0 ssi_st
Status of the Secure Enclave Expansion Interrupt (SEEI) 0-31 after the respective mask field from sec_enc_int_col_msk0 register has been applied.
seei0 assigned to bit[0]: 0b0: Interrupt is de-asserted, 0b1: Interrupt is asserted


secenc_base_sys_ctrl_int_col_st1
SecEnc Base system Interrupt Collator Status 1 register
R
Address : 0x5008e014
Bits Name Description
31 - 0 ssi_st
Status of the Secure Enclave Expansion Interrupt (SEEI) 32-63 after the respective mask field from sec_enc_int_col_msk1 register has been applied.
seei32 assigned to bit[0]: 0b0: Interrupt is de-asserted, 0b1: Interrupt is asserted


secenc_base_sys_ctrl_int_col_st2
SecEnc Base system Interrupt Collator Status 2 register
R
Address : 0x5008e018
Bits Name Description
31 - 0 ssi_st
Status of the Secure Enclave Expansion Interrupt (SEEI) 64-95 after the respective mask field from sec_enc_int_col_msk1 register has been applied.
seei64 assigned to bit[0]: 0b0: Interrupt is de-asserted, 0b1: Interrupt is asserted


secenc_base_sys_ctrl_int_col_st3
SecEnc Base system Interrupt Collator Status 3 register
R
Address : 0x5008e01c
Bits Name Description
31 - 0 secenc_base_sys_ctrl_int_col_st3


secenc_base_sys_ctrl_int_col_msk0
SecEnc Base system Interrupt Collator Mask 0 register
R/W
0x00000000
Address : 0x5008e020
Bits Reset value Name Description
31 - 0 0x0
ssi_msk
Configures whether Secure Enclave Expansion Interrupt (SEEI) 0-31 generates an interrupt to the Secure Enclave Cortex-M0+ core, with SEEI0 assigned to bit[0].
bit[0]: 0b0: Interrupt is unmasked, 0b1: Interrupt is masked


secenc_base_sys_ctrl_int_col_msk1
SecEnc Base system Interrupt Collator Mask 1 register
R/W
0x00000000
Address : 0x5008e024
Bits Reset value Name Description
31 - 0 0x0
ssi_msk
Configures whether Secure Enclave Expansion Interrupt (SEEI) 32-63 generates an interrupt to the Secure Enclave Cortex-M0+ core, with SEEI32 assigned to bit[0].
bit[0]: 0b0: Interrupt is unmasked, 0b1: Interrupt is masked


secenc_base_sys_ctrl_int_col_msk2
SecEnc Base system Interrupt Collator Mask 2 register
R/W
0x00000000
Address : 0x5008e028
Bits Reset value Name Description
31 - 0 0x0
ssi_msk
Configures whether Secure Enclave Expansion Interrupt (SEEI) 32-63 generates an interrupt to the Secure Enclave Cortex-M0+ core, with SEEI32 assigned to bit[0].
bit[0]: 0b0: Interrupt is unmasked, 0b1: Interrupt is masked


secenc_base_sys_ctrl_int_col_msk3
SecEnc Base system Interrupt Collator Mask 3 register
R/W
0x00000000
Address : 0x5008e02c
Bits Reset value Name Description
31 - 0 0
secenc_base_sys_ctrl_int_col_msk3


secenc_base_sys_ctrl_bsys_pwr_req
SecEnc Base system power request registers
R/W
0x00000000
Address : 0x5008e400
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 3 "000"
systop_pwr_req
Select SYSTOP power domain behaviour when no activity in the domain:
0b000: No request for logic or volatile memory to be powered.
0b001: No request for logic to be powered, but volatile memory must be retained.
0b01x: Request for logic to be powered, but volatile memory can be either powered or retained.
0b1xx: Request for logic and volatile memory to be powered.
2 "0"
dbgtop_pwr_req
Select DBGTOP power domain behaviour when no activity in the domain:
0b0: No request for DBGTOP to be powered
0b1: Request for DBGTOP to be powered
1 "0"
refclk_req
Request REFCLK:
0b0: No request for REFCLK to be supplied
0b1: Request for REFCLK to be supplied
0 "0"
wakeup_en
Secure Enclave wakeup enable:
0b0: Wakeup for Secure Enclave is disabled
0b1: Wakeup for Secure Enclave is enabled


secenc_base_sys_ctrl_bsys_pwr_st
SecEnc Base system power status registers
R
Address : 0x5008e404
Bits Name Description
31 - 6 -
 reserved
5 - 3 systop_pwr_st
SYSTOP power domain status:
0b000: SYSTOP is in the OFF or WARM_RST power mode
0b001: SYSTOP is in the MEM_RET power mode
0b010: SYSTOP is in the FUNC_RET power mode
0b100: SYSTOP is in the ON power mode
All other values are Reserved
2 dbgtop_pwr_st
DBGTOP power domain status:
0b0: DBGTOP is in the OFF or WARM_RST power mode
0b1: DBGTOP is in the ON-power mode
1 - 0 -
 reserved


secenc_base_sys_ctrl_clk_ctrl
SecEnc clock control register
R/W
0x00000001
Address : 0x5008e800
Bits Reset value Name Description
31 - 24 "00000000"
entry_delay
Configure number of idle clock cycles before clock is gated
23 - 16 0
-
 reserved
15 - 8 "00000000"
clkselect_cur
Currently selected clock source for SECENCCLK:
0x00: Clock gate
0x01: SECENCREFCLK
0x02: SYSPLL
All other values are Reserved.
7 - 0 "00000001"
clkselect
Select the clock source for SECENCCLK:
0x00: Clock gate
0x01: SECENCREFCLK
0x02: SYSPLL
All other values are Reserved.
Selecting a value which is Reserved can cause a deadlock.


secenc_base_sys_ctrl_clk_div
SecEnc clock divider register
R/W
0x00000000
Address : 0x5008e804
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 16 "00000"
clkdiv_cur

15 - 5 0
-
 reserved
4 - 0 "00000"
clkdiv



secenc_base_sys_ctrl_clkforce_st
SecEnc clock force status register
R
Address : 0x5008ea00
Bits Name Description
31 - 1 -
 reserved
0 secencclk_force_st
Status of SECENCCLK clock force:
0b0: High-level clock gating is enabled
0b1: High-level clock gating is disabled


secenc_base_sys_ctrl_clkforce_set
SecEnc clock force set register
W
0x00000000
Address : 0x5008ea04
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
secencclk_force_set
Set secenc_force_st in clkforce_st register
Writing a value of 0b0 has no effect. This field always reads as 0b0.


secenc_base_sys_ctrl_clkforce_clr
SecEnc clock force clear register
W
0x00000000
Address : 0x5008ea08
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
secencclk_force_clr
Clear secenc_force_st in clkforce_st register
Writing a value of 0b0 has no effect. This field always reads as 0b0.


secenc_base_sys_ctrl_pll_st
SecEnc PLL status register
R
Address : 0x5008ea10
Bits Name Description
31 - 1 -
 reserved
0 sysplllock_st
Status of the SYSPLLLOCK input. 0b0: PLL is not locked. 0b1: PLL is locked.


secenc_base_sys_ctrl_pid4
Peripheral ID Register 4
R
Address : 0x5008efd0
Bits Name Description
31 - 8 -
 reserved
7 - 4 size
Number of 4KB occupied by the block. This field is deprecated.
3 - 0 des_2
JEP Continuation


secenc_base_sys_ctrl_pid5
Peripheral ID Register 5
R
Address : 0x5008efd4
Bits Name Description
31 - 0 secenc_base_sys_ctrl_pid5


secenc_base_sys_ctrl_pid6
Peripheral ID Register 6
R
Address : 0x5008efd8
Bits Name Description
31 - 0 secenc_base_sys_ctrl_pid6


secenc_base_sys_ctrl_pid7
Peripheral ID Register 7
R
Address : 0x5008efdc
Bits Name Description
31 - 0 secenc_base_sys_ctrl_pid7


secenc_base_sys_ctrl_pid0
Peripheral ID Register 0
R
Address : 0x5008efe0
Bits Name Description
31 - 8 -
 reserved
7 - 0 part_0
Bits [7:0] of part ID


secenc_base_sys_ctrl_pid1
Peripheral ID Register 1
R
Address : 0x5008efe4
Bits Name Description
31 - 8 -
 reserved
7 - 4 des_0
Bits [3:0] of JEP 106 Identity
3 - 0 part_1
Bits [11:8] of part ID


secenc_base_sys_ctrl_pid2
Peripheral ID Register 2
R
Address : 0x5008efe8
Bits Name Description
31 - 8 -
 reserved
7 - 4 revision
Major revision of the block
3 jedec
Indicates the use of JEDEC JEP106 identification scheme
2 - 0 des_1
Bits [6:4] of JEP 106 Identity


secenc_base_sys_ctrl_pid3
Peripheral ID Register 3
R
Address : 0x5008efec
Bits Name Description
31 - 8 -
 reserved
7 - 4 revand
Minor revision number of the block
3 - 0 cmod
Customer modification number


secenc_base_sys_ctrl_cid0
Component ID Register 0
R
Address : 0x5008eff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble 0


secenc_base_sys_ctrl_cid1
Component ID Register 1
R
Address : 0x5008eff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Class of the component
3 - 0 prmbl_1
Preamble 0


secenc_base_sys_ctrl_cid2
Component ID Register 2
R
Address : 0x5008eff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble 2


secenc_base_sys_ctrl_cid3
Component ID Register 3
R
Address : 0x5008effc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble 3



Base Address Area: secenc_secenc_ram_ctrl, secenc_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_5_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_5_mbist_power1
2-1ff 8-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_5_ecc0
201 804 R/W gen_ram_ctrl_netx22xx_5_ecc1
202-27f 808-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_5_ecc_status_corr0
281 a04 R gen_ram_ctrl_netx22xx_5_ecc_status_corr1
282-2ff a08-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_5_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_netx22xx_5_ecc_status_noncorr1
302-37f c08-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_5_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_5_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_5_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_5_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_5_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_5_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i0 (98304x32 bits excluding any BIRA redundancy, BIST type BIRA)
This logical RAM is always on (HDL parameter).
R/W
0x000000a0
Address@secenc_secenc_ram_ctrl : 0x50091000
Address@secenc_ram_ctrl : 0x50091000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the shutdown mode register has no effect.
6 "0"
sleep
Sleep mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the sleep mode register has no effect.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_5_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i1 (32768x32 bits excluding any BIRA redundancy, BIST type BIST)
This logical RAM is always on (HDL parameter).
R/W
0x000000a0
Address@secenc_secenc_ram_ctrl : 0x50091004
Address@secenc_ram_ctrl : 0x50091004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the shutdown mode register has no effect.
6 "0"
sleep
Sleep mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the sleep mode register has no effect.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_5_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i0 (98304x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091800
Address@secenc_ram_ctrl : 0x50091800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_5_ecc1
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i1 (32768x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091804
Address@secenc_ram_ctrl : 0x50091804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_5_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i0 (98304x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@secenc_secenc_ram_ctrl : 0x50091a00
Address@secenc_ram_ctrl : 0x50091a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_5_ecc_status_corr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i1 (32768x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@secenc_secenc_ram_ctrl : 0x50091a04
Address@secenc_ram_ctrl : 0x50091a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_5_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i0 (98304x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@secenc_secenc_ram_ctrl : 0x50091c00
Address@secenc_ram_ctrl : 0x50091c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_5_ecc_status_noncorr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.top_sse710_r0_aontop_i.u_pd_secenc_f1_top.u_secenc_f1_sepd.u_secenc_f1_core.u_sec_mem_integration.u_secenc_f1_ram_wrapper.gen_ram_hsoc_i1 (32768x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address@secenc_secenc_ram_ctrl : 0x50091c04
Address@secenc_ram_ctrl : 0x50091c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_5_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091e00
Address@secenc_ram_ctrl : 0x50091e00
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_5_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_5_irq_raw_reg0).
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091e40
Address@secenc_ram_ctrl : 0x50091e40
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_5_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_5_irq_raw_reg0
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091e80
Address@secenc_ram_ctrl : 0x50091e80
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_5_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 6 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_1_err_ecc_non_correctable
  2 : irq_reg0-mem_0_err_ecc_correctable
  3 : irq_reg0-mem_1_err_ecc_correctable
  4 : irq_reg0-mem_0_mbist_or_init_finished
  5 : irq_reg0-mem_1_mbist_or_init_finished
  6 : no active IRQ
R/W
0x00000000
Address@secenc_secenc_ram_ctrl : 0x50091ec0
Address@secenc_ram_ctrl : 0x50091ec0
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
4 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
3 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
2 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_5_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address@secenc_secenc_ram_ctrl : 0x50091efc
Address@secenc_ram_ctrl : 0x50091efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: dpm0, dpm1

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W dpm_cfg0x0
1 4 R/W dpm_if_cfg
2 8 R/W dpm_pio_cfg0
3 c R/W dpm_pio_cfg1
4 10 R/W dpm_addr_cfg
5 14 R/W dpm_timing_cfg
6 18 R/W dpm_rdy_cfg
7 1c R dpm_status
8 20 R/W dpm_status_err_reset
9 24 R dpm_status_err_addr
a 28 R/W dpm_misc_cfg
b 2c R/W dpm_io_cfg_misc
c-d 30-34 -  reserved
e 38 R/W dpm_tunnel_cfg
f 3c R/W dpm_itbaddr
10 40 R/W dpm_win1_end
11 44 R/W dpm_win1_map
12 48 R/W dpm_win2_end
13 4c R/W dpm_win2_map
14 50 R/W dpm_win3_end
15 54 R/W dpm_win3_map
16 58 R/W dpm_win4_end
17 5c R/W dpm_win4_map
18-1f 60-7c -  reserved
20 80 R dpm_irq_raw
21 84 R/W dpm_irq_host_sirq_mask_set
22 88 R/W dpm_irq_host_sirq_mask_reset
23 8c R dpm_irq_host_sirq_masked
24 90 R/W dpm_irq_host_dirq_mask_set
25 94 R/W dpm_irq_host_dirq_mask_reset
26 98 R dpm_irq_host_dirq_masked
27-2d 9c-b4 -  reserved
2e b8 R/W dpm_sw_irq
2f bc R/W dpm_crc
30-36 c0-d8 -  reserved
37 dc R/W dpm_reset_request
38-3c e0-f0 -  reserved
3d f4 R dpm_netx_version_bigend16
3e f8 -  reserved
3f fc R dpm_netx_version

dpm_cfg0x0
DPM IO Control Register 0.
This register is accessible in any DPM-mode (8, 16 bit, SRAM, Intel, Motorola, little endian, big endian) by access to DPM address 0.
Basic DPM settings are configurable here to make higher addresses accessible.
To avoid instable system configurations, global changes of important configuration registers must be confirmed
(re)writing 'mode' bit field of this register. View 'mode' description for details.
R/W
0x00000000
Address@dpm0 : 0x60138400
Address@dpm1 : 0x60138500
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
endian
Endianess of 32 bit (DWord) address alignment (B0: least significant byte, B3: most significant byte):
coding   Address   A+3   A+2   A+1   A+0
  00   little endian   B3   B2   B1   B0
  01   16 bit big endian   B2   B3   B0   B1
  10   32 bit big endian   B0   B1   B2   B3
  11   reserved        

Little endian is used netX inside. If big endian host device is used, set to this 01 or 10 according to
host device data width.
3 - 0 "0000"
mode
Basic DPM interface mode:
Additionally writing to this bit field will confirm global interface configuration changes:
Interface configuration can not always be written one single access (e.g. in 8 bit data mode
changing of 'dpm_if_cfg' is not possible in one single access as there are more than 8 bits
for configuration). However changing interface configuration by more than one single access could
lead to instable interfaces. This is avoided by following procedure:
For proper interface configuration, values of important interface configuration
registers are buffered in temporary registers first. Interface configuration is changed
finally by (re)writing 'mode' bits. There is no need to really change a prior programmed 'mode'
setting, interface change is done when low byte of this registers is target of a write access.
Temporary registers which must be confirmed by this are:
- All bits of 'dpm_if_cfg' register.
Note:
   The address comparators and the 'addr_cmp_a*' bit fields in 'dpm_addr_cfg' of earlier netX versions
   were dropped since netX90
Note:
   Interface configuration confirm must be done regardless wether programmed by host via
   external interfaces or by internal ARM via internal INTLOGIC configuration channel.
DPM interface mode must be further configured in 'dpm_if_cfg' register. Data width and
address multiplexing mode must be configure here.
Supported basic DPM modes are:
0000 8 bit data non multiplexed mode.
DPM_D7..0 are used as data lines, DPM_D15..8 can be used as PIOs (+8 PIOs).
0001 reserved.
0010




8 bit data multiplexed mode.
DPM_D7..0 are used as address and data lines.
DPM_A7..0 and DPM_D15..8 can be used as PIOs (+16 PIOs).
DPM_A10..8 will used as address lines.
DPM_A19..11 can used as address lines (depending on selectde 'addr_range'.
High address lines will be sampled at the same time when lower address bits are
latched from DPM_D7..0.
0011 reserved.
0100 16 bit data non multiplexed mode.
DPM_D15..0 are used as data lines.
0101 reserved.
0110




16 bit data multiplexed mode with 2 byte-enables on separated lines.
DPM_D15..0 are used as address and data lines.
DPM_A15..0 can be used as PIOs (+16 PIOs).
Two byte-enable signals can be used additionally. View register 'dpm_if_cfg' 'be_sel'.
DPM_A17..16 can used as address lines (depending on selectde 'addr_range'.
High address lines will be sampled at the same time when lower address bits are
latched from DPM_D15..0.
0111 reserved
  : reserved.
1111 reserved.

Note:
   For DPM modes with less than 32 bit data, write data could not written immediate to netX memory or
   registers ('byte_area' and 'dis_rd_latch' of 'dpm_win1_map' register).


dpm_if_cfg
DPM interface configuration register.
DPM interface mode must be basically configured in 'dpm_cfg0x0' register. Interface configuration is
split up into two registers to support setup from external host CPU when DPM is in 8 bit non-multiplexed default mode after reset.
However this does not work for all interfaces. E.g. for modes where DPM_WRN is not write trigger this is not
possible. Interface setup must be done by netX internal CPU then.
To avoid instable system configurations, changes of this registers must be confirmed
(re)writing 'mode' bit field of dpm_cfg0x0 register. View 'mode' description there for details.
 Host connection  cs_ctrl  addr_sh  aen_pol  aen_sel  be_wr  be_rd  be_pol  be_sel  dir_ctrl  cfg_0x0.mode
           _dis  _dis        
 SRAM or Intel 8bit       0       x       x      0    x    x    x     0      0     0x0
 SRAM, 16bit,byte-enable       0       0       x      0    0    0    0     0      0     0x4
 SRAM, or Intel, 8bit multiplexed       0       x       1      2    x    x    x     0      0     0x2
 SRAM, 16bit mul. (netx50: Intel, no BEs)       0       0       1      2    1    1    x     0      0     0x6
 SRAM, 16bit mul. 2BEs, byte-addr       0       0       1      2    0    0    0     0      0     0x6
 SRAM, 16bit mul. 2BEs, word-addr       0       1       1      2    0    0    0     0      0     0x6
 Intel, 16bit,byte-write       0       0       x      0    0    1    0     1      1     0x4
 Intel, 16bit mul. byte-write       0       1       1      2    0    1    0     1      1     0x6
 TI OMAP, 16bit non-multiplexed       0       0       x      0    0    0    0     0      0     0x4
 TI OMAP, 16bit multiplexed       0       1       0      2    0    0    0     0      0     0x6
 Motorola, 8bit (6800)       0       x       x      0    0    0    1     1      2     0x0
 Motorola, 16bit       0       0       x      0    0    0    0     0      2     0x4
 Motorola, 16bit (68000)       0       0       0      2    0    0    0     0      2     0x4
 Motorola, 8bit multiplexed       0       x       x      0    0    0    1     1      2     0x2
 Motorola, 16bit mul.netx50: byte-addr       0       0       1      2    0    0    0     0      2     0x6
 Motorola, 16bit mul.word-addr       0       1       1      2    0    0    0     0      2     0x6
R/W
0x00000000
Address@dpm0 : 0x60138404
Address@dpm1 : 0x60138504
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 16 "000"
cs_ctrl
chip-select controlling.
 000: Use 1 low active chip-select signal (DPM_CSN).
 001: Use 2 low active chip-select signals (DPM_CSN or DPM_BHE1n must be low).
 010: Use high active chip-select signal (DPM_CSN).
 011: Use 2 high active chip-select signals (DPM_CSN or DPM_BHE1n must be high).
 100: No chip-select signal. Behaves like DPM_CSN is permanent active.
 111: Chip access is disabled.
 others: reserved
15 "0"
addr_sh
Address is Byte address or shifted according to selected data size.
This bit is irrelevant in 8 bit data modes.
 0
Address is always Byte address (not shifted).
In 16 bit data modes: Address bit 0 can be used as low byte-enable or can be ignored.
Use 'be_sel' to select byte-enables and 'be_wr_dis' or 'be_rd_dis' to ignore them.
 1 Address is shifted according to programmed data width.
In 16 bit data modes: Address from host starting at A0 (or AD0 when multiplexed ) is 16 bit word address.
14 "0"
aen_pol
Address-Enable active level polarity.
  0: Address is latched while ALE-signal is low (i.e. low active ALE/AEN).
  1: Address is latched while ALE-signal is high (i.e. high active ALE/AEN).
In non-multiplexed modes, address is only latched when chip-select is additionally active (as programmed
in 'cs_ctrl').
In multiplexed modes, address latching is not controlled by chip-select. Address is latched all time
when ALE is active then.
13 - 12 "00"
aen_sel
Address-Enable (AEN-modes) or Address-Latch-Enable (multiplexed modes) Control.
 00: No additional Address controlling function.
 01: reserved
 10: Address-Enable active.
 11: reserved.
Note:
   In multiplexed modes read or write access will not be started netX internally while address-phase
   is active. ALE signal must return to idle state first.
11 - 8 "0000"
be_pol
DPM access byte-enable active level polarity.
byte-enable active polarity can be set for each data byte separately. byte-enable signals
can be selected by 'be_sel'.
Bits inside this bit field are associated as follows:
 Bit   data lines
 be_pol[0]   D[7:0]
 be_pol[1]   D[15:8]

Function:
  0: BE signals are low active byte-enables.
  1: BE signals are high active byte-enables (e.g. 8 bit Motorola 6800).
7 "0"
be_wr_dis
DPM write access byte-enable configuration.
  0: byte-enables will be used on write access, only data lines of enabled bytes will be written.
  1: byte-enables will be ignored on write access, all used data lines will be written.
Note:
   Do not set this bit when 'dir_ctrl' is set to nWR-mode ('01'). Byte-Write-Strobes are essentially in this case.
Note:
   This bit is ignored for 8 bit data modes when 'be_sel' bit is not set.
6 "0"
be_rd_dis
DPM read access byte-enable configuration.
  0: byte-enables will be used on read access, only data lines of enabled bytes will be driven.
  1: byte-enables will be ignored on read access, all used data lines will be driven.
Note:
   Do not set this bit when 'dir_ctrl' is set to nRW-mode ('10'). Byte-Write-Strobes are essentially in this case.
Note:
   This bit is ignored for 8 bit data modes when 'be_sel' bit is not set.
5 0
-
 reserved
4 "0"
be_sel
DPM access byte-enable signal selection.
Basically BE signals depend on selected data width (cfg0x0).
setting  data width  D[15:8]  D[7:0]
      0   8bit    -
      0  16bit  BHE1n  A0
--------- ------------- ----------- ----------
      1   8bit    BHE1n
      1  16bit  WRHn  WRn

Note:
   WRHn is the signal name for DPM versions with 16 data bus width. It is equivalent with BHE3n for
   DPM implementations with 32 bit data bus width.
Note:
   For 8 bit data modes this bit must only be set when an additional
   byte-enable Signal is required (e.g. Motorola 6800). Do not set 'be_sel' and ignore
   for read and write (be_wr_dis, be_rd_dis) - DPM Ready generation will care
   for BHE1n anyhow.
Note:
   Internal read access data width is always 32 bit.
3 - 2 0
-
 reserved
1 - 0 "00"
dir_ctrl
DPM access direction control.
 00:






dedicated low active read- and write control signals (RDn + WRn) with optional byte-enables.
byte-enables have address character i.e. they must be stable while read- or write-control
signal is active. byte-enables are not used as Strobe signals.
A read-access is started when RDn signal becomes active low at access start. Address, chip-select and
byte-enable signals must be stable then.
A write-access is done when WRn becomes inactive high at access end. Address, chip-select, data and
byte-enable signals must be stable then.
Ready/Busy signal is asserted when RDn or WRn is active.
This setting can be used for standard SRAM interfaces.
 01:







RDn is direction signal nRW (signal high: write, low: read).
For read byte-enables have address character i.e. they must be stable when RDn becomes low.
For write byte-enables have strobe character i.e. Address, Data and RDn must be stable when they
become inactive at access end..
A read-access is started when RDn signal becomes low at access start. Address, chip-select and
byte-enable signals must be stable then.
A write-access is done when byte-enables becomes inactive at access end. Address, chip-select, data and
RDn signals must be stable then.
Ready/Busy signal is asserted when RDn is low or byte-enables are active.
This setting is typically used for Intel-like interfaces with Byte-Write-Strobe signals..
 10:



RDn is direction signal nWR (signal low: write, high: read).
byte-enables have strobe character for both read and write i.e. Address, and RDn must be stable when they
become active at access start. These signals must remain stable until byte-enables become inactive
at access end. For write data must be stable then.
Ready/Busy signal is asserted when at least one byte-enables is active.
This setting is typically used for Motorola-like interfaces with Byte-Write-Strobe signals.


dpm_pio_cfg0
DPM PIO Configuration Register0.
Signals to be used as PIOs when netX DPM is active must be selected here or in 'dpm_pio_cfg1' register. Since netx56
PIO function will not be automatically activated depending on other settings. E.g. DPM_D15..8 can not be used
automatically when 8 bit data mode is selected.
R/W
0x00000000
Address@dpm0 : 0x60138408
Address@dpm1 : 0x60138508
Bits Reset value Name Description
31 - 0 0x0
sel_d_pio
Use related DPM_D-pin as PIO pin.


dpm_pio_cfg1
DPM PIO Configuration Register1.
PIO usage of DPM_SIRQ, DPM_DIRQ and DPM_RDY has moved from 'dpm_io_cfg_misc' to this register since netx56.
Signals to be used as PIOs when netX DPM is active must be selected here or in 'dpm_pio_cfg0' register.
R/W
0xe0000000
Address@dpm0 : 0x6013840c
Address@dpm1 : 0x6013850c
Bits Reset value Name Description
31 "1"
sel_sirq_pio
Use DPM_SIRQ-pin as PIO pin.
Note:
   For serial DPM (HIF_B_MUX selection) this bit is related to HIF_A11(DPM0) or HIF_A13(DPM1). Setting of for HIF_A11/HIF_A13
   inside 'dpm_pio_cfg1 register is ignored then. I.e. this bit must be programmed
   to '0' for DPM_SIRQ/FIQ usage regardless whether serial or parallel DPM is used.
30 "1"
sel_dirq_pio
Use DPM_DIRQ-pin as PIO pin.
Note:
   For serial DPM this bit is related to HIF_DIRQ(DPM0) or HIF_D3(DPM1). Setting of for HIF_D3
   inside 'dpm_pio_cfg0 register is ignored then. I.e. this bit must be programmed
   to '0' for DPM_DIRQ/IRQ usage regardless whether serial or parallel DPM is used.
29 "1"
sel_rdy_pio
Use DPM_RDY-pin as PIO pin. RDY is by default PIO to avoid RDY-conflicts during reset.
28 "0"
sel_wrn_pio
Use DPM_WRN-pin as PIO pin.
27 "0"
sel_rdn_pio
Use DPM_RDN-pin as PIO pin.
26 "0"
sel_csn_pio
Use DPM_CSN-pin as PIO pin.
25 "0"
sel_bhe3_pio
Use DPM_WRHN as PIO pin.
Note:
   Depending on the implementation of the DPM interface WRHn equivalent with BHE3n.
   The Bit here is always named 'sel_bhe3_pio' although the IO function is named DPM_WRHN.
24 "0"
sel_bhe1_pio
Use DPM_BHE1-pin as PIO pin.
23 - 20 0
-
 reserved
19 - 0 0x0
sel_a_pio
Use related DPM_A-pin as PIO pin.
Note:
   PIO selects for DPM_A19..18 are only used for test purpose here. To select PIO function
   of high DPM_A lines which are multiplexed on DPM_D15..14 use related bits of 'sel_d_pio'
   Bit field in 'dpm_pio_cfg0' register.


dpm_addr_cfg
DPM External Address Configuration Register.
R/W
0x00000002
Address@dpm0 : 0x60138410
Address@dpm1 : 0x60138510
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
cfg_win_addr_cfg
Location of the DPM Configuration Window (Window 0).
Supported settings are:
 00: Low Configuration Window: The Configuration Window is located in the first 256 bytes of external DPM address
range (0x0 to 0xff). It is located before the first enabled Data Window (1 to 4).
 01: High Configuration Window: The Configuration Window is located in the last 256 bytes of external DPM address
range.
     Example: 'addr_range' is 8kB: Configuration Window is located in 0x1F00..0x1FFF.
 10: reserved.
 11: Configuration Window is disabled for external DPM access. Full DPM address
range can be used for Windows 1 to 4.
Note:
  The Configuration Window 0 has higher priority than normal DPM Window. The location of the Configuration Window
  does not depend on the Data Window configuration (the setting of the 'dpm_winX_end' or 'dpm_winX_map' registers).
  I.e. for setting '00' (low Configuration Window) the first enabled Data Window starts at address 0x100. For
  setting '01' (high Configuration Window) it would hide the last 256 bytes of the last enabled Data Window when
  this is configured to end on the last external address.
  The Configuration Window 0 has lower priority than Access Tunnel. I.e. the Access Tunnel could be laid over
  the configuration window.
3 - 0 "0010"
addr_range
DPM external address range.
coding Byte Address range address used signals
 0000 reserved  
 0001 reserved  
 0010 2KB address range DPM_A[10:0]
 0011 4KB address range DPM_A[11:0]
 0100 8KB address range DPM_A[12:0]
 0101 16KB address range DPM_A[13:0]
 0110 32KB address range DPM_A[14:0]
 0111 64KB address range DPM_A[15:0]
 1000 128KB address range DPM_A[16:0]
 1001 256KB address range DPM_A[17:0]
  : reserved  
 1111 reserved  

Following settings are only valid for 8 bit multiplexed/non-multiplexed data mode.
coding Byte Address range address used signals
 1010 512KB address range HIF_D14, DPM_A[17:0]
 1011 1024KB address range HIF_D[15:14], DPM_A[17:0]
  : reserved  
 1111 reserved  

This setting is related to Byte address. I.e. it is not possible to expand address rage
by setting the 'addr_sh' bit inside the 'dpm_if_cfg' register. However required address lines
will decrease by 1 for 16 bit data mode when the 'addr_sh' bit is set.

For multiplexed modes:
If programmed address range exceeds number of data lines, high address bits will be sampled
from DPM_A lines starting above last used data line. High address will be sampled at the same moment
when low address bits are sampled from data lines.
Example 1:
8 bit data multiplexed mode, 64KB address range programmed and 'aen_pol' is set to 0:
Address bits A7..0 are sampled from DPM_D7..0 before DPM_ALE is released to 1. Address bits A15..8
are sampled from DPM_A15..8 also before DPM_ALE is released to 1.
Example 2:
16 bit data multiplexed mode, 64KB address range programmed, 'aen_pol' is set
to 0 and 'addr_sh' is set to 1:
Address bits A15..1 are sampled from DPM_D14..0 before DPM_ALE is released to 1.
I.e. a 16 bit word address is
carried on DPM_D14..0 and is left-shifted internally by 1 to resolve a byte address.


dpm_timing_cfg
(dpm_access_cfg)
DPM timing and access configuration register.
R/W
0x0000003d
Address@dpm0 : 0x60138414
Address@dpm1 : 0x60138514
Bits Reset value Name Description
31 "0"
sdpm_miso_early
Serial DPM early MISO (read-data) generation.
Serial DPM based on standard SPI changes read data on the edge following the sampling clock edge, i.e.
works on both serial clock edges. That avoids hold timing errors on MISO-data but decreases
maximum serial data rate on the other hand. Hence, for fast serial data rates this bit must be set.
MISO hold times will always be positive but could get very short then. For details view netX
timing characteristics.
 0: Change MISO on the clock edge following the sampling edge.
 1: Change MISO on the sampling edge.
Note:
   Sampling and generating clock edges are determined by serial DPM mode (clock phase and polarity).
   Related configuration must be done outside DPM module.
Note:
   Hold timings can be relaxed by decreasing serial clock rate when this bit is not set. When this
   bit is set, MISO hold timing does not depend on serial clock rate.
Note:
   This is a new netx56 feature.
30 "0"
en_dpm_serial_sqi
When DPM is in serial mode ('dpm_status.sel_dpm_serial' active), serial DPM
can be switched to SQI-compatible 4-bit mode.
Note:
   Netx DPM changes serial configuration immediately when this bit is changed. Hence
   do not change this bit by a longer serial sequence from host.
   E.g.: Change from SPI to SQI from host-side when host:
   1.: Set this bit by SPI write sequence from host.
   2.: Terminate sequence after the byte containing this bit was written.
   3.: Ensure that host has completed writing this byte serially (host transfer could last
even when related commands are already finished, e.g. due to FIFOs inside host SPI module).
   4.: Change host to SQI.
   5.: Continue accessing netX DPM in SQI mode.
Note:
   This bit has no effect when DPM is in parallel mode.
Note:
   This is a new netx56 feature.
29 - 9 0
-
 reserved
8 "0"
rd_burst_en
Read burst enable.
Read bursts are subsequent read accesses without toggling chip-select or read-enable in between.
They are supported for non-multiplexed modes only.
7 - 4 "0011"
t_rds
Read data setup time (in steps of 6ns; default: 18ns).
For parallel DPM:
If DPM_RDY-signal is used (rdy_mode != 0), ready-state is generated t_rds*6ns after read data is stored on data bus.
Without using the DPM_RDY-signal (rdy_mode == 0) read access error is detected if access terminates before t_rds*6ns
passed after read data generation.
Valid settings for parallel DPM are: 0..15.
Note:
   The read-data-access-time will increased by t_rds * 6ns if t_rds is not 0.
Note:
   For compatibility to other netX devices it is not recommended to use values > 10.
For serial DPM (since final netX90):
t_rds defines the guaranteed setup time of the first bit of serial read data before its sampling clock edge (MISO
before sampling edge of SCK). By default (t_rds=3) the first bit of serial read data might become valid on MISO
shortly befor the sampling edge of SCK (t_SPMOS, typically some nanoseconds, refer to the detailed IO-timing
description of the serial DPM). If the serial read data becomes valid later, a rd_err is detected (register dpm_status).
Typically t_SPMOS is sufficient. However, for serial masters requiring a longer  setup time, t_rds can be used to
shift the access-error-detection to an earlier point of time in steps of 6ns: The rd_err-state will be detected if the serial-read-data
is not generated at least t_SPMOS + (t_rds-2)*6ns before the sampling clock edge. Hence t_rds does not really provide
a longer setup time but it allows to detect accesses with too short setup-times and provides the possibility
to repeat them (similar to parallel DPM without DPM_RDY-signal).
Valid settings for serial DPM are: 2..7. The recommended value is 3.
Note:
   It makes no sense to set t_rds in a way that leads to a setup-time larger than the half serial period. The serial
   clock rate must be reduced then additionally.
3 "1"
filter
Filter DPM Control Signals.
If this bit is set, DPM signals chip-select, Read-Enable and Write-Enable (and Address latch enable if multiplexed
Parallel DPM modes are used) are filtered for spike suppression.
 0: no spike suppression.
 1: Spikes < 6ns are suppressed, read data access time increased by 6ns.
Note:
   Data, address and byte-enable inputs are not filtered and must be stable when sampled. I.e. during
   the last 20ns of a write access and at the first 10ns of read access start.
Note:
   Read data access time is increased by 6ns if this bit is set.
2 - 0 "101"
t_osa
Address Setup Time (t_osa * 6ns; default 30ns).
Address sampling can be delayed for read and write accesses by this parameter.
E.g. host device asserts chip-select, Read-Enable and address lines simultaneously but
some address lines are not stable while chip-select and Read-Enable are both low, set t_osa
to delay address sampling by t_osa * 6ns.
When data direction is controlled by RDn line ('if_cfg.dir_ctrl' not '00') and byte-enables are used
for read ('if_cfg.be_rd_dis' not set), a read access is initiated when active byte-enable signals
are detected stable for t_osa netX clock periods.
Valid settings are: 0..7.
Note:
   Read data access time will increased by t_osa * 6ns if t_osa is not 0.
Note:
   For compatibility to other netX devices it is not recommended to use values > 5.


dpm_rdy_cfg
DPM Ready (DPM_RDY) Signal Configuration Register.
R/W
0x00000001
Address@dpm0 : 0x60138418
Address@dpm1 : 0x60138518
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 4 "00"
rdy_to_cfg
Ready Timeout Configuration.
Ready Timeout detection can controlled this bit. For further information
see description of rdy_to_err bit of dpm_status register.
00: Ready Timeout after 2048 netX system clock cycles (i.e. 12.34us)
01: Ready Timeout after 256 netX system clock cycles (i.e. 1.54us)
10: reserved
11: Ready Timeout disabled.
The value programmed here is ignored for serial DPM with stream-type 'ready-polling'. In this mode
no ready-timeout will be generated to avoid additional status checking. A ready-polling timeout
counter should be implemented in serial DPM host application.
Note:
   The system clock of netx22xx runs with 166MHz.
Note:
   This is a new netx56 feature.
3 "0"
rdy_sig_mode
Ready signal mode.
1:

DPM_RDY is generated as ready/acknowledge pulse.
In this mode, DPM_RDY is only in active state at access end to sign that host device is allowed to finish the
current access. If no access to DPM is done or if host device runs DPM access but is not allowed to finish it yet,
DPM_RDY will remain in inactive state.
0:

DPM_RDY is generated as wait/busy state signal.
In this mode, DPM_RDY becomes active at access start and will remain active while host device is not allowed to finish the
current access. If no access to DPM is done or if host device runs DPM access and allowed to finish it and continue
access generation, DPM_RDY will be in inactive state.
2 - 1 "00"
rdy_drv_mode
Ready generation mode.
00: ready signal generation is disabled (High-Impedance mode).
01: ready is driven when active and inactive. Never highZ. (Push-Pull mode)
10:




ready is driven when active and for a short time when inactive-phase starts for fast
busy to ready signal state change (Sustain-Tristate mode).
Inactive-phase ready driving time (tRPm02, tRPm12) depends on rdy_sig_mode:
For rdy_sig_mode=0 this time (tRPm02) is 6ns.
For rdy_sig_mode=1 this time (tRPm12) depends on programmed input signal
filtering (register dpm_timing_cfg bit filter): If filtering is disabled tRPm12 is 12ns to 18ns,
if input filtering is enabled,  tRPm12 is 18ns to 24ns.
11: ready is only driven when cycle active (Open-Drain/Open-Source mode).
Note:
      Mode 2 and 3 are reordered in comparison to netX100/500/50.
0 "1"
rdy_pol
Ready signal ready-state polarity.
1: DPM is ready when external RDY-signal is high.
0: DPM is busy when external RDY-signal is high.


dpm_status
DPM Status Register.
DPM access errors can generate IRQ for host device (view DPM IRQ registers further down). For
error handling, the address an error occurred with is logged in dpm_status_err_addr register. Error bits can be cleared by
access to dpm_status_err_reset register.
Note


 for 'bus_conflict_rd_addr_err', 'bus_conflict_rd_err' and 'bus_conflict_wr_err':
Bus-conflict error detection is basically implemented as debug feature. Detected errors could be result of hazardous signals, incorrect configured DPM mode or not supported host interfaces. However there could some be some applications where error detection is too strict (see description of 'dis_bus_conflict_err_detect' of 'dpm_misc_cfg'). For that reason bus-conflict error behaviour can be controlled by 'dis_bus_conflict_err_detect' of 'dpm_misc_cfg' register. However, status bits inside this register (and inside 'dpm_status_err_reset') will always be set when an error was detected.
When error detection is enabled ('dis_bus_conflict_err_detect' is not set), an error-access will be aborted (ready-signal will be set to ready state when used) and DPM will wait for idle bus (dir_mode==0: deselected or read and write control signal inactive, dir_mode!=0: deselected or all byte-enables inactive). The error IRQ ('dpm_err') will be asserted. Read data of related access will be invalid and write data will be junked.
When error detection is disabled ('dis_bus_conflict_err_detect' is set) bus-conflict errors do not assert the 'dpm_err' IRQ, erroneous access will not be aborted and DPM will not wait for bus idle state. I.e. the erroneous access will be finished as read or write. However consequences of an error access are not predictable: Read or write data or address could be invalid.
Error detection is disabled by default after power on and must be enabled before usage.
Note

 for 'rdy_to_err', 'wr_err' and 'rd_err':
These errors are basically set when an host access is too fast to be handled by netX internally. NetX internal access times depend on target address area. However there are some address areas where other netX modules have higher access priority than DPM. Fore these address areas access times could become unpredictable (depending on application running netX inside). Especially when using host devices without ready-signal handshaking (i.e. also serial DPM) where netX access times could not be met under all conditions error detection handling becomes mandatory. It is recommended to check for errors after each access. In error-case the last access must be repeated. If an error occurs permanently the host must stretch external DPM access by inserting wait states. For all other DPM connections this error detection should only be a debug feature.
Behaviour of 'wr_err' and 'rd_err' can be additionally controlled by 'dis_access_err_halt' of 'dpm_misc_cfg' register: When error detection is enabled ('dis_access_err_halt' is not set), all read-access after occurrence of a read-error and all write-access after occurrence of a write-error will be ignored. Error states must be reset first before new accesses are performed internally. This is implemented to protect netX from unpredictable results of access errors. However some applications always require access to netX internal address area (e.g. as DPM configuration window 0 for error handling was disabled). For this purpose error-detection could be disabled.
DPM error IRQ ('dpm_err') and error-status flags will always be set in error case independent of 'dis_access_err_halt'. Error detection is disabled by default after power on and must be enabled before usage.
Note:  Errors could be avoided by programming input filtering, burst support or timing. That can be configured by dpm_timing_cfg register.
Note:  Serial DPM status send on the first byte of a serial access by netX is reordered and bus_conflict-errors are omitted (as they are related to parallel DPM only). Serial DPM status byte is transferred MSB first and contains following information (serial DPM protocol was completely revised for netx56 and this is a new netx56 feature):
 bit of first serial byte status information
            7 (MSB)                  0
            6                  0
            5          abort_err
            4     sel_dpm_serial
            3         rdy_to_err
            2             wr_err
            1             rd_err
            0 (LSB)           unlocked
Note:

The first serial transfer after reset is always ignored by the DPM module (due to initial synchronizations between the serial
and parallel part of the DPM module).

R
Address@dpm0 : 0x6013841c
Address@dpm1 : 0x6013851c
Bits Name Description
31 - 9 -
 reserved
8 abort_err
Abort error state (since netX90).
The internal netX-logic may return an abort response for an access. Reason could
be that the access is blocked by a firewall or it targets address area, which is not
available for the DPM. An aborted access means data failure: An aborted read access
will return invalid data. Data of an aborted write access is junked by the netX.
0: No access was aborted
1: An access was aborted (AHB HRESP returned ERROR). Data is lost.
7 sel_dpm_serial
Serial mode configuration state.
0: DPM is in parallel mode.
1: DPM is in serial mode.
Mode selection is done by hif_io_cfg register inside HIF_IO_CTRL address area.
Note:
   After enabling serial DPM 2 dummy read streams must be performed to initialize internal logic.
6 bus_conflict_rd_addr_err
Parallel DPM read access address change bus error detected.
This bit is set if address lines change (after filtering if enabled) during a read access while
burst support is not enabled. byte-enables are not included in this error-detection.
Note:
   For additional information view note in register description header.
5 bus_conflict_rd_err
Parallel DPM read access bus error detected.
This bit is set if a read access was started and signals change to write access states.
I.e. for dir_mode 0: Write-control (nWR) signal becomes active (low, after filtering if enabled)
during a read access.
I.e. for dir_mode 1: Direction line (nRD) signal changes to write (low, after filtering if enabled)
during a read access.
Note:
   For additional information view note in register description header.
4 bus_conflict_wr_err
Parallel DPM write access bus error detected.
This bit is set if a write access was started and signals change to read access states.
I.e. for dir_mode 0: Read-control (nRD) signal becomes active (low, after filtering if enabled)
during a write access.
I.e. for dir_mode 2: Direction line (nRD) signal changes to read (low, after filtering if enabled)
during a write access.
Note:
   For additional information view note in register description header.
3 rdy_to_err
DPM_RDY Timeout Error Status Flag.
This error could occur if host device tries to access permanently busy netX address area.
To avoid host device stalling DPM_RDY signal is releasedto ready state after
2048 or 256 system clock cycles at least.
1: Last access went to netX busy address and was broken to avoid host device stalling.
0: Access was finished successfully by DPM_RDY assertion to ready state.
Note:
   For additional information view note in register description header.
2 wr_err
DPM Write Error Status Flag.
Write errors occur if ready signal (DPM_RDY) is not respected by host device and
external DPM write access terminated before data could be stored.
In some cases certain netX address areas could be busy for not predictable time. If DPM_RDY is
not used, check for write error after write access to these areas.
In case of write error this bit is set immediately after the appropriate write access. Repeat
the write access until no error occurs.
1: The external DPM write access was too fast to store write data. Repeat the write access.
0: Write access terminated without error.
Note:
   For additional information view note in register description header.
1 rd_err
DPM Read Error Status Flag.
Read errors occur if ready signal (DPM_RDY) is not respected by host device and
external DPM read access terminated before read data could be asserted on the external DPM data
bus (view also t_rds in dpm_timing_cfg register).
In case of read error this bit is set immediately after the appropriate read access. Repeat the
read access until no error occurs.
1: The external DPM read access was too fast. Repeat the read access.
0: Read data OK.
Note:
   For additional information view note in register description header.
0 unlocked
DPM is locked during netX power up and boot phase.
DPM access to other addresses than DPM configuration window 0 cannot be done before this bit is
set to 1. Write access to data windows (netX AHB area) will be ignored and read access
will deliver invalid data while locked.
Poll for 1 after power-up or reset.


dpm_status_err_reset
DPM Error Status Reset Register.
Each flags can be reset by writing a '1' to it. For fast error detection for DPM interfaces without ready usage,
reset-on-read-function can be enabled for this register.

Note:
   If reset-on-read-function is enabled, this register must be read with a single access as bits are cleared
   immediately after the access. You should always use a byte access in this case.

Note:
   View dpm_status register for detailed error description.

Note:
   reset-on-read-function is controlled by enable_flag_reset_on_rd-bit in dpm_misc_cfg-register.

Note:
   In cases where internal access time is not predictable and host provides no
   ready function, it is recommended to enable reset-on-read-function. There is only one access
   necessary for error detection and clearing this flag then.
R/W
0x00000000
Address@dpm0 : 0x60138420
Address@dpm1 : 0x60138520
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
abort_err_rst
Abort error state (since netX90).
7 0
-
 reserved
6 "0"
bus_conflict_rd_addr_err_rst
Parallel DPM read access address change bus error detected.
5 "0"
bus_conflict_rd_err_rst
Parallel DPM read access bus error detected.
4 "0"
bus_conflict_wr_err_rst
Parallel DPM write access bus error detected.
3 "0"
rdy_to_err_rst
DPM_RDY timeout error.
2 "0"
wr_err_rst
DPM write error detection bit with auto reset function.
For fast read error detection this bit can be checked after each read access. If it was set, the read
access must be repeated.
1 "0"
rd_err_rst
DPM read error detection bit with auto reset function.
For fast write error detection this bit can be checked after each write access. If it was set, the write
access must be repeated.
0 0
-
 reserved


dpm_status_err_addr
DPM Error Address Status Register.
R
Address@dpm0 : 0x60138424
Address@dpm1 : 0x60138524
Bits Name Description
31 - 20 -
 reserved
19 - 0 err_addr
Access error address.
Address of first erroneous access. IRQ handler can use this value to repeat failed accesses after error
bits are set in dpm_status or dpm_status_err_reset register. However, only DPM Read Error (rd_err),
DPM Write Error (wr_err) and DPM_RDY Timeout Error (rdy_to_err) are cared for address logging.
This register is only valid if one of the error bits is set and should be read before error bits are cleared. If no error bit is set,
it is updated each access to the current address.
Note:
   Address status during bus conflict errors will not be logged. Bus conflict error status information
   is for debug purpose of unstable systems. Purpose of this register is primarily access error
   handling for systems without ready usage.


dpm_misc_cfg
DPM Configuration Register for some Special Functions.
R/W
0x00000006
Address@dpm0 : 0x60138428
Address@dpm1 : 0x60138528
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "1"
dis_bus_conflict_err_detect
This bit controls bus-error-detection.
When this bit is set, detected bus errors will only be flagged inside 'dpm_status' register
without further action. When this bit is cleared, dpm_error IRQ will be asserted and erroneous
accesses are terminated (or ignored) in error case additionally.
View also 'bus_conflict' status bits and description of 'dpm_status' register for details.
Note:
   This bit is set by default, but it is strongly recommended to clear it. However keeping
   this bit set could be helpful for debugging or when DPM configuration window 0 is disabled
   and not available for error handling.
Note:
   This bit could become necessary to be set for modes with direction signal
   where byte-enables change (nearly) simultaneously to direction signal (e.g. old Motorola 8bit CPUs).
   In this case DPM could detect an error at read access end when direction line is
   already sampled inactive while byte-enables are still sampled active.
Note:
   This is a new netx56 feature.
1 "1"
dis_access_err_halt
Disable halt after access-errors where detected.
When this bit is set access-error-detection ('rd_err', 'wr_err' and 'rdy_to_err' status bits
of 'dpm_status' register) will be set in error case but following accesses to netX internal
address area will not be blocked. Error IRQs will be generated.
Note:
   This bit is set by default, but it is strongly recommended to clear it. However keeping
   this bit set could be helpful for debugging or when DPM configuration window 0 is disabled
   and not available for error handling.
Note:
   IRQ 'dpm_err' is asserted in case of access-errors even when this bit is set.
Note:
   This is a new netx56 feature.
0 "0"
enable_flag_reset_on_rd
Enable Status Flag Reset by reading the 'dpm_status_err_reset' register.
When enable_flag_reset_on_rd-bit is set to '1', there is only one access necessary for
error detection and clearing the error status bits. In cases where internal access time is
not predictable and host provides no ready function, it is recommended to enable reset-on-read-function
to minimize traffic.


dpm_io_cfg_misc
DPM IO Configuration Register.
PIO usage of DPM_SIRQ, DPM_DIRQ and DPM_RDY has moved from this register to register'dpm_pio_cfg1' since netx56.
Signals which should be used as PIOs when netX DPM is active must be selected there.
R/W
0x000000a0
Address@dpm0 : 0x6013842c
Address@dpm1 : 0x6013852c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "1"
fiq_oec
FIQ/SIRQ output enable controlled.
0: FIQ/SIRQ signal is always driven.
1: FIQ/SIRQ signal is only driven when active. Inactive level must be realized by external pull-up or pull-down resistor.
6 "0"
fiq_pol
FIQ/SIRQ signal polarity.
0: FIQ/SIRQ is active low.
1: FIQ/SIRQ is active high.
5 "1"
irq_oec
IRQ output enable controlled.
0: IRQ/DIRQ signal is always driven.
1: IRQ/DIRQ signal is only driven when active. Inactive level must be realized by external pull-up or pull-down resistor.
4 "0"
irq_pol
IRQ/DIRQ signal polarity.
0: IRQ/DIRQ is active low.
1: IRQ/DIRQ is active high.
3 - 0 0
-
 reserved


dpm_tunnel_cfg
DPM Access Tunnel Configuration Register.
The DPM Access Tunnel (DATunnel) is a 64 byte (16DWord) address window which can be mapped on any 64 byte boundary of the external
visible address space. At the last DWord (offset 0x3C) of the DATunnel the Internal Target Base Address (ITBAddr) can be programmed.
This is the base address of the 64 byte tunnel target area inside the full 32-bit netX address range (however some address areas
could not be reachable as connections could be cut from the DPM inside the netX data-switch, refer to the data-switch documentation
of your netX).
By the DWords 0 to 14 of the tunnel the internal netX addresses starting at ITBAddr can be reached. The 'enable'-bit must be active
for this (read-only functionality can be configured by 'wp_data'-bit).
For access to netX data with ITBAddr DWord offset 15, the lower bits 5 to 2 of the programmed ITBAddr are interpreted as a mapping
value. This value will be added to the internal access address before tunnelling (wrapping around at the 64 byte boundary). Hence it
is possible to access always 15 of the 16 netX DWord while the one hidden by the ITBAddr can be selected by an appropriate mapping
value.
The ITBAddr can also be programmed by the 'dpm_itbaddr' register of the configuration window 0 (or the INTLOGIC area). The ITBAddr on
tunnel offset 0x3C can be write-protected by the 'wp_itbaddr'-bit. This could be useful to protect the NETX from reconfiguring the
tunnel from the host side but provides the host the internal NETX destination address anyhow. However this only makes sense when
the configuration window 0 is disabled ('dpm_addr_cfg' register). Otherwise the host could reconfigure the tunnel by the 'dpm_itbaddr'
register.
Additionally the 'tunnel_all'-bit provides the possibility of tunnelling all 16DWords to the NETX side.
To protect the NETX from reconfiguring the tunnel from the host side when the configuration window 0 is enabled, the 'wp_cfg_win'
can be activated. Then the tunnel configuration can only be changed from the NETX side (INTLOGIC area) but not from configuration
window 0 (in contrast to the 'wp_itbaddr'-bit which protects only offset 0x3C).

Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also the remapping
   of the DPM data windows cannot be changed by the host (refer to registers 'dpm_winX_end' and 'dpm_winX_map').

External to internal address mapping for DATunnel area can be calculated by following formula:
   INAAdr = (ITBAddr & 0xffffffc0) + ((EDAAdr + ITBAddr) & 0x3C)

With:
   INAAdr: Internal netX Access Address
   ITBAddr: Internal netX 32-bit Tunnel Target Base Address
   EDAAdr: External DPM Access Address

Condition for DATunnel access is:
   EDAAdr>>6 equals value of bit field 'base' from this register.

To map netX internal DWord N to invisible last external DWord (15), use mapping value
   map = (N - 15) & 0xf
on bits 5 to 2.
Internal to external address offset inside DATunnel area for internal DWord N can be calculated by following formula:
   External offset = (N*4 - map*4) & 0x3C = (N*4 - ITBAddr) & 0x3C

Example 1:
   Access to netX sys_time module by host via DATunnel on external DPM addresses are starting at 0x240.
   - Set bit field 'base' of this register to 9 (0x240>>6), set 'enable'-bit (and write protection depending on application).
     DATunnel now is enabled on external DPM addresses 0x240 to 0x27f.
   - ITBAddr of netX10 sys_time module is 0x101c1000.
     For direct DATunnel to this address, host must write 0x101c1000 to external DPM address 0x27c. This
     can be done e.g. by four byte accesses to 0x27c, 0x27d, 0x27e and 0x27f or by two 16-bit accesses to 0x27c and 0x27e.
     Now sys_time module registers 0 to 14 can be accessed on external DPM address 0x240 to 0x27b.

Example 2:
   Register 15 of sys_time is hidden by ITBAddr configuration on 0x27c in example 1 but must also be accessed. However, sys_time
   Register 6 is never kind of interest.
   - Configure this register like described in example 1.
   - To map Register 6 (Module offset 6*4) to external offset 0x3C (hidden data on DWord 15),
     the following rule must be complied:
        0x3C + map*4 = 6*4.
     That leads to a mapping value of:
        map*4 = (6*4 - 0x3C) & 0x3C = 1C
     Hence, write 0x101c101C to DATunnel DWord 15 (external DPM address 0x27c) to map sys_time Register 6 to
     hidden DWord 15.
     INAAdr now will be derived from EDAAdr before tunnelling as follows:
        INAAdr = 0x101c1000 + ((EDAAdr + 0x1C) & 0x3C)
     External offset of Module DWord N results from:
        External offset = (N*4 - 0x1C) & 0x3C
     Register 15 of sys_time unit now can be accessed by external DPM address 0x240+((0xf*4-0x1C) & 0x3C) = 0x260 (i.e. Tunnel DWord 8).
     Register 0  of sys_time unit now can be accessed by external DPM address 0x240+((0x0*4-0x1C) & 0x3C) = 0x264 (i.e. Tunnel DWord 9).
     Register 1  of sys_time unit now can be accessed by external DPM address 0x240+((0x1*4-0x1C) & 0x3C) = 0x268 (i.e. Tunnel DWord 10).
     and so on.
     Register 6  of sys_time unit can not be accessed as it is hidden by ITBAddr configuration on 0x27c (i.e. Tunnel DWord 15).
     Register 7  of sys_time unit now can be accessed by external DPM address 0x240+((0x7*4-0x1C) & 0x3C) = 0x240 (i.e. Tunnel DWord 0).

Note:
  Access to netX ITBAddr data is done without read ahead and with byte collecting (view adr_dpm_win1_map for details).

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.
R/W
0x80000101
Address@dpm0 : 0x60138438
Address@dpm1 : 0x60138538
Bits Reset value Name Description
31 "1"
wp_cfg_win
Write-protect tunnel configuration inside the configuration window 0.
0: The two tunnel configuration registers ('dpm_tunnel_cfg' and 'dpm_itbaddr') can be programmed
via configuration window 0 and the INTLOGIC_SYS-IDPM address area.
1:
The tunnel configuration registers ('dpm_tunnel_cfg' and 'dpm_itbaddr') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC_SYS-IDPM address area.
Note: Set this bit to protect the NETX from reconfiguring the tunnel by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
30 - 20 0
-
 reserved
19 - 6 0x4
base
DPM Access Tunnel (DATunnel) Base Address divided by 64 on external visible address space.
Note:
   Default setting for tunnel base is starting on external address 0x100.
5 "0"
dis_rd_latch
Disabled read data latch for Tunnel. View 'dis_rd_latch' of 'dpm_win1_map' register for details.
Note:
   This is a new netx56 feature.
4 "0"
byte_area
Tunnel is byte area or not. View 'byte_area' of 'dpm_win1_map' register for details.
Note:
   This is a new netx56 feature.
3 "0"
tunnel_all
Enable/disable external access to Internal Target Base Address (ITBAddr) Configuration Register.
If this bit is set Internal Target Base Address (ITBAddr) configuration is not available at tunnel
offset 0x3C. All 64 tunnel target bytes can be accessed then (no hidden register). Target mapping and address
(base and map) will not be changed when enable or disabled.
Note:
   This is a new netx56 feature.
2 "0"
enable
Enable/disable Access Tunnel function.
1 "0"
wp_itbaddr
ITBAddr is write-protected from host.
If this bit is set, ITBAddr (Internal netX 32 bit Tunnel Target Base Address)
can only be changed from netX side using dpm_itbaddr address.
Write accesses to DWords 0 to 14 of DATunnel will be ignored.
0 "1"
wp_data
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
Write accesses to DWords 0 to 14 of DATunnel will be ignored.
Data write protection for host is enabled by default and can be disabled by clearing this bit.


dpm_itbaddr
DPM Access Tunnel (DATunnel) netX Internal Target Base Address (ITBAddr) Configuration Register.
For DPM Access Tunnel (DATunnel) function view description of dpm_tunnel_cfg register.
This register contains ITBAddr value that can also be changed by host on last offset 0x3c (last DWord) of
external DATunnel area (defined by bit field 'base' in 'dpm_tunnel_cfg' register). However this register can
also be write-protected from host if bit 'wp_itbaddr' in 'dpm_tunnel_cfg' register is set.
Write protection bits of DATunnel configured in 'dpm_tunnel_cfg' register can also be read from this register. Host
can read access rights from these bits on last DWord of external DATunnel address area.

Note: This register can be write-protected by the 'wp_cfg_win' and the 'wp_itbaddr'-bit of the 'dpm_tunnel_cfg' register.
R/W
0x00000001
Address@dpm0 : 0x6013843c
Address@dpm1 : 0x6013853c
Bits Reset value Name Description
31 - 6 0x0
base
Internal netX Tunnel Target Base Address (ITBAddr) divided by 64.
View description of dpm_tunnel_cfg register.
5 - 2 "0000"
map
Mapping part of ITBAddr.
View description of dpm_tunnel_cfg register.
1 -
wp_itbaddr_ro
ITBAddr is write-protected from host.
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.
0 -
wp_data_ro
Access Tunnel function is write-protected from data access (DWords 0 to 14 of DATunnel).
This is a read-only bit here. Its setting can be changed in 'dpm_tunnel_cfg' register.
View description of dpm_tunnel_cfg register.


dpm_win1_end
DPM Window 1 End Address Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
At address 0x0 DPM configuration window is mapped after reset (length: 256 bytes, containing all DPM addresses defined here). Each window starts at
window end address of the preceding window. Hence external window 1 start address is 0x100, window 2 starts at value programmed in this register and so on.
Windows with programmed end addresses exceeding external address range (view dpm_addr_cfg) can not be accessed by host device.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.

Note:
  Configuration Window 0 access detection has higher priority than normal DPM Window
  detection but lower priority than Access Tunnel access detection.

Note:
  Since netX10 window configuration can be done in steps of 128 bytes. In netx5 only steps of 256 bytes are possible.

Note:
  Since netX10 there are 4 programmable DPM windows provided. Only for netX5 there are 5 windows.
R/W
0x00000000
Address@dpm0 : 0x60138440
Address@dpm1 : 0x60138540
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 7 0x0
win_end
Window 1 End Address divided by 128.
Last external address is win_end*128-1.
Setting win_end to 0 will disable this window.
If programmed external address range (adr_dpm_addr_cfg) is smaller than maximum
external address range, access addresses will be zero-expanded for upper unused address lines
before window match detection.
6 - 0 0
-
 reserved


dpm_win1_map
DPM Window 1 Address Map Configuration Register.
Smallest DPM window configuration unit is 128 bytes (i.e. lowest 7 bits of address configuration are always 0).
For further information view description of 'dpm_win1_end' register.

Note:
  Since netX10 window pages of 1MB is supported. For netX5 this was not necessary as all netX5 addresses are in bound of 1MB..
R/W
0x01800000
Address@dpm0 : 0x60138444
Address@dpm1 : 0x60138544
Bits Reset value Name Description
31 - 20 0x18
win_page
Window 1 address page.
Internal address space of netX is divided in 1MB pages. Changing win_map allows addressing inside
the whole currently set page.
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x01808000.
   The programmed value for the related page is 0x018.
19 - 7 0x0
win_map
Window 1 Address Mapping.
Internal access address HADDR to netX logic is combined by DPM interface by:
HADDR[31:20]: win_page
HADDR[19:0]:  mapped DPM address. This part of address is defined by programmed win_map value for each window.
The value to be programmed is address bits 19 to 0 of netX internal window start address minus start address of the
external window (i.e. end address of preceding window) .
Example:
   Window n starts at 0x400 of external DPM address range (i.e. programmed win_end value of window (n-1) and targets
   netX address 0x01808000.
   For address calculation only lower 20 bits of netX address are relevant, i.e. 0x08000.
   The complete 20 bit address map value is then:0x08000-0x400=0x07C00.
   Hence the programmed 13 bit value must be 0x07C00>>7=0xf8.
6 0
-
 reserved
5 "0"
wp_cfg_win
Write-protect window configuration inside the configuration window 0.
0: All 8 window configuration registers ('dpm_winX_end' and 'dpm_winX_map') can be programmed
via configuration window 0 and the INTLOGIC-DPM address area.
1:
All 8 window configuration registers ('dpm_winX_end' and 'dpm_winX_map') cannot
be programmed by the host via configuration window 0 (they are read-only for the host there).
They can only be programmed via the INTLOGIC-DPM address area.
Note: Set this bit to protect the NETX from reconfiguring the window mapping by the host when configuration
   window 0 is activated for the host (e.g. for IRQ handling).
Note:
   To protect the netX completely from host-access to not permitted address areas it must be ensured that also
   the remapping of the DPM tunnel cannot be changed by the host (refer to register 'dpm_tunnel_cfg').
Note:
   This bit does only exist in the 'dpm_win1_map'-register but not in the registers for the higher windows.
   However this bit protect all DPM 'dpm_winX_end' and 'dpm_winX_map'-registers from being written via
   configuration window 0.
Note:
   The 'wp_cfg_win'-bit is a new feature since netX4000 and netX6.
4 "0"
dis_rd_latch
Window 1 read data latch disable.
By default all netX internal read access are done as 32 bit access and read data is latched
inside DPM interface. This is done to provide data consistence when host is connected by
an interface smaller than 32 bit. Read data latch is updated (new read form netX logic)
when host read address is changing to another 32 bit address or if host read access repeats
reading the same data within the 32 bit address boundary of prior accesses (e.g. polling).
Reading 32 bit status information from netX should be done with byte latching (Example 1).
Read data latch can be disabled by setting this bit to avoid special handling of byte (or
16 bit) data streams (Example 2).
Example 1: Enabled read data latching (default, 'dis_rd_latch' bit is not set):
   Reading 32 bit systime from netX without data latching will fail when DPM
   is not 32 bit wide. Considering an 8 bit DPM interface would lead to 4 single
   host byte read accesses for complete systime. Without data latching systime will
   be re-read for each byte requested by host. This will lead to invalid data as systime
   will change between single reads.
   When data latching is enabled, systime will be read from netX at the first host byte read
   access. Following 3 host byte reads will receive data from DPM data latch which contains
   complete 32 bit systime value read at the first access. Host will receive valid systime data.
Example 2 Disabled read data latching ('dis_rd_latch' bit is set):
   Reading a byte stream could fail when it is appended by an application running netX inside
   could fail. Considering an netX application providing 13 bytes starting at a 32 bit boundary
   for host and host is reading these bytes. After that netX application is appending new data
   bytes 14 to 20. When data read latch is enabled host will receive bytes 14 to 16 from data
   latch. However these bytes are not valid any longer as netX application changed them in
   background. In this case data latching must be disabled.
   However reading byte streams is also possible with enabled data latch. In this case
   host must always read full 32 bit data words (i.e. restart with byte 13 when reading the
   second part of the stream).
Note:
   When read data latch is disable 'read_ahead' bit should not be set for the same window. Otherwise access
   timing could decrease dramatically (does not apply to setting of another window).
Note:
   All netX internal read access are performed as 32 bit access.
Note:
   This is a new netx56 feature.
   Behaviour of older netX versions (e.g. netX10) is similar to default setting 0. No functional
   changes are done for default case.
3 - 2 0
-
 reserved
1 "0"
read_ahead
Read ahead.
If this bit is set, read ahead will be done. This will minimize read cycle time if ready generation is
used but could cause problems with read sensitive logic (e.g. FIFOs).
Note:
   Read-ahead should not be enabled when 'dis_rd_latch' bit is set for the same window. Otherwise access
   timing could decrease dramatically (does not apply to setting of another window).
0 "0"
byte_area
Window is byte-write area.
1: Target area of this window is byte accessible. Any write access are done immediately internally.
0:
Target area of this window is 32 bit accessible. Single write accesses are collected until a 32 bit data
word (DWord) is received completely from host (write-byte-collecting). Data is written to netX target address when
the 32bit data word is complete.
Note:
   Since netX56 write-byte-collecting buffer is cleared when host is leaving the current 4-byte-address-boundary
   (e.g. changing address from 0x103 to 0x104). That means all sub-DWord access which should make up the whole DWord
   must target the same 4-byte-boundary. In prior DPM versions only the last written data determined netX internal
   access address and there was no check whether all prior written data was written to the same DWord. The
   address-boundary check is implemented to avoid write-byte-collecting getting confused by single DPM access
   errors (e.g. by a single missing byte-write).
Note:
   The setting of this bit does not affect read functionality. For details see 'dis_rd_latch' bit description.


dpm_win2_end
DPM Window 2 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x00000000
Address@dpm0 : 0x60138448
Address@dpm1 : 0x60138548
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 7 0x0
win_end
Window 2 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


dpm_win2_map
DPM Window 2 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x01800000
Address@dpm0 : 0x6013844c
Address@dpm1 : 0x6013854c
Bits Reset value Name Description
31 - 20 0x18
win_page
Window address page.
19 - 7 0x0
win_map
Window address mapping.
6 - 5 0
-
 reserved
4 "0"
dis_rd_latch
Window read data latch disable.
3 - 2 0
-
 reserved
1 "0"
read_ahead
Read ahead.
0 "0"
byte_area
Window is byte area.


dpm_win3_end
DPM Window 3 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x00000000
Address@dpm0 : 0x60138450
Address@dpm1 : 0x60138550
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 7 0x0
win_end
Window 3 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


dpm_win3_map
DPM Window 3 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x01800000
Address@dpm0 : 0x60138454
Address@dpm1 : 0x60138554
Bits Reset value Name Description
31 - 20 0x18
win_page
Window address page.
19 - 7 0x0
win_map
Window map address.
6 - 5 0
-
 reserved
4 "0"
dis_rd_latch
Window read data latch disable.
3 - 2 0
-
 reserved
1 "0"
read_ahead
Read ahead.
0 "0"
byte_area
Window is byte area.


dpm_win4_end
DPM Window 4 End Address Configuration Register.
For detailed information refer to 'dpm_win1_end' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x00000000
Address@dpm0 : 0x60138458
Address@dpm1 : 0x60138558
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 - 7 0x0
win_end
Window 4 End Address divided by 128. Last external address is win_end*128-1.
6 - 0 0
-
 reserved


dpm_win4_map
DPM Window 4 Address Map Configuration Register.
For detailed information refer to 'dpm_win1_map' register description.

Note:
  This register can be write-protected by the 'wp_cfg_win'-bit of the 'dpm_win1_map' register.
R/W
0x01800000
Address@dpm0 : 0x6013845c
Address@dpm1 : 0x6013855c
Bits Reset value Name Description
31 - 20 0x18
win_page
Window address page.
19 - 7 0x0
win_map
Window map address.
6 - 5 0
-
 reserved
4 "0"
dis_rd_latch
Window read data latch disable.
3 - 2 0
-
 reserved
1 "0"
read_ahead
Read ahead.
0 "0"
byte_area
Window is byte area.


dpm_irq_raw
DPM Raw (before masking) IRQ Status Register.
If a bit is set, the related interrupt is asserted.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.

Note:
   The 'dpm_sw' IRQ can be controlled by the 'dpm_sw_irq' register for each
   IRQ target differently, i.e. there are 2 different 'dpm_sw' IRQs internally, one
   for each IRQ target. However, 'dpm_sw' will be set inside the 'dpm_irq_raw' register here
   when the 'dpm_sw' is activated for at least one IRQ target. But each IRQ target
   obtains only the 'dpm_sw' IRQ state programmed for this target inside the 'dpm_sw_irq'
   register. For an example view description of 'dpm_sw_irq' register.

Note:
    The 'test' function is obsolete since netX56, the 'dpm_sw' bit can be used instead of this.

Note:
    For all netX modules which are capable generating IRQs for ARM, ARM-IRQ is taken here.
R
Address@dpm0 : 0x60138480
Address@dpm1 : 0x60138580
Bits Name Description
31 dpm_sw
raw software IRQ of this DPM module for netX IRQ targets interrupt
30 dpm_err
raw DPM access error IRQ of this DPM module interrupt
29 - 0 sms
raw SMS host IRQ vectort bits [29:0] interrupt


dpm_irq_host_sirq_mask_set
DPM Interrupt Mask Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address@dpm0 : 0x60138484
Address@dpm1 : 0x60138584
Bits Reset value Name Description
31 "0"
dpm_sw
set software IRQ of this DPM module for netX IRQ targets interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
30 "0"
dpm_err
set DPM access error IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 - 0 0x0
sms
set SMS host IRQ vectort bits [29:0] interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_mask_reset
DPM Interrupt Mask Reset Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address@dpm0 : 0x60138488
Address@dpm1 : 0x60138588
Bits Reset value Name Description
31 "0"
dpm_sw
reset software IRQ of this DPM module for netX IRQ targets interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
30 "0"
dpm_err
reset DPM access error IRQ of this DPM module interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 - 0 0x0
sms
reset SMS host IRQ vectort bits [29:0] interrupt mask for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_sirq_masked
DPM Masked Interrupt Status Register for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_sirq_mask'-register and the related interrupt is asserted.
IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
Address@dpm0 : 0x6013848c
Address@dpm1 : 0x6013858c
Bits Name Description
31 dpm_sw
masked software IRQ of this DPM module for netX IRQ targets interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
30 dpm_err
masked DPM access error IRQ of this DPM module interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)
29 - 0 sms
masked SMS host IRQ vectort bits [29:0] interrupt state for high-priority netX interrupt output signal (DPM_FIQ/HIF_SIRQ)


dpm_irq_host_dirq_mask_set
DPM Interrupt Mask Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' sets related interrupt mask bits (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address@dpm0 : 0x60138490
Address@dpm1 : 0x60138590
Bits Reset value Name Description
31 "0"
dpm_sw
set software IRQ of this DPM module for netX IRQ targets interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
30 "0"
dpm_err
set DPM access error IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 - 0 0x0
sms
set SMS host IRQ vectort bits [29:0] interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_mask_reset
DPM Interrupt Mask Reset Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Write access with '1' resets related interrupt mask bits (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence related interrupt mask bit.
Read access shows actual interrupt mask.
If a mask bit is set, the related interrupt will activate the IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R/W
0x00000000
Address@dpm0 : 0x60138494
Address@dpm1 : 0x60138594
Bits Reset value Name Description
31 "0"
dpm_sw
reset software IRQ of this DPM module for netX IRQ targets interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
30 "0"
dpm_err
reset DPM access error IRQ of this DPM module interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 - 0 0x0
sms
reset SMS host IRQ vectort bits [29:0] interrupt mask for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_irq_host_dirq_masked
DPM Masked Interrupt Status Register for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ).
A bit is set, when the related mask bit is set in 'dpm_irq_host_dirq_mask'-register and the related interrupt is asserted.
IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) is asserted if at least one bit is set here.
Interrupts must be reset in interrupt generating module. Interrupts cannot be cleared here.
To release IRQ for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ) without clearing interrupt in module, reset related mask bit to 0.

Note:
   For further information view description of 'dpm_irq_raw' register.
R
Address@dpm0 : 0x60138498
Address@dpm1 : 0x60138598
Bits Name Description
31 dpm_sw
masked software IRQ of this DPM module for netX IRQ targets interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
30 dpm_err
masked DPM access error IRQ of this DPM module interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)
29 - 0 sms
masked SMS host IRQ vectort bits [29:0] interrupt state for normal netX interrupt output signal (DPM_IRQ/HIF_DIRQ)


dpm_sw_irq
DPM Register for Software Interrupt Generation.
To propagate interrupt states from this register to the interrupt target the 'dpm_sw' bit must
be set inside the appropriate interrupt mask (e.g. 'dpm_irq_host_sirq_mask_set' register).

Note:
   For each netX interrupt target  there is a set and a reset bit provided to avoid read-modify-write sequences.
   When both (set and reset) bits are set for the same target, the related interrupt will be set (set will win).
   Reset bits are always 0 on read. Set-bits show current interrupt status when read.
Note:
   This register is a new netx56 feature..
R/W
0x00000000
Address@dpm0 : 0x601384b8
Address@dpm1 : 0x601385b8
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
reset_host_dirq
Reset 'dpm_sw' IRQ for DIRQ/IRQ-signal (always 0 when read)
8 "0"
reset_host_sirq
Reset 'dpm_sw' IRQ for SIRQ/FIQ-signal (always 0 when read)
7 - 2 0
-
 reserved
1 "0"
set_host_dirq
Set 'dpm_sw' IRQ for DIRQ/IRQ-signal (current 'dpm_sw' status for host_dirq when read)
0 "0"
set_host_sirq
Set 'dpm_sw' IRQ for SIRQ/FIQ-signal (current 'dpm_sw' status for host_sirq when read)


dpm_crc
DPM CRC for access to NETX data (window1-4)
R/W
0xffffffff
Address@dpm0 : 0x601384bc
Address@dpm1 : 0x601385bc
Bits Reset value Name Description
31 - 16 0xffff
crc_wdata
Provides the current CRC of data written to DPM windows 1-4 since last write-CRC clear.
Write 0x1 to this bit field to clear write-CRC generation to restart CRC for a new write data.
15 - 0 0xffff
crc_rdata
Provides the current CRC of data read from DPM windows 1-4 since last read-CRC clear.
Write 0x1 to this bit field to clear read-CRC generation to restart CRC for a new read data.


dpm_reset_request
(DPM_HOST_RESET_REQ)
DPM Reset Request Register.

Note: This register is compatible to netx50 DPM_HOST_RESET_REQ register
R/W
0x00000000
Address@dpm0 : 0x601384dc
Address@dpm1 : 0x601385dc
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
reset_key
Reset key sequence register.
A netx hardware reset is generated if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this DPM module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected by the DPM module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this DPM register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The DPM reset request is internally a level-signal, not only a pulse. Additionally the
   DPM reset request could be masked (disabled) by the global reset controller (netX4000).
   If the DPM reset request is disabled globally but issued by the DPM module there are two
   possibilities to get out of this:
   1.: Enable the DPM reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this DPM register area. This will clear the DPM
reset FSM and the reset request of this DPM module to the global reset controller.
Note:
  For netx10 a 9th access (write 0xff) was necessary to perform a reset  This access
  is not netx50 compatible and not required any longer since netx56.


dpm_netx_version_bigend16
DPM netX Version Register in big endianess 16 data mapping.
This registers content is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
Together with dpm_netx_version register, full 32 bit version can be read by any host device, even if DPM interface is not initialized yet.
Bytes byte1 and byte3 can be always read here even if DPM is uninitialized (8 bit default from dpm_cfg0x0 after power on) and
host device has 8, 16 or 32 bit data width.
   8 bit DPM  16 bit DPM  32 bit DPM
 byte 0 (D7:0)  byte read this address +1  adr_dpm_netx_version  adr_dpm_netx_version
 byte 1 (D15:8)  byte read this address +0  byte read this address  DWord read this address
 byte 2 (D23:16)  byte read this address +3  adr_dpm_netx_version  adr_dpm_netx_version
 byte 3 (D31:24)  byte read this address +2  byte read this address +2  byte read this address +0
R
Address@dpm0 : 0x601384f4
Address@dpm1 : 0x601385f4
Bits Name Description
31 - 24 netx_version_byte2_swap
netX version bits 24 to 16.
23 - 16 netx_version_byte3_swap
netX version bits 31 to 24.
15 - 8 netx_version_byte0_swap
netX version bits 8 to 0.
7 - 0 netx_version_byte1_swap
netX version bits 16 to 8.


dpm_netx_version
DPM netX Version Register.
This register is mirrored form asic_ctrl register area and can be set during netX booting phase by netX firmware.
This register is not valid if unlocked bit is not set in dpm_status register.
Together with dpm_netx_version register, full 32 bit version can be read by any host device, even if DPM interface is not initialized yet.
Bytes byte0 and byte2 can be always read here even if DPM is uninitialized (8 bit default from dpm_cfg0x0 after power on) and
host device has 8, 16 or 32 bit data width.
   8 bit DPM  16 bit DPM 32 bit DPM
 byte 0 (D7:0)  byte read this address +0  byte read this address  DWord read this address
 byte 1 (D15:8)  byte read this address +1  adr_dpm_netx_version_bigend16  adr_dpm_netx_version_bigend16
 byte 2 (D23:16)  byte read this address +2  byte read this address +2  byte read this address +0
 byte 3 (D31:24)  byte read this address +3  adr_dpm_netx_version_bigend16  adr_dpm_netx_version_bigend16
R
Address@dpm0 : 0x601384fc
Address@dpm1 : 0x601385fc
Bits Name Description
31 - 24 netx_version_byte3
netX version bits 31 to 24.
23 - 16 netx_version_byte2
netX version bits 24 to 16.
15 - 8 netx_version_byte1
netX version bits 16 to 8.
7 - 0 netx_version_byte0
netX version bits 8 to 0.



Base Address Area: hif_io_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W hif_io_cfg
1 4 R/W hif_pio_cfg
2 8 R/W hif_pio_out0
3 c R/W hif_pio_out1
4 10 R/W hif_pio_oe0
5 14 R/W hif_pio_oe1
6 18 R hif_pio_in0
7 1c R hif_pio_in1
8 20 -  reserved
9 24 R hif_pio_irq_raw
a 28 R/W hif_pio_irq_arm_mask_set
b 2c R/W hif_pio_irq_arm_mask_reset
c 30 R hif_pio_irq_arm_masked
d 34 R/W hif_pio_irq_xpic_mask_set
e 38 R/W hif_pio_irq_xpic_mask_reset
f 3c R hif_pio_irq_xpic_masked

hif_io_cfg
IO Config Register:
Selects of HIF pin multiplexing.
See Excel pinning sheet for details.
This configuration must be set up according to external netX connection before any access to external logic.
R/W
0x00000000
Address : 0x60138600
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
unlock_dpm
for DPM0 and DPM1 module. TBD: right place here?.
11 - 5 0
-
 reserved
4 "0"
en_sdpm1
Enables the 2nd serial DPM for netXtiny.
 0: 2nd serial DPM is disabled.
 1: 2nd serial DPM is enabled.
Note:
   It is possible to enable the 2nd serial DPM stand-alone or together with the normal DPM
   in serial mode (i.e. both bits 'sel_hif_dpm' and 'sel_dpm_serial' set).
   It is not possible to use the 2nd serial DPM together with the first DPM in parallel mode
   as they use the same IOs (the 2nd DPM does not provide the parallel mode).
Note:
   The mode of the 2nd serial DPM is same as for the first DPM (programmed by
   the bits 'sel_dpm_serial_spo' and 'sel_dpm_serial_sph')
Note: You must additionally select the HIF/DPM function by the registers global_asic_ctrl_hif_io_cfgX.
3 "0"
sel_dpm_serial_spo
serial DPM mode SPI clock polarity selection (sel_hif_dpm and sel_dpm_serial must be set)
 0: Serial clock idle state is low.
 1: Serial clock idle state is high.
2 "0"
sel_dpm_serial_sph
serial DPM mode SPI clock phase selection (sel_hif_dpm and sel_dpm_serial must be set)
 0: Serial data sampling on first serial clock edge.
 1: Serial data sampling on second serial clock edge.
1 "0"
sel_dpm_serial
serial (SPI) DPM mode selection (ignored if sel_hif_dpm not set).
There are 2 independent serial DPM interfaces for netXtiny. They can be used together,
e.g. one for cyclic and one for acyclic data) or stand-alone. The 1st sDPM (sDPM0) can
always be used together with external memory (even 16bit mode). sDPM1 can only be used with
an 8 bit MI. The pinning positions of serial DPM interfaces are provided by the main pinning
table: The pinning-functions "dpm0_spi*" represent sDPM0,  pinning-functions "dpm1_spi*" represent sDPM1.
Note:
For parallel DPM, the IRQ signals to the host are located on HIF_DIRQ and HIF_SIRQ (DPM0 only).
When external SDRAM is used (en_hif_sdram_mi) the IRQ on HIF_SIRQ is not available). For serial DPM
the IRQs are located on different IOs (refer to main pinning table).
Note: You must additionally select the HIF/DPM function by the registers global_asic_ctrl_hif_io_cfgX.
0 "0"
sel_hif_dpm
Enable DPM0 module (serial or parallel)
Note: You must additionally select the HIF/DPM function by the registers global_asic_ctrl_hif_io_cfgX.
Note: For parallel DPM IO configuration use config registers in address area DPM.
Note: Parallel DPM fast/service IRQ functionality (SIRQ/FIQ) on HIF_SIRQ is controlled by
en_hif_sdram_mi bit
Note: For parallel DPM host IRQs can be generated on HIF_DIRQ and HIF_SIRQ IOs.
Note: For parallel DPM HIF PIO function muse be configured inside 'dpm_pio_cfg'
registers for all HIF IOs.


hif_pio_cfg
HIF PIO Mode configuration register.
R/W
0x80000008
Address : 0x60138604
Bits Reset value Name Description
31 "1"
filter_irqs
Filtering of HIF PIO inputs for IRQ generation.
By default filtering is applied on HIF PIO inputs before IRQ generation.
 0 Spikes on PIOs will not be suppressed for HIF PIO IRQ generation.
 1 Spikes up to 10ns on HIF PIOs will be suppressed by sample stages for HIF PIO
   IRQ generation. That causes 10ns additionally IRQ latency.
30 - 28 0
-
 reserved
27 - 26 "00"
irq_hif_dirq_cfg
HIF_DIRQ IRQ input configuration
   Mode Function
     00 low level active IRQ
     01 high level active IRQ
     10 falling edge active IRQ
     11 rising edge active IRQ

For IRQ usage this IO should be in PIO input mode, (programmed in the 'hif_io_cfg' register or
PIO-configuration registers of the DPM module). For input its PIO output enable must be programmed to '0'.
Spikes on related PIO can be suppressed by 'filter_irqs' bit.
Note: HIF PIO IRQs can be assigned and monitored in hif_pio_irq registers further down.
Note: The HIF IRQ input bit fields are reordered since netx56
25 - 22 0
-
 reserved
21 - 20 "00"
irq_hif_a17_cfg
HIF_A17 IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
19 - 18 "00"
irq_hif_a16_cfg
HIF_A16 IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
17 - 16 "00"
irq_hif_d12_cfg
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ) IRQ input configuration
For coding refer to irq_hif_dirq_cfg bit-field.
15 - 4 0
-
 reserved
3 "1"
filter_en_in
HIF PIO Input sampling enable (EN_IN) filter.
 0 Spikes will not be suppressed for EN_IN.
 1 Spikes up to 10ns will be suppressed by HIF PIO EN_IN sample stages.
Note:
   Spike suppression can only done for EN_IN input.
   There is no spike suppression for data inputs of 'hif_pio_in0,1' registers.
2 0
-
 reserved
1 - 0 "00"
in_ctrl
HIF PIO Input sampling mode.
HIF input status registers hif_pio_in0,1 can be configured by programming these bits.
   Mode Function
     00 Reserved/obsolete, use sample_at_pwron_stat* of global_asic_ctrl instead.
(was until netX90: pio_in registers show HIF IO states sampled at power-on-reset release)
     01 HIF IO states are sampled continuously (each netX system clock cycle)
     10 HIF IO states are sampling is done each system clock cycle when enable signal
EN_IN (HIF_WRHN, TBD) level is low.
     11 HIF IO states are sampling is done each system clock cycle when enable signal
EN_IN (HIF_WRHN, TBD) level is high.
 others reserved

Note:
   Settings 00 to 11 are netX 50 compatible (netX 50 register DPM_ARM_IO_MODE1.IN_CONTROL).
Note:
   Power-on-reset states will not be lost when 'in_ctrl' is set to a value not 0.
Note:
    Power-on-reset states can be used to read pullup/down configuration of HIF-IOs.
    However, be careful using reset sampled values of HIF data lines when SDRAM is
    connected: When Reset is done during SDRAM read access, SDRAM device will keep
    driving data bus. Pull-up/down values will be overdriven by that.


hif_pio_out0
HIF PIO Output State Configuration Register 0.
All unused HIF signals can be used as PIOs. IOs will be driven to the programmed state if appropriate enable bit
is set in hif_pio_oe0 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
0x00000000
Address : 0x60138608
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hif_d15
PIO output drive level of HIF_D15 signal.
14 "0"
hif_d14
PIO output drive level of HIF_D14 signal.
13 "0"
hif_d13
PIO output drive level of HIF_D13 signal.
12 "0"
hif_d12
PIO output drive level of HIF_D12 signal.
11 "0"
hif_d11
PIO output drive level of HIF_D11 signal.
10 "0"
hif_d10
PIO output drive level of HIF_D10 signal.
9 "0"
hif_d9
PIO output drive level of HIF_D9 signal.
8 "0"
hif_d8
PIO output drive level of HIF_D8 signal.
7 "0"
hif_d7
PIO output drive level of HIF_D7 signal.
6 "0"
hif_d6
PIO output drive level of HIF_D6 signal.
5 "0"
hif_d5
PIO output drive level of HIF_D5 signal.
4 "0"
hif_d4
PIO output drive level of HIF_D4 signal.
3 "0"
hif_d3
PIO output drive level of HIF_D3 signal.
2 "0"
hif_d2
PIO output drive level of HIF_D2 signal.
1 "0"
hif_d1
PIO output drive level of HIF_D1 signal.
0 "0"
hif_d0
PIO output drive level of HIF_D0 signal.


hif_pio_out1
HIF PIO Output State Configuration Register 1.
All unused HIF signals can be used as PIOs. IOs will be driven to the programmed state if appropriate enable bit
is set in hif_pio_oe1 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
0x00000000
Address : 0x6013860c
Bits Reset value Name Description
31 "0"
hif_sirq
PIO output drive level of HIF_SIRQ signal.
30 "0"
hif_dirq
PIO output drive level of HIF_DIRQ signal.
29 "0"
hif_rdy
PIO output drive level of HIF_RDY signal.
28 "0"
hif_csn
PIO output drive level of HIF_CSN signal.
27 "0"
hif_wrn
PIO output drive level of HIF_WRN signal.
26 "0"
hif_rdn
PIO output drive level of HIF_RDN signal.
25 "0"
hif_bhe
PIO output drive level of HIF_BHE signals.
24 "0"
hif_ale
PIO output drive level of HIF_ALE signals.
23 "0"
hif_wrhn
PIO output drive level of HIF_WRHN signals.
22 - 18 0
-
 reserved
17 "0"
hif_a17
PIO output drive level of HIF_A17 signal.
16 "0"
hif_a16
PIO output drive level of HIF_A16 signal.
15 "0"
hif_a15
PIO output drive level of HIF_A15 signal.
14 "0"
hif_a14
PIO output drive level of HIF_A14 signal.
13 "0"
hif_a13
PIO output drive level of HIF_A13 signal.
12 "0"
hif_a12
PIO output drive level of HIF_A12 signal.
11 "0"
hif_a11
PIO output drive level of HIF_A11 signal.
10 "0"
hif_a10
PIO output drive level of HIF_A10 signal.
9 "0"
hif_a9
PIO output drive level of HIF_A9 signal.
8 "0"
hif_a8
PIO output drive level of HIF_A8 signal.
7 "0"
hif_a7
PIO output drive level of HIF_A7 signal.
6 "0"
hif_a6
PIO output drive level of HIF_A6 signal.
5 "0"
hif_a5
PIO output drive level of HIF_A5 signal.
4 "0"
hif_a4
PIO output drive level of HIF_A4 signal.
3 "0"
hif_a3
PIO output drive level of HIF_A3 signal.
2 "0"
hif_a2
PIO output drive level of HIF_A2 signal.
1 "0"
hif_a1
PIO output drive level of HIF_A1 signal.
0 "0"
hif_a0
PIO output drive level of HIF_A0 signal.


hif_pio_oe0
HIF PIO Output Enable Configuration Register 0.
All unused HIF signals can be used as PIOs. IOs will be driven to the output state
programmed in in hif_pio_out0 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
0x00000000
Address : 0x60138610
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
hif_d15
PIO output enable of HIF_D15 signal.
14 "0"
hif_d14
PIO output enable of HIF_D14 signal.
13 "0"
hif_d13
PIO output enable of HIF_D13 signal.
12 "0"
hif_d12
PIO output enable of HIF_D12 signal.
11 "0"
hif_d11
PIO output enable of HIF_D11 signal.
10 "0"
hif_d10
PIO output enable of HIF_D10 signal.
9 "0"
hif_d9
PIO output enable of HIF_D9 signal.
8 "0"
hif_d8
PIO output enable of HIF_D8 signal.
7 "0"
hif_d7
PIO output enable of HIF_D7 signal.
6 "0"
hif_d6
PIO output enable of HIF_D6 signal.
5 "0"
hif_d5
PIO output enable of HIF_D5 signal.
4 "0"
hif_d4
PIO output enable of HIF_D4 signal.
3 "0"
hif_d3
PIO output enable of HIF_D3 signal.
2 "0"
hif_d2
PIO output enable of HIF_D2 signal.
1 "0"
hif_d1
PIO output enable of HIF_D1 signal.
0 "0"
hif_d0
PIO output enable of HIF_D0 signal.


hif_pio_oe1
HIF PIO Output Enable Configuration Register 1.
All unused HIF signals can be used as PIOs. IOs will be driven to the output state
programmed in in hif_pio_out1 register.
PIO mode driving of HIF-IOs used in current HIF/EXT_BUS Memory Interface configuration is not possible.
-----------------------
Note:
   This register can be read or written by 8, 16 or 32 bit access.
R/W
0x00000000
Address : 0x60138614
Bits Reset value Name Description
31 "0"
hif_sirq
PIO output enable of HIF_SIRQ signal.
30 "0"
hif_dirq
PIO output enable of HIF_DIRQ signal.
29 "0"
hif_rdy
PIO output enable of HIF_RDY signal.
28 "0"
hif_csn
PIO output enable of HIF_CSN signal.
27 "0"
hif_wrn
PIO output enable of HIF_WRN signal.
26 "0"
hif_rdn
PIO output enable of HIF_RDN signal.
25 "0"
hif_bhe
PIO output enable of HIF_BHE signals.
24 "0"
hif_ale
PIO output enable of HIF_ALE signals.
23 "0"
hif_wrhn
PIO output enable of HIF_WRHN signals.
22 - 18 0
-
 reserved
17 "0"
hif_a17
PIO output enable of HIF_A17 signal.
16 "0"
hif_a16
PIO output enable of HIF_A16 signal.
15 "0"
hif_a15
PIO output enable of HIF_A15 signal.
14 "0"
hif_a14
PIO output enable of HIF_A14 signal.
13 "0"
hif_a13
PIO output enable of HIF_A13 signal.
12 "0"
hif_a12
PIO output enable of HIF_A12 signal.
11 "0"
hif_a11
PIO output enable of HIF_A11 signal.
10 "0"
hif_a10
PIO output enable of HIF_A10 signal.
9 "0"
hif_a9
PIO output enable of HIF_A9 signal.
8 "0"
hif_a8
PIO output enable of HIF_A8 signal.
7 "0"
hif_a7
PIO output enable of HIF_A7 signal.
6 "0"
hif_a6
PIO output enable of HIF_A6 signal.
5 "0"
hif_a5
PIO output enable of HIF_A5 signal.
4 "0"
hif_a4
PIO output enable of HIF_A4 signal.
3 "0"
hif_a3
PIO output enable of HIF_A3 signal.
2 "0"
hif_a2
PIO output enable of HIF_A2 signal.
1 "0"
hif_a1
PIO output enable of HIF_A1 signal.
0 "0"
hif_a0
PIO output enable of HIF_A0 signal.


hif_pio_in0
HIF PIO Input State Register 0.
IO input states can be read here regardless whether IO is used in current HIF/EXT_BUS Memory Interface configuration.
HIF IO sampling behaviour can be programmed by 'in_ctrl' bits of 'hif_pio_cfg' register.
R
Address : 0x60138618
Bits Name Description
31 - 16 -
 reserved
15 hif_d15
PIO input state of HIF_D15 signal.
14 hif_d14
PIO input state of HIF_D14 signal.
13 hif_d13
PIO input state of HIF_D13 signal.
12 hif_d12
PIO input state of HIF_D12 signal.
11 hif_d11
PIO input state of HIF_D11 signal.
10 hif_d10
PIO input state of HIF_D10 signal.
9 hif_d9
PIO input state of HIF_D9 signal.
8 hif_d8
PIO input state of HIF_D8 signal.
7 hif_d7
PIO input state of HIF_D7 signal.
6 hif_d6
PIO input state of HIF_D6 signal.
5 hif_d5
PIO input state of HIF_D5 signal.
4 hif_d4
PIO input state of HIF_D4 signal.
3 hif_d3
PIO input state of HIF_D3 signal.
2 hif_d2
PIO input state of HIF_D2 signal.
1 hif_d1
PIO input state of HIF_D1 signal.
0 hif_d0
PIO input state of HIF_D0 signal.


hif_pio_in1
HIF PIO Input State Register 1.
IO input states can be read here regardless whether IO is used in current HIF/EXT_BUS Memory Interface configuration.
R
Address : 0x6013861c
Bits Name Description
31 hif_sirq
PIO input state of HIF_SIRQ signal.
30 hif_dirq
PIO input state of HIF_DIRQ signal.
29 hif_rdy
PIO input state of HIF_RDY signal.
28 hif_csn
PIO input state of HIF_CSN signal.
27 hif_wrn
PIO input state of HIF_WRN signal.
26 hif_rdn
PIO input state of HIF_RDN signal.
25 hif_bhe
PIO input state of HIF_BHE signal.
24 hif_ale
PIO input state of HIF_ALE signal.
23 hif_wrhn
PIO input state of HIF_WRHN signal.
22 - 18 -
 reserved
17 hif_a17
PIO input state of HIF_A17 signal
16 hif_a16
PIO input state of HIF_A16 signal
15 hif_a15
PIO input state of HIF_A15 signal.
14 hif_a14
PIO input state of HIF_A14 signal.
13 hif_a13
PIO input state of HIF_A13 signal.
12 hif_a12
PIO input state of HIF_A12 signal.
11 hif_a11
PIO input state of HIF_A11 signal.
10 hif_a10
PIO input state of HIF_A10 signal.
9 hif_a9
PIO input state of HIF_A9 signal.
8 hif_a8
PIO input state of HIF_A8 signal.
7 hif_a7
PIO input state of HIF_A7 signal.
6 hif_a6
PIO input state of HIF_A6 signal.
5 hif_a5
PIO input state of HIF_A5 signal.
4 hif_a4
PIO input state of HIF_A4 signal.
3 hif_a3
PIO input state of HIF_A3 signal.
2 hif_a2
PIO input state of HIF_A2 signal.
1 hif_a1
PIO input state of HIF_A1 signal.
0 hif_a0
PIO input state of HIF_A0 signal.


hif_pio_irq_raw
HIF PIO Raw (before masking) IRQ Status Register.
If bit is set, the according interrupt is asserted.
Interrupt status can be cleared by writing ones to this register.
Each IRQ source can be assigned either to xPIC or to ARM (or to both) by the following registers.
IRQ clearing has lower priority than IRQ set when done simultaneously.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
Note: The bits of this register are reordered since netx56.
R
Address : 0x60138624
Bits Name Description
31 - 4 -
 reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_mask_set
HIF PIO Interrupt Mask Register for netX internal ARM.
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal ARM.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
0x00000000
Address : 0x60138628
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
irq_hif_a17
HIF_A17 IRQ
1 "0"
irq_hif_a16
HIF_A16 IRQ
0 "0"
irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_mask_reset
HIF PIO Interrupt Mask Reset Register for netX internal ARM.
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal ARM if asserted.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
0x00000000
Address : 0x6013862c
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
irq_hif_a17
HIF_A17 IRQ
1 "0"
irq_hif_a16
HIF_A16 IRQ
0 "0"
irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_arm_masked
HIF PIO Masked Interrupt Status Register for netX internal ARM.
If bit is set, if the according mask bit is set in hif_pio_irq_arm_mask-register and the according interrupt is asserted.
IRQ for netX internal ARM signal is asserted if at least one bit is set here.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal ARM signal without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R
Address : 0x60138630
Bits Name Description
31 - 4 -
 reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_mask_set
HIF PIO Interrupt Mask Register for netX internal xPIC.
Write access with '1' sets interrupt mask bit (enables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal xPIC.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
0x00000000
Address : 0x60138634
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
irq_hif_a17
HIF_A17 IRQ
1 "0"
irq_hif_a16
HIF_A16 IRQ
0 "0"
irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_mask_reset
HIF PIO Interrupt Mask Reset Register for netX internal xPIC.
Write access with '1' resets interrupt mask bit (disables interrupt request for corresponding interrupt source).
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
If bit is set, the according interrupt will activate the IRQ for netX internal xPIC if asserted.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R/W
0x00000000
Address : 0x60138638
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 "0"
irq_hif_dirq
HIF_DIRQ IRQ
2 "0"
irq_hif_a17
HIF_A17 IRQ
1 "0"
irq_hif_a16
HIF_A16 IRQ
0 "0"
irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)


hif_pio_irq_xpic_masked
HIF PIO Masked Interrupt Status Register for netX internal xPIC.
If bit is set, if the according mask bit is set in hif_pio_irq_xpic_mask-register and the according interrupt is asserted.
IRQ for netX internal xPIC signal is asserted if at least one bit is set here.
Interrupt status can be cleared by writing ones to the hif_pio_irq_raw register.
To release IRQ for netX internal xPIC signal without clearing interrupt in module, reset according mask bit to 0.
Note: Spikes up to 10ns will be suppressed by HIF PIO IRQ sample stages.
Note: HIF PIO interrupt function can be configured in the hif_pio_cfg register.
Note: HIF PIO IRQs are combined with DPM IRQs and Handshake-Cell (HANDSHACKE_CTRL) IRQs.
R
Address : 0x6013863c
Bits Name Description
31 - 4 -
 reserved
3 irq_hif_dirq
HIF_DIRQ IRQ
2 irq_hif_a17
HIF_A17 IRQ
1 irq_hif_a16
HIF_A16 IRQ
0 irq_hif_d12
HIF_D12 (DPM_SPI_DIRQ/SPM_DIRQ)



Base Address Area: sms_host_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R sms_host_irq_pending
1 4 R sms_host_irq_pending_masked
2 8 R sms_host_irq_latch_state
3 c R sms_host_irq_mask_state
4 10 W sms_host_irq_latch_rst
5 14 W sms_host_irq_latch_set
6 18 W sms_host_irq_mask_rst
7 1c W sms_host_irq_mask_set
8 20 R/W sms_host_irq_is_edge
9-f 24-3c -  reserved

sms_host_irq_pending
Host IRQ pending register
pending[n] <= input[n] | latch[n]
R
Address : 0x60180400
Bits Name Description
31 - 30 -
 reserved
29 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 - 16 sync_selected
SYNC_SELECTED IRQ
15 - 12 tbuf_tx_prod
TBUF_TX prod IRQ
11 - 8 tbuf_rx_cons
TBUF_RX cons IRQ
7 - 0 hsc
HSC IRQ


sms_host_irq_pending_masked
Host Pending Masked register
pending & mask IRQ vector
R
Address : 0x60180404
Bits Name Description
31 - 30 -
 reserved
29 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 - 16 sync_selected
SYNC_SELECTED IRQ
15 - 12 tbuf_tx_prod
TBUF_TX prod IRQ
11 - 8 tbuf_rx_cons
TBUF_RX cons IRQ
7 - 0 hsc
HSC IRQ


sms_host_irq_latch_state
Host Latch State register
Current latch state
R
Address : 0x60180408
Bits Name Description
31 - 30 -
 reserved
29 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 - 16 sync_selected
SYNC_SELECTED IRQ
15 - 12 tbuf_tx_prod
TBUF_TX prod IRQ
11 - 8 tbuf_rx_cons
TBUF_RX cons IRQ
7 - 0 hsc
HSC IRQ


sms_host_irq_mask_state
Host Mask State register
Current mask state
R
Address : 0x6018040c
Bits Name Description
31 - 30 -
 reserved
29 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 - 16 sync_selected
SYNC_SELECTED IRQ
15 - 12 tbuf_tx_prod
TBUF_TX prod IRQ
11 - 8 tbuf_rx_cons
TBUF_RX cons IRQ
7 - 0 hsc
HSC IRQ


sms_host_irq_latch_rst
Host Latch Reset register
write-one-to-clear latch (confirms edge-triggered and software IRQ)
W
0x00000000
Address : 0x60180410
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 28 "00"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 - 16 "0000"
sync_selected
SYNC_SELECTED IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_prod
TBUF_TX prod IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_cons
TBUF_RX cons IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC IRQ
the hardware will automatically reset this bit


sms_host_irq_latch_set
Host Latch Set register
write-one-to-set latch to stimulate software IRQ (write-only)
W
0x00000000
Address : 0x60180414
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 28 "00"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 - 16 "0000"
sync_selected
SYNC_SELECTED IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_prod
TBUF_TX prod IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_cons
TBUF_RX cons IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC IRQ
the hardware will automatically reset this bit


sms_host_irq_mask_rst
Host Mask Reset register
write-one-to-clear-mask (write-only)
W
0x00000000
Address : 0x60180418
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 28 "00"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 - 16 "0000"
sync_selected
SYNC_SELECTED IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_prod
TBUF_TX prod IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_cons
TBUF_RX cons IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC IRQ
the hardware will automatically reset this bit


sms_host_irq_mask_set
Host Mask Set register
write-one-to-set-mask (write-only)
W
0x00000000
Address : 0x6018041c
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 28 "00"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 - 16 "0000"
sync_selected
SYNC_SELECTED IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_prod
TBUF_TX prod IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_cons
TBUF_RX cons IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC IRQ
the hardware will automatically reset this bit


sms_host_irq_is_edge
Host IRQ IS_EDGE configuration register
One bit controlling edge-detection per input - also see pending
If enabled for the IRQ, latch[n] will be set when a high level is detected on the input[n]
R/W
0x00000000
Address : 0x60180420
Bits Reset value Name Description
31 - 30 0
-
 reserved
29 - 28 "00"
sw
Software IRQ
27 - 20 "00000000"
tba
TBA IRQ
19 - 16 "0000"
sync_selected
SYNC_SELECTED IRQ
15 - 12 "0000"
tbuf_tx_prod
TBUF_TX prod IRQ
11 - 8 "0000"
tbuf_rx_cons
TBUF_RX cons IRQ
7 - 0 "00000000"
hsc
HSC IRQ



Base Address Area: sms_host_irq_logic, sms_device_irq_logic

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R sms_irq_logic_pending
1 4 R sms_irq_logic_pending_masked
2 8 R sms_irq_logic_latch_state
3 c R sms_irq_logic_mask_state
4 10 W sms_irq_logic_latch_rst
5 14 W sms_irq_logic_latch_set
6 18 W sms_irq_logic_mask_rst
7 1c W sms_irq_logic_mask_set
8 20 R/W sms_irq_logic_is_edge
9-f 24-3c -  reserved

sms_irq_logic_pending
IRQ pending register
pending[n] <= input[n] | latch_state[n]
R
Address@sms_host_irq_logic : 0x60180400
Address@sms_device_irq_logic : 0x601b0000
Bits Name Description
31 - 0 pending
Pending state of IRQ vector


sms_irq_logic_pending_masked
Pending Masked register
pending & mask IRQ vector
R
Address@sms_host_irq_logic : 0x60180404
Address@sms_device_irq_logic : 0x601b0004
Bits Name Description
31 - 0 pending_masked
State of masked IRQ vector


sms_irq_logic_latch_state
Latch State register
Current latch state
R
Address@sms_host_irq_logic : 0x60180408
Address@sms_device_irq_logic : 0x601b0008
Bits Name Description
31 - 0 state
Current latch state of IRQ vector


sms_irq_logic_mask_state
Mask State register
Current mask state
R
Address@sms_host_irq_logic : 0x6018040c
Address@sms_device_irq_logic : 0x601b000c
Bits Name Description
31 - 0 msk_state
State of mask of IRQ vector


sms_irq_logic_latch_rst
Latch Reset register
write-one-to-clear latch (confirms edge-triggered and software IRQ)
W
0x00000000
Address@sms_host_irq_logic : 0x60180410
Address@sms_device_irq_logic : 0x601b0010
Bits Reset value Name Description
31 - 0 0x0
rst
Clear latch request for IRQ vector
the hardware will automatically reset this bit


sms_irq_logic_latch_set
Latch Set register
write-one-to-set latch to stimulate software IRQ (write-only)
W
0x00000000
Address@sms_host_irq_logic : 0x60180414
Address@sms_device_irq_logic : 0x601b0014
Bits Reset value Name Description
31 - 0 0x0
set
Set latch request for IRQ vector
the hardware will automatically reset this bit


sms_irq_logic_mask_rst
Mask Reset register
write-one-to-clear-mask (write-only)
W
0x00000000
Address@sms_host_irq_logic : 0x60180418
Address@sms_device_irq_logic : 0x601b0018
Bits Reset value Name Description
31 - 0 0x0
msk_rst
Clear mask of IRQ vector
the hardware will automatically reset this bit


sms_irq_logic_mask_set
Mask Set register
write-one-to-set-mask (write-only)
W
0x00000000
Address@sms_host_irq_logic : 0x6018041c
Address@sms_device_irq_logic : 0x601b001c
Bits Reset value Name Description
31 - 0 0x0
msk_set
Set mask of IRQ vector
the hardware will automatically reset this bit


sms_irq_logic_is_edge
IRQ IS_EDGE configuration register
One bit controlling edge-detection per input - also see pending
If enabled for the IRQ, latch[n] will be set when a high level is detected on the input[n]
R/W
0x00000000
Address@sms_host_irq_logic : 0x60180420
Address@sms_device_irq_logic : 0x601b0020
Bits Reset value Name Description
31 - 0 0x0
cfg
Configuration vector to enable edge detection via latch per bit



Base Address Area: sms_host_tba

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R sms_tba_slv_0_status
1 4 -  reserved
2 8 R/W sms_tba_slv_0_action
3 c -  reserved
4 10 R/W sms_tba_slv_0_ctrl
5-3f 14-fc -  reserved

sms_tba_slv_0_status
SMS_TBA_SLV_0_STATUS
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the status of
TBA no. 4, calculate: 4*32
R
Address : 0x60181000
Bits Name Description
31 - 16 -
 reserved
15 master_is_consumer
0: master is producer
1: master is consumer
14 - 12 bal_pre_master
state of the balance counter immediately before the last master action
11 - 9 bal_pre_slave
state of the balance counter immediately before the last slave action
8 - 6 bal
signed & saturated balance counter
< 0 : underrun
  0 : empty
  1 : full
> 1 : overrun
5 - 4 master_idx
number of the buffer owned by the master
3 - 2 mid_idx
number of the free buffer
1 - 0 slave_idx
number of the buffer owned by the slave


sms_tba_slv_0_action
SMS_TBA_SLV_0_ACTION
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the action register of
TBA no. 4, calculate: 4*32 + 8
R/W
0x00000000
Address : 0x60181008
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
tgl_slave
Toggling this bit executes the action for the slave
swap TBA_STATUS.slave_idx with TBA_STATUS.mid_idx and
modify the balance counter:
master_is_consumer == 0: fetch (consumer)
master_is_consumer == 1: commit (producer)


sms_tba_slv_0_ctrl
SMS_TBA_SLV_0_CTRL
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the ctrl register of
TBA no. 4, calculate: 4*32 + 16
R/W
0x00000000
Address : 0x60181010
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
slv_irq_en
Setting this bit enables the slave IRQ



Base Address Area: sms_host_cfg_regs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_host_cfg_device_reset
1 4 R/W sms_host_cfg_device_reset_excl_pcie
2 8 R sms_host_cfg_capabilities
3 c -  reserved

sms_host_cfg_device_reset
Host-side device netX reset request
R/W
0x00000000
Address : 0x60182000
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
reset_key
Reset key sequence register.
The reset requested by this register is gated by the sms_host_cfg_capabilities.reset bit.
A netx hardware reset is generated if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The reset request is internally a level-signal, not only a pulse.
   If the reset request is disabled globally but issued by the module there are two
   possibilities to get out of this:
   1.: Enable the reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this register area. This will clear the
reset FSM and the reset request of this module to the global reset controller.


sms_host_cfg_device_reset_excl_pcie
Host-side device netX reset request without pcie
R/W
0x00000000
Address : 0x60182004
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
reset_key
Reset key sequence register.
The reset requested by this register is gated by the sms_host_cfg_capabilities.reset_excl_pcie bit.
A netx hardware reset is generated, excluding PCIE, if the following sequence is written to this register:
  1st access: write 0x00
  2nd access: write 0x01
  3rd access: write 0x03
  4th access: write 0x07
  5th access: write 0x0f
  6th access: write 0x1f
  7th access: write 0x3f
  8th access: write 0x7f
To issue a reset the sequence must not be interrupted by a write access to another register
of this module register area. Writing 0x00 will always restart the sequence.
Reading this register will always provide the next write data. Hence it is also possible
performing 8 times a read-write sequence to this register (however this is not required,
simply writing the sequence will also succeed).
Writing any other value than the next expected module, the internal reset FSM will
be cleared and the register will return 0x00 for the next read. The FSM will also be cleared
if the sequence is interrupted by a write access to any other register of this register
area. The sequence must be restarted with the 1st access (writing 0x00) in this case.
Note:
   The reset request is internally a level-signal, not only a pulse.
   If the reset request is disabled globally but issued by the module there are two
   possibilities to get out of this:
   1.: Enable the reset in the global reset controller. The NETX will be reset then
immediately (typically this must be done by the NETX-side CPU and cannot be done by a host).
   2.:
Write 0x00 (or any other value except 0xFF) to this register or perform a write
access to any other register of this register area. This will clear the
reset FSM and the reset request of this module to the global reset controller.


sms_host_cfg_capabilities
Host capabilities register
R
Address : 0x60182008
Bits Name Description
31 - 2 -
 reserved
1 reset_excl_pcie
If this bit is set, the device side allowed hosts to trigger a netX reset without losing the active PCIe link.
0 reset
If this bit is set, the device side allowed hosts to trigger a netX-wide reset



Base Address Area: sms_host_irq_router_pcie_int_a_0

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_host_irq_router_pcie_int_a_0_irq_raw
1 4 R/W sms_host_irq_router_pcie_int_a_0_irq_masked
2 8 R/W sms_host_irq_router_pcie_int_a_0_irq_mask_set
3 c R/W sms_host_irq_router_pcie_int_a_0_irq_mask_rst

sms_host_irq_router_pcie_int_a_0_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x6018f000
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ int_a[0]
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ int_a[0]
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ int_a[0]
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ int_a[0]
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ int_a[0]
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ int_a[0]
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ int_a[0]
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ int_a[0]
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ int_a[0]
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ int_a[0]
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ int_a[0]
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ int_a[0]
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ int_a[0]
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ int_a[0]
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ int_a[0]
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ int_a[0]
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ int_a[0]
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ int_a[0]
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ int_a[0]
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ int_a[0]
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ int_a[0]
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ int_a[0]
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ int_a[0]
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ int_a[0]
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ int_a[0]
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ int_a[0]
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ int_a[0]
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ int_a[0]
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ int_a[0]
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ int_a[0]
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ int_a[0]
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ int_a[0]


sms_host_irq_router_pcie_int_a_0_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sms_host_irq_router_pcie_int_a_0_irq_raw).
R/W
0x00000000
Address : 0x6018f004
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ int_a[0]
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ int_a[0]
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ int_a[0]
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ int_a[0]
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ int_a[0]
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ int_a[0]
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ int_a[0]
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ int_a[0]
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ int_a[0]
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ int_a[0]
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ int_a[0]
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ int_a[0]
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ int_a[0]
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ int_a[0]
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ int_a[0]
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ int_a[0]
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ int_a[0]
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ int_a[0]
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ int_a[0]
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ int_a[0]
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ int_a[0]
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ int_a[0]
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ int_a[0]
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ int_a[0]
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ int_a[0]
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ int_a[0]
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ int_a[0]
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ int_a[0]
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ int_a[0]
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ int_a[0]
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ int_a[0]
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ int_a[0]


sms_host_irq_router_pcie_int_a_0_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sms_host_irq_router_pcie_int_a_0_irq_raw
R/W
0x00000000
Address : 0x6018f008
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ int_a[0]
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ int_a[0]
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ int_a[0]
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ int_a[0]
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ int_a[0]
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ int_a[0]
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ int_a[0]
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ int_a[0]
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ int_a[0]
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ int_a[0]
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ int_a[0]
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ int_a[0]
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ int_a[0]
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ int_a[0]
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ int_a[0]
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ int_a[0]
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ int_a[0]
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ int_a[0]
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ int_a[0]
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ int_a[0]
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ int_a[0]
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ int_a[0]
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ int_a[0]
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ int_a[0]
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ int_a[0]
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ int_a[0]
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ int_a[0]
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ int_a[0]
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ int_a[0]
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ int_a[0]
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ int_a[0]
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ int_a[0]


sms_host_irq_router_pcie_int_a_0_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : int_a_0_irq-host_irq_vector_0
  1  : int_a_0_irq-host_irq_vector_1
  2  : int_a_0_irq-host_irq_vector_2
  3  : int_a_0_irq-host_irq_vector_3
  4  : int_a_0_irq-host_irq_vector_4
  5  : int_a_0_irq-host_irq_vector_5
  6  : int_a_0_irq-host_irq_vector_6
  7  : int_a_0_irq-host_irq_vector_7
  8  : int_a_0_irq-host_irq_vector_8
  9  : int_a_0_irq-host_irq_vector_9
  10 : int_a_0_irq-host_irq_vector_10
  11 : int_a_0_irq-host_irq_vector_11
  12 : int_a_0_irq-host_irq_vector_12
  13 : int_a_0_irq-host_irq_vector_13
  14 : int_a_0_irq-host_irq_vector_14
  15 : int_a_0_irq-host_irq_vector_15
  16 : int_a_0_irq-host_irq_vector_16
  17 : int_a_0_irq-host_irq_vector_17
  18 : int_a_0_irq-host_irq_vector_18
  19 : int_a_0_irq-host_irq_vector_19
  20 : int_a_0_irq-host_irq_vector_20
  21 : int_a_0_irq-host_irq_vector_21
  22 : int_a_0_irq-host_irq_vector_22
  23 : int_a_0_irq-host_irq_vector_23
  24 : int_a_0_irq-host_irq_vector_24
  25 : int_a_0_irq-host_irq_vector_25
  26 : int_a_0_irq-host_irq_vector_26
  27 : int_a_0_irq-host_irq_vector_27
  28 : int_a_0_irq-host_irq_vector_28
  29 : int_a_0_irq-host_irq_vector_29
  30 : int_a_0_irq-host_irq_vector_30
  31 : int_a_0_irq-host_irq_vector_31
  32 : no active IRQ
R/W
0x00000000
Address : 0x6018f00c
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ int_a[0]
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ int_a[0]
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ int_a[0]
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ int_a[0]
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ int_a[0]
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ int_a[0]
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ int_a[0]
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ int_a[0]
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ int_a[0]
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ int_a[0]
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ int_a[0]
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ int_a[0]
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ int_a[0]
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ int_a[0]
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ int_a[0]
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ int_a[0]
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ int_a[0]
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ int_a[0]
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ int_a[0]
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ int_a[0]
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ int_a[0]
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ int_a[0]
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ int_a[0]
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ int_a[0]
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ int_a[0]
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ int_a[0]
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ int_a[0]
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ int_a[0]
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ int_a[0]
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ int_a[0]
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ int_a[0]
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ int_a[0]



Base Address Area: sms_device_irq_router_ada_plic_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_device_irq_router_ada_plic_irq_irq_raw
1 4 R/W sms_device_irq_router_ada_plic_irq_irq_masked
2 8 R/W sms_device_irq_router_ada_plic_irq_irq_mask_set
3 c R/W sms_device_irq_router_ada_plic_irq_irq_mask_rst

sms_device_irq_router_ada_plic_irq_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601a0000
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_ada_plic_irq_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sms_device_irq_router_ada_plic_irq_irq_raw).
R/W
0x00000000
Address : 0x601a0004
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_ada_plic_irq_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sms_device_irq_router_ada_plic_irq_irq_raw
R/W
0x00000000
Address : 0x601a0008
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_ada_plic_irq_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : plic_irq_irq-host_irq_vector_0
  1  : plic_irq_irq-host_irq_vector_1
  2  : plic_irq_irq-host_irq_vector_2
  3  : plic_irq_irq-host_irq_vector_3
  4  : plic_irq_irq-host_irq_vector_4
  5  : plic_irq_irq-host_irq_vector_5
  6  : plic_irq_irq-host_irq_vector_6
  7  : plic_irq_irq-host_irq_vector_7
  8  : plic_irq_irq-host_irq_vector_8
  9  : plic_irq_irq-host_irq_vector_9
  10 : plic_irq_irq-host_irq_vector_10
  11 : plic_irq_irq-host_irq_vector_11
  12 : plic_irq_irq-host_irq_vector_12
  13 : plic_irq_irq-host_irq_vector_13
  14 : plic_irq_irq-host_irq_vector_14
  15 : plic_irq_irq-host_irq_vector_15
  16 : plic_irq_irq-host_irq_vector_16
  17 : plic_irq_irq-host_irq_vector_17
  18 : plic_irq_irq-host_irq_vector_18
  19 : plic_irq_irq-host_irq_vector_19
  20 : plic_irq_irq-host_irq_vector_20
  21 : plic_irq_irq-host_irq_vector_21
  22 : plic_irq_irq-host_irq_vector_22
  23 : plic_irq_irq-host_irq_vector_23
  24 : plic_irq_irq-host_irq_vector_24
  25 : plic_irq_irq-host_irq_vector_25
  26 : plic_irq_irq-host_irq_vector_26
  27 : plic_irq_irq-host_irq_vector_27
  28 : plic_irq_irq-host_irq_vector_28
  29 : plic_irq_irq-host_irq_vector_29
  30 : plic_irq_irq-host_irq_vector_30
  31 : plic_irq_irq-host_irq_vector_31
  32 : no active IRQ
R/W
0x00000000
Address : 0x601a000c
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq



Base Address Area: sms_device_irq_router_cda_rx_plic_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_device_irq_router_cda_rx_plic_irq_irq_raw
1 4 R/W sms_device_irq_router_cda_rx_plic_irq_irq_masked
2 8 R/W sms_device_irq_router_cda_rx_plic_irq_irq_mask_set
3 c R/W sms_device_irq_router_cda_rx_plic_irq_irq_mask_rst

sms_device_irq_router_cda_rx_plic_irq_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601a1000
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_rx_plic_irq_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sms_device_irq_router_cda_rx_plic_irq_irq_raw).
R/W
0x00000000
Address : 0x601a1004
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_rx_plic_irq_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sms_device_irq_router_cda_rx_plic_irq_irq_raw
R/W
0x00000000
Address : 0x601a1008
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_rx_plic_irq_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : plic_irq_irq-host_irq_vector_0
  1  : plic_irq_irq-host_irq_vector_1
  2  : plic_irq_irq-host_irq_vector_2
  3  : plic_irq_irq-host_irq_vector_3
  4  : plic_irq_irq-host_irq_vector_4
  5  : plic_irq_irq-host_irq_vector_5
  6  : plic_irq_irq-host_irq_vector_6
  7  : plic_irq_irq-host_irq_vector_7
  8  : plic_irq_irq-host_irq_vector_8
  9  : plic_irq_irq-host_irq_vector_9
  10 : plic_irq_irq-host_irq_vector_10
  11 : plic_irq_irq-host_irq_vector_11
  12 : plic_irq_irq-host_irq_vector_12
  13 : plic_irq_irq-host_irq_vector_13
  14 : plic_irq_irq-host_irq_vector_14
  15 : plic_irq_irq-host_irq_vector_15
  16 : plic_irq_irq-host_irq_vector_16
  17 : plic_irq_irq-host_irq_vector_17
  18 : plic_irq_irq-host_irq_vector_18
  19 : plic_irq_irq-host_irq_vector_19
  20 : plic_irq_irq-host_irq_vector_20
  21 : plic_irq_irq-host_irq_vector_21
  22 : plic_irq_irq-host_irq_vector_22
  23 : plic_irq_irq-host_irq_vector_23
  24 : plic_irq_irq-host_irq_vector_24
  25 : plic_irq_irq-host_irq_vector_25
  26 : plic_irq_irq-host_irq_vector_26
  27 : plic_irq_irq-host_irq_vector_27
  28 : plic_irq_irq-host_irq_vector_28
  29 : plic_irq_irq-host_irq_vector_29
  30 : plic_irq_irq-host_irq_vector_30
  31 : plic_irq_irq-host_irq_vector_31
  32 : no active IRQ
R/W
0x00000000
Address : 0x601a100c
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq



Base Address Area: sms_device_irq_router_cda_tx_plic_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_device_irq_router_cda_tx_plic_irq_irq_raw
1 4 R/W sms_device_irq_router_cda_tx_plic_irq_irq_masked
2 8 R/W sms_device_irq_router_cda_tx_plic_irq_irq_mask_set
3 c R/W sms_device_irq_router_cda_tx_plic_irq_irq_mask_rst

sms_device_irq_router_cda_tx_plic_irq_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601a2000
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_tx_plic_irq_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sms_device_irq_router_cda_tx_plic_irq_irq_raw).
R/W
0x00000000
Address : 0x601a2004
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_tx_plic_irq_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sms_device_irq_router_cda_tx_plic_irq_irq_raw
R/W
0x00000000
Address : 0x601a2008
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_cda_tx_plic_irq_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : plic_irq_irq-host_irq_vector_0
  1  : plic_irq_irq-host_irq_vector_1
  2  : plic_irq_irq-host_irq_vector_2
  3  : plic_irq_irq-host_irq_vector_3
  4  : plic_irq_irq-host_irq_vector_4
  5  : plic_irq_irq-host_irq_vector_5
  6  : plic_irq_irq-host_irq_vector_6
  7  : plic_irq_irq-host_irq_vector_7
  8  : plic_irq_irq-host_irq_vector_8
  9  : plic_irq_irq-host_irq_vector_9
  10 : plic_irq_irq-host_irq_vector_10
  11 : plic_irq_irq-host_irq_vector_11
  12 : plic_irq_irq-host_irq_vector_12
  13 : plic_irq_irq-host_irq_vector_13
  14 : plic_irq_irq-host_irq_vector_14
  15 : plic_irq_irq-host_irq_vector_15
  16 : plic_irq_irq-host_irq_vector_16
  17 : plic_irq_irq-host_irq_vector_17
  18 : plic_irq_irq-host_irq_vector_18
  19 : plic_irq_irq-host_irq_vector_19
  20 : plic_irq_irq-host_irq_vector_20
  21 : plic_irq_irq-host_irq_vector_21
  22 : plic_irq_irq-host_irq_vector_22
  23 : plic_irq_irq-host_irq_vector_23
  24 : plic_irq_irq-host_irq_vector_24
  25 : plic_irq_irq-host_irq_vector_25
  26 : plic_irq_irq-host_irq_vector_26
  27 : plic_irq_irq-host_irq_vector_27
  28 : plic_irq_irq-host_irq_vector_28
  29 : plic_irq_irq-host_irq_vector_29
  30 : plic_irq_irq-host_irq_vector_30
  31 : plic_irq_irq-host_irq_vector_31
  32 : no active IRQ
R/W
0x00000000
Address : 0x601a200c
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq



Base Address Area: sms_device_irq_router_iol_plic_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_device_irq_router_iol_plic_irq_irq_raw
1 4 R/W sms_device_irq_router_iol_plic_irq_irq_masked
2 8 R/W sms_device_irq_router_iol_plic_irq_irq_mask_set
3 c R/W sms_device_irq_router_iol_plic_irq_irq_mask_rst

sms_device_irq_router_iol_plic_irq_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601a3000
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_iol_plic_irq_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_sms_device_irq_router_iol_plic_irq_irq_raw).
R/W
0x00000000
Address : 0x601a3004
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_iol_plic_irq_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_sms_device_irq_router_iol_plic_irq_irq_raw
R/W
0x00000000
Address : 0x601a3008
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq


sms_device_irq_router_iol_plic_irq_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : plic_irq_irq-host_irq_vector_0
  1  : plic_irq_irq-host_irq_vector_1
  2  : plic_irq_irq-host_irq_vector_2
  3  : plic_irq_irq-host_irq_vector_3
  4  : plic_irq_irq-host_irq_vector_4
  5  : plic_irq_irq-host_irq_vector_5
  6  : plic_irq_irq-host_irq_vector_6
  7  : plic_irq_irq-host_irq_vector_7
  8  : plic_irq_irq-host_irq_vector_8
  9  : plic_irq_irq-host_irq_vector_9
  10 : plic_irq_irq-host_irq_vector_10
  11 : plic_irq_irq-host_irq_vector_11
  12 : plic_irq_irq-host_irq_vector_12
  13 : plic_irq_irq-host_irq_vector_13
  14 : plic_irq_irq-host_irq_vector_14
  15 : plic_irq_irq-host_irq_vector_15
  16 : plic_irq_irq-host_irq_vector_16
  17 : plic_irq_irq-host_irq_vector_17
  18 : plic_irq_irq-host_irq_vector_18
  19 : plic_irq_irq-host_irq_vector_19
  20 : plic_irq_irq-host_irq_vector_20
  21 : plic_irq_irq-host_irq_vector_21
  22 : plic_irq_irq-host_irq_vector_22
  23 : plic_irq_irq-host_irq_vector_23
  24 : plic_irq_irq-host_irq_vector_24
  25 : plic_irq_irq-host_irq_vector_25
  26 : plic_irq_irq-host_irq_vector_26
  27 : plic_irq_irq-host_irq_vector_27
  28 : plic_irq_irq-host_irq_vector_28
  29 : plic_irq_irq-host_irq_vector_29
  30 : plic_irq_irq-host_irq_vector_30
  31 : plic_irq_irq-host_irq_vector_31
  32 : no active IRQ
R/W
0x00000000
Address : 0x601a300c
Bits Reset value Name Description
31 "0"
host_irq_vector_31
EVENT host_irq_vector[31] contribution to IRQ plic_irq
30 "0"
host_irq_vector_30
EVENT host_irq_vector[30] contribution to IRQ plic_irq
29 "0"
host_irq_vector_29
EVENT host_irq_vector[29] contribution to IRQ plic_irq
28 "0"
host_irq_vector_28
EVENT host_irq_vector[28] contribution to IRQ plic_irq
27 "0"
host_irq_vector_27
EVENT host_irq_vector[27] contribution to IRQ plic_irq
26 "0"
host_irq_vector_26
EVENT host_irq_vector[26] contribution to IRQ plic_irq
25 "0"
host_irq_vector_25
EVENT host_irq_vector[25] contribution to IRQ plic_irq
24 "0"
host_irq_vector_24
EVENT host_irq_vector[24] contribution to IRQ plic_irq
23 "0"
host_irq_vector_23
EVENT host_irq_vector[23] contribution to IRQ plic_irq
22 "0"
host_irq_vector_22
EVENT host_irq_vector[22] contribution to IRQ plic_irq
21 "0"
host_irq_vector_21
EVENT host_irq_vector[21] contribution to IRQ plic_irq
20 "0"
host_irq_vector_20
EVENT host_irq_vector[20] contribution to IRQ plic_irq
19 "0"
host_irq_vector_19
EVENT host_irq_vector[19] contribution to IRQ plic_irq
18 "0"
host_irq_vector_18
EVENT host_irq_vector[18] contribution to IRQ plic_irq
17 "0"
host_irq_vector_17
EVENT host_irq_vector[17] contribution to IRQ plic_irq
16 "0"
host_irq_vector_16
EVENT host_irq_vector[16] contribution to IRQ plic_irq
15 "0"
host_irq_vector_15
EVENT host_irq_vector[15] contribution to IRQ plic_irq
14 "0"
host_irq_vector_14
EVENT host_irq_vector[14] contribution to IRQ plic_irq
13 "0"
host_irq_vector_13
EVENT host_irq_vector[13] contribution to IRQ plic_irq
12 "0"
host_irq_vector_12
EVENT host_irq_vector[12] contribution to IRQ plic_irq
11 "0"
host_irq_vector_11
EVENT host_irq_vector[11] contribution to IRQ plic_irq
10 "0"
host_irq_vector_10
EVENT host_irq_vector[10] contribution to IRQ plic_irq
9 "0"
host_irq_vector_9
EVENT host_irq_vector[9] contribution to IRQ plic_irq
8 "0"
host_irq_vector_8
EVENT host_irq_vector[8] contribution to IRQ plic_irq
7 "0"
host_irq_vector_7
EVENT host_irq_vector[7] contribution to IRQ plic_irq
6 "0"
host_irq_vector_6
EVENT host_irq_vector[6] contribution to IRQ plic_irq
5 "0"
host_irq_vector_5
EVENT host_irq_vector[5] contribution to IRQ plic_irq
4 "0"
host_irq_vector_4
EVENT host_irq_vector[4] contribution to IRQ plic_irq
3 "0"
host_irq_vector_3
EVENT host_irq_vector[3] contribution to IRQ plic_irq
2 "0"
host_irq_vector_2
EVENT host_irq_vector[2] contribution to IRQ plic_irq
1 "0"
host_irq_vector_1
EVENT host_irq_vector[1] contribution to IRQ plic_irq
0 "0"
host_irq_vector_0
EVENT host_irq_vector[0] contribution to IRQ plic_irq



Base Address Area: sms_device_irq

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R sms_device_irq_pending
1 4 R sms_device_irq_pending_masked
2 8 R sms_device_irq_latch_state
3 c R sms_device_irq_mask_state
4 10 W sms_device_irq_latch_rst
5 14 W sms_device_irq_latch_set
6 18 W sms_device_irq_mask_rst
7 1c W sms_device_irq_mask_set
8 20 R/W sms_device_irq_is_edge
9-f 24-3c -  reserved

sms_device_irq_pending
Device IRQ pending register
pending[n] <= input[n] | latch[n]
R
Address : 0x601b0000
Bits Name Description
31 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 tbuf_tx_prod_err
TBUF_TX producer error IRQ
18 tbuf_tx_cons_err
TBUF_TX consumer error IRQ
17 tbuf_rx_prod_err
TBUF_RX producer error IRQ
16 tbuf_rx_cons_err
TBUF_RX consumer error IRQ
15 - 12 tbuf_tx_cons
TBUF_TX consumer IRQ
11 - 8 tbuf_rx_prod
TBUF_RX producer IRQ
7 - 0 hsc
HSC[15..8] IRQ


sms_device_irq_pending_masked
Device Pending Masked register
pending & mask IRQ vector
R
Address : 0x601b0004
Bits Name Description
31 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 tbuf_tx_prod_err
TBUF_TX producer error IRQ
18 tbuf_tx_cons_err
TBUF_TX consumer error IRQ
17 tbuf_rx_prod_err
TBUF_RX producer error IRQ
16 tbuf_rx_cons_err
TBUF_RX consumer error IRQ
15 - 12 tbuf_tx_cons
TBUF_TX consumer IRQ
11 - 8 tbuf_rx_prod
TBUF_RX producer IRQ
7 - 0 hsc
HSC[15..8] IRQ


sms_device_irq_latch_state
Device Latch State register
Current latch state
R
Address : 0x601b0008
Bits Name Description
31 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 tbuf_tx_prod_err
TBUF_TX producer error IRQ
18 tbuf_tx_cons_err
TBUF_TX consumer error IRQ
17 tbuf_rx_prod_err
TBUF_RX producer error IRQ
16 tbuf_rx_cons_err
TBUF_RX consumer error IRQ
15 - 12 tbuf_tx_cons
TBUF_TX consumer IRQ
11 - 8 tbuf_rx_prod
TBUF_RX producer IRQ
7 - 0 hsc
HSC[15..8] IRQ


sms_device_irq_mask_state
Device Mask State register
Current mask state
R
Address : 0x601b000c
Bits Name Description
31 - 28 sw
Software IRQ
27 - 20 tba
TBA IRQ
19 tbuf_tx_prod_err
TBUF_TX producer error IRQ
18 tbuf_tx_cons_err
TBUF_TX consumer error IRQ
17 tbuf_rx_prod_err
TBUF_RX producer error IRQ
16 tbuf_rx_cons_err
TBUF_RX consumer error IRQ
15 - 12 tbuf_tx_cons
TBUF_TX consumer IRQ
11 - 8 tbuf_rx_prod
TBUF_RX producer IRQ
7 - 0 hsc
HSC[15..8] IRQ


sms_device_irq_latch_rst
Device Latch Reset register
write-one-to-clear latch (confirms edge-triggered and software IRQ)
W
0x00000000
Address : 0x601b0010
Bits Reset value Name Description
31 - 28 "0000"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 "0"
tbuf_tx_prod_err
TBUF_TX producer error IRQ
the hardware will automatically reset this bit
18 "0"
tbuf_tx_cons_err
TBUF_TX consumer error IRQ
the hardware will automatically reset this bit
17 "0"
tbuf_rx_prod_err
TBUF_RX producer error IRQ
the hardware will automatically reset this bit
16 "0"
tbuf_rx_cons_err
TBUF_RX consumer error IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_cons
TBUF_TX consumer IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_prod
TBUF_RX producer IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC[15..8] IRQ
the hardware will automatically reset this bit


sms_device_irq_latch_set
Device Latch Set register
write-one-to-set latch to stimulate software IRQ (write-only)
W
0x00000000
Address : 0x601b0014
Bits Reset value Name Description
31 - 28 "0000"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 "0"
tbuf_tx_prod_err
TBUF_TX producer error IRQ
the hardware will automatically reset this bit
18 "0"
tbuf_tx_cons_err
TBUF_TX consumer error IRQ
the hardware will automatically reset this bit
17 "0"
tbuf_rx_prod_err
TBUF_RX producer error IRQ
the hardware will automatically reset this bit
16 "0"
tbuf_rx_cons_err
TBUF_RX consumer error IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_cons
TBUF_TX consumer IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_prod
TBUF_RX producer IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC[15..8] IRQ
the hardware will automatically reset this bit


sms_device_irq_mask_rst
Device Mask Reset register
write-one-to-clear-mask (write-only)
W
0x00000000
Address : 0x601b0018
Bits Reset value Name Description
31 - 28 "0000"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 "0"
tbuf_tx_prod_err
TBUF_TX producer error IRQ
the hardware will automatically reset this bit
18 "0"
tbuf_tx_cons_err
TBUF_TX consumer error IRQ
the hardware will automatically reset this bit
17 "0"
tbuf_rx_prod_err
TBUF_RX producer error IRQ
the hardware will automatically reset this bit
16 "0"
tbuf_rx_cons_err
TBUF_RX consumer error IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_cons
TBUF_TX consumer IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_prod
TBUF_RX producer IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC[15..8] IRQ
the hardware will automatically reset this bit


sms_device_irq_mask_set
Device Mask Set register
write-one-to-set-mask (write-only)
W
0x00000000
Address : 0x601b001c
Bits Reset value Name Description
31 - 28 "0000"
sw
Software IRQ
the hardware will automatically reset this bit
27 - 20 "00000000"
tba
TBA IRQ
the hardware will automatically reset this bit
19 "0"
tbuf_tx_prod_err
TBUF_TX producer error IRQ
the hardware will automatically reset this bit
18 "0"
tbuf_tx_cons_err
TBUF_TX consumer error IRQ
the hardware will automatically reset this bit
17 "0"
tbuf_rx_prod_err
TBUF_RX producer error IRQ
the hardware will automatically reset this bit
16 "0"
tbuf_rx_cons_err
TBUF_RX consumer error IRQ
the hardware will automatically reset this bit
15 - 12 "0000"
tbuf_tx_cons
TBUF_TX consumer IRQ
the hardware will automatically reset this bit
11 - 8 "0000"
tbuf_rx_prod
TBUF_RX producer IRQ
the hardware will automatically reset this bit
7 - 0 "00000000"
hsc
HSC[15..8] IRQ
the hardware will automatically reset this bit


sms_device_irq_is_edge
Device IRQ IS_EDGE configuration register
One bit controlling edge-detection per input - also see pending
If enabled for the IRQ, latch[n] will be set when a high level is detected on the input[n]
R/W
0x00000000
Address : 0x601b0020
Bits Reset value Name Description
31 - 28 "0000"
sw
Software IRQ
27 - 20 "00000000"
tba
TBA IRQ
19 "0"
tbuf_tx_prod_err
TBUF_TX producer error IRQ
18 "0"
tbuf_tx_cons_err
TBUF_TX consumer error IRQ
17 "0"
tbuf_rx_prod_err
TBUF_RX producer error IRQ
16 "0"
tbuf_rx_cons_err
TBUF_RX consumer error IRQ
15 - 12 "0000"
tbuf_tx_cons
TBUF_TX consumer IRQ
11 - 8 "0000"
tbuf_rx_prod
TBUF_RX producer IRQ
7 - 0 "00000000"
hsc
HSC[15..8] IRQ



Base Address Area: sms_tbuf_rx, sms_tbuf_tx

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_tbuf0_prod_start
1 4 R/W sms_tbuf0_prod_start_action_cfg
2 8 R/W sms_tbuf0_prod_end
3 c R/W sms_tbuf0_prod_end_action_cfg
4 10 R/W sms_tbuf0_cons_start
5 14 R/W sms_tbuf0_cons_start_action_cfg
6 18 R/W sms_tbuf0_cons_end
7 1c R/W sms_tbuf0_cons_end_action_cfg
8 20 R/W sms_tbuf0_prod_offset_0
9 24 R/W sms_tbuf0_cons_offset_0
a 28 R/W sms_tbuf0_prod_offset_1
b 2c R/W sms_tbuf0_cons_offset_1
c 30 R/W sms_tbuf0_prod_offset_2
d 34 R/W sms_tbuf0_cons_offset_2
e 38 R/W sms_tbuf0_trigger
f 3c R/W sms_tbuf0_state
10 40 R/W sms_tbuf0_cfg
11 44 R/W sms_tbuf1_prod_start
12 48 R/W sms_tbuf1_prod_start_action_cfg
13 4c R/W sms_tbuf1_prod_end
14 50 R/W sms_tbuf1_prod_end_action_cfg
15 54 R/W sms_tbuf1_cons_start
16 58 R/W sms_tbuf1_cons_start_action_cfg
17 5c R/W sms_tbuf1_cons_end
18 60 R/W sms_tbuf1_cons_end_action_cfg
19 64 R/W sms_tbuf1_prod_offset_0
1a 68 R/W sms_tbuf1_cons_offset_0
1b 6c R/W sms_tbuf1_prod_offset_1
1c 70 R/W sms_tbuf1_cons_offset_1
1d 74 R/W sms_tbuf1_prod_offset_2
1e 78 R/W sms_tbuf1_cons_offset_2
1f 7c R/W sms_tbuf1_trigger
20 80 R/W sms_tbuf1_state
21 84 R/W sms_tbuf1_cfg
22 88 R/W sms_tbuf2_prod_start
23 8c R/W sms_tbuf2_prod_start_action_cfg
24 90 R/W sms_tbuf2_prod_end
25 94 R/W sms_tbuf2_prod_end_action_cfg
26 98 R/W sms_tbuf2_cons_start
27 9c R/W sms_tbuf2_cons_start_action_cfg
28 a0 R/W sms_tbuf2_cons_end
29 a4 R/W sms_tbuf2_cons_end_action_cfg
2a a8 R/W sms_tbuf2_prod_offset_0
2b ac R/W sms_tbuf2_cons_offset_0
2c b0 R/W sms_tbuf2_prod_offset_1
2d b4 R/W sms_tbuf2_cons_offset_1
2e b8 R/W sms_tbuf2_prod_offset_2
2f bc R/W sms_tbuf2_cons_offset_2
30 c0 R/W sms_tbuf2_trigger
31 c4 R/W sms_tbuf2_state
32 c8 R/W sms_tbuf2_cfg
33 cc R/W sms_tbuf3_prod_start
34 d0 R/W sms_tbuf3_prod_start_action_cfg
35 d4 R/W sms_tbuf3_prod_end
36 d8 R/W sms_tbuf3_prod_end_action_cfg
37 dc R/W sms_tbuf3_cons_start
38 e0 R/W sms_tbuf3_cons_start_action_cfg
39 e4 R/W sms_tbuf3_cons_end
3a e8 R/W sms_tbuf3_cons_end_action_cfg
3b ec R/W sms_tbuf3_prod_offset_0
3c f0 R/W sms_tbuf3_cons_offset_0
3d f4 R/W sms_tbuf3_prod_offset_1
3e f8 R/W sms_tbuf3_cons_offset_1
3f fc R/W sms_tbuf3_prod_offset_2
40 100 R/W sms_tbuf3_cons_offset_2
41 104 R/W sms_tbuf3_trigger
42 108 R/W sms_tbuf3_state
43 10c R/W sms_tbuf3_cfg
44 110 R sms_tbuf_all_state_0
45 114 R sms_tbuf_all_state_error_0
46-7f 118-1fc -  reserved

sms_tbuf0_prod_start
sms_tbuf producer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0200
Address@sms_tbuf_tx : 0x601b0400
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of producer buffer.
Transactions addressing between buf0_prod_start.adr and buf0_prod_end.adr
are identified as producer transactions to buffer number 0.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf0_prod_start_action_cfg
sms_tbuf producer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0204
Address@sms_tbuf_tx : 0x601b0404
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf0_state.prod_err
1*: clears buf0_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf0_prod_end
sms_tbuf producer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0208
Address@sms_tbuf_tx : 0x601b0408
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of producer buffer.
Transactions addressing between buf0_prod_end.adr and buf0_prod_end.adr
are identified as producer transactions to buffer number 0.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf0_prod_end_action_cfg
sms_tbuf producer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b020c
Address@sms_tbuf_tx : 0x601b040c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf0_state.prod_err
1*: clears buf0_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf0_cons_start
sms_tbuf consumer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0210
Address@sms_tbuf_tx : 0x601b0410
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of consumer buffer.
Transactions addressing between buf0_cons_start.adr and buf0_cons_start.adr
are identified as consumer transactions to buffer number 0.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf0_cons_start_action_cfg
sms_tbuf consumer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0214
Address@sms_tbuf_tx : 0x601b0414
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf0_state.prod_err
1*: clears buf0_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf0_cons_end
sms_tbuf consumer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0218
Address@sms_tbuf_tx : 0x601b0418
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of consumer buffer.
Transactions addressing between buf0_cons_end.adr and buf0_cons_end.adr
are identified as consumer transactions to buffer number 0.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf0_cons_end_action_cfg
sms_tbuf consumer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b021c
Address@sms_tbuf_tx : 0x601b041c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf0_state.prod_err
1*: clears buf0_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf0_prod_offset_0
sms_tbuf producer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0220
Address@sms_tbuf_tx : 0x601b0420
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 0(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf0_cons_offset_0
sms_tbuf consumer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0224
Address@sms_tbuf_tx : 0x601b0424
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 0(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf0_prod_offset_1
sms_tbuf producer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0228
Address@sms_tbuf_tx : 0x601b0428
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 0(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf0_cons_offset_1
sms_tbuf consumer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b022c
Address@sms_tbuf_tx : 0x601b042c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 0(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf0_prod_offset_2
sms_tbuf producer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0230
Address@sms_tbuf_tx : 0x601b0430
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 0(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf0_cons_offset_2
sms_tbuf consumer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0234
Address@sms_tbuf_tx : 0x601b0434
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 0(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf0_trigger
Trigger register
This register allows the triggering of buffer mechanisms (lock/unlock/commit/fetch). Balance and IRQ state are updated as if the boundary actions would be used.
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0238
Address@sms_tbuf_tx : 0x601b0438
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
tgl_cond_en
1: Enables the toggle condition. The operation specified in bits [3:0] in this register during
a write is only executed, when the tgl bitfield changes.
0: Operations are always executed, regardless of the tgl_bit state or the write payload to this trigger register.
16 "0"
tgl
tgl bit for the trigger register. See tgl_cond_en.
15 - 4 0
-
 reserved
3 "0"
unlock_cons
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as consumer
2 "0"
unlock_prod
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as producer
1 "0"
fetch_lock_cons
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Fetch
When in SINGLE_BUFFER_MODE: Lock as consumer
0 "0"
commit_lock_prod
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Commit
When in SINGLE_BUFFER_MODE: Lock as producer


sms_tbuf0_state
sms_tbuf state register (only 32bit write allowed!)
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b023c
Address@sms_tbuf_tx : 0x601b043c
Bits Reset value Name Description
31 "0"
prod_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
30 "0"
cons_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
29 "0"
prod_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
28 "0"
cons_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
27 "0"
locked_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
26 "0"
bal_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
25 "0"
cons_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
24 "0"
mid_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
23 "0"
prod_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
22 "0"
bal_latched_mask
writable, but can also be changed by hardware
1: fields 'bal_prod' and 'bal_cons' are written
0: write value of fields are ignored
21 - 19 "000"
bal_prod
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last producer action.
18 - 16 "000"
bal_cons
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last consumer action.
15 "0"
prod_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
prod_seq_err is asserted, when a lock operation is performed on a already producer-locked buffer.
14 "0"
cons_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
cons_seq_err is asserted, when a lock operation is performed on a already consumer-locked buffer.
13 - 12 "00"
cons_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to consumer
11 - 10 "00"
mid_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to middle buffer
9 - 8 "00"
prod_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to producer
7 "0"
prod_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: prod_err is asserted when the producer accesses
(read/write to producer address range) a buffer locked by the consumer
Triple buffer mode: prod_err is asserted when the producer accesses
the buffer during the synchronization of the incremental update feature
6 "0"
cons_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: cons_err is asserted when the consumer accesses
(read/write to consumer address range) a buffer locked by the producer
5 - 4 "00"
locked
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
00: buffer not locked
01: buffer is locked by consumer (single buffer mode) or an incremental update is in progress (triple buffer mode)
10: buffer is locked by producer (single buffer mode)
11: reserved
3 - 1 "000"
bal
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
balance counter
<0 : buffer underrun - single buffer: number of locks by consumer since buffer was empty
                       triple buffer: number of fetches since buffer was empty
 0 : buffer empty    - single buffer: buffer unlocked by consumer and has been full or overrun before lock
                       triple buffer: buffer was fetched once since last commit
 1 : buffer full     - single buffer: buffer unlocked by producer and has been empty or underrun before lock
                       triple buffer: buffer was commited once since last fetch
>1 : buffer overrun  - single buffer: number of locks by producer since buffer was full
                       triple buffer: number of commits since buffer was empty
0 0
-
 reserved


sms_tbuf0_cfg
sms_tbuf config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0240
Address@sms_tbuf_tx : 0x601b0440
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
cirq_fullover
1: cirq is only asserted when the buffer is full or overrun
Note: all conditions (cirq_fullover/cirq_unlocked) must be met for cirq to be asserted
19 "0"
cirq_unlocked
1: cirq is only asserted when the buffer is unlocked
18 "0"
cirq_en
1: cirq is enabled
17 "0"
ceirq_seq_en
1: ceirq is also asserted when buf0_state.cons_seq_err is high, in addition
to the setting provided by ceirq_en
16 "0"
ceirq_en
1: ceirq is enabled -> IRQ reflects state of buf0_state.cons_err
15 - 13 0
-
 reserved
12 "0"
pirq_emptyunder
1: pirq is only asserted when the buffer is empty or underrun
Note: all conditions (pirq_emptyunder/pirq_unlocked) must be met for pirq to be asserted
11 "0"
pirq_unlocked
1: pirq is only asserted when the buffer is unlocked
10 "0"
pirq_en
1: pirq is enabled
9 "0"
peirq_seq_en
1: peirq is also asserted when buf0_state.prod_seq_err is high, in addition
to the setting provided by peirq_en
8 "0"
peirq_en
1: peirq is enabled -> IRQ reflects state of buf0_state.prod_err
7 - 2 0
-
 reserved
1 - 0 "00"
buffer_mode
00: no hw acceleration / buffer disabled
01: single buffer mode
10: triple buffer mode
11: triple buffer mode with incremental updates


sms_tbuf1_prod_start
sms_tbuf producer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0244
Address@sms_tbuf_tx : 0x601b0444
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of producer buffer.
Transactions addressing between buf1_prod_start.adr and buf1_prod_end.adr
are identified as producer transactions to buffer number 1.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf1_prod_start_action_cfg
sms_tbuf producer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0248
Address@sms_tbuf_tx : 0x601b0448
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf1_state.prod_err
1*: clears buf1_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf1_prod_end
sms_tbuf producer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b024c
Address@sms_tbuf_tx : 0x601b044c
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of producer buffer.
Transactions addressing between buf1_prod_end.adr and buf1_prod_end.adr
are identified as producer transactions to buffer number 1.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf1_prod_end_action_cfg
sms_tbuf producer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0250
Address@sms_tbuf_tx : 0x601b0450
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf1_state.prod_err
1*: clears buf1_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf1_cons_start
sms_tbuf consumer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0254
Address@sms_tbuf_tx : 0x601b0454
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of consumer buffer.
Transactions addressing between buf1_cons_start.adr and buf1_cons_start.adr
are identified as consumer transactions to buffer number 1.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf1_cons_start_action_cfg
sms_tbuf consumer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0258
Address@sms_tbuf_tx : 0x601b0458
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf1_state.prod_err
1*: clears buf1_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf1_cons_end
sms_tbuf consumer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b025c
Address@sms_tbuf_tx : 0x601b045c
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of consumer buffer.
Transactions addressing between buf1_cons_end.adr and buf1_cons_end.adr
are identified as consumer transactions to buffer number 1.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf1_cons_end_action_cfg
sms_tbuf consumer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0260
Address@sms_tbuf_tx : 0x601b0460
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf1_state.prod_err
1*: clears buf1_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf1_prod_offset_0
sms_tbuf producer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0264
Address@sms_tbuf_tx : 0x601b0464
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 1(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf1_cons_offset_0
sms_tbuf consumer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0268
Address@sms_tbuf_tx : 0x601b0468
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 1(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf1_prod_offset_1
sms_tbuf producer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b026c
Address@sms_tbuf_tx : 0x601b046c
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 1(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf1_cons_offset_1
sms_tbuf consumer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0270
Address@sms_tbuf_tx : 0x601b0470
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 1(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf1_prod_offset_2
sms_tbuf producer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0274
Address@sms_tbuf_tx : 0x601b0474
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 1(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf1_cons_offset_2
sms_tbuf consumer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0278
Address@sms_tbuf_tx : 0x601b0478
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 1(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf1_trigger
Trigger register
This register allows the triggering of buffer mechanisms (lock/unlock/commit/fetch). Balance and IRQ state are updated as if the boundary actions would be used.
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b027c
Address@sms_tbuf_tx : 0x601b047c
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
tgl_cond_en
1: Enables the toggle condition. The operation specified in bits [3:0] in this register during
a write is only executed, when the tgl bitfield changes.
0: Operations are always executed, regardless of the tgl_bit state or the write payload to this trigger register.
16 "0"
tgl
tgl bit for the trigger register. See tgl_cond_en.
15 - 4 0
-
 reserved
3 "0"
unlock_cons
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as consumer
2 "0"
unlock_prod
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as producer
1 "0"
fetch_lock_cons
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Fetch
When in SINGLE_BUFFER_MODE: Lock as consumer
0 "0"
commit_lock_prod
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Commit
When in SINGLE_BUFFER_MODE: Lock as producer


sms_tbuf1_state
sms_tbuf state register (only 32bit write allowed!)
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0280
Address@sms_tbuf_tx : 0x601b0480
Bits Reset value Name Description
31 "0"
prod_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
30 "0"
cons_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
29 "0"
prod_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
28 "0"
cons_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
27 "0"
locked_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
26 "0"
bal_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
25 "0"
cons_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
24 "0"
mid_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
23 "0"
prod_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
22 "0"
bal_latched_mask
writable, but can also be changed by hardware
1: fields 'bal_prod' and 'bal_cons' are written
0: write value of fields are ignored
21 - 19 "000"
bal_prod
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last producer action.
18 - 16 "000"
bal_cons
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last consumer action.
15 "0"
prod_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
prod_seq_err is asserted, when a lock operation is performed on a already producer-locked buffer.
14 "0"
cons_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
cons_seq_err is asserted, when a lock operation is performed on a already consumer-locked buffer.
13 - 12 "00"
cons_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to consumer
11 - 10 "00"
mid_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to middle buffer
9 - 8 "00"
prod_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to producer
7 "0"
prod_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: prod_err is asserted when the producer accesses
(read/write to producer address range) a buffer locked by the consumer
Triple buffer mode: prod_err is asserted when the producer accesses
the buffer during the synchronization of the incremental update feature
6 "0"
cons_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: cons_err is asserted when the consumer accesses
(read/write to consumer address range) a buffer locked by the producer
5 - 4 "00"
locked
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
00: buffer not locked
01: buffer is locked by consumer (single buffer mode) or an incremental update is in progress (triple buffer mode)
10: buffer is locked by producer (single buffer mode)
11: reserved
3 - 1 "000"
bal
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
balance counter
<0 : buffer underrun - single buffer: number of locks by consumer since buffer was empty
                       triple buffer: number of fetches since buffer was empty
 0 : buffer empty    - single buffer: buffer unlocked by consumer and has been full or overrun before lock
                       triple buffer: buffer was fetched once since last commit
 1 : buffer full     - single buffer: buffer unlocked by producer and has been empty or underrun before lock
                       triple buffer: buffer was commited once since last fetch
>1 : buffer overrun  - single buffer: number of locks by producer since buffer was full
                       triple buffer: number of commits since buffer was empty
0 0
-
 reserved


sms_tbuf1_cfg
sms_tbuf config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0284
Address@sms_tbuf_tx : 0x601b0484
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
cirq_fullover
1: cirq is only asserted when the buffer is full or overrun
Note: all conditions (cirq_fullover/cirq_unlocked) must be met for cirq to be asserted
19 "0"
cirq_unlocked
1: cirq is only asserted when the buffer is unlocked
18 "0"
cirq_en
1: cirq is enabled
17 "0"
ceirq_seq_en
1: ceirq is also asserted when buf1_state.cons_seq_err is high, in addition
to the setting provided by ceirq_en
16 "0"
ceirq_en
1: ceirq is enabled -> IRQ reflects state of buf1_state.cons_err
15 - 13 0
-
 reserved
12 "0"
pirq_emptyunder
1: pirq is only asserted when the buffer is empty or underrun
Note: all conditions (pirq_emptyunder/pirq_unlocked) must be met for pirq to be asserted
11 "0"
pirq_unlocked
1: pirq is only asserted when the buffer is unlocked
10 "0"
pirq_en
1: pirq is enabled
9 "0"
peirq_seq_en
1: peirq is also asserted when buf1_state.prod_seq_err is high, in addition
to the setting provided by peirq_en
8 "0"
peirq_en
1: peirq is enabled -> IRQ reflects state of buf1_state.prod_err
7 - 2 0
-
 reserved
1 - 0 "00"
buffer_mode
00: no hw acceleration / buffer disabled
01: single buffer mode
10: triple buffer mode
11: triple buffer mode with incremental updates


sms_tbuf2_prod_start
sms_tbuf producer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0288
Address@sms_tbuf_tx : 0x601b0488
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of producer buffer.
Transactions addressing between buf2_prod_start.adr and buf2_prod_end.adr
are identified as producer transactions to buffer number 2.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf2_prod_start_action_cfg
sms_tbuf producer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b028c
Address@sms_tbuf_tx : 0x601b048c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf2_state.prod_err
1*: clears buf2_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf2_prod_end
sms_tbuf producer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0290
Address@sms_tbuf_tx : 0x601b0490
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of producer buffer.
Transactions addressing between buf2_prod_end.adr and buf2_prod_end.adr
are identified as producer transactions to buffer number 2.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf2_prod_end_action_cfg
sms_tbuf producer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0294
Address@sms_tbuf_tx : 0x601b0494
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf2_state.prod_err
1*: clears buf2_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf2_cons_start
sms_tbuf consumer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b0298
Address@sms_tbuf_tx : 0x601b0498
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of consumer buffer.
Transactions addressing between buf2_cons_start.adr and buf2_cons_start.adr
are identified as consumer transactions to buffer number 2.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf2_cons_start_action_cfg
sms_tbuf consumer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b029c
Address@sms_tbuf_tx : 0x601b049c
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf2_state.prod_err
1*: clears buf2_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf2_cons_end
sms_tbuf consumer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b02a0
Address@sms_tbuf_tx : 0x601b04a0
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of consumer buffer.
Transactions addressing between buf2_cons_end.adr and buf2_cons_end.adr
are identified as consumer transactions to buffer number 2.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf2_cons_end_action_cfg
sms_tbuf consumer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02a4
Address@sms_tbuf_tx : 0x601b04a4
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf2_state.prod_err
1*: clears buf2_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf2_prod_offset_0
sms_tbuf producer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02a8
Address@sms_tbuf_tx : 0x601b04a8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 2(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf2_cons_offset_0
sms_tbuf consumer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02ac
Address@sms_tbuf_tx : 0x601b04ac
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 2(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf2_prod_offset_1
sms_tbuf producer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02b0
Address@sms_tbuf_tx : 0x601b04b0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 2(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf2_cons_offset_1
sms_tbuf consumer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02b4
Address@sms_tbuf_tx : 0x601b04b4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 2(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf2_prod_offset_2
sms_tbuf producer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02b8
Address@sms_tbuf_tx : 0x601b04b8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 2(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf2_cons_offset_2
sms_tbuf consumer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02bc
Address@sms_tbuf_tx : 0x601b04bc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 2(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf2_trigger
Trigger register
This register allows the triggering of buffer mechanisms (lock/unlock/commit/fetch). Balance and IRQ state are updated as if the boundary actions would be used.
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02c0
Address@sms_tbuf_tx : 0x601b04c0
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
tgl_cond_en
1: Enables the toggle condition. The operation specified in bits [3:0] in this register during
a write is only executed, when the tgl bitfield changes.
0: Operations are always executed, regardless of the tgl_bit state or the write payload to this trigger register.
16 "0"
tgl
tgl bit for the trigger register. See tgl_cond_en.
15 - 4 0
-
 reserved
3 "0"
unlock_cons
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as consumer
2 "0"
unlock_prod
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as producer
1 "0"
fetch_lock_cons
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Fetch
When in SINGLE_BUFFER_MODE: Lock as consumer
0 "0"
commit_lock_prod
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Commit
When in SINGLE_BUFFER_MODE: Lock as producer


sms_tbuf2_state
sms_tbuf state register (only 32bit write allowed!)
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02c4
Address@sms_tbuf_tx : 0x601b04c4
Bits Reset value Name Description
31 "0"
prod_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
30 "0"
cons_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
29 "0"
prod_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
28 "0"
cons_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
27 "0"
locked_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
26 "0"
bal_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
25 "0"
cons_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
24 "0"
mid_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
23 "0"
prod_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
22 "0"
bal_latched_mask
writable, but can also be changed by hardware
1: fields 'bal_prod' and 'bal_cons' are written
0: write value of fields are ignored
21 - 19 "000"
bal_prod
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last producer action.
18 - 16 "000"
bal_cons
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last consumer action.
15 "0"
prod_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
prod_seq_err is asserted, when a lock operation is performed on a already producer-locked buffer.
14 "0"
cons_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
cons_seq_err is asserted, when a lock operation is performed on a already consumer-locked buffer.
13 - 12 "00"
cons_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to consumer
11 - 10 "00"
mid_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to middle buffer
9 - 8 "00"
prod_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to producer
7 "0"
prod_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: prod_err is asserted when the producer accesses
(read/write to producer address range) a buffer locked by the consumer
Triple buffer mode: prod_err is asserted when the producer accesses
the buffer during the synchronization of the incremental update feature
6 "0"
cons_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: cons_err is asserted when the consumer accesses
(read/write to consumer address range) a buffer locked by the producer
5 - 4 "00"
locked
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
00: buffer not locked
01: buffer is locked by consumer (single buffer mode) or an incremental update is in progress (triple buffer mode)
10: buffer is locked by producer (single buffer mode)
11: reserved
3 - 1 "000"
bal
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
balance counter
<0 : buffer underrun - single buffer: number of locks by consumer since buffer was empty
                       triple buffer: number of fetches since buffer was empty
 0 : buffer empty    - single buffer: buffer unlocked by consumer and has been full or overrun before lock
                       triple buffer: buffer was fetched once since last commit
 1 : buffer full     - single buffer: buffer unlocked by producer and has been empty or underrun before lock
                       triple buffer: buffer was commited once since last fetch
>1 : buffer overrun  - single buffer: number of locks by producer since buffer was full
                       triple buffer: number of commits since buffer was empty
0 0
-
 reserved


sms_tbuf2_cfg
sms_tbuf config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02c8
Address@sms_tbuf_tx : 0x601b04c8
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
cirq_fullover
1: cirq is only asserted when the buffer is full or overrun
Note: all conditions (cirq_fullover/cirq_unlocked) must be met for cirq to be asserted
19 "0"
cirq_unlocked
1: cirq is only asserted when the buffer is unlocked
18 "0"
cirq_en
1: cirq is enabled
17 "0"
ceirq_seq_en
1: ceirq is also asserted when buf2_state.cons_seq_err is high, in addition
to the setting provided by ceirq_en
16 "0"
ceirq_en
1: ceirq is enabled -> IRQ reflects state of buf2_state.cons_err
15 - 13 0
-
 reserved
12 "0"
pirq_emptyunder
1: pirq is only asserted when the buffer is empty or underrun
Note: all conditions (pirq_emptyunder/pirq_unlocked) must be met for pirq to be asserted
11 "0"
pirq_unlocked
1: pirq is only asserted when the buffer is unlocked
10 "0"
pirq_en
1: pirq is enabled
9 "0"
peirq_seq_en
1: peirq is also asserted when buf2_state.prod_seq_err is high, in addition
to the setting provided by peirq_en
8 "0"
peirq_en
1: peirq is enabled -> IRQ reflects state of buf2_state.prod_err
7 - 2 0
-
 reserved
1 - 0 "00"
buffer_mode
00: no hw acceleration / buffer disabled
01: single buffer mode
10: triple buffer mode
11: triple buffer mode with incremental updates


sms_tbuf3_prod_start
sms_tbuf producer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b02cc
Address@sms_tbuf_tx : 0x601b04cc
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of producer buffer.
Transactions addressing between buf3_prod_start.adr and buf3_prod_end.adr
are identified as producer transactions to buffer number 3.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf3_prod_start_action_cfg
sms_tbuf producer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02d0
Address@sms_tbuf_tx : 0x601b04d0
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf3_state.prod_err
1*: clears buf3_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf3_prod_end
sms_tbuf producer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b02d4
Address@sms_tbuf_tx : 0x601b04d4
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of producer buffer.
Transactions addressing between buf3_prod_end.adr and buf3_prod_end.adr
are identified as producer transactions to buffer number 3.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf3_prod_end_action_cfg
sms_tbuf producer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02d8
Address@sms_tbuf_tx : 0x601b04d8
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf3_state.prod_err
1*: clears buf3_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf3_cons_start
sms_tbuf consumer start address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b02dc
Address@sms_tbuf_tx : 0x601b04dc
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading start address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical start address of consumer buffer.
Transactions addressing between buf3_cons_start.adr and buf3_cons_start.adr
are identified as consumer transactions to buffer number 3.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf3_cons_start_action_cfg
sms_tbuf consumer start action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02e0
Address@sms_tbuf_tx : 0x601b04e0
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf3_state.prod_err
1*: clears buf3_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf3_cons_end
sms_tbuf consumer end address register
R/W
0x0003fff8
Address@sms_tbuf_rx : 0x601b02e4
Address@sms_tbuf_tx : 0x601b04e4
Bits Reset value Name Description
31 - 22 0
-
 reserved
21 - 19 "000"
overlay_shift
If a read action is enabled and overlay_en is active:
determines how many bytes the overlay (buffer status) is shifted within the return data.
000: overlay at read_data[7:0]
001: overlay at read_data[15:8]
010: overlay at read_data[23:16]
011: overlay at read_data[31:24]
100: overlay at read_data[39:32]
101: overlay at read_data[47:40]
110: overlay at read_data[55:48]
111: overlay at read_data[63:56]
18 "0"
overlay_en
1: Reading end address returns action cell content
0: Reading returns memory content
17 - 3 0x7fff
adr
Logical end address of consumer buffer.
Transactions addressing between buf3_cons_end.adr and buf3_cons_end.adr
are identified as consumer transactions to buffer number 3.

Must be 64bit aligned.
Bit slice reasoning: 64kB DPM must be addressable with at least 3 mirrors (pass-through, producer, consumer),
increasing the address space by factor 3, adding two bits to [15:0]. 3 LSB can be ignored, as 64 bit memory is used.
2 0
-
 reserved
1 "0"
tgl_mask
writable, but can also be changed by hardware
When '1', the value of the 'tgl' bitfield will be written to the configuration,
else the value of the 'tgl' bitfield in the write access will not be commited.
0 "0"
tgl
writable, but can also be changed by hardware
Set the 'tgl' bit manually, without activating a corresponding tgl_action. # default 0
The 'tgl_mask' bit must be set for this bit to be commited to the configuration register.
During operation, this bit reflects the payload bit[0] of the monitored memory at address 'adr'.


sms_tbuf3_cons_end_action_cfg
sms_tbuf consumer end action config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02e8
Address@sms_tbuf_tx : 0x601b04e8
Bits Reset value Name Description
31 - 20 0
-
 reserved
19 - 18 "00"
read_clears
Reading the boundary buf.adr clears:
00: no clear
*1: clears buf3_state.prod_err
1*: clears buf3_state.cons_err
17 - 16 "00"
write_clears
Writing the boundary buf.adr clears:
see read_clears
15 - 14 "00"
tgl_clears
Toggling bit 0 of the boundary buf.adr clears:
see read_clears
13 - 12 "00"
read_action
Reading triggers:
00: no action
01: Fetch / Lock
10: Commit / Unlock
11: reserved
11 - 10 "00"
write_action
Writing triggers:
see read_action
9 - 8 "00"
tgl_action
Toggling bit 0 of the stored payload triggers:
see read_action
!! If both, write_action and tgl_action are defined for the same operation, tgl_action has precedence.
A write without a toggling tgl bit will NOT trigger a write_action in this case!
7 - 3 0
-
 reserved
2 - 0 "000"
wstrb_sel
Determines which byte within the (64bit-)word at buf.adr must be written
for the 'write_action' to be triggered. E.g. wstrb_sel = 4 requires the bits [39:32] to be written.
The 'read_action' is triggered at every read access.


sms_tbuf3_prod_offset_0
sms_tbuf producer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02ec
Address@sms_tbuf_tx : 0x601b04ec
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 3(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf3_cons_offset_0
sms_tbuf consumer offset 0 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02f0
Address@sms_tbuf_tx : 0x601b04f0
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 3(logical) and physical start of buffer 0.
This address is used when in single buffer mode.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
Bit slice reasoning: The offset is calculated from (physical_address_start - logical_address_start),
the worst cases are: MIN(-logical_address_start) and MAX(physical_address_start).
As this value is a signed representation, it needs an additional bit in comparison to logical_address_start.
2 - 0 0
-
 reserved


sms_tbuf3_prod_offset_1
sms_tbuf producer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02f4
Address@sms_tbuf_tx : 0x601b04f4
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 3(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf3_cons_offset_1
sms_tbuf consumer offset 1 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02f8
Address@sms_tbuf_tx : 0x601b04f8
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 3(logical) and physical start of buffer 1.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf3_prod_offset_2
sms_tbuf producer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b02fc
Address@sms_tbuf_tx : 0x601b04fc
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the producer start address of buffer 3(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf3_cons_offset_2
sms_tbuf consumer offset 2 register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0300
Address@sms_tbuf_tx : 0x601b0500
Bits Reset value Name Description
31 - 19 0
-
 reserved
18 - 3 0x0
adr
Offset between the consumer start address of buffer 3(logical) and physical start of buffer 2.
Must be 64bit aligned. Higher address bits are ignored, if they are out of range of the implemented memory.
2 - 0 0
-
 reserved


sms_tbuf3_trigger
Trigger register
This register allows the triggering of buffer mechanisms (lock/unlock/commit/fetch). Balance and IRQ state are updated as if the boundary actions would be used.
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0304
Address@sms_tbuf_tx : 0x601b0504
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 "0"
tgl_cond_en
1: Enables the toggle condition. The operation specified in bits [3:0] in this register during
a write is only executed, when the tgl bitfield changes.
0: Operations are always executed, regardless of the tgl_bit state or the write payload to this trigger register.
16 "0"
tgl
tgl bit for the trigger register. See tgl_cond_en.
15 - 4 0
-
 reserved
3 "0"
unlock_cons
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as consumer
2 "0"
unlock_prod
the hardware will automatically reset this bit
When in SINGLE_BUFFER_MODE: Unlock as producer
1 "0"
fetch_lock_cons
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Fetch
When in SINGLE_BUFFER_MODE: Lock as consumer
0 "0"
commit_lock_prod
the hardware will automatically reset this bit
When in (TRIPLE_BUFFER_MODE | TRIPLE_BUFFER_MODE_INCUP): Commit
When in SINGLE_BUFFER_MODE: Lock as producer


sms_tbuf3_state
sms_tbuf state register (only 32bit write allowed!)
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b0308
Address@sms_tbuf_tx : 0x601b0508
Bits Reset value Name Description
31 "0"
prod_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
30 "0"
cons_seq_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
29 "0"
prod_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
28 "0"
cons_err_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
27 "0"
locked_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
26 "0"
bal_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
25 "0"
cons_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
24 "0"
mid_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
23 "0"
prod_idx_mask
writable, but can also be changed by hardware
1: field is written
0: write value of field is ignored
22 "0"
bal_latched_mask
writable, but can also be changed by hardware
1: fields 'bal_prod' and 'bal_cons' are written
0: write value of fields are ignored
21 - 19 "000"
bal_prod
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last producer action.
18 - 16 "000"
bal_cons
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Signed balance counter latched at last consumer action.
15 "0"
prod_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
prod_seq_err is asserted, when a lock operation is performed on a already producer-locked buffer.
14 "0"
cons_seq_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
cons_seq_err is asserted, when a lock operation is performed on a already consumer-locked buffer.
13 - 12 "00"
cons_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to consumer
11 - 10 "00"
mid_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to middle buffer
9 - 8 "00"
prod_idx
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Index of physical buffer currently assigned to producer
7 "0"
prod_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: prod_err is asserted when the producer accesses
(read/write to producer address range) a buffer locked by the consumer
Triple buffer mode: prod_err is asserted when the producer accesses
the buffer during the synchronization of the incremental update feature
6 "0"
cons_err
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
Single buffer mode: cons_err is asserted when the consumer accesses
(read/write to consumer address range) a buffer locked by the producer
5 - 4 "00"
locked
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
00: buffer not locked
01: buffer is locked by consumer (single buffer mode) or an incremental update is in progress (triple buffer mode)
10: buffer is locked by producer (single buffer mode)
11: reserved
3 - 1 "000"
bal
writable, but can also be changed by hardware
This bit is only written when the corresponding mask bit is also set.
balance counter
<0 : buffer underrun - single buffer: number of locks by consumer since buffer was empty
                       triple buffer: number of fetches since buffer was empty
 0 : buffer empty    - single buffer: buffer unlocked by consumer and has been full or overrun before lock
                       triple buffer: buffer was fetched once since last commit
 1 : buffer full     - single buffer: buffer unlocked by producer and has been empty or underrun before lock
                       triple buffer: buffer was commited once since last fetch
>1 : buffer overrun  - single buffer: number of locks by producer since buffer was full
                       triple buffer: number of commits since buffer was empty
0 0
-
 reserved


sms_tbuf3_cfg
sms_tbuf config register
R/W
0x00000000
Address@sms_tbuf_rx : 0x601b030c
Address@sms_tbuf_tx : 0x601b050c
Bits Reset value Name Description
31 - 21 0
-
 reserved
20 "0"
cirq_fullover
1: cirq is only asserted when the buffer is full or overrun
Note: all conditions (cirq_fullover/cirq_unlocked) must be met for cirq to be asserted
19 "0"
cirq_unlocked
1: cirq is only asserted when the buffer is unlocked
18 "0"
cirq_en
1: cirq is enabled
17 "0"
ceirq_seq_en
1: ceirq is also asserted when buf3_state.cons_seq_err is high, in addition
to the setting provided by ceirq_en
16 "0"
ceirq_en
1: ceirq is enabled -> IRQ reflects state of buf3_state.cons_err
15 - 13 0
-
 reserved
12 "0"
pirq_emptyunder
1: pirq is only asserted when the buffer is empty or underrun
Note: all conditions (pirq_emptyunder/pirq_unlocked) must be met for pirq to be asserted
11 "0"
pirq_unlocked
1: pirq is only asserted when the buffer is unlocked
10 "0"
pirq_en
1: pirq is enabled
9 "0"
peirq_seq_en
1: peirq is also asserted when buf3_state.prod_seq_err is high, in addition
to the setting provided by peirq_en
8 "0"
peirq_en
1: peirq is enabled -> IRQ reflects state of buf3_state.prod_err
7 - 2 0
-
 reserved
1 - 0 "00"
buffer_mode
00: no hw acceleration / buffer disabled
01: single buffer mode
10: triple buffer mode
11: triple buffer mode with incremental updates


sms_tbuf_all_state_0
sms_tbuf all_state register (read-only) buffer [7 - 0]
R
Address@sms_tbuf_rx : 0x601b0310
Address@sms_tbuf_tx : 0x601b0510
Bits Name Description
31 - 16 -
 reserved
15 - 14 buf3_bal
Balance counter state of logical buffer 3
13 - 12 buf3_locked
Locked state of logical buffer 3
11 - 10 buf2_bal
Balance counter state of logical buffer 2
9 - 8 buf2_locked
Locked state of logical buffer 2
7 - 6 buf1_bal
Balance counter state of logical buffer 1
5 - 4 buf1_locked
Locked state of logical buffer 1
3 - 2 buf0_bal
Balance counter state of logical buffer 0
1 - 0 buf0_locked
Locked state of logical buffer 0


sms_tbuf_all_state_error_0
sms_tbuf all_state_error register (read-only) buffer [7 - 0]
R
Address@sms_tbuf_rx : 0x601b0314
Address@sms_tbuf_tx : 0x601b0514
Bits Name Description
31 - 16 -
 reserved
15 buf3_prod_err
Producer error state of logical buffer 3
14 buf3_cons_err
Consumer error state of logical buffer 3
13 buf3_prod_seq_err
Producer sequence error state of logical buffer 3
12 buf3_cons_seq_err
Consumer sequence error state of logical buffer 3
11 buf2_prod_err
Producer error state of logical buffer 2
10 buf2_cons_err
Consumer error state of logical buffer 2
9 buf2_prod_seq_err
Producer sequence error state of logical buffer 2
8 buf2_cons_seq_err
Consumer sequence error state of logical buffer 2
7 buf1_prod_err
Producer error state of logical buffer 1
6 buf1_cons_err
Consumer error state of logical buffer 1
5 buf1_prod_seq_err
Producer sequence error state of logical buffer 1
4 buf1_cons_seq_err
Consumer sequence error state of logical buffer 1
3 buf0_prod_err
Producer error state of logical buffer 0
2 buf0_cons_err
Consumer error state of logical buffer 0
1 buf0_prod_seq_err
Producer sequence error state of logical buffer 0
0 buf0_cons_seq_err
Consumer sequence error state of logical buffer 0



Base Address Area: sms_device_tba

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_tba_mst_0_status
1 4 -  reserved
2 8 R/W sms_tba_mst_0_action
3 c -  reserved
4 10 R/W sms_tba_mst_0_ctrl
5-3f 14-fc -  reserved

sms_tba_mst_0_status
SMS_TBA_MST_0_STATUS
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the status of
TBA no. 4, calculate: 4*32
R/W
0x00000024
Address : 0x601b0600
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
master_is_consumer
0: master is producer
1: master is consumer
14 - 12 "000"
bal_pre_slave
state of the balance counter immediately before the last slave action
11 - 9 "000"
bal_pre_master
state of the balance counter immediately before the last master action
8 - 6 "000"
bal
signed & saturated balance counter
< 0 : underrun
  0 : empty
  1 : full
> 1 : overrun
5 - 4 "10"
slave_idx
number of the buffer owned by the slave
3 - 2 "01"
mid_idx
number of the free buffer
1 - 0 "00"
master_idx
number of the buffer owned by the master


sms_tba_mst_0_action
SMS_TBA_MST_0_ACTION
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the action register of
TBA no. 4, calculate: 4*32 + 8
R/W
0x00000000
Address : 0x601b0608
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
tgl_slave
Toggling this bit executes the action for the slave
swap TBA_STATUS.slave_idx with TBA_STATUS.mid_idx and
modify the balance counter:
master_is_consumer == 0: fetch (consumer)
master_is_consumer == 1: commit (producer)
0 "0"
tgl_master
Toggling this bit executes the action for the master
swap TBA_STATUS.master_idx with TBA_STATUS.mid_idx and
modify the balance counter:
master_is_consumer == 0: commit (producer)
master_is_consumer == 1: fetch (consumer)


sms_tba_mst_0_ctrl
SMS_TBA_MST_0_CTRL
There are sms_tba.NO of these registers, spaced 32 byte apart. To get the ctrl register of
TBA no. 4, calculate: 4*32 + 16
R/W
0x00000000
Address : 0x601b0610
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
slv_irq_en
Setting this bit enables the slave IRQ
0 "0"
mst_irq_en
Setting this bit enables the master IRQ



Base Address Area: sms_device_cfg_regs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W sms_device_cfg_sync_src_sel
1 4 R/W sms_device_cfg_host_capability
2-3 8-c -  reserved

sms_device_cfg_sync_src_sel
Sync selection MUX for HOST side
R/W
0x00000000
Address : 0x601b0700
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 6 "00"
sel_3
Select host_sync[3] driver:
00: com_sync_timer[3]
01: com_sync_timer_global[3]
10: gxc_trigger_lt_sync1
11: gxc_trigger_lt_global_sync1
5 - 4 "00"
sel_2
Select host_sync[2] driver:
00: com_sync_timer[2]
01: com_sync_timer_global[2]
10: gxc_trigger_lt_sync0
11: gxc_trigger_lt_global_sync0
3 - 2 "00"
sel_1
Select host_sync[1] driver:
00: com_sync_timer[1]
01: com_sync_timer_global[1]
10: gxc_trigger_lt_sync1
11: gxc_trigger_lt_global_sync1
1 - 0 "00"
sel_0
Select host_sync[0] driver:
00: com_sync_timer[0]
01: com_sync_timer_global[0]
10: gxc_trigger_lt_sync0
11: gxc_trigger_lt_global_sync0


sms_device_cfg_host_capability
Host capability configuration register
R/W
0x00000000
Address : 0x601b0704
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
reset_excl_pcie
Setting this bit enables the host to trigger a netX reset without losing the active PCIe link.
0 "0"
reset
Setting this bit enables the host to trigger a netX wide reset.



Base Address Area: dpm_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_0_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_0_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_0_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_0_mbist_power3
4 10 R/W gen_ram_ctrl_netx22xx_0_mbist_power4
5 14 R/W gen_ram_ctrl_netx22xx_0_mbist_power5
6 18 R/W gen_ram_ctrl_netx22xx_0_mbist_power6
7 1c R/W gen_ram_ctrl_netx22xx_0_mbist_power7
8 20 R/W gen_ram_ctrl_netx22xx_0_mbist_power8
9-1ff 24-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_0_ecc0
201 804 R/W gen_ram_ctrl_netx22xx_0_ecc1
202 808 R/W gen_ram_ctrl_netx22xx_0_ecc2
203 80c R/W gen_ram_ctrl_netx22xx_0_ecc3
204 810 R/W gen_ram_ctrl_netx22xx_0_ecc4
205 814 R/W gen_ram_ctrl_netx22xx_0_ecc5
206 818 R/W gen_ram_ctrl_netx22xx_0_ecc6
207 81c R/W gen_ram_ctrl_netx22xx_0_ecc7
208 820 R/W gen_ram_ctrl_netx22xx_0_ecc8
209-27f 824-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_0_ecc_status_corr0
281 a04 R gen_ram_ctrl_netx22xx_0_ecc_status_corr1
282 a08 R gen_ram_ctrl_netx22xx_0_ecc_status_corr2
283 a0c R gen_ram_ctrl_netx22xx_0_ecc_status_corr3
284 a10 R gen_ram_ctrl_netx22xx_0_ecc_status_corr4
285 a14 R gen_ram_ctrl_netx22xx_0_ecc_status_corr5
286 a18 R gen_ram_ctrl_netx22xx_0_ecc_status_corr6
287 a1c R gen_ram_ctrl_netx22xx_0_ecc_status_corr7
288 a20 R gen_ram_ctrl_netx22xx_0_ecc_status_corr8
289-2ff a24-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr3
304 c10 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr4
305 c14 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr5
306 c18 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr6
307 c1c R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr7
308 c20 R gen_ram_ctrl_netx22xx_0_ecc_status_noncorr8
309-37f c24-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_0_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_0_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_0_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_0_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_0_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_0_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.ac_mem_i.gen_ram_hsoc_i (8192x64 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c1000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c100c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power4
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power5
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power6
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power7
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c101c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_mbist_power8
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any BIRA redundancy, BIST type BIST)
R/W
0x000000a0
Address : 0x601c1020
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_0_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.ac_mem_i.gen_ram_hsoc_i (8192x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc1
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc2
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc3
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c180c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc4
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1810
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc5
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1814
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc6
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1818
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc7
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c181c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc8
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x601c1820
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_0_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.ac_mem_i.gen_ram_hsoc_i (8192x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_corr8
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1a20
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.ac_mem_i.gen_ram_hsoc_i (8192x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_rx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_0_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_1_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_2_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_ecc_status_noncorr8
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.sms_i.sms_tbuf_tx.sms_tbuf_ahbl_bus_logic_i.interleaved_ram_3_sms_tbuf_i.gen_ram_hsoc_i (2048x64 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c1c20
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_0_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601c1e00
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_0_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_0_irq_raw_reg0).
R/W
0x00000000
Address : 0x601c1e40
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_0_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_0_irq_raw_reg0
R/W
0x00000000
Address : 0x601c1e80
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_0_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 27 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_4_err_ecc_non_correctable
  5  : irq_reg0-mem_5_err_ecc_non_correctable
  6  : irq_reg0-mem_6_err_ecc_non_correctable
  7  : irq_reg0-mem_7_err_ecc_non_correctable
  8  : irq_reg0-mem_8_err_ecc_non_correctable
  9  : irq_reg0-mem_0_err_ecc_correctable
  10 : irq_reg0-mem_1_err_ecc_correctable
  11 : irq_reg0-mem_2_err_ecc_correctable
  12 : irq_reg0-mem_3_err_ecc_correctable
  13 : irq_reg0-mem_4_err_ecc_correctable
  14 : irq_reg0-mem_5_err_ecc_correctable
  15 : irq_reg0-mem_6_err_ecc_correctable
  16 : irq_reg0-mem_7_err_ecc_correctable
  17 : irq_reg0-mem_8_err_ecc_correctable
  18 : irq_reg0-mem_0_mbist_or_init_finished
  19 : irq_reg0-mem_1_mbist_or_init_finished
  20 : irq_reg0-mem_2_mbist_or_init_finished
  21 : irq_reg0-mem_3_mbist_or_init_finished
  22 : irq_reg0-mem_4_mbist_or_init_finished
  23 : irq_reg0-mem_5_mbist_or_init_finished
  24 : irq_reg0-mem_6_mbist_or_init_finished
  25 : irq_reg0-mem_7_mbist_or_init_finished
  26 : irq_reg0-mem_8_mbist_or_init_finished
  27 : no active IRQ
R/W
0x00000000
Address : 0x601c1ec0
Bits Reset value Name Description
31 - 27 0
-
 reserved
26 "0"
mem_8_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
25 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
24 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
23 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_8_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
16 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
15 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_8_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_0_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x601c1efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: intram0_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_1_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_1_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_1_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_1_mbist_power3
4 10 R/W gen_ram_ctrl_netx22xx_1_mbist_power4
5 14 R/W gen_ram_ctrl_netx22xx_1_mbist_power5
6 18 R/W gen_ram_ctrl_netx22xx_1_mbist_power6
7 1c R/W gen_ram_ctrl_netx22xx_1_mbist_power7
8-1ff 20-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_1_ecc0
201 804 R/W gen_ram_ctrl_netx22xx_1_ecc1
202 808 R/W gen_ram_ctrl_netx22xx_1_ecc2
203 80c R/W gen_ram_ctrl_netx22xx_1_ecc3
204 810 R/W gen_ram_ctrl_netx22xx_1_ecc4
205 814 R/W gen_ram_ctrl_netx22xx_1_ecc5
206 818 R/W gen_ram_ctrl_netx22xx_1_ecc6
207 81c R/W gen_ram_ctrl_netx22xx_1_ecc7
208-27f 820-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_1_ecc_status_corr0
281 a04 R gen_ram_ctrl_netx22xx_1_ecc_status_corr1
282 a08 R gen_ram_ctrl_netx22xx_1_ecc_status_corr2
283 a0c R gen_ram_ctrl_netx22xx_1_ecc_status_corr3
284 a10 R gen_ram_ctrl_netx22xx_1_ecc_status_corr4
285 a14 R gen_ram_ctrl_netx22xx_1_ecc_status_corr5
286 a18 R gen_ram_ctrl_netx22xx_1_ecc_status_corr6
287 a1c R gen_ram_ctrl_netx22xx_1_ecc_status_corr7
288-2ff a20-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr3
304 c10 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr4
305 c14 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr5
306 c18 R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr6
307 c1c R gen_ram_ctrl_netx22xx_1_ecc_status_noncorr7
308-37f c20-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_1_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_1_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_1_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_1_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_1_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_1_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c200c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power4
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power5
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power6
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c2018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_mbist_power7
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c201c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_1_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc1
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc2
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc3
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c280c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc4
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2810
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc5
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2814
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc6
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c2818
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc7
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
R/W
0x00000000
Address : 0x601c281c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_1_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_corr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2a1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_ecc_status_noncorr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i0.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 64 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c2c1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_1_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601c2e00
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_1_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_1_irq_raw_reg0).
R/W
0x00000000
Address : 0x601c2e40
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_1_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_1_irq_raw_reg0
R/W
0x00000000
Address : 0x601c2e80
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_1_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 24 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_4_err_ecc_non_correctable
  5  : irq_reg0-mem_5_err_ecc_non_correctable
  6  : irq_reg0-mem_6_err_ecc_non_correctable
  7  : irq_reg0-mem_7_err_ecc_non_correctable
  8  : irq_reg0-mem_0_err_ecc_correctable
  9  : irq_reg0-mem_1_err_ecc_correctable
  10 : irq_reg0-mem_2_err_ecc_correctable
  11 : irq_reg0-mem_3_err_ecc_correctable
  12 : irq_reg0-mem_4_err_ecc_correctable
  13 : irq_reg0-mem_5_err_ecc_correctable
  14 : irq_reg0-mem_6_err_ecc_correctable
  15 : irq_reg0-mem_7_err_ecc_correctable
  16 : irq_reg0-mem_0_mbist_or_init_finished
  17 : irq_reg0-mem_1_mbist_or_init_finished
  18 : irq_reg0-mem_2_mbist_or_init_finished
  19 : irq_reg0-mem_3_mbist_or_init_finished
  20 : irq_reg0-mem_4_mbist_or_init_finished
  21 : irq_reg0-mem_5_mbist_or_init_finished
  22 : irq_reg0-mem_6_mbist_or_init_finished
  23 : irq_reg0-mem_7_mbist_or_init_finished
  24 : no active IRQ
R/W
0x00000000
Address : 0x601c2ec0
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_1_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x601c2efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: intram1_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_2_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_2_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_2_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_2_mbist_power3
4 10 R/W gen_ram_ctrl_netx22xx_2_mbist_power4
5 14 R/W gen_ram_ctrl_netx22xx_2_mbist_power5
6 18 R/W gen_ram_ctrl_netx22xx_2_mbist_power6
7 1c R/W gen_ram_ctrl_netx22xx_2_mbist_power7
8-1ff 20-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_2_ecc0
201 804 R/W gen_ram_ctrl_netx22xx_2_ecc1
202 808 R/W gen_ram_ctrl_netx22xx_2_ecc2
203 80c R/W gen_ram_ctrl_netx22xx_2_ecc3
204 810 R/W gen_ram_ctrl_netx22xx_2_ecc4
205 814 R/W gen_ram_ctrl_netx22xx_2_ecc5
206 818 R/W gen_ram_ctrl_netx22xx_2_ecc6
207 81c R/W gen_ram_ctrl_netx22xx_2_ecc7
208-27f 820-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_2_ecc_status_corr0
281 a04 R gen_ram_ctrl_netx22xx_2_ecc_status_corr1
282 a08 R gen_ram_ctrl_netx22xx_2_ecc_status_corr2
283 a0c R gen_ram_ctrl_netx22xx_2_ecc_status_corr3
284 a10 R gen_ram_ctrl_netx22xx_2_ecc_status_corr4
285 a14 R gen_ram_ctrl_netx22xx_2_ecc_status_corr5
286 a18 R gen_ram_ctrl_netx22xx_2_ecc_status_corr6
287 a1c R gen_ram_ctrl_netx22xx_2_ecc_status_corr7
288-2ff a20-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr3
304 c10 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr4
305 c14 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr5
306 c18 R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr6
307 c1c R gen_ram_ctrl_netx22xx_2_ecc_status_noncorr7
308-37f c20-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_2_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_2_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_2_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_2_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_2_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_2_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c300c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power4
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power5
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power6
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c3018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_mbist_power7
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c301c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_2_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc1
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc2
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc3
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c380c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc4
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3810
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc5
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3814
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc6
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c3818
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc7
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c381c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_2_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_corr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3a1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_ecc_status_noncorr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i1.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c3c1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_2_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601c3e00
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_2_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_2_irq_raw_reg0).
R/W
0x00000000
Address : 0x601c3e40
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_2_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_2_irq_raw_reg0
R/W
0x00000000
Address : 0x601c3e80
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_2_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 24 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_4_err_ecc_non_correctable
  5  : irq_reg0-mem_5_err_ecc_non_correctable
  6  : irq_reg0-mem_6_err_ecc_non_correctable
  7  : irq_reg0-mem_7_err_ecc_non_correctable
  8  : irq_reg0-mem_0_err_ecc_correctable
  9  : irq_reg0-mem_1_err_ecc_correctable
  10 : irq_reg0-mem_2_err_ecc_correctable
  11 : irq_reg0-mem_3_err_ecc_correctable
  12 : irq_reg0-mem_4_err_ecc_correctable
  13 : irq_reg0-mem_5_err_ecc_correctable
  14 : irq_reg0-mem_6_err_ecc_correctable
  15 : irq_reg0-mem_7_err_ecc_correctable
  16 : irq_reg0-mem_0_mbist_or_init_finished
  17 : irq_reg0-mem_1_mbist_or_init_finished
  18 : irq_reg0-mem_2_mbist_or_init_finished
  19 : irq_reg0-mem_3_mbist_or_init_finished
  20 : irq_reg0-mem_4_mbist_or_init_finished
  21 : irq_reg0-mem_5_mbist_or_init_finished
  22 : irq_reg0-mem_6_mbist_or_init_finished
  23 : irq_reg0-mem_7_mbist_or_init_finished
  24 : no active IRQ
R/W
0x00000000
Address : 0x601c3ec0
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_2_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x601c3efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: intram2_ram_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_netx22xx_3_mbist_power0
1 4 R/W gen_ram_ctrl_netx22xx_3_mbist_power1
2 8 R/W gen_ram_ctrl_netx22xx_3_mbist_power2
3 c R/W gen_ram_ctrl_netx22xx_3_mbist_power3
4 10 R/W gen_ram_ctrl_netx22xx_3_mbist_power4
5 14 R/W gen_ram_ctrl_netx22xx_3_mbist_power5
6 18 R/W gen_ram_ctrl_netx22xx_3_mbist_power6
7 1c R/W gen_ram_ctrl_netx22xx_3_mbist_power7
8-1ff 20-7fc -  reserved
200 800 R/W gen_ram_ctrl_netx22xx_3_ecc0
201 804 R/W gen_ram_ctrl_netx22xx_3_ecc1
202 808 R/W gen_ram_ctrl_netx22xx_3_ecc2
203 80c R/W gen_ram_ctrl_netx22xx_3_ecc3
204 810 R/W gen_ram_ctrl_netx22xx_3_ecc4
205 814 R/W gen_ram_ctrl_netx22xx_3_ecc5
206 818 R/W gen_ram_ctrl_netx22xx_3_ecc6
207 81c R/W gen_ram_ctrl_netx22xx_3_ecc7
208-27f 820-9fc -  reserved
280 a00 R gen_ram_ctrl_netx22xx_3_ecc_status_corr0
281 a04 R gen_ram_ctrl_netx22xx_3_ecc_status_corr1
282 a08 R gen_ram_ctrl_netx22xx_3_ecc_status_corr2
283 a0c R gen_ram_ctrl_netx22xx_3_ecc_status_corr3
284 a10 R gen_ram_ctrl_netx22xx_3_ecc_status_corr4
285 a14 R gen_ram_ctrl_netx22xx_3_ecc_status_corr5
286 a18 R gen_ram_ctrl_netx22xx_3_ecc_status_corr6
287 a1c R gen_ram_ctrl_netx22xx_3_ecc_status_corr7
288-2ff a20-bfc -  reserved
300 c00 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr0
301 c04 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr1
302 c08 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr2
303 c0c R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr3
304 c10 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr4
305 c14 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr5
306 c18 R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr6
307 c1c R gen_ram_ctrl_netx22xx_3_ecc_status_noncorr7
308-37f c20-dfc -  reserved
380 e00 R/W gen_ram_ctrl_netx22xx_3_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_netx22xx_3_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_netx22xx_3_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_netx22xx_3_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_netx22xx_3_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_netx22xx_3_mbist_power0
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power1
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4004
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power2
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power3
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c400c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power4
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4010
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power5
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4014
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power6
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c4018
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_mbist_power7
MBIST/power control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any BIRA redundancy, BIST type BIRA)
R/W
0x000000a0
Address : 0x601c401c
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
If 1, the memory is set to shutdown mode, saving more power, but destroying its memory contents, and not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
6 "0"
sleep
Sleep mode register
If 1, the memory is set to sleep mode, saving power, maintaining its memory contents, but not allowing access.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_netx22xx_3_ecc0
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc1
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4804
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc2
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4808
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc3
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c480c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc4
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4810
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc5
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4814
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc6
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c4818
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc7
ECC control and status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
R/W
0x00000000
Address : 0x601c481c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_netx22xx_3_ecc_status_corr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_corr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4a1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr0
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[0].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr1
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[1].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c04
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr2
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[2].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c08
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr3
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[3].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c0c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr4
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[4].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c10
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr5
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[5].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c14
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr6
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[6].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c18
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_ecc_status_noncorr7
ECC status register
For memory netx22xx_mux_i.netx22xx_core_i.com_i.com_intram_wrapper_i2.fragmented_ram_i.ram_fragment[7].ram_present.ram_inst (8192x128 bits excluding any parity bits)
The memory includes ECC/parity per 32 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x601c4c1c
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_netx22xx_3_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x601c4e00
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_3_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_netx22xx_3_irq_raw_reg0).
R/W
0x00000000
Address : 0x601c4e40
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_3_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_netx22xx_3_irq_raw_reg0
R/W
0x00000000
Address : 0x601c4e80
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_3_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 24 when no IRQ is set:
  0  : irq_reg0-mem_0_err_ecc_non_correctable
  1  : irq_reg0-mem_1_err_ecc_non_correctable
  2  : irq_reg0-mem_2_err_ecc_non_correctable
  3  : irq_reg0-mem_3_err_ecc_non_correctable
  4  : irq_reg0-mem_4_err_ecc_non_correctable
  5  : irq_reg0-mem_5_err_ecc_non_correctable
  6  : irq_reg0-mem_6_err_ecc_non_correctable
  7  : irq_reg0-mem_7_err_ecc_non_correctable
  8  : irq_reg0-mem_0_err_ecc_correctable
  9  : irq_reg0-mem_1_err_ecc_correctable
  10 : irq_reg0-mem_2_err_ecc_correctable
  11 : irq_reg0-mem_3_err_ecc_correctable
  12 : irq_reg0-mem_4_err_ecc_correctable
  13 : irq_reg0-mem_5_err_ecc_correctable
  14 : irq_reg0-mem_6_err_ecc_correctable
  15 : irq_reg0-mem_7_err_ecc_correctable
  16 : irq_reg0-mem_0_mbist_or_init_finished
  17 : irq_reg0-mem_1_mbist_or_init_finished
  18 : irq_reg0-mem_2_mbist_or_init_finished
  19 : irq_reg0-mem_3_mbist_or_init_finished
  20 : irq_reg0-mem_4_mbist_or_init_finished
  21 : irq_reg0-mem_5_mbist_or_init_finished
  22 : irq_reg0-mem_6_mbist_or_init_finished
  23 : irq_reg0-mem_7_mbist_or_init_finished
  24 : no active IRQ
R/W
0x00000000
Address : 0x601c4ec0
Bits Reset value Name Description
31 - 24 0
-
 reserved
23 "0"
mem_7_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
22 "0"
mem_6_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
21 "0"
mem_5_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
20 "0"
mem_4_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
19 "0"
mem_3_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
18 "0"
mem_2_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
17 "0"
mem_1_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
16 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
15 "0"
mem_7_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
14 "0"
mem_6_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
13 "0"
mem_5_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
12 "0"
mem_4_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
11 "0"
mem_3_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
10 "0"
mem_2_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
9 "0"
mem_1_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
8 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
7 "0"
mem_7_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
6 "0"
mem_6_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
5 "0"
mem_5_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
4 "0"
mem_4_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
3 "0"
mem_3_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
2 "0"
mem_2_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
1 "0"
mem_1_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_netx22xx_3_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x601c4efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories



Base Address Area: msi2irq_0, msi2irq_1, msi2irq_2, msi2irq_3

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_msi2irq_msg
1-3 4-c -  reserved

pcie_msi2irq_msg
MSI access register
R/W
0x00000000
Address@msi2irq_0 : 0x68000000
Address@msi2irq_1 : 0x68000010
Address@msi2irq_2 : 0x68000020
Address@msi2irq_3 : 0x68000030
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
msg
MSI access register
Write to this register to trigger an MSI interrupt.
You need to write the payload configured in the msi2irq_cfg.data_mask.data bitfield.
If configured correctly, you may target different IRQ vectors by writing the IRQ index into the LSBs.
Reads return the last VALID msi message.



Base Address Area: pcie_sys_ctrl

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_link0_sw_reset
1 4 R pcie_link0_credit_availability_status
2 8 R/W pcie_link0_config
3 c R/W pcie_link0_ctrl
4 10 R pcie_link0_config_info
5 14 R/W pcie_link0_vendor_specific_capability
6 18 R pcie_link0_vendor_specific_capability_info
7 1c R pcie_link0_debug
8 20 R pcie_link0_debug_1
9 24 R pcie_link0_irq_state
a 28 W pcie_link0_irq_clear
b 2c W pcie_link0_irq_set
c 30 R/W pcie_link0_irq_mask
d 34 W pcie_link0_issue_error
e 38 R/W pcie_link0_legacy_irq_mask
f 3c R/W pcie_link0_msg_config
10 40 R pcie_link0_msg_status
11 44 R pcie_link0_msg_fifo
12 48 R pcie_link0_msg_sideband
13 4c R/W pcie_pipe_pma0
14 50 R pcie_pipe_pma0_info
15 54 R/W pcie_link0_hot_reset
16 58 R/W pcie_link0_perf_mask_0
17 5c R/W pcie_link0_perf_mask_1
18 60 R/W pcie_link0_perf_mask_2
19 64 R/W pcie_link0_perf_mask_3
1a 68 W pcie_link0_perf_strobe
1b 6c R pcie_link_perf_cnt_0
1c 70 R pcie_link_perf_cnt_1
1d 74 R pcie_link_perf_cnt_2
1e 78 R pcie_link_perf_cnt_3
1f-3f 7c-fc -  reserved
40 100 R/W pcie_ram_sleep_ctrl
41 104 R/W pcie_ram_shutdown_ctrl
42 108 R/W pcie_ram_disable_ctrl
43 10c R/W pcie_ram_autosleep_ctrl_mask
44 110 R/W pcie_ram_autosleep_ctrl
45 114 R/W pcie_ram_ctrl_shutdown_timing
46-3fff 118-fffc -  reserved

pcie_link0_sw_reset
Software reset register
R/W
0x00000000
Address : 0x68020000
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
link0_pm_sw_reset_n
Software reset for PCIe Link 0 power management Registers
7 "0"
link0_mgmt_sw_reset_n
Software reset for PCIe Link 0 controller MGMT Registers (without sticky registers)
6 "0"
link0_mgmt_sticky_sw_reset_n
Software reset for PCIe Link 0 controller sticky MGMT registers
5 "0"
link0_axi_sw_reset_n
Software reset for PCIe Link 0 controller core AXI port
4 "0"
link0_sw_reset_n
Software reset for PCIe Link 0 controller core (with exception of config registers)
3 "0"
link0_pipe_sw_reset_n
Software reset for PCIe Link 0 controller PIPE interface
2 "0"
phy_pipe_sw_reset_n
Software reset for PCIe PHY pipe reset
1 "0"
phy_apb_sw_reset_n
Software reset for PCIe PHY APB port
0 "0"
link0_apb_sw_reset_n
Software reset for PCIe Link 0 controller core APB port


pcie_link0_credit_availability_status
Credit availability status register
R
Address : 0x68020004
Bits Name Description
31 link0_npd_credit_avail7
Non-posted Payload credit availability signal.
30 link0_nph_credit_avail7
Non-posted header credit availability signal.
29 link0_pd_credit_avail7
Posted Payload credit availability signal.
28 link0_ph_credit_avail7
Posted header credit availability signal.
27 link0_npd_credit_avail6
Non-posted Payload credit availability signal.
26 link0_nph_credit_avail6
Non-posted header credit availability signal.
25 link0_pd_credit_avail6
Posted Payload credit availability signal.
24 link0_ph_credit_avail6
Posted header credit availability signal.
23 link0_npd_credit_avail5
Non-posted Payload credit availability signal.
22 link0_nph_credit_avail5
Non-posted header credit availability signal.
21 link0_pd_credit_avail5
Posted Payload credit availability signal.
20 link0_ph_credit_avail5
Posted header credit availability signal.
19 link0_npd_credit_avail4
Non-posted Payload credit availability signal.
18 link0_nph_credit_avail4
Non-posted header credit availability signal.
17 link0_pd_credit_avail4
Posted Payload credit availability signal.
16 link0_ph_credit_avail4
Posted header credit availability signal.
15 link0_npd_credit_avail3
Non-posted Payload credit availability signal.
14 link0_nph_credit_avail3
Non-posted header credit availability signal.
13 link0_pd_credit_avail3
Posted Payload credit availability signal.
12 link0_ph_credit_avail3
Posted header credit availability signal.
11 link0_npd_credit_avail2
Non-posted Payload credit availability signal.
10 link0_nph_credit_avail2
Non-posted header credit availability signal.
9 link0_pd_credit_avail2
Posted Payload credit availability signal.
8 link0_ph_credit_avail2
Posted header credit availability signal.
7 link0_npd_credit_avail1
Non-posted Payload credit availability signal.
6 link0_nph_credit_avail1
Non-posted header credit availability signal.
5 link0_pd_credit_avail1
Posted Payload credit availability signal.
4 link0_ph_credit_avail1
Posted header credit availability signal.
3 link0_npd_credit_avail0
Non-posted Payload credit availability signal.
2 link0_nph_credit_avail0
Non-posted header credit availability signal.
1 link0_pd_credit_avail0
Posted Payload credit availability signal.
0 link0_ph_credit_avail0
Posted header credit availability signal.


pcie_link0_config
PCIe Link0 Config Register
R/W
0x00000000
Address : 0x68020008
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 "0"
force_power_state_change_ack
Force 'power_state_change_ack' to '1', always
acknowledging incoming power state change requests.
Overwrites setting of power_state_change_ack in
'Link0 IRQ clear' register.
11 - 9 "000"
vc_count
Number of VCs configured.
8 "0"
core_clk_shutoff_detect_en
Enables the APB Bridge to not hang on APB accesses
when core_clk is shutoff.
7 - 3 "00000"
apb_core_clk_ratio
User driven to the ratio of apb_clk to core_clk.
2 "0"
sris_enable
Should be set as per the System Reference Clocking Implementation.
Note that the common Refclk architecture utilizes the same Refclk
for Tx and Rx and so does not introduce any difference between the Tx and Rx Refclk rates.
SRIS_ENABLE input should be tied to 0 in this case also.
0: Separate Tx and Rx Reference Clocks with No Spread Spectum Clocking - SRNS Mode
1: Separate Tx and Rx Reference Clocks with Spread Spectum Clocking - SRIS Mode
1 "0"
mode_select
This strap input determines PCIe mode configuration
0: for Endpoint operation
1: for Root Port operation
Note: This strap input is used internally to initialize the PCIe Capabilities Linked List Pointers. Hence must be stable prior to deasserting the mgmt_reset_n.
0 "0"
pcie_generation_sel
This strap input selects the generation of the
PCI Express protocol supported by the Controller. Valid settings are:
0: Gen1 mode. The Controller advertises only Gen1 capability in this mode and will always operate at Gen1 speed.
1: Gen2 mode. The Controller advertises Gen1 and Gen2 capabilities in this mode, but not Gen3.
Note: This strap input is used internally to initialize the PCIe Capabilities Linked List Pointers. Hence must be stable prior to deasserting the mgmt_reset_n.


pcie_link0_ctrl
PCIe Link0 Control Register
R/W
0x00000000
Address : 0x6802000c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 "0"
clear_link_down_bit
This bit will be set when link down reset comes.
Client should clear this bit before issueing new traffic to the core
6 "0"
client_req_exit_l1_substate
Assertion requests L1 substate -> L0 transition
Can be enhanced with dedicated logic
5 "0"
pcie_target_non_posted_rej
This is a single bit input signal which can be
asserted by client logic when it cannot service a
non-posted request. The core will not present any
non-posted requests that it receives from the PCIe
Link. It will hold them in the PNP FIFO RAM till
the signal is de-asserted. If a non-posted TLP has
already been queued from the PNP FIFO and this
signal is asserted, the core will place it on the AXI
bridge. The client logic must accept the non-posted
TLP. The in-flight non-posted TLPs in the core from
the PNP FIFO cannot be stopped. However, non-
posted TLPs that are in the PNP FIFO RAM when
this signal is asserted or come in after the signal is
asserted will not be forwarded to the AXI interface.
The client must assert this signal when it still can
process two or three non-posted TLPs. This will
allow posted TLPs to go past non-posted TLPs at
the AXI master write interface due to client not
being able to service non-posted TLPs.
4 "0"
client_req_exit_l1
Client logic can trigger an explicit L1 exit by asserting
this signal. This signal triggers an exit to L0 from L1
or from L1-substates. This signal can also be used to
block L1 entry in End point controllers.
3 "0"
req_pm_transition_l23_ready
When the Controller is configured as EndPoint, the
client may assert this input to transition the power
management state of the Controller to L23_READY
Asserting this input causes the link to
transition to the L2 state, and requires a power-on
reset to resume operation. This input can be hardwired
to 0 if the link is not required to transition to L2.
This input is not used in the Root Port mode.
2 "0"
link_training_enable
This input must be set to 1 to enable the LTSSM to
bring up the link. Setting it to 0 forces the LTSSM to
stay in the Detect.Quiet state.
1 "0"
client_req_exit_l2
This input can be asserted by the client only in the
short interval of time after the link enters L2 and
before the system is powered OFF. While the power
and clocks are still ON, the client can assert this input
to initiate an exit from L2_IDLE->DETECT.
0 "0"
config_enable
 When this input is set to 0 in the EP mode,
the Controller will generate a CRS Completion in response to Configuration Requests. # default 0
 When this input is set to 1 in the EP mode, the Controller will generate SC/UR Completion in response to Configuration Requests
 based on the target function. In systems where the Controller configuration registers are loaded from RAM on power-up,
 this prevents the Controller from responding to Configuration Requests before all the registers are loaded.
 This input can be strapped high when the power-on default values of the Configuration Registers do not need to be modified before
 Configuration Space enumeration. This input is unused in RP Mode and can be set to 0 when in RP mode.


pcie_link0_config_info
PCIe Link0 Config Info
R
Address : 0x68020010
Bits Name Description
31 - 30 -
 reserved
29 link0_ltr_mechanism_enable
Reflects setting of LTR Mechanism Enable Bit in
Device Control 2 Register of PF0.
In EP mode: Client logic uses this output to
enable the generation of LTR messages.
In RC mode: Not used.
28 - 26 link0_tph_st_mode
Bits [2:0] of this output reflect the setting of the
ST Mode Select bits in the TPH Requester Control
Register of Physical Function 0.
These bits are active only in the EndPoint mode. They
indicate the allowed modes for generation of TPH
Hints by the corresponding Physical Function.
25 link0_tph_requester_enable
Bit 0 of this output drives the TPH Requester Enable
bit [8] of the TPH Requester Control Register in the
TPH Requester Capability Structure of the Physical
Function 0.
These bits are active only in the EndPoint mode.
They indicate whether the software has enabled the
device to generate requests with TPH Hints from the
associated Physical Function.
24 - 23 link0_obff_enable
This output reflects the setting of the OBFF Enable
field in the Device Control 2 Register:
00 = OBFF disabled
01 = OBFF enabled using message signaling, Variation A
10 = OBFF enabled using message signaling, Variation B
11 = OBFF enabled using WAKE# signaling
22 link0_rcb_status
Provides the setting of the Read Completion
Boundary (RCB) bit in the Link Control Register of
each Physical Function. In the EndPoint mode, bit 1
indicates the RCB for PF 1 and so on. In the RP mode,
bit 1 indicates the RCB setting of the Link Control
Register of the RP 1.
For each bit, a value of 0 indicates an RCB of 64 bytes
and 1 indicates 128 bytes.
21 - 19 link0_max_payload_size
The maximum payload size field programmed in
the PCI Express Device Control Register. In multi-
Function cores, this output provides the minimum
of the max-payload-size field in the Device Control
Registers of all the enabled Physical Functions.
The client logic must limit the size of Outgoing
Completion payloads to this value. The 3-bit codes
are the same as those defined in PCIe Specifications:
000 = 128 bytes
001 = 256 bytes
010 = 512 bytes
011 = 1024 bytes
100 = 2048 bytes
101 = 4096 bytes
18 - 16 link0_max_read_req_size
The maximum request size field programmed in
the PCI Express Device Control Register. In multi-
Function cores, this output provides the minimum
of the max-read-request field in the Device Control
Registers of all the Physical Functions. The client
logic must limit the size of outgoing read requests
to this value. The 3-bit codes are the same as those
defined in PCIe Specifications:
000 = 128 bytes
001 = 256 bytes
010 = 512 bytes
011 = 1024 bytes
100 = 2048 bytes
101 = 4096 bytes
15 - 13 -
 reserved
12 - 10 link0_function_power_state
These outputs provide the current power state of the
Physical Functions. Bits [2:0] capture the power state
of Function 0 The possible power states are:
000: D0_uninitialized
001: D0_active
010: D1
100: D3_hot
9 - 6 link0_function_status
These outputs indicate the states of the Command
Register bits in the PCI configuration space of each
Function. These outputs are used to enable requests
and completions from the host logic. The assignment
of bits is as follows:
Bit 0: Function 0 IO Space Enable
Bit 1: Function 0 Memory Space Enable
Bit 2: Function 0 Bus Master Enable
Bit 3: Function 0 INTx Disable
and so on depending on the number of functions.
5 link0_negotiated_speed
Current operating speed of the link is as follows:
0: 2.5GT/s
1: 5GT/s
4 -
 reserved
3 - 2 link0_link_status
Status of the PCI Express link.
00 = No receivers detected.
01 = Link training in progress.
10 = Link up, DL initialization in progress.
11 = Link up, DL initialization completed.
1 link0_core_clk_shutoff
Level signal indicating that core_clk is shutoff.
0 -
 reserved


pcie_link0_vendor_specific_capability
PCIe Link0 Vendor Specific Capability
R/W
0x00000000
Address : 0x68020014
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
link0_set_f0_vsec_control
The state of these inputs can be read from bits [7:0]
of the Vendor-Specific Control Register in the
Vendor-Specific Capability Structure of PF0. The
setting of these inputs does not affect the operation
of the core in any other way.


pcie_link0_vendor_specific_capability_info
PCIe Link0 Vendor-Specific Capability Info
R
Address : 0x68020018
Bits Name Description
31 - 23 -
 reserved
22 - 0 link0_get_f0_vsec_control
This output is driven by Bit{31:9} of the Vendor-
Specific Control Register in the Vendor-Specific
Capability Structure of PF0. It can be used by the
host to signal vendor specific control data to the
application logic outside the core.


pcie_link0_debug
PCIe Link0 Debug
R
Address : 0x6802001c
Bits Name Description
31 - 9 -
 reserved
8 - 6 link0_l1_pm_substate_out
This output provides the current state of the L1
PM substates state machine. This output is in the
PM_CLK clock domain. Its encodings are:
000: L1-substate machine not active
001: L1.0 substate, register shows L1.0 after
the delay programmed in L1 substate entry delay in
reg:low_power_debug_control()
010: L1.1 substate
011: reserved
100: L1.2.Entry substate
101: L1.2.Idle substate
110: L1.2.Exit substate
111: reserved
5 - 0 link0_ltssm_state
Current state of the Link0 Training and Status State
Machine within the core.


pcie_link0_debug_1
PCIe Link0 Debug Register 2
R
Address : 0x68020020
Bits Name Description
31 - 0 link0_ltssm_transition_cause_data
Provides debug information about the most recent
LTSSM transition.
31-22: reserved
21-14: ltssm state transition cause, 8 bit encoded value
 13-7: current ltssm state
  6-0: previous ltssm state


pcie_link0_irq_state
PCIe Link0 IRQ state
R
Address : 0x68020024
Bits Name Description
31 - 10 -
 reserved
9 link0_msg_sb_fifo_overflow
State of interrupt indicating link0 message fifo overflow
8 link0_msg_sb_fifo_not_empty
State of interrupt indicating link0 message fifo is not empty
7 link0_reg_access_clk_shutoff
State of interrupt indicating an APB access when the core_clk
was shutoff.
6 link0_power_state_change
State of interrupt indicating link0_power_state_change
5 link0_correctable_error
State of interrupt indicating link0_correctable_error
4 link0_non_fatal_error
State of interrupt indicating link0_non_fatal_error
3 link0_fatal_error
State of interrupt indicating link0_fatal_error
2 link0_link_down_reset
State of interrupt indicating link0_link_down_reset
1 link0_hot_reset
State of interrupt indicating link0_hot_reset
0 link0_msi_enabled
State of interrupt indicating msi has been enabled


pcie_link0_irq_clear
PCIe Link0 IRQ clear
W
0x00000000
Address : 0x68020028
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
link0_msg_sb_fifo_overflow_ack
Clears interrupt indicating link0_msg_sb_fifo_overflow
the hardware will automatically reset this bit
8 0
-
 reserved
7 "0"
link0_reg_access_clk_shutoff_ack
Clears interrupt indicating link0_reg_access_clk_shutoff
the hardware will automatically reset this bit
6 "0"
link0_power_state_change_ack
Clears interrupt indicating link0_power_state_change
the hardware will automatically reset this bit
5 "0"
link0_correctable_error_ack
Clears interrupt indicating link0_correctable_error
the hardware will automatically reset this bit
4 "0"
link0_non_fatal_error_ack
Clears interrupt indicating link0_non_fatal_error
the hardware will automatically reset this bit
3 "0"
link0_fatal_error_ack
Clears interrupt indicating link0_fatal_error
the hardware will automatically reset this bit
2 "0"
link0_link_down_reset_ack
Clears interrupt indicating link0_link_down_reset
the hardware will automatically reset this bit
1 "0"
link0_hot_reset_ack
Clears interrupt indicating link0_hot_reset
the hardware will automatically reset this bit
0 "0"
link0_msi_enabled_ack
Clears interrupt indicating link0_msi_enabled
the hardware will automatically reset this bit


pcie_link0_irq_set
PCIe Link0 IRQ set
W
0x00000000
Address : 0x6802002c
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
link0_msg_sb_fifo_overflow_set
Sets interrupt indicating link0_msg_sb_fifo_overflow
the hardware will automatically reset this bit
8 0
-
 reserved
7 "0"
link0_reg_access_clk_shutoff_set
Sets interrupt indicating link0_reg_access_clk_shutoff
the hardware will automatically reset this bit
6 0
-
 reserved
5 "0"
link0_correctable_error_set
Sets interrupt indicating link0_correctable_error
the hardware will automatically reset this bit
4 "0"
link0_non_fatal_error_set
Sets interrupt indicating link0_non_fatal_error
the hardware will automatically reset this bit
3 "0"
link0_fatal_error_set
Sets interrupt indicating link0_fatal_error
the hardware will automatically reset this bit
2 "0"
link0_link_down_reset_set
Sets interrupt indicating link0_link_down_reset
the hardware will automatically reset this bit
1 "0"
link0_hot_reset_set
Sets interrupt indicating link0_hot_reset
the hardware will automatically reset this bit
0 "0"
link0_msi_enabled_set
Sets interrupt indicating link0_msi_enabled
the hardware will automatically reset this bit


pcie_link0_irq_mask
PCIe Link0 IRQ mask
R/W
0x00000040
Address : 0x68020030
Bits Reset value Name Description
31 - 10 0
-
 reserved
9 "0"
link0_msg_sb_fifo_overflow_mask
Masks interrupt indicating link0 message fifo overflow
8 "0"
link0_msg_sb_fifo_not_empty_mask
Masks interrupt indicating link0 message fifo is not empty
7 "0"
link0_reg_access_clk_shutoff_mask
Masks interrupt indicating link0_reg_access_clk_shutoff
6 "1"
link0_power_state_change_mask
Masks interrupt indicating link0_power_state_change
5 "0"
link0_correctable_error_mask
Masks interrupt indicating link0_correctable_error
4 "0"
link0_non_fatal_error_mask
Masks interrupt indicating link0_non_fatal_error
3 "0"
link0_fatal_error_mask
Masks interrupt indicating link0_fatal_error
2 "0"
link0_link_down_reset_mask
Masks interrupt indicating link0_link_down_reset
1 "0"
link0_hot_reset_mask
Masks interrupt indicating link0_hot_reset
0 "0"
link0_msi_enabled_mask
Masks interrupt indicating link0_msi_enabled


pcie_link0_issue_error
PCIe Link0 issue error
W
0x00000000
Address : 0x68020034
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
link0_uncorrectable_error_in
The client may activate this input for one cycle to
indicate an uncorrectable error detected within the
client logic that needs to be reported as an internal
error through the PCI Express Advanced Error
Reporting mechanism. In response, the Controller
sets the Uncorrectable Internal Error Status bit in
the AER Uncorrectable Error Status Register of all
enabled Functions, and in EP mode also sends an
error message if enabled to do so. This error is not
considered Function-specific.
the hardware will automatically reset this bit
0 "0"
link0_correctable_error_in
The client may activate this input for one cycle
to indicate a correctable error detected within the
client logic that needs to be reported as an internal
error through the PCI Express Advanced Error
Reporting mechanism. In response, the Controller
sets the Corrected Internal Error Status bit in
the AER Correctable Error Status Register of all
enabled Functions, and in EP mode also sends an
error message if enabled to do so. This error is not
considered Function-specific.
the hardware will automatically reset this bit


pcie_link0_legacy_irq_mask
PCIe Link0 legacy IRQ mask
R/W
0x00000000
Address : 0x68020038
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
link0_inta_in_mask
set to high enables PCIe legacy interrupt INTA for link 0


pcie_link0_msg_config
PCIe Link0 Message Fifo Configuration
R/W
0x00000001
Address : 0x6802003c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 2 "000000"
link0_msg_vdh_max_data
Max number o 64-bit data words allowed for VD Messages.
If the number of data words of a vendor defined message exceed
this value, the remainind data words are dropped.
1 0
-
 reserved
0 "1"
link0_msg_fifo_enable
Enable Message FIFO
(0) Message FIFO is disabled and all messages are dropped. Message FIFO is cleared.
(1) Message FFIO is enabled and will store message.


pcie_link0_msg_status
PCIe Link0 Message Fifo Status
R
Address : 0x68020040
Bits Name Description
31 - 16 -
 reserved
15 - 8 link0_msg_data_fifo_level
Number of entries in MSG HDR/DATA FIFO
7 -
 reserved
6 - 0 link0_msg_sb_fifo_level
Number of entries in MSG Sideband FIFO


pcie_link0_msg_fifo
PCIe Link0 Message Fifo
R
Address : 0x68020044
Bits Name Description
31 - 0 link0_msg_data
Read Top Of LINK0 Message Header/Data Fifo


pcie_link0_msg_sideband
PCIe Link0 Message Sideband Fifo
R
Address : 0x68020048
Bits Name Description
31 - 0 link0_msg_sb
Read Top Of LINK0 Message Sideband Information FIFO:
0: VDH - This message is a Vendor define message
2-1: NHDR - Number of header words
8-3: NDATA - Number of data words
9: DATA_DROPPED - All or part of data dropped
10: HDR_OVERFLOW - Data FIFO overflow inside header section
11: DATA_OVERFLOW - Data FIFO overflow inside data section
19:12: BYTE_EN_FIRST - Byte Enables of first data word
28:20: BYTE_EN_LAST - Byte Enables of last data word
31:29: Reserved - all 0


pcie_pipe_pma0
PCIe Pipe PMA0
R/W
0x00000003
Address : 0x6802004c
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
pma_cmn_ext_refclk_detected_cfg
External reference clock active detection configuration
0: Do not perform detection
1: Attempt to detect external reference clock active uppon
de-assertion of apb_preset_n
1 - 0 "11"
pma_cmn_refclk_sel
PMA common reference clock select.
0 : Differential 100MHz clock on the cmn_refclk_p and cmn_refclk_m off chip pins.
1 : reserved (not supported by the netx22xx implementation of the PCIe IP)
2 : Single ended clock on the cmn_refclk_p off chip pin.
Note that this mode is only supported for test purposes.
3 : Default: Drive the reference clock internally by the netx22xx XTAL (25MHz).


pcie_pipe_pma0_info
PCIe Pipe PMA0 Info
R
Address : 0x68020050
Bits Name Description
31 - 12 -
 reserved
11 pma_cmn_ext_refclk_detected_valid
External reference clock active detection result valid:
0: Not valid.
1: pma_cmn_ext_refclk_detected value is valid
(i.e. detection operation has completed)
10 pma_cmn_ext_refclk_detected
External reference clock active detection result:
0: Not detected
1: External reference clock detected
9 pma_cmn_ready
PMA common ready - indicates status of
PMA startup.
0: PMA startup is not complete
1: PMA startup is complete (resistor
calibration, VCO calibration and PLL lock)
For observation purposes only.
8 pma_cmn_macro_suspend_ack
PMA common macro suspend
acknowledge - When asserted high,
indicates the PHY is currently in the
suspend state.
For observation purposes only.
7 - 2 -
 reserved
1 link0_clock_stable
The deassertion of this output from 1 to 0, after
the PHY is brought out of reset, indicates that
all the clock outputs from the PHY module are
stable.
This output can be used to deassert the resets to
the Controller during power on reset. It should
be noted that this output is connected to the
pipe_phy_status output of the PHY lane0.
Thus it may toggle after the removal of PHY
Resets. Subsequent transitions of this output
after the first de-assertion should be ignored.
0 pipe_rate0
Indicates the signaling rate to be used by the PHY.
0: 2.5 GT/s
1: 5 GT/s


pcie_link0_hot_reset
PCIe Line0 Hot Reset
R/W
0x00000000
Address : 0x68020054
Bits Reset value Name Description
31 - 1 0
-
 reserved
0 "0"
link0_set_hot_reset
PCIe Core initiates a Hot Reset sequence to Link 0 (Root Complex mode)


pcie_link0_perf_mask_0
PCIe Link0 Performance Counter Mask Register #0
R/W
0x00000000
Address : 0x68020058
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 0 0x0
link0_perf_data_mask_0
Event mask for PCIe performance counter 0
bit(n)=0: dont count event n
bit(n)=1: count event n


pcie_link0_perf_mask_1
PCIe Link0 Performance Counter Mask Register #1
R/W
0x00000000
Address : 0x6802005c
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 0 0x0
link0_perf_data_mask_1
Event mask for PCIe performance counter 1
bit(n)=0: dont count event n
bit(n)=1: count event n


pcie_link0_perf_mask_2
PCIe Link0 Performance Counter Mask Register #2
R/W
0x00000000
Address : 0x68020060
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 0 0x0
link0_perf_data_mask_2
Event mask for PCIe performance counter 2
bit(n)=0: dont count event n
bit(n)=1: count event n


pcie_link0_perf_mask_3
PCIe Link0 Performance Counter Mask Register #3
R/W
0x00000000
Address : 0x68020064
Bits Reset value Name Description
31 - 18 0
-
 reserved
17 - 0 0x0
link0_perf_data_mask_3
Event mask for PCIe performance counter 3
bit(n)=0: dont count event n
bit(n)=1: count event n


pcie_link0_perf_strobe
PCIe Link0 Performance Strobe
W
0x00000000
Address : 0x68020068
Bits Reset value Name Description
31 - 4 0
-
 reserved
3 - 0 "0000"
link0_perf_strobe
Strobe current performance counters into
read out registers PCIE_PERF_CNT_N:
bit(n)=1: Performance counter value is saved into read out latch.
At the same time performance counter is cleared.
the hardware will automatically reset this bit


pcie_link_perf_cnt_0
PCIe Link0 Performance Counter Register #0
R
Address : 0x6802006c
Bits Name Description
31 - 0 link0_perf_cnt_0
Latched PCIe performance counter value 0


pcie_link_perf_cnt_1
PCIe Link0 Performance Counter Register #1
R
Address : 0x68020070
Bits Name Description
31 - 0 link0_perf_cnt_1
Latched PCIe performance counter value 1


pcie_link_perf_cnt_2
PCIe Link0 Performance Counter Register #2
R
Address : 0x68020074
Bits Name Description
31 - 0 link0_perf_cnt_2
Latched PCIe performance counter value 2


pcie_link_perf_cnt_3
PCIe Link0 Performance Counter Register #3
R
Address : 0x68020078
Bits Name Description
31 - 0 link0_perf_cnt_3
Latched PCIe performance counter value 3


pcie_ram_sleep_ctrl
PCIe RAM Sleep Control Register
R/W
0x00000000
Address : 0x68020100
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
dma_table_ram
Put this RAM to sleep
23 - 18 0
-
 reserved
17 "0"
pcie_msg_sb_ram
Put this RAM to sleep
16 "0"
pcie_msg_data_ram
Put this RAM to sleep
15 - 10 0
-
 reserved
9 "0"
axi_dma_outbound_buffer_dpram
Put this RAM to sleep
8 "0"
axi_dma_inbound_buffer_dpram
Put this RAM to sleep
7 0
-
 reserved
6 "0"
axi_master_rfifo
Put this RAM to sleep
5 "0"
axi_slv_fifo
Put this RAM to sleep
4 "0"
sc_fifo
Put this RAM to sleep
3 "0"
pnp_fifo
Put this RAM to sleep
2 "0"
axi_slv_rd_reorder
Put this RAM to sleep
1 "0"
axi_interleaving_sram
Put this RAM to sleep
0 "0"
replay_buffer
Put this RAM to sleep


pcie_ram_shutdown_ctrl
PCIe RAM Shutdown Control Register
R/W
0x0103037f
Address : 0x68020104
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "1"
dma_table_ram
Shutdown this RAM
23 - 18 0
-
 reserved
17 "1"
pcie_msg_sb_ram
Shutdown this RAM
16 "1"
pcie_msg_data_ram
Shutdown this RAM
15 - 10 0
-
 reserved
9 "1"
axi_dma_outbound_buffer_dpram
Shutdown this RAM
8 "1"
axi_dma_inbound_buffer_dpram
Shutdown this RAM
7 0
-
 reserved
6 "1"
axi_master_rfifo
Shutdown this RAM
5 "1"
axi_slv_fifo
Shutdown this RAM
4 "1"
sc_fifo
Shutdown this RAM
3 "1"
pnp_fifo
Shutdown this RAM
2 "1"
axi_slv_rd_reorder
Shutdown this RAM
1 "1"
axi_interleaving_sram
Shutdown this RAM
0 "1"
replay_buffer
Shutdown this RAM


pcie_ram_disable_ctrl
PCIe RAM Disable Control Register
R/W
0x0103037f
Address : 0x68020108
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "1"
dma_table_ram
Disable this RAM (sets memories 'cs' to '0')
23 - 18 0
-
 reserved
17 "1"
pcie_msg_sb_ram
Disable this RAM (sets memories 'cs' to '0')
16 "1"
pcie_msg_data_ram
Disable this RAM (sets memories 'cs' to '0')
15 - 10 0
-
 reserved
9 "1"
axi_dma_outbound_buffer_dpram
Disable this RAM (sets memories 'cs' to '0')
8 "1"
axi_dma_inbound_buffer_dpram
Disable this RAM (sets memories 'cs' to '0')
7 0
-
 reserved
6 "1"
axi_master_rfifo
Disable this RAM (sets memories 'cs' to '0')
5 "1"
axi_slv_fifo
Disable this RAM (sets memories 'cs' to '0')
4 "1"
sc_fifo
Disable this RAM (sets memories 'cs' to '0')
3 "1"
pnp_fifo
Disable this RAM (sets memories 'cs' to '0')
2 "1"
axi_slv_rd_reorder
Disable this RAM (sets memories 'cs' to '0')
1 "1"
axi_interleaving_sram
Disable this RAM (sets memories 'cs' to '0')
0 "1"
replay_buffer
Disable this RAM (sets memories 'cs' to '0')


pcie_ram_autosleep_ctrl_mask
PCIe RAM Autosleep Control Mask Register
R/W
0x00000000
Address : 0x6802010c
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
dma_table_ram
When set, this RAM will automatically be set to sleep by the IP
23 - 18 0
-
 reserved
17 "0"
pcie_msg_sb_ram
When set, this RAM will automatically be set to sleep by the IP
16 "0"
pcie_msg_data_ram
When set, this RAM will automatically be set to sleep by the IP
15 - 10 0
-
 reserved
9 "0"
axi_dma_outbound_buffer_dpram
When set, this RAM will automatically be set to sleep by the IP
8 "0"
axi_dma_inbound_buffer_dpram
When set, this RAM will automatically be set to sleep by the IP
7 0
-
 reserved
6 "0"
axi_master_rfifo
When set, this RAM will automatically be set to sleep by the IP
5 "0"
axi_slv_fifo
When set, this RAM will automatically be set to sleep by the IP
4 "0"
sc_fifo
When set, this RAM will automatically be set to sleep by the IP
3 "0"
pnp_fifo
When set, this RAM will automatically be set to sleep by the IP
2 "0"
axi_slv_rd_reorder
When set, this RAM will automatically be set to sleep by the IP
1 "0"
axi_interleaving_sram
When set, this RAM will automatically be set to sleep by the IP
0 "0"
replay_buffer
When set, this RAM will automatically be set to sleep by the IP


pcie_ram_autosleep_ctrl
PCIe RAM Autosleep Control
R/W
0x00000000
Address : 0x68020110
Bits Reset value Name Description
31 "0"
sleep_synced
Set, when the sequencer is done synchronizing the requested input vector
this bit will be reset automatically by hardware
30 - 24 0
-
 reserved
23 - 16 "00000000"
propagate_sleep_ticks
Defines in pm_clk cycles how many periods should be waited between
waking different RAMs or putting them to the sleep state
15 - 11 "00000"
disable_ticks
Determines how many clock ticks in the disabling clk-domain the mem_disable signal will be
asserted before transitioning into sleep.
e.g.: 0 -> mem_disable (disables cs pin on memories) and mem_sleep are asserted simultaneously
3 -> mem_disable is asserted and 3 clk ticks later mem_sleep is asserted
NOTE: only used with the pcie_autosleep feature
When RAMs are put to sleep or shutdown manually, the SW designer needs to
implement a suitable delay between mem_disable als sleep/shutdown assertion
10 - 2 0
-
 reserved
1 "0"
invert_polarity
Invert the polarity of the IP's sleep control signal (derived from link_state / clkreq)
0 "0"
enable_autosleep
When set, the IP's link state (clkreq signal) will be used to selectively put the RAMs to sleep.
The RAMs which should be put to sleep can be selected using the autosleep_ctrl_mask register


pcie_ram_ctrl_shutdown_timing
PCIe RAM shutdown propagate tick count register
R/W
0x00000000
Address : 0x68020114
Bits Reset value Name Description
31 "0"
shutdown_synced
Set, when the sequencer is done synchronizing the requested input vector
this bit will be reset automatically by hardware
30 - 8 0
-
 reserved
7 - 0 "00000000"
propagate_shutdown_ticks
Defines in pm_clk cycles how many periods should be waited between
waking different RAMs or putting them to the sleep state



Base Address Area: irq2msi_cfg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_irq2msi_msi_addr
1 4 R/W pcie_irq2msi_msi_data
2 8 R/W pcie_irq2msi_cfg
3 c R pcie_irq2msi_axi_state

pcie_irq2msi_msi_addr
IRQ2MSI MSI address register
R/W
0x00000000
Address : 0x68030000
Bits Reset value Name Description
31 - 0 0x0
addr
32 bit AXI address, which should be written to in order to trigger a MSI memory write.


pcie_irq2msi_msi_data
IRQ2MSI MSI data register
R/W
0x00000000
Address : 0x68030004
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
data
16 bit AXI write payload, which should be written in the MSI memory write.


pcie_irq2msi_cfg
IRQ2MSI Config register
R/W
0x00000000
Address : 0x68030008
Bits Reset value Name Description
31 - 9 0
-
 reserved
8 "0"
ack_resp
(write-only) Acknowledge the axi_state.resp, clearing any errors and resetting the latching mechanism. The cleared registers are:
axi_state.resp_valid
axi_state.resp_id
axi_state.resp

the hardware will automatically reset this bit
7 - 2 0
-
 reserved
1 "0"
auto_disable
If set, the module is automatically disabled when the 'msi_enable' deasserts,
by clearing the 'enable' bit. This allows software to reconfigure the address and
payload registers before a new MSI access is generated by the hardware.
0 "0"
enable
Enable processing within this module. Module operation is additionally gated by the 'msi_enable' input.

writable, but can also be changed by hardware


pcie_irq2msi_axi_state
IRQ2MSI AXI state register
R
Address : 0x6803000c
Bits Name Description
31 - 8 -
 reserved
7 resp_valid
Set if a AXI write response was latched.
This register will be cleared along with 'resp' when the cfg.ack_resp bit is set.
6 - 2 resp_id
The response ID of the last AXI write response. If an error response is detected it is latched and cannot be overwritten by successive bus responses.
The resp_id is mapped 1:1 to the interrupt input vector.
A resp_id==4 means that interrupt[4] sent this MSI write access.
This register will be cleared along with 'resp' when the cfg.ack_resp bit is set.
1 - 0 resp
Last AXI write response. If an error response (SLVERR | DECERR) is detected it is latched and cannot be overwritten by successive bus responses.
This register will be cleared when the cfg.ack_resp bit is set.



Base Address Area: msi2irq_0_cfg, msi2irq_1_cfg, msi2irq_2_cfg, msi2irq_3_cfg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_msi2irq_cfg_irq_raw
1 4 R/W pcie_msi2irq_cfg_irq_masked
2 8 R/W pcie_msi2irq_cfg_irq_mask_set
3 c R/W pcie_msi2irq_cfg_irq_mask_rst
4 10 R/W pcie_msi2irq_cfg_data_mask
5 14 R pcie_msi2irq_cfg_last_msg
6-7 18-1c -  reserved

pcie_msi2irq_cfg_irq_raw
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address@msi2irq_0_cfg : 0x68030020
Address@msi2irq_1_cfg : 0x68030040
Address@msi2irq_2_cfg : 0x68030060
Address@msi2irq_3_cfg : 0x68030080
Bits Reset value Name Description
31 "0"
irq31
EVENT: IRQ 31 of vector
30 "0"
irq30
EVENT: IRQ 30 of vector
29 "0"
irq29
EVENT: IRQ 29 of vector
28 "0"
irq28
EVENT: IRQ 28 of vector
27 "0"
irq27
EVENT: IRQ 27 of vector
26 "0"
irq26
EVENT: IRQ 26 of vector
25 "0"
irq25
EVENT: IRQ 25 of vector
24 "0"
irq24
EVENT: IRQ 24 of vector
23 "0"
irq23
EVENT: IRQ 23 of vector
22 "0"
irq22
EVENT: IRQ 22 of vector
21 "0"
irq21
EVENT: IRQ 21 of vector
20 "0"
irq20
EVENT: IRQ 20 of vector
19 "0"
irq19
EVENT: IRQ 19 of vector
18 "0"
irq18
EVENT: IRQ 18 of vector
17 "0"
irq17
EVENT: IRQ 17 of vector
16 "0"
irq16
EVENT: IRQ 16 of vector
15 "0"
irq15
EVENT: IRQ 15 of vector
14 "0"
irq14
EVENT: IRQ 14 of vector
13 "0"
irq13
EVENT: IRQ 13 of vector
12 "0"
irq12
EVENT: IRQ 12 of vector
11 "0"
irq11
EVENT: IRQ 11 of vector
10 "0"
irq10
EVENT: IRQ 10 of vector
9 "0"
irq9
EVENT: IRQ 9 of vector
8 "0"
irq8
EVENT: IRQ 8 of vector
7 "0"
irq7
EVENT: IRQ 7 of vector
6 "0"
irq6
EVENT: IRQ 6 of vector
5 "0"
irq5
EVENT: IRQ 5 of vector
4 "0"
irq4
EVENT: IRQ 4 of vector
3 "0"
irq3
EVENT: IRQ 3 of vector
2 "0"
irq2
EVENT: IRQ 2 of vector
1 "0"
irq1
EVENT: IRQ 1 of vector
0 "0"
irq0
EVENT: IRQ 0 of vector


pcie_msi2irq_cfg_irq_masked
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_pcie_msi2irq_cfg_irq_raw).
R/W
0x00000000
Address@msi2irq_0_cfg : 0x68030024
Address@msi2irq_1_cfg : 0x68030044
Address@msi2irq_2_cfg : 0x68030064
Address@msi2irq_3_cfg : 0x68030084
Bits Reset value Name Description
31 "0"
irq31
EVENT: IRQ 31 of vector
30 "0"
irq30
EVENT: IRQ 30 of vector
29 "0"
irq29
EVENT: IRQ 29 of vector
28 "0"
irq28
EVENT: IRQ 28 of vector
27 "0"
irq27
EVENT: IRQ 27 of vector
26 "0"
irq26
EVENT: IRQ 26 of vector
25 "0"
irq25
EVENT: IRQ 25 of vector
24 "0"
irq24
EVENT: IRQ 24 of vector
23 "0"
irq23
EVENT: IRQ 23 of vector
22 "0"
irq22
EVENT: IRQ 22 of vector
21 "0"
irq21
EVENT: IRQ 21 of vector
20 "0"
irq20
EVENT: IRQ 20 of vector
19 "0"
irq19
EVENT: IRQ 19 of vector
18 "0"
irq18
EVENT: IRQ 18 of vector
17 "0"
irq17
EVENT: IRQ 17 of vector
16 "0"
irq16
EVENT: IRQ 16 of vector
15 "0"
irq15
EVENT: IRQ 15 of vector
14 "0"
irq14
EVENT: IRQ 14 of vector
13 "0"
irq13
EVENT: IRQ 13 of vector
12 "0"
irq12
EVENT: IRQ 12 of vector
11 "0"
irq11
EVENT: IRQ 11 of vector
10 "0"
irq10
EVENT: IRQ 10 of vector
9 "0"
irq9
EVENT: IRQ 9 of vector
8 "0"
irq8
EVENT: IRQ 8 of vector
7 "0"
irq7
EVENT: IRQ 7 of vector
6 "0"
irq6
EVENT: IRQ 6 of vector
5 "0"
irq5
EVENT: IRQ 5 of vector
4 "0"
irq4
EVENT: IRQ 4 of vector
3 "0"
irq3
EVENT: IRQ 3 of vector
2 "0"
irq2
EVENT: IRQ 2 of vector
1 "0"
irq1
EVENT: IRQ 1 of vector
0 "0"
irq0
EVENT: IRQ 0 of vector


pcie_msi2irq_cfg_irq_mask_set
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_pcie_msi2irq_cfg_irq_raw
R/W
0x00000000
Address@msi2irq_0_cfg : 0x68030028
Address@msi2irq_1_cfg : 0x68030048
Address@msi2irq_2_cfg : 0x68030068
Address@msi2irq_3_cfg : 0x68030088
Bits Reset value Name Description
31 "0"
irq31
EVENT: IRQ 31 of vector
30 "0"
irq30
EVENT: IRQ 30 of vector
29 "0"
irq29
EVENT: IRQ 29 of vector
28 "0"
irq28
EVENT: IRQ 28 of vector
27 "0"
irq27
EVENT: IRQ 27 of vector
26 "0"
irq26
EVENT: IRQ 26 of vector
25 "0"
irq25
EVENT: IRQ 25 of vector
24 "0"
irq24
EVENT: IRQ 24 of vector
23 "0"
irq23
EVENT: IRQ 23 of vector
22 "0"
irq22
EVENT: IRQ 22 of vector
21 "0"
irq21
EVENT: IRQ 21 of vector
20 "0"
irq20
EVENT: IRQ 20 of vector
19 "0"
irq19
EVENT: IRQ 19 of vector
18 "0"
irq18
EVENT: IRQ 18 of vector
17 "0"
irq17
EVENT: IRQ 17 of vector
16 "0"
irq16
EVENT: IRQ 16 of vector
15 "0"
irq15
EVENT: IRQ 15 of vector
14 "0"
irq14
EVENT: IRQ 14 of vector
13 "0"
irq13
EVENT: IRQ 13 of vector
12 "0"
irq12
EVENT: IRQ 12 of vector
11 "0"
irq11
EVENT: IRQ 11 of vector
10 "0"
irq10
EVENT: IRQ 10 of vector
9 "0"
irq9
EVENT: IRQ 9 of vector
8 "0"
irq8
EVENT: IRQ 8 of vector
7 "0"
irq7
EVENT: IRQ 7 of vector
6 "0"
irq6
EVENT: IRQ 6 of vector
5 "0"
irq5
EVENT: IRQ 5 of vector
4 "0"
irq4
EVENT: IRQ 4 of vector
3 "0"
irq3
EVENT: IRQ 3 of vector
2 "0"
irq2
EVENT: IRQ 2 of vector
1 "0"
irq1
EVENT: IRQ 1 of vector
0 "0"
irq0
EVENT: IRQ 0 of vector


pcie_msi2irq_cfg_irq_mask_rst
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 32 when no IRQ is set:
  0  : irq-irq0
  1  : irq-irq1
  2  : irq-irq2
  3  : irq-irq3
  4  : irq-irq4
  5  : irq-irq5
  6  : irq-irq6
  7  : irq-irq7
  8  : irq-irq8
  9  : irq-irq9
  10 : irq-irq10
  11 : irq-irq11
  12 : irq-irq12
  13 : irq-irq13
  14 : irq-irq14
  15 : irq-irq15
  16 : irq-irq16
  17 : irq-irq17
  18 : irq-irq18
  19 : irq-irq19
  20 : irq-irq20
  21 : irq-irq21
  22 : irq-irq22
  23 : irq-irq23
  24 : irq-irq24
  25 : irq-irq25
  26 : irq-irq26
  27 : irq-irq27
  28 : irq-irq28
  29 : irq-irq29
  30 : irq-irq30
  31 : irq-irq31
  32 : no active IRQ
R/W
0x00000000
Address@msi2irq_0_cfg : 0x6803002c
Address@msi2irq_1_cfg : 0x6803004c
Address@msi2irq_2_cfg : 0x6803006c
Address@msi2irq_3_cfg : 0x6803008c
Bits Reset value Name Description
31 "0"
irq31
EVENT: IRQ 31 of vector
30 "0"
irq30
EVENT: IRQ 30 of vector
29 "0"
irq29
EVENT: IRQ 29 of vector
28 "0"
irq28
EVENT: IRQ 28 of vector
27 "0"
irq27
EVENT: IRQ 27 of vector
26 "0"
irq26
EVENT: IRQ 26 of vector
25 "0"
irq25
EVENT: IRQ 25 of vector
24 "0"
irq24
EVENT: IRQ 24 of vector
23 "0"
irq23
EVENT: IRQ 23 of vector
22 "0"
irq22
EVENT: IRQ 22 of vector
21 "0"
irq21
EVENT: IRQ 21 of vector
20 "0"
irq20
EVENT: IRQ 20 of vector
19 "0"
irq19
EVENT: IRQ 19 of vector
18 "0"
irq18
EVENT: IRQ 18 of vector
17 "0"
irq17
EVENT: IRQ 17 of vector
16 "0"
irq16
EVENT: IRQ 16 of vector
15 "0"
irq15
EVENT: IRQ 15 of vector
14 "0"
irq14
EVENT: IRQ 14 of vector
13 "0"
irq13
EVENT: IRQ 13 of vector
12 "0"
irq12
EVENT: IRQ 12 of vector
11 "0"
irq11
EVENT: IRQ 11 of vector
10 "0"
irq10
EVENT: IRQ 10 of vector
9 "0"
irq9
EVENT: IRQ 9 of vector
8 "0"
irq8
EVENT: IRQ 8 of vector
7 "0"
irq7
EVENT: IRQ 7 of vector
6 "0"
irq6
EVENT: IRQ 6 of vector
5 "0"
irq5
EVENT: IRQ 5 of vector
4 "0"
irq4
EVENT: IRQ 4 of vector
3 "0"
irq3
EVENT: IRQ 3 of vector
2 "0"
irq2
EVENT: IRQ 2 of vector
1 "0"
irq1
EVENT: IRQ 1 of vector
0 "0"
irq0
EVENT: IRQ 0 of vector


pcie_msi2irq_cfg_data_mask
MSI data mask register
R/W
0x00000000
Address@msi2irq_0_cfg : 0x68030030
Address@msi2irq_1_cfg : 0x68030050
Address@msi2irq_2_cfg : 0x68030070
Address@msi2irq_3_cfg : 0x68030090
Bits Reset value Name Description
31 - 16 0x0
data
Data word that must be matched against the incoming MSI write request
15 - 0 0x0
msk
msk[n]==1: Bit n of incoming MSI write request must match against the corresponding bit in msi_data.data field
If the msk bits in the write request do not match the data bits in this register, no IRQ is generated
msk[4:0] also define if the LSBs of the input payload should be used to address an index of an IRQ.
The IRQ to trigger index is defined as: irq_index = ~msk[4:0] & write_data[4:0]


pcie_msi2irq_cfg_last_msg
MSI last message register
R
Address@msi2irq_0_cfg : 0x68030034
Address@msi2irq_1_cfg : 0x68030054
Address@msi2irq_2_cfg : 0x68030074
Address@msi2irq_3_cfg : 0x68030094
Bits Name Description
31 - 16 -
 reserved
15 - 0 msg
last MSI message



Base Address Area: pcie_ep_cfg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R pcie_ep_cfg_id
1 4 R/W pcie_ep_cfg_command_status
2 8 - pcie_ep_cfg_revision_id_class_code
3 c - pcie_ep_cfg_bist_header_latency_cache_line
4 10 R/W pcie_ep_cfg_base_addr_0
5 14 R/W pcie_ep_cfg_base_addr_1
6-23 18-8c -  reserved
24 90 R/W pcie_ep_cfg_msi_ctrl
25 94 R/W pcie_ep_cfg_msi_addr_low
26 98 R/W pcie_ep_cfg_msi_addr_high
27 9c R/W pcie_ep_cfg_msi_msg_data
28 a0 R/W pcie_ep_cfg_msi_mask
29-242 a4-908 -  reserved
243 90c R/W pcie_ep_cfg_l1_pm_substates_ctrl_2
244-3ff 910-ffc -  reserved

pcie_ep_cfg_id
EP Vendor ID and Device ID register
R
Address : 0x6f800000
Bits Name Description
31 - 16 device_id
Device ID assigned by the manufacturer of the device.
This field can be rewritten independently for each Function from the local management bus.
15 - 0 vendor_id
Vendor ID assigned by PCI SIG to the manufacturer of the device.
The Vendor ID register is set within the local management register block.


pcie_ep_cfg_command_status
EP Command and Status register
R/W
0x00100000
Address : 0x6f800004
Bits Reset value Name Description
31 "0"
dpe
Detected Parity Error
30 "0"
sse
Signaled System Error
29 "0"
rma
Received Master Abort
28 "0"
rta
Received Target Abort
27 "0"
sta
Signaled Target Abort
26 - 25 0
-
 reserved
24 "0"
mdpe
Master Data Parity Error
23 - 21 0
-
 reserved
20 -
cl_ro
Capabilities List
19 -
is_ro
Interrupt Status
18 - 11 0
-
 reserved
10 "0"
imd
INTx Message Disabled
9 0
-
 reserved
8 "0"
se
SERR Enable
7 0
-
 reserved
6 "0"
pere
Parity Error Response Enable
5 - 3 0
-
 reserved
2 "0"
be
Bus-Master Enable
Controls the ability of a Function to issue Memory and I/O Read/Write Requests,
in the Upstream direction. Can be written from the local management bus.
The Controller does not gate any requests based on this bit, the Client Application must handle that.
1 "0"
mse
Mem-Space Enable
Same as ise, but with Memory-Space accesses.
0 "0"
ise
IO-Space Enable
Controls a Function's response to IO Space accesses from PCIe Link.
When this bit is 0: all IO Space accesses are handled as Unsupported Requests
When this bit is 1: all received IO Space accesses are decoded and processed normally
Can be written from the local management bus.


pcie_ep_cfg_revision_id_class_code

Address : 0x6f800008
Bits Name Description
31 - 0 pcie_ep_cfg_revision_id_class_code


pcie_ep_cfg_bist_header_latency_cache_line

Address : 0x6f80000c
Bits Name Description
31 - 0 pcie_ep_cfg_bist_header_latency_cache_line


pcie_ep_cfg_base_addr_0
EP Base Address Register 0
R/W
0x00000004
Address : 0x6f800010
Bits Reset value Name Description
31 - 22 0x0
bamrw
Base Address - RW part
21 - 8 -
bamro_ro
Base Address - RO part
7 - 4 0
-
 reserved
3 -
po_ro
Prefetchability
0: non-prefetchable
1: prefetchable
2 -
so_ro
Size
0: 32-bit
1: 64-bit
1 0
-
 reserved
0 -
msio_ro
Memory Space Indicator
0: memory
1: I/O


pcie_ep_cfg_base_addr_1
EP Base Address Register 1
R/W
0x00000000
Address : 0x6f800014
Bits Reset value Name Description
31 - 0 0x0
bamrw
Base Address - RW part
Only active when register before this one is configured as 64-bit.
When the previous register is 32-bit, this can be configured as another 32-bit one.


pcie_ep_cfg_msi_ctrl
EP MSI Control Register
R/W
0x00000000
Address : 0x6f800090
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 -
mc_ro
MSI masking capable
23 -
bac64_ro
64-bit Address Capable
22 - 20 "000"
mme
Multiple Message Enable
19 - 17 -
mmc_ro
Multiple Message Capable
16 "0"
me
MSI Enable, set to enable MSI feature
15 - 8 -
cp1_ro
Pointer to the next PCI Capability structure.
7 - 0 -
cid1_ro
Specifies that the capability structure is for MSI. Hardwired.


pcie_ep_cfg_msi_addr_low
EP MSI Message Low Address Register
R/W
0x00000000
Address : 0x6f800094
Bits Reset value Name Description
31 - 0 0x0
mal
32 lower bits of the address to be used in MSI messages


pcie_ep_cfg_msi_addr_high
EP MSI Message High Address Register
R/W
0x00000000
Address : 0x6f800098
Bits Reset value Name Description
31 - 0 0x0
mah
32 upper bits of the address to be used in MSI messages
A value of 0 specifies that 32-bit addresses are to be used.


pcie_ep_cfg_msi_msg_data
EP MSI Message Data Register
R/W
0x00000000
Address : 0x6f80009c
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 - 0 0x0
md
Message Data, payload to be used for this function.


pcie_ep_cfg_msi_mask
EP MSI Mask Register
R/W
0x00000000
Address : 0x6f8000a0
Bits Reset value Name Description
31 - 0 0x0
mm
MSI Mask , bitfield width changes with Multiple Message Capable configuration


pcie_ep_cfg_l1_pm_substates_ctrl_2
EP L1 PM Substates Control 2 Register
R/W
0x00000028
Address : 0x6f80090c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 3 "00101"
l1pwronval
Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the
Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.
T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.
2 0
-
 reserved
1 - 0 "00"
l1pwronsc
Specifies the scale used for T_POWER_ON Value.
Range of Values: 00b = 2us, 01b = 10us, 10b = 100us, 11b = reserved



Base Address Area: pcie_rp_cfg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R pcie_rp_cfg_id
1 4 R/W pcie_rp_cfg_command_status
2 8 - pcie_rp_cfg_revision_id_class_code
3 c - pcie_rp_cfg_bist_header_latency_cache_line
4-242 10-908 -  reserved
243 90c R/W pcie_rp_cfg_l1_pm_substates_ctrl_2
244-3ff 910-ffc -  reserved

pcie_rp_cfg_id
RP Vendor ID and Device ID register
R
Address : 0x6f800000
Bits Name Description
31 - 16 device_id
Device ID assigned by the manufacturer of the device.
This field can be rewritten independently for each Function from the local management bus.
15 - 0 vendor_id
Vendor ID assigned by PCI SIG to the manufacturer of the device.
The Vendor ID register is set within the local management register block.


pcie_rp_cfg_command_status
RP Command and Status register
R/W
0x00100000
Address : 0x6f800004
Bits Reset value Name Description
31 "0"
dpe
Detected Parity Error
30 "0"
sse
Signaled System Error
29 "0"
rma
Received Master Abort
28 "0"
rta
Received Target Abort
27 "0"
sta
Signaled Target Abort
26 - 25 0
-
 reserved
24 "0"
mdpe
Master Data Parity Error
23 - 21 0
-
 reserved
20 -
cl_ro
Capabilities List
19 -
is_ro
Interrupt Status
18 - 11 0
-
 reserved
10 "0"
imd
INTx Message Disabled
9 0
-
 reserved
8 "0"
se
SERR Enable
7 0
-
 reserved
6 "0"
pere
Parity Error Response Enable
5 - 3 0
-
 reserved
2 "0"
be
Bus-Master Enable
Controls the ability of a Function to issue Memory and I/O Read/Write Requests,
in the Upstream direction. Can be written from the local management bus.
The Controller does not gate any requests based on this bit, the Client Application must handle that.
1 "0"
mse
Mem-Space Enable
Same as ise, but with Memory-Space accesses.
0 "0"
ise
IO-Space Enable
Controls a Function's response to IO Space accesses from PCIe Link.
When this bit is 0: all IO Space accesses are handled as Unsupported Requests
When this bit is 1: all received IO Space accesses are decoded and processed normally
Can be written from the local management bus.


pcie_rp_cfg_revision_id_class_code

Address : 0x6f800008
Bits Name Description
31 - 0 pcie_rp_cfg_revision_id_class_code


pcie_rp_cfg_bist_header_latency_cache_line

Address : 0x6f80000c
Bits Name Description
31 - 0 pcie_rp_cfg_bist_header_latency_cache_line


pcie_rp_cfg_l1_pm_substates_ctrl_2
RP L1 PM Substates Control 2 Register
R/W
0x00000028
Address : 0x6f80090c
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 3 "00101"
l1pwronval
Along with the T_POWER_ON Scale sets the minimum amount of time (in us) that the
Port must wait in L1.2.Exit after sampling CLKREQ# asserted before actively driving the interface.
T_POWER_ON is calculated by multiplying the value in this field by the value in the T_POWER_ON Scale field.
2 0
-
 reserved
1 - 0 "00"
l1pwronsc
Specifies the scale used for T_POWER_ON Value.
Range of Values: 00b = 2us, 01b = 10us, 10b = 100us, 11b = reserved



Base Address Area: pcie_local_mgmt

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_local_mgmt_i_pl_config_0_reg
1-3ed 4-fb4 -  reserved
3ee fb8 R/W pcie_local_mgmt_i_ltssm_timer_control_reg3
3ef-3ff fbc-ffc -  reserved

pcie_local_mgmt_i_pl_config_0_reg
Physical Layer Configuration Register 0
R/W
0x00000020
Address : 0x6f900000
Bits Reset value Name Description
31 "0"
mle
Master Loopback Enable
When the Controller is operating as a Root Port, setting this bit to 1 causes the LTSSM to initiate
a loopback and become the loopback master. This bit is not used in the EndPoint Mode.
30 -
r0_ro
Remote Linkwidth Upconfigure Capability Status.
More info in UserDoc.
29 - 24 -
ltssm_ro
Current state of the LTSSM. The encoding of the states is given in Appendix C.
More info in UserDoc.
23 - 16 -
rlid_ro
Link ID received from other side during link training.
15 - 8 -
rfc_ro
FTS count received from the other side during link training for use at the 2.5GT/s link speed.
More info in UserDoc.
7 "0"
tss
This bit drives the PIPE_TX_SWING output of the controller.
6 "0"
aper
This bit controls the reporting of Errors Detected by the PHY.
More info in UserDoc.
5 -
ltd_ro
The state of this bit indicates whether the Controller completed link training as an upstream
port(EndPoint)(=0) of a downstream port(RootPort)(=1).Default value depends on CORE_TYPE strap pin.
4 - 3 -
ns_ro
Current operating speed of link (b00 = 2.5G, b01 = 5G, b10 = 8G, b11 = 16G)
2 - 1 0
-
 reserved
0 -
ls_ro
Current state of the link (1 = link training complete, 0 = link training not complete)


pcie_local_mgmt_i_ltssm_timer_control_reg3
LTSSM Timer Control Register 3
R/W
0xb71b7a12
Address : 0x6f900fb8
Bits Reset value Name Description
31 - 16 0xb71b
l48mstm
LTSSM 48ms Time Interval
More info in UserDoc.
15 - 0 0x7a12
l32mstm
LTSSM 32ms Time Interval
More info in UserDoc.



Base Address Area: pcie_axi_cfg

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_axi_cfg_outbound_at_reg0
1-21c 4-870 -  reserved
21d 874 R/W pcie_axi_cfg_function0_bar6_ep_inbound_at_reg1
21e 878 -  reserved
21f 87c R/W pcie_axi_cfg_reserved
220-3ff 880-ffc -  reserved

pcie_axi_cfg_outbound_at_reg0
Region 0 Outbound AXI to PCIe Address Translation Register 0
R/W
0x00000000
Address : 0x6fc00000
Bits Reset value Name Description
31 - 8 0x0
data
Bits [31:8] of PCIe Address Register for region N
7 - 6 0
-
 reserved
5 - 0 "000000"
num_bits
Number_bits + 1 bits are passed through from AXI address to the PCIe address


pcie_axi_cfg_function0_bar6_ep_inbound_at_reg1
Function 0 BAR 6 End Point Inbound PCIe to AXI Address Translation Register 1
R/W
0x00000000
Address : 0x6fc00874
Bits Reset value Name Description
31 - 0 0x0
data
Bits [63:32] of AXI Address Register for BAR N


pcie_axi_cfg_reserved
Reserved
R/W
0x00000000
Address : 0x6fc0087c
Bits Reset value Name Description
31 - 0 0x0
data
Bits [63:32] of AXI Address Register for BAR N



Base Address Area: pcie_dma

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W pcie_dma_channel0_ctrl
1 4 R/W pcie_dma_channel0_sp_l
2 8 R/W pcie_dma_channel0_sp_u
3 c R/W pcie_dma_channel0_attr_l
4 10 R/W pcie_dma_channel0_attr_u
5 14 R/W pcie_dma_channel1_ctrl
6 18 R/W pcie_dma_channel1_sp_l
7 1c R/W pcie_dma_channel1_sp_u
8 20 R/W pcie_dma_channel1_attr_l
9 24 R/W pcie_dma_channel1_attr_u
a 28 R/W pcie_dma_channel2_ctrl
b 2c R/W pcie_dma_channel2_sp_l
c 30 R/W pcie_dma_channel2_sp_u
d 34 R/W pcie_dma_channel2_attr_l
e 38 R/W pcie_dma_channel2_attr_u
f 3c R/W pcie_dma_channel3_ctrl
10 40 R/W pcie_dma_channel3_sp_l
11 44 R/W pcie_dma_channel3_sp_u
12 48 R/W pcie_dma_channel3_attr_l
13 4c R/W pcie_dma_channel3_attr_u
14-27 50-9c -  reserved
28 a0 R/W pcie_dma_common_udma_int
29 a4 R/W pcie_dma_common_udma_int_ena
2a a8 R/W pcie_dma_common_udma_int_dis
2b ac R pcie_dma_common_udma_ib_ecc_uncorrectable_errors
2c b0 R pcie_dma_common_udma_ib_ecc_correctable_errors
2d b4 R pcie_dma_common_udma_ob_ecc_uncorrectable_errors
2e b8 R pcie_dma_common_udma_ob_ecc_correctable_errors
2f-3d bc-f4 -  reserved
3e f8 R pcie_dma_common_udma_cap_ver
3f fc R pcie_dma_common_udma_config
40-3ff 100-ffc -  reserved

pcie_dma_channel0_ctrl
DMA Channel 0 Control Register
R/W
0x00000000
Address : 0x6fe00000
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
ob_not_ib
Outbound transfer, not inbound.
Determines the direction of the DMA transfer
0 "0"
go
Kicks off the uDMA channel controller to fetch
valid Outbound or Inbound linked list.


pcie_dma_channel0_sp_l
DMA Channel 0 Start Pointer Lower Register
R/W
0x00000000
Address : 0x6fe00004
Bits Reset value Name Description
31 - 0 0x0
ptr
Lower 32-bits Pointer Address Registers


pcie_dma_channel0_sp_u
DMA Channel 0 Start Pointer Upper Register
R/W
0x00000000
Address : 0x6fe00008
Bits Reset value Name Description
31 - 0 0x0
ptr
Upper 32-bits Pointer Address Registers


pcie_dma_channel0_attr_l
DMA Channel 0 Attribute Lower Register
R/W
0x00000000
Address : 0x6fe0000c
Bits Reset value Name Description
31 - 0 0x0
attr
Lower 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel0_attr_u
DMA Channel 0 Attribute Upper Register
R/W
0x00000000
Address : 0x6fe00010
Bits Reset value Name Description
31 - 0 0x0
attr
Upper 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel1_ctrl
DMA Channel 1 Control Register
R/W
0x00000000
Address : 0x6fe00014
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
ob_not_ib
Outbound transfer, not inbound.
Determines the direction of the DMA transfer
0 "0"
go
Kicks off the uDMA channel controller to fetch
valid Outbound or Inbound linked list.


pcie_dma_channel1_sp_l
DMA Channel 1 Start Pointer Lower Register
R/W
0x00000000
Address : 0x6fe00018
Bits Reset value Name Description
31 - 0 0x0
ptr
Lower 32-bits Pointer Address Registers


pcie_dma_channel1_sp_u
DMA Channel 1 Start Pointer Upper Register
R/W
0x00000000
Address : 0x6fe0001c
Bits Reset value Name Description
31 - 0 0x0
ptr
Upper 32-bits Pointer Address Registers


pcie_dma_channel1_attr_l
DMA Channel 1 Attribute Lower Register
R/W
0x00000000
Address : 0x6fe00020
Bits Reset value Name Description
31 - 0 0x0
attr
Lower 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel1_attr_u
DMA Channel 1 Attribute Upper Register
R/W
0x00000000
Address : 0x6fe00024
Bits Reset value Name Description
31 - 0 0x0
attr
Upper 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel2_ctrl
DMA Channel 2 Control Register
R/W
0x00000000
Address : 0x6fe00028
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
ob_not_ib
Outbound transfer, not inbound.
Determines the direction of the DMA transfer
0 "0"
go
Kicks off the uDMA channel controller to fetch
valid Outbound or Inbound linked list.


pcie_dma_channel2_sp_l
DMA Channel 2 Start Pointer Lower Register
R/W
0x00000000
Address : 0x6fe0002c
Bits Reset value Name Description
31 - 0 0x0
ptr
Lower 32-bits Pointer Address Registers


pcie_dma_channel2_sp_u
DMA Channel 2 Start Pointer Upper Register
R/W
0x00000000
Address : 0x6fe00030
Bits Reset value Name Description
31 - 0 0x0
ptr
Upper 32-bits Pointer Address Registers


pcie_dma_channel2_attr_l
DMA Channel 2 Attribute Lower Register
R/W
0x00000000
Address : 0x6fe00034
Bits Reset value Name Description
31 - 0 0x0
attr
Lower 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel2_attr_u
DMA Channel 2 Attribute Upper Register
R/W
0x00000000
Address : 0x6fe00038
Bits Reset value Name Description
31 - 0 0x0
attr
Upper 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel3_ctrl
DMA Channel 3 Control Register
R/W
0x00000000
Address : 0x6fe0003c
Bits Reset value Name Description
31 - 2 0
-
 reserved
1 "0"
ob_not_ib
Outbound transfer, not inbound.
Determines the direction of the DMA transfer
0 "0"
go
Kicks off the uDMA channel controller to fetch
valid Outbound or Inbound linked list.


pcie_dma_channel3_sp_l
DMA Channel 3 Start Pointer Lower Register
R/W
0x00000000
Address : 0x6fe00040
Bits Reset value Name Description
31 - 0 0x0
ptr
Lower 32-bits Pointer Address Registers


pcie_dma_channel3_sp_u
DMA Channel 3 Start Pointer Upper Register
R/W
0x00000000
Address : 0x6fe00044
Bits Reset value Name Description
31 - 0 0x0
ptr
Upper 32-bits Pointer Address Registers


pcie_dma_channel3_attr_l
DMA Channel 3 Attribute Lower Register
R/W
0x00000000
Address : 0x6fe00048
Bits Reset value Name Description
31 - 0 0x0
attr
Lower 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_channel3_attr_u
DMA Channel 3 Attribute Upper Register
R/W
0x00000000
Address : 0x6fe0004c
Bits Reset value Name Description
31 - 0 0x0
attr
Upper 32-bits Attribute Values used when
fetching and returning link list descriptors.


pcie_dma_common_udma_int
DMA Interrupt Register
R/W
0x00000000
Address : 0x6fe000a0
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "0"
ch7_error_int
Channel 7 Error Interrupt Register
14 "0"
ch6_error_int
Channel 6 Error Interrupt Register
13 "0"
ch5_error_int
Channel 5 Error Interrupt Register
12 "0"
ch4_error_int
Channel 4 Error Interrupt Register
11 "0"
ch3_error_int
Channel 3 Error Interrupt Register
10 "0"
ch2_error_int
Channel 2 Error Interrupt Register
9 "0"
ch1_error_int
Channel 1 Error Interrupt Register
8 "0"
ch0_error_int
Channel 0 Error Interrupt Register
7 "0"
ch7_done_int
Channel 7 Done Interrupt Register
6 "0"
ch6_done_int
Channel 6 Done Interrupt Register
5 "0"
ch5_done_int
Channel 5 Done Interrupt Register
4 "0"
ch4_done_int
Channel 4 Done Interrupt Register
3 "0"
ch3_done_int
Channel 3 Done Interrupt Register
2 "0"
ch2_done_int
Channel 2 Done Interrupt Register
1 "0"
ch1_done_int
Channel 1 Done Interrupt Register
0 "0"
ch0_done_int
Channel 0 Done Interrupt Register


pcie_dma_common_udma_int_ena
DMA Interrupt Enable Register
R/W
0x0000ffff
Address : 0x6fe000a4
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "1"
ch7_error_ena
Assert to 1 to enable error interrupts to be generated
14 "1"
ch6_error_ena
Assert to 1 to enable error interrupts to be generated
13 "1"
ch5_error_ena
Assert to 1 to enable error interrupts to be generated
12 "1"
ch4_error_ena
Assert to 1 to enable error interrupts to be generated
11 "1"
ch3_error_ena
Assert to 1 to enable error interrupts to be generated
10 "1"
ch2_error_ena
Assert to 1 to enable error interrupts to be generated
9 "1"
ch1_error_ena
Assert to 1 to enable error interrupts to be generated
8 "1"
ch0_error_ena
Assert to 1 to enable error interrupts to be generated
7 "1"
ch7_done_ena
Assert to 1 to enable done interrupts to be generated
6 "1"
ch6_done_ena
Assert to 1 to enable done interrupts to be generated
5 "1"
ch5_done_ena
Assert to 1 to enable done interrupts to be generated
4 "1"
ch4_done_ena
Assert to 1 to enable done interrupts to be generated
3 "1"
ch3_done_ena
Assert to 1 to enable done interrupts to be generated
2 "1"
ch2_done_ena
Assert to 1 to enable done interrupts to be generated
1 "1"
ch1_done_ena
Assert to 1 to enable done interrupts to be generated
0 "1"
ch0_done_ena
Assert to 1 to enable done interrupts to be generated


pcie_dma_common_udma_int_dis
DMA Interrupt Disable Register
R/W
0x0000ffff
Address : 0x6fe000a8
Bits Reset value Name Description
31 - 16 0
-
 reserved
15 "1"
ch7_error_dis
Assert to 1 to disable error interrupts to be generated
14 "1"
ch6_error_dis
Assert to 1 to disable error interrupts to be generated
13 "1"
ch5_error_dis
Assert to 1 to disable error interrupts to be generated
12 "1"
ch4_error_dis
Assert to 1 to disable error interrupts to be generated
11 "1"
ch3_error_dis
Assert to 1 to disable error interrupts to be generated
10 "1"
ch2_error_dis
Assert to 1 to disable error interrupts to be generated
9 "1"
ch1_error_dis
Assert to 1 to disable error interrupts to be generated
8 "1"
ch0_error_dis
Assert to 1 to disable error interrupts to be generated
7 "1"
ch7_done_dis
Assert to 1 to disable done interrupts to be generated
6 "1"
ch6_done_dis
Assert to 1 to disable done interrupts to be generated
5 "1"
ch5_done_dis
Assert to 1 to disable done interrupts to be generated
4 "1"
ch4_done_dis
Assert to 1 to disable done interrupts to be generated
3 "1"
ch3_done_dis
Assert to 1 to disable done interrupts to be generated
2 "1"
ch2_done_dis
Assert to 1 to disable done interrupts to be generated
1 "1"
ch1_done_dis
Assert to 1 to disable done interrupts to be generated
0 "1"
ch0_done_dis
Assert to 1 to disable done interrupts to be generated


pcie_dma_common_udma_ib_ecc_uncorrectable_errors
DMA Inbound Buffer Uncorrected ECC Errors
R
Address : 0x6fe000ac
Bits Name Description
31 - 16 -
 reserved
15 - 0 total
ECC Error Detection Register


pcie_dma_common_udma_ib_ecc_correctable_errors
DMA Inbound Buffer corrected ECC Errors
R
Address : 0x6fe000b0
Bits Name Description
31 - 16 -
 reserved
15 - 0 total
ECC Error Detection Register


pcie_dma_common_udma_ob_ecc_uncorrectable_errors
DMA Outbound Buffer Uncorrected ECC Errors
R
Address : 0x6fe000b4
Bits Name Description
31 - 16 -
 reserved
15 - 0 total
ECC Error Detection Register


pcie_dma_common_udma_ob_ecc_correctable_errors
DMA Outbound Buffer corrected ECC Errors
R
Address : 0x6fe000b8
Bits Name Description
31 - 16 -
 reserved
15 - 0 total
ECC Error Detection Register


pcie_dma_common_udma_cap_ver
DMA Capability and Version Register
R
Address : 0x6fe000f8
Bits Name Description
31 - 16 -
 reserved
15 - 8 maj_ver
Major Version No
7 - 0 min_ver
Minor Version No


pcie_dma_common_udma_config
DMA Configuration Register
R
Address : 0x6fe000fc
Bits Name Description
31 - 16 -
 reserved
15 ext_tw_gt_32
Ext Attr Width > 32-bits
14 ext_aw_gt_32
Ext Addr Width > 32-bits
13 sys_tw_gt_32
Sys Attr Width > 32-bits
12 sys_aw_gt_32
Sys Addr Width > 32-bits
11 - 8 partition_size
Size of each Partition                        # default 4'd5
7 - 4 num_partitions
Number of DPRAM Partitions                    # default 4'd4
3 - 0 num_channels
Number of uDMA Channels                       # default 4'd4



Base Address Area: secenc_cm0_scs

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0-1 0-4 -  reserved
2 8 R/W cm0_scs_actlr
3 c -  reserved
4 10 R/W cm0_scs_syst_csr
5 14 R/W cm0_scs_syst_rvr
6 18 R/W cm0_scs_syst_cvr
7 1c R cm0_scs_syst_calib
8-3f 20-fc -  reserved
40 100 R/W cm0_scs_nvic_iser
41-5f 104-17c -  reserved
60 180 R/W cm0_scs_nvic_icer
61-7f 184-1fc -  reserved
80 200 R/W cm0_scs_nvic_ispr
81-9f 204-27c -  reserved
a0 280 R/W cm0_scs_nvic_icpr
a1-ff 284-3fc -  reserved
100 400 R/W cm0_scs_nvic_ipr0
101 404 R/W cm0_scs_nvic_ipr1
102 408 R/W cm0_scs_nvic_ipr2
103 40c R/W cm0_scs_nvic_ipr3
104 410 R/W cm0_scs_nvic_ipr4
105 414 R/W cm0_scs_nvic_ipr5
106 418 R/W cm0_scs_nvic_ipr6
107 41c R/W cm0_scs_nvic_ipr7
108-33f 420-cfc -  reserved
340 d00 R cm0_scs_cpuid
341 d04 R/W cm0_scs_icsr
342 d08 R/W cm0_scs_vtor
343 d0c R/W cm0_scs_aircr
344 d10 R/W cm0_scs_scr
345 d14 R/W cm0_scs_ccr
346 d18 -  reserved
347 d1c R/W cm0_scs_shpr2
348 d20 R/W cm0_scs_shpr3
349 d24 R/W cm0_scs_shcsr
34a-34b d28-d2c -  reserved
34c d30 R/W cm0_scs_dfsr
34d-363 d34-d8c -  reserved
364 d90 R cm0_scs_mpu_type
365 d94 R/W cm0_scs_mpu_ctrl
366 d98 R/W cm0_scs_mpu_rnr
367 d9c R/W cm0_scs_mpu_rbar
368 da0 R/W cm0_scs_mpu_rasr
369-37b da4-dec -  reserved
37c df0 R/W cm0_scs_dhcsr
37d df4 W cm0_scs_dcrsr
37e df8 R/W cm0_scs_dcrdr
37f dfc R/W cm0_scs_demcr
380-3f3 e00-fcc -  reserved
3f4 fd0 R cm0_scs_pidr4
3f5-3f7 fd4-fdc -  reserved
3f8 fe0 R cm0_scs_pidr0
3f9 fe4 R cm0_scs_pidr1
3fa fe8 R cm0_scs_pidr2
3fb fec R cm0_scs_pidr3
3fc ff0 R cm0_scs_cidr0
3fd ff4 R cm0_scs_cidr1
3fe ff8 R cm0_scs_cidr2
3ff ffc R cm0_scs_cidr3

cm0_scs_actlr
Auxiliary control register
R/W
0x00000000
Address : 0xe000e008
Bits Reset value Name Description
31 - 0 0
cm0_scs_actlr


cm0_scs_syst_csr
SysTick control and status register
R/W
0x00000000
Address : 0xe000e010
Bits Reset value Name Description
31 - 0 0
cm0_scs_syst_csr


cm0_scs_syst_rvr
SysTick Reload Value register
R/W
0x00000000
Address : 0xe000e014
Bits Reset value Name Description
31 - 0 0
cm0_scs_syst_rvr


cm0_scs_syst_cvr
SysTick current value register
R/W
0x00000000
Address : 0xe000e018
Bits Reset value Name Description
31 - 0 0
cm0_scs_syst_cvr


cm0_scs_syst_calib
SysTick calibration value register
R
Address : 0xe000e01c
Bits Name Description
31 - 0 cm0_scs_syst_calib


cm0_scs_nvic_iser
Interrupt set-enable register
Enables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e100
Bits Reset value Name Description
31 - 0 0x0
setena
For register cm0_scs_nvic_iser[n], enables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, enable interrupt.
Software can enable multiple interrupts in a single write to cm0_scs_nvic_iser[n].


cm0_scs_nvic_icer
Interrupt clear-enable register
Disables, or reads the enable state of a group of interrupts.
R/W
0x00000000
Address : 0xe000e180
Bits Reset value Name Description
31 - 0 0x0
clrena
For register cm0_scs_nvic_icer[n], disables or shows the current enabled state of interrupt (m+(32*n)):
0: On reads, interrupt disabled. On writes, no effect.
1: On reads, interrupt enabled. On writes, disable interrupt.
Software can disable multiple interrupts in a single write to cm0_scs_nvic_icer[n].


cm0_scs_nvic_ispr
Interrupt set-pending register
For a group of interrupts, changes interrupt status to pending, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e200
Bits Reset value Name Description
31 - 0 0x0
setpend
For register cm0_scs_nvic_ispr[n], changes the state of interrupt (m+(32*n)) to pending, or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, change state of interrupt to pending.
Software can set multiple interrupts to pending state in a single write to cm0_scs_nvic_ispr[n].


cm0_scs_nvic_icpr
Interrupt clear-pending register
For a group of interrupts, clears the interrupt pending status, or shows the current pending status.
R/W
0x00000000
Address : 0xe000e280
Bits Reset value Name Description
31 - 0 0x0
clrpend
For register cm0_scs_nvic_ispr[n], clears the pending state of interrupt (m+(32*n)), or shows whether the state of the interrupt is pending:
0: On reads, interrupt is not pending. On writes, no effect.
1: On reads, interrupt is pending. On writes, clears the pending state of interrupt.
Software can clear the pending state of multiple interrupts in a single write to cm0_scs_nvic_icpr[n].


cm0_scs_nvic_ipr0
Interrupt priority register 0
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e400
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr1
Interrupt priority register 1
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e404
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr2
Interrupt priority register 2
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e408
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr3
Interrupt priority register 3
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e40c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr4
Interrupt priority register 4
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e410
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr5
Interrupt priority register 5
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e414
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr6
Interrupt priority register 6
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e418
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_nvic_ipr7
Interrupt priority register 7
Sets or reads interrupt priorities.
R/W
0x00000000
Address : 0xe000e41c
Bits Reset value Name Description
31 - 24 "00000000"
pri_n3
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+3.
23 - 16 "00000000"
pri_n2
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+2.
15 - 8 "00000000"
pri_n1
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n+1.
7 - 0 "00000000"
pri_n0
For register cm0_scs_nvic_ipr[n], priority of interrupt number 4n.


cm0_scs_cpuid
CPUID base register
R
Address : 0xe000ed00
Bits Name Description
31 - 0 cm0_scs_cpuid


cm0_scs_icsr
Interrupt control and state register
R/W
0x00000000
Address : 0xe000ed04
Bits Reset value Name Description
31 - 0 0
cm0_scs_icsr


cm0_scs_vtor
Vector table offset register
Holds the vector table address.
R/W
0x00000000
Address : 0xe000ed08
Bits Reset value Name Description
31 - 7 0x0
tbloff
Bits[31:7] of the vector table address.
6 - 0 0
-
 reserved


cm0_scs_aircr
Application interrupt and reset control reister
Sets or returns interrupt control data.
R/W
0xfa050000
Address : 0xe000ed0c
Bits Reset value Name Description
31 - 16 0xfa05
vectkey
Vector Key.
Register writes must write 0x05FA to this field, otherwise the write is ignored.
On reads, returns 0xFA05.
15 "0"
endianness
Indicates the memory system endianness: 0 - Little endian, 1 - Big endian.
This bit is static or configured by a hardware input on reset.
This bit is read only.
14 - 3 0
-
 reserved
2 "0"
sysresetreq
System Reset Request.
Writing 1 to this bit asserts a signal to the external system to request a Local reset. A Local or Power-on reset clears this bit to 0.
1 "0"
vectclractive
Writing 1 to this bit clears all active state information for fixed and configurable exceptions. This includes clearing the IPSR to zero.
The effect of writing a 1 to this bit if the processor is not halted in Debug state is UNPREDICTABLE.
This bit is write only.
0 0
-
 reserved


cm0_scs_scr
System control Register
R/W
0x00000000
Address : 0xe000ed10
Bits Reset value Name Description
31 - 0 0
cm0_scs_scr


cm0_scs_ccr
Configuration and control Register
R/W
0x00000000
Address : 0xe000ed14
Bits Reset value Name Description
31 - 0 0
cm0_scs_ccr


cm0_scs_shpr2
System Handler Priority Register 2
R/W
0x00000000
Address : 0xe000ed1c
Bits Reset value Name Description
31 - 0 0
cm0_scs_shpr2


cm0_scs_shpr3
System Handler Priority Register 3
R/W
0x00000000
Address : 0xe000ed20
Bits Reset value Name Description
31 - 0 0
cm0_scs_shpr3


cm0_scs_shcsr
System Handler Control and State Register
R/W
0x00000000
Address : 0xe000ed24
Bits Reset value Name Description
31 - 0 0
cm0_scs_shcsr


cm0_scs_dfsr
Debug fault status Register
Shows which debug event occurred.
Note: Writing 1 to a register bit clears the bit to 0.
R/W
0x00000000
Address : 0xe000ed30
Bits Reset value Name Description
31 - 5 0
-
 reserved
4 "0"
external
Indicates a debug event generated because of the assertion of an external debug request.
3 "0"
vcatch
Indicates triggering of a Vector catch.
2 "0"
dwttrap
Indicates a debug event generated by the DWT.
1 "0"
bkpt
Indicates a debug event generated by BKPT instruction execution or a breakpoint match in FPB.
0 "0"
halted
Indicates a debug event generated by either:
- A C_HALT or C_STEP request, triggered by a write to the DHCSR.
- A step request triggered by setting DEMCR.MON_STEP to 1.


cm0_scs_mpu_type
MPU Type Register
R
Address : 0xe000ed90
Bits Name Description
31 - 0 cm0_scs_mpu_type


cm0_scs_mpu_ctrl
MPU Control Register
R/W
0x00000000
Address : 0xe000ed94
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
privdefena

1 "0"
hfnmiena

0 "0"
enable



cm0_scs_mpu_rnr
MPU Region Number Register
R/W
0x00000000
Address : 0xe000ed98
Bits Reset value Name Description
31 - 8 0
-
 reserved
7 - 0 "00000000"
region



cm0_scs_mpu_rbar
MPU Region Base Address Register
R/W
0x00000000
Address : 0xe000ed9c
Bits Reset value Name Description
31 - 5 0x0
addr

4 "0"
valid

3 - 0 "0000"
region



cm0_scs_mpu_rasr
MPU Region Attribute and Size Register
R/W
0x00000000
Address : 0xe000eda0
Bits Reset value Name Description
31 - 29 0
-
 reserved
28 "0"
xn

27 0
-
 reserved
26 - 24 "000"
ap

23 - 22 0
-
 reserved
21 - 19 "000"
tex

18 "0"
s

17 "0"
c

16 "0"
b

15 - 6 0
-
 reserved
5 - 1 "00000"
size

0 "0"
enable



cm0_scs_dhcsr
Debug halting control and status register
Controls halting debug.
Note: On writes bits 31-16 (dbgkey) must be set to 0xA05F.
R/W
0x00000000
Address : 0xe000edf0
Bits Reset value Name Description
31 - 26 0
-
 reserved
25 "0"
s_reset_st
Indicates whether the processor has been reset since the last read of DHCSR.
This is a sticky bit, that clears to 0 on a read of DHCSR. This bit is read-only.
24 "0"
s_retire_st
Set to 1 every time the processor retires one or more instructions.
This is a sticky bit, that clears to 0 on a read of DHCSR.
The architecture does not define precisely when this bit is set to 1. It requires only that this happen periodically in Non-debug state to indicate that software execution is progressing.
This bit is UNKNOWN after a Power-on or Local reset, but then is set to 1 as soon as the processor executes and retires an instruction.
This bit is read-only.
23 - 20 0
-
 reserved
19 "0"
s_lockup
Indicates whether the processor is locked up because of an unrecoverable exception.
This bit can only be read as 1 by a remote debugger, using the DAP. The value of 1 indicates that the processor is running but locked up.
The bit clears to 0 when the processor enters Debug state.
This bit is read-only.
18 "0"
s_sleep
Indicates whether the processor is sleeping.
The debugger must set the C_HALT bit to 1 to gain control, or wait for an interrupt or other wakeup event to wakeup the system.
This bit is read-only.
17 "0"
s_halt
Indicates whether the processor is in Debug state.
This bit is read-only.
16 "0"
s_regrdy
A handshake flag for transfers through the DCRDR:
- Writing to DCRSR clears the bit to 0.
- Completion of the DCRDR transfer then sets the bit to 1.
For more information about DCRDR transfers see Debug Core Register Data Register, DCRDR.
This bit is valid only when the processor is in Debug state, otherwise the bit is UNKNOWN.
This bit is read-only.
15 - 4 0
-
 reserved
3 "0"
c_maskints
When debug is enabled, the debugger can write to this bit to mask PendSV, SysTick and external configurable interrupts:
- 0: Do not mask.
- 1: Mask PendSV, SysTick and external configurable interrupts.
The effect of any attempt to change the value of this bit is UNPREDICTABLE unless both:
- Before the write to DHCSR, the value of the C_HALT bit is 1.
- The write to the DHCSR that changes the C_MASKINTS bit also writes 1 to the C_HALT bit.
This means that a single write to DHCSR cannot set the C_HALT to 0 and change the value of the C_MASKINTS bit.
The bit does not affect NMI. When DHCSR.C_DEBUGEN is set to 0, the value of this bit is UNKNOWN.
This bit is UNKNOWN after a Power-on reset.
2 "0"
c_step
Processor step bit. The effects of writes to this bit are:
- 0: No effect.
- 1: Single step enabled.
This bit is UNKNOWN after a Power-on reset.
1 "0"
c_halt
Processor halt bit. The effects of writes to this bit are:
- 0: Causes the processor to leave Debug state, if in Debug state.
- 1: Halt the processor.
This bit is UNKNOWN after a Power-on reset, and is 0 after a Local reset.
0 "0"
c_debugen
Halting debug enable bit.
If a debugger writes to DHCSR to change the value of this bit from 0 to 1, it must also write 0 to the C_MASKINTS bit, otherwise behavior is UNPREDICTABLE.
This bit can only be written by the DAP, it ignores writes from software.


cm0_scs_dcrsr
Debug core register selector register
With the DCRDR, the DCRSR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. A write to DCRSR specifies the register to transfer, whether the transfer is a read or a write, and starts the transfer.
W
0x00000000
Address : 0xe000edf4
Bits Reset value Name Description
31 - 17 0
-
 reserved
16 "0"
regwnr
Specifies the access type for the transfer:
0 : Read.
1 : Write.
15 - 7 0
-
 reserved
6 - 0 "0000000"
regsel
Specifies the ARM core register, special-purpose register, or Floating-point extension register, to transfer:
 0 - 12  ARM core registers R0-R12.
     13  The current SP. See also values 17 (MSP) and 18 (PSP).
     14  LR.
     15  DebugReturnAddress.
     16  xPSR.
     17  Main stack pointer, MSP.
     18  Process stack pointer, PSP.
     20  Bits[31:24]: CONTROL, Bits[7:0]: PRIMASK. In each field, the valid bits are packed with leading zeros. For example, DCRDR[31:26] is 0.

All other values are Reserved.


cm0_scs_dcrdr
Debug core register data register
With the DCRSR, the DCRDR provides debug access to the ARM core registers, special-purpose registers, and Floating-point extension registers. The DCRDR is the data register for these accesses.
Used on its own, the DCRDR provides a message passing resource between an external debugger and a debug agent running on the processor.
Note: The architecture does not define any handshaking mechanism for this use of DCRDR.
R/W
0x00000000
Address : 0xe000edf8
Bits Reset value Name Description
31 - 0 0x0
dbgtmp
Data temporary cache, for reading and writing the ARM core registers, special-purpose registers, and Floating-point extension registers.


cm0_scs_demcr
Debug exception and monitor control register
Manages vector catch behavior and DebugMonitor handling when debugging.
R/W
0x00000000
Address : 0xe000edfc
Bits Reset value Name Description
31 - 25 0
-
 reserved
24 "0"
dwtena
 Global enable for all features configured and controlled by the DWT unit:
- 0: DWT disabled.
- 1: DWT enabled.
When DWTENA is set to 0 DWT registers return UNKNOWN values on reads.
In addition, it is IMPLEMENTATION DEFINED whether the processor ignores writes to the DWT while DWTENA is 0.
23 - 11 0
-
 reserved
10 "0"
vc_harderr
Enable halting debug trap on a HardFault exception.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.
9 - 1 0
-
 reserved
0 "0"
vc_corereset
Enable Reset Vector Catch. This causes a Local reset to halt a running system.
If DHCSR.C_DEBUGEN is set to 0, the processor ignores the value of this bit.


cm0_scs_pidr4
Peripheral ID Register 4
R
Address : 0xe000efd0
Bits Name Description
31 - 0 cm0_scs_pidr4


cm0_scs_pidr0
Peripheral ID Register 0
R
Address : 0xe000efe0
Bits Name Description
31 - 0 cm0_scs_pidr0


cm0_scs_pidr1
Peripheral ID Register 1
R
Address : 0xe000efe4
Bits Name Description
31 - 0 cm0_scs_pidr1


cm0_scs_pidr2
Peripheral ID Register 2
R
Address : 0xe000efe8
Bits Name Description
31 - 0 cm0_scs_pidr2


cm0_scs_pidr3
Peripheral ID Register 3
R
Address : 0xe000efec
Bits Name Description
31 - 0 cm0_scs_pidr3


cm0_scs_cidr0
Component ID Register 0
R
Address : 0xe000eff0
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_0
Preamble byte 0.


cm0_scs_cidr1
Component ID Register 1
R
Address : 0xe000eff4
Bits Name Description
31 - 8 -
 reserved
7 - 4 class
Component class.
3 - 0 prmbl_1
Preamble bits[11:8].


cm0_scs_cidr2
Component ID Register 2
R
Address : 0xe000eff8
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_2
Preamble byte 2.


cm0_scs_cidr3
Component ID Register 3
R
Address : 0xe000effc
Bits Name Description
31 - 8 -
 reserved
7 - 0 prmbl_3
Preamble byte 3.



Base Address Area:

Address mapping
DWord Offset (hex) Byte Offset (hex) Mode Register
0 0 R/W gen_ram_ctrl_mbist_power0
1-1ff 4-7fc -  reserved
200 800 R/W gen_ram_ctrl_ecc0
201-27f 804-9fc -  reserved
280 a00 R gen_ram_ctrl_ecc_status_corr0
281-2ff a04-bfc -  reserved
300 c00 R gen_ram_ctrl_ecc_status_noncorr0
301-37f c04-dfc -  reserved
380 e00 R/W gen_ram_ctrl_irq_raw_reg0
381-38f e04-e3c -  reserved
390 e40 R/W gen_ram_ctrl_irq_masked_reg0
391-39f e44-e7c -  reserved
3a0 e80 R/W gen_ram_ctrl_irq_mask_set_reg0
3a1-3af e84-ebc -  reserved
3b0 ec0 R/W gen_ram_ctrl_irq_mask_rst_reg0
3b1-3be ec4-ef8 -  reserved
3bf efc R/W gen_ram_ctrl_power_sequencer_ctrl_reg
3c0-3ff f00-ffc -  reserved

gen_ram_ctrl_mbist_power0
MBIST/power control and status register
For memory dut_1.gen_ram_hsoc_i (32x32 bits excluding any BIRA redundancy, BIST type BIRA)
This logical RAM is always on (HDL parameter).
R/W
0x000000a0
Address : 0x00000000
Bits Reset value Name Description
31 - 13 0
-
 reserved
12 -
ecc_support_ro
Memory ECC feature
Reflects whether the memory supports ECC error detection and/or correction.
{       |
 Value   feature
 0       ECC is not supported
 1       ECC is supported
11 -
sleep_support_ro
Memory sleep mode feature
Reflects whether the memory supports sleep mode and shutdown mode.
Value feature
0 sleep mode and shutdown mode are not supported
1 sleep mode and shutdown mode are supported
10 -
mbist_init_support_ro
Memory implementation MBIST/INIT register
Reflects whether the memory has been implemented with support for MBIST and memory initialization.
Value implementation
0 MBIST and memory initialization are not supported
1 MBIST and memory initialization are supported
9 "0"
enable_mode_abort
Abort control register
If 1, any memory access on a memory in disable_mem mode will trigger an abort.
8 "0"
enable_ecc_abort
Abort control register
If 1, any non correctable ECC error will trigger an abort.
7 "1"
shutdown
Shutdown mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the shutdown mode register has no effect.
6 "0"
sleep
Sleep mode register
This logical RAM is always on (HDL parameter).
In case of logical memories composed of multiple physical memories, this applies all physical memories.
Therefore the sleep mode register has no effect.
5 "1"
disable_mem
disable_mem register
If 1, the memory chip select is forced off, and the memory clock is gated, which is required before activating sleep mode or shutdown mode.
In case of logical memories composed of multiple physical memories, this bit controls all physical memories.
4 - 2 -
bist_status_ro
MBIST status register (read only)
This bit field reflects the memory BIST status.
Value status
0 not started
1 running
4 finished, OK
6 finished, fail, might be BIRA repairable (depending on redundancy resources left after any prior BIRA)
7 finished, fail, non repairable

In case of logical memories composed of multiple physical memories, the status value is
7 (fail) if any physical memory's status has that value, else
6 (fail) if any physical memory's status has that value, else
1 (running) if any physical memory's status has that value, else
4 (OK) if any physical memory's status has that value, else
0 (not started) if any physical memory's status has that value, else
2 (illegal).
1 - 0 "00"
bist_mode
MBIST mode register
This bit field controls in-system memory BIST running on the individual memory's system clock.
Value mode
0 disabled
1 init RAM with 0
2 run MBIST

Note: this feature is only available for memories supporting MBIST and memory initialization, see register bit mbist_init_support_ro
In case of logical memories composed of multiple physical memories, the mode controls all physical memories.


gen_ram_ctrl_ecc0
ECC control and status register
For memory dut_1.gen_ram_hsoc_i (32x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
R/W
0x00000000
Address : 0x00000800
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 -
ecc_corr_support_ro
Memory ECC correction feature
Reflects whether the memory supports ECC error correction.
{       |
 Value   feature
 0       ECC errors are reported, not corrected
 1       ECC single bit errors are corrected, double bit errors are reported
1 "0"
ecc_freeze_checkbits
ECC/parity debug register
If 1, ECC/parity checkbits are not written to the memory but are left unchanged.
This allows generating any combination of data and checkbits by
(1) writing data creating the desired checkbits in normal mode
(2) writing the desired data word to the same address after setting this debug bit.
0 "0"
ecc_enable
ECC/parity enable register
If 1, ECC mode is enabled if the memory was built with ECC.
If 1, parity mode is enabled if the memory was built with parity.
Memories can support either ECC or parity, or none.


gen_ram_ctrl_ecc_status_corr0
ECC status register
For memory dut_1.gen_ram_hsoc_i (32x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x00000a00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for correctable errors
When reading the register, the counter is set to 0.
Subsequent correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for correctable errors
This bit field reflects the first address at which a correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_ecc_status_noncorr0
ECC status register
For memory dut_1.gen_ram_hsoc_i (32x32 bits excluding any parity bits)
The memory includes ECC/parity per 8 data bits.
In RAMs with standard ECC (ecc_type=1), single bit errors are corrected, double bit errors are not reliably detected
In RAMs with enhanced ECC (ecc_type=2), single bit errors are corrected, double bit errors are detected (non correctable)
In RAMs with parity, single bit errors are detected (non correctable), double bit errors are not detected.
R
Address : 0x00000c00
Bits Name Description
31 - 24 ecc_err_counter
ECC/parity error counter register for non correctable errors
When reading the register, the counter is set to 0.
Subsequent non correctable ECC/parity errors will increment the counter value.
The counter saturates at its maximum value.
23 - 0 ecc_err_address
ECC/parity error address register for non correctable errors
This bit field reflects the first address at which a non correctable ECC/parity error ocurred.
When reading the register, this field is cleared, and the the address of the next ECC/parity error will be stored.
Subsequent non correctable ECC/parity errors will not change this bit field unless the register has been read in between.
The ecc_err_counter field is used for differentiation between 'no error' and 'error at address 0'.


gen_ram_ctrl_irq_raw_reg0
Raw IRQs:
Read access shows status of unmasked IRQs.
Write access with '1' resets the appropriate IRQ.
Write access with '0' does not influence this bit.
R/W
0x00000000
Address : 0x00000e00
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_irq_masked_reg0
Masked IRQs:
Read access shows status of masked IRQs (as connected to IRQ controller).
Write access is for debug only: '1' sets irq_raw bit (reset by writing to adr_gen_ram_ctrl_irq_raw_reg0).
R/W
0x00000000
Address : 0x00000e40
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_irq_mask_set_reg0
IRQ enable mask:
The IRQ mask register enables interrupt requests for corresponding interrupt sources. As its bits might be changed by different software tasks, the IRQ mask register is not writable directly, but by irq_mask_set and irq_mask_rst addresses:
Write access with '1' sets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows actual interrupt mask.
Note: Before activating interrupt mask, delete old pending interrupts by writing to adr_gen_ram_ctrl_irq_raw_reg0
R/W
0x00000000
Address : 0x00000e80
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_irq_mask_rst_reg0
IRQ disable mask:
The irq_mask_rst address is used to reset bits of the IRQ mask register:
Write access with '1' resets interrupt mask bit.
Write access with '0' does not influence this bit.
Read access shows the number of highest prior active IRQ (= lowest IRQ number) or 3 when no IRQ is set:
  0 : irq_reg0-mem_0_err_ecc_non_correctable
  1 : irq_reg0-mem_0_err_ecc_correctable
  2 : irq_reg0-mem_0_mbist_or_init_finished
  3 : no active IRQ
R/W
0x00000000
Address : 0x00000ec0
Bits Reset value Name Description
31 - 3 0
-
 reserved
2 "0"
mem_0_mbist_or_init_finished
Event: gen_ram_ctrl status IRQ, BIST controller has finished MBIST or RAM initialization
1 "0"
mem_0_err_ecc_correctable
Event: gen_ram_ctrl error IRQ, correctable ECC error
0 "0"
mem_0_err_ecc_non_correctable
Event: gen_ram_ctrl error IRQ, non correctable ECC error


gen_ram_ctrl_power_sequencer_ctrl_reg
Power sequencer control register
R/W
0x0000000a
Address : 0x00000efc
Bits Reset value Name Description
31 - 6 0
-
 reserved
5 - 0 "001010"
power_sequencer_num_cycles
Power sequencer: number of clock cycles per step when incrementally enabling physical memories